projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/radeon/kms/atom: add support for setting DP panel mode
[deliverable/linux.git] / drivers / gpu / drm / radeon / atombios_dp.c
CommitLineData
746c1aa4
DA		 1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26#include "drmP.h"
27#include "radeon_drm.h"
28#include "radeon.h"
29
30#include "atom.h"
31#include "atom-bits.h"
32#include "drm_dp_helper.h"
33
f92a8b67 34/* move these to drm_dp_helper.c/h */
5801ead6
AD		 35#define DP_LINK_CONFIGURATION_SIZE 9
36#define DP_LINK_STATUS_SIZE 6
37#define DP_DPCD_SIZE 8
38
39static char *voltage_names[] = {
40 "0.4V", "0.6V", "0.8V", "1.2V"
41};
42static char *pre_emph_names[] = {
43 "0dB", "3.5dB", "6dB", "9.5dB"
44};
f92a8b67
AD		 45
46static const int dp_clocks[] = {
53c1e09f
AD		 47 54000, /* 1 lane, 1.62 Ghz */
48 90000, /* 1 lane, 2.70 Ghz */
49 108000, /* 2 lane, 1.62 Ghz */
50 180000, /* 2 lane, 2.70 Ghz */
51 216000, /* 4 lane, 1.62 Ghz */
52 360000, /* 4 lane, 2.70 Ghz */
f92a8b67
AD		 53};
54
55static const int num_dp_clocks = sizeof(dp_clocks) / sizeof(int);
56
5801ead6
AD		 57/* common helper functions */
58static int dp_lanes_for_mode_clock(u8 dpcd[DP_DPCD_SIZE], int mode_clock)
f92a8b67
AD		 59{
60 int i;
5801ead6
AD		 61 u8 max_link_bw;
62 u8 max_lane_count;
63
64 if (!dpcd)
65 return 0;
66
67 max_link_bw = dpcd[DP_MAX_LINK_RATE];
68 max_lane_count = dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK;
f92a8b67
AD		 69
70 switch (max_link_bw) {
71 case DP_LINK_BW_1_62:
72 default:
73 for (i = 0; i < num_dp_clocks; i++) {
74 if (i % 2)
75 continue;
5801ead6
AD		 76 switch (max_lane_count) {
77 case 1:
78 if (i > 1)
79 return 0;
80 break;
81 case 2:
82 if (i > 3)
83 return 0;
84 break;
85 case 4:
86 default:
87 break;
88 }
f92a8b67
AD		 89 if (dp_clocks[i] > mode_clock) {
90 if (i < 2)
91 return 1;
92 else if (i < 4)
93 return 2;
94 else
95 return 4;
96 }
97 }
98 break;
99 case DP_LINK_BW_2_7:
100 for (i = 0; i < num_dp_clocks; i++) {
5801ead6
AD		 101 switch (max_lane_count) {
102 case 1:
103 if (i > 1)
104 return 0;
105 break;
106 case 2:
107 if (i > 3)
108 return 0;
109 break;
110 case 4:
111 default:
112 break;
113 }
f92a8b67
AD		 114 if (dp_clocks[i] > mode_clock) {
115 if (i < 2)
116 return 1;
117 else if (i < 4)
118 return 2;
119 else
120 return 4;
121 }
122 }
123 break;
124 }
125
126 return 0;
127}
128
5801ead6 129static int dp_link_clock_for_mode_clock(u8 dpcd[DP_DPCD_SIZE], int mode_clock)
f92a8b67
AD		 130{
131 int i;
5801ead6
AD		 132 u8 max_link_bw;
133 u8 max_lane_count;
134
135 if (!dpcd)
136 return 0;
137
138 max_link_bw = dpcd[DP_MAX_LINK_RATE];
139 max_lane_count = dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK;
f92a8b67
AD		 140
141 switch (max_link_bw) {
142 case DP_LINK_BW_1_62:
143 default:
5801ead6
AD		 144 for (i = 0; i < num_dp_clocks; i++) {
145 if (i % 2)
146 continue;
147 switch (max_lane_count) {
148 case 1:
149 if (i > 1)
150 return 0;
151 break;
152 case 2:
153 if (i > 3)
154 return 0;
155 break;
156 case 4:
157 default:
158 break;
159 }
160 if (dp_clocks[i] > mode_clock)
161 return 162000;
162 }
f92a8b67
AD		 163 break;
164 case DP_LINK_BW_2_7:
165 for (i = 0; i < num_dp_clocks; i++) {
5801ead6
AD		 166 switch (max_lane_count) {
167 case 1:
168 if (i > 1)
169 return 0;
170 break;
171 case 2:
172 if (i > 3)
173 return 0;
174 break;
175 case 4:
176 default:
177 break;
178 }
f92a8b67
AD		 179 if (dp_clocks[i] > mode_clock)
180 return (i % 2) ? 270000 : 162000;
181 }
182 }
183
184 return 0;
185}
186
5801ead6
AD		 187int dp_mode_valid(u8 dpcd[DP_DPCD_SIZE], int mode_clock)
188{
189 int lanes = dp_lanes_for_mode_clock(dpcd, mode_clock);
6bba2e11 190 int dp_clock = dp_link_clock_for_mode_clock(dpcd, mode_clock);
5801ead6 191
6bba2e11 192 if ((lanes == 0) || (dp_clock == 0))
5801ead6
AD		 193 return MODE_CLOCK_HIGH;
194
195 return MODE_OK;
196}
197
198static u8 dp_link_status(u8 link_status[DP_LINK_STATUS_SIZE], int r)
199{
200 return link_status[r - DP_LANE0_1_STATUS];
201}
202
203static u8 dp_get_lane_status(u8 link_status[DP_LINK_STATUS_SIZE],
204 int lane)
205{
206 int i = DP_LANE0_1_STATUS + (lane >> 1);
207 int s = (lane & 1) * 4;
208 u8 l = dp_link_status(link_status, i);
209 return (l >> s) & 0xf;
210}
211
212static bool dp_clock_recovery_ok(u8 link_status[DP_LINK_STATUS_SIZE],
213 int lane_count)
214{
215 int lane;
216 u8 lane_status;
217
218 for (lane = 0; lane < lane_count; lane++) {
219 lane_status = dp_get_lane_status(link_status, lane);
220 if ((lane_status & DP_LANE_CR_DONE) == 0)
221 return false;
222 }
223 return true;
224}
225
226static bool dp_channel_eq_ok(u8 link_status[DP_LINK_STATUS_SIZE],
227 int lane_count)
228{
229 u8 lane_align;
230 u8 lane_status;
231 int lane;
232
233 lane_align = dp_link_status(link_status,
234 DP_LANE_ALIGN_STATUS_UPDATED);
235 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
236 return false;
237 for (lane = 0; lane < lane_count; lane++) {
238 lane_status = dp_get_lane_status(link_status, lane);
239 if ((lane_status & DP_CHANNEL_EQ_BITS) != DP_CHANNEL_EQ_BITS)
240 return false;
241 }
242 return true;
243}
244
245static u8 dp_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE],
246 int lane)
247
248{
249 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
250 int s = ((lane & 1) ?
251 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
252 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
253 u8 l = dp_link_status(link_status, i);
254
255 return ((l >> s) & 0x3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
256}
257
258static u8 dp_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE],
259 int lane)
260{
261 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
262 int s = ((lane & 1) ?
263 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
264 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
265 u8 l = dp_link_status(link_status, i);
266
267 return ((l >> s) & 0x3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
268}
269
270/* XXX fix me -- chip specific */
271#define DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_1200
272static u8 dp_pre_emphasis_max(u8 voltage_swing)
273{
274 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
275 case DP_TRAIN_VOLTAGE_SWING_400:
276 return DP_TRAIN_PRE_EMPHASIS_6;
277 case DP_TRAIN_VOLTAGE_SWING_600:
278 return DP_TRAIN_PRE_EMPHASIS_6;
279 case DP_TRAIN_VOLTAGE_SWING_800:
280 return DP_TRAIN_PRE_EMPHASIS_3_5;
281 case DP_TRAIN_VOLTAGE_SWING_1200:
282 default:
283 return DP_TRAIN_PRE_EMPHASIS_0;
284 }
285}
286
287static void dp_get_adjust_train(u8 link_status[DP_LINK_STATUS_SIZE],
288 int lane_count,
289 u8 train_set[4])
290{
291 u8 v = 0;
292 u8 p = 0;
293 int lane;
294
295 for (lane = 0; lane < lane_count; lane++) {
296 u8 this_v = dp_get_adjust_request_voltage(link_status, lane);
297 u8 this_p = dp_get_adjust_request_pre_emphasis(link_status, lane);
298
d9fdaafb 299 DRM_DEBUG_KMS("requested signal parameters: lane %d voltage %s pre_emph %s\n",
53c1e09f
AD		 300 lane,
301 voltage_names[this_v >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
302 pre_emph_names[this_p >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
5801ead6
AD		 303
304 if (this_v > v)
305 v = this_v;
306 if (this_p > p)
307 p = this_p;
308 }
309
310 if (v >= DP_VOLTAGE_MAX)
311 v = DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED;
312
313 if (p >= dp_pre_emphasis_max(v))
314 p = dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
315
d9fdaafb 316 DRM_DEBUG_KMS("using signal parameters: voltage %s pre_emph %s\n",
53c1e09f
AD		 317 voltage_names[(v & DP_TRAIN_VOLTAGE_SWING_MASK) >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
318 pre_emph_names[(p & DP_TRAIN_PRE_EMPHASIS_MASK) >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
5801ead6
AD		 319
320 for (lane = 0; lane < 4; lane++)
321 train_set[lane] = v | p;
322}
323
bcc1c2a1
AD		 324union aux_channel_transaction {
325 PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION v1;
326 PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 v2;
327};
5801ead6
AD		 328
329/* radeon aux chan functions */
834b2904
AD		 330static int radeon_process_aux_ch(struct radeon_i2c_chan *chan,
331 u8 *send, int send_bytes,
332 u8 *recv, int recv_size,
333 u8 delay, u8 *ack)
746c1aa4
DA		 334{
335 struct drm_device *dev = chan->dev;
336 struct radeon_device *rdev = dev->dev_private;
bcc1c2a1 337 union aux_channel_transaction args;
746c1aa4
DA		 338 int index = GetIndexIntoMasterTable(COMMAND, ProcessAuxChannelTransaction);
339 unsigned char *base;
834b2904 340 int recv_bytes;
1a66c95a 341
746c1aa4 342 memset(&args, 0, sizeof(args));
1a66c95a 343
746c1aa4
DA		 344 base = (unsigned char *)rdev->mode_info.atom_context->scratch;
345
834b2904 346 memcpy(base, send, send_bytes);
746c1aa4 347
bcc1c2a1
AD		 348 args.v1.lpAuxRequest = 0;
349 args.v1.lpDataOut = 16;
350 args.v1.ucDataOutLen = 0;
351 args.v1.ucChannelID = chan->rec.i2c_id;
352 args.v1.ucDelay = delay / 10;
353 if (ASIC_IS_DCE4(rdev))
8e36ed00 354 args.v2.ucHPD_ID = chan->rec.hpd;
746c1aa4
DA		 355
356 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
357
834b2904
AD		 358 *ack = args.v1.ucReplyStatus;
359
360 /* timeout */
361 if (args.v1.ucReplyStatus == 1) {
362 DRM_DEBUG_KMS("dp_aux_ch timeout\n");
363 return -ETIMEDOUT;
746c1aa4
DA		 364 }
365
834b2904
AD		 366 /* flags not zero */
367 if (args.v1.ucReplyStatus == 2) {
368 DRM_DEBUG_KMS("dp_aux_ch flags not zero\n");
369 return -EBUSY;
746c1aa4 370 }
834b2904
AD		 371
372 /* error */
373 if (args.v1.ucReplyStatus == 3) {
374 DRM_DEBUG_KMS("dp_aux_ch error\n");
375 return -EIO;
376 }
377
378 recv_bytes = args.v1.ucDataOutLen;
379 if (recv_bytes > recv_size)
380 recv_bytes = recv_size;
381
382 if (recv && recv_size)
383 memcpy(recv, base + 16, recv_bytes);
384
385 return recv_bytes;
746c1aa4
DA		 386}
387
834b2904
AD		 388static int radeon_dp_aux_native_write(struct radeon_connector *radeon_connector,
389 u16 address, u8 *send, u8 send_bytes, u8 delay)
746c1aa4 390{
5801ead6 391 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
834b2904 392 int ret;
746c1aa4 393 u8 msg[20];
834b2904
AD		 394 int msg_bytes = send_bytes + 4;
395 u8 ack;
396
397 if (send_bytes > 16)
398 return -1;
746c1aa4 399
746c1aa4
DA		 400 msg[0] = address;
401 msg[1] = address >> 8;
402 msg[2] = AUX_NATIVE_WRITE << 4;
834b2904
AD		 403 msg[3] = (msg_bytes << 4) | (send_bytes - 1);
404 memcpy(&msg[4], send, send_bytes);
746c1aa4 405
834b2904
AD		 406 while (1) {
407 ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus,
408 msg, msg_bytes, NULL, 0, delay, &ack);
409 if (ret < 0)
410 return ret;
411 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
412 break;
413 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
414 udelay(400);
415 else
416 return -EIO;
417 }
746c1aa4 418
834b2904 419 return send_bytes;
746c1aa4
DA		 420}
421
834b2904
AD		 422static int radeon_dp_aux_native_read(struct radeon_connector *radeon_connector,
423 u16 address, u8 *recv, int recv_bytes, u8 delay)
746c1aa4 424{
5801ead6 425 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
834b2904
AD		 426 u8 msg[4];
427 int msg_bytes = 4;
428 u8 ack;
429 int ret;
430
746c1aa4
DA		 431 msg[0] = address;
432 msg[1] = address >> 8;
433 msg[2] = AUX_NATIVE_READ << 4;
834b2904
AD		 434 msg[3] = (msg_bytes << 4) | (recv_bytes - 1);
435
436 while (1) {
437 ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus,
438 msg, msg_bytes, recv, recv_bytes, delay, &ack);
439 if (ret == 0)
440 return -EPROTO;
441 if (ret < 0)
442 return ret;
443 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
444 return ret;
445 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
446 udelay(400);
447 else
448 return -EIO;
449 }
746c1aa4
DA		 450}
451
5801ead6 452/* radeon dp functions */
834b2904
AD		 453static u8 radeon_dp_encoder_service(struct radeon_device *rdev,
454 int action, int dp_clock,
5801ead6
AD		 455 uint8_t ucconfig, uint8_t lane_num)
456{
457 DP_ENCODER_SERVICE_PARAMETERS args;
458 int index = GetIndexIntoMasterTable(COMMAND, DPEncoderService);
459
460 memset(&args, 0, sizeof(args));
461 args.ucLinkClock = dp_clock / 10;
462 args.ucConfig = ucconfig;
463 args.ucAction = action;
464 args.ucLaneNum = lane_num;
465 args.ucStatus = 0;
466
467 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
468 return args.ucStatus;
469}
470
471u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector)
472{
473 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
474 struct drm_device *dev = radeon_connector->base.dev;
475 struct radeon_device *rdev = dev->dev_private;
476
477 return radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_GET_SINK_TYPE, 0,
478 dig_connector->dp_i2c_bus->rec.i2c_id, 0);
479}
480
9fa05c98 481bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector)
746c1aa4 482{
5801ead6 483 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
746c1aa4
DA		 484 u8 msg[25];
485 int ret;
486
834b2904
AD		 487 ret = radeon_dp_aux_native_read(radeon_connector, DP_DPCD_REV, msg, 8, 0);
488 if (ret > 0) {
5801ead6 489 memcpy(dig_connector->dpcd, msg, 8);
1a66c95a 490 {
746c1aa4 491 int i;
d9fdaafb 492 DRM_DEBUG_KMS("DPCD: ");
746c1aa4 493 for (i = 0; i < 8; i++)
d9fdaafb
DA		 494 DRM_DEBUG_KMS("%02x ", msg[i]);
495 DRM_DEBUG_KMS("\n");
746c1aa4 496 }
9fa05c98 497 return true;
746c1aa4 498 }
5801ead6 499 dig_connector->dpcd[0] = 0;
9fa05c98 500 return false;
746c1aa4
DA		 501}
502
5801ead6
AD		 503void radeon_dp_set_link_config(struct drm_connector *connector,
504 struct drm_display_mode *mode)
505{
506 struct radeon_connector *radeon_connector;
507 struct radeon_connector_atom_dig *dig_connector;
508
97b94ccb 509 if ((connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) &&
196c58d2 510 (connector->connector_type != DRM_MODE_CONNECTOR_eDP))
5801ead6
AD		 511 return;
512
513 radeon_connector = to_radeon_connector(connector);
514 if (!radeon_connector->con_priv)
515 return;
516 dig_connector = radeon_connector->con_priv;
517
518 dig_connector->dp_clock =
519 dp_link_clock_for_mode_clock(dig_connector->dpcd, mode->clock);
520 dig_connector->dp_lane_count =
521 dp_lanes_for_mode_clock(dig_connector->dpcd, mode->clock);
522}
523
524int radeon_dp_mode_valid_helper(struct radeon_connector *radeon_connector,
525 struct drm_display_mode *mode)
526{
527 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
528
529 return dp_mode_valid(dig_connector->dpcd, mode->clock);
530}
531
746c1aa4
DA		 532static bool atom_dp_get_link_status(struct radeon_connector *radeon_connector,
533 u8 link_status[DP_LINK_STATUS_SIZE])
534{
535 int ret;
834b2904
AD		 536 ret = radeon_dp_aux_native_read(radeon_connector, DP_LANE0_1_STATUS,
537 link_status, DP_LINK_STATUS_SIZE, 100);
538 if (ret <= 0) {
746c1aa4
DA		 539 DRM_ERROR("displayport link status failed\n");
540 return false;
541 }
542
d9fdaafb 543 DRM_DEBUG_KMS("link status %02x %02x %02x %02x %02x %02x\n",
53c1e09f
AD		 544 link_status[0], link_status[1], link_status[2],
545 link_status[3], link_status[4], link_status[5]);
746c1aa4
DA		 546 return true;
547}
548
d4877cf2
AD		 549bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector)
550{
551 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
552 u8 link_status[DP_LINK_STATUS_SIZE];
553
554 if (!atom_dp_get_link_status(radeon_connector, link_status))
555 return false;
556 if (dp_channel_eq_ok(link_status, dig_connector->dp_lane_count))
557 return false;
558 return true;
559}
560
746c1aa4
DA		 561static void dp_set_power(struct radeon_connector *radeon_connector, u8 power_state)
562{
5801ead6
AD		 563 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
564
565 if (dig_connector->dpcd[0] >= 0x11) {
834b2904
AD		 566 radeon_dp_aux_native_write(radeon_connector, DP_SET_POWER,
567 &power_state, 1, 0);
746c1aa4
DA		 568 }
569}
570
5801ead6
AD		 571static void dp_set_downspread(struct radeon_connector *radeon_connector, u8 downspread)
572{
834b2904
AD		 573 radeon_dp_aux_native_write(radeon_connector, DP_DOWNSPREAD_CTRL,
574 &downspread, 1, 0);
5801ead6
AD		 575}
576
577static void dp_set_link_bw_lanes(struct radeon_connector *radeon_connector,
578 u8 link_configuration[DP_LINK_CONFIGURATION_SIZE])
579{
834b2904
AD		 580 radeon_dp_aux_native_write(radeon_connector, DP_LINK_BW_SET,
581 link_configuration, 2, 0);
5801ead6
AD		 582}
583
746c1aa4 584static void dp_update_dpvs_emph(struct radeon_connector *radeon_connector,
5801ead6 585 struct drm_encoder *encoder,
746c1aa4
DA		 586 u8 train_set[4])
587{
5801ead6
AD		 588 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
589 int i;
590
591 for (i = 0; i < dig_connector->dp_lane_count; i++)
592 atombios_dig_transmitter_setup(encoder,
593 ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH,
594 i, train_set[i]);
746c1aa4 595
746c1aa4 596 radeon_dp_aux_native_write(radeon_connector, DP_TRAINING_LANE0_SET,
834b2904 597 train_set, dig_connector->dp_lane_count, 0);
746c1aa4
DA		 598}
599
600static void dp_set_training(struct radeon_connector *radeon_connector,
601 u8 training)
602{
603 radeon_dp_aux_native_write(radeon_connector, DP_TRAINING_PATTERN_SET,
834b2904 604 &training, 1, 0);
746c1aa4
DA		 605}
606
5801ead6
AD		 607void dp_link_train(struct drm_encoder *encoder,
608 struct drm_connector *connector)
609{
610 struct drm_device *dev = encoder->dev;
611 struct radeon_device *rdev = dev->dev_private;
612 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
613 struct radeon_encoder_atom_dig *dig;
614 struct radeon_connector *radeon_connector;
615 struct radeon_connector_atom_dig *dig_connector;
616 int enc_id = 0;
617 bool clock_recovery, channel_eq;
618 u8 link_status[DP_LINK_STATUS_SIZE];
619 u8 link_configuration[DP_LINK_CONFIGURATION_SIZE];
620 u8 tries, voltage;
621 u8 train_set[4];
622 int i;
623
97b94ccb 624 if ((connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) &&
196c58d2 625 (connector->connector_type != DRM_MODE_CONNECTOR_eDP))
5801ead6
AD		 626 return;
627
628 if (!radeon_encoder->enc_priv)
629 return;
630 dig = radeon_encoder->enc_priv;
631
632 radeon_connector = to_radeon_connector(connector);
633 if (!radeon_connector->con_priv)
634 return;
635 dig_connector = radeon_connector->con_priv;
636
f28cf339
DA		 637 if (dig->dig_encoder)
638 enc_id |= ATOM_DP_CONFIG_DIG2_ENCODER;
639 else
640 enc_id |= ATOM_DP_CONFIG_DIG1_ENCODER;
5137ee94 641 if (dig->linkb)
f28cf339
DA		 642 enc_id |= ATOM_DP_CONFIG_LINK_B;
643 else
644 enc_id |= ATOM_DP_CONFIG_LINK_A;
5801ead6
AD		 645
646 memset(link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
647 if (dig_connector->dp_clock == 270000)
648 link_configuration[0] = DP_LINK_BW_2_7;
649 else
650 link_configuration[0] = DP_LINK_BW_1_62;
651 link_configuration[1] = dig_connector->dp_lane_count;
652 if (dig_connector->dpcd[0] >= 0x11)
653 link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
654
655 /* power up the sink */
656 dp_set_power(radeon_connector, DP_SET_POWER_D0);
657 /* disable the training pattern on the sink */
658 dp_set_training(radeon_connector, DP_TRAINING_PATTERN_DISABLE);
659 /* set link bw and lanes on the sink */
660 dp_set_link_bw_lanes(radeon_connector, link_configuration);
661 /* disable downspread on the sink */
662 dp_set_downspread(radeon_connector, 0);
bcc1c2a1
AD		 663 if (ASIC_IS_DCE4(rdev)) {
664 /* start training on the source */
558e27db 665 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_LINK_TRAINING_START, 0);
bcc1c2a1 666 /* set training pattern 1 on the source */
558e27db 667 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1, 0);
bcc1c2a1
AD		 668 } else {
669 /* start training on the source */
670 radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_TRAINING_START,
671 dig_connector->dp_clock, enc_id, 0);
672 /* set training pattern 1 on the source */
673 radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_TRAINING_PATTERN_SEL,
674 dig_connector->dp_clock, enc_id, 0);
675 }
5801ead6
AD		 676
677 /* set initial vs/emph */
678 memset(train_set, 0, 4);
5801ead6
AD		 679 udelay(400);
680 /* set training pattern 1 on the sink */
681 dp_set_training(radeon_connector, DP_TRAINING_PATTERN_1);
682
5fbfce7f
DA		 683 dp_update_dpvs_emph(radeon_connector, encoder, train_set);
684
5801ead6
AD		 685 /* clock recovery loop */
686 clock_recovery = false;
687 tries = 0;
688 voltage = 0xff;
689 for (;;) {
690 udelay(100);
691 if (!atom_dp_get_link_status(radeon_connector, link_status))
692 break;
693
694 if (dp_clock_recovery_ok(link_status, dig_connector->dp_lane_count)) {
695 clock_recovery = true;
696 break;
697 }
698
699 for (i = 0; i < dig_connector->dp_lane_count; i++) {
700 if ((train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
701 break;
702 }
703 if (i == dig_connector->dp_lane_count) {
704 DRM_ERROR("clock recovery reached max voltage\n");
705 break;
706 }
707
708 if ((train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
709 ++tries;
710 if (tries == 5) {
711 DRM_ERROR("clock recovery tried 5 times\n");
712 break;
713 }
714 } else
715 tries = 0;
716
717 voltage = train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
718
719 /* Compute new train_set as requested by sink */
720 dp_get_adjust_train(link_status, dig_connector->dp_lane_count, train_set);
721 dp_update_dpvs_emph(radeon_connector, encoder, train_set);
722 }
723 if (!clock_recovery)
724 DRM_ERROR("clock recovery failed\n");
725 else
d9fdaafb 726 DRM_DEBUG_KMS("clock recovery at voltage %d pre-emphasis %d\n",
53c1e09f
AD		 727 train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
728 (train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >>
729 DP_TRAIN_PRE_EMPHASIS_SHIFT);
5801ead6
AD		 730
731
732 /* set training pattern 2 on the sink */
733 dp_set_training(radeon_connector, DP_TRAINING_PATTERN_2);
734 /* set training pattern 2 on the source */
bcc1c2a1 735 if (ASIC_IS_DCE4(rdev))
558e27db 736 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2, 0);
bcc1c2a1
AD		 737 else
738 radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_TRAINING_PATTERN_SEL,
739 dig_connector->dp_clock, enc_id, 1);
5801ead6
AD		 740
741 /* channel equalization loop */
742 tries = 0;
743 channel_eq = false;
744 for (;;) {
745 udelay(400);
746 if (!atom_dp_get_link_status(radeon_connector, link_status))
747 break;
748
749 if (dp_channel_eq_ok(link_status, dig_connector->dp_lane_count)) {
750 channel_eq = true;
751 break;
752 }
753
754 /* Try 5 times */
755 if (tries > 5) {
756 DRM_ERROR("channel eq failed: 5 tries\n");
757 break;
758 }
759
760 /* Compute new train_set as requested by sink */
761 dp_get_adjust_train(link_status, dig_connector->dp_lane_count, train_set);
762 dp_update_dpvs_emph(radeon_connector, encoder, train_set);
763
764 tries++;
765 }
766
767 if (!channel_eq)
768 DRM_ERROR("channel eq failed\n");
769 else
d9fdaafb 770 DRM_DEBUG_KMS("channel eq at voltage %d pre-emphasis %d\n",
53c1e09f
AD		 771 train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
772 (train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK)
773 >> DP_TRAIN_PRE_EMPHASIS_SHIFT);
5801ead6
AD		 774
775 /* disable the training pattern on the sink */
3b01a119
AD		 776 dp_set_training(radeon_connector, DP_TRAINING_PATTERN_DISABLE);
777
778 /* disable the training pattern on the source */
bcc1c2a1 779 if (ASIC_IS_DCE4(rdev))
558e27db 780 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE, 0);
bcc1c2a1
AD		 781 else
782 radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_TRAINING_COMPLETE,
783 dig_connector->dp_clock, enc_id, 0);
5801ead6
AD		 784}
785
746c1aa4 786int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
834b2904 787 u8 write_byte, u8 *read_byte)
746c1aa4
DA		 788{
789 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
790 struct radeon_i2c_chan *auxch = (struct radeon_i2c_chan *)adapter;
834b2904
AD		 791 u16 address = algo_data->address;
792 u8 msg[5];
793 u8 reply[2];
794 unsigned retry;
795 int msg_bytes;
796 int reply_bytes = 1;
797 int ret;
798 u8 ack;
746c1aa4
DA		 799
800 /* Set up the command byte */
801 if (mode & MODE_I2C_READ)
802 msg[2] = AUX_I2C_READ << 4;
803 else
804 msg[2] = AUX_I2C_WRITE << 4;
805
806 if (!(mode & MODE_I2C_STOP))
807 msg[2] |= AUX_I2C_MOT << 4;
808
809 msg[0] = address;
810 msg[1] = address >> 8;
811
746c1aa4
DA		 812 switch (mode) {
813 case MODE_I2C_WRITE:
834b2904
AD		 814 msg_bytes = 5;
815 msg[3] = msg_bytes << 4;
746c1aa4 816 msg[4] = write_byte;
746c1aa4
DA		 817 break;
818 case MODE_I2C_READ:
834b2904
AD		 819 msg_bytes = 4;
820 msg[3] = msg_bytes << 4;
746c1aa4
DA		 821 break;
822 default:
834b2904
AD		 823 msg_bytes = 4;
824 msg[3] = 3 << 4;
746c1aa4
DA		 825 break;
826 }
827
834b2904
AD		 828 for (retry = 0; retry < 4; retry++) {
829 ret = radeon_process_aux_ch(auxch,
830 msg, msg_bytes, reply, reply_bytes, 0, &ack);
831 if (ret < 0) {
832 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
833 return ret;
834 }
835
836 switch (ack & AUX_NATIVE_REPLY_MASK) {
837 case AUX_NATIVE_REPLY_ACK:
838 /* I2C-over-AUX Reply field is only valid
839 * when paired with AUX ACK.
840 */
841 break;
842 case AUX_NATIVE_REPLY_NACK:
843 DRM_DEBUG_KMS("aux_ch native nack\n");
844 return -EREMOTEIO;
845 case AUX_NATIVE_REPLY_DEFER:
846 DRM_DEBUG_KMS("aux_ch native defer\n");
847 udelay(400);
848 continue;
849 default:
850 DRM_ERROR("aux_ch invalid native reply 0x%02x\n", ack);
851 return -EREMOTEIO;
852 }
746c1aa4 853
834b2904
AD		 854 switch (ack & AUX_I2C_REPLY_MASK) {
855 case AUX_I2C_REPLY_ACK:
856 if (mode == MODE_I2C_READ)
857 *read_byte = reply[0];
858 return ret;
859 case AUX_I2C_REPLY_NACK:
860 DRM_DEBUG_KMS("aux_i2c nack\n");
861 return -EREMOTEIO;
862 case AUX_I2C_REPLY_DEFER:
863 DRM_DEBUG_KMS("aux_i2c defer\n");
864 udelay(400);
865 break;
866 default:
867 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", ack);
868 return -EREMOTEIO;
869 }
746c1aa4 870 }
834b2904
AD		 871
872 DRM_ERROR("aux i2c too many retries, giving up\n");
746c1aa4
DA		 873 return -EREMOTEIO;
874}
5801ead6 875
Linux kernel - Deliverables
This page took 0.155596 seconds and 5 git commands to generate.