projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge branch 'for-linus' of git://git.infradead.org/users/sameo/mfd-2.6
[deliverable/linux.git] / drivers / gpu / drm / radeon / atombios_dp.c
CommitLineData
746c1aa4
DA		 1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26#include "drmP.h"
27#include "radeon_drm.h"
28#include "radeon.h"
29
30#include "atom.h"
31#include "atom-bits.h"
32#include "drm_dp_helper.h"
33
f92a8b67 34/* move these to drm_dp_helper.c/h */
5801ead6
AD		 35#define DP_LINK_CONFIGURATION_SIZE 9
36#define DP_LINK_STATUS_SIZE 6
37#define DP_DPCD_SIZE 8
38
39static char *voltage_names[] = {
40 "0.4V", "0.6V", "0.8V", "1.2V"
41};
42static char *pre_emph_names[] = {
43 "0dB", "3.5dB", "6dB", "9.5dB"
44};
f92a8b67 45
224d94b1
AD		 46/***** radeon AUX functions *****/
47union aux_channel_transaction {
48 PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION v1;
49 PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 v2;
f92a8b67
AD		 50};
51
224d94b1
AD		 52static int radeon_process_aux_ch(struct radeon_i2c_chan *chan,
53 u8 *send, int send_bytes,
54 u8 *recv, int recv_size,
55 u8 delay, u8 *ack)
56{
57 struct drm_device *dev = chan->dev;
58 struct radeon_device *rdev = dev->dev_private;
59 union aux_channel_transaction args;
60 int index = GetIndexIntoMasterTable(COMMAND, ProcessAuxChannelTransaction);
61 unsigned char *base;
62 int recv_bytes;
63
64 memset(&args, 0, sizeof(args));
f92a8b67 65
224d94b1
AD		 66 base = (unsigned char *)rdev->mode_info.atom_context->scratch;
67
68 memcpy(base, send, send_bytes);
69
70 args.v1.lpAuxRequest = 0;
71 args.v1.lpDataOut = 16;
72 args.v1.ucDataOutLen = 0;
73 args.v1.ucChannelID = chan->rec.i2c_id;
74 args.v1.ucDelay = delay / 10;
75 if (ASIC_IS_DCE4(rdev))
76 args.v2.ucHPD_ID = chan->rec.hpd;
77
78 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
79
80 *ack = args.v1.ucReplyStatus;
81
82 /* timeout */
83 if (args.v1.ucReplyStatus == 1) {
84 DRM_DEBUG_KMS("dp_aux_ch timeout\n");
85 return -ETIMEDOUT;
86 }
87
88 /* flags not zero */
89 if (args.v1.ucReplyStatus == 2) {
90 DRM_DEBUG_KMS("dp_aux_ch flags not zero\n");
91 return -EBUSY;
92 }
93
94 /* error */
95 if (args.v1.ucReplyStatus == 3) {
96 DRM_DEBUG_KMS("dp_aux_ch error\n");
97 return -EIO;
98 }
99
100 recv_bytes = args.v1.ucDataOutLen;
101 if (recv_bytes > recv_size)
102 recv_bytes = recv_size;
103
104 if (recv && recv_size)
105 memcpy(recv, base + 16, recv_bytes);
106
107 return recv_bytes;
108}
109
110static int radeon_dp_aux_native_write(struct radeon_connector *radeon_connector,
111 u16 address, u8 *send, u8 send_bytes, u8 delay)
f92a8b67 112{
224d94b1
AD		 113 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
114 int ret;
115 u8 msg[20];
116 int msg_bytes = send_bytes + 4;
117 u8 ack;
5801ead6 118
224d94b1
AD		 119 if (send_bytes > 16)
120 return -1;
5801ead6 121
224d94b1
AD		 122 msg[0] = address;
123 msg[1] = address >> 8;
124 msg[2] = AUX_NATIVE_WRITE << 4;
125 msg[3] = (msg_bytes << 4) | (send_bytes - 1);
126 memcpy(&msg[4], send, send_bytes);
f92a8b67 127
224d94b1
AD		 128 while (1) {
129 ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus,
130 msg, msg_bytes, NULL, 0, delay, &ack);
131 if (ret < 0)
132 return ret;
133 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
134 break;
135 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
136 udelay(400);
137 else
138 return -EIO;
f92a8b67
AD		 139 }
140
224d94b1 141 return send_bytes;
f92a8b67
AD		 142}
143
224d94b1
AD		 144static int radeon_dp_aux_native_read(struct radeon_connector *radeon_connector,
145 u16 address, u8 *recv, int recv_bytes, u8 delay)
f92a8b67 146{
224d94b1
AD		 147 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
148 u8 msg[4];
149 int msg_bytes = 4;
150 u8 ack;
151 int ret;
5801ead6 152
224d94b1
AD		 153 msg[0] = address;
154 msg[1] = address >> 8;
155 msg[2] = AUX_NATIVE_READ << 4;
156 msg[3] = (msg_bytes << 4) | (recv_bytes - 1);
5801ead6 157
224d94b1
AD		 158 while (1) {
159 ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus,
160 msg, msg_bytes, recv, recv_bytes, delay, &ack);
161 if (ret == 0)
162 return -EPROTO;
163 if (ret < 0)
164 return ret;
165 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
166 return ret;
167 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
168 udelay(400);
169 else
170 return -EIO;
171 }
172}
f92a8b67 173
224d94b1
AD		 174static void radeon_write_dpcd_reg(struct radeon_connector *radeon_connector,
175 u16 reg, u8 val)
176{
177 radeon_dp_aux_native_write(radeon_connector, reg, &val, 1, 0);
178}
179
180static u8 radeon_read_dpcd_reg(struct radeon_connector *radeon_connector,
181 u16 reg)
182{
183 u8 val = 0;
184
185 radeon_dp_aux_native_read(radeon_connector, reg, &val, 1, 0);
186
187 return val;
188}
189
190int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
191 u8 write_byte, u8 *read_byte)
192{
193 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
194 struct radeon_i2c_chan *auxch = (struct radeon_i2c_chan *)adapter;
195 u16 address = algo_data->address;
196 u8 msg[5];
197 u8 reply[2];
198 unsigned retry;
199 int msg_bytes;
200 int reply_bytes = 1;
201 int ret;
202 u8 ack;
203
204 /* Set up the command byte */
205 if (mode & MODE_I2C_READ)
206 msg[2] = AUX_I2C_READ << 4;
207 else
208 msg[2] = AUX_I2C_WRITE << 4;
209
210 if (!(mode & MODE_I2C_STOP))
211 msg[2] |= AUX_I2C_MOT << 4;
212
213 msg[0] = address;
214 msg[1] = address >> 8;
215
216 switch (mode) {
217 case MODE_I2C_WRITE:
218 msg_bytes = 5;
219 msg[3] = msg_bytes << 4;
220 msg[4] = write_byte;
221 break;
222 case MODE_I2C_READ:
223 msg_bytes = 4;
224 msg[3] = msg_bytes << 4;
225 break;
f92a8b67 226 default:
224d94b1
AD		 227 msg_bytes = 4;
228 msg[3] = 3 << 4;
f92a8b67 229 break;
f92a8b67
AD		 230 }
231
224d94b1
AD		 232 for (retry = 0; retry < 4; retry++) {
233 ret = radeon_process_aux_ch(auxch,
234 msg, msg_bytes, reply, reply_bytes, 0, &ack);
235 if (ret < 0) {
236 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
237 return ret;
238 }
f92a8b67 239
224d94b1
AD		 240 switch (ack & AUX_NATIVE_REPLY_MASK) {
241 case AUX_NATIVE_REPLY_ACK:
242 /* I2C-over-AUX Reply field is only valid
243 * when paired with AUX ACK.
244 */
245 break;
246 case AUX_NATIVE_REPLY_NACK:
247 DRM_DEBUG_KMS("aux_ch native nack\n");
248 return -EREMOTEIO;
249 case AUX_NATIVE_REPLY_DEFER:
250 DRM_DEBUG_KMS("aux_ch native defer\n");
251 udelay(400);
252 continue;
253 default:
254 DRM_ERROR("aux_ch invalid native reply 0x%02x\n", ack);
255 return -EREMOTEIO;
256 }
5801ead6 257
224d94b1
AD		 258 switch (ack & AUX_I2C_REPLY_MASK) {
259 case AUX_I2C_REPLY_ACK:
260 if (mode == MODE_I2C_READ)
261 *read_byte = reply[0];
262 return ret;
263 case AUX_I2C_REPLY_NACK:
264 DRM_DEBUG_KMS("aux_i2c nack\n");
265 return -EREMOTEIO;
266 case AUX_I2C_REPLY_DEFER:
267 DRM_DEBUG_KMS("aux_i2c defer\n");
268 udelay(400);
269 break;
270 default:
271 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", ack);
272 return -EREMOTEIO;
273 }
274 }
5801ead6 275
224d94b1
AD		 276 DRM_ERROR("aux i2c too many retries, giving up\n");
277 return -EREMOTEIO;
5801ead6
AD		 278}
279
224d94b1
AD		 280/***** general DP utility functions *****/
281
5801ead6
AD		 282static u8 dp_link_status(u8 link_status[DP_LINK_STATUS_SIZE], int r)
283{
284 return link_status[r - DP_LANE0_1_STATUS];
285}
286
287static u8 dp_get_lane_status(u8 link_status[DP_LINK_STATUS_SIZE],
288 int lane)
289{
290 int i = DP_LANE0_1_STATUS + (lane >> 1);
291 int s = (lane & 1) * 4;
292 u8 l = dp_link_status(link_status, i);
293 return (l >> s) & 0xf;
294}
295
296static bool dp_clock_recovery_ok(u8 link_status[DP_LINK_STATUS_SIZE],
297 int lane_count)
298{
299 int lane;
300 u8 lane_status;
301
302 for (lane = 0; lane < lane_count; lane++) {
303 lane_status = dp_get_lane_status(link_status, lane);
304 if ((lane_status & DP_LANE_CR_DONE) == 0)
305 return false;
306 }
307 return true;
308}
309
310static bool dp_channel_eq_ok(u8 link_status[DP_LINK_STATUS_SIZE],
311 int lane_count)
312{
313 u8 lane_align;
314 u8 lane_status;
315 int lane;
316
317 lane_align = dp_link_status(link_status,
318 DP_LANE_ALIGN_STATUS_UPDATED);
319 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
320 return false;
321 for (lane = 0; lane < lane_count; lane++) {
322 lane_status = dp_get_lane_status(link_status, lane);
323 if ((lane_status & DP_CHANNEL_EQ_BITS) != DP_CHANNEL_EQ_BITS)
324 return false;
325 }
326 return true;
327}
328
224d94b1 329static u8 dp_get_adjust_request_voltage(u8 link_status[DP_LINK_STATUS_SIZE],
5801ead6
AD		 330 int lane)
331
332{
333 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
334 int s = ((lane & 1) ?
335 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
336 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
337 u8 l = dp_link_status(link_status, i);
338
339 return ((l >> s) & 0x3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
340}
341
224d94b1 342static u8 dp_get_adjust_request_pre_emphasis(u8 link_status[DP_LINK_STATUS_SIZE],
5801ead6
AD		 343 int lane)
344{
345 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
346 int s = ((lane & 1) ?
347 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
348 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
349 u8 l = dp_link_status(link_status, i);
350
351 return ((l >> s) & 0x3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
352}
353
5801ead6 354#define DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_1200
224d94b1 355#define DP_PRE_EMPHASIS_MAX DP_TRAIN_PRE_EMPHASIS_9_5
5801ead6
AD		 356
357static void dp_get_adjust_train(u8 link_status[DP_LINK_STATUS_SIZE],
358 int lane_count,
359 u8 train_set[4])
360{
361 u8 v = 0;
362 u8 p = 0;
363 int lane;
364
365 for (lane = 0; lane < lane_count; lane++) {
366 u8 this_v = dp_get_adjust_request_voltage(link_status, lane);
367 u8 this_p = dp_get_adjust_request_pre_emphasis(link_status, lane);
368
d9fdaafb 369 DRM_DEBUG_KMS("requested signal parameters: lane %d voltage %s pre_emph %s\n",
53c1e09f
AD		 370 lane,
371 voltage_names[this_v >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
372 pre_emph_names[this_p >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
5801ead6
AD		 373
374 if (this_v > v)
375 v = this_v;
376 if (this_p > p)
377 p = this_p;
378 }
379
380 if (v >= DP_VOLTAGE_MAX)
224d94b1 381 v |= DP_TRAIN_MAX_SWING_REACHED;
5801ead6 382
224d94b1
AD		 383 if (p >= DP_PRE_EMPHASIS_MAX)
384 p |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
5801ead6 385
d9fdaafb 386 DRM_DEBUG_KMS("using signal parameters: voltage %s pre_emph %s\n",
53c1e09f
AD		 387 voltage_names[(v & DP_TRAIN_VOLTAGE_SWING_MASK) >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
388 pre_emph_names[(p & DP_TRAIN_PRE_EMPHASIS_MASK) >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
5801ead6
AD		 389
390 for (lane = 0; lane < 4; lane++)
391 train_set[lane] = v | p;
392}
393
224d94b1
AD		 394/* convert bits per color to bits per pixel */
395/* get bpc from the EDID */
396static int convert_bpc_to_bpp(int bpc)
746c1aa4 397{
224d94b1
AD		 398 if (bpc == 0)
399 return 24;
400 else
401 return bpc * 3;
402}
746c1aa4 403
224d94b1
AD		 404/* get the max pix clock supported by the link rate and lane num */
405static int dp_get_max_dp_pix_clock(int link_rate,
406 int lane_num,
407 int bpp)
408{
409 return (link_rate * lane_num * 8) / bpp;
410}
834b2904 411
224d94b1
AD		 412static int dp_get_max_link_rate(u8 dpcd[DP_DPCD_SIZE])
413{
414 switch (dpcd[DP_MAX_LINK_RATE]) {
415 case DP_LINK_BW_1_62:
416 default:
417 return 162000;
418 case DP_LINK_BW_2_7:
419 return 270000;
420 case DP_LINK_BW_5_4:
421 return 540000;
834b2904 422 }
746c1aa4
DA		 423}
424
224d94b1 425static u8 dp_get_max_lane_number(u8 dpcd[DP_DPCD_SIZE])
746c1aa4 426{
224d94b1
AD		 427 return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK;
428}
834b2904 429
224d94b1
AD		 430static u8 dp_get_dp_link_rate_coded(int link_rate)
431{
432 switch (link_rate) {
433 case 162000:
434 default:
435 return DP_LINK_BW_1_62;
436 case 270000:
437 return DP_LINK_BW_2_7;
438 case 540000:
439 return DP_LINK_BW_5_4;
440 }
441}
746c1aa4 442
224d94b1 443/***** radeon specific DP functions *****/
746c1aa4 444
224d94b1
AD		 445/* First get the min lane# when low rate is used according to pixel clock
446 * (prefer low rate), second check max lane# supported by DP panel,
447 * if the max lane# < low rate lane# then use max lane# instead.
448 */
449static int radeon_dp_get_dp_lane_number(struct drm_connector *connector,
450 u8 dpcd[DP_DPCD_SIZE],
451 int pix_clock)
452{
453 int bpp = convert_bpc_to_bpp(connector->display_info.bpc);
454 int max_link_rate = dp_get_max_link_rate(dpcd);
455 int max_lane_num = dp_get_max_lane_number(dpcd);
456 int lane_num;
457 int max_dp_pix_clock;
458
459 for (lane_num = 1; lane_num < max_lane_num; lane_num <<= 1) {
460 max_dp_pix_clock = dp_get_max_dp_pix_clock(max_link_rate, lane_num, bpp);
461 if (pix_clock <= max_dp_pix_clock)
462 break;
834b2904 463 }
746c1aa4 464
224d94b1 465 return lane_num;
746c1aa4
DA		 466}
467
224d94b1
AD		 468static int radeon_dp_get_dp_link_clock(struct drm_connector *connector,
469 u8 dpcd[DP_DPCD_SIZE],
470 int pix_clock)
746c1aa4 471{
224d94b1
AD		 472 int bpp = convert_bpc_to_bpp(connector->display_info.bpc);
473 int lane_num, max_pix_clock;
474
475 if (radeon_connector_encoder_is_dp_bridge(connector))
476 return 270000;
477
478 lane_num = radeon_dp_get_dp_lane_number(connector, dpcd, pix_clock);
479 max_pix_clock = dp_get_max_dp_pix_clock(162000, lane_num, bpp);
480 if (pix_clock <= max_pix_clock)
481 return 162000;
482 max_pix_clock = dp_get_max_dp_pix_clock(270000, lane_num, bpp);
483 if (pix_clock <= max_pix_clock)
484 return 270000;
485 if (radeon_connector_is_dp12_capable(connector)) {
486 max_pix_clock = dp_get_max_dp_pix_clock(540000, lane_num, bpp);
487 if (pix_clock <= max_pix_clock)
488 return 540000;
834b2904 489 }
224d94b1
AD		 490
491 return dp_get_max_link_rate(dpcd);
746c1aa4
DA		 492}
493
834b2904
AD		 494static u8 radeon_dp_encoder_service(struct radeon_device *rdev,
495 int action, int dp_clock,
224d94b1 496 u8 ucconfig, u8 lane_num)
5801ead6
AD		 497{
498 DP_ENCODER_SERVICE_PARAMETERS args;
499 int index = GetIndexIntoMasterTable(COMMAND, DPEncoderService);
500
501 memset(&args, 0, sizeof(args));
502 args.ucLinkClock = dp_clock / 10;
503 args.ucConfig = ucconfig;
504 args.ucAction = action;
505 args.ucLaneNum = lane_num;
506 args.ucStatus = 0;
507
508 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
509 return args.ucStatus;
510}
511
512u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector)
513{
514 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
515 struct drm_device *dev = radeon_connector->base.dev;
516 struct radeon_device *rdev = dev->dev_private;
517
518 return radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_GET_SINK_TYPE, 0,
519 dig_connector->dp_i2c_bus->rec.i2c_id, 0);
520}
521
9fa05c98 522bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector)
746c1aa4 523{
5801ead6 524 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
746c1aa4 525 u8 msg[25];
224d94b1 526 int ret, i;
746c1aa4 527
834b2904
AD		 528 ret = radeon_dp_aux_native_read(radeon_connector, DP_DPCD_REV, msg, 8, 0);
529 if (ret > 0) {
5801ead6 530 memcpy(dig_connector->dpcd, msg, 8);
224d94b1
AD		 531 DRM_DEBUG_KMS("DPCD: ");
532 for (i = 0; i < 8; i++)
533 DRM_DEBUG_KMS("%02x ", msg[i]);
534 DRM_DEBUG_KMS("\n");
9fa05c98 535 return true;
746c1aa4 536 }
5801ead6 537 dig_connector->dpcd[0] = 0;
9fa05c98 538 return false;
746c1aa4
DA		 539}
540
224d94b1
AD		 541static void radeon_dp_set_panel_mode(struct drm_encoder *encoder,
542 struct drm_connector *connector)
543{
544 struct drm_device *dev = encoder->dev;
545 struct radeon_device *rdev = dev->dev_private;
546 int panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
547
548 if (!ASIC_IS_DCE4(rdev))
549 return;
550
551 if (radeon_connector_encoder_is_dp_bridge(connector))
552 panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE;
553
554 atombios_dig_encoder_setup(encoder,
555 ATOM_ENCODER_CMD_SETUP_PANEL_MODE,
556 panel_mode);
557}
558
5801ead6
AD		 559void radeon_dp_set_link_config(struct drm_connector *connector,
560 struct drm_display_mode *mode)
561{
224d94b1 562 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
5801ead6
AD		 563 struct radeon_connector_atom_dig *dig_connector;
564
5801ead6
AD		 565 if (!radeon_connector->con_priv)
566 return;
567 dig_connector = radeon_connector->con_priv;
568
224d94b1
AD		 569 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
570 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
571 dig_connector->dp_clock =
572 radeon_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock);
573 dig_connector->dp_lane_count =
574 radeon_dp_get_dp_lane_number(connector, dig_connector->dpcd, mode->clock);
575 }
5801ead6
AD		 576}
577
224d94b1 578int radeon_dp_mode_valid_helper(struct drm_connector *connector,
5801ead6
AD		 579 struct drm_display_mode *mode)
580{
224d94b1
AD		 581 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
582 struct radeon_connector_atom_dig *dig_connector;
583 int dp_clock;
5801ead6 584
224d94b1
AD		 585 if (!radeon_connector->con_priv)
586 return MODE_CLOCK_HIGH;
587 dig_connector = radeon_connector->con_priv;
588
589 dp_clock =
590 radeon_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock);
591
592 if ((dp_clock == 540000) &&
593 (!radeon_connector_is_dp12_capable(connector)))
594 return MODE_CLOCK_HIGH;
595
596 return MODE_OK;
5801ead6
AD		 597}
598
224d94b1
AD		 599static bool radeon_dp_get_link_status(struct radeon_connector *radeon_connector,
600 u8 link_status[DP_LINK_STATUS_SIZE])
746c1aa4
DA		 601{
602 int ret;
834b2904
AD		 603 ret = radeon_dp_aux_native_read(radeon_connector, DP_LANE0_1_STATUS,
604 link_status, DP_LINK_STATUS_SIZE, 100);
605 if (ret <= 0) {
746c1aa4
DA		 606 DRM_ERROR("displayport link status failed\n");
607 return false;
608 }
609
d9fdaafb 610 DRM_DEBUG_KMS("link status %02x %02x %02x %02x %02x %02x\n",
53c1e09f
AD		 611 link_status[0], link_status[1], link_status[2],
612 link_status[3], link_status[4], link_status[5]);
746c1aa4
DA		 613 return true;
614}
615
d5811e87
AD		 616bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector)
617{
618 u8 link_status[DP_LINK_STATUS_SIZE];
619 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
620
621 if (!radeon_dp_get_link_status(radeon_connector, link_status))
622 return false;
623 if (dp_channel_eq_ok(link_status, dig->dp_lane_count))
624 return false;
625 return true;
626}
627
224d94b1
AD		 628struct radeon_dp_link_train_info {
629 struct radeon_device *rdev;
630 struct drm_encoder *encoder;
631 struct drm_connector *connector;
632 struct radeon_connector *radeon_connector;
633 int enc_id;
634 int dp_clock;
635 int dp_lane_count;
636 int rd_interval;
637 bool tp3_supported;
638 u8 dpcd[8];
639 u8 train_set[4];
640 u8 link_status[DP_LINK_STATUS_SIZE];
641 u8 tries;
5a96a899 642 bool use_dpencoder;
224d94b1 643};
5801ead6 644
224d94b1 645static void radeon_dp_update_vs_emph(struct radeon_dp_link_train_info *dp_info)
5801ead6 646{
224d94b1
AD		 647 /* set the initial vs/emph on the source */
648 atombios_dig_transmitter_setup(dp_info->encoder,
649 ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH,
650 0, dp_info->train_set[0]); /* sets all lanes at once */
651
652 /* set the vs/emph on the sink */
653 radeon_dp_aux_native_write(dp_info->radeon_connector, DP_TRAINING_LANE0_SET,
654 dp_info->train_set, dp_info->dp_lane_count, 0);
5801ead6
AD		 655}
656
224d94b1 657static void radeon_dp_set_tp(struct radeon_dp_link_train_info *dp_info, int tp)
746c1aa4 658{
224d94b1 659 int rtp = 0;
746c1aa4 660
224d94b1 661 /* set training pattern on the source */
5a96a899 662 if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) {
224d94b1
AD		 663 switch (tp) {
664 case DP_TRAINING_PATTERN_1:
665 rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1;
666 break;
667 case DP_TRAINING_PATTERN_2:
668 rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2;
669 break;
670 case DP_TRAINING_PATTERN_3:
671 rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3;
672 break;
673 }
674 atombios_dig_encoder_setup(dp_info->encoder, rtp, 0);
675 } else {
676 switch (tp) {
677 case DP_TRAINING_PATTERN_1:
678 rtp = 0;
679 break;
680 case DP_TRAINING_PATTERN_2:
681 rtp = 1;
682 break;
683 }
684 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_PATTERN_SEL,
685 dp_info->dp_clock, dp_info->enc_id, rtp);
686 }
746c1aa4 687
224d94b1
AD		 688 /* enable training pattern on the sink */
689 radeon_write_dpcd_reg(dp_info->radeon_connector, DP_TRAINING_PATTERN_SET, tp);
746c1aa4
DA		 690}
691
224d94b1 692static int radeon_dp_link_train_init(struct radeon_dp_link_train_info *dp_info)
5801ead6 693{
224d94b1 694 u8 tmp;
5801ead6 695
224d94b1
AD		 696 /* power up the sink */
697 if (dp_info->dpcd[0] >= 0x11)
698 radeon_write_dpcd_reg(dp_info->radeon_connector,
699 DP_SET_POWER, DP_SET_POWER_D0);
700
701 /* possibly enable downspread on the sink */
702 if (dp_info->dpcd[3] & 0x1)
703 radeon_write_dpcd_reg(dp_info->radeon_connector,
704 DP_DOWNSPREAD_CTRL, DP_SPREAD_AMP_0_5);
705 else
706 radeon_write_dpcd_reg(dp_info->radeon_connector,
707 DP_DOWNSPREAD_CTRL, 0);
5801ead6 708
224d94b1 709 radeon_dp_set_panel_mode(dp_info->encoder, dp_info->connector);
5801ead6 710
224d94b1
AD		 711 /* set the lane count on the sink */
712 tmp = dp_info->dp_lane_count;
713 if (dp_info->dpcd[0] >= 0x11)
714 tmp |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
715 radeon_write_dpcd_reg(dp_info->radeon_connector, DP_LANE_COUNT_SET, tmp);
5801ead6 716
224d94b1
AD		 717 /* set the link rate on the sink */
718 tmp = dp_get_dp_link_rate_coded(dp_info->dp_clock);
719 radeon_write_dpcd_reg(dp_info->radeon_connector, DP_LINK_BW_SET, tmp);
5801ead6 720
224d94b1 721 /* start training on the source */
5a96a899 722 if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder)
224d94b1
AD		 723 atombios_dig_encoder_setup(dp_info->encoder,
724 ATOM_ENCODER_CMD_DP_LINK_TRAINING_START, 0);
5801ead6 725 else
224d94b1
AD		 726 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_START,
727 dp_info->dp_clock, dp_info->enc_id, 0);
5801ead6 728
5801ead6 729 /* disable the training pattern on the sink */
224d94b1
AD		 730 radeon_write_dpcd_reg(dp_info->radeon_connector,
731 DP_TRAINING_PATTERN_SET,
732 DP_TRAINING_PATTERN_DISABLE);
733
734 return 0;
735}
5801ead6 736
224d94b1
AD		 737static int radeon_dp_link_train_finish(struct radeon_dp_link_train_info *dp_info)
738{
5801ead6 739 udelay(400);
5801ead6 740
224d94b1
AD		 741 /* disable the training pattern on the sink */
742 radeon_write_dpcd_reg(dp_info->radeon_connector,
743 DP_TRAINING_PATTERN_SET,
744 DP_TRAINING_PATTERN_DISABLE);
745
746 /* disable the training pattern on the source */
5a96a899 747 if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder)
224d94b1
AD		 748 atombios_dig_encoder_setup(dp_info->encoder,
749 ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE, 0);
750 else
751 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_COMPLETE,
752 dp_info->dp_clock, dp_info->enc_id, 0);
753
754 return 0;
755}
756
757static int radeon_dp_link_train_cr(struct radeon_dp_link_train_info *dp_info)
758{
759 bool clock_recovery;
760 u8 voltage;
761 int i;
762
763 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_1);
764 memset(dp_info->train_set, 0, 4);
765 radeon_dp_update_vs_emph(dp_info);
766
767 udelay(400);
5fbfce7f 768
5801ead6
AD		 769 /* clock recovery loop */
770 clock_recovery = false;
224d94b1 771 dp_info->tries = 0;
5801ead6 772 voltage = 0xff;
224d94b1
AD		 773 while (1) {
774 if (dp_info->rd_interval == 0)
775 udelay(100);
776 else
777 mdelay(dp_info->rd_interval * 4);
778
779 if (!radeon_dp_get_link_status(dp_info->radeon_connector, dp_info->link_status))
5801ead6
AD		 780 break;
781
224d94b1 782 if (dp_clock_recovery_ok(dp_info->link_status, dp_info->dp_lane_count)) {
5801ead6
AD		 783 clock_recovery = true;
784 break;
785 }
786
224d94b1
AD		 787 for (i = 0; i < dp_info->dp_lane_count; i++) {
788 if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
5801ead6
AD		 789 break;
790 }
224d94b1 791 if (i == dp_info->dp_lane_count) {
5801ead6
AD		 792 DRM_ERROR("clock recovery reached max voltage\n");
793 break;
794 }
795
224d94b1
AD		 796 if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
797 ++dp_info->tries;
798 if (dp_info->tries == 5) {
5801ead6
AD		 799 DRM_ERROR("clock recovery tried 5 times\n");
800 break;
801 }
802 } else
224d94b1 803 dp_info->tries = 0;
5801ead6 804
224d94b1 805 voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
5801ead6
AD		 806
807 /* Compute new train_set as requested by sink */
224d94b1
AD		 808 dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set);
809
810 radeon_dp_update_vs_emph(dp_info);
5801ead6 811 }
224d94b1 812 if (!clock_recovery) {
5801ead6 813 DRM_ERROR("clock recovery failed\n");
224d94b1
AD		 814 return -1;
815 } else {
d9fdaafb 816 DRM_DEBUG_KMS("clock recovery at voltage %d pre-emphasis %d\n",
224d94b1
AD		 817 dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
818 (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >>
53c1e09f 819 DP_TRAIN_PRE_EMPHASIS_SHIFT);
224d94b1
AD		 820 return 0;
821 }
822}
5801ead6 823
224d94b1
AD		 824static int radeon_dp_link_train_ce(struct radeon_dp_link_train_info *dp_info)
825{
826 bool channel_eq;
5801ead6 827
224d94b1
AD		 828 if (dp_info->tp3_supported)
829 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_3);
bcc1c2a1 830 else
224d94b1 831 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_2);
5801ead6
AD		 832
833 /* channel equalization loop */
224d94b1 834 dp_info->tries = 0;
5801ead6 835 channel_eq = false;
224d94b1
AD		 836 while (1) {
837 if (dp_info->rd_interval == 0)
838 udelay(400);
839 else
840 mdelay(dp_info->rd_interval * 4);
841
842 if (!radeon_dp_get_link_status(dp_info->radeon_connector, dp_info->link_status))
5801ead6
AD		 843 break;
844
224d94b1 845 if (dp_channel_eq_ok(dp_info->link_status, dp_info->dp_lane_count)) {
5801ead6
AD		 846 channel_eq = true;
847 break;
848 }
849
850 /* Try 5 times */
224d94b1 851 if (dp_info->tries > 5) {
5801ead6
AD		 852 DRM_ERROR("channel eq failed: 5 tries\n");
853 break;
854 }
855
856 /* Compute new train_set as requested by sink */
224d94b1 857 dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set);
5801ead6 858
224d94b1
AD		 859 radeon_dp_update_vs_emph(dp_info);
860 dp_info->tries++;
5801ead6
AD		 861 }
862
224d94b1 863 if (!channel_eq) {
5801ead6 864 DRM_ERROR("channel eq failed\n");
224d94b1
AD		 865 return -1;
866 } else {
d9fdaafb 867 DRM_DEBUG_KMS("channel eq at voltage %d pre-emphasis %d\n",
224d94b1
AD		 868 dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
869 (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK)
53c1e09f 870 >> DP_TRAIN_PRE_EMPHASIS_SHIFT);
224d94b1
AD		 871 return 0;
872 }
5801ead6
AD		 873}
874
224d94b1
AD		 875void radeon_dp_link_train(struct drm_encoder *encoder,
876 struct drm_connector *connector)
746c1aa4 877{
224d94b1
AD		 878 struct drm_device *dev = encoder->dev;
879 struct radeon_device *rdev = dev->dev_private;
880 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
881 struct radeon_encoder_atom_dig *dig;
882 struct radeon_connector *radeon_connector;
883 struct radeon_connector_atom_dig *dig_connector;
884 struct radeon_dp_link_train_info dp_info;
5a96a899
JG		 885 int index;
886 u8 tmp, frev, crev;
746c1aa4 887
224d94b1
AD		 888 if (!radeon_encoder->enc_priv)
889 return;
890 dig = radeon_encoder->enc_priv;
746c1aa4 891
224d94b1
AD		 892 radeon_connector = to_radeon_connector(connector);
893 if (!radeon_connector->con_priv)
894 return;
895 dig_connector = radeon_connector->con_priv;
834b2904 896
224d94b1
AD		 897 if ((dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) &&
898 (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_eDP))
899 return;
746c1aa4 900
5a96a899
JG		 901 /* DPEncoderService newer than 1.1 can't program properly the
902 * training pattern. When facing such version use the
903 * DIGXEncoderControl (X== 1 | 2)
904 */
905 dp_info.use_dpencoder = true;
906 index = GetIndexIntoMasterTable(COMMAND, DPEncoderService);
907 if (atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) {
908 if (crev > 1) {
909 dp_info.use_dpencoder = false;
910 }
911 }
912
224d94b1
AD		 913 dp_info.enc_id = 0;
914 if (dig->dig_encoder)
915 dp_info.enc_id |= ATOM_DP_CONFIG_DIG2_ENCODER;
916 else
917 dp_info.enc_id |= ATOM_DP_CONFIG_DIG1_ENCODER;
918 if (dig->linkb)
919 dp_info.enc_id |= ATOM_DP_CONFIG_LINK_B;
920 else
921 dp_info.enc_id |= ATOM_DP_CONFIG_LINK_A;
834b2904 922
224d94b1
AD		 923 dp_info.rd_interval = radeon_read_dpcd_reg(radeon_connector, DP_TRAINING_AUX_RD_INTERVAL);
924 tmp = radeon_read_dpcd_reg(radeon_connector, DP_MAX_LANE_COUNT);
925 if (ASIC_IS_DCE5(rdev) && (tmp & DP_TPS3_SUPPORTED))
926 dp_info.tp3_supported = true;
927 else
928 dp_info.tp3_supported = false;
929
930 memcpy(dp_info.dpcd, dig_connector->dpcd, 8);
931 dp_info.rdev = rdev;
932 dp_info.encoder = encoder;
933 dp_info.connector = connector;
934 dp_info.radeon_connector = radeon_connector;
935 dp_info.dp_lane_count = dig_connector->dp_lane_count;
936 dp_info.dp_clock = dig_connector->dp_clock;
937
938 if (radeon_dp_link_train_init(&dp_info))
939 goto done;
940 if (radeon_dp_link_train_cr(&dp_info))
941 goto done;
942 if (radeon_dp_link_train_ce(&dp_info))
943 goto done;
944done:
945 if (radeon_dp_link_train_finish(&dp_info))
946 return;
746c1aa4 947}
Linux kernel - Deliverables
This page took 0.198429 seconds and 5 git commands to generate.