Commit | Line | Data |
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746c1aa4 DA |
1 | /* |
2 | * Copyright 2007-8 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice shall be included in | |
13 | * all copies or substantial portions of the Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
21 | * OTHER DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: Dave Airlie | |
24 | * Alex Deucher | |
8d1c702a | 25 | * Jerome Glisse |
746c1aa4 | 26 | */ |
760285e7 DH |
27 | #include <drm/drmP.h> |
28 | #include <drm/radeon_drm.h> | |
746c1aa4 DA |
29 | #include "radeon.h" |
30 | ||
31 | #include "atom.h" | |
32 | #include "atom-bits.h" | |
760285e7 | 33 | #include <drm/drm_dp_helper.h> |
746c1aa4 | 34 | |
f92a8b67 | 35 | /* move these to drm_dp_helper.c/h */ |
5801ead6 | 36 | #define DP_LINK_CONFIGURATION_SIZE 9 |
1a644cd4 | 37 | #define DP_DPCD_SIZE DP_RECEIVER_CAP_SIZE |
5801ead6 AD |
38 | |
39 | static char *voltage_names[] = { | |
40 | "0.4V", "0.6V", "0.8V", "1.2V" | |
41 | }; | |
42 | static char *pre_emph_names[] = { | |
43 | "0dB", "3.5dB", "6dB", "9.5dB" | |
44 | }; | |
f92a8b67 | 45 | |
224d94b1 | 46 | /***** radeon AUX functions *****/ |
34be8c9a AD |
47 | |
48 | /* Atom needs data in little endian format | |
49 | * so swap as appropriate when copying data to | |
50 | * or from atom. Note that atom operates on | |
51 | * dw units. | |
52 | */ | |
4543eda5 | 53 | void radeon_atom_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le) |
34be8c9a AD |
54 | { |
55 | #ifdef __BIG_ENDIAN | |
56 | u8 src_tmp[20], dst_tmp[20]; /* used for byteswapping */ | |
57 | u32 *dst32, *src32; | |
58 | int i; | |
59 | ||
60 | memcpy(src_tmp, src, num_bytes); | |
61 | src32 = (u32 *)src_tmp; | |
62 | dst32 = (u32 *)dst_tmp; | |
63 | if (to_le) { | |
64 | for (i = 0; i < ((num_bytes + 3) / 4); i++) | |
65 | dst32[i] = cpu_to_le32(src32[i]); | |
66 | memcpy(dst, dst_tmp, num_bytes); | |
67 | } else { | |
68 | u8 dws = num_bytes & ~3; | |
69 | for (i = 0; i < ((num_bytes + 3) / 4); i++) | |
70 | dst32[i] = le32_to_cpu(src32[i]); | |
71 | memcpy(dst, dst_tmp, dws); | |
72 | if (num_bytes % 4) { | |
73 | for (i = 0; i < (num_bytes % 4); i++) | |
74 | dst[dws+i] = dst_tmp[dws+i]; | |
75 | } | |
76 | } | |
77 | #else | |
78 | memcpy(dst, src, num_bytes); | |
79 | #endif | |
80 | } | |
81 | ||
224d94b1 AD |
82 | union aux_channel_transaction { |
83 | PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION v1; | |
84 | PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 v2; | |
f92a8b67 AD |
85 | }; |
86 | ||
224d94b1 AD |
87 | static int radeon_process_aux_ch(struct radeon_i2c_chan *chan, |
88 | u8 *send, int send_bytes, | |
89 | u8 *recv, int recv_size, | |
90 | u8 delay, u8 *ack) | |
91 | { | |
92 | struct drm_device *dev = chan->dev; | |
93 | struct radeon_device *rdev = dev->dev_private; | |
94 | union aux_channel_transaction args; | |
95 | int index = GetIndexIntoMasterTable(COMMAND, ProcessAuxChannelTransaction); | |
96 | unsigned char *base; | |
97 | int recv_bytes; | |
831719d6 | 98 | int r = 0; |
224d94b1 AD |
99 | |
100 | memset(&args, 0, sizeof(args)); | |
f92a8b67 | 101 | |
831719d6 | 102 | mutex_lock(&chan->mutex); |
1c949842 | 103 | mutex_lock(&rdev->mode_info.atom_context->scratch_mutex); |
831719d6 | 104 | |
97412a7a | 105 | base = (unsigned char *)(rdev->mode_info.atom_context->scratch + 1); |
224d94b1 | 106 | |
4543eda5 | 107 | radeon_atom_copy_swap(base, send, send_bytes, true); |
224d94b1 | 108 | |
34be8c9a AD |
109 | args.v1.lpAuxRequest = cpu_to_le16((u16)(0 + 4)); |
110 | args.v1.lpDataOut = cpu_to_le16((u16)(16 + 4)); | |
224d94b1 AD |
111 | args.v1.ucDataOutLen = 0; |
112 | args.v1.ucChannelID = chan->rec.i2c_id; | |
113 | args.v1.ucDelay = delay / 10; | |
114 | if (ASIC_IS_DCE4(rdev)) | |
115 | args.v2.ucHPD_ID = chan->rec.hpd; | |
116 | ||
1c949842 | 117 | atom_execute_table_scratch_unlocked(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
224d94b1 AD |
118 | |
119 | *ack = args.v1.ucReplyStatus; | |
120 | ||
121 | /* timeout */ | |
122 | if (args.v1.ucReplyStatus == 1) { | |
123 | DRM_DEBUG_KMS("dp_aux_ch timeout\n"); | |
831719d6 AD |
124 | r = -ETIMEDOUT; |
125 | goto done; | |
224d94b1 AD |
126 | } |
127 | ||
128 | /* flags not zero */ | |
129 | if (args.v1.ucReplyStatus == 2) { | |
130 | DRM_DEBUG_KMS("dp_aux_ch flags not zero\n"); | |
f6be5e64 | 131 | r = -EIO; |
831719d6 | 132 | goto done; |
224d94b1 AD |
133 | } |
134 | ||
135 | /* error */ | |
136 | if (args.v1.ucReplyStatus == 3) { | |
137 | DRM_DEBUG_KMS("dp_aux_ch error\n"); | |
831719d6 AD |
138 | r = -EIO; |
139 | goto done; | |
224d94b1 AD |
140 | } |
141 | ||
142 | recv_bytes = args.v1.ucDataOutLen; | |
143 | if (recv_bytes > recv_size) | |
144 | recv_bytes = recv_size; | |
145 | ||
146 | if (recv && recv_size) | |
4543eda5 | 147 | radeon_atom_copy_swap(recv, base + 16, recv_bytes, false); |
224d94b1 | 148 | |
831719d6 AD |
149 | r = recv_bytes; |
150 | done: | |
1c949842 | 151 | mutex_unlock(&rdev->mode_info.atom_context->scratch_mutex); |
831719d6 AD |
152 | mutex_unlock(&chan->mutex); |
153 | ||
154 | return r; | |
224d94b1 AD |
155 | } |
156 | ||
25377b92 AD |
157 | #define BARE_ADDRESS_SIZE 3 |
158 | #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1) | |
5801ead6 | 159 | |
496263bf | 160 | static ssize_t |
875711f0 | 161 | radeon_dp_aux_transfer_atom(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) |
f92a8b67 | 162 | { |
496263bf AD |
163 | struct radeon_i2c_chan *chan = |
164 | container_of(aux, struct radeon_i2c_chan, aux); | |
224d94b1 | 165 | int ret; |
496263bf AD |
166 | u8 tx_buf[20]; |
167 | size_t tx_size; | |
168 | u8 ack, delay = 0; | |
169 | ||
170 | if (WARN_ON(msg->size > 16)) | |
171 | return -E2BIG; | |
172 | ||
173 | tx_buf[0] = msg->address & 0xff; | |
174 | tx_buf[1] = msg->address >> 8; | |
175 | tx_buf[2] = msg->request << 4; | |
25377b92 | 176 | tx_buf[3] = msg->size ? (msg->size - 1) : 0; |
496263bf AD |
177 | |
178 | switch (msg->request & ~DP_AUX_I2C_MOT) { | |
179 | case DP_AUX_NATIVE_WRITE: | |
180 | case DP_AUX_I2C_WRITE: | |
94a47c49 AD |
181 | /* The atom implementation only supports writes with a max payload of |
182 | * 12 bytes since it uses 4 bits for the total count (header + payload) | |
183 | * in the parameter space. The atom interface supports 16 byte | |
184 | * payloads for reads. The hw itself supports up to 16 bytes of payload. | |
185 | */ | |
186 | if (WARN_ON_ONCE(msg->size > 12)) | |
187 | return -E2BIG; | |
25377b92 AD |
188 | /* tx_size needs to be 4 even for bare address packets since the atom |
189 | * table needs the info in tx_buf[3]. | |
190 | */ | |
496263bf | 191 | tx_size = HEADER_SIZE + msg->size; |
25377b92 AD |
192 | if (msg->size == 0) |
193 | tx_buf[3] |= BARE_ADDRESS_SIZE << 4; | |
194 | else | |
195 | tx_buf[3] |= tx_size << 4; | |
496263bf AD |
196 | memcpy(tx_buf + HEADER_SIZE, msg->buffer, msg->size); |
197 | ret = radeon_process_aux_ch(chan, | |
198 | tx_buf, tx_size, NULL, 0, delay, &ack); | |
199 | if (ret >= 0) | |
200 | /* Return payload size. */ | |
201 | ret = msg->size; | |
202 | break; | |
203 | case DP_AUX_NATIVE_READ: | |
204 | case DP_AUX_I2C_READ: | |
25377b92 AD |
205 | /* tx_size needs to be 4 even for bare address packets since the atom |
206 | * table needs the info in tx_buf[3]. | |
207 | */ | |
496263bf | 208 | tx_size = HEADER_SIZE; |
25377b92 AD |
209 | if (msg->size == 0) |
210 | tx_buf[3] |= BARE_ADDRESS_SIZE << 4; | |
211 | else | |
212 | tx_buf[3] |= tx_size << 4; | |
496263bf AD |
213 | ret = radeon_process_aux_ch(chan, |
214 | tx_buf, tx_size, msg->buffer, msg->size, delay, &ack); | |
215 | break; | |
216 | default: | |
217 | ret = -EINVAL; | |
218 | break; | |
224d94b1 | 219 | } |
6375bda0 | 220 | |
25377b92 | 221 | if (ret >= 0) |
496263bf | 222 | msg->reply = ack >> 4; |
f92a8b67 | 223 | |
496263bf | 224 | return ret; |
224d94b1 AD |
225 | } |
226 | ||
496263bf | 227 | void radeon_dp_aux_init(struct radeon_connector *radeon_connector) |
224d94b1 | 228 | { |
875711f0 DA |
229 | struct drm_device *dev = radeon_connector->base.dev; |
230 | struct radeon_device *rdev = dev->dev_private; | |
224d94b1 | 231 | int ret; |
f92a8b67 | 232 | |
ad47b8fa | 233 | radeon_connector->ddc_bus->rec.hpd = radeon_connector->hpd.hpd; |
379dfc25 | 234 | radeon_connector->ddc_bus->aux.dev = radeon_connector->base.kdev; |
875711f0 DA |
235 | if (ASIC_IS_DCE5(rdev)) { |
236 | if (radeon_auxch) | |
237 | radeon_connector->ddc_bus->aux.transfer = radeon_dp_aux_transfer_native; | |
238 | else | |
239 | radeon_connector->ddc_bus->aux.transfer = radeon_dp_aux_transfer_atom; | |
240 | } else { | |
241 | radeon_connector->ddc_bus->aux.transfer = radeon_dp_aux_transfer_atom; | |
242 | } | |
4f71d0cb DA |
243 | |
244 | ret = drm_dp_aux_register(&radeon_connector->ddc_bus->aux); | |
379dfc25 AD |
245 | if (!ret) |
246 | radeon_connector->ddc_bus->has_aux = true; | |
f92a8b67 | 247 | |
4f71d0cb | 248 | WARN(ret, "drm_dp_aux_register() failed with error %d\n", ret); |
5801ead6 AD |
249 | } |
250 | ||
224d94b1 AD |
251 | /***** general DP utility functions *****/ |
252 | ||
9cecb371 SJ |
253 | #define DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_LEVEL_3 |
254 | #define DP_PRE_EMPHASIS_MAX DP_TRAIN_PRE_EMPH_LEVEL_3 | |
5801ead6 AD |
255 | |
256 | static void dp_get_adjust_train(u8 link_status[DP_LINK_STATUS_SIZE], | |
257 | int lane_count, | |
258 | u8 train_set[4]) | |
259 | { | |
260 | u8 v = 0; | |
261 | u8 p = 0; | |
262 | int lane; | |
263 | ||
264 | for (lane = 0; lane < lane_count; lane++) { | |
0f037bde DV |
265 | u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane); |
266 | u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane); | |
5801ead6 | 267 | |
d9fdaafb | 268 | DRM_DEBUG_KMS("requested signal parameters: lane %d voltage %s pre_emph %s\n", |
53c1e09f AD |
269 | lane, |
270 | voltage_names[this_v >> DP_TRAIN_VOLTAGE_SWING_SHIFT], | |
271 | pre_emph_names[this_p >> DP_TRAIN_PRE_EMPHASIS_SHIFT]); | |
5801ead6 AD |
272 | |
273 | if (this_v > v) | |
274 | v = this_v; | |
275 | if (this_p > p) | |
276 | p = this_p; | |
277 | } | |
278 | ||
279 | if (v >= DP_VOLTAGE_MAX) | |
224d94b1 | 280 | v |= DP_TRAIN_MAX_SWING_REACHED; |
5801ead6 | 281 | |
224d94b1 AD |
282 | if (p >= DP_PRE_EMPHASIS_MAX) |
283 | p |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; | |
5801ead6 | 284 | |
d9fdaafb | 285 | DRM_DEBUG_KMS("using signal parameters: voltage %s pre_emph %s\n", |
53c1e09f AD |
286 | voltage_names[(v & DP_TRAIN_VOLTAGE_SWING_MASK) >> DP_TRAIN_VOLTAGE_SWING_SHIFT], |
287 | pre_emph_names[(p & DP_TRAIN_PRE_EMPHASIS_MASK) >> DP_TRAIN_PRE_EMPHASIS_SHIFT]); | |
5801ead6 AD |
288 | |
289 | for (lane = 0; lane < 4; lane++) | |
290 | train_set[lane] = v | p; | |
291 | } | |
292 | ||
224d94b1 AD |
293 | /* convert bits per color to bits per pixel */ |
294 | /* get bpc from the EDID */ | |
295 | static int convert_bpc_to_bpp(int bpc) | |
746c1aa4 | 296 | { |
224d94b1 AD |
297 | if (bpc == 0) |
298 | return 24; | |
299 | else | |
300 | return bpc * 3; | |
301 | } | |
746c1aa4 | 302 | |
224d94b1 AD |
303 | /* get the max pix clock supported by the link rate and lane num */ |
304 | static int dp_get_max_dp_pix_clock(int link_rate, | |
305 | int lane_num, | |
306 | int bpp) | |
307 | { | |
308 | return (link_rate * lane_num * 8) / bpp; | |
309 | } | |
834b2904 | 310 | |
224d94b1 | 311 | /***** radeon specific DP functions *****/ |
746c1aa4 | 312 | |
2be123d7 DA |
313 | int radeon_dp_get_max_link_rate(struct drm_connector *connector, |
314 | u8 dpcd[DP_DPCD_SIZE]) | |
3b6d9fd2 AD |
315 | { |
316 | int max_link_rate; | |
317 | ||
318 | if (radeon_connector_is_dp12_capable(connector)) | |
319 | max_link_rate = min(drm_dp_max_link_rate(dpcd), 540000); | |
320 | else | |
321 | max_link_rate = min(drm_dp_max_link_rate(dpcd), 270000); | |
322 | ||
323 | return max_link_rate; | |
324 | } | |
325 | ||
224d94b1 AD |
326 | /* First get the min lane# when low rate is used according to pixel clock |
327 | * (prefer low rate), second check max lane# supported by DP panel, | |
328 | * if the max lane# < low rate lane# then use max lane# instead. | |
329 | */ | |
330 | static int radeon_dp_get_dp_lane_number(struct drm_connector *connector, | |
331 | u8 dpcd[DP_DPCD_SIZE], | |
332 | int pix_clock) | |
333 | { | |
eccea792 | 334 | int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector)); |
3b6d9fd2 | 335 | int max_link_rate = radeon_dp_get_max_link_rate(connector, dpcd); |
397fe157 | 336 | int max_lane_num = drm_dp_max_lane_count(dpcd); |
224d94b1 AD |
337 | int lane_num; |
338 | int max_dp_pix_clock; | |
339 | ||
340 | for (lane_num = 1; lane_num < max_lane_num; lane_num <<= 1) { | |
341 | max_dp_pix_clock = dp_get_max_dp_pix_clock(max_link_rate, lane_num, bpp); | |
342 | if (pix_clock <= max_dp_pix_clock) | |
343 | break; | |
834b2904 | 344 | } |
746c1aa4 | 345 | |
224d94b1 | 346 | return lane_num; |
746c1aa4 DA |
347 | } |
348 | ||
224d94b1 AD |
349 | static int radeon_dp_get_dp_link_clock(struct drm_connector *connector, |
350 | u8 dpcd[DP_DPCD_SIZE], | |
351 | int pix_clock) | |
746c1aa4 | 352 | { |
eccea792 | 353 | int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector)); |
224d94b1 AD |
354 | int lane_num, max_pix_clock; |
355 | ||
fdca78c3 AD |
356 | if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) == |
357 | ENCODER_OBJECT_ID_NUTMEG) | |
224d94b1 AD |
358 | return 270000; |
359 | ||
360 | lane_num = radeon_dp_get_dp_lane_number(connector, dpcd, pix_clock); | |
361 | max_pix_clock = dp_get_max_dp_pix_clock(162000, lane_num, bpp); | |
362 | if (pix_clock <= max_pix_clock) | |
363 | return 162000; | |
364 | max_pix_clock = dp_get_max_dp_pix_clock(270000, lane_num, bpp); | |
365 | if (pix_clock <= max_pix_clock) | |
366 | return 270000; | |
367 | if (radeon_connector_is_dp12_capable(connector)) { | |
368 | max_pix_clock = dp_get_max_dp_pix_clock(540000, lane_num, bpp); | |
369 | if (pix_clock <= max_pix_clock) | |
370 | return 540000; | |
834b2904 | 371 | } |
224d94b1 | 372 | |
3b6d9fd2 | 373 | return radeon_dp_get_max_link_rate(connector, dpcd); |
746c1aa4 DA |
374 | } |
375 | ||
834b2904 AD |
376 | static u8 radeon_dp_encoder_service(struct radeon_device *rdev, |
377 | int action, int dp_clock, | |
224d94b1 | 378 | u8 ucconfig, u8 lane_num) |
5801ead6 AD |
379 | { |
380 | DP_ENCODER_SERVICE_PARAMETERS args; | |
381 | int index = GetIndexIntoMasterTable(COMMAND, DPEncoderService); | |
382 | ||
383 | memset(&args, 0, sizeof(args)); | |
384 | args.ucLinkClock = dp_clock / 10; | |
385 | args.ucConfig = ucconfig; | |
386 | args.ucAction = action; | |
387 | args.ucLaneNum = lane_num; | |
388 | args.ucStatus = 0; | |
389 | ||
390 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
391 | return args.ucStatus; | |
392 | } | |
393 | ||
394 | u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector) | |
395 | { | |
5801ead6 AD |
396 | struct drm_device *dev = radeon_connector->base.dev; |
397 | struct radeon_device *rdev = dev->dev_private; | |
398 | ||
399 | return radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_GET_SINK_TYPE, 0, | |
379dfc25 | 400 | radeon_connector->ddc_bus->rec.i2c_id, 0); |
5801ead6 AD |
401 | } |
402 | ||
40c5d876 AJ |
403 | static void radeon_dp_probe_oui(struct radeon_connector *radeon_connector) |
404 | { | |
405 | struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; | |
406 | u8 buf[3]; | |
407 | ||
408 | if (!(dig_connector->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) | |
409 | return; | |
410 | ||
aa019b79 | 411 | if (drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_SINK_OUI, buf, 3) == 3) |
40c5d876 AJ |
412 | DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n", |
413 | buf[0], buf[1], buf[2]); | |
414 | ||
aa019b79 | 415 | if (drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_BRANCH_OUI, buf, 3) == 3) |
40c5d876 AJ |
416 | DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n", |
417 | buf[0], buf[1], buf[2]); | |
418 | } | |
419 | ||
9fa05c98 | 420 | bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector) |
746c1aa4 | 421 | { |
5801ead6 | 422 | struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; |
1a644cd4 | 423 | u8 msg[DP_DPCD_SIZE]; |
0f28d128 | 424 | int ret, i; |
4e5f97de | 425 | |
0f28d128 AD |
426 | for (i = 0; i < 7; i++) { |
427 | ret = drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_DPCD_REV, msg, | |
428 | DP_DPCD_SIZE); | |
429 | if (ret == DP_DPCD_SIZE) { | |
430 | memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE); | |
4e5f97de | 431 | |
0f28d128 AD |
432 | DRM_DEBUG_KMS("DPCD: %*ph\n", (int)sizeof(dig_connector->dpcd), |
433 | dig_connector->dpcd); | |
40c5d876 | 434 | |
0f28d128 | 435 | radeon_dp_probe_oui(radeon_connector); |
40c5d876 | 436 | |
0f28d128 AD |
437 | return true; |
438 | } | |
746c1aa4 | 439 | } |
5801ead6 | 440 | dig_connector->dpcd[0] = 0; |
9fa05c98 | 441 | return false; |
746c1aa4 DA |
442 | } |
443 | ||
386d4d75 AD |
444 | int radeon_dp_get_panel_mode(struct drm_encoder *encoder, |
445 | struct drm_connector *connector) | |
224d94b1 AD |
446 | { |
447 | struct drm_device *dev = encoder->dev; | |
448 | struct radeon_device *rdev = dev->dev_private; | |
00dfb8df | 449 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
496263bf | 450 | struct radeon_connector_atom_dig *dig_connector; |
224d94b1 | 451 | int panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE; |
0ceb996c AD |
452 | u16 dp_bridge = radeon_connector_encoder_get_dp_bridge_encoder_id(connector); |
453 | u8 tmp; | |
224d94b1 AD |
454 | |
455 | if (!ASIC_IS_DCE4(rdev)) | |
386d4d75 | 456 | return panel_mode; |
224d94b1 | 457 | |
496263bf AD |
458 | if (!radeon_connector->con_priv) |
459 | return panel_mode; | |
460 | ||
461 | dig_connector = radeon_connector->con_priv; | |
462 | ||
0ceb996c AD |
463 | if (dp_bridge != ENCODER_OBJECT_ID_NONE) { |
464 | /* DP bridge chips */ | |
aa019b79 AD |
465 | if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux, |
466 | DP_EDP_CONFIGURATION_CAP, &tmp) == 1) { | |
467 | if (tmp & 1) | |
468 | panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE; | |
469 | else if ((dp_bridge == ENCODER_OBJECT_ID_NUTMEG) || | |
470 | (dp_bridge == ENCODER_OBJECT_ID_TRAVIS)) | |
471 | panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE; | |
472 | else | |
473 | panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE; | |
474 | } | |
304a4840 | 475 | } else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { |
0ceb996c | 476 | /* eDP */ |
aa019b79 AD |
477 | if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux, |
478 | DP_EDP_CONFIGURATION_CAP, &tmp) == 1) { | |
479 | if (tmp & 1) | |
480 | panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE; | |
481 | } | |
00dfb8df | 482 | } |
224d94b1 | 483 | |
386d4d75 | 484 | return panel_mode; |
224d94b1 AD |
485 | } |
486 | ||
5801ead6 | 487 | void radeon_dp_set_link_config(struct drm_connector *connector, |
e811f5ae | 488 | const struct drm_display_mode *mode) |
5801ead6 | 489 | { |
224d94b1 | 490 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
5801ead6 AD |
491 | struct radeon_connector_atom_dig *dig_connector; |
492 | ||
5801ead6 AD |
493 | if (!radeon_connector->con_priv) |
494 | return; | |
495 | dig_connector = radeon_connector->con_priv; | |
496 | ||
224d94b1 AD |
497 | if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || |
498 | (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) { | |
499 | dig_connector->dp_clock = | |
500 | radeon_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock); | |
501 | dig_connector->dp_lane_count = | |
502 | radeon_dp_get_dp_lane_number(connector, dig_connector->dpcd, mode->clock); | |
503 | } | |
5801ead6 AD |
504 | } |
505 | ||
224d94b1 | 506 | int radeon_dp_mode_valid_helper(struct drm_connector *connector, |
5801ead6 AD |
507 | struct drm_display_mode *mode) |
508 | { | |
224d94b1 AD |
509 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
510 | struct radeon_connector_atom_dig *dig_connector; | |
511 | int dp_clock; | |
5801ead6 | 512 | |
410cce2a AD |
513 | if ((mode->clock > 340000) && |
514 | (!radeon_connector_is_dp12_capable(connector))) | |
515 | return MODE_CLOCK_HIGH; | |
516 | ||
224d94b1 AD |
517 | if (!radeon_connector->con_priv) |
518 | return MODE_CLOCK_HIGH; | |
519 | dig_connector = radeon_connector->con_priv; | |
520 | ||
521 | dp_clock = | |
522 | radeon_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock); | |
523 | ||
524 | if ((dp_clock == 540000) && | |
525 | (!radeon_connector_is_dp12_capable(connector))) | |
526 | return MODE_CLOCK_HIGH; | |
527 | ||
528 | return MODE_OK; | |
5801ead6 AD |
529 | } |
530 | ||
d5811e87 AD |
531 | bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector) |
532 | { | |
533 | u8 link_status[DP_LINK_STATUS_SIZE]; | |
534 | struct radeon_connector_atom_dig *dig = radeon_connector->con_priv; | |
535 | ||
379dfc25 AD |
536 | if (drm_dp_dpcd_read_link_status(&radeon_connector->ddc_bus->aux, link_status) |
537 | <= 0) | |
d5811e87 | 538 | return false; |
1ffdff13 | 539 | if (drm_dp_channel_eq_ok(link_status, dig->dp_lane_count)) |
d5811e87 AD |
540 | return false; |
541 | return true; | |
542 | } | |
543 | ||
2953da15 AD |
544 | void radeon_dp_set_rx_power_state(struct drm_connector *connector, |
545 | u8 power_state) | |
546 | { | |
547 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
548 | struct radeon_connector_atom_dig *dig_connector; | |
549 | ||
550 | if (!radeon_connector->con_priv) | |
551 | return; | |
552 | ||
553 | dig_connector = radeon_connector->con_priv; | |
554 | ||
555 | /* power up/down the sink */ | |
556 | if (dig_connector->dpcd[0] >= 0x11) { | |
379dfc25 | 557 | drm_dp_dpcd_writeb(&radeon_connector->ddc_bus->aux, |
2953da15 AD |
558 | DP_SET_POWER, power_state); |
559 | usleep_range(1000, 2000); | |
560 | } | |
561 | } | |
562 | ||
563 | ||
224d94b1 AD |
564 | struct radeon_dp_link_train_info { |
565 | struct radeon_device *rdev; | |
566 | struct drm_encoder *encoder; | |
567 | struct drm_connector *connector; | |
224d94b1 AD |
568 | int enc_id; |
569 | int dp_clock; | |
570 | int dp_lane_count; | |
224d94b1 | 571 | bool tp3_supported; |
1a644cd4 | 572 | u8 dpcd[DP_RECEIVER_CAP_SIZE]; |
224d94b1 AD |
573 | u8 train_set[4]; |
574 | u8 link_status[DP_LINK_STATUS_SIZE]; | |
575 | u8 tries; | |
5a96a899 | 576 | bool use_dpencoder; |
496263bf | 577 | struct drm_dp_aux *aux; |
224d94b1 | 578 | }; |
5801ead6 | 579 | |
224d94b1 | 580 | static void radeon_dp_update_vs_emph(struct radeon_dp_link_train_info *dp_info) |
5801ead6 | 581 | { |
224d94b1 AD |
582 | /* set the initial vs/emph on the source */ |
583 | atombios_dig_transmitter_setup(dp_info->encoder, | |
584 | ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH, | |
585 | 0, dp_info->train_set[0]); /* sets all lanes at once */ | |
586 | ||
587 | /* set the vs/emph on the sink */ | |
496263bf AD |
588 | drm_dp_dpcd_write(dp_info->aux, DP_TRAINING_LANE0_SET, |
589 | dp_info->train_set, dp_info->dp_lane_count); | |
5801ead6 AD |
590 | } |
591 | ||
224d94b1 | 592 | static void radeon_dp_set_tp(struct radeon_dp_link_train_info *dp_info, int tp) |
746c1aa4 | 593 | { |
224d94b1 | 594 | int rtp = 0; |
746c1aa4 | 595 | |
224d94b1 | 596 | /* set training pattern on the source */ |
5a96a899 | 597 | if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) { |
224d94b1 AD |
598 | switch (tp) { |
599 | case DP_TRAINING_PATTERN_1: | |
600 | rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1; | |
601 | break; | |
602 | case DP_TRAINING_PATTERN_2: | |
603 | rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2; | |
604 | break; | |
605 | case DP_TRAINING_PATTERN_3: | |
606 | rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3; | |
607 | break; | |
608 | } | |
609 | atombios_dig_encoder_setup(dp_info->encoder, rtp, 0); | |
610 | } else { | |
611 | switch (tp) { | |
612 | case DP_TRAINING_PATTERN_1: | |
613 | rtp = 0; | |
614 | break; | |
615 | case DP_TRAINING_PATTERN_2: | |
616 | rtp = 1; | |
617 | break; | |
618 | } | |
619 | radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_PATTERN_SEL, | |
620 | dp_info->dp_clock, dp_info->enc_id, rtp); | |
621 | } | |
746c1aa4 | 622 | |
224d94b1 | 623 | /* enable training pattern on the sink */ |
496263bf | 624 | drm_dp_dpcd_writeb(dp_info->aux, DP_TRAINING_PATTERN_SET, tp); |
746c1aa4 DA |
625 | } |
626 | ||
224d94b1 | 627 | static int radeon_dp_link_train_init(struct radeon_dp_link_train_info *dp_info) |
5801ead6 | 628 | { |
386d4d75 AD |
629 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(dp_info->encoder); |
630 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; | |
224d94b1 | 631 | u8 tmp; |
5801ead6 | 632 | |
224d94b1 | 633 | /* power up the sink */ |
2953da15 | 634 | radeon_dp_set_rx_power_state(dp_info->connector, DP_SET_POWER_D0); |
224d94b1 AD |
635 | |
636 | /* possibly enable downspread on the sink */ | |
637 | if (dp_info->dpcd[3] & 0x1) | |
496263bf AD |
638 | drm_dp_dpcd_writeb(dp_info->aux, |
639 | DP_DOWNSPREAD_CTRL, DP_SPREAD_AMP_0_5); | |
224d94b1 | 640 | else |
496263bf AD |
641 | drm_dp_dpcd_writeb(dp_info->aux, |
642 | DP_DOWNSPREAD_CTRL, 0); | |
5801ead6 | 643 | |
66c2b84b | 644 | if (dig->panel_mode == DP_PANEL_MODE_INTERNAL_DP2_MODE) |
496263bf | 645 | drm_dp_dpcd_writeb(dp_info->aux, DP_EDP_CONFIGURATION_SET, 1); |
5801ead6 | 646 | |
224d94b1 AD |
647 | /* set the lane count on the sink */ |
648 | tmp = dp_info->dp_lane_count; | |
27f75dc6 | 649 | if (drm_dp_enhanced_frame_cap(dp_info->dpcd)) |
224d94b1 | 650 | tmp |= DP_LANE_COUNT_ENHANCED_FRAME_EN; |
496263bf | 651 | drm_dp_dpcd_writeb(dp_info->aux, DP_LANE_COUNT_SET, tmp); |
5801ead6 | 652 | |
224d94b1 | 653 | /* set the link rate on the sink */ |
3b5c662e | 654 | tmp = drm_dp_link_rate_to_bw_code(dp_info->dp_clock); |
496263bf | 655 | drm_dp_dpcd_writeb(dp_info->aux, DP_LINK_BW_SET, tmp); |
5801ead6 | 656 | |
224d94b1 | 657 | /* start training on the source */ |
5a96a899 | 658 | if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) |
224d94b1 AD |
659 | atombios_dig_encoder_setup(dp_info->encoder, |
660 | ATOM_ENCODER_CMD_DP_LINK_TRAINING_START, 0); | |
5801ead6 | 661 | else |
224d94b1 AD |
662 | radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_START, |
663 | dp_info->dp_clock, dp_info->enc_id, 0); | |
5801ead6 | 664 | |
5801ead6 | 665 | /* disable the training pattern on the sink */ |
496263bf AD |
666 | drm_dp_dpcd_writeb(dp_info->aux, |
667 | DP_TRAINING_PATTERN_SET, | |
668 | DP_TRAINING_PATTERN_DISABLE); | |
224d94b1 AD |
669 | |
670 | return 0; | |
671 | } | |
5801ead6 | 672 | |
224d94b1 AD |
673 | static int radeon_dp_link_train_finish(struct radeon_dp_link_train_info *dp_info) |
674 | { | |
5801ead6 | 675 | udelay(400); |
5801ead6 | 676 | |
224d94b1 | 677 | /* disable the training pattern on the sink */ |
496263bf AD |
678 | drm_dp_dpcd_writeb(dp_info->aux, |
679 | DP_TRAINING_PATTERN_SET, | |
680 | DP_TRAINING_PATTERN_DISABLE); | |
224d94b1 AD |
681 | |
682 | /* disable the training pattern on the source */ | |
5a96a899 | 683 | if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) |
224d94b1 AD |
684 | atombios_dig_encoder_setup(dp_info->encoder, |
685 | ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE, 0); | |
686 | else | |
687 | radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_COMPLETE, | |
688 | dp_info->dp_clock, dp_info->enc_id, 0); | |
689 | ||
690 | return 0; | |
691 | } | |
692 | ||
693 | static int radeon_dp_link_train_cr(struct radeon_dp_link_train_info *dp_info) | |
694 | { | |
695 | bool clock_recovery; | |
696 | u8 voltage; | |
697 | int i; | |
698 | ||
699 | radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_1); | |
700 | memset(dp_info->train_set, 0, 4); | |
701 | radeon_dp_update_vs_emph(dp_info); | |
702 | ||
703 | udelay(400); | |
5fbfce7f | 704 | |
5801ead6 AD |
705 | /* clock recovery loop */ |
706 | clock_recovery = false; | |
224d94b1 | 707 | dp_info->tries = 0; |
5801ead6 | 708 | voltage = 0xff; |
224d94b1 | 709 | while (1) { |
1a644cd4 | 710 | drm_dp_link_train_clock_recovery_delay(dp_info->dpcd); |
224d94b1 | 711 | |
ab8f1a2a AD |
712 | if (drm_dp_dpcd_read_link_status(dp_info->aux, |
713 | dp_info->link_status) <= 0) { | |
8d1c702a | 714 | DRM_ERROR("displayport link status failed\n"); |
5801ead6 | 715 | break; |
8d1c702a | 716 | } |
5801ead6 | 717 | |
01916270 | 718 | if (drm_dp_clock_recovery_ok(dp_info->link_status, dp_info->dp_lane_count)) { |
5801ead6 AD |
719 | clock_recovery = true; |
720 | break; | |
721 | } | |
722 | ||
224d94b1 AD |
723 | for (i = 0; i < dp_info->dp_lane_count; i++) { |
724 | if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) | |
5801ead6 AD |
725 | break; |
726 | } | |
224d94b1 | 727 | if (i == dp_info->dp_lane_count) { |
5801ead6 AD |
728 | DRM_ERROR("clock recovery reached max voltage\n"); |
729 | break; | |
730 | } | |
731 | ||
224d94b1 AD |
732 | if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { |
733 | ++dp_info->tries; | |
734 | if (dp_info->tries == 5) { | |
5801ead6 AD |
735 | DRM_ERROR("clock recovery tried 5 times\n"); |
736 | break; | |
737 | } | |
738 | } else | |
224d94b1 | 739 | dp_info->tries = 0; |
5801ead6 | 740 | |
224d94b1 | 741 | voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; |
5801ead6 AD |
742 | |
743 | /* Compute new train_set as requested by sink */ | |
224d94b1 AD |
744 | dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set); |
745 | ||
746 | radeon_dp_update_vs_emph(dp_info); | |
5801ead6 | 747 | } |
224d94b1 | 748 | if (!clock_recovery) { |
5801ead6 | 749 | DRM_ERROR("clock recovery failed\n"); |
224d94b1 AD |
750 | return -1; |
751 | } else { | |
d9fdaafb | 752 | DRM_DEBUG_KMS("clock recovery at voltage %d pre-emphasis %d\n", |
224d94b1 AD |
753 | dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK, |
754 | (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >> | |
53c1e09f | 755 | DP_TRAIN_PRE_EMPHASIS_SHIFT); |
224d94b1 AD |
756 | return 0; |
757 | } | |
758 | } | |
5801ead6 | 759 | |
224d94b1 AD |
760 | static int radeon_dp_link_train_ce(struct radeon_dp_link_train_info *dp_info) |
761 | { | |
762 | bool channel_eq; | |
5801ead6 | 763 | |
224d94b1 AD |
764 | if (dp_info->tp3_supported) |
765 | radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_3); | |
bcc1c2a1 | 766 | else |
224d94b1 | 767 | radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_2); |
5801ead6 AD |
768 | |
769 | /* channel equalization loop */ | |
224d94b1 | 770 | dp_info->tries = 0; |
5801ead6 | 771 | channel_eq = false; |
224d94b1 | 772 | while (1) { |
1a644cd4 | 773 | drm_dp_link_train_channel_eq_delay(dp_info->dpcd); |
224d94b1 | 774 | |
ab8f1a2a AD |
775 | if (drm_dp_dpcd_read_link_status(dp_info->aux, |
776 | dp_info->link_status) <= 0) { | |
8d1c702a | 777 | DRM_ERROR("displayport link status failed\n"); |
5801ead6 | 778 | break; |
8d1c702a | 779 | } |
5801ead6 | 780 | |
1ffdff13 | 781 | if (drm_dp_channel_eq_ok(dp_info->link_status, dp_info->dp_lane_count)) { |
5801ead6 AD |
782 | channel_eq = true; |
783 | break; | |
784 | } | |
785 | ||
786 | /* Try 5 times */ | |
224d94b1 | 787 | if (dp_info->tries > 5) { |
5801ead6 AD |
788 | DRM_ERROR("channel eq failed: 5 tries\n"); |
789 | break; | |
790 | } | |
791 | ||
792 | /* Compute new train_set as requested by sink */ | |
224d94b1 | 793 | dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set); |
5801ead6 | 794 | |
224d94b1 AD |
795 | radeon_dp_update_vs_emph(dp_info); |
796 | dp_info->tries++; | |
5801ead6 AD |
797 | } |
798 | ||
224d94b1 | 799 | if (!channel_eq) { |
5801ead6 | 800 | DRM_ERROR("channel eq failed\n"); |
224d94b1 AD |
801 | return -1; |
802 | } else { | |
d9fdaafb | 803 | DRM_DEBUG_KMS("channel eq at voltage %d pre-emphasis %d\n", |
224d94b1 AD |
804 | dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK, |
805 | (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) | |
53c1e09f | 806 | >> DP_TRAIN_PRE_EMPHASIS_SHIFT); |
224d94b1 AD |
807 | return 0; |
808 | } | |
5801ead6 AD |
809 | } |
810 | ||
224d94b1 AD |
811 | void radeon_dp_link_train(struct drm_encoder *encoder, |
812 | struct drm_connector *connector) | |
746c1aa4 | 813 | { |
224d94b1 AD |
814 | struct drm_device *dev = encoder->dev; |
815 | struct radeon_device *rdev = dev->dev_private; | |
816 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
817 | struct radeon_encoder_atom_dig *dig; | |
818 | struct radeon_connector *radeon_connector; | |
819 | struct radeon_connector_atom_dig *dig_connector; | |
820 | struct radeon_dp_link_train_info dp_info; | |
5a96a899 JG |
821 | int index; |
822 | u8 tmp, frev, crev; | |
746c1aa4 | 823 | |
224d94b1 AD |
824 | if (!radeon_encoder->enc_priv) |
825 | return; | |
826 | dig = radeon_encoder->enc_priv; | |
746c1aa4 | 827 | |
224d94b1 AD |
828 | radeon_connector = to_radeon_connector(connector); |
829 | if (!radeon_connector->con_priv) | |
830 | return; | |
831 | dig_connector = radeon_connector->con_priv; | |
834b2904 | 832 | |
224d94b1 AD |
833 | if ((dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) && |
834 | (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_eDP)) | |
835 | return; | |
746c1aa4 | 836 | |
5a96a899 JG |
837 | /* DPEncoderService newer than 1.1 can't program properly the |
838 | * training pattern. When facing such version use the | |
839 | * DIGXEncoderControl (X== 1 | 2) | |
840 | */ | |
841 | dp_info.use_dpencoder = true; | |
842 | index = GetIndexIntoMasterTable(COMMAND, DPEncoderService); | |
843 | if (atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) { | |
844 | if (crev > 1) { | |
845 | dp_info.use_dpencoder = false; | |
846 | } | |
847 | } | |
848 | ||
224d94b1 AD |
849 | dp_info.enc_id = 0; |
850 | if (dig->dig_encoder) | |
851 | dp_info.enc_id |= ATOM_DP_CONFIG_DIG2_ENCODER; | |
852 | else | |
853 | dp_info.enc_id |= ATOM_DP_CONFIG_DIG1_ENCODER; | |
854 | if (dig->linkb) | |
855 | dp_info.enc_id |= ATOM_DP_CONFIG_LINK_B; | |
856 | else | |
857 | dp_info.enc_id |= ATOM_DP_CONFIG_LINK_A; | |
834b2904 | 858 | |
aa019b79 AD |
859 | if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux, DP_MAX_LANE_COUNT, &tmp) |
860 | == 1) { | |
861 | if (ASIC_IS_DCE5(rdev) && (tmp & DP_TPS3_SUPPORTED)) | |
862 | dp_info.tp3_supported = true; | |
863 | else | |
864 | dp_info.tp3_supported = false; | |
865 | } else { | |
224d94b1 | 866 | dp_info.tp3_supported = false; |
aa019b79 | 867 | } |
224d94b1 | 868 | |
1a644cd4 | 869 | memcpy(dp_info.dpcd, dig_connector->dpcd, DP_RECEIVER_CAP_SIZE); |
224d94b1 AD |
870 | dp_info.rdev = rdev; |
871 | dp_info.encoder = encoder; | |
872 | dp_info.connector = connector; | |
224d94b1 AD |
873 | dp_info.dp_lane_count = dig_connector->dp_lane_count; |
874 | dp_info.dp_clock = dig_connector->dp_clock; | |
379dfc25 | 875 | dp_info.aux = &radeon_connector->ddc_bus->aux; |
224d94b1 AD |
876 | |
877 | if (radeon_dp_link_train_init(&dp_info)) | |
878 | goto done; | |
879 | if (radeon_dp_link_train_cr(&dp_info)) | |
880 | goto done; | |
881 | if (radeon_dp_link_train_ce(&dp_info)) | |
882 | goto done; | |
883 | done: | |
884 | if (radeon_dp_link_train_finish(&dp_info)) | |
885 | return; | |
746c1aa4 | 886 | } |