Commit | Line | Data |
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3f03ced8 AD |
1 | /* |
2 | * Copyright 2007-11 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice shall be included in | |
13 | * all copies or substantial portions of the Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
21 | * OTHER DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: Dave Airlie | |
24 | * Alex Deucher | |
25 | */ | |
760285e7 DH |
26 | #include <drm/drmP.h> |
27 | #include <drm/drm_crtc_helper.h> | |
28 | #include <drm/radeon_drm.h> | |
3f03ced8 | 29 | #include "radeon.h" |
6e72376d | 30 | #include "radeon_audio.h" |
3f03ced8 | 31 | #include "atom.h" |
f3728734 | 32 | #include <linux/backlight.h> |
3f03ced8 AD |
33 | |
34 | extern int atom_debug; | |
35 | ||
f3728734 AD |
36 | static u8 |
37 | radeon_atom_get_backlight_level_from_reg(struct radeon_device *rdev) | |
38 | { | |
39 | u8 backlight_level; | |
40 | u32 bios_2_scratch; | |
41 | ||
42 | if (rdev->family >= CHIP_R600) | |
43 | bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH); | |
44 | else | |
45 | bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH); | |
46 | ||
47 | backlight_level = ((bios_2_scratch & ATOM_S2_CURRENT_BL_LEVEL_MASK) >> | |
48 | ATOM_S2_CURRENT_BL_LEVEL_SHIFT); | |
49 | ||
50 | return backlight_level; | |
51 | } | |
52 | ||
53 | static void | |
54 | radeon_atom_set_backlight_level_to_reg(struct radeon_device *rdev, | |
55 | u8 backlight_level) | |
56 | { | |
57 | u32 bios_2_scratch; | |
58 | ||
59 | if (rdev->family >= CHIP_R600) | |
60 | bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH); | |
61 | else | |
62 | bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH); | |
63 | ||
64 | bios_2_scratch &= ~ATOM_S2_CURRENT_BL_LEVEL_MASK; | |
65 | bios_2_scratch |= ((backlight_level << ATOM_S2_CURRENT_BL_LEVEL_SHIFT) & | |
66 | ATOM_S2_CURRENT_BL_LEVEL_MASK); | |
67 | ||
68 | if (rdev->family >= CHIP_R600) | |
69 | WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch); | |
70 | else | |
71 | WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch); | |
72 | } | |
73 | ||
6d92f81d AD |
74 | u8 |
75 | atombios_get_backlight_level(struct radeon_encoder *radeon_encoder) | |
76 | { | |
77 | struct drm_device *dev = radeon_encoder->base.dev; | |
78 | struct radeon_device *rdev = dev->dev_private; | |
79 | ||
80 | if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) | |
81 | return 0; | |
82 | ||
83 | return radeon_atom_get_backlight_level_from_reg(rdev); | |
84 | } | |
85 | ||
fda4b25c | 86 | void |
37e9b6a6 | 87 | atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level) |
f3728734 AD |
88 | { |
89 | struct drm_encoder *encoder = &radeon_encoder->base; | |
90 | struct drm_device *dev = radeon_encoder->base.dev; | |
91 | struct radeon_device *rdev = dev->dev_private; | |
92 | struct radeon_encoder_atom_dig *dig; | |
93 | DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args; | |
94 | int index; | |
95 | ||
37e9b6a6 AD |
96 | if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) |
97 | return; | |
98 | ||
99 | if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) && | |
100 | radeon_encoder->enc_priv) { | |
f3728734 | 101 | dig = radeon_encoder->enc_priv; |
37e9b6a6 | 102 | dig->backlight_level = level; |
f3728734 AD |
103 | radeon_atom_set_backlight_level_to_reg(rdev, dig->backlight_level); |
104 | ||
105 | switch (radeon_encoder->encoder_id) { | |
106 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: | |
107 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: | |
108 | index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); | |
109 | if (dig->backlight_level == 0) { | |
110 | args.ucAction = ATOM_LCD_BLOFF; | |
111 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
112 | } else { | |
113 | args.ucAction = ATOM_LCD_BL_BRIGHTNESS_CONTROL; | |
114 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
115 | args.ucAction = ATOM_LCD_BLON; | |
116 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
117 | } | |
118 | break; | |
119 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: | |
120 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: | |
121 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: | |
122 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: | |
123 | if (dig->backlight_level == 0) | |
124 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0); | |
125 | else { | |
126 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL, 0, 0); | |
127 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0); | |
128 | } | |
129 | break; | |
130 | default: | |
131 | break; | |
132 | } | |
133 | } | |
134 | } | |
135 | ||
bced76f2 AD |
136 | #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) |
137 | ||
f3728734 AD |
138 | static u8 radeon_atom_bl_level(struct backlight_device *bd) |
139 | { | |
140 | u8 level; | |
141 | ||
142 | /* Convert brightness to hardware level */ | |
143 | if (bd->props.brightness < 0) | |
144 | level = 0; | |
145 | else if (bd->props.brightness > RADEON_MAX_BL_LEVEL) | |
146 | level = RADEON_MAX_BL_LEVEL; | |
147 | else | |
148 | level = bd->props.brightness; | |
149 | ||
150 | return level; | |
151 | } | |
152 | ||
153 | static int radeon_atom_backlight_update_status(struct backlight_device *bd) | |
154 | { | |
155 | struct radeon_backlight_privdata *pdata = bl_get_data(bd); | |
156 | struct radeon_encoder *radeon_encoder = pdata->encoder; | |
157 | ||
37e9b6a6 | 158 | atombios_set_backlight_level(radeon_encoder, radeon_atom_bl_level(bd)); |
f3728734 AD |
159 | |
160 | return 0; | |
161 | } | |
162 | ||
163 | static int radeon_atom_backlight_get_brightness(struct backlight_device *bd) | |
164 | { | |
165 | struct radeon_backlight_privdata *pdata = bl_get_data(bd); | |
166 | struct radeon_encoder *radeon_encoder = pdata->encoder; | |
167 | struct drm_device *dev = radeon_encoder->base.dev; | |
168 | struct radeon_device *rdev = dev->dev_private; | |
169 | ||
170 | return radeon_atom_get_backlight_level_from_reg(rdev); | |
171 | } | |
172 | ||
173 | static const struct backlight_ops radeon_atom_backlight_ops = { | |
174 | .get_brightness = radeon_atom_backlight_get_brightness, | |
175 | .update_status = radeon_atom_backlight_update_status, | |
176 | }; | |
177 | ||
178 | void radeon_atom_backlight_init(struct radeon_encoder *radeon_encoder, | |
179 | struct drm_connector *drm_connector) | |
180 | { | |
181 | struct drm_device *dev = radeon_encoder->base.dev; | |
182 | struct radeon_device *rdev = dev->dev_private; | |
183 | struct backlight_device *bd; | |
184 | struct backlight_properties props; | |
185 | struct radeon_backlight_privdata *pdata; | |
186 | struct radeon_encoder_atom_dig *dig; | |
614499b4 | 187 | char bl_name[16]; |
f3728734 | 188 | |
80101790 AD |
189 | /* Mac laptops with multiple GPUs use the gmux driver for backlight |
190 | * so don't register a backlight device | |
191 | */ | |
192 | if ((rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) && | |
193 | (rdev->pdev->device == 0x6741)) | |
194 | return; | |
195 | ||
f3728734 AD |
196 | if (!radeon_encoder->enc_priv) |
197 | return; | |
198 | ||
199 | if (!rdev->is_atom_bios) | |
200 | return; | |
201 | ||
202 | if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) | |
203 | return; | |
204 | ||
205 | pdata = kmalloc(sizeof(struct radeon_backlight_privdata), GFP_KERNEL); | |
206 | if (!pdata) { | |
207 | DRM_ERROR("Memory allocation failed\n"); | |
208 | goto error; | |
209 | } | |
210 | ||
211 | memset(&props, 0, sizeof(props)); | |
212 | props.max_brightness = RADEON_MAX_BL_LEVEL; | |
213 | props.type = BACKLIGHT_RAW; | |
614499b4 AD |
214 | snprintf(bl_name, sizeof(bl_name), |
215 | "radeon_bl%d", dev->primary->index); | |
5bdebb18 | 216 | bd = backlight_device_register(bl_name, drm_connector->kdev, |
f3728734 AD |
217 | pdata, &radeon_atom_backlight_ops, &props); |
218 | if (IS_ERR(bd)) { | |
219 | DRM_ERROR("Backlight registration failed\n"); | |
220 | goto error; | |
221 | } | |
222 | ||
223 | pdata->encoder = radeon_encoder; | |
224 | ||
f3728734 AD |
225 | dig = radeon_encoder->enc_priv; |
226 | dig->bl_dev = bd; | |
227 | ||
228 | bd->props.brightness = radeon_atom_backlight_get_brightness(bd); | |
201bb624 AD |
229 | /* Set a reasonable default here if the level is 0 otherwise |
230 | * fbdev will attempt to turn the backlight on after console | |
231 | * unblanking and it will try and restore 0 which turns the backlight | |
232 | * off again. | |
233 | */ | |
234 | if (bd->props.brightness == 0) | |
235 | bd->props.brightness = RADEON_MAX_BL_LEVEL; | |
f3728734 AD |
236 | bd->props.power = FB_BLANK_UNBLANK; |
237 | backlight_update_status(bd); | |
238 | ||
239 | DRM_INFO("radeon atom DIG backlight initialized\n"); | |
4cee6a90 | 240 | rdev->mode_info.bl_encoder = radeon_encoder; |
f3728734 AD |
241 | |
242 | return; | |
243 | ||
244 | error: | |
245 | kfree(pdata); | |
246 | return; | |
247 | } | |
248 | ||
249 | static void radeon_atom_backlight_exit(struct radeon_encoder *radeon_encoder) | |
250 | { | |
251 | struct drm_device *dev = radeon_encoder->base.dev; | |
252 | struct radeon_device *rdev = dev->dev_private; | |
253 | struct backlight_device *bd = NULL; | |
254 | struct radeon_encoder_atom_dig *dig; | |
255 | ||
256 | if (!radeon_encoder->enc_priv) | |
257 | return; | |
258 | ||
259 | if (!rdev->is_atom_bios) | |
260 | return; | |
261 | ||
262 | if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) | |
263 | return; | |
264 | ||
265 | dig = radeon_encoder->enc_priv; | |
266 | bd = dig->bl_dev; | |
267 | dig->bl_dev = NULL; | |
268 | ||
269 | if (bd) { | |
270 | struct radeon_legacy_backlight_privdata *pdata; | |
271 | ||
272 | pdata = bl_get_data(bd); | |
273 | backlight_device_unregister(bd); | |
274 | kfree(pdata); | |
275 | ||
276 | DRM_INFO("radeon atom LVDS backlight unloaded\n"); | |
277 | } | |
278 | } | |
279 | ||
280 | #else /* !CONFIG_BACKLIGHT_CLASS_DEVICE */ | |
281 | ||
282 | void radeon_atom_backlight_init(struct radeon_encoder *encoder) | |
283 | { | |
284 | } | |
285 | ||
286 | static void radeon_atom_backlight_exit(struct radeon_encoder *encoder) | |
287 | { | |
288 | } | |
289 | ||
290 | #endif | |
291 | ||
3f03ced8 AD |
292 | /* evil but including atombios.h is much worse */ |
293 | bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index, | |
294 | struct drm_display_mode *mode); | |
295 | ||
3f03ced8 | 296 | static bool radeon_atom_mode_fixup(struct drm_encoder *encoder, |
e811f5ae | 297 | const struct drm_display_mode *mode, |
3f03ced8 AD |
298 | struct drm_display_mode *adjusted_mode) |
299 | { | |
300 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
301 | struct drm_device *dev = encoder->dev; | |
302 | struct radeon_device *rdev = dev->dev_private; | |
303 | ||
304 | /* set the active encoder to connector routing */ | |
305 | radeon_encoder_set_active_device(encoder); | |
306 | drm_mode_set_crtcinfo(adjusted_mode, 0); | |
307 | ||
308 | /* hw bug */ | |
309 | if ((mode->flags & DRM_MODE_FLAG_INTERLACE) | |
310 | && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2))) | |
311 | adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2; | |
312 | ||
3104b812 AD |
313 | /* vertical FP must be at least 1 */ |
314 | if (mode->crtc_vsync_start == mode->crtc_vdisplay) | |
315 | adjusted_mode->crtc_vsync_start++; | |
316 | ||
da997620 AD |
317 | /* get the native mode for scaling */ |
318 | if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) { | |
3f03ced8 | 319 | radeon_panel_mode_fixup(encoder, adjusted_mode); |
da997620 | 320 | } else if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) { |
3f03ced8 AD |
321 | struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv; |
322 | if (tv_dac) { | |
323 | if (tv_dac->tv_std == TV_STD_NTSC || | |
324 | tv_dac->tv_std == TV_STD_NTSC_J || | |
325 | tv_dac->tv_std == TV_STD_PAL_M) | |
326 | radeon_atom_get_tv_timings(rdev, 0, adjusted_mode); | |
327 | else | |
328 | radeon_atom_get_tv_timings(rdev, 1, adjusted_mode); | |
329 | } | |
da997620 AD |
330 | } else if (radeon_encoder->rmx_type != RMX_OFF) { |
331 | radeon_panel_mode_fixup(encoder, adjusted_mode); | |
3f03ced8 AD |
332 | } |
333 | ||
334 | if (ASIC_IS_DCE3(rdev) && | |
335 | ((radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) || | |
336 | (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE))) { | |
337 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); | |
93927f9c | 338 | radeon_dp_set_link_config(connector, adjusted_mode); |
3f03ced8 AD |
339 | } |
340 | ||
341 | return true; | |
342 | } | |
343 | ||
344 | static void | |
345 | atombios_dac_setup(struct drm_encoder *encoder, int action) | |
346 | { | |
347 | struct drm_device *dev = encoder->dev; | |
348 | struct radeon_device *rdev = dev->dev_private; | |
349 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
350 | DAC_ENCODER_CONTROL_PS_ALLOCATION args; | |
351 | int index = 0; | |
352 | struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv; | |
353 | ||
354 | memset(&args, 0, sizeof(args)); | |
355 | ||
356 | switch (radeon_encoder->encoder_id) { | |
357 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: | |
358 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: | |
359 | index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl); | |
360 | break; | |
361 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: | |
362 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: | |
363 | index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl); | |
364 | break; | |
365 | } | |
366 | ||
367 | args.ucAction = action; | |
368 | ||
369 | if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT)) | |
370 | args.ucDacStandard = ATOM_DAC1_PS2; | |
371 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) | |
372 | args.ucDacStandard = ATOM_DAC1_CV; | |
373 | else { | |
374 | switch (dac_info->tv_std) { | |
375 | case TV_STD_PAL: | |
376 | case TV_STD_PAL_M: | |
377 | case TV_STD_SCART_PAL: | |
378 | case TV_STD_SECAM: | |
379 | case TV_STD_PAL_CN: | |
380 | args.ucDacStandard = ATOM_DAC1_PAL; | |
381 | break; | |
382 | case TV_STD_NTSC: | |
383 | case TV_STD_NTSC_J: | |
384 | case TV_STD_PAL_60: | |
385 | default: | |
386 | args.ucDacStandard = ATOM_DAC1_NTSC; | |
387 | break; | |
388 | } | |
389 | } | |
390 | args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); | |
391 | ||
392 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
393 | ||
394 | } | |
395 | ||
396 | static void | |
397 | atombios_tv_setup(struct drm_encoder *encoder, int action) | |
398 | { | |
399 | struct drm_device *dev = encoder->dev; | |
400 | struct radeon_device *rdev = dev->dev_private; | |
401 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
402 | TV_ENCODER_CONTROL_PS_ALLOCATION args; | |
403 | int index = 0; | |
404 | struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv; | |
405 | ||
406 | memset(&args, 0, sizeof(args)); | |
407 | ||
408 | index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl); | |
409 | ||
410 | args.sTVEncoder.ucAction = action; | |
411 | ||
412 | if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) | |
413 | args.sTVEncoder.ucTvStandard = ATOM_TV_CV; | |
414 | else { | |
415 | switch (dac_info->tv_std) { | |
416 | case TV_STD_NTSC: | |
417 | args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC; | |
418 | break; | |
419 | case TV_STD_PAL: | |
420 | args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; | |
421 | break; | |
422 | case TV_STD_PAL_M: | |
423 | args.sTVEncoder.ucTvStandard = ATOM_TV_PALM; | |
424 | break; | |
425 | case TV_STD_PAL_60: | |
426 | args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60; | |
427 | break; | |
428 | case TV_STD_NTSC_J: | |
429 | args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ; | |
430 | break; | |
431 | case TV_STD_SCART_PAL: | |
432 | args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */ | |
433 | break; | |
434 | case TV_STD_SECAM: | |
435 | args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM; | |
436 | break; | |
437 | case TV_STD_PAL_CN: | |
438 | args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN; | |
439 | break; | |
440 | default: | |
441 | args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC; | |
442 | break; | |
443 | } | |
444 | } | |
445 | ||
446 | args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); | |
447 | ||
448 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
449 | ||
450 | } | |
451 | ||
1f0e2943 AD |
452 | static u8 radeon_atom_get_bpc(struct drm_encoder *encoder) |
453 | { | |
1f0e2943 AD |
454 | int bpc = 8; |
455 | ||
7d5a33b0 AD |
456 | if (encoder->crtc) { |
457 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); | |
458 | bpc = radeon_crtc->bpc; | |
459 | } | |
1f0e2943 AD |
460 | |
461 | switch (bpc) { | |
462 | case 0: | |
463 | return PANEL_BPC_UNDEFINE; | |
464 | case 6: | |
465 | return PANEL_6BIT_PER_COLOR; | |
466 | case 8: | |
467 | default: | |
468 | return PANEL_8BIT_PER_COLOR; | |
469 | case 10: | |
470 | return PANEL_10BIT_PER_COLOR; | |
471 | case 12: | |
472 | return PANEL_12BIT_PER_COLOR; | |
473 | case 16: | |
474 | return PANEL_16BIT_PER_COLOR; | |
475 | } | |
476 | } | |
477 | ||
3f03ced8 AD |
478 | union dvo_encoder_control { |
479 | ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds; | |
480 | DVO_ENCODER_CONTROL_PS_ALLOCATION dvo; | |
481 | DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3; | |
aea65641 | 482 | DVO_ENCODER_CONTROL_PS_ALLOCATION_V1_4 dvo_v4; |
3f03ced8 AD |
483 | }; |
484 | ||
485 | void | |
486 | atombios_dvo_setup(struct drm_encoder *encoder, int action) | |
487 | { | |
488 | struct drm_device *dev = encoder->dev; | |
489 | struct radeon_device *rdev = dev->dev_private; | |
490 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
491 | union dvo_encoder_control args; | |
492 | int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl); | |
24153dd3 | 493 | uint8_t frev, crev; |
3f03ced8 AD |
494 | |
495 | memset(&args, 0, sizeof(args)); | |
496 | ||
24153dd3 AD |
497 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) |
498 | return; | |
499 | ||
afceb931 AD |
500 | /* some R4xx chips have the wrong frev */ |
501 | if (rdev->family <= CHIP_RV410) | |
502 | frev = 1; | |
503 | ||
24153dd3 AD |
504 | switch (frev) { |
505 | case 1: | |
506 | switch (crev) { | |
507 | case 1: | |
508 | /* R4xx, R5xx */ | |
509 | args.ext_tmds.sXTmdsEncoder.ucEnable = action; | |
510 | ||
9aa59993 | 511 | if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
24153dd3 AD |
512 | args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL; |
513 | ||
514 | args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB; | |
515 | break; | |
516 | case 2: | |
517 | /* RS600/690/740 */ | |
518 | args.dvo.sDVOEncoder.ucAction = action; | |
519 | args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); | |
520 | /* DFP1, CRT1, TV1 depending on the type of port */ | |
521 | args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX; | |
522 | ||
9aa59993 | 523 | if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
24153dd3 AD |
524 | args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL; |
525 | break; | |
526 | case 3: | |
527 | /* R6xx */ | |
528 | args.dvo_v3.ucAction = action; | |
529 | args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); | |
530 | args.dvo_v3.ucDVOConfig = 0; /* XXX */ | |
531 | break; | |
aea65641 AD |
532 | case 4: |
533 | /* DCE8 */ | |
534 | args.dvo_v4.ucAction = action; | |
535 | args.dvo_v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); | |
536 | args.dvo_v4.ucDVOConfig = 0; /* XXX */ | |
537 | args.dvo_v4.ucBitPerColor = radeon_atom_get_bpc(encoder); | |
538 | break; | |
24153dd3 AD |
539 | default: |
540 | DRM_ERROR("Unknown table version %d, %d\n", frev, crev); | |
541 | break; | |
542 | } | |
543 | break; | |
544 | default: | |
545 | DRM_ERROR("Unknown table version %d, %d\n", frev, crev); | |
546 | break; | |
3f03ced8 AD |
547 | } |
548 | ||
549 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
550 | } | |
551 | ||
552 | union lvds_encoder_control { | |
553 | LVDS_ENCODER_CONTROL_PS_ALLOCATION v1; | |
554 | LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2; | |
555 | }; | |
556 | ||
557 | void | |
558 | atombios_digital_setup(struct drm_encoder *encoder, int action) | |
559 | { | |
560 | struct drm_device *dev = encoder->dev; | |
561 | struct radeon_device *rdev = dev->dev_private; | |
562 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
563 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; | |
564 | union lvds_encoder_control args; | |
565 | int index = 0; | |
566 | int hdmi_detected = 0; | |
567 | uint8_t frev, crev; | |
568 | ||
569 | if (!dig) | |
570 | return; | |
571 | ||
572 | if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) | |
573 | hdmi_detected = 1; | |
574 | ||
575 | memset(&args, 0, sizeof(args)); | |
576 | ||
577 | switch (radeon_encoder->encoder_id) { | |
578 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: | |
579 | index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl); | |
580 | break; | |
581 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: | |
582 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: | |
583 | index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl); | |
584 | break; | |
585 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: | |
586 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) | |
587 | index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl); | |
588 | else | |
589 | index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl); | |
590 | break; | |
591 | } | |
592 | ||
593 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) | |
594 | return; | |
595 | ||
596 | switch (frev) { | |
597 | case 1: | |
598 | case 2: | |
599 | switch (crev) { | |
600 | case 1: | |
601 | args.v1.ucMisc = 0; | |
602 | args.v1.ucAction = action; | |
603 | if (hdmi_detected) | |
604 | args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE; | |
605 | args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); | |
606 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { | |
607 | if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL) | |
608 | args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL; | |
609 | if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB) | |
610 | args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB; | |
611 | } else { | |
612 | if (dig->linkb) | |
613 | args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB; | |
9aa59993 | 614 | if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
3f03ced8 AD |
615 | args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL; |
616 | /*if (pScrn->rgbBits == 8) */ | |
617 | args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB; | |
618 | } | |
619 | break; | |
620 | case 2: | |
621 | case 3: | |
622 | args.v2.ucMisc = 0; | |
623 | args.v2.ucAction = action; | |
624 | if (crev == 3) { | |
625 | if (dig->coherent_mode) | |
626 | args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT; | |
627 | } | |
628 | if (hdmi_detected) | |
629 | args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE; | |
630 | args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); | |
631 | args.v2.ucTruncate = 0; | |
632 | args.v2.ucSpatial = 0; | |
633 | args.v2.ucTemporal = 0; | |
634 | args.v2.ucFRC = 0; | |
635 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { | |
636 | if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL) | |
637 | args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL; | |
638 | if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) { | |
639 | args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN; | |
640 | if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB) | |
641 | args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH; | |
642 | } | |
643 | if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) { | |
644 | args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN; | |
645 | if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB) | |
646 | args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH; | |
647 | if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2) | |
648 | args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4; | |
649 | } | |
650 | } else { | |
651 | if (dig->linkb) | |
652 | args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB; | |
9aa59993 | 653 | if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
3f03ced8 AD |
654 | args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL; |
655 | } | |
656 | break; | |
657 | default: | |
658 | DRM_ERROR("Unknown table version %d, %d\n", frev, crev); | |
659 | break; | |
660 | } | |
661 | break; | |
662 | default: | |
663 | DRM_ERROR("Unknown table version %d, %d\n", frev, crev); | |
664 | break; | |
665 | } | |
666 | ||
667 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
668 | } | |
669 | ||
670 | int | |
671 | atombios_get_encoder_mode(struct drm_encoder *encoder) | |
672 | { | |
e55bca26 SG |
673 | struct drm_device *dev = encoder->dev; |
674 | struct radeon_device *rdev = dev->dev_private; | |
3f03ced8 | 675 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
3f03ced8 AD |
676 | struct drm_connector *connector; |
677 | struct radeon_connector *radeon_connector; | |
678 | struct radeon_connector_atom_dig *dig_connector; | |
9843ead0 | 679 | struct radeon_encoder_atom_dig *dig_enc; |
3f03ced8 | 680 | |
9843ead0 DA |
681 | if (radeon_encoder_is_digital(encoder)) { |
682 | dig_enc = radeon_encoder->enc_priv; | |
683 | if (dig_enc->active_mst_links) | |
684 | return ATOM_ENCODER_MODE_DP_MST; | |
685 | } | |
686 | if (radeon_encoder->is_mst_encoder || radeon_encoder->offset) | |
687 | return ATOM_ENCODER_MODE_DP_MST; | |
3f03ced8 AD |
688 | /* dp bridges are always DP */ |
689 | if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) | |
690 | return ATOM_ENCODER_MODE_DP; | |
691 | ||
692 | /* DVO is always DVO */ | |
a59fbb8e AD |
693 | if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DVO1) || |
694 | (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)) | |
3f03ced8 AD |
695 | return ATOM_ENCODER_MODE_DVO; |
696 | ||
697 | connector = radeon_get_connector_for_encoder(encoder); | |
698 | /* if we don't have an active device yet, just use one of | |
699 | * the connectors tied to the encoder. | |
700 | */ | |
701 | if (!connector) | |
702 | connector = radeon_get_connector_for_encoder_init(encoder); | |
703 | radeon_connector = to_radeon_connector(connector); | |
704 | ||
705 | switch (connector->connector_type) { | |
706 | case DRM_MODE_CONNECTOR_DVII: | |
707 | case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */ | |
108dc8e8 AD |
708 | if (radeon_audio != 0) { |
709 | if (radeon_connector->use_digital && | |
710 | (radeon_connector->audio == RADEON_AUDIO_ENABLE)) | |
711 | return ATOM_ENCODER_MODE_HDMI; | |
377bd8a9 | 712 | else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) && |
108dc8e8 AD |
713 | (radeon_connector->audio == RADEON_AUDIO_AUTO)) |
714 | return ATOM_ENCODER_MODE_HDMI; | |
715 | else if (radeon_connector->use_digital) | |
716 | return ATOM_ENCODER_MODE_DVI; | |
717 | else | |
718 | return ATOM_ENCODER_MODE_CRT; | |
719 | } else if (radeon_connector->use_digital) { | |
3f03ced8 | 720 | return ATOM_ENCODER_MODE_DVI; |
108dc8e8 | 721 | } else { |
3f03ced8 | 722 | return ATOM_ENCODER_MODE_CRT; |
108dc8e8 | 723 | } |
3f03ced8 AD |
724 | break; |
725 | case DRM_MODE_CONNECTOR_DVID: | |
726 | case DRM_MODE_CONNECTOR_HDMIA: | |
727 | default: | |
108dc8e8 AD |
728 | if (radeon_audio != 0) { |
729 | if (radeon_connector->audio == RADEON_AUDIO_ENABLE) | |
730 | return ATOM_ENCODER_MODE_HDMI; | |
377bd8a9 | 731 | else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) && |
108dc8e8 AD |
732 | (radeon_connector->audio == RADEON_AUDIO_AUTO)) |
733 | return ATOM_ENCODER_MODE_HDMI; | |
734 | else | |
735 | return ATOM_ENCODER_MODE_DVI; | |
736 | } else { | |
3f03ced8 | 737 | return ATOM_ENCODER_MODE_DVI; |
108dc8e8 | 738 | } |
3f03ced8 AD |
739 | break; |
740 | case DRM_MODE_CONNECTOR_LVDS: | |
741 | return ATOM_ENCODER_MODE_LVDS; | |
742 | break; | |
743 | case DRM_MODE_CONNECTOR_DisplayPort: | |
744 | dig_connector = radeon_connector->con_priv; | |
745 | if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || | |
108dc8e8 | 746 | (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) { |
3473f542 AD |
747 | if (radeon_audio != 0 && |
748 | drm_detect_monitor_audio(radeon_connector_edid(connector)) && | |
749 | ASIC_IS_DCE4(rdev) && !ASIC_IS_DCE5(rdev)) | |
e55bca26 | 750 | return ATOM_ENCODER_MODE_DP_AUDIO; |
3f03ced8 | 751 | return ATOM_ENCODER_MODE_DP; |
108dc8e8 AD |
752 | } else if (radeon_audio != 0) { |
753 | if (radeon_connector->audio == RADEON_AUDIO_ENABLE) | |
754 | return ATOM_ENCODER_MODE_HDMI; | |
377bd8a9 | 755 | else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) && |
108dc8e8 AD |
756 | (radeon_connector->audio == RADEON_AUDIO_AUTO)) |
757 | return ATOM_ENCODER_MODE_HDMI; | |
758 | else | |
759 | return ATOM_ENCODER_MODE_DVI; | |
760 | } else { | |
3f03ced8 | 761 | return ATOM_ENCODER_MODE_DVI; |
108dc8e8 | 762 | } |
3f03ced8 AD |
763 | break; |
764 | case DRM_MODE_CONNECTOR_eDP: | |
3473f542 AD |
765 | if (radeon_audio != 0 && |
766 | drm_detect_monitor_audio(radeon_connector_edid(connector)) && | |
767 | ASIC_IS_DCE4(rdev) && !ASIC_IS_DCE5(rdev)) | |
e55bca26 | 768 | return ATOM_ENCODER_MODE_DP_AUDIO; |
3f03ced8 AD |
769 | return ATOM_ENCODER_MODE_DP; |
770 | case DRM_MODE_CONNECTOR_DVIA: | |
771 | case DRM_MODE_CONNECTOR_VGA: | |
772 | return ATOM_ENCODER_MODE_CRT; | |
773 | break; | |
774 | case DRM_MODE_CONNECTOR_Composite: | |
775 | case DRM_MODE_CONNECTOR_SVIDEO: | |
776 | case DRM_MODE_CONNECTOR_9PinDIN: | |
777 | /* fix me */ | |
778 | return ATOM_ENCODER_MODE_TV; | |
779 | /*return ATOM_ENCODER_MODE_CV;*/ | |
780 | break; | |
781 | } | |
782 | } | |
783 | ||
784 | /* | |
785 | * DIG Encoder/Transmitter Setup | |
786 | * | |
787 | * DCE 3.0/3.1 | |
788 | * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA. | |
789 | * Supports up to 3 digital outputs | |
790 | * - 2 DIG encoder blocks. | |
791 | * DIG1 can drive UNIPHY link A or link B | |
792 | * DIG2 can drive UNIPHY link B or LVTMA | |
793 | * | |
794 | * DCE 3.2 | |
795 | * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B). | |
796 | * Supports up to 5 digital outputs | |
797 | * - 2 DIG encoder blocks. | |
798 | * DIG1/2 can drive UNIPHY0/1/2 link A or link B | |
799 | * | |
2d415869 | 800 | * DCE 4.0/5.0/6.0 |
3f03ced8 AD |
801 | * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B). |
802 | * Supports up to 6 digital outputs | |
803 | * - 6 DIG encoder blocks. | |
804 | * - DIG to PHY mapping is hardcoded | |
805 | * DIG1 drives UNIPHY0 link A, A+B | |
806 | * DIG2 drives UNIPHY0 link B | |
807 | * DIG3 drives UNIPHY1 link A, A+B | |
808 | * DIG4 drives UNIPHY1 link B | |
809 | * DIG5 drives UNIPHY2 link A, A+B | |
810 | * DIG6 drives UNIPHY2 link B | |
811 | * | |
812 | * DCE 4.1 | |
813 | * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B). | |
814 | * Supports up to 6 digital outputs | |
815 | * - 2 DIG encoder blocks. | |
2d415869 | 816 | * llano |
3f03ced8 | 817 | * DIG1/2 can drive UNIPHY0/1/2 link A or link B |
2d415869 AD |
818 | * ontario |
819 | * DIG1 drives UNIPHY0/1/2 link A | |
820 | * DIG2 drives UNIPHY0/1/2 link B | |
3f03ced8 AD |
821 | * |
822 | * Routing | |
823 | * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links) | |
824 | * Examples: | |
825 | * crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI | |
826 | * crtc1 -> dig1 -> UNIPHY0 link B -> DP | |
827 | * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS | |
828 | * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI | |
829 | */ | |
830 | ||
831 | union dig_encoder_control { | |
832 | DIG_ENCODER_CONTROL_PS_ALLOCATION v1; | |
833 | DIG_ENCODER_CONTROL_PARAMETERS_V2 v2; | |
834 | DIG_ENCODER_CONTROL_PARAMETERS_V3 v3; | |
835 | DIG_ENCODER_CONTROL_PARAMETERS_V4 v4; | |
836 | }; | |
837 | ||
838 | void | |
bf071900 | 839 | atombios_dig_encoder_setup2(struct drm_encoder *encoder, int action, int panel_mode, int enc_override) |
3f03ced8 AD |
840 | { |
841 | struct drm_device *dev = encoder->dev; | |
842 | struct radeon_device *rdev = dev->dev_private; | |
843 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
844 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; | |
845 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); | |
846 | union dig_encoder_control args; | |
847 | int index = 0; | |
848 | uint8_t frev, crev; | |
849 | int dp_clock = 0; | |
850 | int dp_lane_count = 0; | |
851 | int hpd_id = RADEON_HPD_NONE; | |
3f03ced8 AD |
852 | |
853 | if (connector) { | |
854 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
855 | struct radeon_connector_atom_dig *dig_connector = | |
856 | radeon_connector->con_priv; | |
857 | ||
858 | dp_clock = dig_connector->dp_clock; | |
859 | dp_lane_count = dig_connector->dp_lane_count; | |
860 | hpd_id = radeon_connector->hpd.hpd; | |
3f03ced8 AD |
861 | } |
862 | ||
863 | /* no dig encoder assigned */ | |
864 | if (dig->dig_encoder == -1) | |
865 | return; | |
866 | ||
867 | memset(&args, 0, sizeof(args)); | |
868 | ||
869 | if (ASIC_IS_DCE4(rdev)) | |
870 | index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl); | |
871 | else { | |
872 | if (dig->dig_encoder) | |
873 | index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl); | |
874 | else | |
875 | index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl); | |
876 | } | |
877 | ||
878 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) | |
879 | return; | |
880 | ||
58cdcb8b AD |
881 | switch (frev) { |
882 | case 1: | |
883 | switch (crev) { | |
884 | case 1: | |
885 | args.v1.ucAction = action; | |
886 | args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); | |
887 | if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE) | |
888 | args.v3.ucPanelMode = panel_mode; | |
889 | else | |
890 | args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder); | |
891 | ||
892 | if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode)) | |
893 | args.v1.ucLaneNum = dp_lane_count; | |
9aa59993 | 894 | else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
58cdcb8b AD |
895 | args.v1.ucLaneNum = 8; |
896 | else | |
897 | args.v1.ucLaneNum = 4; | |
898 | ||
58cdcb8b AD |
899 | switch (radeon_encoder->encoder_id) { |
900 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: | |
901 | args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1; | |
902 | break; | |
903 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: | |
904 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: | |
905 | args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2; | |
906 | break; | |
907 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: | |
908 | args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3; | |
909 | break; | |
910 | } | |
911 | if (dig->linkb) | |
912 | args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB; | |
913 | else | |
914 | args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA; | |
459ee1c3 MK |
915 | |
916 | if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000)) | |
917 | args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ; | |
918 | ||
3f03ced8 | 919 | break; |
58cdcb8b AD |
920 | case 2: |
921 | case 3: | |
922 | args.v3.ucAction = action; | |
923 | args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); | |
924 | if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE) | |
925 | args.v3.ucPanelMode = panel_mode; | |
926 | else | |
927 | args.v3.ucEncoderMode = atombios_get_encoder_mode(encoder); | |
928 | ||
2f6fa79a | 929 | if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode)) |
58cdcb8b | 930 | args.v3.ucLaneNum = dp_lane_count; |
9aa59993 | 931 | else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
58cdcb8b AD |
932 | args.v3.ucLaneNum = 8; |
933 | else | |
934 | args.v3.ucLaneNum = 4; | |
935 | ||
2f6fa79a | 936 | if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode) && (dp_clock == 270000)) |
58cdcb8b | 937 | args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ; |
bf071900 DA |
938 | if (enc_override != -1) |
939 | args.v3.acConfig.ucDigSel = enc_override; | |
940 | else | |
941 | args.v3.acConfig.ucDigSel = dig->dig_encoder; | |
1f0e2943 | 942 | args.v3.ucBitPerColor = radeon_atom_get_bpc(encoder); |
3f03ced8 | 943 | break; |
58cdcb8b AD |
944 | case 4: |
945 | args.v4.ucAction = action; | |
946 | args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); | |
947 | if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE) | |
948 | args.v4.ucPanelMode = panel_mode; | |
949 | else | |
950 | args.v4.ucEncoderMode = atombios_get_encoder_mode(encoder); | |
951 | ||
2f6fa79a | 952 | if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode)) |
58cdcb8b | 953 | args.v4.ucLaneNum = dp_lane_count; |
9aa59993 | 954 | else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
58cdcb8b AD |
955 | args.v4.ucLaneNum = 8; |
956 | else | |
957 | args.v4.ucLaneNum = 4; | |
958 | ||
2f6fa79a | 959 | if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode)) { |
e68adef8 | 960 | if (dp_clock == 540000) |
58cdcb8b | 961 | args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ; |
e68adef8 AD |
962 | else if (dp_clock == 324000) |
963 | args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_3_24GHZ; | |
964 | else if (dp_clock == 270000) | |
965 | args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ; | |
966 | else | |
967 | args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ; | |
58cdcb8b | 968 | } |
bf071900 DA |
969 | |
970 | if (enc_override != -1) | |
971 | args.v4.acConfig.ucDigSel = enc_override; | |
972 | else | |
973 | args.v4.acConfig.ucDigSel = dig->dig_encoder; | |
1f0e2943 | 974 | args.v4.ucBitPerColor = radeon_atom_get_bpc(encoder); |
58cdcb8b AD |
975 | if (hpd_id == RADEON_HPD_NONE) |
976 | args.v4.ucHPD_ID = 0; | |
977 | else | |
978 | args.v4.ucHPD_ID = hpd_id + 1; | |
3f03ced8 | 979 | break; |
3f03ced8 | 980 | default: |
58cdcb8b | 981 | DRM_ERROR("Unknown table version %d, %d\n", frev, crev); |
3f03ced8 AD |
982 | break; |
983 | } | |
58cdcb8b AD |
984 | break; |
985 | default: | |
986 | DRM_ERROR("Unknown table version %d, %d\n", frev, crev); | |
987 | break; | |
3f03ced8 AD |
988 | } |
989 | ||
990 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
991 | ||
992 | } | |
993 | ||
bf071900 DA |
994 | void |
995 | atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode) | |
996 | { | |
997 | atombios_dig_encoder_setup2(encoder, action, panel_mode, -1); | |
998 | } | |
999 | ||
3f03ced8 AD |
1000 | union dig_transmitter_control { |
1001 | DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1; | |
1002 | DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2; | |
1003 | DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3; | |
1004 | DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4; | |
47aef7a8 | 1005 | DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 v5; |
3f03ced8 AD |
1006 | }; |
1007 | ||
1008 | void | |
bf071900 | 1009 | atombios_dig_transmitter_setup2(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set, int fe) |
3f03ced8 AD |
1010 | { |
1011 | struct drm_device *dev = encoder->dev; | |
1012 | struct radeon_device *rdev = dev->dev_private; | |
1013 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
1014 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; | |
1015 | struct drm_connector *connector; | |
1016 | union dig_transmitter_control args; | |
1017 | int index = 0; | |
1018 | uint8_t frev, crev; | |
1019 | bool is_dp = false; | |
1020 | int pll_id = 0; | |
1021 | int dp_clock = 0; | |
1022 | int dp_lane_count = 0; | |
1023 | int connector_object_id = 0; | |
1024 | int igp_lane_info = 0; | |
1025 | int dig_encoder = dig->dig_encoder; | |
47aef7a8 | 1026 | int hpd_id = RADEON_HPD_NONE; |
3f03ced8 AD |
1027 | |
1028 | if (action == ATOM_TRANSMITTER_ACTION_INIT) { | |
1029 | connector = radeon_get_connector_for_encoder_init(encoder); | |
1030 | /* just needed to avoid bailing in the encoder check. the encoder | |
1031 | * isn't used for init | |
1032 | */ | |
1033 | dig_encoder = 0; | |
1034 | } else | |
1035 | connector = radeon_get_connector_for_encoder(encoder); | |
1036 | ||
1037 | if (connector) { | |
1038 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
1039 | struct radeon_connector_atom_dig *dig_connector = | |
1040 | radeon_connector->con_priv; | |
1041 | ||
47aef7a8 | 1042 | hpd_id = radeon_connector->hpd.hpd; |
3f03ced8 AD |
1043 | dp_clock = dig_connector->dp_clock; |
1044 | dp_lane_count = dig_connector->dp_lane_count; | |
1045 | connector_object_id = | |
1046 | (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; | |
1047 | igp_lane_info = dig_connector->igp_lane_info; | |
1048 | } | |
1049 | ||
a3b08294 AD |
1050 | if (encoder->crtc) { |
1051 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); | |
1052 | pll_id = radeon_crtc->pll_id; | |
1053 | } | |
1054 | ||
3f03ced8 AD |
1055 | /* no dig encoder assigned */ |
1056 | if (dig_encoder == -1) | |
1057 | return; | |
1058 | ||
1059 | if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder))) | |
1060 | is_dp = true; | |
1061 | ||
1062 | memset(&args, 0, sizeof(args)); | |
1063 | ||
1064 | switch (radeon_encoder->encoder_id) { | |
1065 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: | |
1066 | index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl); | |
1067 | break; | |
1068 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: | |
1069 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: | |
1070 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: | |
e68adef8 | 1071 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: |
3f03ced8 AD |
1072 | index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl); |
1073 | break; | |
1074 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: | |
1075 | index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl); | |
1076 | break; | |
1077 | } | |
1078 | ||
1079 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) | |
1080 | return; | |
1081 | ||
a3b08294 AD |
1082 | switch (frev) { |
1083 | case 1: | |
1084 | switch (crev) { | |
1085 | case 1: | |
1086 | args.v1.ucAction = action; | |
1087 | if (action == ATOM_TRANSMITTER_ACTION_INIT) { | |
1088 | args.v1.usInitInfo = cpu_to_le16(connector_object_id); | |
1089 | } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { | |
1090 | args.v1.asMode.ucLaneSel = lane_num; | |
1091 | args.v1.asMode.ucLaneSet = lane_set; | |
1092 | } else { | |
1093 | if (is_dp) | |
6e76a2df | 1094 | args.v1.usPixelClock = cpu_to_le16(dp_clock / 10); |
9aa59993 | 1095 | else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
a3b08294 AD |
1096 | args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); |
1097 | else | |
1098 | args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); | |
1099 | } | |
3f03ced8 | 1100 | |
a3b08294 | 1101 | args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL; |
3f03ced8 | 1102 | |
a3b08294 AD |
1103 | if (dig_encoder) |
1104 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER; | |
1105 | else | |
1106 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER; | |
1107 | ||
1108 | if ((rdev->flags & RADEON_IS_IGP) && | |
1109 | (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) { | |
9aa59993 AD |
1110 | if (is_dp || |
1111 | !radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) { | |
a3b08294 AD |
1112 | if (igp_lane_info & 0x1) |
1113 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3; | |
1114 | else if (igp_lane_info & 0x2) | |
1115 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7; | |
1116 | else if (igp_lane_info & 0x4) | |
1117 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11; | |
1118 | else if (igp_lane_info & 0x8) | |
1119 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15; | |
1120 | } else { | |
1121 | if (igp_lane_info & 0x3) | |
1122 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7; | |
1123 | else if (igp_lane_info & 0xc) | |
1124 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15; | |
1125 | } | |
1126 | } | |
1127 | ||
1128 | if (dig->linkb) | |
1129 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB; | |
1130 | else | |
1131 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA; | |
1132 | ||
1133 | if (is_dp) | |
1134 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT; | |
1135 | else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { | |
1136 | if (dig->coherent_mode) | |
1137 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT; | |
9aa59993 | 1138 | if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
a3b08294 AD |
1139 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK; |
1140 | } | |
1141 | break; | |
1142 | case 2: | |
1143 | args.v2.ucAction = action; | |
1144 | if (action == ATOM_TRANSMITTER_ACTION_INIT) { | |
1145 | args.v2.usInitInfo = cpu_to_le16(connector_object_id); | |
1146 | } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { | |
1147 | args.v2.asMode.ucLaneSel = lane_num; | |
1148 | args.v2.asMode.ucLaneSet = lane_set; | |
1149 | } else { | |
1150 | if (is_dp) | |
6e76a2df | 1151 | args.v2.usPixelClock = cpu_to_le16(dp_clock / 10); |
9aa59993 | 1152 | else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
a3b08294 AD |
1153 | args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); |
1154 | else | |
1155 | args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); | |
1156 | } | |
1157 | ||
1158 | args.v2.acConfig.ucEncoderSel = dig_encoder; | |
1159 | if (dig->linkb) | |
1160 | args.v2.acConfig.ucLinkSel = 1; | |
1161 | ||
1162 | switch (radeon_encoder->encoder_id) { | |
1163 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: | |
1164 | args.v2.acConfig.ucTransmitterSel = 0; | |
1165 | break; | |
1166 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: | |
1167 | args.v2.acConfig.ucTransmitterSel = 1; | |
1168 | break; | |
1169 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: | |
1170 | args.v2.acConfig.ucTransmitterSel = 2; | |
1171 | break; | |
1172 | } | |
3f03ced8 | 1173 | |
3f03ced8 | 1174 | if (is_dp) { |
a3b08294 AD |
1175 | args.v2.acConfig.fCoherentMode = 1; |
1176 | args.v2.acConfig.fDPConnector = 1; | |
1177 | } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { | |
1178 | if (dig->coherent_mode) | |
1179 | args.v2.acConfig.fCoherentMode = 1; | |
9aa59993 | 1180 | if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
a3b08294 AD |
1181 | args.v2.acConfig.fDualLinkConnector = 1; |
1182 | } | |
1183 | break; | |
1184 | case 3: | |
1185 | args.v3.ucAction = action; | |
1186 | if (action == ATOM_TRANSMITTER_ACTION_INIT) { | |
1187 | args.v3.usInitInfo = cpu_to_le16(connector_object_id); | |
1188 | } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { | |
1189 | args.v3.asMode.ucLaneSel = lane_num; | |
1190 | args.v3.asMode.ucLaneSet = lane_set; | |
1191 | } else { | |
1192 | if (is_dp) | |
6e76a2df | 1193 | args.v3.usPixelClock = cpu_to_le16(dp_clock / 10); |
9aa59993 | 1194 | else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
a3b08294 | 1195 | args.v3.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); |
3f03ced8 | 1196 | else |
a3b08294 AD |
1197 | args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
1198 | } | |
1199 | ||
1200 | if (is_dp) | |
1201 | args.v3.ucLaneNum = dp_lane_count; | |
9aa59993 | 1202 | else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
a3b08294 AD |
1203 | args.v3.ucLaneNum = 8; |
1204 | else | |
1205 | args.v3.ucLaneNum = 4; | |
1206 | ||
1207 | if (dig->linkb) | |
1208 | args.v3.acConfig.ucLinkSel = 1; | |
1209 | if (dig_encoder & 1) | |
1210 | args.v3.acConfig.ucEncoderSel = 1; | |
1211 | ||
1212 | /* Select the PLL for the PHY | |
1213 | * DP PHY should be clocked from external src if there is | |
1214 | * one. | |
1215 | */ | |
3f03ced8 AD |
1216 | /* On DCE4, if there is an external clock, it generates the DP ref clock */ |
1217 | if (is_dp && rdev->clock.dp_extclk) | |
1218 | args.v3.acConfig.ucRefClkSource = 2; /* external src */ | |
1219 | else | |
1220 | args.v3.acConfig.ucRefClkSource = pll_id; | |
3f03ced8 | 1221 | |
a3b08294 AD |
1222 | switch (radeon_encoder->encoder_id) { |
1223 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: | |
1224 | args.v3.acConfig.ucTransmitterSel = 0; | |
1225 | break; | |
1226 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: | |
1227 | args.v3.acConfig.ucTransmitterSel = 1; | |
1228 | break; | |
1229 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: | |
1230 | args.v3.acConfig.ucTransmitterSel = 2; | |
1231 | break; | |
1232 | } | |
3f03ced8 | 1233 | |
a3b08294 AD |
1234 | if (is_dp) |
1235 | args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */ | |
1236 | else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { | |
1237 | if (dig->coherent_mode) | |
1238 | args.v3.acConfig.fCoherentMode = 1; | |
9aa59993 | 1239 | if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
a3b08294 AD |
1240 | args.v3.acConfig.fDualLinkConnector = 1; |
1241 | } | |
3f03ced8 | 1242 | break; |
a3b08294 AD |
1243 | case 4: |
1244 | args.v4.ucAction = action; | |
1245 | if (action == ATOM_TRANSMITTER_ACTION_INIT) { | |
1246 | args.v4.usInitInfo = cpu_to_le16(connector_object_id); | |
1247 | } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { | |
1248 | args.v4.asMode.ucLaneSel = lane_num; | |
1249 | args.v4.asMode.ucLaneSet = lane_set; | |
3f03ced8 | 1250 | } else { |
a3b08294 | 1251 | if (is_dp) |
6e76a2df | 1252 | args.v4.usPixelClock = cpu_to_le16(dp_clock / 10); |
9aa59993 | 1253 | else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
a3b08294 AD |
1254 | args.v4.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); |
1255 | else | |
1256 | args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); | |
3f03ced8 | 1257 | } |
3f03ced8 | 1258 | |
a3b08294 AD |
1259 | if (is_dp) |
1260 | args.v4.ucLaneNum = dp_lane_count; | |
9aa59993 | 1261 | else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
a3b08294 AD |
1262 | args.v4.ucLaneNum = 8; |
1263 | else | |
1264 | args.v4.ucLaneNum = 4; | |
3f03ced8 | 1265 | |
a3b08294 AD |
1266 | if (dig->linkb) |
1267 | args.v4.acConfig.ucLinkSel = 1; | |
1268 | if (dig_encoder & 1) | |
1269 | args.v4.acConfig.ucEncoderSel = 1; | |
1270 | ||
1271 | /* Select the PLL for the PHY | |
1272 | * DP PHY should be clocked from external src if there is | |
1273 | * one. | |
1274 | */ | |
1275 | /* On DCE5 DCPLL usually generates the DP ref clock */ | |
1276 | if (is_dp) { | |
1277 | if (rdev->clock.dp_extclk) | |
1278 | args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK; | |
1279 | else | |
1280 | args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL; | |
1281 | } else | |
1282 | args.v4.acConfig.ucRefClkSource = pll_id; | |
1283 | ||
1284 | switch (radeon_encoder->encoder_id) { | |
1285 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: | |
1286 | args.v4.acConfig.ucTransmitterSel = 0; | |
1287 | break; | |
1288 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: | |
1289 | args.v4.acConfig.ucTransmitterSel = 1; | |
1290 | break; | |
1291 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: | |
1292 | args.v4.acConfig.ucTransmitterSel = 2; | |
1293 | break; | |
1294 | } | |
1295 | ||
1296 | if (is_dp) | |
1297 | args.v4.acConfig.fCoherentMode = 1; /* DP requires coherent */ | |
1298 | else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { | |
1299 | if (dig->coherent_mode) | |
1300 | args.v4.acConfig.fCoherentMode = 1; | |
9aa59993 | 1301 | if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
a3b08294 AD |
1302 | args.v4.acConfig.fDualLinkConnector = 1; |
1303 | } | |
1304 | break; | |
47aef7a8 AD |
1305 | case 5: |
1306 | args.v5.ucAction = action; | |
1307 | if (is_dp) | |
1308 | args.v5.usSymClock = cpu_to_le16(dp_clock / 10); | |
1309 | else | |
1310 | args.v5.usSymClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); | |
1311 | ||
1312 | switch (radeon_encoder->encoder_id) { | |
1313 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: | |
1314 | if (dig->linkb) | |
1315 | args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYB; | |
1316 | else | |
1317 | args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYA; | |
1318 | break; | |
1319 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: | |
1320 | if (dig->linkb) | |
1321 | args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYD; | |
1322 | else | |
1323 | args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYC; | |
1324 | break; | |
1325 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: | |
1326 | if (dig->linkb) | |
1327 | args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYF; | |
1328 | else | |
1329 | args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYE; | |
1330 | break; | |
e68adef8 AD |
1331 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: |
1332 | args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYG; | |
1333 | break; | |
47aef7a8 AD |
1334 | } |
1335 | if (is_dp) | |
1336 | args.v5.ucLaneNum = dp_lane_count; | |
d03874c8 | 1337 | else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
47aef7a8 AD |
1338 | args.v5.ucLaneNum = 8; |
1339 | else | |
1340 | args.v5.ucLaneNum = 4; | |
1341 | args.v5.ucConnObjId = connector_object_id; | |
1342 | args.v5.ucDigMode = atombios_get_encoder_mode(encoder); | |
1343 | ||
1344 | if (is_dp && rdev->clock.dp_extclk) | |
1345 | args.v5.asConfig.ucPhyClkSrcId = ENCODER_REFCLK_SRC_EXTCLK; | |
1346 | else | |
1347 | args.v5.asConfig.ucPhyClkSrcId = pll_id; | |
1348 | ||
1349 | if (is_dp) | |
1350 | args.v5.asConfig.ucCoherentMode = 1; /* DP requires coherent */ | |
1351 | else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { | |
1352 | if (dig->coherent_mode) | |
1353 | args.v5.asConfig.ucCoherentMode = 1; | |
1354 | } | |
1355 | if (hpd_id == RADEON_HPD_NONE) | |
1356 | args.v5.asConfig.ucHPDSel = 0; | |
1357 | else | |
1358 | args.v5.asConfig.ucHPDSel = hpd_id + 1; | |
bf071900 | 1359 | args.v5.ucDigEncoderSel = (fe != -1) ? (1 << fe) : (1 << dig_encoder); |
47aef7a8 AD |
1360 | args.v5.ucDPLaneSet = lane_set; |
1361 | break; | |
a3b08294 AD |
1362 | default: |
1363 | DRM_ERROR("Unknown table version %d, %d\n", frev, crev); | |
1364 | break; | |
3f03ced8 | 1365 | } |
a3b08294 AD |
1366 | break; |
1367 | default: | |
1368 | DRM_ERROR("Unknown table version %d, %d\n", frev, crev); | |
1369 | break; | |
3f03ced8 AD |
1370 | } |
1371 | ||
1372 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
1373 | } | |
1374 | ||
bf071900 DA |
1375 | void |
1376 | atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set) | |
1377 | { | |
1378 | atombios_dig_transmitter_setup2(encoder, action, lane_num, lane_set, -1); | |
1379 | } | |
1380 | ||
3f03ced8 AD |
1381 | bool |
1382 | atombios_set_edp_panel_power(struct drm_connector *connector, int action) | |
1383 | { | |
1384 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
1385 | struct drm_device *dev = radeon_connector->base.dev; | |
1386 | struct radeon_device *rdev = dev->dev_private; | |
1387 | union dig_transmitter_control args; | |
1388 | int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl); | |
1389 | uint8_t frev, crev; | |
1390 | ||
1391 | if (connector->connector_type != DRM_MODE_CONNECTOR_eDP) | |
1392 | goto done; | |
1393 | ||
1394 | if (!ASIC_IS_DCE4(rdev)) | |
1395 | goto done; | |
1396 | ||
1397 | if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) && | |
1398 | (action != ATOM_TRANSMITTER_ACTION_POWER_OFF)) | |
1399 | goto done; | |
1400 | ||
1401 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) | |
1402 | goto done; | |
1403 | ||
1404 | memset(&args, 0, sizeof(args)); | |
1405 | ||
1406 | args.v1.ucAction = action; | |
1407 | ||
1408 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
1409 | ||
1410 | /* wait for the panel to power up */ | |
1411 | if (action == ATOM_TRANSMITTER_ACTION_POWER_ON) { | |
1412 | int i; | |
1413 | ||
1414 | for (i = 0; i < 300; i++) { | |
1415 | if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd)) | |
1416 | return true; | |
1417 | mdelay(1); | |
1418 | } | |
1419 | return false; | |
1420 | } | |
1421 | done: | |
1422 | return true; | |
1423 | } | |
1424 | ||
1425 | union external_encoder_control { | |
1426 | EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1; | |
1427 | EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3; | |
1428 | }; | |
1429 | ||
1430 | static void | |
1431 | atombios_external_encoder_setup(struct drm_encoder *encoder, | |
1432 | struct drm_encoder *ext_encoder, | |
1433 | int action) | |
1434 | { | |
1435 | struct drm_device *dev = encoder->dev; | |
1436 | struct radeon_device *rdev = dev->dev_private; | |
1437 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
1438 | struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder); | |
1439 | union external_encoder_control args; | |
1440 | struct drm_connector *connector; | |
1441 | int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl); | |
1442 | u8 frev, crev; | |
1443 | int dp_clock = 0; | |
1444 | int dp_lane_count = 0; | |
1445 | int connector_object_id = 0; | |
1446 | u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT; | |
3f03ced8 AD |
1447 | |
1448 | if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT) | |
1449 | connector = radeon_get_connector_for_encoder_init(encoder); | |
1450 | else | |
1451 | connector = radeon_get_connector_for_encoder(encoder); | |
1452 | ||
1453 | if (connector) { | |
1454 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
1455 | struct radeon_connector_atom_dig *dig_connector = | |
1456 | radeon_connector->con_priv; | |
1457 | ||
1458 | dp_clock = dig_connector->dp_clock; | |
1459 | dp_lane_count = dig_connector->dp_lane_count; | |
1460 | connector_object_id = | |
1461 | (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; | |
3f03ced8 AD |
1462 | } |
1463 | ||
1464 | memset(&args, 0, sizeof(args)); | |
1465 | ||
1466 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) | |
1467 | return; | |
1468 | ||
1469 | switch (frev) { | |
1470 | case 1: | |
1471 | /* no params on frev 1 */ | |
1472 | break; | |
1473 | case 2: | |
1474 | switch (crev) { | |
1475 | case 1: | |
1476 | case 2: | |
1477 | args.v1.sDigEncoder.ucAction = action; | |
1478 | args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); | |
1479 | args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder); | |
1480 | ||
1481 | if (ENCODER_MODE_IS_DP(args.v1.sDigEncoder.ucEncoderMode)) { | |
1482 | if (dp_clock == 270000) | |
1483 | args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ; | |
1484 | args.v1.sDigEncoder.ucLaneNum = dp_lane_count; | |
9aa59993 | 1485 | } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
3f03ced8 AD |
1486 | args.v1.sDigEncoder.ucLaneNum = 8; |
1487 | else | |
1488 | args.v1.sDigEncoder.ucLaneNum = 4; | |
1489 | break; | |
1490 | case 3: | |
1491 | args.v3.sExtEncoder.ucAction = action; | |
1492 | if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT) | |
1493 | args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id); | |
1494 | else | |
1495 | args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); | |
1496 | args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder); | |
1497 | ||
1498 | if (ENCODER_MODE_IS_DP(args.v3.sExtEncoder.ucEncoderMode)) { | |
1499 | if (dp_clock == 270000) | |
1500 | args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ; | |
1501 | else if (dp_clock == 540000) | |
1502 | args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ; | |
1503 | args.v3.sExtEncoder.ucLaneNum = dp_lane_count; | |
9aa59993 | 1504 | } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
3f03ced8 AD |
1505 | args.v3.sExtEncoder.ucLaneNum = 8; |
1506 | else | |
1507 | args.v3.sExtEncoder.ucLaneNum = 4; | |
1508 | switch (ext_enum) { | |
1509 | case GRAPH_OBJECT_ENUM_ID1: | |
1510 | args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1; | |
1511 | break; | |
1512 | case GRAPH_OBJECT_ENUM_ID2: | |
1513 | args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2; | |
1514 | break; | |
1515 | case GRAPH_OBJECT_ENUM_ID3: | |
1516 | args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3; | |
1517 | break; | |
1518 | } | |
1f0e2943 | 1519 | args.v3.sExtEncoder.ucBitPerColor = radeon_atom_get_bpc(encoder); |
3f03ced8 AD |
1520 | break; |
1521 | default: | |
1522 | DRM_ERROR("Unknown table version: %d, %d\n", frev, crev); | |
1523 | return; | |
1524 | } | |
1525 | break; | |
1526 | default: | |
1527 | DRM_ERROR("Unknown table version: %d, %d\n", frev, crev); | |
1528 | return; | |
1529 | } | |
1530 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
1531 | } | |
1532 | ||
1533 | static void | |
1534 | atombios_yuv_setup(struct drm_encoder *encoder, bool enable) | |
1535 | { | |
1536 | struct drm_device *dev = encoder->dev; | |
1537 | struct radeon_device *rdev = dev->dev_private; | |
1538 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
1539 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); | |
1540 | ENABLE_YUV_PS_ALLOCATION args; | |
1541 | int index = GetIndexIntoMasterTable(COMMAND, EnableYUV); | |
1542 | uint32_t temp, reg; | |
1543 | ||
1544 | memset(&args, 0, sizeof(args)); | |
1545 | ||
1546 | if (rdev->family >= CHIP_R600) | |
1547 | reg = R600_BIOS_3_SCRATCH; | |
1548 | else | |
1549 | reg = RADEON_BIOS_3_SCRATCH; | |
1550 | ||
1551 | /* XXX: fix up scratch reg handling */ | |
1552 | temp = RREG32(reg); | |
1553 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) | |
1554 | WREG32(reg, (ATOM_S3_TV1_ACTIVE | | |
1555 | (radeon_crtc->crtc_id << 18))); | |
1556 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) | |
1557 | WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24))); | |
1558 | else | |
1559 | WREG32(reg, 0); | |
1560 | ||
1561 | if (enable) | |
1562 | args.ucEnable = ATOM_ENABLE; | |
1563 | args.ucCRTC = radeon_crtc->crtc_id; | |
1564 | ||
1565 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
1566 | ||
1567 | WREG32(reg, temp); | |
1568 | } | |
1569 | ||
1570 | static void | |
1571 | radeon_atom_encoder_dpms_avivo(struct drm_encoder *encoder, int mode) | |
1572 | { | |
1573 | struct drm_device *dev = encoder->dev; | |
1574 | struct radeon_device *rdev = dev->dev_private; | |
1575 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
1576 | DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args; | |
1577 | int index = 0; | |
1578 | ||
1579 | memset(&args, 0, sizeof(args)); | |
1580 | ||
1581 | switch (radeon_encoder->encoder_id) { | |
1582 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: | |
1583 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: | |
1584 | index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl); | |
1585 | break; | |
1586 | case ENCODER_OBJECT_ID_INTERNAL_DVO1: | |
1587 | case ENCODER_OBJECT_ID_INTERNAL_DDI: | |
1588 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: | |
1589 | index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl); | |
1590 | break; | |
1591 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: | |
1592 | index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); | |
1593 | break; | |
1594 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: | |
1595 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) | |
1596 | index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); | |
1597 | else | |
1598 | index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl); | |
1599 | break; | |
1600 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: | |
1601 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: | |
1602 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) | |
1603 | index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); | |
1604 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) | |
1605 | index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); | |
1606 | else | |
1607 | index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl); | |
1608 | break; | |
1609 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: | |
1610 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: | |
1611 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) | |
1612 | index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); | |
1613 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) | |
1614 | index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); | |
1615 | else | |
1616 | index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl); | |
1617 | break; | |
1618 | default: | |
1619 | return; | |
1620 | } | |
1621 | ||
1622 | switch (mode) { | |
1623 | case DRM_MODE_DPMS_ON: | |
1624 | args.ucAction = ATOM_ENABLE; | |
1625 | /* workaround for DVOOutputControl on some RS690 systems */ | |
1626 | if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DDI) { | |
1627 | u32 reg = RREG32(RADEON_BIOS_3_SCRATCH); | |
1628 | WREG32(RADEON_BIOS_3_SCRATCH, reg & ~ATOM_S3_DFP2I_ACTIVE); | |
1629 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
1630 | WREG32(RADEON_BIOS_3_SCRATCH, reg); | |
1631 | } else | |
1632 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
1633 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { | |
ae93580e AD |
1634 | if (rdev->mode_info.bl_encoder) { |
1635 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; | |
4281f46e | 1636 | |
ae93580e AD |
1637 | atombios_set_backlight_level(radeon_encoder, dig->backlight_level); |
1638 | } else { | |
1639 | args.ucAction = ATOM_LCD_BLON; | |
1640 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
1641 | } | |
3f03ced8 AD |
1642 | } |
1643 | break; | |
1644 | case DRM_MODE_DPMS_STANDBY: | |
1645 | case DRM_MODE_DPMS_SUSPEND: | |
1646 | case DRM_MODE_DPMS_OFF: | |
1647 | args.ucAction = ATOM_DISABLE; | |
1648 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
1649 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { | |
1650 | args.ucAction = ATOM_LCD_BLOFF; | |
1651 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
1652 | } | |
1653 | break; | |
1654 | } | |
1655 | } | |
1656 | ||
1657 | static void | |
1658 | radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode) | |
1659 | { | |
1660 | struct drm_device *dev = encoder->dev; | |
1661 | struct radeon_device *rdev = dev->dev_private; | |
1662 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
8d1af57a AD |
1663 | struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); |
1664 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; | |
3f03ced8 AD |
1665 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); |
1666 | struct radeon_connector *radeon_connector = NULL; | |
1667 | struct radeon_connector_atom_dig *radeon_dig_connector = NULL; | |
6f50e075 | 1668 | bool travis_quirk = false; |
3f03ced8 AD |
1669 | |
1670 | if (connector) { | |
1671 | radeon_connector = to_radeon_connector(connector); | |
1672 | radeon_dig_connector = radeon_connector->con_priv; | |
6f50e075 AD |
1673 | if ((radeon_connector_encoder_get_dp_bridge_encoder_id(connector) == |
1674 | ENCODER_OBJECT_ID_TRAVIS) && | |
1675 | (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) && | |
1676 | !ASIC_IS_DCE5(rdev)) | |
1677 | travis_quirk = true; | |
3f03ced8 AD |
1678 | } |
1679 | ||
1680 | switch (mode) { | |
1681 | case DRM_MODE_DPMS_ON: | |
8d1af57a AD |
1682 | if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) { |
1683 | if (!connector) | |
1684 | dig->panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE; | |
1685 | else | |
1686 | dig->panel_mode = radeon_dp_get_panel_mode(encoder, connector); | |
1687 | ||
1688 | /* setup and enable the encoder */ | |
1689 | atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0); | |
1690 | atombios_dig_encoder_setup(encoder, | |
1691 | ATOM_ENCODER_CMD_SETUP_PANEL_MODE, | |
1692 | dig->panel_mode); | |
1693 | if (ext_encoder) { | |
1694 | if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) | |
1695 | atombios_external_encoder_setup(encoder, ext_encoder, | |
1696 | EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP); | |
fcedac67 | 1697 | } |
8d1af57a AD |
1698 | } else if (ASIC_IS_DCE4(rdev)) { |
1699 | /* setup and enable the encoder */ | |
1700 | atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0); | |
8d1af57a AD |
1701 | } else { |
1702 | /* setup and enable the encoder and transmitter */ | |
1703 | atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0); | |
1704 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0); | |
fcedac67 | 1705 | } |
3f03ced8 AD |
1706 | if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) { |
1707 | if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { | |
1708 | atombios_set_edp_panel_power(connector, | |
1709 | ATOM_TRANSMITTER_ACTION_POWER_ON); | |
1710 | radeon_dig_connector->edp_on = true; | |
1711 | } | |
6f50e075 AD |
1712 | } |
1713 | /* enable the transmitter */ | |
1714 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0); | |
1715 | if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) { | |
1716 | /* DP_SET_POWER_D0 is set in radeon_dp_link_train */ | |
3f03ced8 AD |
1717 | radeon_dp_link_train(encoder, connector); |
1718 | if (ASIC_IS_DCE4(rdev)) | |
1719 | atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0); | |
1720 | } | |
ae93580e AD |
1721 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { |
1722 | if (rdev->mode_info.bl_encoder) | |
1723 | atombios_set_backlight_level(radeon_encoder, dig->backlight_level); | |
1724 | else | |
1725 | atombios_dig_transmitter_setup(encoder, | |
1726 | ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0); | |
1727 | } | |
6f50e075 AD |
1728 | if (ext_encoder) |
1729 | atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE); | |
3f03ced8 AD |
1730 | break; |
1731 | case DRM_MODE_DPMS_STANDBY: | |
1732 | case DRM_MODE_DPMS_SUSPEND: | |
1733 | case DRM_MODE_DPMS_OFF: | |
9843ead0 DA |
1734 | |
1735 | /* don't power off encoders with active MST links */ | |
1736 | if (dig->active_mst_links) | |
1737 | return; | |
1738 | ||
6f50e075 AD |
1739 | if (ASIC_IS_DCE4(rdev)) { |
1740 | if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) | |
1741 | atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0); | |
1742 | } | |
1743 | if (ext_encoder) | |
1744 | atombios_external_encoder_setup(encoder, ext_encoder, ATOM_DISABLE); | |
1745 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) | |
1746 | atombios_dig_transmitter_setup(encoder, | |
1747 | ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0); | |
1748 | ||
1749 | if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && | |
1750 | connector && !travis_quirk) | |
1751 | radeon_dp_set_rx_power_state(connector, DP_SET_POWER_D3); | |
40390961 | 1752 | if (ASIC_IS_DCE4(rdev)) { |
8d1af57a | 1753 | /* disable the transmitter */ |
6f50e075 AD |
1754 | atombios_dig_transmitter_setup(encoder, |
1755 | ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); | |
8d1af57a AD |
1756 | } else { |
1757 | /* disable the encoder and transmitter */ | |
6f50e075 AD |
1758 | atombios_dig_transmitter_setup(encoder, |
1759 | ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); | |
8d1af57a AD |
1760 | atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0); |
1761 | } | |
3f03ced8 | 1762 | if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) { |
6f50e075 AD |
1763 | if (travis_quirk) |
1764 | radeon_dp_set_rx_power_state(connector, DP_SET_POWER_D3); | |
3f03ced8 AD |
1765 | if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { |
1766 | atombios_set_edp_panel_power(connector, | |
1767 | ATOM_TRANSMITTER_ACTION_POWER_OFF); | |
1768 | radeon_dig_connector->edp_on = false; | |
1769 | } | |
1770 | } | |
3f03ced8 AD |
1771 | break; |
1772 | } | |
1773 | } | |
1774 | ||
1775 | static void | |
1776 | radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode) | |
1777 | { | |
1778 | struct drm_device *dev = encoder->dev; | |
1779 | struct radeon_device *rdev = dev->dev_private; | |
1780 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
5c046a57 | 1781 | int encoder_mode = atombios_get_encoder_mode(encoder); |
3f03ced8 AD |
1782 | |
1783 | DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n", | |
1784 | radeon_encoder->encoder_id, mode, radeon_encoder->devices, | |
1785 | radeon_encoder->active_device); | |
5c046a57 | 1786 | |
38aef154 | 1787 | if ((radeon_audio != 0) && |
5c046a57 | 1788 | ((encoder_mode == ATOM_ENCODER_MODE_HDMI) || |
38aef154 | 1789 | ENCODER_MODE_IS_DP(encoder_mode))) |
5c046a57 AD |
1790 | radeon_audio_dpms(encoder, mode); |
1791 | ||
3f03ced8 AD |
1792 | switch (radeon_encoder->encoder_id) { |
1793 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: | |
1794 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: | |
1795 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: | |
1796 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: | |
1797 | case ENCODER_OBJECT_ID_INTERNAL_DVO1: | |
1798 | case ENCODER_OBJECT_ID_INTERNAL_DDI: | |
1799 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: | |
1800 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: | |
1801 | radeon_atom_encoder_dpms_avivo(encoder, mode); | |
1802 | break; | |
1803 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: | |
1804 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: | |
1805 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: | |
e68adef8 | 1806 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: |
3f03ced8 AD |
1807 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
1808 | radeon_atom_encoder_dpms_dig(encoder, mode); | |
1809 | break; | |
1810 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: | |
1811 | if (ASIC_IS_DCE5(rdev)) { | |
1812 | switch (mode) { | |
1813 | case DRM_MODE_DPMS_ON: | |
1814 | atombios_dvo_setup(encoder, ATOM_ENABLE); | |
1815 | break; | |
1816 | case DRM_MODE_DPMS_STANDBY: | |
1817 | case DRM_MODE_DPMS_SUSPEND: | |
1818 | case DRM_MODE_DPMS_OFF: | |
1819 | atombios_dvo_setup(encoder, ATOM_DISABLE); | |
1820 | break; | |
1821 | } | |
1822 | } else if (ASIC_IS_DCE3(rdev)) | |
1823 | radeon_atom_encoder_dpms_dig(encoder, mode); | |
1824 | else | |
1825 | radeon_atom_encoder_dpms_avivo(encoder, mode); | |
1826 | break; | |
1827 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: | |
1828 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: | |
1829 | if (ASIC_IS_DCE5(rdev)) { | |
1830 | switch (mode) { | |
1831 | case DRM_MODE_DPMS_ON: | |
1832 | atombios_dac_setup(encoder, ATOM_ENABLE); | |
1833 | break; | |
1834 | case DRM_MODE_DPMS_STANDBY: | |
1835 | case DRM_MODE_DPMS_SUSPEND: | |
1836 | case DRM_MODE_DPMS_OFF: | |
1837 | atombios_dac_setup(encoder, ATOM_DISABLE); | |
1838 | break; | |
1839 | } | |
1840 | } else | |
1841 | radeon_atom_encoder_dpms_avivo(encoder, mode); | |
1842 | break; | |
1843 | default: | |
1844 | return; | |
1845 | } | |
1846 | ||
3f03ced8 AD |
1847 | radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); |
1848 | ||
1849 | } | |
1850 | ||
1851 | union crtc_source_param { | |
1852 | SELECT_CRTC_SOURCE_PS_ALLOCATION v1; | |
1853 | SELECT_CRTC_SOURCE_PARAMETERS_V2 v2; | |
1854 | }; | |
1855 | ||
1856 | static void | |
1857 | atombios_set_encoder_crtc_source(struct drm_encoder *encoder) | |
1858 | { | |
1859 | struct drm_device *dev = encoder->dev; | |
1860 | struct radeon_device *rdev = dev->dev_private; | |
1861 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
1862 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); | |
1863 | union crtc_source_param args; | |
1864 | int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source); | |
1865 | uint8_t frev, crev; | |
1866 | struct radeon_encoder_atom_dig *dig; | |
1867 | ||
1868 | memset(&args, 0, sizeof(args)); | |
1869 | ||
1870 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) | |
1871 | return; | |
1872 | ||
1873 | switch (frev) { | |
1874 | case 1: | |
1875 | switch (crev) { | |
1876 | case 1: | |
1877 | default: | |
1878 | if (ASIC_IS_AVIVO(rdev)) | |
1879 | args.v1.ucCRTC = radeon_crtc->crtc_id; | |
1880 | else { | |
1881 | if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) { | |
1882 | args.v1.ucCRTC = radeon_crtc->crtc_id; | |
1883 | } else { | |
1884 | args.v1.ucCRTC = radeon_crtc->crtc_id << 2; | |
1885 | } | |
1886 | } | |
1887 | switch (radeon_encoder->encoder_id) { | |
1888 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: | |
1889 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: | |
1890 | args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX; | |
1891 | break; | |
1892 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: | |
1893 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: | |
1894 | if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) | |
1895 | args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX; | |
1896 | else | |
1897 | args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX; | |
1898 | break; | |
1899 | case ENCODER_OBJECT_ID_INTERNAL_DVO1: | |
1900 | case ENCODER_OBJECT_ID_INTERNAL_DDI: | |
1901 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: | |
1902 | args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX; | |
1903 | break; | |
1904 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: | |
1905 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: | |
1906 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) | |
1907 | args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX; | |
1908 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) | |
1909 | args.v1.ucDevice = ATOM_DEVICE_CV_INDEX; | |
1910 | else | |
1911 | args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX; | |
1912 | break; | |
1913 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: | |
1914 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: | |
1915 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) | |
1916 | args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX; | |
1917 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) | |
1918 | args.v1.ucDevice = ATOM_DEVICE_CV_INDEX; | |
1919 | else | |
1920 | args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX; | |
1921 | break; | |
1922 | } | |
1923 | break; | |
1924 | case 2: | |
1925 | args.v2.ucCRTC = radeon_crtc->crtc_id; | |
1926 | if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) { | |
1927 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); | |
1928 | ||
1929 | if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS) | |
1930 | args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS; | |
1931 | else if (connector->connector_type == DRM_MODE_CONNECTOR_VGA) | |
1932 | args.v2.ucEncodeMode = ATOM_ENCODER_MODE_CRT; | |
1933 | else | |
1934 | args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder); | |
64252835 AD |
1935 | } else if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { |
1936 | args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS; | |
1937 | } else { | |
3f03ced8 | 1938 | args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder); |
64252835 | 1939 | } |
3f03ced8 AD |
1940 | switch (radeon_encoder->encoder_id) { |
1941 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: | |
1942 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: | |
1943 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: | |
e68adef8 | 1944 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: |
3f03ced8 AD |
1945 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
1946 | dig = radeon_encoder->enc_priv; | |
1947 | switch (dig->dig_encoder) { | |
1948 | case 0: | |
1949 | args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID; | |
1950 | break; | |
1951 | case 1: | |
1952 | args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID; | |
1953 | break; | |
1954 | case 2: | |
1955 | args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID; | |
1956 | break; | |
1957 | case 3: | |
1958 | args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID; | |
1959 | break; | |
1960 | case 4: | |
1961 | args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID; | |
1962 | break; | |
1963 | case 5: | |
1964 | args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID; | |
1965 | break; | |
e68adef8 AD |
1966 | case 6: |
1967 | args.v2.ucEncoderID = ASIC_INT_DIG7_ENCODER_ID; | |
1968 | break; | |
3f03ced8 AD |
1969 | } |
1970 | break; | |
1971 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: | |
1972 | args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID; | |
1973 | break; | |
1974 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: | |
1975 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) | |
1976 | args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; | |
1977 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) | |
1978 | args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; | |
1979 | else | |
1980 | args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID; | |
1981 | break; | |
1982 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: | |
1983 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) | |
1984 | args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; | |
1985 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) | |
1986 | args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; | |
1987 | else | |
1988 | args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID; | |
1989 | break; | |
1990 | } | |
1991 | break; | |
1992 | } | |
1993 | break; | |
1994 | default: | |
1995 | DRM_ERROR("Unknown table version: %d, %d\n", frev, crev); | |
1996 | return; | |
1997 | } | |
1998 | ||
1999 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
2000 | ||
2001 | /* update scratch regs with new routing */ | |
2002 | radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); | |
2003 | } | |
2004 | ||
9843ead0 DA |
2005 | void |
2006 | atombios_set_mst_encoder_crtc_source(struct drm_encoder *encoder, int fe) | |
2007 | { | |
2008 | struct drm_device *dev = encoder->dev; | |
2009 | struct radeon_device *rdev = dev->dev_private; | |
2010 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); | |
2011 | int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source); | |
2012 | uint8_t frev, crev; | |
2013 | union crtc_source_param args; | |
2014 | ||
2015 | memset(&args, 0, sizeof(args)); | |
2016 | ||
2017 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) | |
2018 | return; | |
2019 | ||
2020 | if (frev != 1 && crev != 2) | |
2021 | DRM_ERROR("Unknown table for MST %d, %d\n", frev, crev); | |
2022 | ||
2023 | args.v2.ucCRTC = radeon_crtc->crtc_id; | |
2024 | args.v2.ucEncodeMode = ATOM_ENCODER_MODE_DP_MST; | |
2025 | ||
2026 | switch (fe) { | |
2027 | case 0: | |
2028 | args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID; | |
2029 | break; | |
2030 | case 1: | |
2031 | args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID; | |
2032 | break; | |
2033 | case 2: | |
2034 | args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID; | |
2035 | break; | |
2036 | case 3: | |
2037 | args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID; | |
2038 | break; | |
2039 | case 4: | |
2040 | args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID; | |
2041 | break; | |
2042 | case 5: | |
2043 | args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID; | |
2044 | break; | |
2045 | case 6: | |
2046 | args.v2.ucEncoderID = ASIC_INT_DIG7_ENCODER_ID; | |
2047 | break; | |
2048 | } | |
2049 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
2050 | } | |
2051 | ||
3f03ced8 AD |
2052 | static void |
2053 | atombios_apply_encoder_quirks(struct drm_encoder *encoder, | |
2054 | struct drm_display_mode *mode) | |
2055 | { | |
2056 | struct drm_device *dev = encoder->dev; | |
2057 | struct radeon_device *rdev = dev->dev_private; | |
2058 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
2059 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); | |
2060 | ||
2061 | /* Funky macbooks */ | |
2062 | if ((dev->pdev->device == 0x71C5) && | |
2063 | (dev->pdev->subsystem_vendor == 0x106b) && | |
2064 | (dev->pdev->subsystem_device == 0x0080)) { | |
2065 | if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) { | |
2066 | uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL); | |
2067 | ||
2068 | lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN; | |
2069 | lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN; | |
2070 | ||
2071 | WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control); | |
2072 | } | |
2073 | } | |
2074 | ||
2075 | /* set scaler clears this on some chips */ | |
2076 | if (ASIC_IS_AVIVO(rdev) && | |
2077 | (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) { | |
d798f2f2 AD |
2078 | if (ASIC_IS_DCE8(rdev)) { |
2079 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) | |
2080 | WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset, | |
2081 | CIK_INTERLEAVE_EN); | |
2082 | else | |
2083 | WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset, 0); | |
2084 | } else if (ASIC_IS_DCE4(rdev)) { | |
3f03ced8 AD |
2085 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) |
2086 | WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, | |
2087 | EVERGREEN_INTERLEAVE_EN); | |
2088 | else | |
2089 | WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0); | |
2090 | } else { | |
2091 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) | |
2092 | WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, | |
2093 | AVIVO_D1MODE_INTERLEAVE_EN); | |
2094 | else | |
2095 | WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0); | |
2096 | } | |
2097 | } | |
2098 | } | |
2099 | ||
8f0fc088 DA |
2100 | void radeon_atom_release_dig_encoder(struct radeon_device *rdev, int enc_idx) |
2101 | { | |
2102 | if (enc_idx < 0) | |
2103 | return; | |
2104 | rdev->mode_info.active_encoders &= ~(1 << enc_idx); | |
2105 | } | |
2106 | ||
2107 | int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder, int fe_idx) | |
3f03ced8 AD |
2108 | { |
2109 | struct drm_device *dev = encoder->dev; | |
2110 | struct radeon_device *rdev = dev->dev_private; | |
2111 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); | |
2112 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
2113 | struct drm_encoder *test_encoder; | |
41fa5437 | 2114 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
3f03ced8 | 2115 | uint32_t dig_enc_in_use = 0; |
8f0fc088 | 2116 | int enc_idx = -1; |
3f03ced8 | 2117 | |
8f0fc088 DA |
2118 | if (fe_idx >= 0) { |
2119 | enc_idx = fe_idx; | |
2120 | goto assigned; | |
2121 | } | |
41fa5437 AD |
2122 | if (ASIC_IS_DCE6(rdev)) { |
2123 | /* DCE6 */ | |
2124 | switch (radeon_encoder->encoder_id) { | |
2125 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: | |
2126 | if (dig->linkb) | |
8f0fc088 | 2127 | enc_idx = 1; |
41fa5437 | 2128 | else |
8f0fc088 | 2129 | enc_idx = 0; |
41fa5437 AD |
2130 | break; |
2131 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: | |
2132 | if (dig->linkb) | |
8f0fc088 | 2133 | enc_idx = 3; |
41fa5437 | 2134 | else |
8f0fc088 | 2135 | enc_idx = 2; |
41fa5437 AD |
2136 | break; |
2137 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: | |
2138 | if (dig->linkb) | |
8f0fc088 | 2139 | enc_idx = 5; |
41fa5437 | 2140 | else |
8f0fc088 | 2141 | enc_idx = 4; |
41fa5437 | 2142 | break; |
e68adef8 | 2143 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: |
8f0fc088 | 2144 | enc_idx = 6; |
e68adef8 | 2145 | break; |
41fa5437 | 2146 | } |
8f0fc088 | 2147 | goto assigned; |
41fa5437 AD |
2148 | } else if (ASIC_IS_DCE4(rdev)) { |
2149 | /* DCE4/5 */ | |
2150 | if (ASIC_IS_DCE41(rdev) && !ASIC_IS_DCE61(rdev)) { | |
3f03ced8 AD |
2151 | /* ontario follows DCE4 */ |
2152 | if (rdev->family == CHIP_PALM) { | |
2153 | if (dig->linkb) | |
8f0fc088 | 2154 | enc_idx = 1; |
3f03ced8 | 2155 | else |
8f0fc088 | 2156 | enc_idx = 0; |
3f03ced8 AD |
2157 | } else |
2158 | /* llano follows DCE3.2 */ | |
8f0fc088 | 2159 | enc_idx = radeon_crtc->crtc_id; |
3f03ced8 AD |
2160 | } else { |
2161 | switch (radeon_encoder->encoder_id) { | |
2162 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: | |
2163 | if (dig->linkb) | |
8f0fc088 | 2164 | enc_idx = 1; |
3f03ced8 | 2165 | else |
8f0fc088 | 2166 | enc_idx = 0; |
3f03ced8 AD |
2167 | break; |
2168 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: | |
2169 | if (dig->linkb) | |
8f0fc088 | 2170 | enc_idx = 3; |
3f03ced8 | 2171 | else |
8f0fc088 | 2172 | enc_idx = 2; |
3f03ced8 AD |
2173 | break; |
2174 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: | |
2175 | if (dig->linkb) | |
8f0fc088 | 2176 | enc_idx = 5; |
3f03ced8 | 2177 | else |
8f0fc088 | 2178 | enc_idx = 4; |
3f03ced8 AD |
2179 | break; |
2180 | } | |
2181 | } | |
8f0fc088 | 2182 | goto assigned; |
3f03ced8 AD |
2183 | } |
2184 | ||
2185 | /* on DCE32 and encoder can driver any block so just crtc id */ | |
2186 | if (ASIC_IS_DCE32(rdev)) { | |
8f0fc088 DA |
2187 | enc_idx = radeon_crtc->crtc_id; |
2188 | goto assigned; | |
3f03ced8 AD |
2189 | } |
2190 | ||
2191 | /* on DCE3 - LVTMA can only be driven by DIGB */ | |
2192 | list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) { | |
2193 | struct radeon_encoder *radeon_test_encoder; | |
2194 | ||
2195 | if (encoder == test_encoder) | |
2196 | continue; | |
2197 | ||
2198 | if (!radeon_encoder_is_digital(test_encoder)) | |
2199 | continue; | |
2200 | ||
2201 | radeon_test_encoder = to_radeon_encoder(test_encoder); | |
2202 | dig = radeon_test_encoder->enc_priv; | |
2203 | ||
2204 | if (dig->dig_encoder >= 0) | |
2205 | dig_enc_in_use |= (1 << dig->dig_encoder); | |
2206 | } | |
2207 | ||
2208 | if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) { | |
2209 | if (dig_enc_in_use & 0x2) | |
2210 | DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n"); | |
2211 | return 1; | |
2212 | } | |
2213 | if (!(dig_enc_in_use & 1)) | |
2214 | return 0; | |
2215 | return 1; | |
8f0fc088 DA |
2216 | |
2217 | assigned: | |
2218 | if (enc_idx == -1) { | |
2219 | DRM_ERROR("Got encoder index incorrect - returning 0\n"); | |
2220 | return 0; | |
2221 | } | |
2222 | if (rdev->mode_info.active_encoders & (1 << enc_idx)) { | |
2223 | DRM_ERROR("chosen encoder in use %d\n", enc_idx); | |
2224 | } | |
2225 | rdev->mode_info.active_encoders |= (1 << enc_idx); | |
2226 | return enc_idx; | |
3f03ced8 AD |
2227 | } |
2228 | ||
2229 | /* This only needs to be called once at startup */ | |
2230 | void | |
2231 | radeon_atom_encoder_init(struct radeon_device *rdev) | |
2232 | { | |
2233 | struct drm_device *dev = rdev->ddev; | |
2234 | struct drm_encoder *encoder; | |
2235 | ||
2236 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
2237 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
2238 | struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); | |
2239 | ||
2240 | switch (radeon_encoder->encoder_id) { | |
2241 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: | |
2242 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: | |
2243 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: | |
e68adef8 | 2244 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: |
3f03ced8 AD |
2245 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
2246 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0); | |
2247 | break; | |
2248 | default: | |
2249 | break; | |
2250 | } | |
2251 | ||
1d3949c4 | 2252 | if (ext_encoder && (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev))) |
3f03ced8 AD |
2253 | atombios_external_encoder_setup(encoder, ext_encoder, |
2254 | EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT); | |
2255 | } | |
2256 | } | |
2257 | ||
2258 | static void | |
2259 | radeon_atom_encoder_mode_set(struct drm_encoder *encoder, | |
2260 | struct drm_display_mode *mode, | |
2261 | struct drm_display_mode *adjusted_mode) | |
2262 | { | |
2263 | struct drm_device *dev = encoder->dev; | |
2264 | struct radeon_device *rdev = dev->dev_private; | |
2265 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
3473f542 | 2266 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); |
6f945693 | 2267 | int encoder_mode; |
3f03ced8 AD |
2268 | |
2269 | radeon_encoder->pixel_clock = adjusted_mode->clock; | |
2270 | ||
8d1af57a AD |
2271 | /* need to call this here rather than in prepare() since we need some crtc info */ |
2272 | radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); | |
2273 | ||
3f03ced8 AD |
2274 | if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) { |
2275 | if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT)) | |
2276 | atombios_yuv_setup(encoder, true); | |
2277 | else | |
2278 | atombios_yuv_setup(encoder, false); | |
2279 | } | |
2280 | ||
2281 | switch (radeon_encoder->encoder_id) { | |
2282 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: | |
2283 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: | |
2284 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: | |
2285 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: | |
2286 | atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE); | |
2287 | break; | |
2288 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: | |
2289 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: | |
2290 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: | |
e68adef8 | 2291 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: |
3f03ced8 | 2292 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
8d1af57a | 2293 | /* handled in dpms */ |
3f03ced8 AD |
2294 | break; |
2295 | case ENCODER_OBJECT_ID_INTERNAL_DDI: | |
2296 | case ENCODER_OBJECT_ID_INTERNAL_DVO1: | |
2297 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: | |
2298 | atombios_dvo_setup(encoder, ATOM_ENABLE); | |
2299 | break; | |
2300 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: | |
2301 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: | |
2302 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: | |
2303 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: | |
2304 | atombios_dac_setup(encoder, ATOM_ENABLE); | |
2305 | if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) { | |
2306 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) | |
2307 | atombios_tv_setup(encoder, ATOM_ENABLE); | |
2308 | else | |
2309 | atombios_tv_setup(encoder, ATOM_DISABLE); | |
2310 | } | |
2311 | break; | |
2312 | } | |
2313 | ||
3f03ced8 | 2314 | atombios_apply_encoder_quirks(encoder, adjusted_mode); |
5c046a57 AD |
2315 | |
2316 | encoder_mode = atombios_get_encoder_mode(encoder); | |
2317 | if (connector && (radeon_audio != 0) && | |
2318 | ((encoder_mode == ATOM_ENCODER_MODE_HDMI) || | |
7726e72b | 2319 | ENCODER_MODE_IS_DP(encoder_mode))) |
5c046a57 | 2320 | radeon_audio_mode_set(encoder, adjusted_mode); |
3f03ced8 AD |
2321 | } |
2322 | ||
2323 | static bool | |
2324 | atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector) | |
2325 | { | |
2326 | struct drm_device *dev = encoder->dev; | |
2327 | struct radeon_device *rdev = dev->dev_private; | |
2328 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
2329 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
2330 | ||
2331 | if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | | |
2332 | ATOM_DEVICE_CV_SUPPORT | | |
2333 | ATOM_DEVICE_CRT_SUPPORT)) { | |
2334 | DAC_LOAD_DETECTION_PS_ALLOCATION args; | |
2335 | int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection); | |
2336 | uint8_t frev, crev; | |
2337 | ||
2338 | memset(&args, 0, sizeof(args)); | |
2339 | ||
2340 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) | |
2341 | return false; | |
2342 | ||
2343 | args.sDacload.ucMisc = 0; | |
2344 | ||
2345 | if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) || | |
2346 | (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1)) | |
2347 | args.sDacload.ucDacType = ATOM_DAC_A; | |
2348 | else | |
2349 | args.sDacload.ucDacType = ATOM_DAC_B; | |
2350 | ||
2351 | if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) | |
2352 | args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT); | |
2353 | else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) | |
2354 | args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT); | |
2355 | else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { | |
2356 | args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT); | |
2357 | if (crev >= 3) | |
2358 | args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb; | |
2359 | } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { | |
2360 | args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT); | |
2361 | if (crev >= 3) | |
2362 | args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb; | |
2363 | } | |
2364 | ||
2365 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
2366 | ||
2367 | return true; | |
2368 | } else | |
2369 | return false; | |
2370 | } | |
2371 | ||
2372 | static enum drm_connector_status | |
2373 | radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector) | |
2374 | { | |
2375 | struct drm_device *dev = encoder->dev; | |
2376 | struct radeon_device *rdev = dev->dev_private; | |
2377 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
2378 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
2379 | uint32_t bios_0_scratch; | |
2380 | ||
2381 | if (!atombios_dac_load_detect(encoder, connector)) { | |
2382 | DRM_DEBUG_KMS("detect returned false \n"); | |
2383 | return connector_status_unknown; | |
2384 | } | |
2385 | ||
2386 | if (rdev->family >= CHIP_R600) | |
2387 | bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH); | |
2388 | else | |
2389 | bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH); | |
2390 | ||
2391 | DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices); | |
2392 | if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) { | |
2393 | if (bios_0_scratch & ATOM_S0_CRT1_MASK) | |
2394 | return connector_status_connected; | |
2395 | } | |
2396 | if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) { | |
2397 | if (bios_0_scratch & ATOM_S0_CRT2_MASK) | |
2398 | return connector_status_connected; | |
2399 | } | |
2400 | if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { | |
2401 | if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A)) | |
2402 | return connector_status_connected; | |
2403 | } | |
2404 | if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { | |
2405 | if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A)) | |
2406 | return connector_status_connected; /* CTV */ | |
2407 | else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A)) | |
2408 | return connector_status_connected; /* STV */ | |
2409 | } | |
2410 | return connector_status_disconnected; | |
2411 | } | |
2412 | ||
2413 | static enum drm_connector_status | |
2414 | radeon_atom_dig_detect(struct drm_encoder *encoder, struct drm_connector *connector) | |
2415 | { | |
2416 | struct drm_device *dev = encoder->dev; | |
2417 | struct radeon_device *rdev = dev->dev_private; | |
2418 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
2419 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
2420 | struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); | |
2421 | u32 bios_0_scratch; | |
2422 | ||
2423 | if (!ASIC_IS_DCE4(rdev)) | |
2424 | return connector_status_unknown; | |
2425 | ||
2426 | if (!ext_encoder) | |
2427 | return connector_status_unknown; | |
2428 | ||
2429 | if ((radeon_connector->devices & ATOM_DEVICE_CRT_SUPPORT) == 0) | |
2430 | return connector_status_unknown; | |
2431 | ||
2432 | /* load detect on the dp bridge */ | |
2433 | atombios_external_encoder_setup(encoder, ext_encoder, | |
2434 | EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION); | |
2435 | ||
2436 | bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH); | |
2437 | ||
2438 | DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices); | |
2439 | if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) { | |
2440 | if (bios_0_scratch & ATOM_S0_CRT1_MASK) | |
2441 | return connector_status_connected; | |
2442 | } | |
2443 | if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) { | |
2444 | if (bios_0_scratch & ATOM_S0_CRT2_MASK) | |
2445 | return connector_status_connected; | |
2446 | } | |
2447 | if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { | |
2448 | if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A)) | |
2449 | return connector_status_connected; | |
2450 | } | |
2451 | if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { | |
2452 | if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A)) | |
2453 | return connector_status_connected; /* CTV */ | |
2454 | else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A)) | |
2455 | return connector_status_connected; /* STV */ | |
2456 | } | |
2457 | return connector_status_disconnected; | |
2458 | } | |
2459 | ||
2460 | void | |
2461 | radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder) | |
2462 | { | |
2463 | struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); | |
2464 | ||
2465 | if (ext_encoder) | |
2466 | /* ddc_setup on the dp bridge */ | |
2467 | atombios_external_encoder_setup(encoder, ext_encoder, | |
2468 | EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP); | |
2469 | ||
2470 | } | |
2471 | ||
2472 | static void radeon_atom_encoder_prepare(struct drm_encoder *encoder) | |
2473 | { | |
cfcbd6d3 | 2474 | struct radeon_device *rdev = encoder->dev->dev_private; |
3f03ced8 AD |
2475 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
2476 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); | |
2477 | ||
2478 | if ((radeon_encoder->active_device & | |
2479 | (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) || | |
2480 | (radeon_encoder_get_dp_bridge_encoder_id(encoder) != | |
2481 | ENCODER_OBJECT_ID_NONE)) { | |
2482 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; | |
cfcbd6d3 | 2483 | if (dig) { |
8f0fc088 DA |
2484 | if (dig->dig_encoder >= 0) |
2485 | radeon_atom_release_dig_encoder(rdev, dig->dig_encoder); | |
2486 | dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder, -1); | |
cfcbd6d3 RM |
2487 | if (radeon_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) { |
2488 | if (rdev->family >= CHIP_R600) | |
2489 | dig->afmt = rdev->mode_info.afmt[dig->dig_encoder]; | |
2490 | else | |
2491 | /* RS600/690/740 have only 1 afmt block */ | |
2492 | dig->afmt = rdev->mode_info.afmt[0]; | |
2493 | } | |
2494 | } | |
3f03ced8 AD |
2495 | } |
2496 | ||
2497 | radeon_atom_output_lock(encoder, true); | |
3f03ced8 AD |
2498 | |
2499 | if (connector) { | |
2500 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
2501 | ||
2502 | /* select the clock/data port if it uses a router */ | |
2503 | if (radeon_connector->router.cd_valid) | |
2504 | radeon_router_select_cd_port(radeon_connector); | |
2505 | ||
2506 | /* turn eDP panel on for mode set */ | |
2507 | if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) | |
2508 | atombios_set_edp_panel_power(connector, | |
2509 | ATOM_TRANSMITTER_ACTION_POWER_ON); | |
2510 | } | |
2511 | ||
2512 | /* this is needed for the pll/ss setup to work correctly in some cases */ | |
2513 | atombios_set_encoder_crtc_source(encoder); | |
134b480f AD |
2514 | /* set up the FMT blocks */ |
2515 | if (ASIC_IS_DCE8(rdev)) | |
2516 | dce8_program_fmt(encoder); | |
2517 | else if (ASIC_IS_DCE4(rdev)) | |
2518 | dce4_program_fmt(encoder); | |
2519 | else if (ASIC_IS_DCE3(rdev)) | |
2520 | dce3_program_fmt(encoder); | |
2521 | else if (ASIC_IS_AVIVO(rdev)) | |
2522 | avivo_program_fmt(encoder); | |
3f03ced8 AD |
2523 | } |
2524 | ||
2525 | static void radeon_atom_encoder_commit(struct drm_encoder *encoder) | |
2526 | { | |
8d1af57a | 2527 | /* need to call this here as we need the crtc set up */ |
3f03ced8 AD |
2528 | radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON); |
2529 | radeon_atom_output_lock(encoder, false); | |
2530 | } | |
2531 | ||
2532 | static void radeon_atom_encoder_disable(struct drm_encoder *encoder) | |
2533 | { | |
2534 | struct drm_device *dev = encoder->dev; | |
2535 | struct radeon_device *rdev = dev->dev_private; | |
2536 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
2537 | struct radeon_encoder_atom_dig *dig; | |
2538 | ||
2539 | /* check for pre-DCE3 cards with shared encoders; | |
2540 | * can't really use the links individually, so don't disable | |
2541 | * the encoder if it's in use by another connector | |
2542 | */ | |
2543 | if (!ASIC_IS_DCE3(rdev)) { | |
2544 | struct drm_encoder *other_encoder; | |
2545 | struct radeon_encoder *other_radeon_encoder; | |
2546 | ||
2547 | list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) { | |
2548 | other_radeon_encoder = to_radeon_encoder(other_encoder); | |
2549 | if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) && | |
2550 | drm_helper_encoder_in_use(other_encoder)) | |
2551 | goto disable_done; | |
2552 | } | |
2553 | } | |
2554 | ||
2555 | radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); | |
2556 | ||
2557 | switch (radeon_encoder->encoder_id) { | |
2558 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: | |
2559 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: | |
2560 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: | |
2561 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: | |
2562 | atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE); | |
2563 | break; | |
2564 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: | |
2565 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: | |
2566 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: | |
e68adef8 | 2567 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: |
3f03ced8 | 2568 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
8d1af57a | 2569 | /* handled in dpms */ |
3f03ced8 AD |
2570 | break; |
2571 | case ENCODER_OBJECT_ID_INTERNAL_DDI: | |
2572 | case ENCODER_OBJECT_ID_INTERNAL_DVO1: | |
2573 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: | |
2574 | atombios_dvo_setup(encoder, ATOM_DISABLE); | |
2575 | break; | |
2576 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: | |
2577 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: | |
2578 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: | |
2579 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: | |
2580 | atombios_dac_setup(encoder, ATOM_DISABLE); | |
2581 | if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) | |
2582 | atombios_tv_setup(encoder, ATOM_DISABLE); | |
2583 | break; | |
2584 | } | |
2585 | ||
2586 | disable_done: | |
2587 | if (radeon_encoder_is_digital(encoder)) { | |
8f0fc088 DA |
2588 | if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) { |
2589 | if (rdev->asic->display.hdmi_enable) | |
2590 | radeon_hdmi_enable(rdev, encoder, false); | |
2591 | } | |
2592 | if (atombios_get_encoder_mode(encoder) != ATOM_ENCODER_MODE_DP_MST) { | |
2593 | dig = radeon_encoder->enc_priv; | |
2594 | radeon_atom_release_dig_encoder(rdev, dig->dig_encoder); | |
2595 | dig->dig_encoder = -1; | |
2596 | radeon_encoder->active_device = 0; | |
2597 | } | |
2598 | } else | |
2599 | radeon_encoder->active_device = 0; | |
3f03ced8 AD |
2600 | } |
2601 | ||
2602 | /* these are handled by the primary encoders */ | |
2603 | static void radeon_atom_ext_prepare(struct drm_encoder *encoder) | |
2604 | { | |
2605 | ||
2606 | } | |
2607 | ||
2608 | static void radeon_atom_ext_commit(struct drm_encoder *encoder) | |
2609 | { | |
2610 | ||
2611 | } | |
2612 | ||
2613 | static void | |
2614 | radeon_atom_ext_mode_set(struct drm_encoder *encoder, | |
2615 | struct drm_display_mode *mode, | |
2616 | struct drm_display_mode *adjusted_mode) | |
2617 | { | |
2618 | ||
2619 | } | |
2620 | ||
2621 | static void radeon_atom_ext_disable(struct drm_encoder *encoder) | |
2622 | { | |
2623 | ||
2624 | } | |
2625 | ||
2626 | static void | |
2627 | radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode) | |
2628 | { | |
2629 | ||
2630 | } | |
2631 | ||
3f03ced8 AD |
2632 | static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = { |
2633 | .dpms = radeon_atom_ext_dpms, | |
3f03ced8 AD |
2634 | .prepare = radeon_atom_ext_prepare, |
2635 | .mode_set = radeon_atom_ext_mode_set, | |
2636 | .commit = radeon_atom_ext_commit, | |
2637 | .disable = radeon_atom_ext_disable, | |
2638 | /* no detect for TMDS/LVDS yet */ | |
2639 | }; | |
2640 | ||
2641 | static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = { | |
2642 | .dpms = radeon_atom_encoder_dpms, | |
2643 | .mode_fixup = radeon_atom_mode_fixup, | |
2644 | .prepare = radeon_atom_encoder_prepare, | |
2645 | .mode_set = radeon_atom_encoder_mode_set, | |
2646 | .commit = radeon_atom_encoder_commit, | |
2647 | .disable = radeon_atom_encoder_disable, | |
2648 | .detect = radeon_atom_dig_detect, | |
2649 | }; | |
2650 | ||
2651 | static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = { | |
2652 | .dpms = radeon_atom_encoder_dpms, | |
2653 | .mode_fixup = radeon_atom_mode_fixup, | |
2654 | .prepare = radeon_atom_encoder_prepare, | |
2655 | .mode_set = radeon_atom_encoder_mode_set, | |
2656 | .commit = radeon_atom_encoder_commit, | |
2657 | .detect = radeon_atom_dac_detect, | |
2658 | }; | |
2659 | ||
2660 | void radeon_enc_destroy(struct drm_encoder *encoder) | |
2661 | { | |
2662 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
f3728734 AD |
2663 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) |
2664 | radeon_atom_backlight_exit(radeon_encoder); | |
3f03ced8 AD |
2665 | kfree(radeon_encoder->enc_priv); |
2666 | drm_encoder_cleanup(encoder); | |
2667 | kfree(radeon_encoder); | |
2668 | } | |
2669 | ||
2670 | static const struct drm_encoder_funcs radeon_atom_enc_funcs = { | |
2671 | .destroy = radeon_enc_destroy, | |
2672 | }; | |
2673 | ||
1109ca09 | 2674 | static struct radeon_encoder_atom_dac * |
3f03ced8 AD |
2675 | radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder) |
2676 | { | |
2677 | struct drm_device *dev = radeon_encoder->base.dev; | |
2678 | struct radeon_device *rdev = dev->dev_private; | |
2679 | struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL); | |
2680 | ||
2681 | if (!dac) | |
2682 | return NULL; | |
2683 | ||
2684 | dac->tv_std = radeon_atombios_get_tv_info(rdev); | |
2685 | return dac; | |
2686 | } | |
2687 | ||
1109ca09 | 2688 | static struct radeon_encoder_atom_dig * |
3f03ced8 AD |
2689 | radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder) |
2690 | { | |
2691 | int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT; | |
2692 | struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL); | |
2693 | ||
2694 | if (!dig) | |
2695 | return NULL; | |
2696 | ||
2697 | /* coherent mode by default */ | |
2698 | dig->coherent_mode = true; | |
2699 | dig->dig_encoder = -1; | |
2700 | ||
2701 | if (encoder_enum == 2) | |
2702 | dig->linkb = true; | |
2703 | else | |
2704 | dig->linkb = false; | |
2705 | ||
2706 | return dig; | |
2707 | } | |
2708 | ||
2709 | void | |
2710 | radeon_add_atom_encoder(struct drm_device *dev, | |
2711 | uint32_t encoder_enum, | |
2712 | uint32_t supported_device, | |
2713 | u16 caps) | |
2714 | { | |
2715 | struct radeon_device *rdev = dev->dev_private; | |
2716 | struct drm_encoder *encoder; | |
2717 | struct radeon_encoder *radeon_encoder; | |
2718 | ||
2719 | /* see if we already added it */ | |
2720 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
2721 | radeon_encoder = to_radeon_encoder(encoder); | |
2722 | if (radeon_encoder->encoder_enum == encoder_enum) { | |
2723 | radeon_encoder->devices |= supported_device; | |
2724 | return; | |
2725 | } | |
2726 | ||
2727 | } | |
2728 | ||
2729 | /* add a new one */ | |
2730 | radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL); | |
2731 | if (!radeon_encoder) | |
2732 | return; | |
2733 | ||
2734 | encoder = &radeon_encoder->base; | |
2735 | switch (rdev->num_crtc) { | |
2736 | case 1: | |
2737 | encoder->possible_crtcs = 0x1; | |
2738 | break; | |
2739 | case 2: | |
2740 | default: | |
2741 | encoder->possible_crtcs = 0x3; | |
2742 | break; | |
2743 | case 4: | |
2744 | encoder->possible_crtcs = 0xf; | |
2745 | break; | |
2746 | case 6: | |
2747 | encoder->possible_crtcs = 0x3f; | |
2748 | break; | |
2749 | } | |
2750 | ||
2751 | radeon_encoder->enc_priv = NULL; | |
2752 | ||
2753 | radeon_encoder->encoder_enum = encoder_enum; | |
2754 | radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; | |
2755 | radeon_encoder->devices = supported_device; | |
2756 | radeon_encoder->rmx_type = RMX_OFF; | |
2757 | radeon_encoder->underscan_type = UNDERSCAN_OFF; | |
2758 | radeon_encoder->is_ext_encoder = false; | |
2759 | radeon_encoder->caps = caps; | |
2760 | ||
2761 | switch (radeon_encoder->encoder_id) { | |
2762 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: | |
2763 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: | |
2764 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: | |
2765 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: | |
2766 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { | |
2767 | radeon_encoder->rmx_type = RMX_FULL; | |
13a3d91f VS |
2768 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, |
2769 | DRM_MODE_ENCODER_LVDS, NULL); | |
3f03ced8 AD |
2770 | radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder); |
2771 | } else { | |
13a3d91f VS |
2772 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, |
2773 | DRM_MODE_ENCODER_TMDS, NULL); | |
3f03ced8 AD |
2774 | radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); |
2775 | } | |
2776 | drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs); | |
2777 | break; | |
2778 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: | |
13a3d91f VS |
2779 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, |
2780 | DRM_MODE_ENCODER_DAC, NULL); | |
3f03ced8 AD |
2781 | radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder); |
2782 | drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs); | |
2783 | break; | |
2784 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: | |
2785 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: | |
2786 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: | |
13a3d91f VS |
2787 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, |
2788 | DRM_MODE_ENCODER_TVDAC, NULL); | |
3f03ced8 AD |
2789 | radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder); |
2790 | drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs); | |
2791 | break; | |
2792 | case ENCODER_OBJECT_ID_INTERNAL_DVO1: | |
2793 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: | |
2794 | case ENCODER_OBJECT_ID_INTERNAL_DDI: | |
2795 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: | |
2796 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: | |
2797 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: | |
2798 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: | |
e68adef8 | 2799 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: |
3f03ced8 AD |
2800 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { |
2801 | radeon_encoder->rmx_type = RMX_FULL; | |
13a3d91f VS |
2802 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, |
2803 | DRM_MODE_ENCODER_LVDS, NULL); | |
3f03ced8 AD |
2804 | radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder); |
2805 | } else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) { | |
13a3d91f VS |
2806 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, |
2807 | DRM_MODE_ENCODER_DAC, NULL); | |
3f03ced8 AD |
2808 | radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); |
2809 | } else { | |
13a3d91f VS |
2810 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, |
2811 | DRM_MODE_ENCODER_TMDS, NULL); | |
3f03ced8 AD |
2812 | radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); |
2813 | } | |
2814 | drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs); | |
2815 | break; | |
2816 | case ENCODER_OBJECT_ID_SI170B: | |
2817 | case ENCODER_OBJECT_ID_CH7303: | |
2818 | case ENCODER_OBJECT_ID_EXTERNAL_SDVOA: | |
2819 | case ENCODER_OBJECT_ID_EXTERNAL_SDVOB: | |
2820 | case ENCODER_OBJECT_ID_TITFP513: | |
2821 | case ENCODER_OBJECT_ID_VT1623: | |
2822 | case ENCODER_OBJECT_ID_HDMI_SI1930: | |
2823 | case ENCODER_OBJECT_ID_TRAVIS: | |
2824 | case ENCODER_OBJECT_ID_NUTMEG: | |
2825 | /* these are handled by the primary encoders */ | |
2826 | radeon_encoder->is_ext_encoder = true; | |
2827 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) | |
13a3d91f VS |
2828 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, |
2829 | DRM_MODE_ENCODER_LVDS, NULL); | |
3f03ced8 | 2830 | else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) |
13a3d91f VS |
2831 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, |
2832 | DRM_MODE_ENCODER_DAC, NULL); | |
3f03ced8 | 2833 | else |
13a3d91f VS |
2834 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, |
2835 | DRM_MODE_ENCODER_TMDS, NULL); | |
3f03ced8 AD |
2836 | drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs); |
2837 | break; | |
2838 | } | |
2839 | } |