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Merge tag 'batman-adv-fix-for-davem' of git://git.open-mesh.org/linux-merge
[deliverable/linux.git] / drivers / gpu / drm / radeon / atombios_encoders.c
CommitLineData
3f03ced8
AD		 1/*
2 * Copyright 2007-11 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
760285e7
DH		 26#include <drm/drmP.h>
27#include <drm/drm_crtc_helper.h>
28#include <drm/radeon_drm.h>
3f03ced8
AD		 29#include "radeon.h"
30#include "atom.h"
f3728734 31#include <linux/backlight.h>
3f03ced8
AD		 32
33extern int atom_debug;
34
f3728734
AD		 35static u8
36radeon_atom_get_backlight_level_from_reg(struct radeon_device *rdev)
37{
38 u8 backlight_level;
39 u32 bios_2_scratch;
40
41 if (rdev->family >= CHIP_R600)
42 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
43 else
44 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
45
46 backlight_level = ((bios_2_scratch & ATOM_S2_CURRENT_BL_LEVEL_MASK) >>
47 ATOM_S2_CURRENT_BL_LEVEL_SHIFT);
48
49 return backlight_level;
50}
51
52static void
53radeon_atom_set_backlight_level_to_reg(struct radeon_device *rdev,
54 u8 backlight_level)
55{
56 u32 bios_2_scratch;
57
58 if (rdev->family >= CHIP_R600)
59 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
60 else
61 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
62
63 bios_2_scratch &= ~ATOM_S2_CURRENT_BL_LEVEL_MASK;
64 bios_2_scratch |= ((backlight_level << ATOM_S2_CURRENT_BL_LEVEL_SHIFT) &
65 ATOM_S2_CURRENT_BL_LEVEL_MASK);
66
67 if (rdev->family >= CHIP_R600)
68 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
69 else
70 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
71}
72
6d92f81d
AD		 73u8
74atombios_get_backlight_level(struct radeon_encoder *radeon_encoder)
75{
76 struct drm_device *dev = radeon_encoder->base.dev;
77 struct radeon_device *rdev = dev->dev_private;
78
79 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
80 return 0;
81
82 return radeon_atom_get_backlight_level_from_reg(rdev);
83}
84
fda4b25c 85void
37e9b6a6 86atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level)
f3728734
AD		 87{
88 struct drm_encoder *encoder = &radeon_encoder->base;
89 struct drm_device *dev = radeon_encoder->base.dev;
90 struct radeon_device *rdev = dev->dev_private;
91 struct radeon_encoder_atom_dig *dig;
92 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
93 int index;
94
37e9b6a6
AD		 95 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
96 return;
97
98 if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) &&
99 radeon_encoder->enc_priv) {
f3728734 100 dig = radeon_encoder->enc_priv;
37e9b6a6 101 dig->backlight_level = level;
f3728734
AD		 102 radeon_atom_set_backlight_level_to_reg(rdev, dig->backlight_level);
103
104 switch (radeon_encoder->encoder_id) {
105 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
106 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
107 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
108 if (dig->backlight_level == 0) {
109 args.ucAction = ATOM_LCD_BLOFF;
110 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
111 } else {
112 args.ucAction = ATOM_LCD_BL_BRIGHTNESS_CONTROL;
113 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
114 args.ucAction = ATOM_LCD_BLON;
115 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
116 }
117 break;
118 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
119 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
120 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
121 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
122 if (dig->backlight_level == 0)
123 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
124 else {
125 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL, 0, 0);
126 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
127 }
128 break;
129 default:
130 break;
131 }
132 }
133}
134
bced76f2
AD		 135#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
136
f3728734
AD		 137static u8 radeon_atom_bl_level(struct backlight_device *bd)
138{
139 u8 level;
140
141 /* Convert brightness to hardware level */
142 if (bd->props.brightness < 0)
143 level = 0;
144 else if (bd->props.brightness > RADEON_MAX_BL_LEVEL)
145 level = RADEON_MAX_BL_LEVEL;
146 else
147 level = bd->props.brightness;
148
149 return level;
150}
151
152static int radeon_atom_backlight_update_status(struct backlight_device *bd)
153{
154 struct radeon_backlight_privdata *pdata = bl_get_data(bd);
155 struct radeon_encoder *radeon_encoder = pdata->encoder;
156
37e9b6a6 157 atombios_set_backlight_level(radeon_encoder, radeon_atom_bl_level(bd));
f3728734
AD		 158
159 return 0;
160}
161
162static int radeon_atom_backlight_get_brightness(struct backlight_device *bd)
163{
164 struct radeon_backlight_privdata *pdata = bl_get_data(bd);
165 struct radeon_encoder *radeon_encoder = pdata->encoder;
166 struct drm_device *dev = radeon_encoder->base.dev;
167 struct radeon_device *rdev = dev->dev_private;
168
169 return radeon_atom_get_backlight_level_from_reg(rdev);
170}
171
172static const struct backlight_ops radeon_atom_backlight_ops = {
173 .get_brightness = radeon_atom_backlight_get_brightness,
174 .update_status = radeon_atom_backlight_update_status,
175};
176
177void radeon_atom_backlight_init(struct radeon_encoder *radeon_encoder,
178 struct drm_connector *drm_connector)
179{
180 struct drm_device *dev = radeon_encoder->base.dev;
181 struct radeon_device *rdev = dev->dev_private;
182 struct backlight_device *bd;
183 struct backlight_properties props;
184 struct radeon_backlight_privdata *pdata;
185 struct radeon_encoder_atom_dig *dig;
186 u8 backlight_level;
614499b4 187 char bl_name[16];
f3728734
AD		 188
189 if (!radeon_encoder->enc_priv)
190 return;
191
192 if (!rdev->is_atom_bios)
193 return;
194
195 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
196 return;
197
198 pdata = kmalloc(sizeof(struct radeon_backlight_privdata), GFP_KERNEL);
199 if (!pdata) {
200 DRM_ERROR("Memory allocation failed\n");
201 goto error;
202 }
203
204 memset(&props, 0, sizeof(props));
205 props.max_brightness = RADEON_MAX_BL_LEVEL;
206 props.type = BACKLIGHT_RAW;
614499b4
AD		 207 snprintf(bl_name, sizeof(bl_name),
208 "radeon_bl%d", dev->primary->index);
209 bd = backlight_device_register(bl_name, &drm_connector->kdev,
f3728734
AD		 210 pdata, &radeon_atom_backlight_ops, &props);
211 if (IS_ERR(bd)) {
212 DRM_ERROR("Backlight registration failed\n");
213 goto error;
214 }
215
216 pdata->encoder = radeon_encoder;
217
218 backlight_level = radeon_atom_get_backlight_level_from_reg(rdev);
219
220 dig = radeon_encoder->enc_priv;
221 dig->bl_dev = bd;
222
223 bd->props.brightness = radeon_atom_backlight_get_brightness(bd);
224 bd->props.power = FB_BLANK_UNBLANK;
225 backlight_update_status(bd);
226
227 DRM_INFO("radeon atom DIG backlight initialized\n");
228
229 return;
230
231error:
232 kfree(pdata);
233 return;
234}
235
236static void radeon_atom_backlight_exit(struct radeon_encoder *radeon_encoder)
237{
238 struct drm_device *dev = radeon_encoder->base.dev;
239 struct radeon_device *rdev = dev->dev_private;
240 struct backlight_device *bd = NULL;
241 struct radeon_encoder_atom_dig *dig;
242
243 if (!radeon_encoder->enc_priv)
244 return;
245
246 if (!rdev->is_atom_bios)
247 return;
248
249 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
250 return;
251
252 dig = radeon_encoder->enc_priv;
253 bd = dig->bl_dev;
254 dig->bl_dev = NULL;
255
256 if (bd) {
257 struct radeon_legacy_backlight_privdata *pdata;
258
259 pdata = bl_get_data(bd);
260 backlight_device_unregister(bd);
261 kfree(pdata);
262
263 DRM_INFO("radeon atom LVDS backlight unloaded\n");
264 }
265}
266
267#else /* !CONFIG_BACKLIGHT_CLASS_DEVICE */
268
269void radeon_atom_backlight_init(struct radeon_encoder *encoder)
270{
271}
272
273static void radeon_atom_backlight_exit(struct radeon_encoder *encoder)
274{
275}
276
277#endif
278
3f03ced8
AD		 279/* evil but including atombios.h is much worse */
280bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
281 struct drm_display_mode *mode);
282
283
284static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder)
285{
286 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
287 switch (radeon_encoder->encoder_id) {
288 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
289 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
290 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
291 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
292 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
293 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
294 case ENCODER_OBJECT_ID_INTERNAL_DDI:
295 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
296 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
297 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
298 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
299 return true;
300 default:
301 return false;
302 }
303}
304
3f03ced8 305static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
e811f5ae 306 const struct drm_display_mode *mode,
3f03ced8
AD		 307 struct drm_display_mode *adjusted_mode)
308{
309 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
310 struct drm_device *dev = encoder->dev;
311 struct radeon_device *rdev = dev->dev_private;
312
313 /* set the active encoder to connector routing */
314 radeon_encoder_set_active_device(encoder);
315 drm_mode_set_crtcinfo(adjusted_mode, 0);
316
317 /* hw bug */
318 if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
319 && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
320 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
321
322 /* get the native mode for LVDS */
323 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT))
324 radeon_panel_mode_fixup(encoder, adjusted_mode);
325
326 /* get the native mode for TV */
327 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
328 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
329 if (tv_dac) {
330 if (tv_dac->tv_std == TV_STD_NTSC ||
331 tv_dac->tv_std == TV_STD_NTSC_J ||
332 tv_dac->tv_std == TV_STD_PAL_M)
333 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
334 else
335 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
336 }
337 }
338
339 if (ASIC_IS_DCE3(rdev) &&
340 ((radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
341 (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE))) {
342 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
93927f9c 343 radeon_dp_set_link_config(connector, adjusted_mode);
3f03ced8
AD		 344 }
345
346 return true;
347}
348
349static void
350atombios_dac_setup(struct drm_encoder *encoder, int action)
351{
352 struct drm_device *dev = encoder->dev;
353 struct radeon_device *rdev = dev->dev_private;
354 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
355 DAC_ENCODER_CONTROL_PS_ALLOCATION args;
356 int index = 0;
357 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
358
359 memset(&args, 0, sizeof(args));
360
361 switch (radeon_encoder->encoder_id) {
362 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
363 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
364 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
365 break;
366 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
367 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
368 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
369 break;
370 }
371
372 args.ucAction = action;
373
374 if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
375 args.ucDacStandard = ATOM_DAC1_PS2;
376 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
377 args.ucDacStandard = ATOM_DAC1_CV;
378 else {
379 switch (dac_info->tv_std) {
380 case TV_STD_PAL:
381 case TV_STD_PAL_M:
382 case TV_STD_SCART_PAL:
383 case TV_STD_SECAM:
384 case TV_STD_PAL_CN:
385 args.ucDacStandard = ATOM_DAC1_PAL;
386 break;
387 case TV_STD_NTSC:
388 case TV_STD_NTSC_J:
389 case TV_STD_PAL_60:
390 default:
391 args.ucDacStandard = ATOM_DAC1_NTSC;
392 break;
393 }
394 }
395 args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
396
397 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
398
399}
400
401static void
402atombios_tv_setup(struct drm_encoder *encoder, int action)
403{
404 struct drm_device *dev = encoder->dev;
405 struct radeon_device *rdev = dev->dev_private;
406 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
407 TV_ENCODER_CONTROL_PS_ALLOCATION args;
408 int index = 0;
409 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
410
411 memset(&args, 0, sizeof(args));
412
413 index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
414
415 args.sTVEncoder.ucAction = action;
416
417 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
418 args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
419 else {
420 switch (dac_info->tv_std) {
421 case TV_STD_NTSC:
422 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
423 break;
424 case TV_STD_PAL:
425 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
426 break;
427 case TV_STD_PAL_M:
428 args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
429 break;
430 case TV_STD_PAL_60:
431 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
432 break;
433 case TV_STD_NTSC_J:
434 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
435 break;
436 case TV_STD_SCART_PAL:
437 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
438 break;
439 case TV_STD_SECAM:
440 args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
441 break;
442 case TV_STD_PAL_CN:
443 args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
444 break;
445 default:
446 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
447 break;
448 }
449 }
450
451 args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
452
453 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
454
455}
456
1f0e2943
AD		 457static u8 radeon_atom_get_bpc(struct drm_encoder *encoder)
458{
459 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
460 int bpc = 8;
461
462 if (connector)
463 bpc = radeon_get_monitor_bpc(connector);
464
465 switch (bpc) {
466 case 0:
467 return PANEL_BPC_UNDEFINE;
468 case 6:
469 return PANEL_6BIT_PER_COLOR;
470 case 8:
471 default:
472 return PANEL_8BIT_PER_COLOR;
473 case 10:
474 return PANEL_10BIT_PER_COLOR;
475 case 12:
476 return PANEL_12BIT_PER_COLOR;
477 case 16:
478 return PANEL_16BIT_PER_COLOR;
479 }
480}
481
482
3f03ced8
AD		 483union dvo_encoder_control {
484 ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds;
485 DVO_ENCODER_CONTROL_PS_ALLOCATION dvo;
486 DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3;
487};
488
489void
490atombios_dvo_setup(struct drm_encoder *encoder, int action)
491{
492 struct drm_device *dev = encoder->dev;
493 struct radeon_device *rdev = dev->dev_private;
494 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
495 union dvo_encoder_control args;
496 int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
24153dd3 497 uint8_t frev, crev;
3f03ced8
AD		 498
499 memset(&args, 0, sizeof(args));
500
24153dd3
AD		 501 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
502 return;
503
afceb931
AD		 504 /* some R4xx chips have the wrong frev */
505 if (rdev->family <= CHIP_RV410)
506 frev = 1;
507
24153dd3
AD		 508 switch (frev) {
509 case 1:
510 switch (crev) {
511 case 1:
512 /* R4xx, R5xx */
513 args.ext_tmds.sXTmdsEncoder.ucEnable = action;
514
9aa59993 515 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
24153dd3
AD		 516 args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL;
517
518 args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB;
519 break;
520 case 2:
521 /* RS600/690/740 */
522 args.dvo.sDVOEncoder.ucAction = action;
523 args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
524 /* DFP1, CRT1, TV1 depending on the type of port */
525 args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX;
526
9aa59993 527 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
24153dd3
AD		 528 args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL;
529 break;
530 case 3:
531 /* R6xx */
532 args.dvo_v3.ucAction = action;
533 args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
534 args.dvo_v3.ucDVOConfig = 0; /* XXX */
535 break;
536 default:
537 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
538 break;
539 }
540 break;
541 default:
542 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
543 break;
3f03ced8
AD		 544 }
545
546 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
547}
548
549union lvds_encoder_control {
550 LVDS_ENCODER_CONTROL_PS_ALLOCATION v1;
551 LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
552};
553
554void
555atombios_digital_setup(struct drm_encoder *encoder, int action)
556{
557 struct drm_device *dev = encoder->dev;
558 struct radeon_device *rdev = dev->dev_private;
559 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
560 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
561 union lvds_encoder_control args;
562 int index = 0;
563 int hdmi_detected = 0;
564 uint8_t frev, crev;
565
566 if (!dig)
567 return;
568
569 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
570 hdmi_detected = 1;
571
572 memset(&args, 0, sizeof(args));
573
574 switch (radeon_encoder->encoder_id) {
575 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
576 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
577 break;
578 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
579 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
580 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
581 break;
582 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
583 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
584 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
585 else
586 index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
587 break;
588 }
589
590 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
591 return;
592
593 switch (frev) {
594 case 1:
595 case 2:
596 switch (crev) {
597 case 1:
598 args.v1.ucMisc = 0;
599 args.v1.ucAction = action;
600 if (hdmi_detected)
601 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
602 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
603 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
604 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
605 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
606 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
607 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
608 } else {
609 if (dig->linkb)
610 args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
9aa59993 611 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
3f03ced8
AD		 612 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
613 /*if (pScrn->rgbBits == 8) */
614 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
615 }
616 break;
617 case 2:
618 case 3:
619 args.v2.ucMisc = 0;
620 args.v2.ucAction = action;
621 if (crev == 3) {
622 if (dig->coherent_mode)
623 args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
624 }
625 if (hdmi_detected)
626 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
627 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
628 args.v2.ucTruncate = 0;
629 args.v2.ucSpatial = 0;
630 args.v2.ucTemporal = 0;
631 args.v2.ucFRC = 0;
632 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
633 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
634 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
635 if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) {
636 args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
637 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
638 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
639 }
640 if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) {
641 args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
642 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
643 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
644 if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2)
645 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
646 }
647 } else {
648 if (dig->linkb)
649 args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
9aa59993 650 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
3f03ced8
AD		 651 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
652 }
653 break;
654 default:
655 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
656 break;
657 }
658 break;
659 default:
660 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
661 break;
662 }
663
664 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
665}
666
667int
668atombios_get_encoder_mode(struct drm_encoder *encoder)
669{
1cbcca30
AD		 670 struct drm_device *dev = encoder->dev;
671 struct radeon_device *rdev = dev->dev_private;
3f03ced8 672 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3f03ced8
AD		 673 struct drm_connector *connector;
674 struct radeon_connector *radeon_connector;
675 struct radeon_connector_atom_dig *dig_connector;
676
677 /* dp bridges are always DP */
678 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)
679 return ATOM_ENCODER_MODE_DP;
680
681 /* DVO is always DVO */
a59fbb8e
AD		 682 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DVO1) ||
683 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1))
3f03ced8
AD		 684 return ATOM_ENCODER_MODE_DVO;
685
686 connector = radeon_get_connector_for_encoder(encoder);
687 /* if we don't have an active device yet, just use one of
688 * the connectors tied to the encoder.
689 */
690 if (!connector)
691 connector = radeon_get_connector_for_encoder_init(encoder);
692 radeon_connector = to_radeon_connector(connector);
693
694 switch (connector->connector_type) {
695 case DRM_MODE_CONNECTOR_DVII:
696 case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
27d9cc84 697 if (drm_detect_hdmi_monitor(radeon_connector->edid) &&
1cbcca30
AD		 698 radeon_audio &&
699 !ASIC_IS_DCE6(rdev)) /* remove once we support DCE6 */
f92e70ca
RM		 700 return ATOM_ENCODER_MODE_HDMI;
701 else if (radeon_connector->use_digital)
3f03ced8
AD		 702 return ATOM_ENCODER_MODE_DVI;
703 else
704 return ATOM_ENCODER_MODE_CRT;
705 break;
706 case DRM_MODE_CONNECTOR_DVID:
707 case DRM_MODE_CONNECTOR_HDMIA:
708 default:
27d9cc84 709 if (drm_detect_hdmi_monitor(radeon_connector->edid) &&
1cbcca30
AD		 710 radeon_audio &&
711 !ASIC_IS_DCE6(rdev)) /* remove once we support DCE6 */
f92e70ca
RM		 712 return ATOM_ENCODER_MODE_HDMI;
713 else
3f03ced8
AD		 714 return ATOM_ENCODER_MODE_DVI;
715 break;
716 case DRM_MODE_CONNECTOR_LVDS:
717 return ATOM_ENCODER_MODE_LVDS;
718 break;
719 case DRM_MODE_CONNECTOR_DisplayPort:
720 dig_connector = radeon_connector->con_priv;
721 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
722 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP))
723 return ATOM_ENCODER_MODE_DP;
27d9cc84 724 else if (drm_detect_hdmi_monitor(radeon_connector->edid) &&
1cbcca30
AD		 725 radeon_audio &&
726 !ASIC_IS_DCE6(rdev)) /* remove once we support DCE6 */
f92e70ca
RM		 727 return ATOM_ENCODER_MODE_HDMI;
728 else
3f03ced8
AD		 729 return ATOM_ENCODER_MODE_DVI;
730 break;
731 case DRM_MODE_CONNECTOR_eDP:
732 return ATOM_ENCODER_MODE_DP;
733 case DRM_MODE_CONNECTOR_DVIA:
734 case DRM_MODE_CONNECTOR_VGA:
735 return ATOM_ENCODER_MODE_CRT;
736 break;
737 case DRM_MODE_CONNECTOR_Composite:
738 case DRM_MODE_CONNECTOR_SVIDEO:
739 case DRM_MODE_CONNECTOR_9PinDIN:
740 /* fix me */
741 return ATOM_ENCODER_MODE_TV;
742 /*return ATOM_ENCODER_MODE_CV;*/
743 break;
744 }
745}
746
747/*
748 * DIG Encoder/Transmitter Setup
749 *
750 * DCE 3.0/3.1
751 * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
752 * Supports up to 3 digital outputs
753 * - 2 DIG encoder blocks.
754 * DIG1 can drive UNIPHY link A or link B
755 * DIG2 can drive UNIPHY link B or LVTMA
756 *
757 * DCE 3.2
758 * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
759 * Supports up to 5 digital outputs
760 * - 2 DIG encoder blocks.
761 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
762 *
2d415869 763 * DCE 4.0/5.0/6.0
3f03ced8
AD		 764 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
765 * Supports up to 6 digital outputs
766 * - 6 DIG encoder blocks.
767 * - DIG to PHY mapping is hardcoded
768 * DIG1 drives UNIPHY0 link A, A+B
769 * DIG2 drives UNIPHY0 link B
770 * DIG3 drives UNIPHY1 link A, A+B
771 * DIG4 drives UNIPHY1 link B
772 * DIG5 drives UNIPHY2 link A, A+B
773 * DIG6 drives UNIPHY2 link B
774 *
775 * DCE 4.1
776 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
777 * Supports up to 6 digital outputs
778 * - 2 DIG encoder blocks.
2d415869 779 * llano
3f03ced8 780 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
2d415869
AD		 781 * ontario
782 * DIG1 drives UNIPHY0/1/2 link A
783 * DIG2 drives UNIPHY0/1/2 link B
3f03ced8
AD		 784 *
785 * Routing
786 * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
787 * Examples:
788 * crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI
789 * crtc1 -> dig1 -> UNIPHY0 link B -> DP
790 * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS
791 * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI
792 */
793
794union dig_encoder_control {
795 DIG_ENCODER_CONTROL_PS_ALLOCATION v1;
796 DIG_ENCODER_CONTROL_PARAMETERS_V2 v2;
797 DIG_ENCODER_CONTROL_PARAMETERS_V3 v3;
798 DIG_ENCODER_CONTROL_PARAMETERS_V4 v4;
799};
800
801void
802atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode)
803{
804 struct drm_device *dev = encoder->dev;
805 struct radeon_device *rdev = dev->dev_private;
806 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
807 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
808 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
809 union dig_encoder_control args;
810 int index = 0;
811 uint8_t frev, crev;
812 int dp_clock = 0;
813 int dp_lane_count = 0;
814 int hpd_id = RADEON_HPD_NONE;
3f03ced8
AD		 815
816 if (connector) {
817 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
818 struct radeon_connector_atom_dig *dig_connector =
819 radeon_connector->con_priv;
820
821 dp_clock = dig_connector->dp_clock;
822 dp_lane_count = dig_connector->dp_lane_count;
823 hpd_id = radeon_connector->hpd.hpd;
3f03ced8
AD		 824 }
825
826 /* no dig encoder assigned */
827 if (dig->dig_encoder == -1)
828 return;
829
830 memset(&args, 0, sizeof(args));
831
832 if (ASIC_IS_DCE4(rdev))
833 index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl);
834 else {
835 if (dig->dig_encoder)
836 index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
837 else
838 index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
839 }
840
841 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
842 return;
843
58cdcb8b
AD		 844 switch (frev) {
845 case 1:
846 switch (crev) {
847 case 1:
848 args.v1.ucAction = action;
849 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
850 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
851 args.v3.ucPanelMode = panel_mode;
852 else
853 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
854
855 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))
856 args.v1.ucLaneNum = dp_lane_count;
9aa59993 857 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
58cdcb8b
AD		 858 args.v1.ucLaneNum = 8;
859 else
860 args.v1.ucLaneNum = 4;
861
862 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000))
863 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
864 switch (radeon_encoder->encoder_id) {
865 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
866 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
867 break;
868 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
869 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
870 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
871 break;
872 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
873 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
874 break;
875 }
876 if (dig->linkb)
877 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
878 else
879 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
3f03ced8 880 break;
58cdcb8b
AD		 881 case 2:
882 case 3:
883 args.v3.ucAction = action;
884 args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
885 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
886 args.v3.ucPanelMode = panel_mode;
887 else
888 args.v3.ucEncoderMode = atombios_get_encoder_mode(encoder);
889
2f6fa79a 890 if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode))
58cdcb8b 891 args.v3.ucLaneNum = dp_lane_count;
9aa59993 892 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
58cdcb8b
AD		 893 args.v3.ucLaneNum = 8;
894 else
895 args.v3.ucLaneNum = 4;
896
2f6fa79a 897 if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode) && (dp_clock == 270000))
58cdcb8b
AD		 898 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
899 args.v3.acConfig.ucDigSel = dig->dig_encoder;
1f0e2943 900 args.v3.ucBitPerColor = radeon_atom_get_bpc(encoder);
3f03ced8 901 break;
58cdcb8b
AD		 902 case 4:
903 args.v4.ucAction = action;
904 args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
905 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
906 args.v4.ucPanelMode = panel_mode;
907 else
908 args.v4.ucEncoderMode = atombios_get_encoder_mode(encoder);
909
2f6fa79a 910 if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode))
58cdcb8b 911 args.v4.ucLaneNum = dp_lane_count;
9aa59993 912 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
58cdcb8b
AD		 913 args.v4.ucLaneNum = 8;
914 else
915 args.v4.ucLaneNum = 4;
916
2f6fa79a 917 if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode)) {
58cdcb8b
AD		 918 if (dp_clock == 270000)
919 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ;
920 else if (dp_clock == 540000)
921 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ;
922 }
923 args.v4.acConfig.ucDigSel = dig->dig_encoder;
1f0e2943 924 args.v4.ucBitPerColor = radeon_atom_get_bpc(encoder);
58cdcb8b
AD		 925 if (hpd_id == RADEON_HPD_NONE)
926 args.v4.ucHPD_ID = 0;
927 else
928 args.v4.ucHPD_ID = hpd_id + 1;
3f03ced8 929 break;
3f03ced8 930 default:
58cdcb8b 931 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3f03ced8
AD		 932 break;
933 }
58cdcb8b
AD		 934 break;
935 default:
936 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
937 break;
3f03ced8
AD		 938 }
939
940 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
941
942}
943
944union dig_transmitter_control {
945 DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
946 DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
947 DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
948 DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4;
47aef7a8 949 DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 v5;
3f03ced8
AD		 950};
951
952void
953atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set)
954{
955 struct drm_device *dev = encoder->dev;
956 struct radeon_device *rdev = dev->dev_private;
957 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
958 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
959 struct drm_connector *connector;
960 union dig_transmitter_control args;
961 int index = 0;
962 uint8_t frev, crev;
963 bool is_dp = false;
964 int pll_id = 0;
965 int dp_clock = 0;
966 int dp_lane_count = 0;
967 int connector_object_id = 0;
968 int igp_lane_info = 0;
969 int dig_encoder = dig->dig_encoder;
47aef7a8 970 int hpd_id = RADEON_HPD_NONE;
3f03ced8
AD		 971
972 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
973 connector = radeon_get_connector_for_encoder_init(encoder);
974 /* just needed to avoid bailing in the encoder check. the encoder
975 * isn't used for init
976 */
977 dig_encoder = 0;
978 } else
979 connector = radeon_get_connector_for_encoder(encoder);
980
981 if (connector) {
982 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
983 struct radeon_connector_atom_dig *dig_connector =
984 radeon_connector->con_priv;
985
47aef7a8 986 hpd_id = radeon_connector->hpd.hpd;
3f03ced8
AD		 987 dp_clock = dig_connector->dp_clock;
988 dp_lane_count = dig_connector->dp_lane_count;
989 connector_object_id =
990 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
991 igp_lane_info = dig_connector->igp_lane_info;
992 }
993
a3b08294
AD		 994 if (encoder->crtc) {
995 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
996 pll_id = radeon_crtc->pll_id;
997 }
998
3f03ced8
AD		 999 /* no dig encoder assigned */
1000 if (dig_encoder == -1)
1001 return;
1002
1003 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)))
1004 is_dp = true;
1005
1006 memset(&args, 0, sizeof(args));
1007
1008 switch (radeon_encoder->encoder_id) {
1009 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1010 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1011 break;
1012 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1013 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1014 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1015 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1016 break;
1017 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1018 index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl);
1019 break;
1020 }
1021
1022 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1023 return;
1024
a3b08294
AD		 1025 switch (frev) {
1026 case 1:
1027 switch (crev) {
1028 case 1:
1029 args.v1.ucAction = action;
1030 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1031 args.v1.usInitInfo = cpu_to_le16(connector_object_id);
1032 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1033 args.v1.asMode.ucLaneSel = lane_num;
1034 args.v1.asMode.ucLaneSet = lane_set;
1035 } else {
1036 if (is_dp)
6e76a2df 1037 args.v1.usPixelClock = cpu_to_le16(dp_clock / 10);
9aa59993 1038 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
a3b08294
AD		 1039 args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1040 else
1041 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1042 }
3f03ced8 1043
a3b08294 1044 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
3f03ced8 1045
a3b08294
AD		 1046 if (dig_encoder)
1047 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
1048 else
1049 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
1050
1051 if ((rdev->flags & RADEON_IS_IGP) &&
1052 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) {
9aa59993
AD		 1053 if (is_dp ||
1054 !radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) {
a3b08294
AD		 1055 if (igp_lane_info & 0x1)
1056 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
1057 else if (igp_lane_info & 0x2)
1058 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
1059 else if (igp_lane_info & 0x4)
1060 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
1061 else if (igp_lane_info & 0x8)
1062 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
1063 } else {
1064 if (igp_lane_info & 0x3)
1065 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
1066 else if (igp_lane_info & 0xc)
1067 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
1068 }
1069 }
1070
1071 if (dig->linkb)
1072 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
1073 else
1074 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
1075
1076 if (is_dp)
1077 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1078 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1079 if (dig->coherent_mode)
1080 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
9aa59993 1081 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
a3b08294
AD		 1082 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
1083 }
1084 break;
1085 case 2:
1086 args.v2.ucAction = action;
1087 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1088 args.v2.usInitInfo = cpu_to_le16(connector_object_id);
1089 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1090 args.v2.asMode.ucLaneSel = lane_num;
1091 args.v2.asMode.ucLaneSet = lane_set;
1092 } else {
1093 if (is_dp)
6e76a2df 1094 args.v2.usPixelClock = cpu_to_le16(dp_clock / 10);
9aa59993 1095 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
a3b08294
AD		 1096 args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1097 else
1098 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1099 }
1100
1101 args.v2.acConfig.ucEncoderSel = dig_encoder;
1102 if (dig->linkb)
1103 args.v2.acConfig.ucLinkSel = 1;
1104
1105 switch (radeon_encoder->encoder_id) {
1106 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1107 args.v2.acConfig.ucTransmitterSel = 0;
1108 break;
1109 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1110 args.v2.acConfig.ucTransmitterSel = 1;
1111 break;
1112 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1113 args.v2.acConfig.ucTransmitterSel = 2;
1114 break;
1115 }
3f03ced8 1116
3f03ced8 1117 if (is_dp) {
a3b08294
AD		 1118 args.v2.acConfig.fCoherentMode = 1;
1119 args.v2.acConfig.fDPConnector = 1;
1120 } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1121 if (dig->coherent_mode)
1122 args.v2.acConfig.fCoherentMode = 1;
9aa59993 1123 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
a3b08294
AD		 1124 args.v2.acConfig.fDualLinkConnector = 1;
1125 }
1126 break;
1127 case 3:
1128 args.v3.ucAction = action;
1129 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1130 args.v3.usInitInfo = cpu_to_le16(connector_object_id);
1131 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1132 args.v3.asMode.ucLaneSel = lane_num;
1133 args.v3.asMode.ucLaneSet = lane_set;
1134 } else {
1135 if (is_dp)
6e76a2df 1136 args.v3.usPixelClock = cpu_to_le16(dp_clock / 10);
9aa59993 1137 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
a3b08294 1138 args.v3.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
3f03ced8 1139 else
a3b08294
AD		 1140 args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1141 }
1142
1143 if (is_dp)
1144 args.v3.ucLaneNum = dp_lane_count;
9aa59993 1145 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
a3b08294
AD		 1146 args.v3.ucLaneNum = 8;
1147 else
1148 args.v3.ucLaneNum = 4;
1149
1150 if (dig->linkb)
1151 args.v3.acConfig.ucLinkSel = 1;
1152 if (dig_encoder & 1)
1153 args.v3.acConfig.ucEncoderSel = 1;
1154
1155 /* Select the PLL for the PHY
1156 * DP PHY should be clocked from external src if there is
1157 * one.
1158 */
3f03ced8
AD		 1159 /* On DCE4, if there is an external clock, it generates the DP ref clock */
1160 if (is_dp && rdev->clock.dp_extclk)
1161 args.v3.acConfig.ucRefClkSource = 2; /* external src */
1162 else
1163 args.v3.acConfig.ucRefClkSource = pll_id;
3f03ced8 1164
a3b08294
AD		 1165 switch (radeon_encoder->encoder_id) {
1166 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1167 args.v3.acConfig.ucTransmitterSel = 0;
1168 break;
1169 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1170 args.v3.acConfig.ucTransmitterSel = 1;
1171 break;
1172 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1173 args.v3.acConfig.ucTransmitterSel = 2;
1174 break;
1175 }
3f03ced8 1176
a3b08294
AD		 1177 if (is_dp)
1178 args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
1179 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1180 if (dig->coherent_mode)
1181 args.v3.acConfig.fCoherentMode = 1;
9aa59993 1182 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
a3b08294
AD		 1183 args.v3.acConfig.fDualLinkConnector = 1;
1184 }
3f03ced8 1185 break;
a3b08294
AD		 1186 case 4:
1187 args.v4.ucAction = action;
1188 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1189 args.v4.usInitInfo = cpu_to_le16(connector_object_id);
1190 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1191 args.v4.asMode.ucLaneSel = lane_num;
1192 args.v4.asMode.ucLaneSet = lane_set;
3f03ced8 1193 } else {
a3b08294 1194 if (is_dp)
6e76a2df 1195 args.v4.usPixelClock = cpu_to_le16(dp_clock / 10);
9aa59993 1196 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
a3b08294
AD		 1197 args.v4.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1198 else
1199 args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
3f03ced8 1200 }
3f03ced8 1201
a3b08294
AD		 1202 if (is_dp)
1203 args.v4.ucLaneNum = dp_lane_count;
9aa59993 1204 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
a3b08294
AD		 1205 args.v4.ucLaneNum = 8;
1206 else
1207 args.v4.ucLaneNum = 4;
3f03ced8 1208
a3b08294
AD		 1209 if (dig->linkb)
1210 args.v4.acConfig.ucLinkSel = 1;
1211 if (dig_encoder & 1)
1212 args.v4.acConfig.ucEncoderSel = 1;
1213
1214 /* Select the PLL for the PHY
1215 * DP PHY should be clocked from external src if there is
1216 * one.
1217 */
1218 /* On DCE5 DCPLL usually generates the DP ref clock */
1219 if (is_dp) {
1220 if (rdev->clock.dp_extclk)
1221 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK;
1222 else
1223 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL;
1224 } else
1225 args.v4.acConfig.ucRefClkSource = pll_id;
1226
1227 switch (radeon_encoder->encoder_id) {
1228 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1229 args.v4.acConfig.ucTransmitterSel = 0;
1230 break;
1231 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1232 args.v4.acConfig.ucTransmitterSel = 1;
1233 break;
1234 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1235 args.v4.acConfig.ucTransmitterSel = 2;
1236 break;
1237 }
1238
1239 if (is_dp)
1240 args.v4.acConfig.fCoherentMode = 1; /* DP requires coherent */
1241 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1242 if (dig->coherent_mode)
1243 args.v4.acConfig.fCoherentMode = 1;
9aa59993 1244 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
a3b08294
AD		 1245 args.v4.acConfig.fDualLinkConnector = 1;
1246 }
1247 break;
47aef7a8
AD		 1248 case 5:
1249 args.v5.ucAction = action;
1250 if (is_dp)
1251 args.v5.usSymClock = cpu_to_le16(dp_clock / 10);
1252 else
1253 args.v5.usSymClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1254
1255 switch (radeon_encoder->encoder_id) {
1256 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1257 if (dig->linkb)
1258 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYB;
1259 else
1260 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYA;
1261 break;
1262 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1263 if (dig->linkb)
1264 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYD;
1265 else
1266 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYC;
1267 break;
1268 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1269 if (dig->linkb)
1270 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYF;
1271 else
1272 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYE;
1273 break;
1274 }
1275 if (is_dp)
1276 args.v5.ucLaneNum = dp_lane_count;
1277 else if (radeon_encoder->pixel_clock > 165000)
1278 args.v5.ucLaneNum = 8;
1279 else
1280 args.v5.ucLaneNum = 4;
1281 args.v5.ucConnObjId = connector_object_id;
1282 args.v5.ucDigMode = atombios_get_encoder_mode(encoder);
1283
1284 if (is_dp && rdev->clock.dp_extclk)
1285 args.v5.asConfig.ucPhyClkSrcId = ENCODER_REFCLK_SRC_EXTCLK;
1286 else
1287 args.v5.asConfig.ucPhyClkSrcId = pll_id;
1288
1289 if (is_dp)
1290 args.v5.asConfig.ucCoherentMode = 1; /* DP requires coherent */
1291 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1292 if (dig->coherent_mode)
1293 args.v5.asConfig.ucCoherentMode = 1;
1294 }
1295 if (hpd_id == RADEON_HPD_NONE)
1296 args.v5.asConfig.ucHPDSel = 0;
1297 else
1298 args.v5.asConfig.ucHPDSel = hpd_id + 1;
1299 args.v5.ucDigEncoderSel = 1 << dig_encoder;
1300 args.v5.ucDPLaneSet = lane_set;
1301 break;
a3b08294
AD		 1302 default:
1303 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1304 break;
3f03ced8 1305 }
a3b08294
AD		 1306 break;
1307 default:
1308 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1309 break;
3f03ced8
AD		 1310 }
1311
1312 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1313}
1314
1315bool
1316atombios_set_edp_panel_power(struct drm_connector *connector, int action)
1317{
1318 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1319 struct drm_device *dev = radeon_connector->base.dev;
1320 struct radeon_device *rdev = dev->dev_private;
1321 union dig_transmitter_control args;
1322 int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1323 uint8_t frev, crev;
1324
1325 if (connector->connector_type != DRM_MODE_CONNECTOR_eDP)
1326 goto done;
1327
1328 if (!ASIC_IS_DCE4(rdev))
1329 goto done;
1330
1331 if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) &&
1332 (action != ATOM_TRANSMITTER_ACTION_POWER_OFF))
1333 goto done;
1334
1335 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1336 goto done;
1337
1338 memset(&args, 0, sizeof(args));
1339
1340 args.v1.ucAction = action;
1341
1342 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1343
1344 /* wait for the panel to power up */
1345 if (action == ATOM_TRANSMITTER_ACTION_POWER_ON) {
1346 int i;
1347
1348 for (i = 0; i < 300; i++) {
1349 if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd))
1350 return true;
1351 mdelay(1);
1352 }
1353 return false;
1354 }
1355done:
1356 return true;
1357}
1358
1359union external_encoder_control {
1360 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1;
1361 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3;
1362};
1363
1364static void
1365atombios_external_encoder_setup(struct drm_encoder *encoder,
1366 struct drm_encoder *ext_encoder,
1367 int action)
1368{
1369 struct drm_device *dev = encoder->dev;
1370 struct radeon_device *rdev = dev->dev_private;
1371 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1372 struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder);
1373 union external_encoder_control args;
1374 struct drm_connector *connector;
1375 int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl);
1376 u8 frev, crev;
1377 int dp_clock = 0;
1378 int dp_lane_count = 0;
1379 int connector_object_id = 0;
1380 u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
3f03ced8
AD		 1381
1382 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1383 connector = radeon_get_connector_for_encoder_init(encoder);
1384 else
1385 connector = radeon_get_connector_for_encoder(encoder);
1386
1387 if (connector) {
1388 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1389 struct radeon_connector_atom_dig *dig_connector =
1390 radeon_connector->con_priv;
1391
1392 dp_clock = dig_connector->dp_clock;
1393 dp_lane_count = dig_connector->dp_lane_count;
1394 connector_object_id =
1395 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
3f03ced8
AD		 1396 }
1397
1398 memset(&args, 0, sizeof(args));
1399
1400 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1401 return;
1402
1403 switch (frev) {
1404 case 1:
1405 /* no params on frev 1 */
1406 break;
1407 case 2:
1408 switch (crev) {
1409 case 1:
1410 case 2:
1411 args.v1.sDigEncoder.ucAction = action;
1412 args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1413 args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1414
1415 if (ENCODER_MODE_IS_DP(args.v1.sDigEncoder.ucEncoderMode)) {
1416 if (dp_clock == 270000)
1417 args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
1418 args.v1.sDigEncoder.ucLaneNum = dp_lane_count;
9aa59993 1419 } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
3f03ced8
AD		 1420 args.v1.sDigEncoder.ucLaneNum = 8;
1421 else
1422 args.v1.sDigEncoder.ucLaneNum = 4;
1423 break;
1424 case 3:
1425 args.v3.sExtEncoder.ucAction = action;
1426 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1427 args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id);
1428 else
1429 args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1430 args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1431
1432 if (ENCODER_MODE_IS_DP(args.v3.sExtEncoder.ucEncoderMode)) {
1433 if (dp_clock == 270000)
1434 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
1435 else if (dp_clock == 540000)
1436 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ;
1437 args.v3.sExtEncoder.ucLaneNum = dp_lane_count;
9aa59993 1438 } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
3f03ced8
AD		 1439 args.v3.sExtEncoder.ucLaneNum = 8;
1440 else
1441 args.v3.sExtEncoder.ucLaneNum = 4;
1442 switch (ext_enum) {
1443 case GRAPH_OBJECT_ENUM_ID1:
1444 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1;
1445 break;
1446 case GRAPH_OBJECT_ENUM_ID2:
1447 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2;
1448 break;
1449 case GRAPH_OBJECT_ENUM_ID3:
1450 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3;
1451 break;
1452 }
1f0e2943 1453 args.v3.sExtEncoder.ucBitPerColor = radeon_atom_get_bpc(encoder);
3f03ced8
AD		 1454 break;
1455 default:
1456 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1457 return;
1458 }
1459 break;
1460 default:
1461 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1462 return;
1463 }
1464 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1465}
1466
1467static void
1468atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
1469{
1470 struct drm_device *dev = encoder->dev;
1471 struct radeon_device *rdev = dev->dev_private;
1472 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1473 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1474 ENABLE_YUV_PS_ALLOCATION args;
1475 int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
1476 uint32_t temp, reg;
1477
1478 memset(&args, 0, sizeof(args));
1479
1480 if (rdev->family >= CHIP_R600)
1481 reg = R600_BIOS_3_SCRATCH;
1482 else
1483 reg = RADEON_BIOS_3_SCRATCH;
1484
1485 /* XXX: fix up scratch reg handling */
1486 temp = RREG32(reg);
1487 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1488 WREG32(reg, (ATOM_S3_TV1_ACTIVE |
1489 (radeon_crtc->crtc_id << 18)));
1490 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1491 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
1492 else
1493 WREG32(reg, 0);
1494
1495 if (enable)
1496 args.ucEnable = ATOM_ENABLE;
1497 args.ucCRTC = radeon_crtc->crtc_id;
1498
1499 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1500
1501 WREG32(reg, temp);
1502}
1503
1504static void
1505radeon_atom_encoder_dpms_avivo(struct drm_encoder *encoder, int mode)
1506{
1507 struct drm_device *dev = encoder->dev;
1508 struct radeon_device *rdev = dev->dev_private;
1509 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1510 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
1511 int index = 0;
1512
1513 memset(&args, 0, sizeof(args));
1514
1515 switch (radeon_encoder->encoder_id) {
1516 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1517 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1518 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
1519 break;
1520 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1521 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1522 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1523 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1524 break;
1525 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1526 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1527 break;
1528 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1529 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1530 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1531 else
1532 index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
1533 break;
1534 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1535 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1536 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1537 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1538 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1539 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1540 else
1541 index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
1542 break;
1543 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1544 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1545 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1546 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1547 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1548 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1549 else
1550 index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
1551 break;
1552 default:
1553 return;
1554 }
1555
1556 switch (mode) {
1557 case DRM_MODE_DPMS_ON:
1558 args.ucAction = ATOM_ENABLE;
1559 /* workaround for DVOOutputControl on some RS690 systems */
1560 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DDI) {
1561 u32 reg = RREG32(RADEON_BIOS_3_SCRATCH);
1562 WREG32(RADEON_BIOS_3_SCRATCH, reg & ~ATOM_S3_DFP2I_ACTIVE);
1563 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1564 WREG32(RADEON_BIOS_3_SCRATCH, reg);
1565 } else
1566 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1567 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1568 args.ucAction = ATOM_LCD_BLON;
1569 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1570 }
1571 break;
1572 case DRM_MODE_DPMS_STANDBY:
1573 case DRM_MODE_DPMS_SUSPEND:
1574 case DRM_MODE_DPMS_OFF:
1575 args.ucAction = ATOM_DISABLE;
1576 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1577 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1578 args.ucAction = ATOM_LCD_BLOFF;
1579 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1580 }
1581 break;
1582 }
1583}
1584
1585static void
1586radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode)
1587{
1588 struct drm_device *dev = encoder->dev;
1589 struct radeon_device *rdev = dev->dev_private;
1590 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
8d1af57a
AD		 1591 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1592 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
3f03ced8
AD		 1593 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1594 struct radeon_connector *radeon_connector = NULL;
1595 struct radeon_connector_atom_dig *radeon_dig_connector = NULL;
1596
1597 if (connector) {
1598 radeon_connector = to_radeon_connector(connector);
1599 radeon_dig_connector = radeon_connector->con_priv;
1600 }
1601
1602 switch (mode) {
1603 case DRM_MODE_DPMS_ON:
8d1af57a
AD		 1604 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {
1605 if (!connector)
1606 dig->panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
1607 else
1608 dig->panel_mode = radeon_dp_get_panel_mode(encoder, connector);
1609
1610 /* setup and enable the encoder */
1611 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1612 atombios_dig_encoder_setup(encoder,
1613 ATOM_ENCODER_CMD_SETUP_PANEL_MODE,
1614 dig->panel_mode);
1615 if (ext_encoder) {
1616 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev))
1617 atombios_external_encoder_setup(encoder, ext_encoder,
1618 EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP);
fcedac67 1619 }
3f03ced8 1620 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
8d1af57a
AD		 1621 } else if (ASIC_IS_DCE4(rdev)) {
1622 /* setup and enable the encoder */
1623 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1624 /* enable the transmitter */
1625 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
3f03ced8 1626 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
8d1af57a
AD		 1627 } else {
1628 /* setup and enable the encoder and transmitter */
1629 atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0);
1630 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
1631 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1632 /* some early dce3.2 boards have a bug in their transmitter control table */
b9196395 1633 if ((rdev->family != CHIP_RV710) && (rdev->family != CHIP_RV730))
8d1af57a 1634 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
fcedac67 1635 }
3f03ced8
AD		 1636 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1637 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1638 atombios_set_edp_panel_power(connector,
1639 ATOM_TRANSMITTER_ACTION_POWER_ON);
1640 radeon_dig_connector->edp_on = true;
1641 }
3f03ced8
AD		 1642 radeon_dp_link_train(encoder, connector);
1643 if (ASIC_IS_DCE4(rdev))
1644 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0);
1645 }
1646 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1647 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
1648 break;
1649 case DRM_MODE_DPMS_STANDBY:
1650 case DRM_MODE_DPMS_SUSPEND:
1651 case DRM_MODE_DPMS_OFF:
8d1af57a
AD		 1652 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {
1653 /* disable the transmitter */
3a47824d 1654 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
8d1af57a
AD		 1655 } else if (ASIC_IS_DCE4(rdev)) {
1656 /* disable the transmitter */
1657 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
1658 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1659 } else {
1660 /* disable the encoder and transmitter */
3a47824d 1661 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
8d1af57a
AD		 1662 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1663 atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);
1664 }
3f03ced8
AD		 1665 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1666 if (ASIC_IS_DCE4(rdev))
1667 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0);
1668 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1669 atombios_set_edp_panel_power(connector,
1670 ATOM_TRANSMITTER_ACTION_POWER_OFF);
1671 radeon_dig_connector->edp_on = false;
1672 }
1673 }
1674 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1675 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
1676 break;
1677 }
1678}
1679
1680static void
1681radeon_atom_encoder_dpms_ext(struct drm_encoder *encoder,
1682 struct drm_encoder *ext_encoder,
1683 int mode)
1684{
1685 struct drm_device *dev = encoder->dev;
1686 struct radeon_device *rdev = dev->dev_private;
1687
1688 switch (mode) {
1689 case DRM_MODE_DPMS_ON:
1690 default:
1d3949c4 1691 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) {
3f03ced8
AD		 1692 atombios_external_encoder_setup(encoder, ext_encoder,
1693 EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT);
1694 atombios_external_encoder_setup(encoder, ext_encoder,
1695 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF);
1696 } else
1697 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);
1698 break;
1699 case DRM_MODE_DPMS_STANDBY:
1700 case DRM_MODE_DPMS_SUSPEND:
1701 case DRM_MODE_DPMS_OFF:
1d3949c4 1702 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) {
3f03ced8
AD		 1703 atombios_external_encoder_setup(encoder, ext_encoder,
1704 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING);
1705 atombios_external_encoder_setup(encoder, ext_encoder,
1706 EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT);
1707 } else
1708 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_DISABLE);
1709 break;
1710 }
1711}
1712
1713static void
1714radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1715{
1716 struct drm_device *dev = encoder->dev;
1717 struct radeon_device *rdev = dev->dev_private;
1718 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1719 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1720
1721 DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
1722 radeon_encoder->encoder_id, mode, radeon_encoder->devices,
1723 radeon_encoder->active_device);
1724 switch (radeon_encoder->encoder_id) {
1725 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1726 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1727 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1728 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1729 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1730 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1731 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1732 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1733 radeon_atom_encoder_dpms_avivo(encoder, mode);
1734 break;
1735 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1736 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1737 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1738 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1739 radeon_atom_encoder_dpms_dig(encoder, mode);
1740 break;
1741 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1742 if (ASIC_IS_DCE5(rdev)) {
1743 switch (mode) {
1744 case DRM_MODE_DPMS_ON:
1745 atombios_dvo_setup(encoder, ATOM_ENABLE);
1746 break;
1747 case DRM_MODE_DPMS_STANDBY:
1748 case DRM_MODE_DPMS_SUSPEND:
1749 case DRM_MODE_DPMS_OFF:
1750 atombios_dvo_setup(encoder, ATOM_DISABLE);
1751 break;
1752 }
1753 } else if (ASIC_IS_DCE3(rdev))
1754 radeon_atom_encoder_dpms_dig(encoder, mode);
1755 else
1756 radeon_atom_encoder_dpms_avivo(encoder, mode);
1757 break;
1758 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1759 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1760 if (ASIC_IS_DCE5(rdev)) {
1761 switch (mode) {
1762 case DRM_MODE_DPMS_ON:
1763 atombios_dac_setup(encoder, ATOM_ENABLE);
1764 break;
1765 case DRM_MODE_DPMS_STANDBY:
1766 case DRM_MODE_DPMS_SUSPEND:
1767 case DRM_MODE_DPMS_OFF:
1768 atombios_dac_setup(encoder, ATOM_DISABLE);
1769 break;
1770 }
1771 } else
1772 radeon_atom_encoder_dpms_avivo(encoder, mode);
1773 break;
1774 default:
1775 return;
1776 }
1777
1778 if (ext_encoder)
1779 radeon_atom_encoder_dpms_ext(encoder, ext_encoder, mode);
1780
1781 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1782
1783}
1784
1785union crtc_source_param {
1786 SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
1787 SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
1788};
1789
1790static void
1791atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1792{
1793 struct drm_device *dev = encoder->dev;
1794 struct radeon_device *rdev = dev->dev_private;
1795 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1796 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1797 union crtc_source_param args;
1798 int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
1799 uint8_t frev, crev;
1800 struct radeon_encoder_atom_dig *dig;
1801
1802 memset(&args, 0, sizeof(args));
1803
1804 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1805 return;
1806
1807 switch (frev) {
1808 case 1:
1809 switch (crev) {
1810 case 1:
1811 default:
1812 if (ASIC_IS_AVIVO(rdev))
1813 args.v1.ucCRTC = radeon_crtc->crtc_id;
1814 else {
1815 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) {
1816 args.v1.ucCRTC = radeon_crtc->crtc_id;
1817 } else {
1818 args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
1819 }
1820 }
1821 switch (radeon_encoder->encoder_id) {
1822 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1823 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1824 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1825 break;
1826 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1827 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1828 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
1829 args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1830 else
1831 args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1832 break;
1833 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1834 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1835 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1836 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1837 break;
1838 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1839 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1840 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1841 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1842 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1843 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1844 else
1845 args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1846 break;
1847 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1848 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1849 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1850 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1851 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1852 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1853 else
1854 args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1855 break;
1856 }
1857 break;
1858 case 2:
1859 args.v2.ucCRTC = radeon_crtc->crtc_id;
1860 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) {
1861 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1862
1863 if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)
1864 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
1865 else if (connector->connector_type == DRM_MODE_CONNECTOR_VGA)
1866 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_CRT;
1867 else
1868 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1869 } else
1870 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1871 switch (radeon_encoder->encoder_id) {
1872 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1873 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1874 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1875 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1876 dig = radeon_encoder->enc_priv;
1877 switch (dig->dig_encoder) {
1878 case 0:
1879 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1880 break;
1881 case 1:
1882 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1883 break;
1884 case 2:
1885 args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
1886 break;
1887 case 3:
1888 args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
1889 break;
1890 case 4:
1891 args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
1892 break;
1893 case 5:
1894 args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
1895 break;
1896 }
1897 break;
1898 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1899 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1900 break;
1901 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1902 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1903 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1904 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1905 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1906 else
1907 args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1908 break;
1909 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1910 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1911 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1912 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1913 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1914 else
1915 args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1916 break;
1917 }
1918 break;
1919 }
1920 break;
1921 default:
1922 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1923 return;
1924 }
1925
1926 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1927
1928 /* update scratch regs with new routing */
1929 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1930}
1931
1932static void
1933atombios_apply_encoder_quirks(struct drm_encoder *encoder,
1934 struct drm_display_mode *mode)
1935{
1936 struct drm_device *dev = encoder->dev;
1937 struct radeon_device *rdev = dev->dev_private;
1938 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1939 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1940
1941 /* Funky macbooks */
1942 if ((dev->pdev->device == 0x71C5) &&
1943 (dev->pdev->subsystem_vendor == 0x106b) &&
1944 (dev->pdev->subsystem_device == 0x0080)) {
1945 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1946 uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
1947
1948 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
1949 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
1950
1951 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
1952 }
1953 }
1954
1955 /* set scaler clears this on some chips */
1956 if (ASIC_IS_AVIVO(rdev) &&
1957 (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) {
1958 if (ASIC_IS_DCE4(rdev)) {
1959 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1960 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset,
1961 EVERGREEN_INTERLEAVE_EN);
1962 else
1963 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1964 } else {
1965 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1966 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
1967 AVIVO_D1MODE_INTERLEAVE_EN);
1968 else
1969 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1970 }
1971 }
1972}
1973
1974static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder)
1975{
1976 struct drm_device *dev = encoder->dev;
1977 struct radeon_device *rdev = dev->dev_private;
1978 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1979 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1980 struct drm_encoder *test_encoder;
41fa5437 1981 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
3f03ced8
AD		 1982 uint32_t dig_enc_in_use = 0;
1983
41fa5437
AD		 1984 if (ASIC_IS_DCE6(rdev)) {
1985 /* DCE6 */
1986 switch (radeon_encoder->encoder_id) {
1987 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1988 if (dig->linkb)
1989 return 1;
1990 else
1991 return 0;
1992 break;
1993 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1994 if (dig->linkb)
1995 return 3;
1996 else
1997 return 2;
1998 break;
1999 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2000 if (dig->linkb)
2001 return 5;
2002 else
2003 return 4;
2004 break;
2005 }
2006 } else if (ASIC_IS_DCE4(rdev)) {
2007 /* DCE4/5 */
2008 if (ASIC_IS_DCE41(rdev) && !ASIC_IS_DCE61(rdev)) {
3f03ced8
AD		 2009 /* ontario follows DCE4 */
2010 if (rdev->family == CHIP_PALM) {
2011 if (dig->linkb)
2012 return 1;
2013 else
2014 return 0;
2015 } else
2016 /* llano follows DCE3.2 */
2017 return radeon_crtc->crtc_id;
2018 } else {
2019 switch (radeon_encoder->encoder_id) {
2020 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2021 if (dig->linkb)
2022 return 1;
2023 else
2024 return 0;
2025 break;
2026 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2027 if (dig->linkb)
2028 return 3;
2029 else
2030 return 2;
2031 break;
2032 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2033 if (dig->linkb)
2034 return 5;
2035 else
2036 return 4;
2037 break;
2038 }
2039 }
2040 }
2041
2042 /* on DCE32 and encoder can driver any block so just crtc id */
2043 if (ASIC_IS_DCE32(rdev)) {
2044 return radeon_crtc->crtc_id;
2045 }
2046
2047 /* on DCE3 - LVTMA can only be driven by DIGB */
2048 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
2049 struct radeon_encoder *radeon_test_encoder;
2050
2051 if (encoder == test_encoder)
2052 continue;
2053
2054 if (!radeon_encoder_is_digital(test_encoder))
2055 continue;
2056
2057 radeon_test_encoder = to_radeon_encoder(test_encoder);
2058 dig = radeon_test_encoder->enc_priv;
2059
2060 if (dig->dig_encoder >= 0)
2061 dig_enc_in_use |= (1 << dig->dig_encoder);
2062 }
2063
2064 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) {
2065 if (dig_enc_in_use & 0x2)
2066 DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
2067 return 1;
2068 }
2069 if (!(dig_enc_in_use & 1))
2070 return 0;
2071 return 1;
2072}
2073
2074/* This only needs to be called once at startup */
2075void
2076radeon_atom_encoder_init(struct radeon_device *rdev)
2077{
2078 struct drm_device *dev = rdev->ddev;
2079 struct drm_encoder *encoder;
2080
2081 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2082 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2083 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2084
2085 switch (radeon_encoder->encoder_id) {
2086 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2087 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2088 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2089 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2090 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
2091 break;
2092 default:
2093 break;
2094 }
2095
1d3949c4 2096 if (ext_encoder && (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)))
3f03ced8
AD		 2097 atombios_external_encoder_setup(encoder, ext_encoder,
2098 EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT);
2099 }
2100}
2101
2102static void
2103radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
2104 struct drm_display_mode *mode,
2105 struct drm_display_mode *adjusted_mode)
2106{
2107 struct drm_device *dev = encoder->dev;
2108 struct radeon_device *rdev = dev->dev_private;
2109 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3f03ced8
AD		 2110
2111 radeon_encoder->pixel_clock = adjusted_mode->clock;
2112
8d1af57a
AD		 2113 /* need to call this here rather than in prepare() since we need some crtc info */
2114 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2115
3f03ced8
AD		 2116 if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) {
2117 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
2118 atombios_yuv_setup(encoder, true);
2119 else
2120 atombios_yuv_setup(encoder, false);
2121 }
2122
2123 switch (radeon_encoder->encoder_id) {
2124 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2125 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2126 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2127 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2128 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
2129 break;
2130 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2131 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2132 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2133 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
8d1af57a 2134 /* handled in dpms */
3f03ced8
AD		 2135 break;
2136 case ENCODER_OBJECT_ID_INTERNAL_DDI:
2137 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2138 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2139 atombios_dvo_setup(encoder, ATOM_ENABLE);
2140 break;
2141 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2142 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2143 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2144 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2145 atombios_dac_setup(encoder, ATOM_ENABLE);
2146 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) {
2147 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2148 atombios_tv_setup(encoder, ATOM_ENABLE);
2149 else
2150 atombios_tv_setup(encoder, ATOM_DISABLE);
2151 }
2152 break;
2153 }
2154
3f03ced8
AD		 2155 atombios_apply_encoder_quirks(encoder, adjusted_mode);
2156
2157 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
a973bea1
AD		 2158 if (rdev->asic->display.hdmi_enable)
2159 radeon_hdmi_enable(rdev, encoder, true);
2160 if (rdev->asic->display.hdmi_setmode)
2161 radeon_hdmi_setmode(rdev, encoder, adjusted_mode);
3f03ced8
AD		 2162 }
2163}
2164
2165static bool
2166atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2167{
2168 struct drm_device *dev = encoder->dev;
2169 struct radeon_device *rdev = dev->dev_private;
2170 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2171 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2172
2173 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
2174 ATOM_DEVICE_CV_SUPPORT |
2175 ATOM_DEVICE_CRT_SUPPORT)) {
2176 DAC_LOAD_DETECTION_PS_ALLOCATION args;
2177 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
2178 uint8_t frev, crev;
2179
2180 memset(&args, 0, sizeof(args));
2181
2182 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2183 return false;
2184
2185 args.sDacload.ucMisc = 0;
2186
2187 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
2188 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
2189 args.sDacload.ucDacType = ATOM_DAC_A;
2190 else
2191 args.sDacload.ucDacType = ATOM_DAC_B;
2192
2193 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
2194 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
2195 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
2196 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
2197 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2198 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
2199 if (crev >= 3)
2200 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
2201 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2202 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
2203 if (crev >= 3)
2204 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
2205 }
2206
2207 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2208
2209 return true;
2210 } else
2211 return false;
2212}
2213
2214static enum drm_connector_status
2215radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2216{
2217 struct drm_device *dev = encoder->dev;
2218 struct radeon_device *rdev = dev->dev_private;
2219 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2220 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2221 uint32_t bios_0_scratch;
2222
2223 if (!atombios_dac_load_detect(encoder, connector)) {
2224 DRM_DEBUG_KMS("detect returned false \n");
2225 return connector_status_unknown;
2226 }
2227
2228 if (rdev->family >= CHIP_R600)
2229 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2230 else
2231 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2232
2233 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2234 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2235 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2236 return connector_status_connected;
2237 }
2238 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2239 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2240 return connector_status_connected;
2241 }
2242 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2243 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2244 return connector_status_connected;
2245 }
2246 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2247 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2248 return connector_status_connected; /* CTV */
2249 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2250 return connector_status_connected; /* STV */
2251 }
2252 return connector_status_disconnected;
2253}
2254
2255static enum drm_connector_status
2256radeon_atom_dig_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2257{
2258 struct drm_device *dev = encoder->dev;
2259 struct radeon_device *rdev = dev->dev_private;
2260 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2261 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2262 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2263 u32 bios_0_scratch;
2264
2265 if (!ASIC_IS_DCE4(rdev))
2266 return connector_status_unknown;
2267
2268 if (!ext_encoder)
2269 return connector_status_unknown;
2270
2271 if ((radeon_connector->devices & ATOM_DEVICE_CRT_SUPPORT) == 0)
2272 return connector_status_unknown;
2273
2274 /* load detect on the dp bridge */
2275 atombios_external_encoder_setup(encoder, ext_encoder,
2276 EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION);
2277
2278 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2279
2280 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2281 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2282 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2283 return connector_status_connected;
2284 }
2285 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2286 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2287 return connector_status_connected;
2288 }
2289 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2290 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2291 return connector_status_connected;
2292 }
2293 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2294 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2295 return connector_status_connected; /* CTV */
2296 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2297 return connector_status_connected; /* STV */
2298 }
2299 return connector_status_disconnected;
2300}
2301
2302void
2303radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder)
2304{
2305 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2306
2307 if (ext_encoder)
2308 /* ddc_setup on the dp bridge */
2309 atombios_external_encoder_setup(encoder, ext_encoder,
2310 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP);
2311
2312}
2313
2314static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
2315{
cfcbd6d3 2316 struct radeon_device *rdev = encoder->dev->dev_private;
3f03ced8
AD		 2317 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2318 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
2319
2320 if ((radeon_encoder->active_device &
2321 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
2322 (radeon_encoder_get_dp_bridge_encoder_id(encoder) !=
2323 ENCODER_OBJECT_ID_NONE)) {
2324 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
cfcbd6d3 2325 if (dig) {
3f03ced8 2326 dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder);
cfcbd6d3
RM		 2327 if (radeon_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) {
2328 if (rdev->family >= CHIP_R600)
2329 dig->afmt = rdev->mode_info.afmt[dig->dig_encoder];
2330 else
2331 /* RS600/690/740 have only 1 afmt block */
2332 dig->afmt = rdev->mode_info.afmt[0];
2333 }
2334 }
3f03ced8
AD		 2335 }
2336
2337 radeon_atom_output_lock(encoder, true);
3f03ced8
AD		 2338
2339 if (connector) {
2340 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2341
2342 /* select the clock/data port if it uses a router */
2343 if (radeon_connector->router.cd_valid)
2344 radeon_router_select_cd_port(radeon_connector);
2345
2346 /* turn eDP panel on for mode set */
2347 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
2348 atombios_set_edp_panel_power(connector,
2349 ATOM_TRANSMITTER_ACTION_POWER_ON);
2350 }
2351
2352 /* this is needed for the pll/ss setup to work correctly in some cases */
2353 atombios_set_encoder_crtc_source(encoder);
2354}
2355
2356static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
2357{
8d1af57a 2358 /* need to call this here as we need the crtc set up */
3f03ced8
AD		 2359 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
2360 radeon_atom_output_lock(encoder, false);
2361}
2362
2363static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
2364{
2365 struct drm_device *dev = encoder->dev;
2366 struct radeon_device *rdev = dev->dev_private;
2367 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2368 struct radeon_encoder_atom_dig *dig;
2369
2370 /* check for pre-DCE3 cards with shared encoders;
2371 * can't really use the links individually, so don't disable
2372 * the encoder if it's in use by another connector
2373 */
2374 if (!ASIC_IS_DCE3(rdev)) {
2375 struct drm_encoder *other_encoder;
2376 struct radeon_encoder *other_radeon_encoder;
2377
2378 list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) {
2379 other_radeon_encoder = to_radeon_encoder(other_encoder);
2380 if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) &&
2381 drm_helper_encoder_in_use(other_encoder))
2382 goto disable_done;
2383 }
2384 }
2385
2386 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2387
2388 switch (radeon_encoder->encoder_id) {
2389 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2390 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2391 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2392 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2393 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE);
2394 break;
2395 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2396 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2397 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2398 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
8d1af57a 2399 /* handled in dpms */
3f03ced8
AD		 2400 break;
2401 case ENCODER_OBJECT_ID_INTERNAL_DDI:
2402 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2403 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2404 atombios_dvo_setup(encoder, ATOM_DISABLE);
2405 break;
2406 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2407 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2408 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2409 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2410 atombios_dac_setup(encoder, ATOM_DISABLE);
2411 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2412 atombios_tv_setup(encoder, ATOM_DISABLE);
2413 break;
2414 }
2415
2416disable_done:
2417 if (radeon_encoder_is_digital(encoder)) {
a973bea1
AD		 2418 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
2419 if (rdev->asic->display.hdmi_enable)
2420 radeon_hdmi_enable(rdev, encoder, false);
2421 }
3f03ced8
AD		 2422 dig = radeon_encoder->enc_priv;
2423 dig->dig_encoder = -1;
2424 }
2425 radeon_encoder->active_device = 0;
2426}
2427
2428/* these are handled by the primary encoders */
2429static void radeon_atom_ext_prepare(struct drm_encoder *encoder)
2430{
2431
2432}
2433
2434static void radeon_atom_ext_commit(struct drm_encoder *encoder)
2435{
2436
2437}
2438
2439static void
2440radeon_atom_ext_mode_set(struct drm_encoder *encoder,
2441 struct drm_display_mode *mode,
2442 struct drm_display_mode *adjusted_mode)
2443{
2444
2445}
2446
2447static void radeon_atom_ext_disable(struct drm_encoder *encoder)
2448{
2449
2450}
2451
2452static void
2453radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode)
2454{
2455
2456}
2457
2458static bool radeon_atom_ext_mode_fixup(struct drm_encoder *encoder,
e811f5ae 2459 const struct drm_display_mode *mode,
3f03ced8
AD		 2460 struct drm_display_mode *adjusted_mode)
2461{
2462 return true;
2463}
2464
2465static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = {
2466 .dpms = radeon_atom_ext_dpms,
2467 .mode_fixup = radeon_atom_ext_mode_fixup,
2468 .prepare = radeon_atom_ext_prepare,
2469 .mode_set = radeon_atom_ext_mode_set,
2470 .commit = radeon_atom_ext_commit,
2471 .disable = radeon_atom_ext_disable,
2472 /* no detect for TMDS/LVDS yet */
2473};
2474
2475static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
2476 .dpms = radeon_atom_encoder_dpms,
2477 .mode_fixup = radeon_atom_mode_fixup,
2478 .prepare = radeon_atom_encoder_prepare,
2479 .mode_set = radeon_atom_encoder_mode_set,
2480 .commit = radeon_atom_encoder_commit,
2481 .disable = radeon_atom_encoder_disable,
2482 .detect = radeon_atom_dig_detect,
2483};
2484
2485static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
2486 .dpms = radeon_atom_encoder_dpms,
2487 .mode_fixup = radeon_atom_mode_fixup,
2488 .prepare = radeon_atom_encoder_prepare,
2489 .mode_set = radeon_atom_encoder_mode_set,
2490 .commit = radeon_atom_encoder_commit,
2491 .detect = radeon_atom_dac_detect,
2492};
2493
2494void radeon_enc_destroy(struct drm_encoder *encoder)
2495{
2496 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
f3728734
AD		 2497 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2498 radeon_atom_backlight_exit(radeon_encoder);
3f03ced8
AD		 2499 kfree(radeon_encoder->enc_priv);
2500 drm_encoder_cleanup(encoder);
2501 kfree(radeon_encoder);
2502}
2503
2504static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
2505 .destroy = radeon_enc_destroy,
2506};
2507
1109ca09 2508static struct radeon_encoder_atom_dac *
3f03ced8
AD		 2509radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
2510{
2511 struct drm_device *dev = radeon_encoder->base.dev;
2512 struct radeon_device *rdev = dev->dev_private;
2513 struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
2514
2515 if (!dac)
2516 return NULL;
2517
2518 dac->tv_std = radeon_atombios_get_tv_info(rdev);
2519 return dac;
2520}
2521
1109ca09 2522static struct radeon_encoder_atom_dig *
3f03ced8
AD		 2523radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
2524{
2525 int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
2526 struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
2527
2528 if (!dig)
2529 return NULL;
2530
2531 /* coherent mode by default */
2532 dig->coherent_mode = true;
2533 dig->dig_encoder = -1;
2534
2535 if (encoder_enum == 2)
2536 dig->linkb = true;
2537 else
2538 dig->linkb = false;
2539
2540 return dig;
2541}
2542
2543void
2544radeon_add_atom_encoder(struct drm_device *dev,
2545 uint32_t encoder_enum,
2546 uint32_t supported_device,
2547 u16 caps)
2548{
2549 struct radeon_device *rdev = dev->dev_private;
2550 struct drm_encoder *encoder;
2551 struct radeon_encoder *radeon_encoder;
2552
2553 /* see if we already added it */
2554 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2555 radeon_encoder = to_radeon_encoder(encoder);
2556 if (radeon_encoder->encoder_enum == encoder_enum) {
2557 radeon_encoder->devices |= supported_device;
2558 return;
2559 }
2560
2561 }
2562
2563 /* add a new one */
2564 radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
2565 if (!radeon_encoder)
2566 return;
2567
2568 encoder = &radeon_encoder->base;
2569 switch (rdev->num_crtc) {
2570 case 1:
2571 encoder->possible_crtcs = 0x1;
2572 break;
2573 case 2:
2574 default:
2575 encoder->possible_crtcs = 0x3;
2576 break;
2577 case 4:
2578 encoder->possible_crtcs = 0xf;
2579 break;
2580 case 6:
2581 encoder->possible_crtcs = 0x3f;
2582 break;
2583 }
2584
2585 radeon_encoder->enc_priv = NULL;
2586
2587 radeon_encoder->encoder_enum = encoder_enum;
2588 radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
2589 radeon_encoder->devices = supported_device;
2590 radeon_encoder->rmx_type = RMX_OFF;
2591 radeon_encoder->underscan_type = UNDERSCAN_OFF;
2592 radeon_encoder->is_ext_encoder = false;
2593 radeon_encoder->caps = caps;
2594
2595 switch (radeon_encoder->encoder_id) {
2596 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2597 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2598 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2599 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2600 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2601 radeon_encoder->rmx_type = RMX_FULL;
2602 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2603 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2604 } else {
2605 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2606 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2607 }
2608 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2609 break;
2610 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2611 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2612 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2613 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2614 break;
2615 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2616 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2617 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2618 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC);
2619 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2620 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2621 break;
2622 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2623 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2624 case ENCODER_OBJECT_ID_INTERNAL_DDI:
2625 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2626 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2627 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2628 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2629 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2630 radeon_encoder->rmx_type = RMX_FULL;
2631 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2632 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2633 } else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
2634 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2635 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2636 } else {
2637 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2638 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2639 }
2640 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2641 break;
2642 case ENCODER_OBJECT_ID_SI170B:
2643 case ENCODER_OBJECT_ID_CH7303:
2644 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
2645 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
2646 case ENCODER_OBJECT_ID_TITFP513:
2647 case ENCODER_OBJECT_ID_VT1623:
2648 case ENCODER_OBJECT_ID_HDMI_SI1930:
2649 case ENCODER_OBJECT_ID_TRAVIS:
2650 case ENCODER_OBJECT_ID_NUTMEG:
2651 /* these are handled by the primary encoders */
2652 radeon_encoder->is_ext_encoder = true;
2653 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2654 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2655 else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
2656 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2657 else
2658 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2659 drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs);
2660 break;
2661 }
2662}
Linux kernel - Deliverables
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