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Merge tag 'for-4.1' of git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux...
[deliverable/linux.git] / drivers / gpu / drm / radeon / atombios_encoders.c
CommitLineData
3f03ced8
AD		 1/*
2 * Copyright 2007-11 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
760285e7
DH		 26#include <drm/drmP.h>
27#include <drm/drm_crtc_helper.h>
28#include <drm/radeon_drm.h>
3f03ced8 29#include "radeon.h"
6e72376d 30#include "radeon_audio.h"
3f03ced8 31#include "atom.h"
f3728734 32#include <linux/backlight.h>
3f03ced8
AD		 33
34extern int atom_debug;
35
f3728734
AD		 36static u8
37radeon_atom_get_backlight_level_from_reg(struct radeon_device *rdev)
38{
39 u8 backlight_level;
40 u32 bios_2_scratch;
41
42 if (rdev->family >= CHIP_R600)
43 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
44 else
45 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
46
47 backlight_level = ((bios_2_scratch & ATOM_S2_CURRENT_BL_LEVEL_MASK) >>
48 ATOM_S2_CURRENT_BL_LEVEL_SHIFT);
49
50 return backlight_level;
51}
52
53static void
54radeon_atom_set_backlight_level_to_reg(struct radeon_device *rdev,
55 u8 backlight_level)
56{
57 u32 bios_2_scratch;
58
59 if (rdev->family >= CHIP_R600)
60 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
61 else
62 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
63
64 bios_2_scratch &= ~ATOM_S2_CURRENT_BL_LEVEL_MASK;
65 bios_2_scratch |= ((backlight_level << ATOM_S2_CURRENT_BL_LEVEL_SHIFT) &
66 ATOM_S2_CURRENT_BL_LEVEL_MASK);
67
68 if (rdev->family >= CHIP_R600)
69 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
70 else
71 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
72}
73
6d92f81d
AD		 74u8
75atombios_get_backlight_level(struct radeon_encoder *radeon_encoder)
76{
77 struct drm_device *dev = radeon_encoder->base.dev;
78 struct radeon_device *rdev = dev->dev_private;
79
80 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
81 return 0;
82
83 return radeon_atom_get_backlight_level_from_reg(rdev);
84}
85
fda4b25c 86void
37e9b6a6 87atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level)
f3728734
AD		 88{
89 struct drm_encoder *encoder = &radeon_encoder->base;
90 struct drm_device *dev = radeon_encoder->base.dev;
91 struct radeon_device *rdev = dev->dev_private;
92 struct radeon_encoder_atom_dig *dig;
93 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
94 int index;
95
37e9b6a6
AD		 96 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
97 return;
98
99 if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) &&
100 radeon_encoder->enc_priv) {
f3728734 101 dig = radeon_encoder->enc_priv;
37e9b6a6 102 dig->backlight_level = level;
f3728734
AD		 103 radeon_atom_set_backlight_level_to_reg(rdev, dig->backlight_level);
104
105 switch (radeon_encoder->encoder_id) {
106 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
107 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
108 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
109 if (dig->backlight_level == 0) {
110 args.ucAction = ATOM_LCD_BLOFF;
111 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
112 } else {
113 args.ucAction = ATOM_LCD_BL_BRIGHTNESS_CONTROL;
114 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
115 args.ucAction = ATOM_LCD_BLON;
116 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
117 }
118 break;
119 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
120 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
121 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
122 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
123 if (dig->backlight_level == 0)
124 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
125 else {
126 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL, 0, 0);
127 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
128 }
129 break;
130 default:
131 break;
132 }
133 }
134}
135
bced76f2
AD		 136#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
137
f3728734
AD		 138static u8 radeon_atom_bl_level(struct backlight_device *bd)
139{
140 u8 level;
141
142 /* Convert brightness to hardware level */
143 if (bd->props.brightness < 0)
144 level = 0;
145 else if (bd->props.brightness > RADEON_MAX_BL_LEVEL)
146 level = RADEON_MAX_BL_LEVEL;
147 else
148 level = bd->props.brightness;
149
150 return level;
151}
152
153static int radeon_atom_backlight_update_status(struct backlight_device *bd)
154{
155 struct radeon_backlight_privdata *pdata = bl_get_data(bd);
156 struct radeon_encoder *radeon_encoder = pdata->encoder;
157
37e9b6a6 158 atombios_set_backlight_level(radeon_encoder, radeon_atom_bl_level(bd));
f3728734
AD		 159
160 return 0;
161}
162
163static int radeon_atom_backlight_get_brightness(struct backlight_device *bd)
164{
165 struct radeon_backlight_privdata *pdata = bl_get_data(bd);
166 struct radeon_encoder *radeon_encoder = pdata->encoder;
167 struct drm_device *dev = radeon_encoder->base.dev;
168 struct radeon_device *rdev = dev->dev_private;
169
170 return radeon_atom_get_backlight_level_from_reg(rdev);
171}
172
173static const struct backlight_ops radeon_atom_backlight_ops = {
174 .get_brightness = radeon_atom_backlight_get_brightness,
175 .update_status = radeon_atom_backlight_update_status,
176};
177
178void radeon_atom_backlight_init(struct radeon_encoder *radeon_encoder,
179 struct drm_connector *drm_connector)
180{
181 struct drm_device *dev = radeon_encoder->base.dev;
182 struct radeon_device *rdev = dev->dev_private;
183 struct backlight_device *bd;
184 struct backlight_properties props;
185 struct radeon_backlight_privdata *pdata;
186 struct radeon_encoder_atom_dig *dig;
614499b4 187 char bl_name[16];
f3728734 188
80101790
AD		 189 /* Mac laptops with multiple GPUs use the gmux driver for backlight
190 * so don't register a backlight device
191 */
192 if ((rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) &&
193 (rdev->pdev->device == 0x6741))
194 return;
195
f3728734
AD		 196 if (!radeon_encoder->enc_priv)
197 return;
198
199 if (!rdev->is_atom_bios)
200 return;
201
202 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
203 return;
204
205 pdata = kmalloc(sizeof(struct radeon_backlight_privdata), GFP_KERNEL);
206 if (!pdata) {
207 DRM_ERROR("Memory allocation failed\n");
208 goto error;
209 }
210
211 memset(&props, 0, sizeof(props));
212 props.max_brightness = RADEON_MAX_BL_LEVEL;
213 props.type = BACKLIGHT_RAW;
614499b4
AD		 214 snprintf(bl_name, sizeof(bl_name),
215 "radeon_bl%d", dev->primary->index);
5bdebb18 216 bd = backlight_device_register(bl_name, drm_connector->kdev,
f3728734
AD		 217 pdata, &radeon_atom_backlight_ops, &props);
218 if (IS_ERR(bd)) {
219 DRM_ERROR("Backlight registration failed\n");
220 goto error;
221 }
222
223 pdata->encoder = radeon_encoder;
224
f3728734
AD		 225 dig = radeon_encoder->enc_priv;
226 dig->bl_dev = bd;
227
228 bd->props.brightness = radeon_atom_backlight_get_brightness(bd);
201bb624
AD		 229 /* Set a reasonable default here if the level is 0 otherwise
230 * fbdev will attempt to turn the backlight on after console
231 * unblanking and it will try and restore 0 which turns the backlight
232 * off again.
233 */
234 if (bd->props.brightness == 0)
235 bd->props.brightness = RADEON_MAX_BL_LEVEL;
f3728734
AD		 236 bd->props.power = FB_BLANK_UNBLANK;
237 backlight_update_status(bd);
238
239 DRM_INFO("radeon atom DIG backlight initialized\n");
240
241 return;
242
243error:
244 kfree(pdata);
245 return;
246}
247
248static void radeon_atom_backlight_exit(struct radeon_encoder *radeon_encoder)
249{
250 struct drm_device *dev = radeon_encoder->base.dev;
251 struct radeon_device *rdev = dev->dev_private;
252 struct backlight_device *bd = NULL;
253 struct radeon_encoder_atom_dig *dig;
254
255 if (!radeon_encoder->enc_priv)
256 return;
257
258 if (!rdev->is_atom_bios)
259 return;
260
261 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
262 return;
263
264 dig = radeon_encoder->enc_priv;
265 bd = dig->bl_dev;
266 dig->bl_dev = NULL;
267
268 if (bd) {
269 struct radeon_legacy_backlight_privdata *pdata;
270
271 pdata = bl_get_data(bd);
272 backlight_device_unregister(bd);
273 kfree(pdata);
274
275 DRM_INFO("radeon atom LVDS backlight unloaded\n");
276 }
277}
278
279#else /* !CONFIG_BACKLIGHT_CLASS_DEVICE */
280
281void radeon_atom_backlight_init(struct radeon_encoder *encoder)
282{
283}
284
285static void radeon_atom_backlight_exit(struct radeon_encoder *encoder)
286{
287}
288
289#endif
290
3f03ced8
AD		 291/* evil but including atombios.h is much worse */
292bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
293 struct drm_display_mode *mode);
294
3f03ced8 295static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
e811f5ae 296 const struct drm_display_mode *mode,
3f03ced8
AD		 297 struct drm_display_mode *adjusted_mode)
298{
299 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
300 struct drm_device *dev = encoder->dev;
301 struct radeon_device *rdev = dev->dev_private;
302
303 /* set the active encoder to connector routing */
304 radeon_encoder_set_active_device(encoder);
305 drm_mode_set_crtcinfo(adjusted_mode, 0);
306
307 /* hw bug */
308 if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
309 && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
310 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
311
da997620
AD		 312 /* get the native mode for scaling */
313 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) {
3f03ced8 314 radeon_panel_mode_fixup(encoder, adjusted_mode);
da997620 315 } else if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
3f03ced8
AD		 316 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
317 if (tv_dac) {
318 if (tv_dac->tv_std == TV_STD_NTSC ||
319 tv_dac->tv_std == TV_STD_NTSC_J ||
320 tv_dac->tv_std == TV_STD_PAL_M)
321 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
322 else
323 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
324 }
da997620
AD		 325 } else if (radeon_encoder->rmx_type != RMX_OFF) {
326 radeon_panel_mode_fixup(encoder, adjusted_mode);
3f03ced8
AD		 327 }
328
329 if (ASIC_IS_DCE3(rdev) &&
330 ((radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
331 (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE))) {
332 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
93927f9c 333 radeon_dp_set_link_config(connector, adjusted_mode);
3f03ced8
AD		 334 }
335
336 return true;
337}
338
339static void
340atombios_dac_setup(struct drm_encoder *encoder, int action)
341{
342 struct drm_device *dev = encoder->dev;
343 struct radeon_device *rdev = dev->dev_private;
344 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
345 DAC_ENCODER_CONTROL_PS_ALLOCATION args;
346 int index = 0;
347 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
348
349 memset(&args, 0, sizeof(args));
350
351 switch (radeon_encoder->encoder_id) {
352 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
353 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
354 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
355 break;
356 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
357 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
358 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
359 break;
360 }
361
362 args.ucAction = action;
363
364 if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
365 args.ucDacStandard = ATOM_DAC1_PS2;
366 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
367 args.ucDacStandard = ATOM_DAC1_CV;
368 else {
369 switch (dac_info->tv_std) {
370 case TV_STD_PAL:
371 case TV_STD_PAL_M:
372 case TV_STD_SCART_PAL:
373 case TV_STD_SECAM:
374 case TV_STD_PAL_CN:
375 args.ucDacStandard = ATOM_DAC1_PAL;
376 break;
377 case TV_STD_NTSC:
378 case TV_STD_NTSC_J:
379 case TV_STD_PAL_60:
380 default:
381 args.ucDacStandard = ATOM_DAC1_NTSC;
382 break;
383 }
384 }
385 args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
386
387 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
388
389}
390
391static void
392atombios_tv_setup(struct drm_encoder *encoder, int action)
393{
394 struct drm_device *dev = encoder->dev;
395 struct radeon_device *rdev = dev->dev_private;
396 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
397 TV_ENCODER_CONTROL_PS_ALLOCATION args;
398 int index = 0;
399 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
400
401 memset(&args, 0, sizeof(args));
402
403 index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
404
405 args.sTVEncoder.ucAction = action;
406
407 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
408 args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
409 else {
410 switch (dac_info->tv_std) {
411 case TV_STD_NTSC:
412 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
413 break;
414 case TV_STD_PAL:
415 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
416 break;
417 case TV_STD_PAL_M:
418 args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
419 break;
420 case TV_STD_PAL_60:
421 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
422 break;
423 case TV_STD_NTSC_J:
424 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
425 break;
426 case TV_STD_SCART_PAL:
427 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
428 break;
429 case TV_STD_SECAM:
430 args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
431 break;
432 case TV_STD_PAL_CN:
433 args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
434 break;
435 default:
436 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
437 break;
438 }
439 }
440
441 args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
442
443 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
444
445}
446
1f0e2943
AD		 447static u8 radeon_atom_get_bpc(struct drm_encoder *encoder)
448{
1f0e2943
AD		 449 int bpc = 8;
450
7d5a33b0
AD		 451 if (encoder->crtc) {
452 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
453 bpc = radeon_crtc->bpc;
454 }
1f0e2943
AD		 455
456 switch (bpc) {
457 case 0:
458 return PANEL_BPC_UNDEFINE;
459 case 6:
460 return PANEL_6BIT_PER_COLOR;
461 case 8:
462 default:
463 return PANEL_8BIT_PER_COLOR;
464 case 10:
465 return PANEL_10BIT_PER_COLOR;
466 case 12:
467 return PANEL_12BIT_PER_COLOR;
468 case 16:
469 return PANEL_16BIT_PER_COLOR;
470 }
471}
472
3f03ced8
AD		 473union dvo_encoder_control {
474 ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds;
475 DVO_ENCODER_CONTROL_PS_ALLOCATION dvo;
476 DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3;
aea65641 477 DVO_ENCODER_CONTROL_PS_ALLOCATION_V1_4 dvo_v4;
3f03ced8
AD		 478};
479
480void
481atombios_dvo_setup(struct drm_encoder *encoder, int action)
482{
483 struct drm_device *dev = encoder->dev;
484 struct radeon_device *rdev = dev->dev_private;
485 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
486 union dvo_encoder_control args;
487 int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
24153dd3 488 uint8_t frev, crev;
3f03ced8
AD		 489
490 memset(&args, 0, sizeof(args));
491
24153dd3
AD		 492 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
493 return;
494
afceb931
AD		 495 /* some R4xx chips have the wrong frev */
496 if (rdev->family <= CHIP_RV410)
497 frev = 1;
498
24153dd3
AD		 499 switch (frev) {
500 case 1:
501 switch (crev) {
502 case 1:
503 /* R4xx, R5xx */
504 args.ext_tmds.sXTmdsEncoder.ucEnable = action;
505
9aa59993 506 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
24153dd3
AD		 507 args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL;
508
509 args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB;
510 break;
511 case 2:
512 /* RS600/690/740 */
513 args.dvo.sDVOEncoder.ucAction = action;
514 args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
515 /* DFP1, CRT1, TV1 depending on the type of port */
516 args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX;
517
9aa59993 518 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
24153dd3
AD		 519 args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL;
520 break;
521 case 3:
522 /* R6xx */
523 args.dvo_v3.ucAction = action;
524 args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
525 args.dvo_v3.ucDVOConfig = 0; /* XXX */
526 break;
aea65641
AD		 527 case 4:
528 /* DCE8 */
529 args.dvo_v4.ucAction = action;
530 args.dvo_v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
531 args.dvo_v4.ucDVOConfig = 0; /* XXX */
532 args.dvo_v4.ucBitPerColor = radeon_atom_get_bpc(encoder);
533 break;
24153dd3
AD		 534 default:
535 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
536 break;
537 }
538 break;
539 default:
540 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
541 break;
3f03ced8
AD		 542 }
543
544 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
545}
546
547union lvds_encoder_control {
548 LVDS_ENCODER_CONTROL_PS_ALLOCATION v1;
549 LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
550};
551
552void
553atombios_digital_setup(struct drm_encoder *encoder, int action)
554{
555 struct drm_device *dev = encoder->dev;
556 struct radeon_device *rdev = dev->dev_private;
557 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
558 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
559 union lvds_encoder_control args;
560 int index = 0;
561 int hdmi_detected = 0;
562 uint8_t frev, crev;
563
564 if (!dig)
565 return;
566
567 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
568 hdmi_detected = 1;
569
570 memset(&args, 0, sizeof(args));
571
572 switch (radeon_encoder->encoder_id) {
573 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
574 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
575 break;
576 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
577 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
578 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
579 break;
580 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
581 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
582 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
583 else
584 index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
585 break;
586 }
587
588 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
589 return;
590
591 switch (frev) {
592 case 1:
593 case 2:
594 switch (crev) {
595 case 1:
596 args.v1.ucMisc = 0;
597 args.v1.ucAction = action;
598 if (hdmi_detected)
599 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
600 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
601 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
602 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
603 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
604 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
605 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
606 } else {
607 if (dig->linkb)
608 args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
9aa59993 609 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
3f03ced8
AD		 610 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
611 /*if (pScrn->rgbBits == 8) */
612 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
613 }
614 break;
615 case 2:
616 case 3:
617 args.v2.ucMisc = 0;
618 args.v2.ucAction = action;
619 if (crev == 3) {
620 if (dig->coherent_mode)
621 args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
622 }
623 if (hdmi_detected)
624 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
625 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
626 args.v2.ucTruncate = 0;
627 args.v2.ucSpatial = 0;
628 args.v2.ucTemporal = 0;
629 args.v2.ucFRC = 0;
630 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
631 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
632 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
633 if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) {
634 args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
635 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
636 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
637 }
638 if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) {
639 args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
640 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
641 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
642 if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2)
643 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
644 }
645 } else {
646 if (dig->linkb)
647 args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
9aa59993 648 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
3f03ced8
AD		 649 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
650 }
651 break;
652 default:
653 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
654 break;
655 }
656 break;
657 default:
658 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
659 break;
660 }
661
662 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
663}
664
665int
666atombios_get_encoder_mode(struct drm_encoder *encoder)
667{
e55bca26
SG		 668 struct drm_device *dev = encoder->dev;
669 struct radeon_device *rdev = dev->dev_private;
3f03ced8 670 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3f03ced8
AD		 671 struct drm_connector *connector;
672 struct radeon_connector *radeon_connector;
673 struct radeon_connector_atom_dig *dig_connector;
674
675 /* dp bridges are always DP */
676 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)
677 return ATOM_ENCODER_MODE_DP;
678
679 /* DVO is always DVO */
a59fbb8e
AD		 680 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DVO1) ||
681 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1))
3f03ced8
AD		 682 return ATOM_ENCODER_MODE_DVO;
683
684 connector = radeon_get_connector_for_encoder(encoder);
685 /* if we don't have an active device yet, just use one of
686 * the connectors tied to the encoder.
687 */
688 if (!connector)
689 connector = radeon_get_connector_for_encoder_init(encoder);
690 radeon_connector = to_radeon_connector(connector);
691
692 switch (connector->connector_type) {
693 case DRM_MODE_CONNECTOR_DVII:
694 case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
108dc8e8
AD		 695 if (radeon_audio != 0) {
696 if (radeon_connector->use_digital &&
697 (radeon_connector->audio == RADEON_AUDIO_ENABLE))
698 return ATOM_ENCODER_MODE_HDMI;
377bd8a9 699 else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) &&
108dc8e8
AD		 700 (radeon_connector->audio == RADEON_AUDIO_AUTO))
701 return ATOM_ENCODER_MODE_HDMI;
702 else if (radeon_connector->use_digital)
703 return ATOM_ENCODER_MODE_DVI;
704 else
705 return ATOM_ENCODER_MODE_CRT;
706 } else if (radeon_connector->use_digital) {
3f03ced8 707 return ATOM_ENCODER_MODE_DVI;
108dc8e8 708 } else {
3f03ced8 709 return ATOM_ENCODER_MODE_CRT;
108dc8e8 710 }
3f03ced8
AD		 711 break;
712 case DRM_MODE_CONNECTOR_DVID:
713 case DRM_MODE_CONNECTOR_HDMIA:
714 default:
108dc8e8
AD		 715 if (radeon_audio != 0) {
716 if (radeon_connector->audio == RADEON_AUDIO_ENABLE)
717 return ATOM_ENCODER_MODE_HDMI;
377bd8a9 718 else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) &&
108dc8e8
AD		 719 (radeon_connector->audio == RADEON_AUDIO_AUTO))
720 return ATOM_ENCODER_MODE_HDMI;
721 else
722 return ATOM_ENCODER_MODE_DVI;
723 } else {
3f03ced8 724 return ATOM_ENCODER_MODE_DVI;
108dc8e8 725 }
3f03ced8
AD		 726 break;
727 case DRM_MODE_CONNECTOR_LVDS:
728 return ATOM_ENCODER_MODE_LVDS;
729 break;
730 case DRM_MODE_CONNECTOR_DisplayPort:
731 dig_connector = radeon_connector->con_priv;
732 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
108dc8e8 733 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
3473f542
AD		 734 if (radeon_audio != 0 &&
735 drm_detect_monitor_audio(radeon_connector_edid(connector)) &&
736 ASIC_IS_DCE4(rdev) && !ASIC_IS_DCE5(rdev))
e55bca26 737 return ATOM_ENCODER_MODE_DP_AUDIO;
3f03ced8 738 return ATOM_ENCODER_MODE_DP;
108dc8e8
AD		 739 } else if (radeon_audio != 0) {
740 if (radeon_connector->audio == RADEON_AUDIO_ENABLE)
741 return ATOM_ENCODER_MODE_HDMI;
377bd8a9 742 else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) &&
108dc8e8
AD		 743 (radeon_connector->audio == RADEON_AUDIO_AUTO))
744 return ATOM_ENCODER_MODE_HDMI;
745 else
746 return ATOM_ENCODER_MODE_DVI;
747 } else {
3f03ced8 748 return ATOM_ENCODER_MODE_DVI;
108dc8e8 749 }
3f03ced8
AD		 750 break;
751 case DRM_MODE_CONNECTOR_eDP:
3473f542
AD		 752 if (radeon_audio != 0 &&
753 drm_detect_monitor_audio(radeon_connector_edid(connector)) &&
754 ASIC_IS_DCE4(rdev) && !ASIC_IS_DCE5(rdev))
e55bca26 755 return ATOM_ENCODER_MODE_DP_AUDIO;
3f03ced8
AD		 756 return ATOM_ENCODER_MODE_DP;
757 case DRM_MODE_CONNECTOR_DVIA:
758 case DRM_MODE_CONNECTOR_VGA:
759 return ATOM_ENCODER_MODE_CRT;
760 break;
761 case DRM_MODE_CONNECTOR_Composite:
762 case DRM_MODE_CONNECTOR_SVIDEO:
763 case DRM_MODE_CONNECTOR_9PinDIN:
764 /* fix me */
765 return ATOM_ENCODER_MODE_TV;
766 /*return ATOM_ENCODER_MODE_CV;*/
767 break;
768 }
769}
770
771/*
772 * DIG Encoder/Transmitter Setup
773 *
774 * DCE 3.0/3.1
775 * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
776 * Supports up to 3 digital outputs
777 * - 2 DIG encoder blocks.
778 * DIG1 can drive UNIPHY link A or link B
779 * DIG2 can drive UNIPHY link B or LVTMA
780 *
781 * DCE 3.2
782 * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
783 * Supports up to 5 digital outputs
784 * - 2 DIG encoder blocks.
785 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
786 *
2d415869 787 * DCE 4.0/5.0/6.0
3f03ced8
AD		 788 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
789 * Supports up to 6 digital outputs
790 * - 6 DIG encoder blocks.
791 * - DIG to PHY mapping is hardcoded
792 * DIG1 drives UNIPHY0 link A, A+B
793 * DIG2 drives UNIPHY0 link B
794 * DIG3 drives UNIPHY1 link A, A+B
795 * DIG4 drives UNIPHY1 link B
796 * DIG5 drives UNIPHY2 link A, A+B
797 * DIG6 drives UNIPHY2 link B
798 *
799 * DCE 4.1
800 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
801 * Supports up to 6 digital outputs
802 * - 2 DIG encoder blocks.
2d415869 803 * llano
3f03ced8 804 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
2d415869
AD		 805 * ontario
806 * DIG1 drives UNIPHY0/1/2 link A
807 * DIG2 drives UNIPHY0/1/2 link B
3f03ced8
AD		 808 *
809 * Routing
810 * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
811 * Examples:
812 * crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI
813 * crtc1 -> dig1 -> UNIPHY0 link B -> DP
814 * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS
815 * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI
816 */
817
818union dig_encoder_control {
819 DIG_ENCODER_CONTROL_PS_ALLOCATION v1;
820 DIG_ENCODER_CONTROL_PARAMETERS_V2 v2;
821 DIG_ENCODER_CONTROL_PARAMETERS_V3 v3;
822 DIG_ENCODER_CONTROL_PARAMETERS_V4 v4;
823};
824
825void
826atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode)
827{
828 struct drm_device *dev = encoder->dev;
829 struct radeon_device *rdev = dev->dev_private;
830 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
831 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
832 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
833 union dig_encoder_control args;
834 int index = 0;
835 uint8_t frev, crev;
836 int dp_clock = 0;
837 int dp_lane_count = 0;
838 int hpd_id = RADEON_HPD_NONE;
3f03ced8
AD		 839
840 if (connector) {
841 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
842 struct radeon_connector_atom_dig *dig_connector =
843 radeon_connector->con_priv;
844
845 dp_clock = dig_connector->dp_clock;
846 dp_lane_count = dig_connector->dp_lane_count;
847 hpd_id = radeon_connector->hpd.hpd;
3f03ced8
AD		 848 }
849
850 /* no dig encoder assigned */
851 if (dig->dig_encoder == -1)
852 return;
853
854 memset(&args, 0, sizeof(args));
855
856 if (ASIC_IS_DCE4(rdev))
857 index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl);
858 else {
859 if (dig->dig_encoder)
860 index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
861 else
862 index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
863 }
864
865 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
866 return;
867
58cdcb8b
AD		 868 switch (frev) {
869 case 1:
870 switch (crev) {
871 case 1:
872 args.v1.ucAction = action;
873 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
874 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
875 args.v3.ucPanelMode = panel_mode;
876 else
877 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
878
879 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))
880 args.v1.ucLaneNum = dp_lane_count;
9aa59993 881 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
58cdcb8b
AD		 882 args.v1.ucLaneNum = 8;
883 else
884 args.v1.ucLaneNum = 4;
885
886 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000))
887 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
888 switch (radeon_encoder->encoder_id) {
889 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
890 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
891 break;
892 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
893 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
894 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
895 break;
896 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
897 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
898 break;
899 }
900 if (dig->linkb)
901 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
902 else
903 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
3f03ced8 904 break;
58cdcb8b
AD		 905 case 2:
906 case 3:
907 args.v3.ucAction = action;
908 args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
909 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
910 args.v3.ucPanelMode = panel_mode;
911 else
912 args.v3.ucEncoderMode = atombios_get_encoder_mode(encoder);
913
2f6fa79a 914 if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode))
58cdcb8b 915 args.v3.ucLaneNum = dp_lane_count;
9aa59993 916 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
58cdcb8b
AD		 917 args.v3.ucLaneNum = 8;
918 else
919 args.v3.ucLaneNum = 4;
920
2f6fa79a 921 if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode) && (dp_clock == 270000))
58cdcb8b
AD		 922 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
923 args.v3.acConfig.ucDigSel = dig->dig_encoder;
1f0e2943 924 args.v3.ucBitPerColor = radeon_atom_get_bpc(encoder);
3f03ced8 925 break;
58cdcb8b
AD		 926 case 4:
927 args.v4.ucAction = action;
928 args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
929 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
930 args.v4.ucPanelMode = panel_mode;
931 else
932 args.v4.ucEncoderMode = atombios_get_encoder_mode(encoder);
933
2f6fa79a 934 if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode))
58cdcb8b 935 args.v4.ucLaneNum = dp_lane_count;
9aa59993 936 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
58cdcb8b
AD		 937 args.v4.ucLaneNum = 8;
938 else
939 args.v4.ucLaneNum = 4;
940
2f6fa79a 941 if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode)) {
e68adef8 942 if (dp_clock == 540000)
58cdcb8b 943 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ;
e68adef8
AD		 944 else if (dp_clock == 324000)
945 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_3_24GHZ;
946 else if (dp_clock == 270000)
947 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ;
948 else
949 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ;
58cdcb8b
AD		 950 }
951 args.v4.acConfig.ucDigSel = dig->dig_encoder;
1f0e2943 952 args.v4.ucBitPerColor = radeon_atom_get_bpc(encoder);
58cdcb8b
AD		 953 if (hpd_id == RADEON_HPD_NONE)
954 args.v4.ucHPD_ID = 0;
955 else
956 args.v4.ucHPD_ID = hpd_id + 1;
3f03ced8 957 break;
3f03ced8 958 default:
58cdcb8b 959 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3f03ced8
AD		 960 break;
961 }
58cdcb8b
AD		 962 break;
963 default:
964 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
965 break;
3f03ced8
AD		 966 }
967
968 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
969
970}
971
972union dig_transmitter_control {
973 DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
974 DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
975 DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
976 DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4;
47aef7a8 977 DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 v5;
3f03ced8
AD		 978};
979
980void
981atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set)
982{
983 struct drm_device *dev = encoder->dev;
984 struct radeon_device *rdev = dev->dev_private;
985 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
986 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
987 struct drm_connector *connector;
988 union dig_transmitter_control args;
989 int index = 0;
990 uint8_t frev, crev;
991 bool is_dp = false;
992 int pll_id = 0;
993 int dp_clock = 0;
994 int dp_lane_count = 0;
995 int connector_object_id = 0;
996 int igp_lane_info = 0;
997 int dig_encoder = dig->dig_encoder;
47aef7a8 998 int hpd_id = RADEON_HPD_NONE;
3f03ced8
AD		 999
1000 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1001 connector = radeon_get_connector_for_encoder_init(encoder);
1002 /* just needed to avoid bailing in the encoder check. the encoder
1003 * isn't used for init
1004 */
1005 dig_encoder = 0;
1006 } else
1007 connector = radeon_get_connector_for_encoder(encoder);
1008
1009 if (connector) {
1010 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1011 struct radeon_connector_atom_dig *dig_connector =
1012 radeon_connector->con_priv;
1013
47aef7a8 1014 hpd_id = radeon_connector->hpd.hpd;
3f03ced8
AD		 1015 dp_clock = dig_connector->dp_clock;
1016 dp_lane_count = dig_connector->dp_lane_count;
1017 connector_object_id =
1018 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1019 igp_lane_info = dig_connector->igp_lane_info;
1020 }
1021
a3b08294
AD		 1022 if (encoder->crtc) {
1023 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1024 pll_id = radeon_crtc->pll_id;
1025 }
1026
3f03ced8
AD		 1027 /* no dig encoder assigned */
1028 if (dig_encoder == -1)
1029 return;
1030
1031 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)))
1032 is_dp = true;
1033
1034 memset(&args, 0, sizeof(args));
1035
1036 switch (radeon_encoder->encoder_id) {
1037 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1038 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1039 break;
1040 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1041 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1042 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
e68adef8 1043 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3f03ced8
AD		 1044 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1045 break;
1046 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1047 index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl);
1048 break;
1049 }
1050
1051 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1052 return;
1053
a3b08294
AD		 1054 switch (frev) {
1055 case 1:
1056 switch (crev) {
1057 case 1:
1058 args.v1.ucAction = action;
1059 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1060 args.v1.usInitInfo = cpu_to_le16(connector_object_id);
1061 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1062 args.v1.asMode.ucLaneSel = lane_num;
1063 args.v1.asMode.ucLaneSet = lane_set;
1064 } else {
1065 if (is_dp)
6e76a2df 1066 args.v1.usPixelClock = cpu_to_le16(dp_clock / 10);
9aa59993 1067 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
a3b08294
AD		 1068 args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1069 else
1070 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1071 }
3f03ced8 1072
a3b08294 1073 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
3f03ced8 1074
a3b08294
AD		 1075 if (dig_encoder)
1076 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
1077 else
1078 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
1079
1080 if ((rdev->flags & RADEON_IS_IGP) &&
1081 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) {
9aa59993
AD		 1082 if (is_dp ||
1083 !radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) {
a3b08294
AD		 1084 if (igp_lane_info & 0x1)
1085 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
1086 else if (igp_lane_info & 0x2)
1087 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
1088 else if (igp_lane_info & 0x4)
1089 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
1090 else if (igp_lane_info & 0x8)
1091 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
1092 } else {
1093 if (igp_lane_info & 0x3)
1094 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
1095 else if (igp_lane_info & 0xc)
1096 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
1097 }
1098 }
1099
1100 if (dig->linkb)
1101 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
1102 else
1103 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
1104
1105 if (is_dp)
1106 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1107 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1108 if (dig->coherent_mode)
1109 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
9aa59993 1110 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
a3b08294
AD		 1111 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
1112 }
1113 break;
1114 case 2:
1115 args.v2.ucAction = action;
1116 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1117 args.v2.usInitInfo = cpu_to_le16(connector_object_id);
1118 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1119 args.v2.asMode.ucLaneSel = lane_num;
1120 args.v2.asMode.ucLaneSet = lane_set;
1121 } else {
1122 if (is_dp)
6e76a2df 1123 args.v2.usPixelClock = cpu_to_le16(dp_clock / 10);
9aa59993 1124 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
a3b08294
AD		 1125 args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1126 else
1127 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1128 }
1129
1130 args.v2.acConfig.ucEncoderSel = dig_encoder;
1131 if (dig->linkb)
1132 args.v2.acConfig.ucLinkSel = 1;
1133
1134 switch (radeon_encoder->encoder_id) {
1135 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1136 args.v2.acConfig.ucTransmitterSel = 0;
1137 break;
1138 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1139 args.v2.acConfig.ucTransmitterSel = 1;
1140 break;
1141 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1142 args.v2.acConfig.ucTransmitterSel = 2;
1143 break;
1144 }
3f03ced8 1145
3f03ced8 1146 if (is_dp) {
a3b08294
AD		 1147 args.v2.acConfig.fCoherentMode = 1;
1148 args.v2.acConfig.fDPConnector = 1;
1149 } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1150 if (dig->coherent_mode)
1151 args.v2.acConfig.fCoherentMode = 1;
9aa59993 1152 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
a3b08294
AD		 1153 args.v2.acConfig.fDualLinkConnector = 1;
1154 }
1155 break;
1156 case 3:
1157 args.v3.ucAction = action;
1158 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1159 args.v3.usInitInfo = cpu_to_le16(connector_object_id);
1160 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1161 args.v3.asMode.ucLaneSel = lane_num;
1162 args.v3.asMode.ucLaneSet = lane_set;
1163 } else {
1164 if (is_dp)
6e76a2df 1165 args.v3.usPixelClock = cpu_to_le16(dp_clock / 10);
9aa59993 1166 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
a3b08294 1167 args.v3.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
3f03ced8 1168 else
a3b08294
AD		 1169 args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1170 }
1171
1172 if (is_dp)
1173 args.v3.ucLaneNum = dp_lane_count;
9aa59993 1174 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
a3b08294
AD		 1175 args.v3.ucLaneNum = 8;
1176 else
1177 args.v3.ucLaneNum = 4;
1178
1179 if (dig->linkb)
1180 args.v3.acConfig.ucLinkSel = 1;
1181 if (dig_encoder & 1)
1182 args.v3.acConfig.ucEncoderSel = 1;
1183
1184 /* Select the PLL for the PHY
1185 * DP PHY should be clocked from external src if there is
1186 * one.
1187 */
3f03ced8
AD		 1188 /* On DCE4, if there is an external clock, it generates the DP ref clock */
1189 if (is_dp && rdev->clock.dp_extclk)
1190 args.v3.acConfig.ucRefClkSource = 2; /* external src */
1191 else
1192 args.v3.acConfig.ucRefClkSource = pll_id;
3f03ced8 1193
a3b08294
AD		 1194 switch (radeon_encoder->encoder_id) {
1195 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1196 args.v3.acConfig.ucTransmitterSel = 0;
1197 break;
1198 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1199 args.v3.acConfig.ucTransmitterSel = 1;
1200 break;
1201 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1202 args.v3.acConfig.ucTransmitterSel = 2;
1203 break;
1204 }
3f03ced8 1205
a3b08294
AD		 1206 if (is_dp)
1207 args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
1208 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1209 if (dig->coherent_mode)
1210 args.v3.acConfig.fCoherentMode = 1;
9aa59993 1211 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
a3b08294
AD		 1212 args.v3.acConfig.fDualLinkConnector = 1;
1213 }
3f03ced8 1214 break;
a3b08294
AD		 1215 case 4:
1216 args.v4.ucAction = action;
1217 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1218 args.v4.usInitInfo = cpu_to_le16(connector_object_id);
1219 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1220 args.v4.asMode.ucLaneSel = lane_num;
1221 args.v4.asMode.ucLaneSet = lane_set;
3f03ced8 1222 } else {
a3b08294 1223 if (is_dp)
6e76a2df 1224 args.v4.usPixelClock = cpu_to_le16(dp_clock / 10);
9aa59993 1225 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
a3b08294
AD		 1226 args.v4.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1227 else
1228 args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
3f03ced8 1229 }
3f03ced8 1230
a3b08294
AD		 1231 if (is_dp)
1232 args.v4.ucLaneNum = dp_lane_count;
9aa59993 1233 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
a3b08294
AD		 1234 args.v4.ucLaneNum = 8;
1235 else
1236 args.v4.ucLaneNum = 4;
3f03ced8 1237
a3b08294
AD		 1238 if (dig->linkb)
1239 args.v4.acConfig.ucLinkSel = 1;
1240 if (dig_encoder & 1)
1241 args.v4.acConfig.ucEncoderSel = 1;
1242
1243 /* Select the PLL for the PHY
1244 * DP PHY should be clocked from external src if there is
1245 * one.
1246 */
1247 /* On DCE5 DCPLL usually generates the DP ref clock */
1248 if (is_dp) {
1249 if (rdev->clock.dp_extclk)
1250 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK;
1251 else
1252 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL;
1253 } else
1254 args.v4.acConfig.ucRefClkSource = pll_id;
1255
1256 switch (radeon_encoder->encoder_id) {
1257 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1258 args.v4.acConfig.ucTransmitterSel = 0;
1259 break;
1260 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1261 args.v4.acConfig.ucTransmitterSel = 1;
1262 break;
1263 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1264 args.v4.acConfig.ucTransmitterSel = 2;
1265 break;
1266 }
1267
1268 if (is_dp)
1269 args.v4.acConfig.fCoherentMode = 1; /* DP requires coherent */
1270 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1271 if (dig->coherent_mode)
1272 args.v4.acConfig.fCoherentMode = 1;
9aa59993 1273 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
a3b08294
AD		 1274 args.v4.acConfig.fDualLinkConnector = 1;
1275 }
1276 break;
47aef7a8
AD		 1277 case 5:
1278 args.v5.ucAction = action;
1279 if (is_dp)
1280 args.v5.usSymClock = cpu_to_le16(dp_clock / 10);
1281 else
1282 args.v5.usSymClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1283
1284 switch (radeon_encoder->encoder_id) {
1285 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1286 if (dig->linkb)
1287 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYB;
1288 else
1289 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYA;
1290 break;
1291 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1292 if (dig->linkb)
1293 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYD;
1294 else
1295 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYC;
1296 break;
1297 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1298 if (dig->linkb)
1299 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYF;
1300 else
1301 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYE;
1302 break;
e68adef8
AD		 1303 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1304 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYG;
1305 break;
47aef7a8
AD		 1306 }
1307 if (is_dp)
1308 args.v5.ucLaneNum = dp_lane_count;
d03874c8 1309 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
47aef7a8
AD		 1310 args.v5.ucLaneNum = 8;
1311 else
1312 args.v5.ucLaneNum = 4;
1313 args.v5.ucConnObjId = connector_object_id;
1314 args.v5.ucDigMode = atombios_get_encoder_mode(encoder);
1315
1316 if (is_dp && rdev->clock.dp_extclk)
1317 args.v5.asConfig.ucPhyClkSrcId = ENCODER_REFCLK_SRC_EXTCLK;
1318 else
1319 args.v5.asConfig.ucPhyClkSrcId = pll_id;
1320
1321 if (is_dp)
1322 args.v5.asConfig.ucCoherentMode = 1; /* DP requires coherent */
1323 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1324 if (dig->coherent_mode)
1325 args.v5.asConfig.ucCoherentMode = 1;
1326 }
1327 if (hpd_id == RADEON_HPD_NONE)
1328 args.v5.asConfig.ucHPDSel = 0;
1329 else
1330 args.v5.asConfig.ucHPDSel = hpd_id + 1;
1331 args.v5.ucDigEncoderSel = 1 << dig_encoder;
1332 args.v5.ucDPLaneSet = lane_set;
1333 break;
a3b08294
AD		 1334 default:
1335 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1336 break;
3f03ced8 1337 }
a3b08294
AD		 1338 break;
1339 default:
1340 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1341 break;
3f03ced8
AD		 1342 }
1343
1344 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1345}
1346
1347bool
1348atombios_set_edp_panel_power(struct drm_connector *connector, int action)
1349{
1350 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1351 struct drm_device *dev = radeon_connector->base.dev;
1352 struct radeon_device *rdev = dev->dev_private;
1353 union dig_transmitter_control args;
1354 int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1355 uint8_t frev, crev;
1356
1357 if (connector->connector_type != DRM_MODE_CONNECTOR_eDP)
1358 goto done;
1359
1360 if (!ASIC_IS_DCE4(rdev))
1361 goto done;
1362
1363 if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) &&
1364 (action != ATOM_TRANSMITTER_ACTION_POWER_OFF))
1365 goto done;
1366
1367 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1368 goto done;
1369
1370 memset(&args, 0, sizeof(args));
1371
1372 args.v1.ucAction = action;
1373
1374 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1375
1376 /* wait for the panel to power up */
1377 if (action == ATOM_TRANSMITTER_ACTION_POWER_ON) {
1378 int i;
1379
1380 for (i = 0; i < 300; i++) {
1381 if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd))
1382 return true;
1383 mdelay(1);
1384 }
1385 return false;
1386 }
1387done:
1388 return true;
1389}
1390
1391union external_encoder_control {
1392 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1;
1393 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3;
1394};
1395
1396static void
1397atombios_external_encoder_setup(struct drm_encoder *encoder,
1398 struct drm_encoder *ext_encoder,
1399 int action)
1400{
1401 struct drm_device *dev = encoder->dev;
1402 struct radeon_device *rdev = dev->dev_private;
1403 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1404 struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder);
1405 union external_encoder_control args;
1406 struct drm_connector *connector;
1407 int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl);
1408 u8 frev, crev;
1409 int dp_clock = 0;
1410 int dp_lane_count = 0;
1411 int connector_object_id = 0;
1412 u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
3f03ced8
AD		 1413
1414 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1415 connector = radeon_get_connector_for_encoder_init(encoder);
1416 else
1417 connector = radeon_get_connector_for_encoder(encoder);
1418
1419 if (connector) {
1420 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1421 struct radeon_connector_atom_dig *dig_connector =
1422 radeon_connector->con_priv;
1423
1424 dp_clock = dig_connector->dp_clock;
1425 dp_lane_count = dig_connector->dp_lane_count;
1426 connector_object_id =
1427 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
3f03ced8
AD		 1428 }
1429
1430 memset(&args, 0, sizeof(args));
1431
1432 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1433 return;
1434
1435 switch (frev) {
1436 case 1:
1437 /* no params on frev 1 */
1438 break;
1439 case 2:
1440 switch (crev) {
1441 case 1:
1442 case 2:
1443 args.v1.sDigEncoder.ucAction = action;
1444 args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1445 args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1446
1447 if (ENCODER_MODE_IS_DP(args.v1.sDigEncoder.ucEncoderMode)) {
1448 if (dp_clock == 270000)
1449 args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
1450 args.v1.sDigEncoder.ucLaneNum = dp_lane_count;
9aa59993 1451 } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
3f03ced8
AD		 1452 args.v1.sDigEncoder.ucLaneNum = 8;
1453 else
1454 args.v1.sDigEncoder.ucLaneNum = 4;
1455 break;
1456 case 3:
1457 args.v3.sExtEncoder.ucAction = action;
1458 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1459 args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id);
1460 else
1461 args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1462 args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1463
1464 if (ENCODER_MODE_IS_DP(args.v3.sExtEncoder.ucEncoderMode)) {
1465 if (dp_clock == 270000)
1466 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
1467 else if (dp_clock == 540000)
1468 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ;
1469 args.v3.sExtEncoder.ucLaneNum = dp_lane_count;
9aa59993 1470 } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
3f03ced8
AD		 1471 args.v3.sExtEncoder.ucLaneNum = 8;
1472 else
1473 args.v3.sExtEncoder.ucLaneNum = 4;
1474 switch (ext_enum) {
1475 case GRAPH_OBJECT_ENUM_ID1:
1476 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1;
1477 break;
1478 case GRAPH_OBJECT_ENUM_ID2:
1479 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2;
1480 break;
1481 case GRAPH_OBJECT_ENUM_ID3:
1482 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3;
1483 break;
1484 }
1f0e2943 1485 args.v3.sExtEncoder.ucBitPerColor = radeon_atom_get_bpc(encoder);
3f03ced8
AD		 1486 break;
1487 default:
1488 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1489 return;
1490 }
1491 break;
1492 default:
1493 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1494 return;
1495 }
1496 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1497}
1498
1499static void
1500atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
1501{
1502 struct drm_device *dev = encoder->dev;
1503 struct radeon_device *rdev = dev->dev_private;
1504 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1505 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1506 ENABLE_YUV_PS_ALLOCATION args;
1507 int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
1508 uint32_t temp, reg;
1509
1510 memset(&args, 0, sizeof(args));
1511
1512 if (rdev->family >= CHIP_R600)
1513 reg = R600_BIOS_3_SCRATCH;
1514 else
1515 reg = RADEON_BIOS_3_SCRATCH;
1516
1517 /* XXX: fix up scratch reg handling */
1518 temp = RREG32(reg);
1519 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1520 WREG32(reg, (ATOM_S3_TV1_ACTIVE |
1521 (radeon_crtc->crtc_id << 18)));
1522 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1523 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
1524 else
1525 WREG32(reg, 0);
1526
1527 if (enable)
1528 args.ucEnable = ATOM_ENABLE;
1529 args.ucCRTC = radeon_crtc->crtc_id;
1530
1531 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1532
1533 WREG32(reg, temp);
1534}
1535
1536static void
1537radeon_atom_encoder_dpms_avivo(struct drm_encoder *encoder, int mode)
1538{
1539 struct drm_device *dev = encoder->dev;
1540 struct radeon_device *rdev = dev->dev_private;
1541 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1542 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
1543 int index = 0;
1544
1545 memset(&args, 0, sizeof(args));
1546
1547 switch (radeon_encoder->encoder_id) {
1548 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1549 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1550 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
1551 break;
1552 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1553 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1554 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1555 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1556 break;
1557 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1558 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1559 break;
1560 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1561 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1562 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1563 else
1564 index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
1565 break;
1566 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1567 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1568 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1569 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1570 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1571 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1572 else
1573 index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
1574 break;
1575 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1576 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1577 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1578 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1579 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1580 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1581 else
1582 index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
1583 break;
1584 default:
1585 return;
1586 }
1587
1588 switch (mode) {
1589 case DRM_MODE_DPMS_ON:
1590 args.ucAction = ATOM_ENABLE;
1591 /* workaround for DVOOutputControl on some RS690 systems */
1592 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DDI) {
1593 u32 reg = RREG32(RADEON_BIOS_3_SCRATCH);
1594 WREG32(RADEON_BIOS_3_SCRATCH, reg & ~ATOM_S3_DFP2I_ACTIVE);
1595 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1596 WREG32(RADEON_BIOS_3_SCRATCH, reg);
1597 } else
1598 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1599 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1600 args.ucAction = ATOM_LCD_BLON;
1601 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1602 }
1603 break;
1604 case DRM_MODE_DPMS_STANDBY:
1605 case DRM_MODE_DPMS_SUSPEND:
1606 case DRM_MODE_DPMS_OFF:
1607 args.ucAction = ATOM_DISABLE;
1608 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1609 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1610 args.ucAction = ATOM_LCD_BLOFF;
1611 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1612 }
1613 break;
1614 }
1615}
1616
1617static void
1618radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode)
1619{
1620 struct drm_device *dev = encoder->dev;
1621 struct radeon_device *rdev = dev->dev_private;
1622 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
8d1af57a
AD		 1623 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1624 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
3f03ced8
AD		 1625 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1626 struct radeon_connector *radeon_connector = NULL;
1627 struct radeon_connector_atom_dig *radeon_dig_connector = NULL;
6f50e075 1628 bool travis_quirk = false;
3f03ced8
AD		 1629
1630 if (connector) {
1631 radeon_connector = to_radeon_connector(connector);
1632 radeon_dig_connector = radeon_connector->con_priv;
6f50e075
AD		 1633 if ((radeon_connector_encoder_get_dp_bridge_encoder_id(connector) ==
1634 ENCODER_OBJECT_ID_TRAVIS) &&
1635 (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) &&
1636 !ASIC_IS_DCE5(rdev))
1637 travis_quirk = true;
3f03ced8
AD		 1638 }
1639
1640 switch (mode) {
1641 case DRM_MODE_DPMS_ON:
8d1af57a
AD		 1642 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {
1643 if (!connector)
1644 dig->panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
1645 else
1646 dig->panel_mode = radeon_dp_get_panel_mode(encoder, connector);
1647
1648 /* setup and enable the encoder */
1649 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1650 atombios_dig_encoder_setup(encoder,
1651 ATOM_ENCODER_CMD_SETUP_PANEL_MODE,
1652 dig->panel_mode);
1653 if (ext_encoder) {
1654 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev))
1655 atombios_external_encoder_setup(encoder, ext_encoder,
1656 EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP);
fcedac67 1657 }
8d1af57a
AD		 1658 } else if (ASIC_IS_DCE4(rdev)) {
1659 /* setup and enable the encoder */
1660 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
8d1af57a
AD		 1661 } else {
1662 /* setup and enable the encoder and transmitter */
1663 atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0);
1664 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
fcedac67 1665 }
3f03ced8
AD		 1666 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1667 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1668 atombios_set_edp_panel_power(connector,
1669 ATOM_TRANSMITTER_ACTION_POWER_ON);
1670 radeon_dig_connector->edp_on = true;
1671 }
6f50e075
AD		 1672 }
1673 /* enable the transmitter */
1674 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1675 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1676 /* DP_SET_POWER_D0 is set in radeon_dp_link_train */
3f03ced8
AD		 1677 radeon_dp_link_train(encoder, connector);
1678 if (ASIC_IS_DCE4(rdev))
1679 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0);
1680 }
1681 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
6f50e075
AD		 1682 atombios_dig_transmitter_setup(encoder,
1683 ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
1684 if (ext_encoder)
1685 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);
3f03ced8
AD		 1686 break;
1687 case DRM_MODE_DPMS_STANDBY:
1688 case DRM_MODE_DPMS_SUSPEND:
1689 case DRM_MODE_DPMS_OFF:
6f50e075
AD		 1690 if (ASIC_IS_DCE4(rdev)) {
1691 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector)
1692 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0);
1693 }
1694 if (ext_encoder)
1695 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_DISABLE);
1696 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1697 atombios_dig_transmitter_setup(encoder,
1698 ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
1699
1700 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) &&
1701 connector && !travis_quirk)
1702 radeon_dp_set_rx_power_state(connector, DP_SET_POWER_D3);
40390961 1703 if (ASIC_IS_DCE4(rdev)) {
8d1af57a 1704 /* disable the transmitter */
6f50e075
AD		 1705 atombios_dig_transmitter_setup(encoder,
1706 ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
8d1af57a
AD		 1707 } else {
1708 /* disable the encoder and transmitter */
6f50e075
AD		 1709 atombios_dig_transmitter_setup(encoder,
1710 ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
8d1af57a
AD		 1711 atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);
1712 }
3f03ced8 1713 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
6f50e075
AD		 1714 if (travis_quirk)
1715 radeon_dp_set_rx_power_state(connector, DP_SET_POWER_D3);
3f03ced8
AD		 1716 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1717 atombios_set_edp_panel_power(connector,
1718 ATOM_TRANSMITTER_ACTION_POWER_OFF);
1719 radeon_dig_connector->edp_on = false;
1720 }
1721 }
3f03ced8
AD		 1722 break;
1723 }
1724}
1725
1726static void
1727radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1728{
1729 struct drm_device *dev = encoder->dev;
1730 struct radeon_device *rdev = dev->dev_private;
1731 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
5c046a57
AD		 1732 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1733 int encoder_mode = atombios_get_encoder_mode(encoder);
3f03ced8
AD		 1734
1735 DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
1736 radeon_encoder->encoder_id, mode, radeon_encoder->devices,
1737 radeon_encoder->active_device);
5c046a57
AD		 1738
1739 if (connector && (radeon_audio != 0) &&
1740 ((encoder_mode == ATOM_ENCODER_MODE_HDMI) ||
1741 (ENCODER_MODE_IS_DP(encoder_mode) &&
1742 drm_detect_monitor_audio(radeon_connector_edid(connector)))))
1743 radeon_audio_dpms(encoder, mode);
1744
3f03ced8
AD		 1745 switch (radeon_encoder->encoder_id) {
1746 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1747 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1748 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1749 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1750 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1751 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1752 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1753 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1754 radeon_atom_encoder_dpms_avivo(encoder, mode);
1755 break;
1756 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1757 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1758 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
e68adef8 1759 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3f03ced8
AD		 1760 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1761 radeon_atom_encoder_dpms_dig(encoder, mode);
1762 break;
1763 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1764 if (ASIC_IS_DCE5(rdev)) {
1765 switch (mode) {
1766 case DRM_MODE_DPMS_ON:
1767 atombios_dvo_setup(encoder, ATOM_ENABLE);
1768 break;
1769 case DRM_MODE_DPMS_STANDBY:
1770 case DRM_MODE_DPMS_SUSPEND:
1771 case DRM_MODE_DPMS_OFF:
1772 atombios_dvo_setup(encoder, ATOM_DISABLE);
1773 break;
1774 }
1775 } else if (ASIC_IS_DCE3(rdev))
1776 radeon_atom_encoder_dpms_dig(encoder, mode);
1777 else
1778 radeon_atom_encoder_dpms_avivo(encoder, mode);
1779 break;
1780 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1781 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1782 if (ASIC_IS_DCE5(rdev)) {
1783 switch (mode) {
1784 case DRM_MODE_DPMS_ON:
1785 atombios_dac_setup(encoder, ATOM_ENABLE);
1786 break;
1787 case DRM_MODE_DPMS_STANDBY:
1788 case DRM_MODE_DPMS_SUSPEND:
1789 case DRM_MODE_DPMS_OFF:
1790 atombios_dac_setup(encoder, ATOM_DISABLE);
1791 break;
1792 }
1793 } else
1794 radeon_atom_encoder_dpms_avivo(encoder, mode);
1795 break;
1796 default:
1797 return;
1798 }
1799
3f03ced8
AD		 1800 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1801
1802}
1803
1804union crtc_source_param {
1805 SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
1806 SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
1807};
1808
1809static void
1810atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1811{
1812 struct drm_device *dev = encoder->dev;
1813 struct radeon_device *rdev = dev->dev_private;
1814 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1815 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1816 union crtc_source_param args;
1817 int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
1818 uint8_t frev, crev;
1819 struct radeon_encoder_atom_dig *dig;
1820
1821 memset(&args, 0, sizeof(args));
1822
1823 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1824 return;
1825
1826 switch (frev) {
1827 case 1:
1828 switch (crev) {
1829 case 1:
1830 default:
1831 if (ASIC_IS_AVIVO(rdev))
1832 args.v1.ucCRTC = radeon_crtc->crtc_id;
1833 else {
1834 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) {
1835 args.v1.ucCRTC = radeon_crtc->crtc_id;
1836 } else {
1837 args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
1838 }
1839 }
1840 switch (radeon_encoder->encoder_id) {
1841 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1842 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1843 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1844 break;
1845 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1846 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1847 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
1848 args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1849 else
1850 args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1851 break;
1852 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1853 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1854 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1855 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1856 break;
1857 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1858 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1859 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1860 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1861 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1862 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1863 else
1864 args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1865 break;
1866 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1867 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1868 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1869 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1870 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1871 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1872 else
1873 args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1874 break;
1875 }
1876 break;
1877 case 2:
1878 args.v2.ucCRTC = radeon_crtc->crtc_id;
1879 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) {
1880 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1881
1882 if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)
1883 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
1884 else if (connector->connector_type == DRM_MODE_CONNECTOR_VGA)
1885 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_CRT;
1886 else
1887 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
64252835
AD		 1888 } else if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1889 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
1890 } else {
3f03ced8 1891 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
64252835 1892 }
3f03ced8
AD		 1893 switch (radeon_encoder->encoder_id) {
1894 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1895 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1896 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
e68adef8 1897 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3f03ced8
AD		 1898 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1899 dig = radeon_encoder->enc_priv;
1900 switch (dig->dig_encoder) {
1901 case 0:
1902 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1903 break;
1904 case 1:
1905 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1906 break;
1907 case 2:
1908 args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
1909 break;
1910 case 3:
1911 args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
1912 break;
1913 case 4:
1914 args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
1915 break;
1916 case 5:
1917 args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
1918 break;
e68adef8
AD		 1919 case 6:
1920 args.v2.ucEncoderID = ASIC_INT_DIG7_ENCODER_ID;
1921 break;
3f03ced8
AD		 1922 }
1923 break;
1924 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1925 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1926 break;
1927 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1928 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1929 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1930 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1931 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1932 else
1933 args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1934 break;
1935 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1936 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1937 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1938 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1939 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1940 else
1941 args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1942 break;
1943 }
1944 break;
1945 }
1946 break;
1947 default:
1948 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1949 return;
1950 }
1951
1952 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1953
1954 /* update scratch regs with new routing */
1955 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1956}
1957
1958static void
1959atombios_apply_encoder_quirks(struct drm_encoder *encoder,
1960 struct drm_display_mode *mode)
1961{
1962 struct drm_device *dev = encoder->dev;
1963 struct radeon_device *rdev = dev->dev_private;
1964 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1965 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1966
1967 /* Funky macbooks */
1968 if ((dev->pdev->device == 0x71C5) &&
1969 (dev->pdev->subsystem_vendor == 0x106b) &&
1970 (dev->pdev->subsystem_device == 0x0080)) {
1971 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1972 uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
1973
1974 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
1975 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
1976
1977 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
1978 }
1979 }
1980
1981 /* set scaler clears this on some chips */
1982 if (ASIC_IS_AVIVO(rdev) &&
1983 (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) {
d798f2f2
AD		 1984 if (ASIC_IS_DCE8(rdev)) {
1985 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1986 WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset,
1987 CIK_INTERLEAVE_EN);
1988 else
1989 WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1990 } else if (ASIC_IS_DCE4(rdev)) {
3f03ced8
AD		 1991 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1992 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset,
1993 EVERGREEN_INTERLEAVE_EN);
1994 else
1995 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1996 } else {
1997 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1998 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
1999 AVIVO_D1MODE_INTERLEAVE_EN);
2000 else
2001 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
2002 }
2003 }
2004}
2005
2006static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder)
2007{
2008 struct drm_device *dev = encoder->dev;
2009 struct radeon_device *rdev = dev->dev_private;
2010 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
2011 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2012 struct drm_encoder *test_encoder;
41fa5437 2013 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
3f03ced8
AD		 2014 uint32_t dig_enc_in_use = 0;
2015
41fa5437
AD		 2016 if (ASIC_IS_DCE6(rdev)) {
2017 /* DCE6 */
2018 switch (radeon_encoder->encoder_id) {
2019 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2020 if (dig->linkb)
2021 return 1;
2022 else
2023 return 0;
2024 break;
2025 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2026 if (dig->linkb)
2027 return 3;
2028 else
2029 return 2;
2030 break;
2031 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2032 if (dig->linkb)
2033 return 5;
2034 else
2035 return 4;
2036 break;
e68adef8
AD		 2037 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2038 return 6;
2039 break;
41fa5437
AD		 2040 }
2041 } else if (ASIC_IS_DCE4(rdev)) {
2042 /* DCE4/5 */
2043 if (ASIC_IS_DCE41(rdev) && !ASIC_IS_DCE61(rdev)) {
3f03ced8
AD		 2044 /* ontario follows DCE4 */
2045 if (rdev->family == CHIP_PALM) {
2046 if (dig->linkb)
2047 return 1;
2048 else
2049 return 0;
2050 } else
2051 /* llano follows DCE3.2 */
2052 return radeon_crtc->crtc_id;
2053 } else {
2054 switch (radeon_encoder->encoder_id) {
2055 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2056 if (dig->linkb)
2057 return 1;
2058 else
2059 return 0;
2060 break;
2061 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2062 if (dig->linkb)
2063 return 3;
2064 else
2065 return 2;
2066 break;
2067 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2068 if (dig->linkb)
2069 return 5;
2070 else
2071 return 4;
2072 break;
2073 }
2074 }
2075 }
2076
2077 /* on DCE32 and encoder can driver any block so just crtc id */
2078 if (ASIC_IS_DCE32(rdev)) {
2079 return radeon_crtc->crtc_id;
2080 }
2081
2082 /* on DCE3 - LVTMA can only be driven by DIGB */
2083 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
2084 struct radeon_encoder *radeon_test_encoder;
2085
2086 if (encoder == test_encoder)
2087 continue;
2088
2089 if (!radeon_encoder_is_digital(test_encoder))
2090 continue;
2091
2092 radeon_test_encoder = to_radeon_encoder(test_encoder);
2093 dig = radeon_test_encoder->enc_priv;
2094
2095 if (dig->dig_encoder >= 0)
2096 dig_enc_in_use |= (1 << dig->dig_encoder);
2097 }
2098
2099 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) {
2100 if (dig_enc_in_use & 0x2)
2101 DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
2102 return 1;
2103 }
2104 if (!(dig_enc_in_use & 1))
2105 return 0;
2106 return 1;
2107}
2108
2109/* This only needs to be called once at startup */
2110void
2111radeon_atom_encoder_init(struct radeon_device *rdev)
2112{
2113 struct drm_device *dev = rdev->ddev;
2114 struct drm_encoder *encoder;
2115
2116 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2117 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2118 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2119
2120 switch (radeon_encoder->encoder_id) {
2121 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2122 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2123 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
e68adef8 2124 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3f03ced8
AD		 2125 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2126 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
2127 break;
2128 default:
2129 break;
2130 }
2131
1d3949c4 2132 if (ext_encoder && (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)))
3f03ced8
AD		 2133 atombios_external_encoder_setup(encoder, ext_encoder,
2134 EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT);
2135 }
2136}
2137
2138static void
2139radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
2140 struct drm_display_mode *mode,
2141 struct drm_display_mode *adjusted_mode)
2142{
2143 struct drm_device *dev = encoder->dev;
2144 struct radeon_device *rdev = dev->dev_private;
2145 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3473f542 2146 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
6f945693 2147 int encoder_mode;
3f03ced8
AD		 2148
2149 radeon_encoder->pixel_clock = adjusted_mode->clock;
2150
8d1af57a
AD		 2151 /* need to call this here rather than in prepare() since we need some crtc info */
2152 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2153
3f03ced8
AD		 2154 if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) {
2155 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
2156 atombios_yuv_setup(encoder, true);
2157 else
2158 atombios_yuv_setup(encoder, false);
2159 }
2160
2161 switch (radeon_encoder->encoder_id) {
2162 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2163 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2164 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2165 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2166 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
2167 break;
2168 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2169 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2170 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
e68adef8 2171 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3f03ced8 2172 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
8d1af57a 2173 /* handled in dpms */
3f03ced8
AD		 2174 break;
2175 case ENCODER_OBJECT_ID_INTERNAL_DDI:
2176 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2177 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2178 atombios_dvo_setup(encoder, ATOM_ENABLE);
2179 break;
2180 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2181 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2182 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2183 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2184 atombios_dac_setup(encoder, ATOM_ENABLE);
2185 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) {
2186 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2187 atombios_tv_setup(encoder, ATOM_ENABLE);
2188 else
2189 atombios_tv_setup(encoder, ATOM_DISABLE);
2190 }
2191 break;
2192 }
2193
3f03ced8 2194 atombios_apply_encoder_quirks(encoder, adjusted_mode);
5c046a57
AD		 2195
2196 encoder_mode = atombios_get_encoder_mode(encoder);
2197 if (connector && (radeon_audio != 0) &&
2198 ((encoder_mode == ATOM_ENCODER_MODE_HDMI) ||
2199 (ENCODER_MODE_IS_DP(encoder_mode) &&
2200 drm_detect_monitor_audio(radeon_connector_edid(connector)))))
2201 radeon_audio_mode_set(encoder, adjusted_mode);
3f03ced8
AD		 2202}
2203
2204static bool
2205atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2206{
2207 struct drm_device *dev = encoder->dev;
2208 struct radeon_device *rdev = dev->dev_private;
2209 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2210 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2211
2212 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
2213 ATOM_DEVICE_CV_SUPPORT |
2214 ATOM_DEVICE_CRT_SUPPORT)) {
2215 DAC_LOAD_DETECTION_PS_ALLOCATION args;
2216 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
2217 uint8_t frev, crev;
2218
2219 memset(&args, 0, sizeof(args));
2220
2221 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2222 return false;
2223
2224 args.sDacload.ucMisc = 0;
2225
2226 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
2227 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
2228 args.sDacload.ucDacType = ATOM_DAC_A;
2229 else
2230 args.sDacload.ucDacType = ATOM_DAC_B;
2231
2232 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
2233 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
2234 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
2235 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
2236 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2237 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
2238 if (crev >= 3)
2239 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
2240 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2241 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
2242 if (crev >= 3)
2243 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
2244 }
2245
2246 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2247
2248 return true;
2249 } else
2250 return false;
2251}
2252
2253static enum drm_connector_status
2254radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2255{
2256 struct drm_device *dev = encoder->dev;
2257 struct radeon_device *rdev = dev->dev_private;
2258 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2259 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2260 uint32_t bios_0_scratch;
2261
2262 if (!atombios_dac_load_detect(encoder, connector)) {
2263 DRM_DEBUG_KMS("detect returned false \n");
2264 return connector_status_unknown;
2265 }
2266
2267 if (rdev->family >= CHIP_R600)
2268 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2269 else
2270 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2271
2272 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2273 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2274 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2275 return connector_status_connected;
2276 }
2277 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2278 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2279 return connector_status_connected;
2280 }
2281 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2282 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2283 return connector_status_connected;
2284 }
2285 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2286 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2287 return connector_status_connected; /* CTV */
2288 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2289 return connector_status_connected; /* STV */
2290 }
2291 return connector_status_disconnected;
2292}
2293
2294static enum drm_connector_status
2295radeon_atom_dig_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2296{
2297 struct drm_device *dev = encoder->dev;
2298 struct radeon_device *rdev = dev->dev_private;
2299 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2300 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2301 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2302 u32 bios_0_scratch;
2303
2304 if (!ASIC_IS_DCE4(rdev))
2305 return connector_status_unknown;
2306
2307 if (!ext_encoder)
2308 return connector_status_unknown;
2309
2310 if ((radeon_connector->devices & ATOM_DEVICE_CRT_SUPPORT) == 0)
2311 return connector_status_unknown;
2312
2313 /* load detect on the dp bridge */
2314 atombios_external_encoder_setup(encoder, ext_encoder,
2315 EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION);
2316
2317 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2318
2319 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2320 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2321 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2322 return connector_status_connected;
2323 }
2324 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2325 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2326 return connector_status_connected;
2327 }
2328 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2329 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2330 return connector_status_connected;
2331 }
2332 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2333 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2334 return connector_status_connected; /* CTV */
2335 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2336 return connector_status_connected; /* STV */
2337 }
2338 return connector_status_disconnected;
2339}
2340
2341void
2342radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder)
2343{
2344 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2345
2346 if (ext_encoder)
2347 /* ddc_setup on the dp bridge */
2348 atombios_external_encoder_setup(encoder, ext_encoder,
2349 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP);
2350
2351}
2352
2353static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
2354{
cfcbd6d3 2355 struct radeon_device *rdev = encoder->dev->dev_private;
3f03ced8
AD		 2356 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2357 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
2358
2359 if ((radeon_encoder->active_device &
2360 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
2361 (radeon_encoder_get_dp_bridge_encoder_id(encoder) !=
2362 ENCODER_OBJECT_ID_NONE)) {
2363 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
cfcbd6d3 2364 if (dig) {
3f03ced8 2365 dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder);
cfcbd6d3
RM		 2366 if (radeon_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) {
2367 if (rdev->family >= CHIP_R600)
2368 dig->afmt = rdev->mode_info.afmt[dig->dig_encoder];
2369 else
2370 /* RS600/690/740 have only 1 afmt block */
2371 dig->afmt = rdev->mode_info.afmt[0];
2372 }
2373 }
3f03ced8
AD		 2374 }
2375
2376 radeon_atom_output_lock(encoder, true);
3f03ced8
AD		 2377
2378 if (connector) {
2379 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2380
2381 /* select the clock/data port if it uses a router */
2382 if (radeon_connector->router.cd_valid)
2383 radeon_router_select_cd_port(radeon_connector);
2384
2385 /* turn eDP panel on for mode set */
2386 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
2387 atombios_set_edp_panel_power(connector,
2388 ATOM_TRANSMITTER_ACTION_POWER_ON);
2389 }
2390
2391 /* this is needed for the pll/ss setup to work correctly in some cases */
2392 atombios_set_encoder_crtc_source(encoder);
134b480f
AD		 2393 /* set up the FMT blocks */
2394 if (ASIC_IS_DCE8(rdev))
2395 dce8_program_fmt(encoder);
2396 else if (ASIC_IS_DCE4(rdev))
2397 dce4_program_fmt(encoder);
2398 else if (ASIC_IS_DCE3(rdev))
2399 dce3_program_fmt(encoder);
2400 else if (ASIC_IS_AVIVO(rdev))
2401 avivo_program_fmt(encoder);
3f03ced8
AD		 2402}
2403
2404static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
2405{
8d1af57a 2406 /* need to call this here as we need the crtc set up */
3f03ced8
AD		 2407 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
2408 radeon_atom_output_lock(encoder, false);
2409}
2410
2411static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
2412{
2413 struct drm_device *dev = encoder->dev;
2414 struct radeon_device *rdev = dev->dev_private;
2415 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2416 struct radeon_encoder_atom_dig *dig;
2417
2418 /* check for pre-DCE3 cards with shared encoders;
2419 * can't really use the links individually, so don't disable
2420 * the encoder if it's in use by another connector
2421 */
2422 if (!ASIC_IS_DCE3(rdev)) {
2423 struct drm_encoder *other_encoder;
2424 struct radeon_encoder *other_radeon_encoder;
2425
2426 list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) {
2427 other_radeon_encoder = to_radeon_encoder(other_encoder);
2428 if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) &&
2429 drm_helper_encoder_in_use(other_encoder))
2430 goto disable_done;
2431 }
2432 }
2433
2434 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2435
2436 switch (radeon_encoder->encoder_id) {
2437 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2438 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2439 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2440 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2441 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE);
2442 break;
2443 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2444 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2445 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
e68adef8 2446 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3f03ced8 2447 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
8d1af57a 2448 /* handled in dpms */
3f03ced8
AD		 2449 break;
2450 case ENCODER_OBJECT_ID_INTERNAL_DDI:
2451 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2452 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2453 atombios_dvo_setup(encoder, ATOM_DISABLE);
2454 break;
2455 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2456 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2457 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2458 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2459 atombios_dac_setup(encoder, ATOM_DISABLE);
2460 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2461 atombios_tv_setup(encoder, ATOM_DISABLE);
2462 break;
2463 }
2464
2465disable_done:
2466 if (radeon_encoder_is_digital(encoder)) {
3f03ced8
AD		 2467 dig = radeon_encoder->enc_priv;
2468 dig->dig_encoder = -1;
2469 }
2470 radeon_encoder->active_device = 0;
2471}
2472
2473/* these are handled by the primary encoders */
2474static void radeon_atom_ext_prepare(struct drm_encoder *encoder)
2475{
2476
2477}
2478
2479static void radeon_atom_ext_commit(struct drm_encoder *encoder)
2480{
2481
2482}
2483
2484static void
2485radeon_atom_ext_mode_set(struct drm_encoder *encoder,
2486 struct drm_display_mode *mode,
2487 struct drm_display_mode *adjusted_mode)
2488{
2489
2490}
2491
2492static void radeon_atom_ext_disable(struct drm_encoder *encoder)
2493{
2494
2495}
2496
2497static void
2498radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode)
2499{
2500
2501}
2502
2503static bool radeon_atom_ext_mode_fixup(struct drm_encoder *encoder,
e811f5ae 2504 const struct drm_display_mode *mode,
3f03ced8
AD		 2505 struct drm_display_mode *adjusted_mode)
2506{
2507 return true;
2508}
2509
2510static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = {
2511 .dpms = radeon_atom_ext_dpms,
2512 .mode_fixup = radeon_atom_ext_mode_fixup,
2513 .prepare = radeon_atom_ext_prepare,
2514 .mode_set = radeon_atom_ext_mode_set,
2515 .commit = radeon_atom_ext_commit,
2516 .disable = radeon_atom_ext_disable,
2517 /* no detect for TMDS/LVDS yet */
2518};
2519
2520static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
2521 .dpms = radeon_atom_encoder_dpms,
2522 .mode_fixup = radeon_atom_mode_fixup,
2523 .prepare = radeon_atom_encoder_prepare,
2524 .mode_set = radeon_atom_encoder_mode_set,
2525 .commit = radeon_atom_encoder_commit,
2526 .disable = radeon_atom_encoder_disable,
2527 .detect = radeon_atom_dig_detect,
2528};
2529
2530static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
2531 .dpms = radeon_atom_encoder_dpms,
2532 .mode_fixup = radeon_atom_mode_fixup,
2533 .prepare = radeon_atom_encoder_prepare,
2534 .mode_set = radeon_atom_encoder_mode_set,
2535 .commit = radeon_atom_encoder_commit,
2536 .detect = radeon_atom_dac_detect,
2537};
2538
2539void radeon_enc_destroy(struct drm_encoder *encoder)
2540{
2541 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
f3728734
AD		 2542 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2543 radeon_atom_backlight_exit(radeon_encoder);
3f03ced8
AD		 2544 kfree(radeon_encoder->enc_priv);
2545 drm_encoder_cleanup(encoder);
2546 kfree(radeon_encoder);
2547}
2548
2549static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
2550 .destroy = radeon_enc_destroy,
2551};
2552
1109ca09 2553static struct radeon_encoder_atom_dac *
3f03ced8
AD		 2554radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
2555{
2556 struct drm_device *dev = radeon_encoder->base.dev;
2557 struct radeon_device *rdev = dev->dev_private;
2558 struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
2559
2560 if (!dac)
2561 return NULL;
2562
2563 dac->tv_std = radeon_atombios_get_tv_info(rdev);
2564 return dac;
2565}
2566
1109ca09 2567static struct radeon_encoder_atom_dig *
3f03ced8
AD		 2568radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
2569{
2570 int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
2571 struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
2572
2573 if (!dig)
2574 return NULL;
2575
2576 /* coherent mode by default */
2577 dig->coherent_mode = true;
2578 dig->dig_encoder = -1;
2579
2580 if (encoder_enum == 2)
2581 dig->linkb = true;
2582 else
2583 dig->linkb = false;
2584
2585 return dig;
2586}
2587
2588void
2589radeon_add_atom_encoder(struct drm_device *dev,
2590 uint32_t encoder_enum,
2591 uint32_t supported_device,
2592 u16 caps)
2593{
2594 struct radeon_device *rdev = dev->dev_private;
2595 struct drm_encoder *encoder;
2596 struct radeon_encoder *radeon_encoder;
2597
2598 /* see if we already added it */
2599 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2600 radeon_encoder = to_radeon_encoder(encoder);
2601 if (radeon_encoder->encoder_enum == encoder_enum) {
2602 radeon_encoder->devices |= supported_device;
2603 return;
2604 }
2605
2606 }
2607
2608 /* add a new one */
2609 radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
2610 if (!radeon_encoder)
2611 return;
2612
2613 encoder = &radeon_encoder->base;
2614 switch (rdev->num_crtc) {
2615 case 1:
2616 encoder->possible_crtcs = 0x1;
2617 break;
2618 case 2:
2619 default:
2620 encoder->possible_crtcs = 0x3;
2621 break;
2622 case 4:
2623 encoder->possible_crtcs = 0xf;
2624 break;
2625 case 6:
2626 encoder->possible_crtcs = 0x3f;
2627 break;
2628 }
2629
2630 radeon_encoder->enc_priv = NULL;
2631
2632 radeon_encoder->encoder_enum = encoder_enum;
2633 radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
2634 radeon_encoder->devices = supported_device;
2635 radeon_encoder->rmx_type = RMX_OFF;
2636 radeon_encoder->underscan_type = UNDERSCAN_OFF;
2637 radeon_encoder->is_ext_encoder = false;
2638 radeon_encoder->caps = caps;
2639
2640 switch (radeon_encoder->encoder_id) {
2641 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2642 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2643 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2644 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2645 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2646 radeon_encoder->rmx_type = RMX_FULL;
2647 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2648 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2649 } else {
2650 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2651 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2652 }
2653 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2654 break;
2655 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2656 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2657 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2658 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2659 break;
2660 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2661 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2662 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2663 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC);
2664 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2665 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2666 break;
2667 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2668 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2669 case ENCODER_OBJECT_ID_INTERNAL_DDI:
2670 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2671 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2672 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2673 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
e68adef8 2674 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3f03ced8
AD		 2675 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2676 radeon_encoder->rmx_type = RMX_FULL;
2677 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2678 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2679 } else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
2680 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2681 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2682 } else {
2683 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2684 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2685 }
2686 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2687 break;
2688 case ENCODER_OBJECT_ID_SI170B:
2689 case ENCODER_OBJECT_ID_CH7303:
2690 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
2691 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
2692 case ENCODER_OBJECT_ID_TITFP513:
2693 case ENCODER_OBJECT_ID_VT1623:
2694 case ENCODER_OBJECT_ID_HDMI_SI1930:
2695 case ENCODER_OBJECT_ID_TRAVIS:
2696 case ENCODER_OBJECT_ID_NUTMEG:
2697 /* these are handled by the primary encoders */
2698 radeon_encoder->is_ext_encoder = true;
2699 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2700 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2701 else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
2702 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2703 else
2704 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2705 drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs);
2706 break;
2707 }
2708}
Linux kernel - Deliverables
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