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drm/radeon/atom: add DCE8 encoder support
[deliverable/linux.git] / drivers / gpu / drm / radeon / atombios_encoders.c
CommitLineData
3f03ced8
AD		 1/*
2 * Copyright 2007-11 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
760285e7
DH		 26#include <drm/drmP.h>
27#include <drm/drm_crtc_helper.h>
28#include <drm/radeon_drm.h>
3f03ced8
AD		 29#include "radeon.h"
30#include "atom.h"
f3728734 31#include <linux/backlight.h>
3f03ced8
AD		 32
33extern int atom_debug;
34
f3728734
AD		 35static u8
36radeon_atom_get_backlight_level_from_reg(struct radeon_device *rdev)
37{
38 u8 backlight_level;
39 u32 bios_2_scratch;
40
41 if (rdev->family >= CHIP_R600)
42 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
43 else
44 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
45
46 backlight_level = ((bios_2_scratch & ATOM_S2_CURRENT_BL_LEVEL_MASK) >>
47 ATOM_S2_CURRENT_BL_LEVEL_SHIFT);
48
49 return backlight_level;
50}
51
52static void
53radeon_atom_set_backlight_level_to_reg(struct radeon_device *rdev,
54 u8 backlight_level)
55{
56 u32 bios_2_scratch;
57
58 if (rdev->family >= CHIP_R600)
59 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
60 else
61 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
62
63 bios_2_scratch &= ~ATOM_S2_CURRENT_BL_LEVEL_MASK;
64 bios_2_scratch |= ((backlight_level << ATOM_S2_CURRENT_BL_LEVEL_SHIFT) &
65 ATOM_S2_CURRENT_BL_LEVEL_MASK);
66
67 if (rdev->family >= CHIP_R600)
68 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
69 else
70 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
71}
72
6d92f81d
AD		 73u8
74atombios_get_backlight_level(struct radeon_encoder *radeon_encoder)
75{
76 struct drm_device *dev = radeon_encoder->base.dev;
77 struct radeon_device *rdev = dev->dev_private;
78
79 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
80 return 0;
81
82 return radeon_atom_get_backlight_level_from_reg(rdev);
83}
84
fda4b25c 85void
37e9b6a6 86atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level)
f3728734
AD		 87{
88 struct drm_encoder *encoder = &radeon_encoder->base;
89 struct drm_device *dev = radeon_encoder->base.dev;
90 struct radeon_device *rdev = dev->dev_private;
91 struct radeon_encoder_atom_dig *dig;
92 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
93 int index;
94
37e9b6a6
AD		 95 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
96 return;
97
98 if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) &&
99 radeon_encoder->enc_priv) {
f3728734 100 dig = radeon_encoder->enc_priv;
37e9b6a6 101 dig->backlight_level = level;
f3728734
AD		 102 radeon_atom_set_backlight_level_to_reg(rdev, dig->backlight_level);
103
104 switch (radeon_encoder->encoder_id) {
105 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
106 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
107 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
108 if (dig->backlight_level == 0) {
109 args.ucAction = ATOM_LCD_BLOFF;
110 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
111 } else {
112 args.ucAction = ATOM_LCD_BL_BRIGHTNESS_CONTROL;
113 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
114 args.ucAction = ATOM_LCD_BLON;
115 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
116 }
117 break;
118 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
119 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
120 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
121 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
122 if (dig->backlight_level == 0)
123 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
124 else {
125 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL, 0, 0);
126 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
127 }
128 break;
129 default:
130 break;
131 }
132 }
133}
134
bced76f2
AD		 135#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
136
f3728734
AD		 137static u8 radeon_atom_bl_level(struct backlight_device *bd)
138{
139 u8 level;
140
141 /* Convert brightness to hardware level */
142 if (bd->props.brightness < 0)
143 level = 0;
144 else if (bd->props.brightness > RADEON_MAX_BL_LEVEL)
145 level = RADEON_MAX_BL_LEVEL;
146 else
147 level = bd->props.brightness;
148
149 return level;
150}
151
152static int radeon_atom_backlight_update_status(struct backlight_device *bd)
153{
154 struct radeon_backlight_privdata *pdata = bl_get_data(bd);
155 struct radeon_encoder *radeon_encoder = pdata->encoder;
156
37e9b6a6 157 atombios_set_backlight_level(radeon_encoder, radeon_atom_bl_level(bd));
f3728734
AD		 158
159 return 0;
160}
161
162static int radeon_atom_backlight_get_brightness(struct backlight_device *bd)
163{
164 struct radeon_backlight_privdata *pdata = bl_get_data(bd);
165 struct radeon_encoder *radeon_encoder = pdata->encoder;
166 struct drm_device *dev = radeon_encoder->base.dev;
167 struct radeon_device *rdev = dev->dev_private;
168
169 return radeon_atom_get_backlight_level_from_reg(rdev);
170}
171
172static const struct backlight_ops radeon_atom_backlight_ops = {
173 .get_brightness = radeon_atom_backlight_get_brightness,
174 .update_status = radeon_atom_backlight_update_status,
175};
176
177void radeon_atom_backlight_init(struct radeon_encoder *radeon_encoder,
178 struct drm_connector *drm_connector)
179{
180 struct drm_device *dev = radeon_encoder->base.dev;
181 struct radeon_device *rdev = dev->dev_private;
182 struct backlight_device *bd;
183 struct backlight_properties props;
184 struct radeon_backlight_privdata *pdata;
185 struct radeon_encoder_atom_dig *dig;
186 u8 backlight_level;
614499b4 187 char bl_name[16];
f3728734 188
80101790
AD		 189 /* Mac laptops with multiple GPUs use the gmux driver for backlight
190 * so don't register a backlight device
191 */
192 if ((rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) &&
193 (rdev->pdev->device == 0x6741))
194 return;
195
f3728734
AD		 196 if (!radeon_encoder->enc_priv)
197 return;
198
199 if (!rdev->is_atom_bios)
200 return;
201
202 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
203 return;
204
205 pdata = kmalloc(sizeof(struct radeon_backlight_privdata), GFP_KERNEL);
206 if (!pdata) {
207 DRM_ERROR("Memory allocation failed\n");
208 goto error;
209 }
210
211 memset(&props, 0, sizeof(props));
212 props.max_brightness = RADEON_MAX_BL_LEVEL;
213 props.type = BACKLIGHT_RAW;
614499b4
AD		 214 snprintf(bl_name, sizeof(bl_name),
215 "radeon_bl%d", dev->primary->index);
216 bd = backlight_device_register(bl_name, &drm_connector->kdev,
f3728734
AD		 217 pdata, &radeon_atom_backlight_ops, &props);
218 if (IS_ERR(bd)) {
219 DRM_ERROR("Backlight registration failed\n");
220 goto error;
221 }
222
223 pdata->encoder = radeon_encoder;
224
225 backlight_level = radeon_atom_get_backlight_level_from_reg(rdev);
226
227 dig = radeon_encoder->enc_priv;
228 dig->bl_dev = bd;
229
230 bd->props.brightness = radeon_atom_backlight_get_brightness(bd);
231 bd->props.power = FB_BLANK_UNBLANK;
232 backlight_update_status(bd);
233
234 DRM_INFO("radeon atom DIG backlight initialized\n");
235
236 return;
237
238error:
239 kfree(pdata);
240 return;
241}
242
243static void radeon_atom_backlight_exit(struct radeon_encoder *radeon_encoder)
244{
245 struct drm_device *dev = radeon_encoder->base.dev;
246 struct radeon_device *rdev = dev->dev_private;
247 struct backlight_device *bd = NULL;
248 struct radeon_encoder_atom_dig *dig;
249
250 if (!radeon_encoder->enc_priv)
251 return;
252
253 if (!rdev->is_atom_bios)
254 return;
255
256 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
257 return;
258
259 dig = radeon_encoder->enc_priv;
260 bd = dig->bl_dev;
261 dig->bl_dev = NULL;
262
263 if (bd) {
264 struct radeon_legacy_backlight_privdata *pdata;
265
266 pdata = bl_get_data(bd);
267 backlight_device_unregister(bd);
268 kfree(pdata);
269
270 DRM_INFO("radeon atom LVDS backlight unloaded\n");
271 }
272}
273
274#else /* !CONFIG_BACKLIGHT_CLASS_DEVICE */
275
276void radeon_atom_backlight_init(struct radeon_encoder *encoder)
277{
278}
279
280static void radeon_atom_backlight_exit(struct radeon_encoder *encoder)
281{
282}
283
284#endif
285
3f03ced8
AD		 286/* evil but including atombios.h is much worse */
287bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
288 struct drm_display_mode *mode);
289
290
291static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder)
292{
293 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
294 switch (radeon_encoder->encoder_id) {
295 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
296 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
297 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
298 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
299 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
300 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
301 case ENCODER_OBJECT_ID_INTERNAL_DDI:
302 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
303 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
304 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
305 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
e68adef8 306 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3f03ced8
AD		 307 return true;
308 default:
309 return false;
310 }
311}
312
3f03ced8 313static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
e811f5ae 314 const struct drm_display_mode *mode,
3f03ced8
AD		 315 struct drm_display_mode *adjusted_mode)
316{
317 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
318 struct drm_device *dev = encoder->dev;
319 struct radeon_device *rdev = dev->dev_private;
320
321 /* set the active encoder to connector routing */
322 radeon_encoder_set_active_device(encoder);
323 drm_mode_set_crtcinfo(adjusted_mode, 0);
324
325 /* hw bug */
326 if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
327 && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
328 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
329
330 /* get the native mode for LVDS */
331 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT))
332 radeon_panel_mode_fixup(encoder, adjusted_mode);
333
334 /* get the native mode for TV */
335 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
336 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
337 if (tv_dac) {
338 if (tv_dac->tv_std == TV_STD_NTSC ||
339 tv_dac->tv_std == TV_STD_NTSC_J ||
340 tv_dac->tv_std == TV_STD_PAL_M)
341 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
342 else
343 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
344 }
345 }
346
347 if (ASIC_IS_DCE3(rdev) &&
348 ((radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
349 (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE))) {
350 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
93927f9c 351 radeon_dp_set_link_config(connector, adjusted_mode);
3f03ced8
AD		 352 }
353
354 return true;
355}
356
357static void
358atombios_dac_setup(struct drm_encoder *encoder, int action)
359{
360 struct drm_device *dev = encoder->dev;
361 struct radeon_device *rdev = dev->dev_private;
362 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
363 DAC_ENCODER_CONTROL_PS_ALLOCATION args;
364 int index = 0;
365 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
366
367 memset(&args, 0, sizeof(args));
368
369 switch (radeon_encoder->encoder_id) {
370 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
371 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
372 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
373 break;
374 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
375 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
376 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
377 break;
378 }
379
380 args.ucAction = action;
381
382 if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
383 args.ucDacStandard = ATOM_DAC1_PS2;
384 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
385 args.ucDacStandard = ATOM_DAC1_CV;
386 else {
387 switch (dac_info->tv_std) {
388 case TV_STD_PAL:
389 case TV_STD_PAL_M:
390 case TV_STD_SCART_PAL:
391 case TV_STD_SECAM:
392 case TV_STD_PAL_CN:
393 args.ucDacStandard = ATOM_DAC1_PAL;
394 break;
395 case TV_STD_NTSC:
396 case TV_STD_NTSC_J:
397 case TV_STD_PAL_60:
398 default:
399 args.ucDacStandard = ATOM_DAC1_NTSC;
400 break;
401 }
402 }
403 args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
404
405 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
406
407}
408
409static void
410atombios_tv_setup(struct drm_encoder *encoder, int action)
411{
412 struct drm_device *dev = encoder->dev;
413 struct radeon_device *rdev = dev->dev_private;
414 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
415 TV_ENCODER_CONTROL_PS_ALLOCATION args;
416 int index = 0;
417 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
418
419 memset(&args, 0, sizeof(args));
420
421 index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
422
423 args.sTVEncoder.ucAction = action;
424
425 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
426 args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
427 else {
428 switch (dac_info->tv_std) {
429 case TV_STD_NTSC:
430 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
431 break;
432 case TV_STD_PAL:
433 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
434 break;
435 case TV_STD_PAL_M:
436 args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
437 break;
438 case TV_STD_PAL_60:
439 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
440 break;
441 case TV_STD_NTSC_J:
442 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
443 break;
444 case TV_STD_SCART_PAL:
445 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
446 break;
447 case TV_STD_SECAM:
448 args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
449 break;
450 case TV_STD_PAL_CN:
451 args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
452 break;
453 default:
454 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
455 break;
456 }
457 }
458
459 args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
460
461 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
462
463}
464
1f0e2943
AD		 465static u8 radeon_atom_get_bpc(struct drm_encoder *encoder)
466{
467 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
468 int bpc = 8;
469
470 if (connector)
471 bpc = radeon_get_monitor_bpc(connector);
472
473 switch (bpc) {
474 case 0:
475 return PANEL_BPC_UNDEFINE;
476 case 6:
477 return PANEL_6BIT_PER_COLOR;
478 case 8:
479 default:
480 return PANEL_8BIT_PER_COLOR;
481 case 10:
482 return PANEL_10BIT_PER_COLOR;
483 case 12:
484 return PANEL_12BIT_PER_COLOR;
485 case 16:
486 return PANEL_16BIT_PER_COLOR;
487 }
488}
489
490
3f03ced8
AD		 491union dvo_encoder_control {
492 ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds;
493 DVO_ENCODER_CONTROL_PS_ALLOCATION dvo;
494 DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3;
495};
496
497void
498atombios_dvo_setup(struct drm_encoder *encoder, int action)
499{
500 struct drm_device *dev = encoder->dev;
501 struct radeon_device *rdev = dev->dev_private;
502 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
503 union dvo_encoder_control args;
504 int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
24153dd3 505 uint8_t frev, crev;
3f03ced8
AD		 506
507 memset(&args, 0, sizeof(args));
508
24153dd3
AD		 509 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
510 return;
511
afceb931
AD		 512 /* some R4xx chips have the wrong frev */
513 if (rdev->family <= CHIP_RV410)
514 frev = 1;
515
24153dd3
AD		 516 switch (frev) {
517 case 1:
518 switch (crev) {
519 case 1:
520 /* R4xx, R5xx */
521 args.ext_tmds.sXTmdsEncoder.ucEnable = action;
522
9aa59993 523 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
24153dd3
AD		 524 args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL;
525
526 args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB;
527 break;
528 case 2:
529 /* RS600/690/740 */
530 args.dvo.sDVOEncoder.ucAction = action;
531 args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
532 /* DFP1, CRT1, TV1 depending on the type of port */
533 args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX;
534
9aa59993 535 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
24153dd3
AD		 536 args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL;
537 break;
538 case 3:
539 /* R6xx */
540 args.dvo_v3.ucAction = action;
541 args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
542 args.dvo_v3.ucDVOConfig = 0; /* XXX */
543 break;
544 default:
545 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
546 break;
547 }
548 break;
549 default:
550 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
551 break;
3f03ced8
AD		 552 }
553
554 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
555}
556
557union lvds_encoder_control {
558 LVDS_ENCODER_CONTROL_PS_ALLOCATION v1;
559 LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
560};
561
562void
563atombios_digital_setup(struct drm_encoder *encoder, int action)
564{
565 struct drm_device *dev = encoder->dev;
566 struct radeon_device *rdev = dev->dev_private;
567 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
568 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
569 union lvds_encoder_control args;
570 int index = 0;
571 int hdmi_detected = 0;
572 uint8_t frev, crev;
573
574 if (!dig)
575 return;
576
577 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
578 hdmi_detected = 1;
579
580 memset(&args, 0, sizeof(args));
581
582 switch (radeon_encoder->encoder_id) {
583 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
584 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
585 break;
586 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
587 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
588 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
589 break;
590 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
591 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
592 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
593 else
594 index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
595 break;
596 }
597
598 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
599 return;
600
601 switch (frev) {
602 case 1:
603 case 2:
604 switch (crev) {
605 case 1:
606 args.v1.ucMisc = 0;
607 args.v1.ucAction = action;
608 if (hdmi_detected)
609 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
610 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
611 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
612 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
613 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
614 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
615 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
616 } else {
617 if (dig->linkb)
618 args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
9aa59993 619 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
3f03ced8
AD		 620 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
621 /*if (pScrn->rgbBits == 8) */
622 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
623 }
624 break;
625 case 2:
626 case 3:
627 args.v2.ucMisc = 0;
628 args.v2.ucAction = action;
629 if (crev == 3) {
630 if (dig->coherent_mode)
631 args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
632 }
633 if (hdmi_detected)
634 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
635 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
636 args.v2.ucTruncate = 0;
637 args.v2.ucSpatial = 0;
638 args.v2.ucTemporal = 0;
639 args.v2.ucFRC = 0;
640 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
641 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
642 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
643 if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) {
644 args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
645 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
646 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
647 }
648 if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) {
649 args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
650 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
651 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
652 if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2)
653 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
654 }
655 } else {
656 if (dig->linkb)
657 args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
9aa59993 658 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
3f03ced8
AD		 659 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
660 }
661 break;
662 default:
663 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
664 break;
665 }
666 break;
667 default:
668 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
669 break;
670 }
671
672 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
673}
674
675int
676atombios_get_encoder_mode(struct drm_encoder *encoder)
677{
1cbcca30
AD		 678 struct drm_device *dev = encoder->dev;
679 struct radeon_device *rdev = dev->dev_private;
3f03ced8 680 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3f03ced8
AD		 681 struct drm_connector *connector;
682 struct radeon_connector *radeon_connector;
683 struct radeon_connector_atom_dig *dig_connector;
684
685 /* dp bridges are always DP */
686 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)
687 return ATOM_ENCODER_MODE_DP;
688
689 /* DVO is always DVO */
a59fbb8e
AD		 690 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DVO1) ||
691 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1))
3f03ced8
AD		 692 return ATOM_ENCODER_MODE_DVO;
693
694 connector = radeon_get_connector_for_encoder(encoder);
695 /* if we don't have an active device yet, just use one of
696 * the connectors tied to the encoder.
697 */
698 if (!connector)
699 connector = radeon_get_connector_for_encoder_init(encoder);
700 radeon_connector = to_radeon_connector(connector);
701
702 switch (connector->connector_type) {
703 case DRM_MODE_CONNECTOR_DVII:
704 case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
27d9cc84 705 if (drm_detect_hdmi_monitor(radeon_connector->edid) &&
1cbcca30
AD		 706 radeon_audio &&
707 !ASIC_IS_DCE6(rdev)) /* remove once we support DCE6 */
f92e70ca
RM		 708 return ATOM_ENCODER_MODE_HDMI;
709 else if (radeon_connector->use_digital)
3f03ced8
AD		 710 return ATOM_ENCODER_MODE_DVI;
711 else
712 return ATOM_ENCODER_MODE_CRT;
713 break;
714 case DRM_MODE_CONNECTOR_DVID:
715 case DRM_MODE_CONNECTOR_HDMIA:
716 default:
27d9cc84 717 if (drm_detect_hdmi_monitor(radeon_connector->edid) &&
1cbcca30
AD		 718 radeon_audio &&
719 !ASIC_IS_DCE6(rdev)) /* remove once we support DCE6 */
f92e70ca
RM		 720 return ATOM_ENCODER_MODE_HDMI;
721 else
3f03ced8
AD		 722 return ATOM_ENCODER_MODE_DVI;
723 break;
724 case DRM_MODE_CONNECTOR_LVDS:
725 return ATOM_ENCODER_MODE_LVDS;
726 break;
727 case DRM_MODE_CONNECTOR_DisplayPort:
728 dig_connector = radeon_connector->con_priv;
729 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
730 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP))
731 return ATOM_ENCODER_MODE_DP;
27d9cc84 732 else if (drm_detect_hdmi_monitor(radeon_connector->edid) &&
1cbcca30
AD		 733 radeon_audio &&
734 !ASIC_IS_DCE6(rdev)) /* remove once we support DCE6 */
f92e70ca
RM		 735 return ATOM_ENCODER_MODE_HDMI;
736 else
3f03ced8
AD		 737 return ATOM_ENCODER_MODE_DVI;
738 break;
739 case DRM_MODE_CONNECTOR_eDP:
740 return ATOM_ENCODER_MODE_DP;
741 case DRM_MODE_CONNECTOR_DVIA:
742 case DRM_MODE_CONNECTOR_VGA:
743 return ATOM_ENCODER_MODE_CRT;
744 break;
745 case DRM_MODE_CONNECTOR_Composite:
746 case DRM_MODE_CONNECTOR_SVIDEO:
747 case DRM_MODE_CONNECTOR_9PinDIN:
748 /* fix me */
749 return ATOM_ENCODER_MODE_TV;
750 /*return ATOM_ENCODER_MODE_CV;*/
751 break;
752 }
753}
754
755/*
756 * DIG Encoder/Transmitter Setup
757 *
758 * DCE 3.0/3.1
759 * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
760 * Supports up to 3 digital outputs
761 * - 2 DIG encoder blocks.
762 * DIG1 can drive UNIPHY link A or link B
763 * DIG2 can drive UNIPHY link B or LVTMA
764 *
765 * DCE 3.2
766 * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
767 * Supports up to 5 digital outputs
768 * - 2 DIG encoder blocks.
769 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
770 *
2d415869 771 * DCE 4.0/5.0/6.0
3f03ced8
AD		 772 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
773 * Supports up to 6 digital outputs
774 * - 6 DIG encoder blocks.
775 * - DIG to PHY mapping is hardcoded
776 * DIG1 drives UNIPHY0 link A, A+B
777 * DIG2 drives UNIPHY0 link B
778 * DIG3 drives UNIPHY1 link A, A+B
779 * DIG4 drives UNIPHY1 link B
780 * DIG5 drives UNIPHY2 link A, A+B
781 * DIG6 drives UNIPHY2 link B
782 *
783 * DCE 4.1
784 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
785 * Supports up to 6 digital outputs
786 * - 2 DIG encoder blocks.
2d415869 787 * llano
3f03ced8 788 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
2d415869
AD		 789 * ontario
790 * DIG1 drives UNIPHY0/1/2 link A
791 * DIG2 drives UNIPHY0/1/2 link B
3f03ced8
AD		 792 *
793 * Routing
794 * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
795 * Examples:
796 * crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI
797 * crtc1 -> dig1 -> UNIPHY0 link B -> DP
798 * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS
799 * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI
800 */
801
802union dig_encoder_control {
803 DIG_ENCODER_CONTROL_PS_ALLOCATION v1;
804 DIG_ENCODER_CONTROL_PARAMETERS_V2 v2;
805 DIG_ENCODER_CONTROL_PARAMETERS_V3 v3;
806 DIG_ENCODER_CONTROL_PARAMETERS_V4 v4;
807};
808
809void
810atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode)
811{
812 struct drm_device *dev = encoder->dev;
813 struct radeon_device *rdev = dev->dev_private;
814 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
815 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
816 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
817 union dig_encoder_control args;
818 int index = 0;
819 uint8_t frev, crev;
820 int dp_clock = 0;
821 int dp_lane_count = 0;
822 int hpd_id = RADEON_HPD_NONE;
3f03ced8
AD		 823
824 if (connector) {
825 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
826 struct radeon_connector_atom_dig *dig_connector =
827 radeon_connector->con_priv;
828
829 dp_clock = dig_connector->dp_clock;
830 dp_lane_count = dig_connector->dp_lane_count;
831 hpd_id = radeon_connector->hpd.hpd;
3f03ced8
AD		 832 }
833
834 /* no dig encoder assigned */
835 if (dig->dig_encoder == -1)
836 return;
837
838 memset(&args, 0, sizeof(args));
839
840 if (ASIC_IS_DCE4(rdev))
841 index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl);
842 else {
843 if (dig->dig_encoder)
844 index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
845 else
846 index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
847 }
848
849 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
850 return;
851
58cdcb8b
AD		 852 switch (frev) {
853 case 1:
854 switch (crev) {
855 case 1:
856 args.v1.ucAction = action;
857 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
858 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
859 args.v3.ucPanelMode = panel_mode;
860 else
861 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
862
863 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))
864 args.v1.ucLaneNum = dp_lane_count;
9aa59993 865 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
58cdcb8b
AD		 866 args.v1.ucLaneNum = 8;
867 else
868 args.v1.ucLaneNum = 4;
869
870 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000))
871 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
872 switch (radeon_encoder->encoder_id) {
873 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
874 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
875 break;
876 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
877 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
878 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
879 break;
880 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
881 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
882 break;
883 }
884 if (dig->linkb)
885 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
886 else
887 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
3f03ced8 888 break;
58cdcb8b
AD		 889 case 2:
890 case 3:
891 args.v3.ucAction = action;
892 args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
893 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
894 args.v3.ucPanelMode = panel_mode;
895 else
896 args.v3.ucEncoderMode = atombios_get_encoder_mode(encoder);
897
2f6fa79a 898 if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode))
58cdcb8b 899 args.v3.ucLaneNum = dp_lane_count;
9aa59993 900 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
58cdcb8b
AD		 901 args.v3.ucLaneNum = 8;
902 else
903 args.v3.ucLaneNum = 4;
904
2f6fa79a 905 if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode) && (dp_clock == 270000))
58cdcb8b
AD		 906 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
907 args.v3.acConfig.ucDigSel = dig->dig_encoder;
1f0e2943 908 args.v3.ucBitPerColor = radeon_atom_get_bpc(encoder);
3f03ced8 909 break;
58cdcb8b
AD		 910 case 4:
911 args.v4.ucAction = action;
912 args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
913 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
914 args.v4.ucPanelMode = panel_mode;
915 else
916 args.v4.ucEncoderMode = atombios_get_encoder_mode(encoder);
917
2f6fa79a 918 if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode))
58cdcb8b 919 args.v4.ucLaneNum = dp_lane_count;
9aa59993 920 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
58cdcb8b
AD		 921 args.v4.ucLaneNum = 8;
922 else
923 args.v4.ucLaneNum = 4;
924
2f6fa79a 925 if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode)) {
e68adef8 926 if (dp_clock == 540000)
58cdcb8b 927 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ;
e68adef8
AD		 928 else if (dp_clock == 324000)
929 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_3_24GHZ;
930 else if (dp_clock == 270000)
931 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ;
932 else
933 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ;
58cdcb8b
AD		 934 }
935 args.v4.acConfig.ucDigSel = dig->dig_encoder;
1f0e2943 936 args.v4.ucBitPerColor = radeon_atom_get_bpc(encoder);
58cdcb8b
AD		 937 if (hpd_id == RADEON_HPD_NONE)
938 args.v4.ucHPD_ID = 0;
939 else
940 args.v4.ucHPD_ID = hpd_id + 1;
3f03ced8 941 break;
3f03ced8 942 default:
58cdcb8b 943 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3f03ced8
AD		 944 break;
945 }
58cdcb8b
AD		 946 break;
947 default:
948 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
949 break;
3f03ced8
AD		 950 }
951
952 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
953
954}
955
956union dig_transmitter_control {
957 DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
958 DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
959 DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
960 DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4;
47aef7a8 961 DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 v5;
3f03ced8
AD		 962};
963
964void
965atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set)
966{
967 struct drm_device *dev = encoder->dev;
968 struct radeon_device *rdev = dev->dev_private;
969 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
970 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
971 struct drm_connector *connector;
972 union dig_transmitter_control args;
973 int index = 0;
974 uint8_t frev, crev;
975 bool is_dp = false;
976 int pll_id = 0;
977 int dp_clock = 0;
978 int dp_lane_count = 0;
979 int connector_object_id = 0;
980 int igp_lane_info = 0;
981 int dig_encoder = dig->dig_encoder;
47aef7a8 982 int hpd_id = RADEON_HPD_NONE;
3f03ced8
AD		 983
984 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
985 connector = radeon_get_connector_for_encoder_init(encoder);
986 /* just needed to avoid bailing in the encoder check. the encoder
987 * isn't used for init
988 */
989 dig_encoder = 0;
990 } else
991 connector = radeon_get_connector_for_encoder(encoder);
992
993 if (connector) {
994 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
995 struct radeon_connector_atom_dig *dig_connector =
996 radeon_connector->con_priv;
997
47aef7a8 998 hpd_id = radeon_connector->hpd.hpd;
3f03ced8
AD		 999 dp_clock = dig_connector->dp_clock;
1000 dp_lane_count = dig_connector->dp_lane_count;
1001 connector_object_id =
1002 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1003 igp_lane_info = dig_connector->igp_lane_info;
1004 }
1005
a3b08294
AD		 1006 if (encoder->crtc) {
1007 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1008 pll_id = radeon_crtc->pll_id;
1009 }
1010
3f03ced8
AD		 1011 /* no dig encoder assigned */
1012 if (dig_encoder == -1)
1013 return;
1014
1015 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)))
1016 is_dp = true;
1017
1018 memset(&args, 0, sizeof(args));
1019
1020 switch (radeon_encoder->encoder_id) {
1021 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1022 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1023 break;
1024 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1025 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1026 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
e68adef8 1027 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3f03ced8
AD		 1028 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1029 break;
1030 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1031 index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl);
1032 break;
1033 }
1034
1035 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1036 return;
1037
a3b08294
AD		 1038 switch (frev) {
1039 case 1:
1040 switch (crev) {
1041 case 1:
1042 args.v1.ucAction = action;
1043 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1044 args.v1.usInitInfo = cpu_to_le16(connector_object_id);
1045 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1046 args.v1.asMode.ucLaneSel = lane_num;
1047 args.v1.asMode.ucLaneSet = lane_set;
1048 } else {
1049 if (is_dp)
6e76a2df 1050 args.v1.usPixelClock = cpu_to_le16(dp_clock / 10);
9aa59993 1051 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
a3b08294
AD		 1052 args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1053 else
1054 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1055 }
3f03ced8 1056
a3b08294 1057 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
3f03ced8 1058
a3b08294
AD		 1059 if (dig_encoder)
1060 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
1061 else
1062 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
1063
1064 if ((rdev->flags & RADEON_IS_IGP) &&
1065 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) {
9aa59993
AD		 1066 if (is_dp ||
1067 !radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) {
a3b08294
AD		 1068 if (igp_lane_info & 0x1)
1069 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
1070 else if (igp_lane_info & 0x2)
1071 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
1072 else if (igp_lane_info & 0x4)
1073 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
1074 else if (igp_lane_info & 0x8)
1075 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
1076 } else {
1077 if (igp_lane_info & 0x3)
1078 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
1079 else if (igp_lane_info & 0xc)
1080 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
1081 }
1082 }
1083
1084 if (dig->linkb)
1085 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
1086 else
1087 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
1088
1089 if (is_dp)
1090 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1091 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1092 if (dig->coherent_mode)
1093 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
9aa59993 1094 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
a3b08294
AD		 1095 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
1096 }
1097 break;
1098 case 2:
1099 args.v2.ucAction = action;
1100 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1101 args.v2.usInitInfo = cpu_to_le16(connector_object_id);
1102 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1103 args.v2.asMode.ucLaneSel = lane_num;
1104 args.v2.asMode.ucLaneSet = lane_set;
1105 } else {
1106 if (is_dp)
6e76a2df 1107 args.v2.usPixelClock = cpu_to_le16(dp_clock / 10);
9aa59993 1108 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
a3b08294
AD		 1109 args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1110 else
1111 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1112 }
1113
1114 args.v2.acConfig.ucEncoderSel = dig_encoder;
1115 if (dig->linkb)
1116 args.v2.acConfig.ucLinkSel = 1;
1117
1118 switch (radeon_encoder->encoder_id) {
1119 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1120 args.v2.acConfig.ucTransmitterSel = 0;
1121 break;
1122 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1123 args.v2.acConfig.ucTransmitterSel = 1;
1124 break;
1125 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1126 args.v2.acConfig.ucTransmitterSel = 2;
1127 break;
1128 }
3f03ced8 1129
3f03ced8 1130 if (is_dp) {
a3b08294
AD		 1131 args.v2.acConfig.fCoherentMode = 1;
1132 args.v2.acConfig.fDPConnector = 1;
1133 } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1134 if (dig->coherent_mode)
1135 args.v2.acConfig.fCoherentMode = 1;
9aa59993 1136 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
a3b08294
AD		 1137 args.v2.acConfig.fDualLinkConnector = 1;
1138 }
1139 break;
1140 case 3:
1141 args.v3.ucAction = action;
1142 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1143 args.v3.usInitInfo = cpu_to_le16(connector_object_id);
1144 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1145 args.v3.asMode.ucLaneSel = lane_num;
1146 args.v3.asMode.ucLaneSet = lane_set;
1147 } else {
1148 if (is_dp)
6e76a2df 1149 args.v3.usPixelClock = cpu_to_le16(dp_clock / 10);
9aa59993 1150 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
a3b08294 1151 args.v3.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
3f03ced8 1152 else
a3b08294
AD		 1153 args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1154 }
1155
1156 if (is_dp)
1157 args.v3.ucLaneNum = dp_lane_count;
9aa59993 1158 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
a3b08294
AD		 1159 args.v3.ucLaneNum = 8;
1160 else
1161 args.v3.ucLaneNum = 4;
1162
1163 if (dig->linkb)
1164 args.v3.acConfig.ucLinkSel = 1;
1165 if (dig_encoder & 1)
1166 args.v3.acConfig.ucEncoderSel = 1;
1167
1168 /* Select the PLL for the PHY
1169 * DP PHY should be clocked from external src if there is
1170 * one.
1171 */
3f03ced8
AD		 1172 /* On DCE4, if there is an external clock, it generates the DP ref clock */
1173 if (is_dp && rdev->clock.dp_extclk)
1174 args.v3.acConfig.ucRefClkSource = 2; /* external src */
1175 else
1176 args.v3.acConfig.ucRefClkSource = pll_id;
3f03ced8 1177
a3b08294
AD		 1178 switch (radeon_encoder->encoder_id) {
1179 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1180 args.v3.acConfig.ucTransmitterSel = 0;
1181 break;
1182 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1183 args.v3.acConfig.ucTransmitterSel = 1;
1184 break;
1185 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1186 args.v3.acConfig.ucTransmitterSel = 2;
1187 break;
1188 }
3f03ced8 1189
a3b08294
AD		 1190 if (is_dp)
1191 args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
1192 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1193 if (dig->coherent_mode)
1194 args.v3.acConfig.fCoherentMode = 1;
9aa59993 1195 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
a3b08294
AD		 1196 args.v3.acConfig.fDualLinkConnector = 1;
1197 }
3f03ced8 1198 break;
a3b08294
AD		 1199 case 4:
1200 args.v4.ucAction = action;
1201 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1202 args.v4.usInitInfo = cpu_to_le16(connector_object_id);
1203 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1204 args.v4.asMode.ucLaneSel = lane_num;
1205 args.v4.asMode.ucLaneSet = lane_set;
3f03ced8 1206 } else {
a3b08294 1207 if (is_dp)
6e76a2df 1208 args.v4.usPixelClock = cpu_to_le16(dp_clock / 10);
9aa59993 1209 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
a3b08294
AD		 1210 args.v4.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1211 else
1212 args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
3f03ced8 1213 }
3f03ced8 1214
a3b08294
AD		 1215 if (is_dp)
1216 args.v4.ucLaneNum = dp_lane_count;
9aa59993 1217 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
a3b08294
AD		 1218 args.v4.ucLaneNum = 8;
1219 else
1220 args.v4.ucLaneNum = 4;
3f03ced8 1221
a3b08294
AD		 1222 if (dig->linkb)
1223 args.v4.acConfig.ucLinkSel = 1;
1224 if (dig_encoder & 1)
1225 args.v4.acConfig.ucEncoderSel = 1;
1226
1227 /* Select the PLL for the PHY
1228 * DP PHY should be clocked from external src if there is
1229 * one.
1230 */
1231 /* On DCE5 DCPLL usually generates the DP ref clock */
1232 if (is_dp) {
1233 if (rdev->clock.dp_extclk)
1234 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK;
1235 else
1236 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL;
1237 } else
1238 args.v4.acConfig.ucRefClkSource = pll_id;
1239
1240 switch (radeon_encoder->encoder_id) {
1241 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1242 args.v4.acConfig.ucTransmitterSel = 0;
1243 break;
1244 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1245 args.v4.acConfig.ucTransmitterSel = 1;
1246 break;
1247 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1248 args.v4.acConfig.ucTransmitterSel = 2;
1249 break;
1250 }
1251
1252 if (is_dp)
1253 args.v4.acConfig.fCoherentMode = 1; /* DP requires coherent */
1254 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1255 if (dig->coherent_mode)
1256 args.v4.acConfig.fCoherentMode = 1;
9aa59993 1257 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
a3b08294
AD		 1258 args.v4.acConfig.fDualLinkConnector = 1;
1259 }
1260 break;
47aef7a8
AD		 1261 case 5:
1262 args.v5.ucAction = action;
1263 if (is_dp)
1264 args.v5.usSymClock = cpu_to_le16(dp_clock / 10);
1265 else
1266 args.v5.usSymClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1267
1268 switch (radeon_encoder->encoder_id) {
1269 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1270 if (dig->linkb)
1271 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYB;
1272 else
1273 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYA;
1274 break;
1275 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1276 if (dig->linkb)
1277 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYD;
1278 else
1279 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYC;
1280 break;
1281 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1282 if (dig->linkb)
1283 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYF;
1284 else
1285 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYE;
1286 break;
e68adef8
AD		 1287 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1288 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYG;
1289 break;
47aef7a8
AD		 1290 }
1291 if (is_dp)
1292 args.v5.ucLaneNum = dp_lane_count;
1293 else if (radeon_encoder->pixel_clock > 165000)
1294 args.v5.ucLaneNum = 8;
1295 else
1296 args.v5.ucLaneNum = 4;
1297 args.v5.ucConnObjId = connector_object_id;
1298 args.v5.ucDigMode = atombios_get_encoder_mode(encoder);
1299
1300 if (is_dp && rdev->clock.dp_extclk)
1301 args.v5.asConfig.ucPhyClkSrcId = ENCODER_REFCLK_SRC_EXTCLK;
1302 else
1303 args.v5.asConfig.ucPhyClkSrcId = pll_id;
1304
1305 if (is_dp)
1306 args.v5.asConfig.ucCoherentMode = 1; /* DP requires coherent */
1307 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1308 if (dig->coherent_mode)
1309 args.v5.asConfig.ucCoherentMode = 1;
1310 }
1311 if (hpd_id == RADEON_HPD_NONE)
1312 args.v5.asConfig.ucHPDSel = 0;
1313 else
1314 args.v5.asConfig.ucHPDSel = hpd_id + 1;
1315 args.v5.ucDigEncoderSel = 1 << dig_encoder;
1316 args.v5.ucDPLaneSet = lane_set;
1317 break;
a3b08294
AD		 1318 default:
1319 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1320 break;
3f03ced8 1321 }
a3b08294
AD		 1322 break;
1323 default:
1324 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1325 break;
3f03ced8
AD		 1326 }
1327
1328 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1329}
1330
1331bool
1332atombios_set_edp_panel_power(struct drm_connector *connector, int action)
1333{
1334 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1335 struct drm_device *dev = radeon_connector->base.dev;
1336 struct radeon_device *rdev = dev->dev_private;
1337 union dig_transmitter_control args;
1338 int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1339 uint8_t frev, crev;
1340
1341 if (connector->connector_type != DRM_MODE_CONNECTOR_eDP)
1342 goto done;
1343
1344 if (!ASIC_IS_DCE4(rdev))
1345 goto done;
1346
1347 if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) &&
1348 (action != ATOM_TRANSMITTER_ACTION_POWER_OFF))
1349 goto done;
1350
1351 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1352 goto done;
1353
1354 memset(&args, 0, sizeof(args));
1355
1356 args.v1.ucAction = action;
1357
1358 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1359
1360 /* wait for the panel to power up */
1361 if (action == ATOM_TRANSMITTER_ACTION_POWER_ON) {
1362 int i;
1363
1364 for (i = 0; i < 300; i++) {
1365 if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd))
1366 return true;
1367 mdelay(1);
1368 }
1369 return false;
1370 }
1371done:
1372 return true;
1373}
1374
1375union external_encoder_control {
1376 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1;
1377 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3;
1378};
1379
1380static void
1381atombios_external_encoder_setup(struct drm_encoder *encoder,
1382 struct drm_encoder *ext_encoder,
1383 int action)
1384{
1385 struct drm_device *dev = encoder->dev;
1386 struct radeon_device *rdev = dev->dev_private;
1387 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1388 struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder);
1389 union external_encoder_control args;
1390 struct drm_connector *connector;
1391 int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl);
1392 u8 frev, crev;
1393 int dp_clock = 0;
1394 int dp_lane_count = 0;
1395 int connector_object_id = 0;
1396 u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
3f03ced8
AD		 1397
1398 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1399 connector = radeon_get_connector_for_encoder_init(encoder);
1400 else
1401 connector = radeon_get_connector_for_encoder(encoder);
1402
1403 if (connector) {
1404 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1405 struct radeon_connector_atom_dig *dig_connector =
1406 radeon_connector->con_priv;
1407
1408 dp_clock = dig_connector->dp_clock;
1409 dp_lane_count = dig_connector->dp_lane_count;
1410 connector_object_id =
1411 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
3f03ced8
AD		 1412 }
1413
1414 memset(&args, 0, sizeof(args));
1415
1416 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1417 return;
1418
1419 switch (frev) {
1420 case 1:
1421 /* no params on frev 1 */
1422 break;
1423 case 2:
1424 switch (crev) {
1425 case 1:
1426 case 2:
1427 args.v1.sDigEncoder.ucAction = action;
1428 args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1429 args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1430
1431 if (ENCODER_MODE_IS_DP(args.v1.sDigEncoder.ucEncoderMode)) {
1432 if (dp_clock == 270000)
1433 args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
1434 args.v1.sDigEncoder.ucLaneNum = dp_lane_count;
9aa59993 1435 } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
3f03ced8
AD		 1436 args.v1.sDigEncoder.ucLaneNum = 8;
1437 else
1438 args.v1.sDigEncoder.ucLaneNum = 4;
1439 break;
1440 case 3:
1441 args.v3.sExtEncoder.ucAction = action;
1442 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1443 args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id);
1444 else
1445 args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1446 args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1447
1448 if (ENCODER_MODE_IS_DP(args.v3.sExtEncoder.ucEncoderMode)) {
1449 if (dp_clock == 270000)
1450 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
1451 else if (dp_clock == 540000)
1452 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ;
1453 args.v3.sExtEncoder.ucLaneNum = dp_lane_count;
9aa59993 1454 } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
3f03ced8
AD		 1455 args.v3.sExtEncoder.ucLaneNum = 8;
1456 else
1457 args.v3.sExtEncoder.ucLaneNum = 4;
1458 switch (ext_enum) {
1459 case GRAPH_OBJECT_ENUM_ID1:
1460 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1;
1461 break;
1462 case GRAPH_OBJECT_ENUM_ID2:
1463 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2;
1464 break;
1465 case GRAPH_OBJECT_ENUM_ID3:
1466 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3;
1467 break;
1468 }
1f0e2943 1469 args.v3.sExtEncoder.ucBitPerColor = radeon_atom_get_bpc(encoder);
3f03ced8
AD		 1470 break;
1471 default:
1472 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1473 return;
1474 }
1475 break;
1476 default:
1477 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1478 return;
1479 }
1480 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1481}
1482
1483static void
1484atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
1485{
1486 struct drm_device *dev = encoder->dev;
1487 struct radeon_device *rdev = dev->dev_private;
1488 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1489 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1490 ENABLE_YUV_PS_ALLOCATION args;
1491 int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
1492 uint32_t temp, reg;
1493
1494 memset(&args, 0, sizeof(args));
1495
1496 if (rdev->family >= CHIP_R600)
1497 reg = R600_BIOS_3_SCRATCH;
1498 else
1499 reg = RADEON_BIOS_3_SCRATCH;
1500
1501 /* XXX: fix up scratch reg handling */
1502 temp = RREG32(reg);
1503 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1504 WREG32(reg, (ATOM_S3_TV1_ACTIVE |
1505 (radeon_crtc->crtc_id << 18)));
1506 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1507 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
1508 else
1509 WREG32(reg, 0);
1510
1511 if (enable)
1512 args.ucEnable = ATOM_ENABLE;
1513 args.ucCRTC = radeon_crtc->crtc_id;
1514
1515 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1516
1517 WREG32(reg, temp);
1518}
1519
1520static void
1521radeon_atom_encoder_dpms_avivo(struct drm_encoder *encoder, int mode)
1522{
1523 struct drm_device *dev = encoder->dev;
1524 struct radeon_device *rdev = dev->dev_private;
1525 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1526 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
1527 int index = 0;
1528
1529 memset(&args, 0, sizeof(args));
1530
1531 switch (radeon_encoder->encoder_id) {
1532 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1533 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1534 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
1535 break;
1536 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1537 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1538 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1539 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1540 break;
1541 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1542 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1543 break;
1544 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1545 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1546 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1547 else
1548 index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
1549 break;
1550 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1551 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1552 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1553 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1554 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1555 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1556 else
1557 index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
1558 break;
1559 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1560 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1561 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1562 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1563 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1564 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1565 else
1566 index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
1567 break;
1568 default:
1569 return;
1570 }
1571
1572 switch (mode) {
1573 case DRM_MODE_DPMS_ON:
1574 args.ucAction = ATOM_ENABLE;
1575 /* workaround for DVOOutputControl on some RS690 systems */
1576 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DDI) {
1577 u32 reg = RREG32(RADEON_BIOS_3_SCRATCH);
1578 WREG32(RADEON_BIOS_3_SCRATCH, reg & ~ATOM_S3_DFP2I_ACTIVE);
1579 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1580 WREG32(RADEON_BIOS_3_SCRATCH, reg);
1581 } else
1582 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1583 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1584 args.ucAction = ATOM_LCD_BLON;
1585 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1586 }
1587 break;
1588 case DRM_MODE_DPMS_STANDBY:
1589 case DRM_MODE_DPMS_SUSPEND:
1590 case DRM_MODE_DPMS_OFF:
1591 args.ucAction = ATOM_DISABLE;
1592 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1593 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1594 args.ucAction = ATOM_LCD_BLOFF;
1595 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1596 }
1597 break;
1598 }
1599}
1600
1601static void
1602radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode)
1603{
1604 struct drm_device *dev = encoder->dev;
1605 struct radeon_device *rdev = dev->dev_private;
1606 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
8d1af57a
AD		 1607 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1608 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
3f03ced8
AD		 1609 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1610 struct radeon_connector *radeon_connector = NULL;
1611 struct radeon_connector_atom_dig *radeon_dig_connector = NULL;
1612
1613 if (connector) {
1614 radeon_connector = to_radeon_connector(connector);
1615 radeon_dig_connector = radeon_connector->con_priv;
1616 }
1617
1618 switch (mode) {
1619 case DRM_MODE_DPMS_ON:
8d1af57a
AD		 1620 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {
1621 if (!connector)
1622 dig->panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
1623 else
1624 dig->panel_mode = radeon_dp_get_panel_mode(encoder, connector);
1625
1626 /* setup and enable the encoder */
1627 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1628 atombios_dig_encoder_setup(encoder,
1629 ATOM_ENCODER_CMD_SETUP_PANEL_MODE,
1630 dig->panel_mode);
1631 if (ext_encoder) {
1632 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev))
1633 atombios_external_encoder_setup(encoder, ext_encoder,
1634 EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP);
fcedac67 1635 }
3f03ced8 1636 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
8d1af57a
AD		 1637 } else if (ASIC_IS_DCE4(rdev)) {
1638 /* setup and enable the encoder */
1639 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1640 /* enable the transmitter */
1641 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
3f03ced8 1642 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
8d1af57a
AD		 1643 } else {
1644 /* setup and enable the encoder and transmitter */
1645 atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0);
1646 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
1647 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1648 /* some early dce3.2 boards have a bug in their transmitter control table */
b9196395 1649 if ((rdev->family != CHIP_RV710) && (rdev->family != CHIP_RV730))
8d1af57a 1650 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
fcedac67 1651 }
3f03ced8
AD		 1652 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1653 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1654 atombios_set_edp_panel_power(connector,
1655 ATOM_TRANSMITTER_ACTION_POWER_ON);
1656 radeon_dig_connector->edp_on = true;
1657 }
3f03ced8
AD		 1658 radeon_dp_link_train(encoder, connector);
1659 if (ASIC_IS_DCE4(rdev))
1660 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0);
1661 }
1662 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1663 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
1664 break;
1665 case DRM_MODE_DPMS_STANDBY:
1666 case DRM_MODE_DPMS_SUSPEND:
1667 case DRM_MODE_DPMS_OFF:
8d1af57a
AD		 1668 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {
1669 /* disable the transmitter */
3a47824d 1670 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
8d1af57a
AD		 1671 } else if (ASIC_IS_DCE4(rdev)) {
1672 /* disable the transmitter */
1673 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
1674 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1675 } else {
1676 /* disable the encoder and transmitter */
3a47824d 1677 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
8d1af57a
AD		 1678 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1679 atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);
1680 }
3f03ced8
AD		 1681 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1682 if (ASIC_IS_DCE4(rdev))
1683 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0);
1684 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1685 atombios_set_edp_panel_power(connector,
1686 ATOM_TRANSMITTER_ACTION_POWER_OFF);
1687 radeon_dig_connector->edp_on = false;
1688 }
1689 }
1690 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1691 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
1692 break;
1693 }
1694}
1695
1696static void
1697radeon_atom_encoder_dpms_ext(struct drm_encoder *encoder,
1698 struct drm_encoder *ext_encoder,
1699 int mode)
1700{
1701 struct drm_device *dev = encoder->dev;
1702 struct radeon_device *rdev = dev->dev_private;
1703
1704 switch (mode) {
1705 case DRM_MODE_DPMS_ON:
1706 default:
1d3949c4 1707 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) {
3f03ced8
AD		 1708 atombios_external_encoder_setup(encoder, ext_encoder,
1709 EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT);
1710 atombios_external_encoder_setup(encoder, ext_encoder,
1711 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF);
1712 } else
1713 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);
1714 break;
1715 case DRM_MODE_DPMS_STANDBY:
1716 case DRM_MODE_DPMS_SUSPEND:
1717 case DRM_MODE_DPMS_OFF:
1d3949c4 1718 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) {
3f03ced8
AD		 1719 atombios_external_encoder_setup(encoder, ext_encoder,
1720 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING);
1721 atombios_external_encoder_setup(encoder, ext_encoder,
1722 EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT);
1723 } else
1724 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_DISABLE);
1725 break;
1726 }
1727}
1728
1729static void
1730radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1731{
1732 struct drm_device *dev = encoder->dev;
1733 struct radeon_device *rdev = dev->dev_private;
1734 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1735 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1736
1737 DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
1738 radeon_encoder->encoder_id, mode, radeon_encoder->devices,
1739 radeon_encoder->active_device);
1740 switch (radeon_encoder->encoder_id) {
1741 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1742 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1743 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1744 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1745 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1746 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1747 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1748 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1749 radeon_atom_encoder_dpms_avivo(encoder, mode);
1750 break;
1751 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1752 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1753 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
e68adef8 1754 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3f03ced8
AD		 1755 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1756 radeon_atom_encoder_dpms_dig(encoder, mode);
1757 break;
1758 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1759 if (ASIC_IS_DCE5(rdev)) {
1760 switch (mode) {
1761 case DRM_MODE_DPMS_ON:
1762 atombios_dvo_setup(encoder, ATOM_ENABLE);
1763 break;
1764 case DRM_MODE_DPMS_STANDBY:
1765 case DRM_MODE_DPMS_SUSPEND:
1766 case DRM_MODE_DPMS_OFF:
1767 atombios_dvo_setup(encoder, ATOM_DISABLE);
1768 break;
1769 }
1770 } else if (ASIC_IS_DCE3(rdev))
1771 radeon_atom_encoder_dpms_dig(encoder, mode);
1772 else
1773 radeon_atom_encoder_dpms_avivo(encoder, mode);
1774 break;
1775 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1776 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1777 if (ASIC_IS_DCE5(rdev)) {
1778 switch (mode) {
1779 case DRM_MODE_DPMS_ON:
1780 atombios_dac_setup(encoder, ATOM_ENABLE);
1781 break;
1782 case DRM_MODE_DPMS_STANDBY:
1783 case DRM_MODE_DPMS_SUSPEND:
1784 case DRM_MODE_DPMS_OFF:
1785 atombios_dac_setup(encoder, ATOM_DISABLE);
1786 break;
1787 }
1788 } else
1789 radeon_atom_encoder_dpms_avivo(encoder, mode);
1790 break;
1791 default:
1792 return;
1793 }
1794
1795 if (ext_encoder)
1796 radeon_atom_encoder_dpms_ext(encoder, ext_encoder, mode);
1797
1798 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1799
1800}
1801
1802union crtc_source_param {
1803 SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
1804 SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
1805};
1806
1807static void
1808atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1809{
1810 struct drm_device *dev = encoder->dev;
1811 struct radeon_device *rdev = dev->dev_private;
1812 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1813 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1814 union crtc_source_param args;
1815 int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
1816 uint8_t frev, crev;
1817 struct radeon_encoder_atom_dig *dig;
1818
1819 memset(&args, 0, sizeof(args));
1820
1821 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1822 return;
1823
1824 switch (frev) {
1825 case 1:
1826 switch (crev) {
1827 case 1:
1828 default:
1829 if (ASIC_IS_AVIVO(rdev))
1830 args.v1.ucCRTC = radeon_crtc->crtc_id;
1831 else {
1832 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) {
1833 args.v1.ucCRTC = radeon_crtc->crtc_id;
1834 } else {
1835 args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
1836 }
1837 }
1838 switch (radeon_encoder->encoder_id) {
1839 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1840 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1841 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1842 break;
1843 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1844 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1845 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
1846 args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1847 else
1848 args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1849 break;
1850 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1851 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1852 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1853 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1854 break;
1855 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1856 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1857 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1858 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1859 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1860 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1861 else
1862 args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1863 break;
1864 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1865 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1866 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1867 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1868 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1869 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1870 else
1871 args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1872 break;
1873 }
1874 break;
1875 case 2:
1876 args.v2.ucCRTC = radeon_crtc->crtc_id;
1877 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) {
1878 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1879
1880 if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)
1881 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
1882 else if (connector->connector_type == DRM_MODE_CONNECTOR_VGA)
1883 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_CRT;
1884 else
1885 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1886 } else
1887 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1888 switch (radeon_encoder->encoder_id) {
1889 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1890 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1891 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
e68adef8 1892 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3f03ced8
AD		 1893 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1894 dig = radeon_encoder->enc_priv;
1895 switch (dig->dig_encoder) {
1896 case 0:
1897 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1898 break;
1899 case 1:
1900 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1901 break;
1902 case 2:
1903 args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
1904 break;
1905 case 3:
1906 args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
1907 break;
1908 case 4:
1909 args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
1910 break;
1911 case 5:
1912 args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
1913 break;
e68adef8
AD		 1914 case 6:
1915 args.v2.ucEncoderID = ASIC_INT_DIG7_ENCODER_ID;
1916 break;
3f03ced8
AD		 1917 }
1918 break;
1919 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1920 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1921 break;
1922 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1923 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1924 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1925 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1926 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1927 else
1928 args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1929 break;
1930 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1931 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1932 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1933 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1934 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1935 else
1936 args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1937 break;
1938 }
1939 break;
1940 }
1941 break;
1942 default:
1943 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1944 return;
1945 }
1946
1947 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1948
1949 /* update scratch regs with new routing */
1950 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1951}
1952
1953static void
1954atombios_apply_encoder_quirks(struct drm_encoder *encoder,
1955 struct drm_display_mode *mode)
1956{
1957 struct drm_device *dev = encoder->dev;
1958 struct radeon_device *rdev = dev->dev_private;
1959 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1960 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1961
1962 /* Funky macbooks */
1963 if ((dev->pdev->device == 0x71C5) &&
1964 (dev->pdev->subsystem_vendor == 0x106b) &&
1965 (dev->pdev->subsystem_device == 0x0080)) {
1966 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1967 uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
1968
1969 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
1970 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
1971
1972 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
1973 }
1974 }
1975
1976 /* set scaler clears this on some chips */
1977 if (ASIC_IS_AVIVO(rdev) &&
1978 (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) {
d798f2f2
AD		 1979 if (ASIC_IS_DCE8(rdev)) {
1980 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1981 WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset,
1982 CIK_INTERLEAVE_EN);
1983 else
1984 WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1985 } else if (ASIC_IS_DCE4(rdev)) {
3f03ced8
AD		 1986 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1987 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset,
1988 EVERGREEN_INTERLEAVE_EN);
1989 else
1990 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1991 } else {
1992 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1993 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
1994 AVIVO_D1MODE_INTERLEAVE_EN);
1995 else
1996 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1997 }
1998 }
1999}
2000
2001static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder)
2002{
2003 struct drm_device *dev = encoder->dev;
2004 struct radeon_device *rdev = dev->dev_private;
2005 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
2006 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2007 struct drm_encoder *test_encoder;
41fa5437 2008 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
3f03ced8
AD		 2009 uint32_t dig_enc_in_use = 0;
2010
41fa5437
AD		 2011 if (ASIC_IS_DCE6(rdev)) {
2012 /* DCE6 */
2013 switch (radeon_encoder->encoder_id) {
2014 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2015 if (dig->linkb)
2016 return 1;
2017 else
2018 return 0;
2019 break;
2020 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2021 if (dig->linkb)
2022 return 3;
2023 else
2024 return 2;
2025 break;
2026 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2027 if (dig->linkb)
2028 return 5;
2029 else
2030 return 4;
2031 break;
e68adef8
AD		 2032 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2033 return 6;
2034 break;
41fa5437
AD		 2035 }
2036 } else if (ASIC_IS_DCE4(rdev)) {
2037 /* DCE4/5 */
2038 if (ASIC_IS_DCE41(rdev) && !ASIC_IS_DCE61(rdev)) {
3f03ced8
AD		 2039 /* ontario follows DCE4 */
2040 if (rdev->family == CHIP_PALM) {
2041 if (dig->linkb)
2042 return 1;
2043 else
2044 return 0;
2045 } else
2046 /* llano follows DCE3.2 */
2047 return radeon_crtc->crtc_id;
2048 } else {
2049 switch (radeon_encoder->encoder_id) {
2050 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2051 if (dig->linkb)
2052 return 1;
2053 else
2054 return 0;
2055 break;
2056 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2057 if (dig->linkb)
2058 return 3;
2059 else
2060 return 2;
2061 break;
2062 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2063 if (dig->linkb)
2064 return 5;
2065 else
2066 return 4;
2067 break;
2068 }
2069 }
2070 }
2071
2072 /* on DCE32 and encoder can driver any block so just crtc id */
2073 if (ASIC_IS_DCE32(rdev)) {
2074 return radeon_crtc->crtc_id;
2075 }
2076
2077 /* on DCE3 - LVTMA can only be driven by DIGB */
2078 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
2079 struct radeon_encoder *radeon_test_encoder;
2080
2081 if (encoder == test_encoder)
2082 continue;
2083
2084 if (!radeon_encoder_is_digital(test_encoder))
2085 continue;
2086
2087 radeon_test_encoder = to_radeon_encoder(test_encoder);
2088 dig = radeon_test_encoder->enc_priv;
2089
2090 if (dig->dig_encoder >= 0)
2091 dig_enc_in_use |= (1 << dig->dig_encoder);
2092 }
2093
2094 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) {
2095 if (dig_enc_in_use & 0x2)
2096 DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
2097 return 1;
2098 }
2099 if (!(dig_enc_in_use & 1))
2100 return 0;
2101 return 1;
2102}
2103
2104/* This only needs to be called once at startup */
2105void
2106radeon_atom_encoder_init(struct radeon_device *rdev)
2107{
2108 struct drm_device *dev = rdev->ddev;
2109 struct drm_encoder *encoder;
2110
2111 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2112 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2113 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2114
2115 switch (radeon_encoder->encoder_id) {
2116 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2117 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2118 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
e68adef8 2119 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3f03ced8
AD		 2120 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2121 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
2122 break;
2123 default:
2124 break;
2125 }
2126
1d3949c4 2127 if (ext_encoder && (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)))
3f03ced8
AD		 2128 atombios_external_encoder_setup(encoder, ext_encoder,
2129 EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT);
2130 }
2131}
2132
2133static void
2134radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
2135 struct drm_display_mode *mode,
2136 struct drm_display_mode *adjusted_mode)
2137{
2138 struct drm_device *dev = encoder->dev;
2139 struct radeon_device *rdev = dev->dev_private;
2140 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3f03ced8
AD		 2141
2142 radeon_encoder->pixel_clock = adjusted_mode->clock;
2143
8d1af57a
AD		 2144 /* need to call this here rather than in prepare() since we need some crtc info */
2145 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2146
3f03ced8
AD		 2147 if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) {
2148 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
2149 atombios_yuv_setup(encoder, true);
2150 else
2151 atombios_yuv_setup(encoder, false);
2152 }
2153
2154 switch (radeon_encoder->encoder_id) {
2155 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2156 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2157 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2158 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2159 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
2160 break;
2161 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2162 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2163 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
e68adef8 2164 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3f03ced8 2165 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
8d1af57a 2166 /* handled in dpms */
3f03ced8
AD		 2167 break;
2168 case ENCODER_OBJECT_ID_INTERNAL_DDI:
2169 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2170 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2171 atombios_dvo_setup(encoder, ATOM_ENABLE);
2172 break;
2173 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2174 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2175 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2176 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2177 atombios_dac_setup(encoder, ATOM_ENABLE);
2178 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) {
2179 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2180 atombios_tv_setup(encoder, ATOM_ENABLE);
2181 else
2182 atombios_tv_setup(encoder, ATOM_DISABLE);
2183 }
2184 break;
2185 }
2186
3f03ced8
AD		 2187 atombios_apply_encoder_quirks(encoder, adjusted_mode);
2188
2189 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
a973bea1
AD		 2190 if (rdev->asic->display.hdmi_enable)
2191 radeon_hdmi_enable(rdev, encoder, true);
2192 if (rdev->asic->display.hdmi_setmode)
2193 radeon_hdmi_setmode(rdev, encoder, adjusted_mode);
3f03ced8
AD		 2194 }
2195}
2196
2197static bool
2198atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2199{
2200 struct drm_device *dev = encoder->dev;
2201 struct radeon_device *rdev = dev->dev_private;
2202 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2203 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2204
2205 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
2206 ATOM_DEVICE_CV_SUPPORT |
2207 ATOM_DEVICE_CRT_SUPPORT)) {
2208 DAC_LOAD_DETECTION_PS_ALLOCATION args;
2209 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
2210 uint8_t frev, crev;
2211
2212 memset(&args, 0, sizeof(args));
2213
2214 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2215 return false;
2216
2217 args.sDacload.ucMisc = 0;
2218
2219 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
2220 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
2221 args.sDacload.ucDacType = ATOM_DAC_A;
2222 else
2223 args.sDacload.ucDacType = ATOM_DAC_B;
2224
2225 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
2226 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
2227 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
2228 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
2229 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2230 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
2231 if (crev >= 3)
2232 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
2233 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2234 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
2235 if (crev >= 3)
2236 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
2237 }
2238
2239 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2240
2241 return true;
2242 } else
2243 return false;
2244}
2245
2246static enum drm_connector_status
2247radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2248{
2249 struct drm_device *dev = encoder->dev;
2250 struct radeon_device *rdev = dev->dev_private;
2251 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2252 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2253 uint32_t bios_0_scratch;
2254
2255 if (!atombios_dac_load_detect(encoder, connector)) {
2256 DRM_DEBUG_KMS("detect returned false \n");
2257 return connector_status_unknown;
2258 }
2259
2260 if (rdev->family >= CHIP_R600)
2261 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2262 else
2263 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2264
2265 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2266 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2267 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2268 return connector_status_connected;
2269 }
2270 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2271 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2272 return connector_status_connected;
2273 }
2274 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2275 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2276 return connector_status_connected;
2277 }
2278 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2279 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2280 return connector_status_connected; /* CTV */
2281 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2282 return connector_status_connected; /* STV */
2283 }
2284 return connector_status_disconnected;
2285}
2286
2287static enum drm_connector_status
2288radeon_atom_dig_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2289{
2290 struct drm_device *dev = encoder->dev;
2291 struct radeon_device *rdev = dev->dev_private;
2292 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2293 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2294 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2295 u32 bios_0_scratch;
2296
2297 if (!ASIC_IS_DCE4(rdev))
2298 return connector_status_unknown;
2299
2300 if (!ext_encoder)
2301 return connector_status_unknown;
2302
2303 if ((radeon_connector->devices & ATOM_DEVICE_CRT_SUPPORT) == 0)
2304 return connector_status_unknown;
2305
2306 /* load detect on the dp bridge */
2307 atombios_external_encoder_setup(encoder, ext_encoder,
2308 EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION);
2309
2310 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2311
2312 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2313 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2314 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2315 return connector_status_connected;
2316 }
2317 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2318 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2319 return connector_status_connected;
2320 }
2321 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2322 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2323 return connector_status_connected;
2324 }
2325 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2326 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2327 return connector_status_connected; /* CTV */
2328 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2329 return connector_status_connected; /* STV */
2330 }
2331 return connector_status_disconnected;
2332}
2333
2334void
2335radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder)
2336{
2337 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2338
2339 if (ext_encoder)
2340 /* ddc_setup on the dp bridge */
2341 atombios_external_encoder_setup(encoder, ext_encoder,
2342 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP);
2343
2344}
2345
2346static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
2347{
cfcbd6d3 2348 struct radeon_device *rdev = encoder->dev->dev_private;
3f03ced8
AD		 2349 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2350 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
2351
2352 if ((radeon_encoder->active_device &
2353 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
2354 (radeon_encoder_get_dp_bridge_encoder_id(encoder) !=
2355 ENCODER_OBJECT_ID_NONE)) {
2356 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
cfcbd6d3 2357 if (dig) {
3f03ced8 2358 dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder);
cfcbd6d3
RM		 2359 if (radeon_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) {
2360 if (rdev->family >= CHIP_R600)
2361 dig->afmt = rdev->mode_info.afmt[dig->dig_encoder];
2362 else
2363 /* RS600/690/740 have only 1 afmt block */
2364 dig->afmt = rdev->mode_info.afmt[0];
2365 }
2366 }
3f03ced8
AD		 2367 }
2368
2369 radeon_atom_output_lock(encoder, true);
3f03ced8
AD		 2370
2371 if (connector) {
2372 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2373
2374 /* select the clock/data port if it uses a router */
2375 if (radeon_connector->router.cd_valid)
2376 radeon_router_select_cd_port(radeon_connector);
2377
2378 /* turn eDP panel on for mode set */
2379 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
2380 atombios_set_edp_panel_power(connector,
2381 ATOM_TRANSMITTER_ACTION_POWER_ON);
2382 }
2383
2384 /* this is needed for the pll/ss setup to work correctly in some cases */
2385 atombios_set_encoder_crtc_source(encoder);
2386}
2387
2388static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
2389{
8d1af57a 2390 /* need to call this here as we need the crtc set up */
3f03ced8
AD		 2391 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
2392 radeon_atom_output_lock(encoder, false);
2393}
2394
2395static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
2396{
2397 struct drm_device *dev = encoder->dev;
2398 struct radeon_device *rdev = dev->dev_private;
2399 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2400 struct radeon_encoder_atom_dig *dig;
2401
2402 /* check for pre-DCE3 cards with shared encoders;
2403 * can't really use the links individually, so don't disable
2404 * the encoder if it's in use by another connector
2405 */
2406 if (!ASIC_IS_DCE3(rdev)) {
2407 struct drm_encoder *other_encoder;
2408 struct radeon_encoder *other_radeon_encoder;
2409
2410 list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) {
2411 other_radeon_encoder = to_radeon_encoder(other_encoder);
2412 if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) &&
2413 drm_helper_encoder_in_use(other_encoder))
2414 goto disable_done;
2415 }
2416 }
2417
2418 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2419
2420 switch (radeon_encoder->encoder_id) {
2421 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2422 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2423 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2424 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2425 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE);
2426 break;
2427 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2428 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2429 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
e68adef8 2430 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3f03ced8 2431 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
8d1af57a 2432 /* handled in dpms */
3f03ced8
AD		 2433 break;
2434 case ENCODER_OBJECT_ID_INTERNAL_DDI:
2435 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2436 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2437 atombios_dvo_setup(encoder, ATOM_DISABLE);
2438 break;
2439 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2440 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2441 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2442 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2443 atombios_dac_setup(encoder, ATOM_DISABLE);
2444 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2445 atombios_tv_setup(encoder, ATOM_DISABLE);
2446 break;
2447 }
2448
2449disable_done:
2450 if (radeon_encoder_is_digital(encoder)) {
a973bea1
AD		 2451 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
2452 if (rdev->asic->display.hdmi_enable)
2453 radeon_hdmi_enable(rdev, encoder, false);
2454 }
3f03ced8
AD		 2455 dig = radeon_encoder->enc_priv;
2456 dig->dig_encoder = -1;
2457 }
2458 radeon_encoder->active_device = 0;
2459}
2460
2461/* these are handled by the primary encoders */
2462static void radeon_atom_ext_prepare(struct drm_encoder *encoder)
2463{
2464
2465}
2466
2467static void radeon_atom_ext_commit(struct drm_encoder *encoder)
2468{
2469
2470}
2471
2472static void
2473radeon_atom_ext_mode_set(struct drm_encoder *encoder,
2474 struct drm_display_mode *mode,
2475 struct drm_display_mode *adjusted_mode)
2476{
2477
2478}
2479
2480static void radeon_atom_ext_disable(struct drm_encoder *encoder)
2481{
2482
2483}
2484
2485static void
2486radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode)
2487{
2488
2489}
2490
2491static bool radeon_atom_ext_mode_fixup(struct drm_encoder *encoder,
e811f5ae 2492 const struct drm_display_mode *mode,
3f03ced8
AD		 2493 struct drm_display_mode *adjusted_mode)
2494{
2495 return true;
2496}
2497
2498static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = {
2499 .dpms = radeon_atom_ext_dpms,
2500 .mode_fixup = radeon_atom_ext_mode_fixup,
2501 .prepare = radeon_atom_ext_prepare,
2502 .mode_set = radeon_atom_ext_mode_set,
2503 .commit = radeon_atom_ext_commit,
2504 .disable = radeon_atom_ext_disable,
2505 /* no detect for TMDS/LVDS yet */
2506};
2507
2508static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
2509 .dpms = radeon_atom_encoder_dpms,
2510 .mode_fixup = radeon_atom_mode_fixup,
2511 .prepare = radeon_atom_encoder_prepare,
2512 .mode_set = radeon_atom_encoder_mode_set,
2513 .commit = radeon_atom_encoder_commit,
2514 .disable = radeon_atom_encoder_disable,
2515 .detect = radeon_atom_dig_detect,
2516};
2517
2518static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
2519 .dpms = radeon_atom_encoder_dpms,
2520 .mode_fixup = radeon_atom_mode_fixup,
2521 .prepare = radeon_atom_encoder_prepare,
2522 .mode_set = radeon_atom_encoder_mode_set,
2523 .commit = radeon_atom_encoder_commit,
2524 .detect = radeon_atom_dac_detect,
2525};
2526
2527void radeon_enc_destroy(struct drm_encoder *encoder)
2528{
2529 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
f3728734
AD		 2530 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2531 radeon_atom_backlight_exit(radeon_encoder);
3f03ced8
AD		 2532 kfree(radeon_encoder->enc_priv);
2533 drm_encoder_cleanup(encoder);
2534 kfree(radeon_encoder);
2535}
2536
2537static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
2538 .destroy = radeon_enc_destroy,
2539};
2540
1109ca09 2541static struct radeon_encoder_atom_dac *
3f03ced8
AD		 2542radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
2543{
2544 struct drm_device *dev = radeon_encoder->base.dev;
2545 struct radeon_device *rdev = dev->dev_private;
2546 struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
2547
2548 if (!dac)
2549 return NULL;
2550
2551 dac->tv_std = radeon_atombios_get_tv_info(rdev);
2552 return dac;
2553}
2554
1109ca09 2555static struct radeon_encoder_atom_dig *
3f03ced8
AD		 2556radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
2557{
2558 int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
2559 struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
2560
2561 if (!dig)
2562 return NULL;
2563
2564 /* coherent mode by default */
2565 dig->coherent_mode = true;
2566 dig->dig_encoder = -1;
2567
2568 if (encoder_enum == 2)
2569 dig->linkb = true;
2570 else
2571 dig->linkb = false;
2572
2573 return dig;
2574}
2575
2576void
2577radeon_add_atom_encoder(struct drm_device *dev,
2578 uint32_t encoder_enum,
2579 uint32_t supported_device,
2580 u16 caps)
2581{
2582 struct radeon_device *rdev = dev->dev_private;
2583 struct drm_encoder *encoder;
2584 struct radeon_encoder *radeon_encoder;
2585
2586 /* see if we already added it */
2587 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2588 radeon_encoder = to_radeon_encoder(encoder);
2589 if (radeon_encoder->encoder_enum == encoder_enum) {
2590 radeon_encoder->devices |= supported_device;
2591 return;
2592 }
2593
2594 }
2595
2596 /* add a new one */
2597 radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
2598 if (!radeon_encoder)
2599 return;
2600
2601 encoder = &radeon_encoder->base;
2602 switch (rdev->num_crtc) {
2603 case 1:
2604 encoder->possible_crtcs = 0x1;
2605 break;
2606 case 2:
2607 default:
2608 encoder->possible_crtcs = 0x3;
2609 break;
2610 case 4:
2611 encoder->possible_crtcs = 0xf;
2612 break;
2613 case 6:
2614 encoder->possible_crtcs = 0x3f;
2615 break;
2616 }
2617
2618 radeon_encoder->enc_priv = NULL;
2619
2620 radeon_encoder->encoder_enum = encoder_enum;
2621 radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
2622 radeon_encoder->devices = supported_device;
2623 radeon_encoder->rmx_type = RMX_OFF;
2624 radeon_encoder->underscan_type = UNDERSCAN_OFF;
2625 radeon_encoder->is_ext_encoder = false;
2626 radeon_encoder->caps = caps;
2627
2628 switch (radeon_encoder->encoder_id) {
2629 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2630 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2631 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2632 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2633 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2634 radeon_encoder->rmx_type = RMX_FULL;
2635 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2636 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2637 } else {
2638 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2639 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2640 }
2641 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2642 break;
2643 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2644 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2645 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2646 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2647 break;
2648 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2649 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2650 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2651 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC);
2652 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2653 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2654 break;
2655 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2656 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2657 case ENCODER_OBJECT_ID_INTERNAL_DDI:
2658 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2659 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2660 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2661 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
e68adef8 2662 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3f03ced8
AD		 2663 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2664 radeon_encoder->rmx_type = RMX_FULL;
2665 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2666 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2667 } else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
2668 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2669 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2670 } else {
2671 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2672 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2673 }
2674 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2675 break;
2676 case ENCODER_OBJECT_ID_SI170B:
2677 case ENCODER_OBJECT_ID_CH7303:
2678 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
2679 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
2680 case ENCODER_OBJECT_ID_TITFP513:
2681 case ENCODER_OBJECT_ID_VT1623:
2682 case ENCODER_OBJECT_ID_HDMI_SI1930:
2683 case ENCODER_OBJECT_ID_TRAVIS:
2684 case ENCODER_OBJECT_ID_NUTMEG:
2685 /* these are handled by the primary encoders */
2686 radeon_encoder->is_ext_encoder = true;
2687 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2688 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2689 else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
2690 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2691 else
2692 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2693 drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs);
2694 break;
2695 }
2696}
Linux kernel - Deliverables
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