projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 6596afd4 AD |
1 | /* |
| 2 | * Copyright 2010 Advanced Micro Devices, Inc. | |
| 3 | * | |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
| 5 | * copy of this software and associated documentation files (the "Software"), | |
| 6 | * to deal in the Software without restriction, including without limitation | |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the | |
| 9 | * Software is furnished to do so, subject to the following conditions: | |
| 10 | * | |
| 11 | * The above copyright notice and this permission notice shall be included in | |
| 12 | * all copies or substantial portions of the Software. | |
| 13 | * | |
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 20 | * OTHER DEALINGS IN THE SOFTWARE. | |
| 21 | * | |
| 22 | * Authors: Alex Deucher | |
| 23 | */ | |
| 24 | #ifndef _BTCD_H_ | |
| 25 | #define _BTCD_H_ | |
| 26 | ||
| 27 | /* pm registers */ | |
| 28 | ||
| 29 | #define GENERAL_PWRMGT 0x63c | |
| 30 | # define GLOBAL_PWRMGT_EN (1 << 0) | |
| 31 | # define STATIC_PM_EN (1 << 1) | |
| 32 | # define THERMAL_PROTECTION_DIS (1 << 2) | |
| 33 | # define THERMAL_PROTECTION_TYPE (1 << 3) | |
| 34 | # define ENABLE_GEN2PCIE (1 << 4) | |
| 35 | # define ENABLE_GEN2XSP (1 << 5) | |
| 36 | # define SW_SMIO_INDEX(x) ((x) << 6) | |
| 37 | # define SW_SMIO_INDEX_MASK (3 << 6) | |
| 38 | # define SW_SMIO_INDEX_SHIFT 6 | |
| 39 | # define LOW_VOLT_D2_ACPI (1 << 8) | |
| 40 | # define LOW_VOLT_D3_ACPI (1 << 9) | |
| 41 | # define VOLT_PWRMGT_EN (1 << 10) | |
| 42 | # define BACKBIAS_PAD_EN (1 << 18) | |
| 43 | # define BACKBIAS_VALUE (1 << 19) | |
| 44 | # define DYN_SPREAD_SPECTRUM_EN (1 << 23) | |
| 45 | # define AC_DC_SW (1 << 24) | |
| 46 | ||
| 47 | #define CG_BIF_REQ_AND_RSP 0x7f4 | |
| 48 | #define CG_CLIENT_REQ(x) ((x) << 0) | |
| 49 | #define CG_CLIENT_REQ_MASK (0xff << 0) | |
| 50 | #define CG_CLIENT_REQ_SHIFT 0 | |
| 51 | #define CG_CLIENT_RESP(x) ((x) << 8) | |
| 52 | #define CG_CLIENT_RESP_MASK (0xff << 8) | |
| 53 | #define CG_CLIENT_RESP_SHIFT 8 | |
| 54 | #define CLIENT_CG_REQ(x) ((x) << 16) | |
| 55 | #define CLIENT_CG_REQ_MASK (0xff << 16) | |
| 56 | #define CLIENT_CG_REQ_SHIFT 16 | |
| 57 | #define CLIENT_CG_RESP(x) ((x) << 24) | |
| 58 | #define CLIENT_CG_RESP_MASK (0xff << 24) | |
| 59 | #define CLIENT_CG_RESP_SHIFT 24 | |
| 60 | ||
| 61 | #define SCLK_PSKIP_CNTL 0x8c0 | |
| 62 | #define PSKIP_ON_ALLOW_STOP_HI(x) ((x) << 16) | |
| 63 | #define PSKIP_ON_ALLOW_STOP_HI_MASK (0xff << 16) | |
| 64 | #define PSKIP_ON_ALLOW_STOP_HI_SHIFT 16 | |
| 65 | ||
| 66 | #define CG_ULV_CONTROL 0x8c8 | |
| 67 | #define CG_ULV_PARAMETER 0x8cc | |
| 68 | ||
| 69 | #define MC_ARB_DRAM_TIMING 0x2774 | |
| 70 | #define MC_ARB_DRAM_TIMING2 0x2778 | |
| 71 | ||
| 72 | #define MC_ARB_RFSH_RATE 0x27b0 | |
| 73 | #define POWERMODE0(x) ((x) << 0) | |
| 74 | #define POWERMODE0_MASK (0xff << 0) | |
| 75 | #define POWERMODE0_SHIFT 0 | |
| 76 | #define POWERMODE1(x) ((x) << 8) | |
| 77 | #define POWERMODE1_MASK (0xff << 8) | |
| 78 | #define POWERMODE1_SHIFT 8 | |
| 79 | #define POWERMODE2(x) ((x) << 16) | |
| 80 | #define POWERMODE2_MASK (0xff << 16) | |
| 81 | #define POWERMODE2_SHIFT 16 | |
| 82 | #define POWERMODE3(x) ((x) << 24) | |
| 83 | #define POWERMODE3_MASK (0xff << 24) | |
| 84 | #define POWERMODE3_SHIFT 24 | |
| 85 | ||
| 86 | #define MC_ARB_BURST_TIME 0x2808 | |
| 87 | #define STATE0(x) ((x) << 0) | |
| 88 | #define STATE0_MASK (0x1f << 0) | |
| 89 | #define STATE0_SHIFT 0 | |
| 90 | #define STATE1(x) ((x) << 5) | |
| 91 | #define STATE1_MASK (0x1f << 5) | |
| 92 | #define STATE1_SHIFT 5 | |
| 93 | #define STATE2(x) ((x) << 10) | |
| 94 | #define STATE2_MASK (0x1f << 10) | |
| 95 | #define STATE2_SHIFT 10 | |
| 96 | #define STATE3(x) ((x) << 15) | |
| 97 | #define STATE3_MASK (0x1f << 15) | |
| 98 | #define STATE3_SHIFT 15 | |
| 99 | ||
| 100 | #define MC_SEQ_RAS_TIMING 0x28a0 | |
| 101 | #define MC_SEQ_CAS_TIMING 0x28a4 | |
| 102 | #define MC_SEQ_MISC_TIMING 0x28a8 | |
| 103 | #define MC_SEQ_MISC_TIMING2 0x28ac | |
| 104 | ||
| 105 | #define MC_SEQ_RD_CTL_D0 0x28b4 | |
| 106 | #define MC_SEQ_RD_CTL_D1 0x28b8 | |
| 107 | #define MC_SEQ_WR_CTL_D0 0x28bc | |
| 108 | #define MC_SEQ_WR_CTL_D1 0x28c0 | |
| 109 | ||
| 110 | #define MC_PMG_AUTO_CFG 0x28d4 | |
| 111 | ||
| 112 | #define MC_SEQ_STATUS_M 0x29f4 | |
| 113 | # define PMG_PWRSTATE (1 << 16) | |
| 114 | ||
| 115 | #define MC_SEQ_MISC0 0x2a00 | |
| 116 | #define MC_SEQ_MISC0_GDDR5_SHIFT 28 | |
| 117 | #define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000 | |
| 118 | #define MC_SEQ_MISC0_GDDR5_VALUE 5 | |
| 119 | #define MC_SEQ_MISC1 0x2a04 | |
| 120 | #define MC_SEQ_RESERVE_M 0x2a08 | |
| 121 | #define MC_PMG_CMD_EMRS 0x2a0c | |
| 122 | ||
| 123 | #define MC_SEQ_MISC3 0x2a2c | |
| 124 | ||
| 125 | #define MC_SEQ_MISC5 0x2a54 | |
| 126 | #define MC_SEQ_MISC6 0x2a58 | |
| 127 | ||
| 128 | #define MC_SEQ_MISC7 0x2a64 | |
| 129 | ||
| 130 | #define MC_SEQ_CG 0x2a68 | |
| 131 | #define CG_SEQ_REQ(x) ((x) << 0) | |
| 132 | #define CG_SEQ_REQ_MASK (0xff << 0) | |
| 133 | #define CG_SEQ_REQ_SHIFT 0 | |
| 134 | #define CG_SEQ_RESP(x) ((x) << 8) | |
| 135 | #define CG_SEQ_RESP_MASK (0xff << 8) | |
| 136 | #define CG_SEQ_RESP_SHIFT 8 | |
| 137 | #define SEQ_CG_REQ(x) ((x) << 16) | |
| 138 | #define SEQ_CG_REQ_MASK (0xff << 16) | |
| 139 | #define SEQ_CG_REQ_SHIFT 16 | |
| 140 | #define SEQ_CG_RESP(x) ((x) << 24) | |
| 141 | #define SEQ_CG_RESP_MASK (0xff << 24) | |
| 142 | #define SEQ_CG_RESP_SHIFT 24 | |
| 143 | #define MC_SEQ_RAS_TIMING_LP 0x2a6c | |
| 144 | #define MC_SEQ_CAS_TIMING_LP 0x2a70 | |
| 145 | #define MC_SEQ_MISC_TIMING_LP 0x2a74 | |
| 146 | #define MC_SEQ_MISC_TIMING2_LP 0x2a78 | |
| 147 | #define MC_SEQ_WR_CTL_D0_LP 0x2a7c | |
| 148 | #define MC_SEQ_WR_CTL_D1_LP 0x2a80 | |
| 149 | #define MC_SEQ_PMG_CMD_EMRS_LP 0x2a84 | |
| 150 | #define MC_SEQ_PMG_CMD_MRS_LP 0x2a88 | |
| 151 | ||
| 152 | #define MC_PMG_CMD_MRS 0x2aac | |
| 153 | ||
| 154 | #define MC_SEQ_RD_CTL_D0_LP 0x2b1c | |
| 155 | #define MC_SEQ_RD_CTL_D1_LP 0x2b20 | |
| 156 | ||
| 157 | #define MC_PMG_CMD_MRS1 0x2b44 | |
| 158 | #define MC_SEQ_PMG_CMD_MRS1_LP 0x2b48 | |
| 159 | ||
| 160 | #define LB_SYNC_RESET_SEL 0x6b28 | |
| 161 | #define LB_SYNC_RESET_SEL_MASK (3 << 0) | |
| 162 | #define LB_SYNC_RESET_SEL_SHIFT 0 | |
| 163 | ||
| 164 | /* PCIE link stuff */ | |
| 165 | #define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */ | |
| 166 | # define LC_GEN2_EN_STRAP (1 << 0) | |
| 167 | # define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 1) | |
| 168 | # define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 5) | |
| 169 | # define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 6) | |
| 170 | # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 8) | |
| 171 | # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 3 | |
| 172 | # define LC_CURRENT_DATA_RATE (1 << 11) | |
| 173 | # define LC_HW_VOLTAGE_IF_CONTROL(x) ((x) << 12) | |
| 174 | # define LC_HW_VOLTAGE_IF_CONTROL_MASK (3 << 12) | |
| 175 | # define LC_HW_VOLTAGE_IF_CONTROL_SHIFT 12 | |
| 176 | # define LC_VOLTAGE_TIMER_SEL_MASK (0xf << 14) | |
| 177 | # define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 21) | |
| 178 | # define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 23) | |
| 179 | # define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 24) | |
| 180 | ||
| 181 | #endif |