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drm/radeon: fix sclk DS enablement
[deliverable/linux.git] / drivers / gpu / drm / radeon / ci_dpm.c
CommitLineData
cc8dbbb4
AD		 1/*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
7e1858f9 24#include <linux/firmware.h>
cc8dbbb4
AD		 25#include "drmP.h"
26#include "radeon.h"
01467a9b 27#include "radeon_asic.h"
7e1858f9 28#include "radeon_ucode.h"
cc8dbbb4
AD		 29#include "cikd.h"
30#include "r600_dpm.h"
31#include "ci_dpm.h"
32#include "atom.h"
94b4adc5 33#include <linux/seq_file.h>
cc8dbbb4
AD		 34
35#define MC_CG_ARB_FREQ_F0 0x0a
36#define MC_CG_ARB_FREQ_F1 0x0b
37#define MC_CG_ARB_FREQ_F2 0x0c
38#define MC_CG_ARB_FREQ_F3 0x0d
39
40#define SMC_RAM_END 0x40000
41
42#define VOLTAGE_SCALE 4
43#define VOLTAGE_VID_OFFSET_SCALE1 625
44#define VOLTAGE_VID_OFFSET_SCALE2 100
45
2d40038d
AD		 46static const struct ci_pt_defaults defaults_hawaii_xt =
47{
48 1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0xB0000,
49 { 0x84, 0x0, 0x0, 0x7F, 0x0, 0x0, 0x5A, 0x60, 0x51, 0x8E, 0x79, 0x6B, 0x5F, 0x90, 0x79 },
50 { 0x1EA, 0x1EA, 0x1EA, 0x224, 0x224, 0x224, 0x24F, 0x24F, 0x24F, 0x28E, 0x28E, 0x28E, 0x2BC, 0x2BC, 0x2BC }
51};
52
53static const struct ci_pt_defaults defaults_hawaii_pro =
54{
55 1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0x65062,
56 { 0x93, 0x0, 0x0, 0x97, 0x0, 0x0, 0x6B, 0x60, 0x51, 0x95, 0x79, 0x6B, 0x5F, 0x90, 0x79 },
57 { 0x1EA, 0x1EA, 0x1EA, 0x224, 0x224, 0x224, 0x24F, 0x24F, 0x24F, 0x28E, 0x28E, 0x28E, 0x2BC, 0x2BC, 0x2BC }
58};
59
cc8dbbb4
AD		 60static const struct ci_pt_defaults defaults_bonaire_xt =
61{
62 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0xB0000,
63 { 0x79, 0x253, 0x25D, 0xAE, 0x72, 0x80, 0x83, 0x86, 0x6F, 0xC8, 0xC9, 0xC9, 0x2F, 0x4D, 0x61 },
64 { 0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203, 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5, 0x2B4 }
65};
66
67static const struct ci_pt_defaults defaults_bonaire_pro =
68{
69 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0x65062,
70 { 0x8C, 0x23F, 0x244, 0xA6, 0x83, 0x85, 0x86, 0x86, 0x83, 0xDB, 0xDB, 0xDA, 0x67, 0x60, 0x5F },
71 { 0x187, 0x193, 0x193, 0x1C7, 0x1D1, 0x1D1, 0x210, 0x219, 0x219, 0x266, 0x26C, 0x26C, 0x2C9, 0x2CB, 0x2CB }
72};
73
74static const struct ci_pt_defaults defaults_saturn_xt =
75{
76 1, 0xF, 0xFD, 0x19, 5, 55, 0, 0x70000,
77 { 0x8C, 0x247, 0x249, 0xA6, 0x80, 0x81, 0x8B, 0x89, 0x86, 0xC9, 0xCA, 0xC9, 0x4D, 0x4D, 0x4D },
78 { 0x187, 0x187, 0x187, 0x1C7, 0x1C7, 0x1C7, 0x210, 0x210, 0x210, 0x266, 0x266, 0x266, 0x2C9, 0x2C9, 0x2C9 }
79};
80
81static const struct ci_pt_defaults defaults_saturn_pro =
82{
83 1, 0xF, 0xFD, 0x19, 5, 55, 0, 0x30000,
84 { 0x96, 0x21D, 0x23B, 0xA1, 0x85, 0x87, 0x83, 0x84, 0x81, 0xE6, 0xE6, 0xE6, 0x71, 0x6A, 0x6A },
85 { 0x193, 0x19E, 0x19E, 0x1D2, 0x1DC, 0x1DC, 0x21A, 0x223, 0x223, 0x26E, 0x27E, 0x274, 0x2CF, 0x2D2, 0x2D2 }
86};
87
88static const struct ci_pt_config_reg didt_config_ci[] =
89{
90 { 0x10, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
91 { 0x10, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
92 { 0x10, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
93 { 0x10, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
94 { 0x11, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
95 { 0x11, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
96 { 0x11, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
97 { 0x11, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
98 { 0x12, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
99 { 0x12, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
100 { 0x12, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
101 { 0x12, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
102 { 0x2, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
103 { 0x2, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
104 { 0x2, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
105 { 0x1, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
106 { 0x1, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
107 { 0x0, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
108 { 0x30, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
109 { 0x30, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
110 { 0x30, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
111 { 0x30, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
112 { 0x31, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
113 { 0x31, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
114 { 0x31, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
115 { 0x31, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
116 { 0x32, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
117 { 0x32, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
118 { 0x32, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
119 { 0x32, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
120 { 0x22, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
121 { 0x22, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
122 { 0x22, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
123 { 0x21, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
124 { 0x21, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
125 { 0x20, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
126 { 0x50, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
127 { 0x50, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
128 { 0x50, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
129 { 0x50, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
130 { 0x51, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
131 { 0x51, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
132 { 0x51, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
133 { 0x51, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
134 { 0x52, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
135 { 0x52, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
136 { 0x52, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
137 { 0x52, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
138 { 0x42, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
139 { 0x42, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
140 { 0x42, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
141 { 0x41, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
142 { 0x41, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
143 { 0x40, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
144 { 0x70, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
145 { 0x70, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
146 { 0x70, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
147 { 0x70, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
148 { 0x71, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
149 { 0x71, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
150 { 0x71, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
151 { 0x71, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
152 { 0x72, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
153 { 0x72, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
154 { 0x72, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
155 { 0x72, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
156 { 0x62, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
157 { 0x62, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
158 { 0x62, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
159 { 0x61, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
160 { 0x61, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
161 { 0x60, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
162 { 0xFFFFFFFF }
163};
164
165extern u8 rv770_get_memory_module_index(struct radeon_device *rdev);
166extern int ni_copy_and_switch_arb_sets(struct radeon_device *rdev,
167 u32 arb_freq_src, u32 arb_freq_dest);
168extern u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock);
169extern u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode);
170extern void si_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev,
171 u32 max_voltage_steps,
172 struct atom_voltage_table *voltage_table);
173extern void cik_enter_rlc_safe_mode(struct radeon_device *rdev);
174extern void cik_exit_rlc_safe_mode(struct radeon_device *rdev);
6c7bccea 175extern int ci_mc_load_microcode(struct radeon_device *rdev);
a1d6f97c
AD		 176extern void cik_update_cg(struct radeon_device *rdev,
177 u32 block, bool enable);
cc8dbbb4
AD		 178
179static int ci_get_std_voltage_value_sidd(struct radeon_device *rdev,
180 struct atom_voltage_table_entry *voltage_table,
181 u16 *std_voltage_hi_sidd, u16 *std_voltage_lo_sidd);
182static int ci_set_power_limit(struct radeon_device *rdev, u32 n);
183static int ci_set_overdrive_target_tdp(struct radeon_device *rdev,
184 u32 target_tdp);
185static int ci_update_uvd_dpm(struct radeon_device *rdev, bool gate);
186
187static struct ci_power_info *ci_get_pi(struct radeon_device *rdev)
188{
189 struct ci_power_info *pi = rdev->pm.dpm.priv;
190
191 return pi;
192}
193
194static struct ci_ps *ci_get_ps(struct radeon_ps *rps)
195{
196 struct ci_ps *ps = rps->ps_priv;
197
198 return ps;
199}
200
201static void ci_initialize_powertune_defaults(struct radeon_device *rdev)
202{
203 struct ci_power_info *pi = ci_get_pi(rdev);
204
205 switch (rdev->pdev->device) {
6abc6d5c 206 case 0x6649:
2d40038d 207 case 0x6650:
6abc6d5c 208 case 0x6651:
2d40038d
AD		 209 case 0x6658:
210 case 0x665C:
6abc6d5c 211 case 0x665D:
2d40038d 212 default:
cc8dbbb4
AD		 213 pi->powertune_defaults = &defaults_bonaire_xt;
214 break;
2d40038d 215 case 0x6640:
2d40038d 216 case 0x6641:
6abc6d5c
AD		 217 case 0x6646:
218 case 0x6647:
219 pi->powertune_defaults = &defaults_saturn_xt;
cc8dbbb4 220 break;
2d40038d
AD		 221 case 0x67B8:
222 case 0x67B0:
6abc6d5c
AD		 223 pi->powertune_defaults = &defaults_hawaii_xt;
224 break;
225 case 0x67BA:
226 case 0x67B1:
227 pi->powertune_defaults = &defaults_hawaii_pro;
228 break;
2d40038d
AD		 229 case 0x67A0:
230 case 0x67A1:
231 case 0x67A2:
232 case 0x67A8:
233 case 0x67A9:
234 case 0x67AA:
235 case 0x67B9:
236 case 0x67BE:
6abc6d5c 237 pi->powertune_defaults = &defaults_bonaire_xt;
2d40038d 238 break;
cc8dbbb4
AD		 239 }
240
241 pi->dte_tj_offset = 0;
242
243 pi->caps_power_containment = true;
244 pi->caps_cac = false;
245 pi->caps_sq_ramping = false;
246 pi->caps_db_ramping = false;
247 pi->caps_td_ramping = false;
248 pi->caps_tcp_ramping = false;
249
250 if (pi->caps_power_containment) {
251 pi->caps_cac = true;
252 pi->enable_bapm_feature = true;
253 pi->enable_tdc_limit_feature = true;
254 pi->enable_pkg_pwr_tracking_feature = true;
255 }
256}
257
258static u8 ci_convert_to_vid(u16 vddc)
259{
260 return (6200 - (vddc * VOLTAGE_SCALE)) / 25;
261}
262
263static int ci_populate_bapm_vddc_vid_sidd(struct radeon_device *rdev)
264{
265 struct ci_power_info *pi = ci_get_pi(rdev);
266 u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd;
267 u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd;
268 u8 *hi2_vid = pi->smc_powertune_table.BapmVddCVidHiSidd2;
269 u32 i;
270
271 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries == NULL)
272 return -EINVAL;
273 if (rdev->pm.dpm.dyn_state.cac_leakage_table.count > 8)
274 return -EINVAL;
275 if (rdev->pm.dpm.dyn_state.cac_leakage_table.count !=
276 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count)
277 return -EINVAL;
278
279 for (i = 0; i < rdev->pm.dpm.dyn_state.cac_leakage_table.count; i++) {
280 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) {
281 lo_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc1);
282 hi_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc2);
283 hi2_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc3);
284 } else {
285 lo_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc);
286 hi_vid[i] = ci_convert_to_vid((u16)rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].leakage);
287 }
288 }
289 return 0;
290}
291
292static int ci_populate_vddc_vid(struct radeon_device *rdev)
293{
294 struct ci_power_info *pi = ci_get_pi(rdev);
295 u8 *vid = pi->smc_powertune_table.VddCVid;
296 u32 i;
297
298 if (pi->vddc_voltage_table.count > 8)
299 return -EINVAL;
300
301 for (i = 0; i < pi->vddc_voltage_table.count; i++)
302 vid[i] = ci_convert_to_vid(pi->vddc_voltage_table.entries[i].value);
303
304 return 0;
305}
306
307static int ci_populate_svi_load_line(struct radeon_device *rdev)
308{
309 struct ci_power_info *pi = ci_get_pi(rdev);
310 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
311
312 pi->smc_powertune_table.SviLoadLineEn = pt_defaults->svi_load_line_en;
313 pi->smc_powertune_table.SviLoadLineVddC = pt_defaults->svi_load_line_vddc;
314 pi->smc_powertune_table.SviLoadLineTrimVddC = 3;
315 pi->smc_powertune_table.SviLoadLineOffsetVddC = 0;
316
317 return 0;
318}
319
320static int ci_populate_tdc_limit(struct radeon_device *rdev)
321{
322 struct ci_power_info *pi = ci_get_pi(rdev);
323 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
324 u16 tdc_limit;
325
326 tdc_limit = rdev->pm.dpm.dyn_state.cac_tdp_table->tdc * 256;
327 pi->smc_powertune_table.TDC_VDDC_PkgLimit = cpu_to_be16(tdc_limit);
328 pi->smc_powertune_table.TDC_VDDC_ThrottleReleaseLimitPerc =
329 pt_defaults->tdc_vddc_throttle_release_limit_perc;
330 pi->smc_powertune_table.TDC_MAWt = pt_defaults->tdc_mawt;
331
332 return 0;
333}
334
335static int ci_populate_dw8(struct radeon_device *rdev)
336{
337 struct ci_power_info *pi = ci_get_pi(rdev);
338 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
339 int ret;
340
341 ret = ci_read_smc_sram_dword(rdev,
342 SMU7_FIRMWARE_HEADER_LOCATION +
343 offsetof(SMU7_Firmware_Header, PmFuseTable) +
344 offsetof(SMU7_Discrete_PmFuses, TdcWaterfallCtl),
345 (u32 *)&pi->smc_powertune_table.TdcWaterfallCtl,
346 pi->sram_end);
347 if (ret)
348 return -EINVAL;
349 else
350 pi->smc_powertune_table.TdcWaterfallCtl = pt_defaults->tdc_waterfall_ctl;
351
352 return 0;
353}
354
355static int ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(struct radeon_device *rdev)
356{
357 struct ci_power_info *pi = ci_get_pi(rdev);
358 u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd;
359 u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd;
360 int i, min, max;
361
362 min = max = hi_vid[0];
363 for (i = 0; i < 8; i++) {
364 if (0 != hi_vid[i]) {
365 if (min > hi_vid[i])
366 min = hi_vid[i];
367 if (max < hi_vid[i])
368 max = hi_vid[i];
369 }
370
371 if (0 != lo_vid[i]) {
372 if (min > lo_vid[i])
373 min = lo_vid[i];
374 if (max < lo_vid[i])
375 max = lo_vid[i];
376 }
377 }
378
379 if ((min == 0) || (max == 0))
380 return -EINVAL;
381 pi->smc_powertune_table.GnbLPMLMaxVid = (u8)max;
382 pi->smc_powertune_table.GnbLPMLMinVid = (u8)min;
383
384 return 0;
385}
386
387static int ci_populate_bapm_vddc_base_leakage_sidd(struct radeon_device *rdev)
388{
389 struct ci_power_info *pi = ci_get_pi(rdev);
390 u16 hi_sidd = pi->smc_powertune_table.BapmVddCBaseLeakageHiSidd;
391 u16 lo_sidd = pi->smc_powertune_table.BapmVddCBaseLeakageLoSidd;
392 struct radeon_cac_tdp_table *cac_tdp_table =
393 rdev->pm.dpm.dyn_state.cac_tdp_table;
394
395 hi_sidd = cac_tdp_table->high_cac_leakage / 100 * 256;
396 lo_sidd = cac_tdp_table->low_cac_leakage / 100 * 256;
397
398 pi->smc_powertune_table.BapmVddCBaseLeakageHiSidd = cpu_to_be16(hi_sidd);
399 pi->smc_powertune_table.BapmVddCBaseLeakageLoSidd = cpu_to_be16(lo_sidd);
400
401 return 0;
402}
403
404static int ci_populate_bapm_parameters_in_dpm_table(struct radeon_device *rdev)
405{
406 struct ci_power_info *pi = ci_get_pi(rdev);
407 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
408 SMU7_Discrete_DpmTable *dpm_table = &pi->smc_state_table;
409 struct radeon_cac_tdp_table *cac_tdp_table =
410 rdev->pm.dpm.dyn_state.cac_tdp_table;
411 struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table;
412 int i, j, k;
413 const u16 *def1;
414 const u16 *def2;
415
416 dpm_table->DefaultTdp = cac_tdp_table->tdp * 256;
417 dpm_table->TargetTdp = cac_tdp_table->configurable_tdp * 256;
418
419 dpm_table->DTETjOffset = (u8)pi->dte_tj_offset;
420 dpm_table->GpuTjMax =
421 (u8)(pi->thermal_temp_setting.temperature_high / 1000);
422 dpm_table->GpuTjHyst = 8;
423
424 dpm_table->DTEAmbientTempBase = pt_defaults->dte_ambient_temp_base;
425
426 if (ppm) {
427 dpm_table->PPM_PkgPwrLimit = cpu_to_be16((u16)ppm->dgpu_tdp * 256 / 1000);
428 dpm_table->PPM_TemperatureLimit = cpu_to_be16((u16)ppm->tj_max * 256);
429 } else {
430 dpm_table->PPM_PkgPwrLimit = cpu_to_be16(0);
431 dpm_table->PPM_TemperatureLimit = cpu_to_be16(0);
432 }
433
434 dpm_table->BAPM_TEMP_GRADIENT = cpu_to_be32(pt_defaults->bapm_temp_gradient);
435 def1 = pt_defaults->bapmti_r;
436 def2 = pt_defaults->bapmti_rc;
437
438 for (i = 0; i < SMU7_DTE_ITERATIONS; i++) {
439 for (j = 0; j < SMU7_DTE_SOURCES; j++) {
440 for (k = 0; k < SMU7_DTE_SINKS; k++) {
441 dpm_table->BAPMTI_R[i][j][k] = cpu_to_be16(*def1);
442 dpm_table->BAPMTI_RC[i][j][k] = cpu_to_be16(*def2);
443 def1++;
444 def2++;
445 }
446 }
447 }
448
449 return 0;
450}
451
452static int ci_populate_pm_base(struct radeon_device *rdev)
453{
454 struct ci_power_info *pi = ci_get_pi(rdev);
455 u32 pm_fuse_table_offset;
456 int ret;
457
458 if (pi->caps_power_containment) {
459 ret = ci_read_smc_sram_dword(rdev,
460 SMU7_FIRMWARE_HEADER_LOCATION +
461 offsetof(SMU7_Firmware_Header, PmFuseTable),
462 &pm_fuse_table_offset, pi->sram_end);
463 if (ret)
464 return ret;
465 ret = ci_populate_bapm_vddc_vid_sidd(rdev);
466 if (ret)
467 return ret;
468 ret = ci_populate_vddc_vid(rdev);
469 if (ret)
470 return ret;
471 ret = ci_populate_svi_load_line(rdev);
472 if (ret)
473 return ret;
474 ret = ci_populate_tdc_limit(rdev);
475 if (ret)
476 return ret;
477 ret = ci_populate_dw8(rdev);
478 if (ret)
479 return ret;
480 ret = ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(rdev);
481 if (ret)
482 return ret;
483 ret = ci_populate_bapm_vddc_base_leakage_sidd(rdev);
484 if (ret)
485 return ret;
486 ret = ci_copy_bytes_to_smc(rdev, pm_fuse_table_offset,
487 (u8 *)&pi->smc_powertune_table,
488 sizeof(SMU7_Discrete_PmFuses), pi->sram_end);
489 if (ret)
490 return ret;
491 }
492
493 return 0;
494}
495
496static void ci_do_enable_didt(struct radeon_device *rdev, const bool enable)
497{
498 struct ci_power_info *pi = ci_get_pi(rdev);
499 u32 data;
500
501 if (pi->caps_sq_ramping) {
502 data = RREG32_DIDT(DIDT_SQ_CTRL0);
503 if (enable)
504 data |= DIDT_CTRL_EN;
505 else
506 data &= ~DIDT_CTRL_EN;
507 WREG32_DIDT(DIDT_SQ_CTRL0, data);
508 }
509
510 if (pi->caps_db_ramping) {
511 data = RREG32_DIDT(DIDT_DB_CTRL0);
512 if (enable)
513 data |= DIDT_CTRL_EN;
514 else
515 data &= ~DIDT_CTRL_EN;
516 WREG32_DIDT(DIDT_DB_CTRL0, data);
517 }
518
519 if (pi->caps_td_ramping) {
520 data = RREG32_DIDT(DIDT_TD_CTRL0);
521 if (enable)
522 data |= DIDT_CTRL_EN;
523 else
524 data &= ~DIDT_CTRL_EN;
525 WREG32_DIDT(DIDT_TD_CTRL0, data);
526 }
527
528 if (pi->caps_tcp_ramping) {
529 data = RREG32_DIDT(DIDT_TCP_CTRL0);
530 if (enable)
531 data |= DIDT_CTRL_EN;
532 else
533 data &= ~DIDT_CTRL_EN;
534 WREG32_DIDT(DIDT_TCP_CTRL0, data);
535 }
536}
537
538static int ci_program_pt_config_registers(struct radeon_device *rdev,
539 const struct ci_pt_config_reg *cac_config_regs)
540{
541 const struct ci_pt_config_reg *config_regs = cac_config_regs;
542 u32 data;
543 u32 cache = 0;
544
545 if (config_regs == NULL)
546 return -EINVAL;
547
548 while (config_regs->offset != 0xFFFFFFFF) {
549 if (config_regs->type == CISLANDS_CONFIGREG_CACHE) {
550 cache |= ((config_regs->value << config_regs->shift) & config_regs->mask);
551 } else {
552 switch (config_regs->type) {
553 case CISLANDS_CONFIGREG_SMC_IND:
554 data = RREG32_SMC(config_regs->offset);
555 break;
556 case CISLANDS_CONFIGREG_DIDT_IND:
557 data = RREG32_DIDT(config_regs->offset);
558 break;
559 default:
560 data = RREG32(config_regs->offset << 2);
561 break;
562 }
563
564 data &= ~config_regs->mask;
565 data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
566 data |= cache;
567
568 switch (config_regs->type) {
569 case CISLANDS_CONFIGREG_SMC_IND:
570 WREG32_SMC(config_regs->offset, data);
571 break;
572 case CISLANDS_CONFIGREG_DIDT_IND:
573 WREG32_DIDT(config_regs->offset, data);
574 break;
575 default:
576 WREG32(config_regs->offset << 2, data);
577 break;
578 }
579 cache = 0;
580 }
581 config_regs++;
582 }
583 return 0;
584}
585
586static int ci_enable_didt(struct radeon_device *rdev, bool enable)
587{
588 struct ci_power_info *pi = ci_get_pi(rdev);
589 int ret;
590
591 if (pi->caps_sq_ramping || pi->caps_db_ramping ||
592 pi->caps_td_ramping || pi->caps_tcp_ramping) {
593 cik_enter_rlc_safe_mode(rdev);
594
595 if (enable) {
596 ret = ci_program_pt_config_registers(rdev, didt_config_ci);
597 if (ret) {
598 cik_exit_rlc_safe_mode(rdev);
599 return ret;
600 }
601 }
602
603 ci_do_enable_didt(rdev, enable);
604
605 cik_exit_rlc_safe_mode(rdev);
606 }
607
608 return 0;
609}
610
611static int ci_enable_power_containment(struct radeon_device *rdev, bool enable)
612{
613 struct ci_power_info *pi = ci_get_pi(rdev);
614 PPSMC_Result smc_result;
615 int ret = 0;
616
617 if (enable) {
618 pi->power_containment_features = 0;
619 if (pi->caps_power_containment) {
620 if (pi->enable_bapm_feature) {
621 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableDTE);
622 if (smc_result != PPSMC_Result_OK)
623 ret = -EINVAL;
624 else
625 pi->power_containment_features |= POWERCONTAINMENT_FEATURE_BAPM;
626 }
627
628 if (pi->enable_tdc_limit_feature) {
629 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_TDCLimitEnable);
630 if (smc_result != PPSMC_Result_OK)
631 ret = -EINVAL;
632 else
633 pi->power_containment_features |= POWERCONTAINMENT_FEATURE_TDCLimit;
634 }
635
636 if (pi->enable_pkg_pwr_tracking_feature) {
637 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_PkgPwrLimitEnable);
638 if (smc_result != PPSMC_Result_OK) {
639 ret = -EINVAL;
640 } else {
641 struct radeon_cac_tdp_table *cac_tdp_table =
642 rdev->pm.dpm.dyn_state.cac_tdp_table;
643 u32 default_pwr_limit =
644 (u32)(cac_tdp_table->maximum_power_delivery_limit * 256);
645
646 pi->power_containment_features |= POWERCONTAINMENT_FEATURE_PkgPwrLimit;
647
648 ci_set_power_limit(rdev, default_pwr_limit);
649 }
650 }
651 }
652 } else {
653 if (pi->caps_power_containment && pi->power_containment_features) {
654 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_TDCLimit)
655 ci_send_msg_to_smc(rdev, PPSMC_MSG_TDCLimitDisable);
656
657 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_BAPM)
658 ci_send_msg_to_smc(rdev, PPSMC_MSG_DisableDTE);
659
660 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit)
661 ci_send_msg_to_smc(rdev, PPSMC_MSG_PkgPwrLimitDisable);
662 pi->power_containment_features = 0;
663 }
664 }
665
666 return ret;
667}
668
669static int ci_enable_smc_cac(struct radeon_device *rdev, bool enable)
670{
671 struct ci_power_info *pi = ci_get_pi(rdev);
672 PPSMC_Result smc_result;
673 int ret = 0;
674
675 if (pi->caps_cac) {
676 if (enable) {
677 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableCac);
678 if (smc_result != PPSMC_Result_OK) {
679 ret = -EINVAL;
680 pi->cac_enabled = false;
681 } else {
682 pi->cac_enabled = true;
683 }
684 } else if (pi->cac_enabled) {
685 ci_send_msg_to_smc(rdev, PPSMC_MSG_DisableCac);
686 pi->cac_enabled = false;
687 }
688 }
689
690 return ret;
691}
692
693static int ci_power_control_set_level(struct radeon_device *rdev)
694{
695 struct ci_power_info *pi = ci_get_pi(rdev);
696 struct radeon_cac_tdp_table *cac_tdp_table =
697 rdev->pm.dpm.dyn_state.cac_tdp_table;
698 s32 adjust_percent;
699 s32 target_tdp;
700 int ret = 0;
701 bool adjust_polarity = false; /* ??? */
702
703 if (pi->caps_power_containment &&
704 (pi->power_containment_features & POWERCONTAINMENT_FEATURE_BAPM)) {
705 adjust_percent = adjust_polarity ?
706 rdev->pm.dpm.tdp_adjustment : (-1 * rdev->pm.dpm.tdp_adjustment);
707 target_tdp = ((100 + adjust_percent) *
708 (s32)cac_tdp_table->configurable_tdp) / 100;
709 target_tdp *= 256;
710
711 ret = ci_set_overdrive_target_tdp(rdev, (u32)target_tdp);
712 }
713
714 return ret;
715}
716
942bdf7f 717void ci_dpm_powergate_uvd(struct radeon_device *rdev, bool gate)
cc8dbbb4 718{
47acb1ff
AD		 719 struct ci_power_info *pi = ci_get_pi(rdev);
720
721 if (pi->uvd_power_gated == gate)
722 return;
723
724 pi->uvd_power_gated = gate;
725
cc8dbbb4
AD		 726 ci_update_uvd_dpm(rdev, gate);
727}
728
5496131e
AD		 729bool ci_dpm_vblank_too_short(struct radeon_device *rdev)
730{
731 struct ci_power_info *pi = ci_get_pi(rdev);
732 u32 vblank_time = r600_dpm_get_vblank_time(rdev);
733 u32 switch_limit = pi->mem_gddr5 ? 450 : 300;
734
735 if (vblank_time < switch_limit)
736 return true;
737 else
738 return false;
739
740}
741
cc8dbbb4
AD		 742static void ci_apply_state_adjust_rules(struct radeon_device *rdev,
743 struct radeon_ps *rps)
744{
745 struct ci_ps *ps = ci_get_ps(rps);
746 struct ci_power_info *pi = ci_get_pi(rdev);
747 struct radeon_clock_and_voltage_limits *max_limits;
748 bool disable_mclk_switching;
749 u32 sclk, mclk;
750 int i;
751
8cd36682
AD		 752 if (rps->vce_active) {
753 rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk;
754 rps->ecclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].ecclk;
755 } else {
756 rps->evclk = 0;
757 rps->ecclk = 0;
758 }
759
5496131e
AD		 760 if ((rdev->pm.dpm.new_active_crtc_count > 1) ||
761 ci_dpm_vblank_too_short(rdev))
cc8dbbb4
AD		 762 disable_mclk_switching = true;
763 else
764 disable_mclk_switching = false;
765
766 if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY)
767 pi->battery_state = true;
768 else
769 pi->battery_state = false;
770
771 if (rdev->pm.dpm.ac_power)
772 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
773 else
774 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
775
776 if (rdev->pm.dpm.ac_power == false) {
777 for (i = 0; i < ps->performance_level_count; i++) {
778 if (ps->performance_levels[i].mclk > max_limits->mclk)
779 ps->performance_levels[i].mclk = max_limits->mclk;
780 if (ps->performance_levels[i].sclk > max_limits->sclk)
781 ps->performance_levels[i].sclk = max_limits->sclk;
782 }
783 }
784
785 /* XXX validate the min clocks required for display */
786
787 if (disable_mclk_switching) {
788 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk;
789 sclk = ps->performance_levels[0].sclk;
790 } else {
791 mclk = ps->performance_levels[0].mclk;
792 sclk = ps->performance_levels[0].sclk;
793 }
794
8cd36682
AD		 795 if (rps->vce_active) {
796 if (sclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk)
797 sclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk;
798 if (mclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk)
799 mclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk;
800 }
801
cc8dbbb4
AD		 802 ps->performance_levels[0].sclk = sclk;
803 ps->performance_levels[0].mclk = mclk;
804
805 if (ps->performance_levels[1].sclk < ps->performance_levels[0].sclk)
806 ps->performance_levels[1].sclk = ps->performance_levels[0].sclk;
807
808 if (disable_mclk_switching) {
809 if (ps->performance_levels[0].mclk < ps->performance_levels[1].mclk)
810 ps->performance_levels[0].mclk = ps->performance_levels[1].mclk;
811 } else {
812 if (ps->performance_levels[1].mclk < ps->performance_levels[0].mclk)
813 ps->performance_levels[1].mclk = ps->performance_levels[0].mclk;
814 }
815}
816
1955f107 817static int ci_thermal_set_temperature_range(struct radeon_device *rdev,
cc8dbbb4
AD		 818 int min_temp, int max_temp)
819{
820 int low_temp = 0 * 1000;
821 int high_temp = 255 * 1000;
822 u32 tmp;
823
824 if (low_temp < min_temp)
825 low_temp = min_temp;
826 if (high_temp > max_temp)
827 high_temp = max_temp;
828 if (high_temp < low_temp) {
829 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
830 return -EINVAL;
831 }
832
833 tmp = RREG32_SMC(CG_THERMAL_INT);
834 tmp &= ~(CI_DIG_THERM_INTH_MASK | CI_DIG_THERM_INTL_MASK);
835 tmp |= CI_DIG_THERM_INTH(high_temp / 1000) |
836 CI_DIG_THERM_INTL(low_temp / 1000);
837 WREG32_SMC(CG_THERMAL_INT, tmp);
838
839#if 0
840 /* XXX: need to figure out how to handle this properly */
841 tmp = RREG32_SMC(CG_THERMAL_CTRL);
842 tmp &= DIG_THERM_DPM_MASK;
843 tmp |= DIG_THERM_DPM(high_temp / 1000);
844 WREG32_SMC(CG_THERMAL_CTRL, tmp);
845#endif
846
6bce8d97
OC		 847 rdev->pm.dpm.thermal.min_temp = low_temp;
848 rdev->pm.dpm.thermal.max_temp = high_temp;
849
cc8dbbb4
AD		 850 return 0;
851}
852
1955f107
AD		 853static int ci_thermal_enable_alert(struct radeon_device *rdev,
854 bool enable)
855{
856 u32 thermal_int = RREG32_SMC(CG_THERMAL_INT);
857 PPSMC_Result result;
858
859 if (enable) {
860 thermal_int &= ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);
861 rdev->irq.dpm_thermal = false;
862 result = ci_send_msg_to_smc(rdev, PPSMC_MSG_Thermal_Cntl_Enable);
863 if (result != PPSMC_Result_OK) {
864 DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
865 return -EINVAL;
866 }
867 } else {
868 thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW;
869 rdev->irq.dpm_thermal = true;
870 result = ci_send_msg_to_smc(rdev, PPSMC_MSG_Thermal_Cntl_Disable);
871 if (result != PPSMC_Result_OK) {
872 DRM_DEBUG_KMS("Could not disable thermal interrupts.\n");
873 return -EINVAL;
874 }
875 }
876
877 WREG32_SMC(CG_THERMAL_INT, thermal_int);
878
879 return 0;
880}
881
cc8dbbb4
AD		 882#if 0
883static int ci_read_smc_soft_register(struct radeon_device *rdev,
884 u16 reg_offset, u32 *value)
885{
886 struct ci_power_info *pi = ci_get_pi(rdev);
887
888 return ci_read_smc_sram_dword(rdev,
889 pi->soft_regs_start + reg_offset,
890 value, pi->sram_end);
891}
892#endif
893
894static int ci_write_smc_soft_register(struct radeon_device *rdev,
895 u16 reg_offset, u32 value)
896{
897 struct ci_power_info *pi = ci_get_pi(rdev);
898
899 return ci_write_smc_sram_dword(rdev,
900 pi->soft_regs_start + reg_offset,
901 value, pi->sram_end);
902}
903
904static void ci_init_fps_limits(struct radeon_device *rdev)
905{
906 struct ci_power_info *pi = ci_get_pi(rdev);
907 SMU7_Discrete_DpmTable *table = &pi->smc_state_table;
908
909 if (pi->caps_fps) {
910 u16 tmp;
911
912 tmp = 45;
913 table->FpsHighT = cpu_to_be16(tmp);
914
915 tmp = 30;
916 table->FpsLowT = cpu_to_be16(tmp);
917 }
918}
919
920static int ci_update_sclk_t(struct radeon_device *rdev)
921{
922 struct ci_power_info *pi = ci_get_pi(rdev);
923 int ret = 0;
924 u32 low_sclk_interrupt_t = 0;
925
926 if (pi->caps_sclk_throttle_low_notification) {
927 low_sclk_interrupt_t = cpu_to_be32(pi->low_sclk_interrupt_t);
928
929 ret = ci_copy_bytes_to_smc(rdev,
930 pi->dpm_table_start +
931 offsetof(SMU7_Discrete_DpmTable, LowSclkInterruptT),
932 (u8 *)&low_sclk_interrupt_t,
933 sizeof(u32), pi->sram_end);
934
935 }
936
937 return ret;
938}
939
940static void ci_get_leakage_voltages(struct radeon_device *rdev)
941{
942 struct ci_power_info *pi = ci_get_pi(rdev);
943 u16 leakage_id, virtual_voltage_id;
944 u16 vddc, vddci;
945 int i;
946
947 pi->vddc_leakage.count = 0;
948 pi->vddci_leakage.count = 0;
949
6b57f20c
AD		 950 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) {
951 for (i = 0; i < CISLANDS_MAX_LEAKAGE_COUNT; i++) {
952 virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
953 if (radeon_atom_get_voltage_evv(rdev, virtual_voltage_id, &vddc) != 0)
954 continue;
955 if (vddc != 0 && vddc != virtual_voltage_id) {
956 pi->vddc_leakage.actual_voltage[pi->vddc_leakage.count] = vddc;
957 pi->vddc_leakage.leakage_id[pi->vddc_leakage.count] = virtual_voltage_id;
958 pi->vddc_leakage.count++;
959 }
960 }
961 } else if (radeon_atom_get_leakage_id_from_vbios(rdev, &leakage_id) == 0) {
cc8dbbb4
AD		 962 for (i = 0; i < CISLANDS_MAX_LEAKAGE_COUNT; i++) {
963 virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
964 if (radeon_atom_get_leakage_vddc_based_on_leakage_params(rdev, &vddc, &vddci,
965 virtual_voltage_id,
966 leakage_id) == 0) {
967 if (vddc != 0 && vddc != virtual_voltage_id) {
968 pi->vddc_leakage.actual_voltage[pi->vddc_leakage.count] = vddc;
969 pi->vddc_leakage.leakage_id[pi->vddc_leakage.count] = virtual_voltage_id;
970 pi->vddc_leakage.count++;
971 }
972 if (vddci != 0 && vddci != virtual_voltage_id) {
973 pi->vddci_leakage.actual_voltage[pi->vddci_leakage.count] = vddci;
974 pi->vddci_leakage.leakage_id[pi->vddci_leakage.count] = virtual_voltage_id;
975 pi->vddci_leakage.count++;
976 }
977 }
978 }
979 }
980}
981
982static void ci_set_dpm_event_sources(struct radeon_device *rdev, u32 sources)
983{
984 struct ci_power_info *pi = ci_get_pi(rdev);
985 bool want_thermal_protection;
986 enum radeon_dpm_event_src dpm_event_src;
987 u32 tmp;
988
989 switch (sources) {
990 case 0:
991 default:
992 want_thermal_protection = false;
993 break;
994 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL):
995 want_thermal_protection = true;
996 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGITAL;
997 break;
998 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL):
999 want_thermal_protection = true;
1000 dpm_event_src = RADEON_DPM_EVENT_SRC_EXTERNAL;
1001 break;
1002 case ((1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL) |
1003 (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL)):
1004 want_thermal_protection = true;
1005 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL;
1006 break;
1007 }
1008
1009 if (want_thermal_protection) {
1010#if 0
1011 /* XXX: need to figure out how to handle this properly */
1012 tmp = RREG32_SMC(CG_THERMAL_CTRL);
1013 tmp &= DPM_EVENT_SRC_MASK;
1014 tmp |= DPM_EVENT_SRC(dpm_event_src);
1015 WREG32_SMC(CG_THERMAL_CTRL, tmp);
1016#endif
1017
1018 tmp = RREG32_SMC(GENERAL_PWRMGT);
1019 if (pi->thermal_protection)
1020 tmp &= ~THERMAL_PROTECTION_DIS;
1021 else
1022 tmp |= THERMAL_PROTECTION_DIS;
1023 WREG32_SMC(GENERAL_PWRMGT, tmp);
1024 } else {
1025 tmp = RREG32_SMC(GENERAL_PWRMGT);
1026 tmp |= THERMAL_PROTECTION_DIS;
1027 WREG32_SMC(GENERAL_PWRMGT, tmp);
1028 }
1029}
1030
1031static void ci_enable_auto_throttle_source(struct radeon_device *rdev,
1032 enum radeon_dpm_auto_throttle_src source,
1033 bool enable)
1034{
1035 struct ci_power_info *pi = ci_get_pi(rdev);
1036
1037 if (enable) {
1038 if (!(pi->active_auto_throttle_sources & (1 << source))) {
1039 pi->active_auto_throttle_sources |= 1 << source;
1040 ci_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
1041 }
1042 } else {
1043 if (pi->active_auto_throttle_sources & (1 << source)) {
1044 pi->active_auto_throttle_sources &= ~(1 << source);
1045 ci_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
1046 }
1047 }
1048}
1049
1050static void ci_enable_vr_hot_gpio_interrupt(struct radeon_device *rdev)
1051{
1052 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT)
1053 ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableVRHotGPIOInterrupt);
1054}
1055
1056static int ci_unfreeze_sclk_mclk_dpm(struct radeon_device *rdev)
1057{
1058 struct ci_power_info *pi = ci_get_pi(rdev);
1059 PPSMC_Result smc_result;
1060
1061 if (!pi->need_update_smu7_dpm_table)
1062 return 0;
1063
1064 if ((!pi->sclk_dpm_key_disabled) &&
1065 (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) {
1066 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_SCLKDPM_UnfreezeLevel);
1067 if (smc_result != PPSMC_Result_OK)
1068 return -EINVAL;
1069 }
1070
1071 if ((!pi->mclk_dpm_key_disabled) &&
1072 (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
1073 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_UnfreezeLevel);
1074 if (smc_result != PPSMC_Result_OK)
1075 return -EINVAL;
1076 }
1077
1078 pi->need_update_smu7_dpm_table = 0;
1079 return 0;
1080}
1081
1082static int ci_enable_sclk_mclk_dpm(struct radeon_device *rdev, bool enable)
1083{
1084 struct ci_power_info *pi = ci_get_pi(rdev);
1085 PPSMC_Result smc_result;
1086
1087 if (enable) {
1088 if (!pi->sclk_dpm_key_disabled) {
1089 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_DPM_Enable);
1090 if (smc_result != PPSMC_Result_OK)
1091 return -EINVAL;
1092 }
1093
1094 if (!pi->mclk_dpm_key_disabled) {
1095 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_Enable);
1096 if (smc_result != PPSMC_Result_OK)
1097 return -EINVAL;
1098
1099 WREG32_P(MC_SEQ_CNTL_3, CAC_EN, ~CAC_EN);
1100
1101 WREG32_SMC(LCAC_MC0_CNTL, 0x05);
1102 WREG32_SMC(LCAC_MC1_CNTL, 0x05);
1103 WREG32_SMC(LCAC_CPL_CNTL, 0x100005);
1104
1105 udelay(10);
1106
1107 WREG32_SMC(LCAC_MC0_CNTL, 0x400005);
1108 WREG32_SMC(LCAC_MC1_CNTL, 0x400005);
1109 WREG32_SMC(LCAC_CPL_CNTL, 0x500005);
1110 }
1111 } else {
1112 if (!pi->sclk_dpm_key_disabled) {
1113 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_DPM_Disable);
1114 if (smc_result != PPSMC_Result_OK)
1115 return -EINVAL;
1116 }
1117
1118 if (!pi->mclk_dpm_key_disabled) {
1119 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_Disable);
1120 if (smc_result != PPSMC_Result_OK)
1121 return -EINVAL;
1122 }
1123 }
1124
1125 return 0;
1126}
1127
1128static int ci_start_dpm(struct radeon_device *rdev)
1129{
1130 struct ci_power_info *pi = ci_get_pi(rdev);
1131 PPSMC_Result smc_result;
1132 int ret;
1133 u32 tmp;
1134
1135 tmp = RREG32_SMC(GENERAL_PWRMGT);
1136 tmp |= GLOBAL_PWRMGT_EN;
1137 WREG32_SMC(GENERAL_PWRMGT, tmp);
1138
1139 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
1140 tmp |= DYNAMIC_PM_EN;
1141 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
1142
1143 ci_write_smc_soft_register(rdev, offsetof(SMU7_SoftRegisters, VoltageChangeTimeout), 0x1000);
1144
1145 WREG32_P(BIF_LNCNT_RESET, 0, ~RESET_LNCNT_EN);
1146
1147 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_Voltage_Cntl_Enable);
1148 if (smc_result != PPSMC_Result_OK)
1149 return -EINVAL;
1150
1151 ret = ci_enable_sclk_mclk_dpm(rdev, true);
1152 if (ret)
1153 return ret;
1154
1155 if (!pi->pcie_dpm_key_disabled) {
1156 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_PCIeDPM_Enable);
1157 if (smc_result != PPSMC_Result_OK)
1158 return -EINVAL;
1159 }
1160
1161 return 0;
1162}
1163
1164static int ci_freeze_sclk_mclk_dpm(struct radeon_device *rdev)
1165{
1166 struct ci_power_info *pi = ci_get_pi(rdev);
1167 PPSMC_Result smc_result;
1168
1169 if (!pi->need_update_smu7_dpm_table)
1170 return 0;
1171
1172 if ((!pi->sclk_dpm_key_disabled) &&
1173 (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) {
1174 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_SCLKDPM_FreezeLevel);
1175 if (smc_result != PPSMC_Result_OK)
1176 return -EINVAL;
1177 }
1178
1179 if ((!pi->mclk_dpm_key_disabled) &&
1180 (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
1181 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_FreezeLevel);
1182 if (smc_result != PPSMC_Result_OK)
1183 return -EINVAL;
1184 }
1185
1186 return 0;
1187}
1188
1189static int ci_stop_dpm(struct radeon_device *rdev)
1190{
1191 struct ci_power_info *pi = ci_get_pi(rdev);
1192 PPSMC_Result smc_result;
1193 int ret;
1194 u32 tmp;
1195
1196 tmp = RREG32_SMC(GENERAL_PWRMGT);
1197 tmp &= ~GLOBAL_PWRMGT_EN;
1198 WREG32_SMC(GENERAL_PWRMGT, tmp);
1199
ed963771 1200 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
cc8dbbb4
AD		 1201 tmp &= ~DYNAMIC_PM_EN;
1202 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
1203
1204 if (!pi->pcie_dpm_key_disabled) {
1205 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_PCIeDPM_Disable);
1206 if (smc_result != PPSMC_Result_OK)
1207 return -EINVAL;
1208 }
1209
1210 ret = ci_enable_sclk_mclk_dpm(rdev, false);
1211 if (ret)
1212 return ret;
1213
1214 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_Voltage_Cntl_Disable);
1215 if (smc_result != PPSMC_Result_OK)
1216 return -EINVAL;
1217
1218 return 0;
1219}
1220
1221static void ci_enable_sclk_control(struct radeon_device *rdev, bool enable)
1222{
1223 u32 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
1224
1225 if (enable)
1226 tmp &= ~SCLK_PWRMGT_OFF;
1227 else
1228 tmp |= SCLK_PWRMGT_OFF;
1229 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
1230}
1231
1232#if 0
1233static int ci_notify_hw_of_power_source(struct radeon_device *rdev,
1234 bool ac_power)
1235{
1236 struct ci_power_info *pi = ci_get_pi(rdev);
1237 struct radeon_cac_tdp_table *cac_tdp_table =
1238 rdev->pm.dpm.dyn_state.cac_tdp_table;
1239 u32 power_limit;
1240
1241 if (ac_power)
1242 power_limit = (u32)(cac_tdp_table->maximum_power_delivery_limit * 256);
1243 else
1244 power_limit = (u32)(cac_tdp_table->battery_power_limit * 256);
1245
1246 ci_set_power_limit(rdev, power_limit);
1247
1248 if (pi->caps_automatic_dc_transition) {
1249 if (ac_power)
1250 ci_send_msg_to_smc(rdev, PPSMC_MSG_RunningOnAC);
1251 else
1252 ci_send_msg_to_smc(rdev, PPSMC_MSG_Remove_DC_Clamp);
1253 }
1254
1255 return 0;
1256}
1257#endif
1258
1259static PPSMC_Result ci_send_msg_to_smc_with_parameter(struct radeon_device *rdev,
1260 PPSMC_Msg msg, u32 parameter)
1261{
1262 WREG32(SMC_MSG_ARG_0, parameter);
1263 return ci_send_msg_to_smc(rdev, msg);
1264}
1265
1266static PPSMC_Result ci_send_msg_to_smc_return_parameter(struct radeon_device *rdev,
1267 PPSMC_Msg msg, u32 *parameter)
1268{
1269 PPSMC_Result smc_result;
1270
1271 smc_result = ci_send_msg_to_smc(rdev, msg);
1272
1273 if ((smc_result == PPSMC_Result_OK) && parameter)
1274 *parameter = RREG32(SMC_MSG_ARG_0);
1275
1276 return smc_result;
1277}
1278
1279static int ci_dpm_force_state_sclk(struct radeon_device *rdev, u32 n)
1280{
1281 struct ci_power_info *pi = ci_get_pi(rdev);
1282
1283 if (!pi->sclk_dpm_key_disabled) {
1284 PPSMC_Result smc_result =
1c52279f 1285 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SCLKDPM_SetEnabledMask, 1 << n);
cc8dbbb4
AD		 1286 if (smc_result != PPSMC_Result_OK)
1287 return -EINVAL;
1288 }
1289
1290 return 0;
1291}
1292
1293static int ci_dpm_force_state_mclk(struct radeon_device *rdev, u32 n)
1294{
1295 struct ci_power_info *pi = ci_get_pi(rdev);
1296
1297 if (!pi->mclk_dpm_key_disabled) {
1298 PPSMC_Result smc_result =
1c52279f 1299 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_MCLKDPM_SetEnabledMask, 1 << n);
cc8dbbb4
AD		 1300 if (smc_result != PPSMC_Result_OK)
1301 return -EINVAL;
1302 }
1303
1304 return 0;
1305}
1306
1307static int ci_dpm_force_state_pcie(struct radeon_device *rdev, u32 n)
1308{
1309 struct ci_power_info *pi = ci_get_pi(rdev);
1310
1311 if (!pi->pcie_dpm_key_disabled) {
1312 PPSMC_Result smc_result =
1313 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_PCIeDPM_ForceLevel, n);
1314 if (smc_result != PPSMC_Result_OK)
1315 return -EINVAL;
1316 }
1317
1318 return 0;
1319}
1320
1321static int ci_set_power_limit(struct radeon_device *rdev, u32 n)
1322{
1323 struct ci_power_info *pi = ci_get_pi(rdev);
1324
1325 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit) {
1326 PPSMC_Result smc_result =
1327 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_PkgPwrSetLimit, n);
1328 if (smc_result != PPSMC_Result_OK)
1329 return -EINVAL;
1330 }
1331
1332 return 0;
1333}
1334
1335static int ci_set_overdrive_target_tdp(struct radeon_device *rdev,
1336 u32 target_tdp)
1337{
1338 PPSMC_Result smc_result =
1339 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_OverDriveSetTargetTdp, target_tdp);
1340 if (smc_result != PPSMC_Result_OK)
1341 return -EINVAL;
1342 return 0;
1343}
1344
1345static int ci_set_boot_state(struct radeon_device *rdev)
1346{
1347 return ci_enable_sclk_mclk_dpm(rdev, false);
1348}
1349
1350static u32 ci_get_average_sclk_freq(struct radeon_device *rdev)
1351{
1352 u32 sclk_freq;
1353 PPSMC_Result smc_result =
1354 ci_send_msg_to_smc_return_parameter(rdev,
1355 PPSMC_MSG_API_GetSclkFrequency,
1356 &sclk_freq);
1357 if (smc_result != PPSMC_Result_OK)
1358 sclk_freq = 0;
1359
1360 return sclk_freq;
1361}
1362
1363static u32 ci_get_average_mclk_freq(struct radeon_device *rdev)
1364{
1365 u32 mclk_freq;
1366 PPSMC_Result smc_result =
1367 ci_send_msg_to_smc_return_parameter(rdev,
1368 PPSMC_MSG_API_GetMclkFrequency,
1369 &mclk_freq);
1370 if (smc_result != PPSMC_Result_OK)
1371 mclk_freq = 0;
1372
1373 return mclk_freq;
1374}
1375
1376static void ci_dpm_start_smc(struct radeon_device *rdev)
1377{
1378 int i;
1379
1380 ci_program_jump_on_start(rdev);
1381 ci_start_smc_clock(rdev);
1382 ci_start_smc(rdev);
1383 for (i = 0; i < rdev->usec_timeout; i++) {
1384 if (RREG32_SMC(FIRMWARE_FLAGS) & INTERRUPTS_ENABLED)
1385 break;
1386 }
1387}
1388
1389static void ci_dpm_stop_smc(struct radeon_device *rdev)
1390{
1391 ci_reset_smc(rdev);
1392 ci_stop_smc_clock(rdev);
1393}
1394
1395static int ci_process_firmware_header(struct radeon_device *rdev)
1396{
1397 struct ci_power_info *pi = ci_get_pi(rdev);
1398 u32 tmp;
1399 int ret;
1400
1401 ret = ci_read_smc_sram_dword(rdev,
1402 SMU7_FIRMWARE_HEADER_LOCATION +
1403 offsetof(SMU7_Firmware_Header, DpmTable),
1404 &tmp, pi->sram_end);
1405 if (ret)
1406 return ret;
1407
1408 pi->dpm_table_start = tmp;
1409
1410 ret = ci_read_smc_sram_dword(rdev,
1411 SMU7_FIRMWARE_HEADER_LOCATION +
1412 offsetof(SMU7_Firmware_Header, SoftRegisters),
1413 &tmp, pi->sram_end);
1414 if (ret)
1415 return ret;
1416
1417 pi->soft_regs_start = tmp;
1418
1419 ret = ci_read_smc_sram_dword(rdev,
1420 SMU7_FIRMWARE_HEADER_LOCATION +
1421 offsetof(SMU7_Firmware_Header, mcRegisterTable),
1422 &tmp, pi->sram_end);
1423 if (ret)
1424 return ret;
1425
1426 pi->mc_reg_table_start = tmp;
1427
1428 ret = ci_read_smc_sram_dword(rdev,
1429 SMU7_FIRMWARE_HEADER_LOCATION +
1430 offsetof(SMU7_Firmware_Header, FanTable),
1431 &tmp, pi->sram_end);
1432 if (ret)
1433 return ret;
1434
1435 pi->fan_table_start = tmp;
1436
1437 ret = ci_read_smc_sram_dword(rdev,
1438 SMU7_FIRMWARE_HEADER_LOCATION +
1439 offsetof(SMU7_Firmware_Header, mcArbDramTimingTable),
1440 &tmp, pi->sram_end);
1441 if (ret)
1442 return ret;
1443
1444 pi->arb_table_start = tmp;
1445
1446 return 0;
1447}
1448
1449static void ci_read_clock_registers(struct radeon_device *rdev)
1450{
1451 struct ci_power_info *pi = ci_get_pi(rdev);
1452
1453 pi->clock_registers.cg_spll_func_cntl =
1454 RREG32_SMC(CG_SPLL_FUNC_CNTL);
1455 pi->clock_registers.cg_spll_func_cntl_2 =
1456 RREG32_SMC(CG_SPLL_FUNC_CNTL_2);
1457 pi->clock_registers.cg_spll_func_cntl_3 =
1458 RREG32_SMC(CG_SPLL_FUNC_CNTL_3);
1459 pi->clock_registers.cg_spll_func_cntl_4 =
1460 RREG32_SMC(CG_SPLL_FUNC_CNTL_4);
1461 pi->clock_registers.cg_spll_spread_spectrum =
1462 RREG32_SMC(CG_SPLL_SPREAD_SPECTRUM);
1463 pi->clock_registers.cg_spll_spread_spectrum_2 =
1464 RREG32_SMC(CG_SPLL_SPREAD_SPECTRUM_2);
1465 pi->clock_registers.dll_cntl = RREG32(DLL_CNTL);
1466 pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL);
1467 pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL);
1468 pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL);
1469 pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL);
1470 pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1);
1471 pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2);
1472 pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);
1473 pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2);
1474}
1475
1476static void ci_init_sclk_t(struct radeon_device *rdev)
1477{
1478 struct ci_power_info *pi = ci_get_pi(rdev);
1479
1480 pi->low_sclk_interrupt_t = 0;
1481}
1482
1483static void ci_enable_thermal_protection(struct radeon_device *rdev,
1484 bool enable)
1485{
1486 u32 tmp = RREG32_SMC(GENERAL_PWRMGT);
1487
1488 if (enable)
1489 tmp &= ~THERMAL_PROTECTION_DIS;
1490 else
1491 tmp |= THERMAL_PROTECTION_DIS;
1492 WREG32_SMC(GENERAL_PWRMGT, tmp);
1493}
1494
1495static void ci_enable_acpi_power_management(struct radeon_device *rdev)
1496{
1497 u32 tmp = RREG32_SMC(GENERAL_PWRMGT);
1498
1499 tmp |= STATIC_PM_EN;
1500
1501 WREG32_SMC(GENERAL_PWRMGT, tmp);
1502}
1503
1504#if 0
1505static int ci_enter_ulp_state(struct radeon_device *rdev)
1506{
1507
1508 WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower);
1509
1510 udelay(25000);
1511
1512 return 0;
1513}
1514
1515static int ci_exit_ulp_state(struct radeon_device *rdev)
1516{
1517 int i;
1518
1519 WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower);
1520
1521 udelay(7000);
1522
1523 for (i = 0; i < rdev->usec_timeout; i++) {
1524 if (RREG32(SMC_RESP_0) == 1)
1525 break;
1526 udelay(1000);
1527 }
1528
1529 return 0;
1530}
1531#endif
1532
1533static int ci_notify_smc_display_change(struct radeon_device *rdev,
1534 bool has_display)
1535{
1536 PPSMC_Msg msg = has_display ? PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay;
1537
1538 return (ci_send_msg_to_smc(rdev, msg) == PPSMC_Result_OK) ? 0 : -EINVAL;
1539}
1540
1541static int ci_enable_ds_master_switch(struct radeon_device *rdev,
1542 bool enable)
1543{
1544 struct ci_power_info *pi = ci_get_pi(rdev);
1545
1546 if (enable) {
1547 if (pi->caps_sclk_ds) {
1548 if (ci_send_msg_to_smc(rdev, PPSMC_MSG_MASTER_DeepSleep_ON) != PPSMC_Result_OK)
1549 return -EINVAL;
1550 } else {
1551 if (ci_send_msg_to_smc(rdev, PPSMC_MSG_MASTER_DeepSleep_OFF) != PPSMC_Result_OK)
1552 return -EINVAL;
1553 }
1554 } else {
1555 if (pi->caps_sclk_ds) {
1556 if (ci_send_msg_to_smc(rdev, PPSMC_MSG_MASTER_DeepSleep_OFF) != PPSMC_Result_OK)
1557 return -EINVAL;
1558 }
1559 }
1560
1561 return 0;
1562}
1563
1564static void ci_program_display_gap(struct radeon_device *rdev)
1565{
1566 u32 tmp = RREG32_SMC(CG_DISPLAY_GAP_CNTL);
1567 u32 pre_vbi_time_in_us;
1568 u32 frame_time_in_us;
1569 u32 ref_clock = rdev->clock.spll.reference_freq;
1570 u32 refresh_rate = r600_dpm_get_vrefresh(rdev);
1571 u32 vblank_time = r600_dpm_get_vblank_time(rdev);
1572
1573 tmp &= ~DISP_GAP_MASK;
1574 if (rdev->pm.dpm.new_active_crtc_count > 0)
1575 tmp |= DISP_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
1576 else
1577 tmp |= DISP_GAP(R600_PM_DISPLAY_GAP_IGNORE);
1578 WREG32_SMC(CG_DISPLAY_GAP_CNTL, tmp);
1579
1580 if (refresh_rate == 0)
1581 refresh_rate = 60;
1582 if (vblank_time == 0xffffffff)
1583 vblank_time = 500;
1584 frame_time_in_us = 1000000 / refresh_rate;
1585 pre_vbi_time_in_us =
1586 frame_time_in_us - 200 - vblank_time;
1587 tmp = pre_vbi_time_in_us * (ref_clock / 100);
1588
1589 WREG32_SMC(CG_DISPLAY_GAP_CNTL2, tmp);
1590 ci_write_smc_soft_register(rdev, offsetof(SMU7_SoftRegisters, PreVBlankGap), 0x64);
1591 ci_write_smc_soft_register(rdev, offsetof(SMU7_SoftRegisters, VBlankTimeout), (frame_time_in_us - pre_vbi_time_in_us));
1592
1593
1594 ci_notify_smc_display_change(rdev, (rdev->pm.dpm.new_active_crtc_count == 1));
1595
1596}
1597
1598static void ci_enable_spread_spectrum(struct radeon_device *rdev, bool enable)
1599{
1600 struct ci_power_info *pi = ci_get_pi(rdev);
1601 u32 tmp;
1602
1603 if (enable) {
1604 if (pi->caps_sclk_ss_support) {
1605 tmp = RREG32_SMC(GENERAL_PWRMGT);
1606 tmp |= DYN_SPREAD_SPECTRUM_EN;
1607 WREG32_SMC(GENERAL_PWRMGT, tmp);
1608 }
1609 } else {
1610 tmp = RREG32_SMC(CG_SPLL_SPREAD_SPECTRUM);
1611 tmp &= ~SSEN;
1612 WREG32_SMC(CG_SPLL_SPREAD_SPECTRUM, tmp);
1613
1614 tmp = RREG32_SMC(GENERAL_PWRMGT);
1615 tmp &= ~DYN_SPREAD_SPECTRUM_EN;
1616 WREG32_SMC(GENERAL_PWRMGT, tmp);
1617 }
1618}
1619
1620static void ci_program_sstp(struct radeon_device *rdev)
1621{
1622 WREG32_SMC(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT)));
1623}
1624
1625static void ci_enable_display_gap(struct radeon_device *rdev)
1626{
1627 u32 tmp = RREG32_SMC(CG_DISPLAY_GAP_CNTL);
1628
1629 tmp &= ~(DISP_GAP_MASK | DISP_GAP_MCHG_MASK);
1630 tmp |= (DISP_GAP(R600_PM_DISPLAY_GAP_IGNORE) |
1631 DISP_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK));
1632
1633 WREG32_SMC(CG_DISPLAY_GAP_CNTL, tmp);
1634}
1635
1636static void ci_program_vc(struct radeon_device *rdev)
1637{
1638 u32 tmp;
1639
1640 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
1641 tmp &= ~(RESET_SCLK_CNT | RESET_BUSY_CNT);
1642 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
1643
1644 WREG32_SMC(CG_FTV_0, CISLANDS_VRC_DFLT0);
1645 WREG32_SMC(CG_FTV_1, CISLANDS_VRC_DFLT1);
1646 WREG32_SMC(CG_FTV_2, CISLANDS_VRC_DFLT2);
1647 WREG32_SMC(CG_FTV_3, CISLANDS_VRC_DFLT3);
1648 WREG32_SMC(CG_FTV_4, CISLANDS_VRC_DFLT4);
1649 WREG32_SMC(CG_FTV_5, CISLANDS_VRC_DFLT5);
1650 WREG32_SMC(CG_FTV_6, CISLANDS_VRC_DFLT6);
1651 WREG32_SMC(CG_FTV_7, CISLANDS_VRC_DFLT7);
1652}
1653
1654static void ci_clear_vc(struct radeon_device *rdev)
1655{
1656 u32 tmp;
1657
1658 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
1659 tmp |= (RESET_SCLK_CNT | RESET_BUSY_CNT);
1660 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
1661
1662 WREG32_SMC(CG_FTV_0, 0);
1663 WREG32_SMC(CG_FTV_1, 0);
1664 WREG32_SMC(CG_FTV_2, 0);
1665 WREG32_SMC(CG_FTV_3, 0);
1666 WREG32_SMC(CG_FTV_4, 0);
1667 WREG32_SMC(CG_FTV_5, 0);
1668 WREG32_SMC(CG_FTV_6, 0);
1669 WREG32_SMC(CG_FTV_7, 0);
1670}
1671
1672static int ci_upload_firmware(struct radeon_device *rdev)
1673{
1674 struct ci_power_info *pi = ci_get_pi(rdev);
1675 int i, ret;
1676
1677 for (i = 0; i < rdev->usec_timeout; i++) {
1678 if (RREG32_SMC(RCU_UC_EVENTS) & BOOT_SEQ_DONE)
1679 break;
1680 }
1681 WREG32_SMC(SMC_SYSCON_MISC_CNTL, 1);
1682
1683 ci_stop_smc_clock(rdev);
1684 ci_reset_smc(rdev);
1685
1686 ret = ci_load_smc_ucode(rdev, pi->sram_end);
1687
1688 return ret;
1689
1690}
1691
1692static int ci_get_svi2_voltage_table(struct radeon_device *rdev,
1693 struct radeon_clock_voltage_dependency_table *voltage_dependency_table,
1694 struct atom_voltage_table *voltage_table)
1695{
1696 u32 i;
1697
1698 if (voltage_dependency_table == NULL)
1699 return -EINVAL;
1700
1701 voltage_table->mask_low = 0;
1702 voltage_table->phase_delay = 0;
1703
1704 voltage_table->count = voltage_dependency_table->count;
1705 for (i = 0; i < voltage_table->count; i++) {
1706 voltage_table->entries[i].value = voltage_dependency_table->entries[i].v;
1707 voltage_table->entries[i].smio_low = 0;
1708 }
1709
1710 return 0;
1711}
1712
1713static int ci_construct_voltage_tables(struct radeon_device *rdev)
1714{
1715 struct ci_power_info *pi = ci_get_pi(rdev);
1716 int ret;
1717
1718 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) {
1719 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC,
1720 VOLTAGE_OBJ_GPIO_LUT,
1721 &pi->vddc_voltage_table);
1722 if (ret)
1723 return ret;
1724 } else if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
1725 ret = ci_get_svi2_voltage_table(rdev,
1726 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
1727 &pi->vddc_voltage_table);
1728 if (ret)
1729 return ret;
1730 }
1731
1732 if (pi->vddc_voltage_table.count > SMU7_MAX_LEVELS_VDDC)
1733 si_trim_voltage_table_to_fit_state_table(rdev, SMU7_MAX_LEVELS_VDDC,
1734 &pi->vddc_voltage_table);
1735
1736 if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) {
1737 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDCI,
1738 VOLTAGE_OBJ_GPIO_LUT,
1739 &pi->vddci_voltage_table);
1740 if (ret)
1741 return ret;
1742 } else if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
1743 ret = ci_get_svi2_voltage_table(rdev,
1744 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
1745 &pi->vddci_voltage_table);
1746 if (ret)
1747 return ret;
1748 }
1749
1750 if (pi->vddci_voltage_table.count > SMU7_MAX_LEVELS_VDDCI)
1751 si_trim_voltage_table_to_fit_state_table(rdev, SMU7_MAX_LEVELS_VDDCI,
1752 &pi->vddci_voltage_table);
1753
1754 if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) {
1755 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_MVDDC,
1756 VOLTAGE_OBJ_GPIO_LUT,
1757 &pi->mvdd_voltage_table);
1758 if (ret)
1759 return ret;
1760 } else if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
1761 ret = ci_get_svi2_voltage_table(rdev,
1762 &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk,
1763 &pi->mvdd_voltage_table);
1764 if (ret)
1765 return ret;
1766 }
1767
1768 if (pi->mvdd_voltage_table.count > SMU7_MAX_LEVELS_MVDD)
1769 si_trim_voltage_table_to_fit_state_table(rdev, SMU7_MAX_LEVELS_MVDD,
1770 &pi->mvdd_voltage_table);
1771
1772 return 0;
1773}
1774
1775static void ci_populate_smc_voltage_table(struct radeon_device *rdev,
1776 struct atom_voltage_table_entry *voltage_table,
1777 SMU7_Discrete_VoltageLevel *smc_voltage_table)
1778{
1779 int ret;
1780
1781 ret = ci_get_std_voltage_value_sidd(rdev, voltage_table,
1782 &smc_voltage_table->StdVoltageHiSidd,
1783 &smc_voltage_table->StdVoltageLoSidd);
1784
1785 if (ret) {
1786 smc_voltage_table->StdVoltageHiSidd = voltage_table->value * VOLTAGE_SCALE;
1787 smc_voltage_table->StdVoltageLoSidd = voltage_table->value * VOLTAGE_SCALE;
1788 }
1789
1790 smc_voltage_table->Voltage = cpu_to_be16(voltage_table->value * VOLTAGE_SCALE);
1791 smc_voltage_table->StdVoltageHiSidd =
1792 cpu_to_be16(smc_voltage_table->StdVoltageHiSidd);
1793 smc_voltage_table->StdVoltageLoSidd =
1794 cpu_to_be16(smc_voltage_table->StdVoltageLoSidd);
1795}
1796
1797static int ci_populate_smc_vddc_table(struct radeon_device *rdev,
1798 SMU7_Discrete_DpmTable *table)
1799{
1800 struct ci_power_info *pi = ci_get_pi(rdev);
1801 unsigned int count;
1802
1803 table->VddcLevelCount = pi->vddc_voltage_table.count;
1804 for (count = 0; count < table->VddcLevelCount; count++) {
1805 ci_populate_smc_voltage_table(rdev,
1806 &pi->vddc_voltage_table.entries[count],
1807 &table->VddcLevel[count]);
1808
1809 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO)
1810 table->VddcLevel[count].Smio |=
1811 pi->vddc_voltage_table.entries[count].smio_low;
1812 else
1813 table->VddcLevel[count].Smio = 0;
1814 }
1815 table->VddcLevelCount = cpu_to_be32(table->VddcLevelCount);
1816
1817 return 0;
1818}
1819
1820static int ci_populate_smc_vddci_table(struct radeon_device *rdev,
1821 SMU7_Discrete_DpmTable *table)
1822{
1823 unsigned int count;
1824 struct ci_power_info *pi = ci_get_pi(rdev);
1825
1826 table->VddciLevelCount = pi->vddci_voltage_table.count;
1827 for (count = 0; count < table->VddciLevelCount; count++) {
1828 ci_populate_smc_voltage_table(rdev,
1829 &pi->vddci_voltage_table.entries[count],
1830 &table->VddciLevel[count]);
1831
1832 if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO)
1833 table->VddciLevel[count].Smio |=
1834 pi->vddci_voltage_table.entries[count].smio_low;
1835 else
1836 table->VddciLevel[count].Smio = 0;
1837 }
1838 table->VddciLevelCount = cpu_to_be32(table->VddciLevelCount);
1839
1840 return 0;
1841}
1842
1843static int ci_populate_smc_mvdd_table(struct radeon_device *rdev,
1844 SMU7_Discrete_DpmTable *table)
1845{
1846 struct ci_power_info *pi = ci_get_pi(rdev);
1847 unsigned int count;
1848
1849 table->MvddLevelCount = pi->mvdd_voltage_table.count;
1850 for (count = 0; count < table->MvddLevelCount; count++) {
1851 ci_populate_smc_voltage_table(rdev,
1852 &pi->mvdd_voltage_table.entries[count],
1853 &table->MvddLevel[count]);
1854
1855 if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO)
1856 table->MvddLevel[count].Smio |=
1857 pi->mvdd_voltage_table.entries[count].smio_low;
1858 else
1859 table->MvddLevel[count].Smio = 0;
1860 }
1861 table->MvddLevelCount = cpu_to_be32(table->MvddLevelCount);
1862
1863 return 0;
1864}
1865
1866static int ci_populate_smc_voltage_tables(struct radeon_device *rdev,
1867 SMU7_Discrete_DpmTable *table)
1868{
1869 int ret;
1870
1871 ret = ci_populate_smc_vddc_table(rdev, table);
1872 if (ret)
1873 return ret;
1874
1875 ret = ci_populate_smc_vddci_table(rdev, table);
1876 if (ret)
1877 return ret;
1878
1879 ret = ci_populate_smc_mvdd_table(rdev, table);
1880 if (ret)
1881 return ret;
1882
1883 return 0;
1884}
1885
1886static int ci_populate_mvdd_value(struct radeon_device *rdev, u32 mclk,
1887 SMU7_Discrete_VoltageLevel *voltage)
1888{
1889 struct ci_power_info *pi = ci_get_pi(rdev);
1890 u32 i = 0;
1891
1892 if (pi->mvdd_control != CISLANDS_VOLTAGE_CONTROL_NONE) {
1893 for (i = 0; i < rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count; i++) {
1894 if (mclk <= rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries[i].clk) {
1895 voltage->Voltage = pi->mvdd_voltage_table.entries[i].value;
1896 break;
1897 }
1898 }
1899
1900 if (i >= rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count)
1901 return -EINVAL;
1902 }
1903
1904 return -EINVAL;
1905}
1906
1907static int ci_get_std_voltage_value_sidd(struct radeon_device *rdev,
1908 struct atom_voltage_table_entry *voltage_table,
1909 u16 *std_voltage_hi_sidd, u16 *std_voltage_lo_sidd)
1910{
1911 u16 v_index, idx;
1912 bool voltage_found = false;
1913 *std_voltage_hi_sidd = voltage_table->value * VOLTAGE_SCALE;
1914 *std_voltage_lo_sidd = voltage_table->value * VOLTAGE_SCALE;
1915
1916 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL)
1917 return -EINVAL;
1918
1919 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) {
1920 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
1921 if (voltage_table->value ==
1922 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
1923 voltage_found = true;
1924 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
1925 idx = v_index;
1926 else
1927 idx = rdev->pm.dpm.dyn_state.cac_leakage_table.count - 1;
1928 *std_voltage_lo_sidd =
1929 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].vddc * VOLTAGE_SCALE;
1930 *std_voltage_hi_sidd =
1931 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].leakage * VOLTAGE_SCALE;
1932 break;
1933 }
1934 }
1935
1936 if (!voltage_found) {
1937 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
1938 if (voltage_table->value <=
1939 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
1940 voltage_found = true;
1941 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
1942 idx = v_index;
1943 else
1944 idx = rdev->pm.dpm.dyn_state.cac_leakage_table.count - 1;
1945 *std_voltage_lo_sidd =
1946 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].vddc * VOLTAGE_SCALE;
1947 *std_voltage_hi_sidd =
1948 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].leakage * VOLTAGE_SCALE;
1949 break;
1950 }
1951 }
1952 }
1953 }
1954
1955 return 0;
1956}
1957
1958static void ci_populate_phase_value_based_on_sclk(struct radeon_device *rdev,
1959 const struct radeon_phase_shedding_limits_table *limits,
1960 u32 sclk,
1961 u32 *phase_shedding)
1962{
1963 unsigned int i;
1964
1965 *phase_shedding = 1;
1966
1967 for (i = 0; i < limits->count; i++) {
1968 if (sclk < limits->entries[i].sclk) {
1969 *phase_shedding = i;
1970 break;
1971 }
1972 }
1973}
1974
1975static void ci_populate_phase_value_based_on_mclk(struct radeon_device *rdev,
1976 const struct radeon_phase_shedding_limits_table *limits,
1977 u32 mclk,
1978 u32 *phase_shedding)
1979{
1980 unsigned int i;
1981
1982 *phase_shedding = 1;
1983
1984 for (i = 0; i < limits->count; i++) {
1985 if (mclk < limits->entries[i].mclk) {
1986 *phase_shedding = i;
1987 break;
1988 }
1989 }
1990}
1991
1992static int ci_init_arb_table_index(struct radeon_device *rdev)
1993{
1994 struct ci_power_info *pi = ci_get_pi(rdev);
1995 u32 tmp;
1996 int ret;
1997
1998 ret = ci_read_smc_sram_dword(rdev, pi->arb_table_start,
1999 &tmp, pi->sram_end);
2000 if (ret)
2001 return ret;
2002
2003 tmp &= 0x00FFFFFF;
2004 tmp |= MC_CG_ARB_FREQ_F1 << 24;
2005
2006 return ci_write_smc_sram_dword(rdev, pi->arb_table_start,
2007 tmp, pi->sram_end);
2008}
2009
2010static int ci_get_dependency_volt_by_clk(struct radeon_device *rdev,
2011 struct radeon_clock_voltage_dependency_table *allowed_clock_voltage_table,
2012 u32 clock, u32 *voltage)
2013{
2014 u32 i = 0;
2015
2016 if (allowed_clock_voltage_table->count == 0)
2017 return -EINVAL;
2018
2019 for (i = 0; i < allowed_clock_voltage_table->count; i++) {
2020 if (allowed_clock_voltage_table->entries[i].clk >= clock) {
2021 *voltage = allowed_clock_voltage_table->entries[i].v;
2022 return 0;
2023 }
2024 }
2025
2026 *voltage = allowed_clock_voltage_table->entries[i-1].v;
2027
2028 return 0;
2029}
2030
2031static u8 ci_get_sleep_divider_id_from_clock(struct radeon_device *rdev,
2032 u32 sclk, u32 min_sclk_in_sr)
2033{
2034 u32 i;
2035 u32 tmp;
2036 u32 min = (min_sclk_in_sr > CISLAND_MINIMUM_ENGINE_CLOCK) ?
2037 min_sclk_in_sr : CISLAND_MINIMUM_ENGINE_CLOCK;
2038
2039 if (sclk < min)
2040 return 0;
2041
2042 for (i = CISLAND_MAX_DEEPSLEEP_DIVIDER_ID; ; i--) {
2043 tmp = sclk / (1 << i);
2044 if (tmp >= min || i == 0)
2045 break;
2046 }
2047
2048 return (u8)i;
2049}
2050
2051static int ci_initial_switch_from_arb_f0_to_f1(struct radeon_device *rdev)
2052{
2053 return ni_copy_and_switch_arb_sets(rdev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
2054}
2055
2056static int ci_reset_to_default(struct radeon_device *rdev)
2057{
2058 return (ci_send_msg_to_smc(rdev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ?
2059 0 : -EINVAL;
2060}
2061
2062static int ci_force_switch_to_arb_f0(struct radeon_device *rdev)
2063{
2064 u32 tmp;
2065
2066 tmp = (RREG32_SMC(SMC_SCRATCH9) & 0x0000ff00) >> 8;
2067
2068 if (tmp == MC_CG_ARB_FREQ_F0)
2069 return 0;
2070
2071 return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0);
2072}
2073
21b8a369
AD		 2074static void ci_register_patching_mc_arb(struct radeon_device *rdev,
2075 const u32 engine_clock,
2076 const u32 memory_clock,
2077 u32 *dram_timimg2)
2078{
2079 bool patch;
2080 u32 tmp, tmp2;
2081
2082 tmp = RREG32(MC_SEQ_MISC0);
2083 patch = ((tmp & 0x0000f00) == 0x300) ? true : false;
2084
2085 if (patch &&
2086 ((rdev->pdev->device == 0x67B0) ||
2087 (rdev->pdev->device == 0x67B1))) {
2088 if ((memory_clock > 100000) && (memory_clock <= 125000)) {
2089 tmp2 = (((0x31 * engine_clock) / 125000) - 1) & 0xff;
2090 *dram_timimg2 &= ~0x00ff0000;
2091 *dram_timimg2 |= tmp2 << 16;
2092 } else if ((memory_clock > 125000) && (memory_clock <= 137500)) {
2093 tmp2 = (((0x36 * engine_clock) / 137500) - 1) & 0xff;
2094 *dram_timimg2 &= ~0x00ff0000;
2095 *dram_timimg2 |= tmp2 << 16;
2096 }
2097 }
2098}
2099
2100
cc8dbbb4
AD		 2101static int ci_populate_memory_timing_parameters(struct radeon_device *rdev,
2102 u32 sclk,
2103 u32 mclk,
2104 SMU7_Discrete_MCArbDramTimingTableEntry *arb_regs)
2105{
2106 u32 dram_timing;
2107 u32 dram_timing2;
2108 u32 burst_time;
2109
2110 radeon_atom_set_engine_dram_timings(rdev, sclk, mclk);
2111
2112 dram_timing = RREG32(MC_ARB_DRAM_TIMING);
2113 dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
2114 burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK;
2115
21b8a369
AD		 2116 ci_register_patching_mc_arb(rdev, sclk, mclk, &dram_timing2);
2117
cc8dbbb4
AD		 2118 arb_regs->McArbDramTiming = cpu_to_be32(dram_timing);
2119 arb_regs->McArbDramTiming2 = cpu_to_be32(dram_timing2);
2120 arb_regs->McArbBurstTime = (u8)burst_time;
2121
2122 return 0;
2123}
2124
2125static int ci_do_program_memory_timing_parameters(struct radeon_device *rdev)
2126{
2127 struct ci_power_info *pi = ci_get_pi(rdev);
2128 SMU7_Discrete_MCArbDramTimingTable arb_regs;
2129 u32 i, j;
2130 int ret = 0;
2131
2132 memset(&arb_regs, 0, sizeof(SMU7_Discrete_MCArbDramTimingTable));
2133
2134 for (i = 0; i < pi->dpm_table.sclk_table.count; i++) {
2135 for (j = 0; j < pi->dpm_table.mclk_table.count; j++) {
2136 ret = ci_populate_memory_timing_parameters(rdev,
2137 pi->dpm_table.sclk_table.dpm_levels[i].value,
2138 pi->dpm_table.mclk_table.dpm_levels[j].value,
2139 &arb_regs.entries[i][j]);
2140 if (ret)
2141 break;
2142 }
2143 }
2144
2145 if (ret == 0)
2146 ret = ci_copy_bytes_to_smc(rdev,
2147 pi->arb_table_start,
2148 (u8 *)&arb_regs,
2149 sizeof(SMU7_Discrete_MCArbDramTimingTable),
2150 pi->sram_end);
2151
2152 return ret;
2153}
2154
2155static int ci_program_memory_timing_parameters(struct radeon_device *rdev)
2156{
2157 struct ci_power_info *pi = ci_get_pi(rdev);
2158
2159 if (pi->need_update_smu7_dpm_table == 0)
2160 return 0;
2161
2162 return ci_do_program_memory_timing_parameters(rdev);
2163}
2164
2165static void ci_populate_smc_initial_state(struct radeon_device *rdev,
2166 struct radeon_ps *radeon_boot_state)
2167{
2168 struct ci_ps *boot_state = ci_get_ps(radeon_boot_state);
2169 struct ci_power_info *pi = ci_get_pi(rdev);
2170 u32 level = 0;
2171
2172 for (level = 0; level < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; level++) {
2173 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[level].clk >=
2174 boot_state->performance_levels[0].sclk) {
2175 pi->smc_state_table.GraphicsBootLevel = level;
2176 break;
2177 }
2178 }
2179
2180 for (level = 0; level < rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.count; level++) {
2181 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries[level].clk >=
2182 boot_state->performance_levels[0].mclk) {
2183 pi->smc_state_table.MemoryBootLevel = level;
2184 break;
2185 }
2186 }
2187}
2188
2189static u32 ci_get_dpm_level_enable_mask_value(struct ci_single_dpm_table *dpm_table)
2190{
2191 u32 i;
2192 u32 mask_value = 0;
2193
2194 for (i = dpm_table->count; i > 0; i--) {
2195 mask_value = mask_value << 1;
2196 if (dpm_table->dpm_levels[i-1].enabled)
2197 mask_value |= 0x1;
2198 else
2199 mask_value &= 0xFFFFFFFE;
2200 }
2201
2202 return mask_value;
2203}
2204
2205static void ci_populate_smc_link_level(struct radeon_device *rdev,
2206 SMU7_Discrete_DpmTable *table)
2207{
2208 struct ci_power_info *pi = ci_get_pi(rdev);
2209 struct ci_dpm_table *dpm_table = &pi->dpm_table;
2210 u32 i;
2211
2212 for (i = 0; i < dpm_table->pcie_speed_table.count; i++) {
2213 table->LinkLevel[i].PcieGenSpeed =
2214 (u8)dpm_table->pcie_speed_table.dpm_levels[i].value;
2215 table->LinkLevel[i].PcieLaneCount =
2216 r600_encode_pci_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1);
2217 table->LinkLevel[i].EnabledForActivity = 1;
2218 table->LinkLevel[i].DownT = cpu_to_be32(5);
2219 table->LinkLevel[i].UpT = cpu_to_be32(30);
2220 }
2221
2222 pi->smc_state_table.LinkLevelCount = (u8)dpm_table->pcie_speed_table.count;
2223 pi->dpm_level_enable_mask.pcie_dpm_enable_mask =
2224 ci_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
2225}
2226
2227static int ci_populate_smc_uvd_level(struct radeon_device *rdev,
2228 SMU7_Discrete_DpmTable *table)
2229{
2230 u32 count;
2231 struct atom_clock_dividers dividers;
2232 int ret = -EINVAL;
2233
2234 table->UvdLevelCount =
2235 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count;
2236
2237 for (count = 0; count < table->UvdLevelCount; count++) {
2238 table->UvdLevel[count].VclkFrequency =
2239 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].vclk;
2240 table->UvdLevel[count].DclkFrequency =
2241 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].dclk;
2242 table->UvdLevel[count].MinVddc =
2243 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE;
2244 table->UvdLevel[count].MinVddcPhases = 1;
2245
2246 ret = radeon_atom_get_clock_dividers(rdev,
2247 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2248 table->UvdLevel[count].VclkFrequency, false, &dividers);
2249 if (ret)
2250 return ret;
2251
2252 table->UvdLevel[count].VclkDivider = (u8)dividers.post_divider;
2253
2254 ret = radeon_atom_get_clock_dividers(rdev,
2255 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2256 table->UvdLevel[count].DclkFrequency, false, &dividers);
2257 if (ret)
2258 return ret;
2259
2260 table->UvdLevel[count].DclkDivider = (u8)dividers.post_divider;
2261
2262 table->UvdLevel[count].VclkFrequency = cpu_to_be32(table->UvdLevel[count].VclkFrequency);
2263 table->UvdLevel[count].DclkFrequency = cpu_to_be32(table->UvdLevel[count].DclkFrequency);
2264 table->UvdLevel[count].MinVddc = cpu_to_be16(table->UvdLevel[count].MinVddc);
2265 }
2266
2267 return ret;
2268}
2269
2270static int ci_populate_smc_vce_level(struct radeon_device *rdev,
2271 SMU7_Discrete_DpmTable *table)
2272{
2273 u32 count;
2274 struct atom_clock_dividers dividers;
2275 int ret = -EINVAL;
2276
2277 table->VceLevelCount =
2278 rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count;
2279
2280 for (count = 0; count < table->VceLevelCount; count++) {
2281 table->VceLevel[count].Frequency =
2282 rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].evclk;
2283 table->VceLevel[count].MinVoltage =
2284 (u16)rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE;
2285 table->VceLevel[count].MinPhases = 1;
2286
2287 ret = radeon_atom_get_clock_dividers(rdev,
2288 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2289 table->VceLevel[count].Frequency, false, &dividers);
2290 if (ret)
2291 return ret;
2292
2293 table->VceLevel[count].Divider = (u8)dividers.post_divider;
2294
2295 table->VceLevel[count].Frequency = cpu_to_be32(table->VceLevel[count].Frequency);
2296 table->VceLevel[count].MinVoltage = cpu_to_be16(table->VceLevel[count].MinVoltage);
2297 }
2298
2299 return ret;
2300
2301}
2302
2303static int ci_populate_smc_acp_level(struct radeon_device *rdev,
2304 SMU7_Discrete_DpmTable *table)
2305{
2306 u32 count;
2307 struct atom_clock_dividers dividers;
2308 int ret = -EINVAL;
2309
2310 table->AcpLevelCount = (u8)
2311 (rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count);
2312
2313 for (count = 0; count < table->AcpLevelCount; count++) {
2314 table->AcpLevel[count].Frequency =
2315 rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[count].clk;
2316 table->AcpLevel[count].MinVoltage =
2317 rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[count].v;
2318 table->AcpLevel[count].MinPhases = 1;
2319
2320 ret = radeon_atom_get_clock_dividers(rdev,
2321 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2322 table->AcpLevel[count].Frequency, false, &dividers);
2323 if (ret)
2324 return ret;
2325
2326 table->AcpLevel[count].Divider = (u8)dividers.post_divider;
2327
2328 table->AcpLevel[count].Frequency = cpu_to_be32(table->AcpLevel[count].Frequency);
2329 table->AcpLevel[count].MinVoltage = cpu_to_be16(table->AcpLevel[count].MinVoltage);
2330 }
2331
2332 return ret;
2333}
2334
2335static int ci_populate_smc_samu_level(struct radeon_device *rdev,
2336 SMU7_Discrete_DpmTable *table)
2337{
2338 u32 count;
2339 struct atom_clock_dividers dividers;
2340 int ret = -EINVAL;
2341
2342 table->SamuLevelCount =
2343 rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count;
2344
2345 for (count = 0; count < table->SamuLevelCount; count++) {
2346 table->SamuLevel[count].Frequency =
2347 rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[count].clk;
2348 table->SamuLevel[count].MinVoltage =
2349 rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE;
2350 table->SamuLevel[count].MinPhases = 1;
2351
2352 ret = radeon_atom_get_clock_dividers(rdev,
2353 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2354 table->SamuLevel[count].Frequency, false, &dividers);
2355 if (ret)
2356 return ret;
2357
2358 table->SamuLevel[count].Divider = (u8)dividers.post_divider;
2359
2360 table->SamuLevel[count].Frequency = cpu_to_be32(table->SamuLevel[count].Frequency);
2361 table->SamuLevel[count].MinVoltage = cpu_to_be16(table->SamuLevel[count].MinVoltage);
2362 }
2363
2364 return ret;
2365}
2366
2367static int ci_calculate_mclk_params(struct radeon_device *rdev,
2368 u32 memory_clock,
2369 SMU7_Discrete_MemoryLevel *mclk,
2370 bool strobe_mode,
2371 bool dll_state_on)
2372{
2373 struct ci_power_info *pi = ci_get_pi(rdev);
2374 u32 dll_cntl = pi->clock_registers.dll_cntl;
2375 u32 mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl;
2376 u32 mpll_ad_func_cntl = pi->clock_registers.mpll_ad_func_cntl;
2377 u32 mpll_dq_func_cntl = pi->clock_registers.mpll_dq_func_cntl;
2378 u32 mpll_func_cntl = pi->clock_registers.mpll_func_cntl;
2379 u32 mpll_func_cntl_1 = pi->clock_registers.mpll_func_cntl_1;
2380 u32 mpll_func_cntl_2 = pi->clock_registers.mpll_func_cntl_2;
2381 u32 mpll_ss1 = pi->clock_registers.mpll_ss1;
2382 u32 mpll_ss2 = pi->clock_registers.mpll_ss2;
2383 struct atom_mpll_param mpll_param;
2384 int ret;
2385
2386 ret = radeon_atom_get_memory_pll_dividers(rdev, memory_clock, strobe_mode, &mpll_param);
2387 if (ret)
2388 return ret;
2389
2390 mpll_func_cntl &= ~BWCTRL_MASK;
2391 mpll_func_cntl |= BWCTRL(mpll_param.bwcntl);
2392
2393 mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK);
2394 mpll_func_cntl_1 |= CLKF(mpll_param.clkf) |
2395 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode);
2396
2397 mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK;
2398 mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div);
2399
2400 if (pi->mem_gddr5) {
2401 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK);
2402 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) |
2403 YCLK_POST_DIV(mpll_param.post_div);
2404 }
2405
2406 if (pi->caps_mclk_ss_support) {
2407 struct radeon_atom_ss ss;
2408 u32 freq_nom;
2409 u32 tmp;
2410 u32 reference_clock = rdev->clock.mpll.reference_freq;
2411
c0392f8f
AD		 2412 if (mpll_param.qdr == 1)
2413 freq_nom = memory_clock * 4 * (1 << mpll_param.post_div);
cc8dbbb4 2414 else
c0392f8f 2415 freq_nom = memory_clock * 2 * (1 << mpll_param.post_div);
cc8dbbb4
AD		 2416
2417 tmp = (freq_nom / reference_clock);
2418 tmp = tmp * tmp;
2419 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
2420 ASIC_INTERNAL_MEMORY_SS, freq_nom)) {
2421 u32 clks = reference_clock * 5 / ss.rate;
2422 u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom);
2423
2424 mpll_ss1 &= ~CLKV_MASK;
2425 mpll_ss1 |= CLKV(clkv);
2426
2427 mpll_ss2 &= ~CLKS_MASK;
2428 mpll_ss2 |= CLKS(clks);
2429 }
2430 }
2431
2432 mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK;
2433 mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed);
2434
2435 if (dll_state_on)
2436 mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB;
2437 else
2438 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
2439
2440 mclk->MclkFrequency = memory_clock;
2441 mclk->MpllFuncCntl = mpll_func_cntl;
2442 mclk->MpllFuncCntl_1 = mpll_func_cntl_1;
2443 mclk->MpllFuncCntl_2 = mpll_func_cntl_2;
2444 mclk->MpllAdFuncCntl = mpll_ad_func_cntl;
2445 mclk->MpllDqFuncCntl = mpll_dq_func_cntl;
2446 mclk->MclkPwrmgtCntl = mclk_pwrmgt_cntl;
2447 mclk->DllCntl = dll_cntl;
2448 mclk->MpllSs1 = mpll_ss1;
2449 mclk->MpllSs2 = mpll_ss2;
2450
2451 return 0;
2452}
2453
2454static int ci_populate_single_memory_level(struct radeon_device *rdev,
2455 u32 memory_clock,
2456 SMU7_Discrete_MemoryLevel *memory_level)
2457{
2458 struct ci_power_info *pi = ci_get_pi(rdev);
2459 int ret;
2460 bool dll_state_on;
2461
2462 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries) {
2463 ret = ci_get_dependency_volt_by_clk(rdev,
2464 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
2465 memory_clock, &memory_level->MinVddc);
2466 if (ret)
2467 return ret;
2468 }
2469
2470 if (rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk.entries) {
2471 ret = ci_get_dependency_volt_by_clk(rdev,
2472 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
2473 memory_clock, &memory_level->MinVddci);
2474 if (ret)
2475 return ret;
2476 }
2477
2478 if (rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries) {
2479 ret = ci_get_dependency_volt_by_clk(rdev,
2480 &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk,
2481 memory_clock, &memory_level->MinMvdd);
2482 if (ret)
2483 return ret;
2484 }
2485
2486 memory_level->MinVddcPhases = 1;
2487
2488 if (pi->vddc_phase_shed_control)
2489 ci_populate_phase_value_based_on_mclk(rdev,
2490 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
2491 memory_clock,
2492 &memory_level->MinVddcPhases);
2493
2494 memory_level->EnabledForThrottle = 1;
cc8dbbb4
AD		 2495 memory_level->UpH = 0;
2496 memory_level->DownH = 100;
2497 memory_level->VoltageDownH = 0;
2498 memory_level->ActivityLevel = (u16)pi->mclk_activity_target;
2499
2500 memory_level->StutterEnable = false;
2501 memory_level->StrobeEnable = false;
2502 memory_level->EdcReadEnable = false;
2503 memory_level->EdcWriteEnable = false;
2504 memory_level->RttEnable = false;
2505
2506 memory_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
2507
2508 if (pi->mclk_stutter_mode_threshold &&
2509 (memory_clock <= pi->mclk_stutter_mode_threshold) &&
2510 (pi->uvd_enabled == false) &&
2511 (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) &&
2512 (rdev->pm.dpm.new_active_crtc_count <= 2))
2513 memory_level->StutterEnable = true;
2514
2515 if (pi->mclk_strobe_mode_threshold &&
2516 (memory_clock <= pi->mclk_strobe_mode_threshold))
2517 memory_level->StrobeEnable = 1;
2518
2519 if (pi->mem_gddr5) {
2520 memory_level->StrobeRatio =
2521 si_get_mclk_frequency_ratio(memory_clock, memory_level->StrobeEnable);
2522 if (pi->mclk_edc_enable_threshold &&
2523 (memory_clock > pi->mclk_edc_enable_threshold))
2524 memory_level->EdcReadEnable = true;
2525
2526 if (pi->mclk_edc_wr_enable_threshold &&
2527 (memory_clock > pi->mclk_edc_wr_enable_threshold))
2528 memory_level->EdcWriteEnable = true;
2529
2530 if (memory_level->StrobeEnable) {
2531 if (si_get_mclk_frequency_ratio(memory_clock, true) >=
2532 ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf))
2533 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
2534 else
2535 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
2536 } else {
2537 dll_state_on = pi->dll_default_on;
2538 }
2539 } else {
2540 memory_level->StrobeRatio = si_get_ddr3_mclk_frequency_ratio(memory_clock);
2541 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
2542 }
2543
2544 ret = ci_calculate_mclk_params(rdev, memory_clock, memory_level, memory_level->StrobeEnable, dll_state_on);
2545 if (ret)
2546 return ret;
2547
2548 memory_level->MinVddc = cpu_to_be32(memory_level->MinVddc * VOLTAGE_SCALE);
2549 memory_level->MinVddcPhases = cpu_to_be32(memory_level->MinVddcPhases);
2550 memory_level->MinVddci = cpu_to_be32(memory_level->MinVddci * VOLTAGE_SCALE);
2551 memory_level->MinMvdd = cpu_to_be32(memory_level->MinMvdd * VOLTAGE_SCALE);
2552
2553 memory_level->MclkFrequency = cpu_to_be32(memory_level->MclkFrequency);
2554 memory_level->ActivityLevel = cpu_to_be16(memory_level->ActivityLevel);
2555 memory_level->MpllFuncCntl = cpu_to_be32(memory_level->MpllFuncCntl);
2556 memory_level->MpllFuncCntl_1 = cpu_to_be32(memory_level->MpllFuncCntl_1);
2557 memory_level->MpllFuncCntl_2 = cpu_to_be32(memory_level->MpllFuncCntl_2);
2558 memory_level->MpllAdFuncCntl = cpu_to_be32(memory_level->MpllAdFuncCntl);
2559 memory_level->MpllDqFuncCntl = cpu_to_be32(memory_level->MpllDqFuncCntl);
2560 memory_level->MclkPwrmgtCntl = cpu_to_be32(memory_level->MclkPwrmgtCntl);
2561 memory_level->DllCntl = cpu_to_be32(memory_level->DllCntl);
2562 memory_level->MpllSs1 = cpu_to_be32(memory_level->MpllSs1);
2563 memory_level->MpllSs2 = cpu_to_be32(memory_level->MpllSs2);
2564
2565 return 0;
2566}
2567
2568static int ci_populate_smc_acpi_level(struct radeon_device *rdev,
2569 SMU7_Discrete_DpmTable *table)
2570{
2571 struct ci_power_info *pi = ci_get_pi(rdev);
2572 struct atom_clock_dividers dividers;
2573 SMU7_Discrete_VoltageLevel voltage_level;
2574 u32 spll_func_cntl = pi->clock_registers.cg_spll_func_cntl;
2575 u32 spll_func_cntl_2 = pi->clock_registers.cg_spll_func_cntl_2;
2576 u32 dll_cntl = pi->clock_registers.dll_cntl;
2577 u32 mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl;
2578 int ret;
2579
2580 table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
2581
2582 if (pi->acpi_vddc)
2583 table->ACPILevel.MinVddc = cpu_to_be32(pi->acpi_vddc * VOLTAGE_SCALE);
2584 else
2585 table->ACPILevel.MinVddc = cpu_to_be32(pi->min_vddc_in_pp_table * VOLTAGE_SCALE);
2586
2587 table->ACPILevel.MinVddcPhases = pi->vddc_phase_shed_control ? 0 : 1;
2588
2589 table->ACPILevel.SclkFrequency = rdev->clock.spll.reference_freq;
2590
2591 ret = radeon_atom_get_clock_dividers(rdev,
2592 COMPUTE_GPUCLK_INPUT_FLAG_SCLK,
2593 table->ACPILevel.SclkFrequency, false, &dividers);
2594 if (ret)
2595 return ret;
2596
2597 table->ACPILevel.SclkDid = (u8)dividers.post_divider;
2598 table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
2599 table->ACPILevel.DeepSleepDivId = 0;
2600
2601 spll_func_cntl &= ~SPLL_PWRON;
2602 spll_func_cntl |= SPLL_RESET;
2603
2604 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
2605 spll_func_cntl_2 |= SCLK_MUX_SEL(4);
2606
2607 table->ACPILevel.CgSpllFuncCntl = spll_func_cntl;
2608 table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2;
2609 table->ACPILevel.CgSpllFuncCntl3 = pi->clock_registers.cg_spll_func_cntl_3;
2610 table->ACPILevel.CgSpllFuncCntl4 = pi->clock_registers.cg_spll_func_cntl_4;
2611 table->ACPILevel.SpllSpreadSpectrum = pi->clock_registers.cg_spll_spread_spectrum;
2612 table->ACPILevel.SpllSpreadSpectrum2 = pi->clock_registers.cg_spll_spread_spectrum_2;
2613 table->ACPILevel.CcPwrDynRm = 0;
2614 table->ACPILevel.CcPwrDynRm1 = 0;
2615
2616 table->ACPILevel.Flags = cpu_to_be32(table->ACPILevel.Flags);
2617 table->ACPILevel.MinVddcPhases = cpu_to_be32(table->ACPILevel.MinVddcPhases);
2618 table->ACPILevel.SclkFrequency = cpu_to_be32(table->ACPILevel.SclkFrequency);
2619 table->ACPILevel.CgSpllFuncCntl = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl);
2620 table->ACPILevel.CgSpllFuncCntl2 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl2);
2621 table->ACPILevel.CgSpllFuncCntl3 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl3);
2622 table->ACPILevel.CgSpllFuncCntl4 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl4);
2623 table->ACPILevel.SpllSpreadSpectrum = cpu_to_be32(table->ACPILevel.SpllSpreadSpectrum);
2624 table->ACPILevel.SpllSpreadSpectrum2 = cpu_to_be32(table->ACPILevel.SpllSpreadSpectrum2);
2625 table->ACPILevel.CcPwrDynRm = cpu_to_be32(table->ACPILevel.CcPwrDynRm);
2626 table->ACPILevel.CcPwrDynRm1 = cpu_to_be32(table->ACPILevel.CcPwrDynRm1);
2627
2628 table->MemoryACPILevel.MinVddc = table->ACPILevel.MinVddc;
2629 table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases;
2630
2631 if (pi->vddci_control != CISLANDS_VOLTAGE_CONTROL_NONE) {
2632 if (pi->acpi_vddci)
2633 table->MemoryACPILevel.MinVddci =
2634 cpu_to_be32(pi->acpi_vddci * VOLTAGE_SCALE);
2635 else
2636 table->MemoryACPILevel.MinVddci =
2637 cpu_to_be32(pi->min_vddci_in_pp_table * VOLTAGE_SCALE);
2638 }
2639
2640 if (ci_populate_mvdd_value(rdev, 0, &voltage_level))
2641 table->MemoryACPILevel.MinMvdd = 0;
2642 else
2643 table->MemoryACPILevel.MinMvdd =
2644 cpu_to_be32(voltage_level.Voltage * VOLTAGE_SCALE);
2645
2646 mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET;
2647 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
2648
2649 dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS);
2650
2651 table->MemoryACPILevel.DllCntl = cpu_to_be32(dll_cntl);
2652 table->MemoryACPILevel.MclkPwrmgtCntl = cpu_to_be32(mclk_pwrmgt_cntl);
2653 table->MemoryACPILevel.MpllAdFuncCntl =
2654 cpu_to_be32(pi->clock_registers.mpll_ad_func_cntl);
2655 table->MemoryACPILevel.MpllDqFuncCntl =
2656 cpu_to_be32(pi->clock_registers.mpll_dq_func_cntl);
2657 table->MemoryACPILevel.MpllFuncCntl =
2658 cpu_to_be32(pi->clock_registers.mpll_func_cntl);
2659 table->MemoryACPILevel.MpllFuncCntl_1 =
2660 cpu_to_be32(pi->clock_registers.mpll_func_cntl_1);
2661 table->MemoryACPILevel.MpllFuncCntl_2 =
2662 cpu_to_be32(pi->clock_registers.mpll_func_cntl_2);
2663 table->MemoryACPILevel.MpllSs1 = cpu_to_be32(pi->clock_registers.mpll_ss1);
2664 table->MemoryACPILevel.MpllSs2 = cpu_to_be32(pi->clock_registers.mpll_ss2);
2665
2666 table->MemoryACPILevel.EnabledForThrottle = 0;
2667 table->MemoryACPILevel.EnabledForActivity = 0;
2668 table->MemoryACPILevel.UpH = 0;
2669 table->MemoryACPILevel.DownH = 100;
2670 table->MemoryACPILevel.VoltageDownH = 0;
2671 table->MemoryACPILevel.ActivityLevel =
2672 cpu_to_be16((u16)pi->mclk_activity_target);
2673
2674 table->MemoryACPILevel.StutterEnable = false;
2675 table->MemoryACPILevel.StrobeEnable = false;
2676 table->MemoryACPILevel.EdcReadEnable = false;
2677 table->MemoryACPILevel.EdcWriteEnable = false;
2678 table->MemoryACPILevel.RttEnable = false;
2679
2680 return 0;
2681}
2682
2683
2684static int ci_enable_ulv(struct radeon_device *rdev, bool enable)
2685{
2686 struct ci_power_info *pi = ci_get_pi(rdev);
2687 struct ci_ulv_parm *ulv = &pi->ulv;
2688
2689 if (ulv->supported) {
2690 if (enable)
2691 return (ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ?
2692 0 : -EINVAL;
2693 else
2694 return (ci_send_msg_to_smc(rdev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ?
2695 0 : -EINVAL;
2696 }
2697
2698 return 0;
2699}
2700
2701static int ci_populate_ulv_level(struct radeon_device *rdev,
2702 SMU7_Discrete_Ulv *state)
2703{
2704 struct ci_power_info *pi = ci_get_pi(rdev);
2705 u16 ulv_voltage = rdev->pm.dpm.backbias_response_time;
2706
2707 state->CcPwrDynRm = 0;
2708 state->CcPwrDynRm1 = 0;
2709
2710 if (ulv_voltage == 0) {
2711 pi->ulv.supported = false;
2712 return 0;
2713 }
2714
2715 if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
2716 if (ulv_voltage > rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v)
2717 state->VddcOffset = 0;
2718 else
2719 state->VddcOffset =
2720 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage;
2721 } else {
2722 if (ulv_voltage > rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v)
2723 state->VddcOffsetVid = 0;
2724 else
2725 state->VddcOffsetVid = (u8)
2726 ((rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage) *
2727 VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1);
2728 }
2729 state->VddcPhase = pi->vddc_phase_shed_control ? 0 : 1;
2730
2731 state->CcPwrDynRm = cpu_to_be32(state->CcPwrDynRm);
2732 state->CcPwrDynRm1 = cpu_to_be32(state->CcPwrDynRm1);
2733 state->VddcOffset = cpu_to_be16(state->VddcOffset);
2734
2735 return 0;
2736}
2737
2738static int ci_calculate_sclk_params(struct radeon_device *rdev,
2739 u32 engine_clock,
2740 SMU7_Discrete_GraphicsLevel *sclk)
2741{
2742 struct ci_power_info *pi = ci_get_pi(rdev);
2743 struct atom_clock_dividers dividers;
2744 u32 spll_func_cntl_3 = pi->clock_registers.cg_spll_func_cntl_3;
2745 u32 spll_func_cntl_4 = pi->clock_registers.cg_spll_func_cntl_4;
2746 u32 cg_spll_spread_spectrum = pi->clock_registers.cg_spll_spread_spectrum;
2747 u32 cg_spll_spread_spectrum_2 = pi->clock_registers.cg_spll_spread_spectrum_2;
2748 u32 reference_clock = rdev->clock.spll.reference_freq;
2749 u32 reference_divider;
2750 u32 fbdiv;
2751 int ret;
2752
2753 ret = radeon_atom_get_clock_dividers(rdev,
2754 COMPUTE_GPUCLK_INPUT_FLAG_SCLK,
2755 engine_clock, false, &dividers);
2756 if (ret)
2757 return ret;
2758
2759 reference_divider = 1 + dividers.ref_div;
2760 fbdiv = dividers.fb_div & 0x3FFFFFF;
2761
2762 spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK;
2763 spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv);
2764 spll_func_cntl_3 |= SPLL_DITHEN;
2765
2766 if (pi->caps_sclk_ss_support) {
2767 struct radeon_atom_ss ss;
2768 u32 vco_freq = engine_clock * dividers.post_div;
2769
2770 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
2771 ASIC_INTERNAL_ENGINE_SS, vco_freq)) {
2772 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);
2773 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);
2774
2775 cg_spll_spread_spectrum &= ~CLK_S_MASK;
2776 cg_spll_spread_spectrum |= CLK_S(clk_s);
2777 cg_spll_spread_spectrum |= SSEN;
2778
2779 cg_spll_spread_spectrum_2 &= ~CLK_V_MASK;
2780 cg_spll_spread_spectrum_2 |= CLK_V(clk_v);
2781 }
2782 }
2783
2784 sclk->SclkFrequency = engine_clock;
2785 sclk->CgSpllFuncCntl3 = spll_func_cntl_3;
2786 sclk->CgSpllFuncCntl4 = spll_func_cntl_4;
2787 sclk->SpllSpreadSpectrum = cg_spll_spread_spectrum;
2788 sclk->SpllSpreadSpectrum2 = cg_spll_spread_spectrum_2;
2789 sclk->SclkDid = (u8)dividers.post_divider;
2790
2791 return 0;
2792}
2793
2794static int ci_populate_single_graphic_level(struct radeon_device *rdev,
2795 u32 engine_clock,
2796 u16 sclk_activity_level_t,
2797 SMU7_Discrete_GraphicsLevel *graphic_level)
2798{
2799 struct ci_power_info *pi = ci_get_pi(rdev);
2800 int ret;
2801
2802 ret = ci_calculate_sclk_params(rdev, engine_clock, graphic_level);
2803 if (ret)
2804 return ret;
2805
2806 ret = ci_get_dependency_volt_by_clk(rdev,
2807 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
2808 engine_clock, &graphic_level->MinVddc);
2809 if (ret)
2810 return ret;
2811
2812 graphic_level->SclkFrequency = engine_clock;
2813
2814 graphic_level->Flags = 0;
2815 graphic_level->MinVddcPhases = 1;
2816
2817 if (pi->vddc_phase_shed_control)
2818 ci_populate_phase_value_based_on_sclk(rdev,
2819 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
2820 engine_clock,
2821 &graphic_level->MinVddcPhases);
2822
2823 graphic_level->ActivityLevel = sclk_activity_level_t;
2824
2825 graphic_level->CcPwrDynRm = 0;
2826 graphic_level->CcPwrDynRm1 = 0;
cc8dbbb4
AD		 2827 graphic_level->EnabledForThrottle = 1;
2828 graphic_level->UpH = 0;
2829 graphic_level->DownH = 0;
2830 graphic_level->VoltageDownH = 0;
2831 graphic_level->PowerThrottle = 0;
2832
2833 if (pi->caps_sclk_ds)
2834 graphic_level->DeepSleepDivId = ci_get_sleep_divider_id_from_clock(rdev,
2835 engine_clock,
2836 CISLAND_MINIMUM_ENGINE_CLOCK);
2837
2838 graphic_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
2839
2840 graphic_level->Flags = cpu_to_be32(graphic_level->Flags);
2841 graphic_level->MinVddc = cpu_to_be32(graphic_level->MinVddc * VOLTAGE_SCALE);
2842 graphic_level->MinVddcPhases = cpu_to_be32(graphic_level->MinVddcPhases);
2843 graphic_level->SclkFrequency = cpu_to_be32(graphic_level->SclkFrequency);
2844 graphic_level->ActivityLevel = cpu_to_be16(graphic_level->ActivityLevel);
2845 graphic_level->CgSpllFuncCntl3 = cpu_to_be32(graphic_level->CgSpllFuncCntl3);
2846 graphic_level->CgSpllFuncCntl4 = cpu_to_be32(graphic_level->CgSpllFuncCntl4);
2847 graphic_level->SpllSpreadSpectrum = cpu_to_be32(graphic_level->SpllSpreadSpectrum);
2848 graphic_level->SpllSpreadSpectrum2 = cpu_to_be32(graphic_level->SpllSpreadSpectrum2);
2849 graphic_level->CcPwrDynRm = cpu_to_be32(graphic_level->CcPwrDynRm);
2850 graphic_level->CcPwrDynRm1 = cpu_to_be32(graphic_level->CcPwrDynRm1);
2851
2852 return 0;
2853}
2854
2855static int ci_populate_all_graphic_levels(struct radeon_device *rdev)
2856{
2857 struct ci_power_info *pi = ci_get_pi(rdev);
2858 struct ci_dpm_table *dpm_table = &pi->dpm_table;
2859 u32 level_array_address = pi->dpm_table_start +
2860 offsetof(SMU7_Discrete_DpmTable, GraphicsLevel);
2861 u32 level_array_size = sizeof(SMU7_Discrete_GraphicsLevel) *
2862 SMU7_MAX_LEVELS_GRAPHICS;
2863 SMU7_Discrete_GraphicsLevel *levels = pi->smc_state_table.GraphicsLevel;
2864 u32 i, ret;
2865
2866 memset(levels, 0, level_array_size);
2867
2868 for (i = 0; i < dpm_table->sclk_table.count; i++) {
2869 ret = ci_populate_single_graphic_level(rdev,
2870 dpm_table->sclk_table.dpm_levels[i].value,
2871 (u16)pi->activity_target[i],
2872 &pi->smc_state_table.GraphicsLevel[i]);
2873 if (ret)
2874 return ret;
489ba72c
AD		 2875 if (i > 1)
2876 pi->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0;
cc8dbbb4
AD		 2877 if (i == (dpm_table->sclk_table.count - 1))
2878 pi->smc_state_table.GraphicsLevel[i].DisplayWatermark =
2879 PPSMC_DISPLAY_WATERMARK_HIGH;
2880 }
d3052b8c 2881 pi->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1;
cc8dbbb4
AD		 2882
2883 pi->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count;
2884 pi->dpm_level_enable_mask.sclk_dpm_enable_mask =
2885 ci_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
2886
2887 ret = ci_copy_bytes_to_smc(rdev, level_array_address,
2888 (u8 *)levels, level_array_size,
2889 pi->sram_end);
2890 if (ret)
2891 return ret;
2892
2893 return 0;
2894}
2895
2896static int ci_populate_ulv_state(struct radeon_device *rdev,
2897 SMU7_Discrete_Ulv *ulv_level)
2898{
2899 return ci_populate_ulv_level(rdev, ulv_level);
2900}
2901
2902static int ci_populate_all_memory_levels(struct radeon_device *rdev)
2903{
2904 struct ci_power_info *pi = ci_get_pi(rdev);
2905 struct ci_dpm_table *dpm_table = &pi->dpm_table;
2906 u32 level_array_address = pi->dpm_table_start +
2907 offsetof(SMU7_Discrete_DpmTable, MemoryLevel);
2908 u32 level_array_size = sizeof(SMU7_Discrete_MemoryLevel) *
2909 SMU7_MAX_LEVELS_MEMORY;
2910 SMU7_Discrete_MemoryLevel *levels = pi->smc_state_table.MemoryLevel;
2911 u32 i, ret;
2912
2913 memset(levels, 0, level_array_size);
2914
2915 for (i = 0; i < dpm_table->mclk_table.count; i++) {
2916 if (dpm_table->mclk_table.dpm_levels[i].value == 0)
2917 return -EINVAL;
2918 ret = ci_populate_single_memory_level(rdev,
2919 dpm_table->mclk_table.dpm_levels[i].value,
2920 &pi->smc_state_table.MemoryLevel[i]);
2921 if (ret)
2922 return ret;
2923 }
2924
d3052b8c
AD		 2925 pi->smc_state_table.MemoryLevel[0].EnabledForActivity = 1;
2926
cc8dbbb4
AD		 2927 pi->smc_state_table.MemoryLevel[0].ActivityLevel = cpu_to_be16(0x1F);
2928
2929 pi->smc_state_table.MemoryDpmLevelCount = (u8)dpm_table->mclk_table.count;
2930 pi->dpm_level_enable_mask.mclk_dpm_enable_mask =
2931 ci_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
2932
2933 pi->smc_state_table.MemoryLevel[dpm_table->mclk_table.count - 1].DisplayWatermark =
2934 PPSMC_DISPLAY_WATERMARK_HIGH;
2935
2936 ret = ci_copy_bytes_to_smc(rdev, level_array_address,
2937 (u8 *)levels, level_array_size,
2938 pi->sram_end);
2939 if (ret)
2940 return ret;
2941
2942 return 0;
2943}
2944
2945static void ci_reset_single_dpm_table(struct radeon_device *rdev,
2946 struct ci_single_dpm_table* dpm_table,
2947 u32 count)
2948{
2949 u32 i;
2950
2951 dpm_table->count = count;
2952 for (i = 0; i < MAX_REGULAR_DPM_NUMBER; i++)
2953 dpm_table->dpm_levels[i].enabled = false;
2954}
2955
2956static void ci_setup_pcie_table_entry(struct ci_single_dpm_table* dpm_table,
2957 u32 index, u32 pcie_gen, u32 pcie_lanes)
2958{
2959 dpm_table->dpm_levels[index].value = pcie_gen;
2960 dpm_table->dpm_levels[index].param1 = pcie_lanes;
2961 dpm_table->dpm_levels[index].enabled = true;
2962}
2963
2964static int ci_setup_default_pcie_tables(struct radeon_device *rdev)
2965{
2966 struct ci_power_info *pi = ci_get_pi(rdev);
2967
2968 if (!pi->use_pcie_performance_levels && !pi->use_pcie_powersaving_levels)
2969 return -EINVAL;
2970
2971 if (pi->use_pcie_performance_levels && !pi->use_pcie_powersaving_levels) {
2972 pi->pcie_gen_powersaving = pi->pcie_gen_performance;
2973 pi->pcie_lane_powersaving = pi->pcie_lane_performance;
2974 } else if (!pi->use_pcie_performance_levels && pi->use_pcie_powersaving_levels) {
2975 pi->pcie_gen_performance = pi->pcie_gen_powersaving;
2976 pi->pcie_lane_performance = pi->pcie_lane_powersaving;
2977 }
2978
2979 ci_reset_single_dpm_table(rdev,
2980 &pi->dpm_table.pcie_speed_table,
2981 SMU7_MAX_LEVELS_LINK);
2982
2983 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0,
2984 pi->pcie_gen_powersaving.min,
2985 pi->pcie_lane_powersaving.min);
2986 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 1,
2987 pi->pcie_gen_performance.min,
2988 pi->pcie_lane_performance.min);
2989 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 2,
2990 pi->pcie_gen_powersaving.min,
2991 pi->pcie_lane_powersaving.max);
2992 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 3,
2993 pi->pcie_gen_performance.min,
2994 pi->pcie_lane_performance.max);
2995 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 4,
2996 pi->pcie_gen_powersaving.max,
2997 pi->pcie_lane_powersaving.max);
2998 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 5,
2999 pi->pcie_gen_performance.max,
3000 pi->pcie_lane_performance.max);
3001
3002 pi->dpm_table.pcie_speed_table.count = 6;
3003
3004 return 0;
3005}
3006
3007static int ci_setup_default_dpm_tables(struct radeon_device *rdev)
3008{
3009 struct ci_power_info *pi = ci_get_pi(rdev);
3010 struct radeon_clock_voltage_dependency_table *allowed_sclk_vddc_table =
3011 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
3012 struct radeon_clock_voltage_dependency_table *allowed_mclk_table =
3013 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk;
3014 struct radeon_cac_leakage_table *std_voltage_table =
3015 &rdev->pm.dpm.dyn_state.cac_leakage_table;
3016 u32 i;
3017
3018 if (allowed_sclk_vddc_table == NULL)
3019 return -EINVAL;
3020 if (allowed_sclk_vddc_table->count < 1)
3021 return -EINVAL;
3022 if (allowed_mclk_table == NULL)
3023 return -EINVAL;
3024 if (allowed_mclk_table->count < 1)
3025 return -EINVAL;
3026
3027 memset(&pi->dpm_table, 0, sizeof(struct ci_dpm_table));
3028
3029 ci_reset_single_dpm_table(rdev,
3030 &pi->dpm_table.sclk_table,
3031 SMU7_MAX_LEVELS_GRAPHICS);
3032 ci_reset_single_dpm_table(rdev,
3033 &pi->dpm_table.mclk_table,
3034 SMU7_MAX_LEVELS_MEMORY);
3035 ci_reset_single_dpm_table(rdev,
3036 &pi->dpm_table.vddc_table,
3037 SMU7_MAX_LEVELS_VDDC);
3038 ci_reset_single_dpm_table(rdev,
3039 &pi->dpm_table.vddci_table,
3040 SMU7_MAX_LEVELS_VDDCI);
3041 ci_reset_single_dpm_table(rdev,
3042 &pi->dpm_table.mvdd_table,
3043 SMU7_MAX_LEVELS_MVDD);
3044
3045 pi->dpm_table.sclk_table.count = 0;
3046 for (i = 0; i < allowed_sclk_vddc_table->count; i++) {
3047 if ((i == 0) ||
3048 (pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count-1].value !=
3049 allowed_sclk_vddc_table->entries[i].clk)) {
3050 pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].value =
3051 allowed_sclk_vddc_table->entries[i].clk;
3052 pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].enabled = true;
3053 pi->dpm_table.sclk_table.count++;
3054 }
3055 }
3056
3057 pi->dpm_table.mclk_table.count = 0;
3058 for (i = 0; i < allowed_mclk_table->count; i++) {
3059 if ((i==0) ||
3060 (pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count-1].value !=
3061 allowed_mclk_table->entries[i].clk)) {
3062 pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].value =
3063 allowed_mclk_table->entries[i].clk;
3064 pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].enabled = true;
3065 pi->dpm_table.mclk_table.count++;
3066 }
3067 }
3068
3069 for (i = 0; i < allowed_sclk_vddc_table->count; i++) {
3070 pi->dpm_table.vddc_table.dpm_levels[i].value =
3071 allowed_sclk_vddc_table->entries[i].v;
3072 pi->dpm_table.vddc_table.dpm_levels[i].param1 =
3073 std_voltage_table->entries[i].leakage;
3074 pi->dpm_table.vddc_table.dpm_levels[i].enabled = true;
3075 }
3076 pi->dpm_table.vddc_table.count = allowed_sclk_vddc_table->count;
3077
3078 allowed_mclk_table = &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk;
3079 if (allowed_mclk_table) {
3080 for (i = 0; i < allowed_mclk_table->count; i++) {
3081 pi->dpm_table.vddci_table.dpm_levels[i].value =
3082 allowed_mclk_table->entries[i].v;
3083 pi->dpm_table.vddci_table.dpm_levels[i].enabled = true;
3084 }
3085 pi->dpm_table.vddci_table.count = allowed_mclk_table->count;
3086 }
3087
3088 allowed_mclk_table = &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk;
3089 if (allowed_mclk_table) {
3090 for (i = 0; i < allowed_mclk_table->count; i++) {
3091 pi->dpm_table.mvdd_table.dpm_levels[i].value =
3092 allowed_mclk_table->entries[i].v;
3093 pi->dpm_table.mvdd_table.dpm_levels[i].enabled = true;
3094 }
3095 pi->dpm_table.mvdd_table.count = allowed_mclk_table->count;
3096 }
3097
3098 ci_setup_default_pcie_tables(rdev);
3099
3100 return 0;
3101}
3102
3103static int ci_find_boot_level(struct ci_single_dpm_table *table,
3104 u32 value, u32 *boot_level)
3105{
3106 u32 i;
3107 int ret = -EINVAL;
3108
3109 for(i = 0; i < table->count; i++) {
3110 if (value == table->dpm_levels[i].value) {
3111 *boot_level = i;
3112 ret = 0;
3113 }
3114 }
3115
3116 return ret;
3117}
3118
3119static int ci_init_smc_table(struct radeon_device *rdev)
3120{
3121 struct ci_power_info *pi = ci_get_pi(rdev);
3122 struct ci_ulv_parm *ulv = &pi->ulv;
3123 struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps;
3124 SMU7_Discrete_DpmTable *table = &pi->smc_state_table;
3125 int ret;
3126
3127 ret = ci_setup_default_dpm_tables(rdev);
3128 if (ret)
3129 return ret;
3130
3131 if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE)
3132 ci_populate_smc_voltage_tables(rdev, table);
3133
3134 ci_init_fps_limits(rdev);
3135
3136 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)
3137 table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
3138
3139 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
3140 table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
3141
3142 if (pi->mem_gddr5)
3143 table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
3144
3145 if (ulv->supported) {
3146 ret = ci_populate_ulv_state(rdev, &pi->smc_state_table.Ulv);
3147 if (ret)
3148 return ret;
3149 WREG32_SMC(CG_ULV_PARAMETER, ulv->cg_ulv_parameter);
3150 }
3151
3152 ret = ci_populate_all_graphic_levels(rdev);
3153 if (ret)
3154 return ret;
3155
3156 ret = ci_populate_all_memory_levels(rdev);
3157 if (ret)
3158 return ret;
3159
3160 ci_populate_smc_link_level(rdev, table);
3161
3162 ret = ci_populate_smc_acpi_level(rdev, table);
3163 if (ret)
3164 return ret;
3165
3166 ret = ci_populate_smc_vce_level(rdev, table);
3167 if (ret)
3168 return ret;
3169
3170 ret = ci_populate_smc_acp_level(rdev, table);
3171 if (ret)
3172 return ret;
3173
3174 ret = ci_populate_smc_samu_level(rdev, table);
3175 if (ret)
3176 return ret;
3177
3178 ret = ci_do_program_memory_timing_parameters(rdev);
3179 if (ret)
3180 return ret;
3181
3182 ret = ci_populate_smc_uvd_level(rdev, table);
3183 if (ret)
3184 return ret;
3185
3186 table->UvdBootLevel = 0;
3187 table->VceBootLevel = 0;
3188 table->AcpBootLevel = 0;
3189 table->SamuBootLevel = 0;
3190 table->GraphicsBootLevel = 0;
3191 table->MemoryBootLevel = 0;
3192
3193 ret = ci_find_boot_level(&pi->dpm_table.sclk_table,
3194 pi->vbios_boot_state.sclk_bootup_value,
3195 (u32 *)&pi->smc_state_table.GraphicsBootLevel);
3196
3197 ret = ci_find_boot_level(&pi->dpm_table.mclk_table,
3198 pi->vbios_boot_state.mclk_bootup_value,
3199 (u32 *)&pi->smc_state_table.MemoryBootLevel);
3200
3201 table->BootVddc = pi->vbios_boot_state.vddc_bootup_value;
3202 table->BootVddci = pi->vbios_boot_state.vddci_bootup_value;
3203 table->BootMVdd = pi->vbios_boot_state.mvdd_bootup_value;
3204
3205 ci_populate_smc_initial_state(rdev, radeon_boot_state);
3206
3207 ret = ci_populate_bapm_parameters_in_dpm_table(rdev);
3208 if (ret)
3209 return ret;
3210
3211 table->UVDInterval = 1;
3212 table->VCEInterval = 1;
3213 table->ACPInterval = 1;
3214 table->SAMUInterval = 1;
3215 table->GraphicsVoltageChangeEnable = 1;
3216 table->GraphicsThermThrottleEnable = 1;
3217 table->GraphicsInterval = 1;
3218 table->VoltageInterval = 1;
3219 table->ThermalInterval = 1;
3220 table->TemperatureLimitHigh = (u16)((pi->thermal_temp_setting.temperature_high *
3221 CISLANDS_Q88_FORMAT_CONVERSION_UNIT) / 1000);
3222 table->TemperatureLimitLow = (u16)((pi->thermal_temp_setting.temperature_low *
3223 CISLANDS_Q88_FORMAT_CONVERSION_UNIT) / 1000);
3224 table->MemoryVoltageChangeEnable = 1;
3225 table->MemoryInterval = 1;
3226 table->VoltageResponseTime = 0;
3227 table->VddcVddciDelta = 4000;
3228 table->PhaseResponseTime = 0;
3229 table->MemoryThermThrottleEnable = 1;
3230 table->PCIeBootLinkLevel = 0;
3231 table->PCIeGenInterval = 1;
3232 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2)
3233 table->SVI2Enable = 1;
3234 else
3235 table->SVI2Enable = 0;
3236
3237 table->ThermGpio = 17;
3238 table->SclkStepSize = 0x4000;
3239
3240 table->SystemFlags = cpu_to_be32(table->SystemFlags);
3241 table->SmioMaskVddcVid = cpu_to_be32(table->SmioMaskVddcVid);
3242 table->SmioMaskVddcPhase = cpu_to_be32(table->SmioMaskVddcPhase);
3243 table->SmioMaskVddciVid = cpu_to_be32(table->SmioMaskVddciVid);
3244 table->SmioMaskMvddVid = cpu_to_be32(table->SmioMaskMvddVid);
3245 table->SclkStepSize = cpu_to_be32(table->SclkStepSize);
3246 table->TemperatureLimitHigh = cpu_to_be16(table->TemperatureLimitHigh);
3247 table->TemperatureLimitLow = cpu_to_be16(table->TemperatureLimitLow);
3248 table->VddcVddciDelta = cpu_to_be16(table->VddcVddciDelta);
3249 table->VoltageResponseTime = cpu_to_be16(table->VoltageResponseTime);
3250 table->PhaseResponseTime = cpu_to_be16(table->PhaseResponseTime);
3251 table->BootVddc = cpu_to_be16(table->BootVddc * VOLTAGE_SCALE);
3252 table->BootVddci = cpu_to_be16(table->BootVddci * VOLTAGE_SCALE);
3253 table->BootMVdd = cpu_to_be16(table->BootMVdd * VOLTAGE_SCALE);
3254
3255 ret = ci_copy_bytes_to_smc(rdev,
3256 pi->dpm_table_start +
3257 offsetof(SMU7_Discrete_DpmTable, SystemFlags),
3258 (u8 *)&table->SystemFlags,
3259 sizeof(SMU7_Discrete_DpmTable) - 3 * sizeof(SMU7_PIDController),
3260 pi->sram_end);
3261 if (ret)
3262 return ret;
3263
3264 return 0;
3265}
3266
3267static void ci_trim_single_dpm_states(struct radeon_device *rdev,
3268 struct ci_single_dpm_table *dpm_table,
3269 u32 low_limit, u32 high_limit)
3270{
3271 u32 i;
3272
3273 for (i = 0; i < dpm_table->count; i++) {
3274 if ((dpm_table->dpm_levels[i].value < low_limit) ||
3275 (dpm_table->dpm_levels[i].value > high_limit))
3276 dpm_table->dpm_levels[i].enabled = false;
3277 else
3278 dpm_table->dpm_levels[i].enabled = true;
3279 }
3280}
3281
3282static void ci_trim_pcie_dpm_states(struct radeon_device *rdev,
3283 u32 speed_low, u32 lanes_low,
3284 u32 speed_high, u32 lanes_high)
3285{
3286 struct ci_power_info *pi = ci_get_pi(rdev);
3287 struct ci_single_dpm_table *pcie_table = &pi->dpm_table.pcie_speed_table;
3288 u32 i, j;
3289
3290 for (i = 0; i < pcie_table->count; i++) {
3291 if ((pcie_table->dpm_levels[i].value < speed_low) ||
3292 (pcie_table->dpm_levels[i].param1 < lanes_low) ||
3293 (pcie_table->dpm_levels[i].value > speed_high) ||
3294 (pcie_table->dpm_levels[i].param1 > lanes_high))
3295 pcie_table->dpm_levels[i].enabled = false;
3296 else
3297 pcie_table->dpm_levels[i].enabled = true;
3298 }
3299
3300 for (i = 0; i < pcie_table->count; i++) {
3301 if (pcie_table->dpm_levels[i].enabled) {
3302 for (j = i + 1; j < pcie_table->count; j++) {
3303 if (pcie_table->dpm_levels[j].enabled) {
3304 if ((pcie_table->dpm_levels[i].value == pcie_table->dpm_levels[j].value) &&
3305 (pcie_table->dpm_levels[i].param1 == pcie_table->dpm_levels[j].param1))
3306 pcie_table->dpm_levels[j].enabled = false;
3307 }
3308 }
3309 }
3310 }
3311}
3312
3313static int ci_trim_dpm_states(struct radeon_device *rdev,
3314 struct radeon_ps *radeon_state)
3315{
3316 struct ci_ps *state = ci_get_ps(radeon_state);
3317 struct ci_power_info *pi = ci_get_pi(rdev);
3318 u32 high_limit_count;
3319
3320 if (state->performance_level_count < 1)
3321 return -EINVAL;
3322
3323 if (state->performance_level_count == 1)
3324 high_limit_count = 0;
3325 else
3326 high_limit_count = 1;
3327
3328 ci_trim_single_dpm_states(rdev,
3329 &pi->dpm_table.sclk_table,
3330 state->performance_levels[0].sclk,
3331 state->performance_levels[high_limit_count].sclk);
3332
3333 ci_trim_single_dpm_states(rdev,
3334 &pi->dpm_table.mclk_table,
3335 state->performance_levels[0].mclk,
3336 state->performance_levels[high_limit_count].mclk);
3337
3338 ci_trim_pcie_dpm_states(rdev,
3339 state->performance_levels[0].pcie_gen,
3340 state->performance_levels[0].pcie_lane,
3341 state->performance_levels[high_limit_count].pcie_gen,
3342 state->performance_levels[high_limit_count].pcie_lane);
3343
3344 return 0;
3345}
3346
3347static int ci_apply_disp_minimum_voltage_request(struct radeon_device *rdev)
3348{
3349 struct radeon_clock_voltage_dependency_table *disp_voltage_table =
3350 &rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk;
3351 struct radeon_clock_voltage_dependency_table *vddc_table =
3352 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
3353 u32 requested_voltage = 0;
3354 u32 i;
3355
3356 if (disp_voltage_table == NULL)
3357 return -EINVAL;
3358 if (!disp_voltage_table->count)
3359 return -EINVAL;
3360
3361 for (i = 0; i < disp_voltage_table->count; i++) {
3362 if (rdev->clock.current_dispclk == disp_voltage_table->entries[i].clk)
3363 requested_voltage = disp_voltage_table->entries[i].v;
3364 }
3365
3366 for (i = 0; i < vddc_table->count; i++) {
3367 if (requested_voltage <= vddc_table->entries[i].v) {
3368 requested_voltage = vddc_table->entries[i].v;
3369 return (ci_send_msg_to_smc_with_parameter(rdev,
3370 PPSMC_MSG_VddC_Request,
3371 requested_voltage * VOLTAGE_SCALE) == PPSMC_Result_OK) ?
3372 0 : -EINVAL;
3373 }
3374 }
3375
3376 return -EINVAL;
3377}
3378
3379static int ci_upload_dpm_level_enable_mask(struct radeon_device *rdev)
3380{
3381 struct ci_power_info *pi = ci_get_pi(rdev);
3382 PPSMC_Result result;
3383
3384 if (!pi->sclk_dpm_key_disabled) {
3385 if (pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3386 result = ci_send_msg_to_smc_with_parameter(rdev,
3387 PPSMC_MSG_SCLKDPM_SetEnabledMask,
3388 pi->dpm_level_enable_mask.sclk_dpm_enable_mask);
3389 if (result != PPSMC_Result_OK)
3390 return -EINVAL;
3391 }
3392 }
3393
3394 if (!pi->mclk_dpm_key_disabled) {
3395 if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3396 result = ci_send_msg_to_smc_with_parameter(rdev,
3397 PPSMC_MSG_MCLKDPM_SetEnabledMask,
3398 pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
3399 if (result != PPSMC_Result_OK)
3400 return -EINVAL;
3401 }
3402 }
3403
3404 if (!pi->pcie_dpm_key_disabled) {
3405 if (pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3406 result = ci_send_msg_to_smc_with_parameter(rdev,
3407 PPSMC_MSG_PCIeDPM_SetEnabledMask,
3408 pi->dpm_level_enable_mask.pcie_dpm_enable_mask);
3409 if (result != PPSMC_Result_OK)
3410 return -EINVAL;
3411 }
3412 }
3413
3414 ci_apply_disp_minimum_voltage_request(rdev);
3415
3416 return 0;
3417}
3418
3419static void ci_find_dpm_states_clocks_in_dpm_table(struct radeon_device *rdev,
3420 struct radeon_ps *radeon_state)
3421{
3422 struct ci_power_info *pi = ci_get_pi(rdev);
3423 struct ci_ps *state = ci_get_ps(radeon_state);
3424 struct ci_single_dpm_table *sclk_table = &pi->dpm_table.sclk_table;
3425 u32 sclk = state->performance_levels[state->performance_level_count-1].sclk;
3426 struct ci_single_dpm_table *mclk_table = &pi->dpm_table.mclk_table;
3427 u32 mclk = state->performance_levels[state->performance_level_count-1].mclk;
3428 u32 i;
3429
3430 pi->need_update_smu7_dpm_table = 0;
3431
3432 for (i = 0; i < sclk_table->count; i++) {
3433 if (sclk == sclk_table->dpm_levels[i].value)
3434 break;
3435 }
3436
3437 if (i >= sclk_table->count) {
3438 pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
3439 } else {
3440 /* XXX check display min clock requirements */
3441 if (0 != CISLAND_MINIMUM_ENGINE_CLOCK)
3442 pi->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK;
3443 }
3444
3445 for (i = 0; i < mclk_table->count; i++) {
3446 if (mclk == mclk_table->dpm_levels[i].value)
3447 break;
3448 }
3449
3450 if (i >= mclk_table->count)
3451 pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
3452
3453 if (rdev->pm.dpm.current_active_crtc_count !=
3454 rdev->pm.dpm.new_active_crtc_count)
3455 pi->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK;
3456}
3457
3458static int ci_populate_and_upload_sclk_mclk_dpm_levels(struct radeon_device *rdev,
3459 struct radeon_ps *radeon_state)
3460{
3461 struct ci_power_info *pi = ci_get_pi(rdev);
3462 struct ci_ps *state = ci_get_ps(radeon_state);
3463 u32 sclk = state->performance_levels[state->performance_level_count-1].sclk;
3464 u32 mclk = state->performance_levels[state->performance_level_count-1].mclk;
3465 struct ci_dpm_table *dpm_table = &pi->dpm_table;
3466 int ret;
3467
3468 if (!pi->need_update_smu7_dpm_table)
3469 return 0;
3470
3471 if (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK)
3472 dpm_table->sclk_table.dpm_levels[dpm_table->sclk_table.count-1].value = sclk;
3473
3474 if (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)
3475 dpm_table->mclk_table.dpm_levels[dpm_table->mclk_table.count-1].value = mclk;
3476
3477 if (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK)) {
3478 ret = ci_populate_all_graphic_levels(rdev);
3479 if (ret)
3480 return ret;
3481 }
3482
3483 if (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_MCLK | DPMTABLE_UPDATE_MCLK)) {
3484 ret = ci_populate_all_memory_levels(rdev);
3485 if (ret)
3486 return ret;
3487 }
3488
3489 return 0;
3490}
3491
3492static int ci_enable_uvd_dpm(struct radeon_device *rdev, bool enable)
3493{
3494 struct ci_power_info *pi = ci_get_pi(rdev);
3495 const struct radeon_clock_and_voltage_limits *max_limits;
3496 int i;
3497
3498 if (rdev->pm.dpm.ac_power)
3499 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3500 else
3501 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3502
3503 if (enable) {
3504 pi->dpm_level_enable_mask.uvd_dpm_enable_mask = 0;
3505
3506 for (i = rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
3507 if (rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
3508 pi->dpm_level_enable_mask.uvd_dpm_enable_mask |= 1 << i;
3509
3510 if (!pi->caps_uvd_dpm)
3511 break;
3512 }
3513 }
3514
3515 ci_send_msg_to_smc_with_parameter(rdev,
3516 PPSMC_MSG_UVDDPM_SetEnabledMask,
3517 pi->dpm_level_enable_mask.uvd_dpm_enable_mask);
3518
3519 if (pi->last_mclk_dpm_enable_mask & 0x1) {
3520 pi->uvd_enabled = true;
3521 pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE;
3522 ci_send_msg_to_smc_with_parameter(rdev,
3523 PPSMC_MSG_MCLKDPM_SetEnabledMask,
3524 pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
3525 }
3526 } else {
3527 if (pi->last_mclk_dpm_enable_mask & 0x1) {
3528 pi->uvd_enabled = false;
3529 pi->dpm_level_enable_mask.mclk_dpm_enable_mask |= 1;
3530 ci_send_msg_to_smc_with_parameter(rdev,
3531 PPSMC_MSG_MCLKDPM_SetEnabledMask,
3532 pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
3533 }
3534 }
3535
3536 return (ci_send_msg_to_smc(rdev, enable ?
3537 PPSMC_MSG_UVDDPM_Enable : PPSMC_MSG_UVDDPM_Disable) == PPSMC_Result_OK) ?
3538 0 : -EINVAL;
3539}
3540
cc8dbbb4
AD		 3541static int ci_enable_vce_dpm(struct radeon_device *rdev, bool enable)
3542{
3543 struct ci_power_info *pi = ci_get_pi(rdev);
3544 const struct radeon_clock_and_voltage_limits *max_limits;
3545 int i;
3546
3547 if (rdev->pm.dpm.ac_power)
3548 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3549 else
3550 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3551
3552 if (enable) {
3553 pi->dpm_level_enable_mask.vce_dpm_enable_mask = 0;
3554 for (i = rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
3555 if (rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
3556 pi->dpm_level_enable_mask.vce_dpm_enable_mask |= 1 << i;
3557
3558 if (!pi->caps_vce_dpm)
3559 break;
3560 }
3561 }
3562
3563 ci_send_msg_to_smc_with_parameter(rdev,
3564 PPSMC_MSG_VCEDPM_SetEnabledMask,
3565 pi->dpm_level_enable_mask.vce_dpm_enable_mask);
3566 }
3567
3568 return (ci_send_msg_to_smc(rdev, enable ?
3569 PPSMC_MSG_VCEDPM_Enable : PPSMC_MSG_VCEDPM_Disable) == PPSMC_Result_OK) ?
3570 0 : -EINVAL;
3571}
3572
8cd36682 3573#if 0
cc8dbbb4
AD		 3574static int ci_enable_samu_dpm(struct radeon_device *rdev, bool enable)
3575{
3576 struct ci_power_info *pi = ci_get_pi(rdev);
3577 const struct radeon_clock_and_voltage_limits *max_limits;
3578 int i;
3579
3580 if (rdev->pm.dpm.ac_power)
3581 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3582 else
3583 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3584
3585 if (enable) {
3586 pi->dpm_level_enable_mask.samu_dpm_enable_mask = 0;
3587 for (i = rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
3588 if (rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
3589 pi->dpm_level_enable_mask.samu_dpm_enable_mask |= 1 << i;
3590
3591 if (!pi->caps_samu_dpm)
3592 break;
3593 }
3594 }
3595
3596 ci_send_msg_to_smc_with_parameter(rdev,
3597 PPSMC_MSG_SAMUDPM_SetEnabledMask,
3598 pi->dpm_level_enable_mask.samu_dpm_enable_mask);
3599 }
3600 return (ci_send_msg_to_smc(rdev, enable ?
3601 PPSMC_MSG_SAMUDPM_Enable : PPSMC_MSG_SAMUDPM_Disable) == PPSMC_Result_OK) ?
3602 0 : -EINVAL;
3603}
3604
3605static int ci_enable_acp_dpm(struct radeon_device *rdev, bool enable)
3606{
3607 struct ci_power_info *pi = ci_get_pi(rdev);
3608 const struct radeon_clock_and_voltage_limits *max_limits;
3609 int i;
3610
3611 if (rdev->pm.dpm.ac_power)
3612 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3613 else
3614 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3615
3616 if (enable) {
3617 pi->dpm_level_enable_mask.acp_dpm_enable_mask = 0;
3618 for (i = rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
3619 if (rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
3620 pi->dpm_level_enable_mask.acp_dpm_enable_mask |= 1 << i;
3621
3622 if (!pi->caps_acp_dpm)
3623 break;
3624 }
3625 }
3626
3627 ci_send_msg_to_smc_with_parameter(rdev,
3628 PPSMC_MSG_ACPDPM_SetEnabledMask,
3629 pi->dpm_level_enable_mask.acp_dpm_enable_mask);
3630 }
3631
3632 return (ci_send_msg_to_smc(rdev, enable ?
3633 PPSMC_MSG_ACPDPM_Enable : PPSMC_MSG_ACPDPM_Disable) == PPSMC_Result_OK) ?
3634 0 : -EINVAL;
3635}
3636#endif
3637
3638static int ci_update_uvd_dpm(struct radeon_device *rdev, bool gate)
3639{
3640 struct ci_power_info *pi = ci_get_pi(rdev);
3641 u32 tmp;
3642
3643 if (!gate) {
3644 if (pi->caps_uvd_dpm ||
3645 (rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count <= 0))
3646 pi->smc_state_table.UvdBootLevel = 0;
3647 else
3648 pi->smc_state_table.UvdBootLevel =
3649 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count - 1;
3650
3651 tmp = RREG32_SMC(DPM_TABLE_475);
3652 tmp &= ~UvdBootLevel_MASK;
3653 tmp |= UvdBootLevel(pi->smc_state_table.UvdBootLevel);
3654 WREG32_SMC(DPM_TABLE_475, tmp);
3655 }
3656
3657 return ci_enable_uvd_dpm(rdev, !gate);
3658}
3659
cc8dbbb4
AD		 3660static u8 ci_get_vce_boot_level(struct radeon_device *rdev)
3661{
3662 u8 i;
3663 u32 min_evclk = 30000; /* ??? */
3664 struct radeon_vce_clock_voltage_dependency_table *table =
3665 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
3666
3667 for (i = 0; i < table->count; i++) {
3668 if (table->entries[i].evclk >= min_evclk)
3669 return i;
3670 }
3671
3672 return table->count - 1;
3673}
3674
3675static int ci_update_vce_dpm(struct radeon_device *rdev,
3676 struct radeon_ps *radeon_new_state,
3677 struct radeon_ps *radeon_current_state)
3678{
3679 struct ci_power_info *pi = ci_get_pi(rdev);
cc8dbbb4
AD		 3680 int ret = 0;
3681 u32 tmp;
3682
8cd36682
AD		 3683 if (radeon_current_state->evclk != radeon_new_state->evclk) {
3684 if (radeon_new_state->evclk) {
a1d6f97c
AD		 3685 /* turn the clocks on when encoding */
3686 cik_update_cg(rdev, RADEON_CG_BLOCK_VCE, false);
cc8dbbb4 3687
a1d6f97c 3688 pi->smc_state_table.VceBootLevel = ci_get_vce_boot_level(rdev);
cc8dbbb4
AD		 3689 tmp = RREG32_SMC(DPM_TABLE_475);
3690 tmp &= ~VceBootLevel_MASK;
3691 tmp |= VceBootLevel(pi->smc_state_table.VceBootLevel);
3692 WREG32_SMC(DPM_TABLE_475, tmp);
3693
3694 ret = ci_enable_vce_dpm(rdev, true);
3695 } else {
a1d6f97c
AD		 3696 /* turn the clocks off when not encoding */
3697 cik_update_cg(rdev, RADEON_CG_BLOCK_VCE, true);
3698
cc8dbbb4
AD		 3699 ret = ci_enable_vce_dpm(rdev, false);
3700 }
3701 }
3702 return ret;
3703}
3704
8cd36682 3705#if 0
cc8dbbb4
AD		 3706static int ci_update_samu_dpm(struct radeon_device *rdev, bool gate)
3707{
3708 return ci_enable_samu_dpm(rdev, gate);
3709}
3710
3711static int ci_update_acp_dpm(struct radeon_device *rdev, bool gate)
3712{
3713 struct ci_power_info *pi = ci_get_pi(rdev);
3714 u32 tmp;
3715
3716 if (!gate) {
3717 pi->smc_state_table.AcpBootLevel = 0;
3718
3719 tmp = RREG32_SMC(DPM_TABLE_475);
3720 tmp &= ~AcpBootLevel_MASK;
3721 tmp |= AcpBootLevel(pi->smc_state_table.AcpBootLevel);
3722 WREG32_SMC(DPM_TABLE_475, tmp);
3723 }
3724
3725 return ci_enable_acp_dpm(rdev, !gate);
3726}
3727#endif
3728
3729static int ci_generate_dpm_level_enable_mask(struct radeon_device *rdev,
3730 struct radeon_ps *radeon_state)
3731{
3732 struct ci_power_info *pi = ci_get_pi(rdev);
3733 int ret;
3734
3735 ret = ci_trim_dpm_states(rdev, radeon_state);
3736 if (ret)
3737 return ret;
3738
3739 pi->dpm_level_enable_mask.sclk_dpm_enable_mask =
3740 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.sclk_table);
3741 pi->dpm_level_enable_mask.mclk_dpm_enable_mask =
3742 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.mclk_table);
3743 pi->last_mclk_dpm_enable_mask =
3744 pi->dpm_level_enable_mask.mclk_dpm_enable_mask;
3745 if (pi->uvd_enabled) {
3746 if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask & 1)
3747 pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE;
3748 }
3749 pi->dpm_level_enable_mask.pcie_dpm_enable_mask =
3750 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.pcie_speed_table);
3751
3752 return 0;
3753}
3754
89536fd6
AD		 3755static u32 ci_get_lowest_enabled_level(struct radeon_device *rdev,
3756 u32 level_mask)
3757{
3758 u32 level = 0;
3759
3760 while ((level_mask & (1 << level)) == 0)
3761 level++;
3762
3763 return level;
3764}
3765
3766
3767int ci_dpm_force_performance_level(struct radeon_device *rdev,
3768 enum radeon_dpm_forced_level level)
3769{
3770 struct ci_power_info *pi = ci_get_pi(rdev);
89536fd6
AD		 3771 u32 tmp, levels, i;
3772 int ret;
3773
3774 if (level == RADEON_DPM_FORCED_LEVEL_HIGH) {
3775 if ((!pi->sclk_dpm_key_disabled) &&
3776 pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3777 levels = 0;
3778 tmp = pi->dpm_level_enable_mask.sclk_dpm_enable_mask;
3779 while (tmp >>= 1)
3780 levels++;
3781 if (levels) {
3782 ret = ci_dpm_force_state_sclk(rdev, levels);
3783 if (ret)
3784 return ret;
3785 for (i = 0; i < rdev->usec_timeout; i++) {
3786 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) &
3787 CURR_SCLK_INDEX_MASK) >> CURR_SCLK_INDEX_SHIFT;
3788 if (tmp == levels)
3789 break;
3790 udelay(1);
3791 }
3792 }
3793 }
3794 if ((!pi->mclk_dpm_key_disabled) &&
3795 pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3796 levels = 0;
3797 tmp = pi->dpm_level_enable_mask.mclk_dpm_enable_mask;
3798 while (tmp >>= 1)
3799 levels++;
3800 if (levels) {
3801 ret = ci_dpm_force_state_mclk(rdev, levels);
3802 if (ret)
3803 return ret;
3804 for (i = 0; i < rdev->usec_timeout; i++) {
3805 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) &
3806 CURR_MCLK_INDEX_MASK) >> CURR_MCLK_INDEX_SHIFT;
3807 if (tmp == levels)
3808 break;
3809 udelay(1);
3810 }
3811 }
3812 }
3813 if ((!pi->pcie_dpm_key_disabled) &&
3814 pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3815 levels = 0;
3816 tmp = pi->dpm_level_enable_mask.pcie_dpm_enable_mask;
3817 while (tmp >>= 1)
3818 levels++;
3819 if (levels) {
3820 ret = ci_dpm_force_state_pcie(rdev, level);
3821 if (ret)
3822 return ret;
3823 for (i = 0; i < rdev->usec_timeout; i++) {
3824 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX_1) &
3825 CURR_PCIE_INDEX_MASK) >> CURR_PCIE_INDEX_SHIFT;
3826 if (tmp == levels)
3827 break;
3828 udelay(1);
3829 }
3830 }
3831 }
3832 } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) {
3833 if ((!pi->sclk_dpm_key_disabled) &&
3834 pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3835 levels = ci_get_lowest_enabled_level(rdev,
3836 pi->dpm_level_enable_mask.sclk_dpm_enable_mask);
3837 ret = ci_dpm_force_state_sclk(rdev, levels);
3838 if (ret)
3839 return ret;
3840 for (i = 0; i < rdev->usec_timeout; i++) {
3841 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) &
3842 CURR_SCLK_INDEX_MASK) >> CURR_SCLK_INDEX_SHIFT;
3843 if (tmp == levels)
3844 break;
3845 udelay(1);
3846 }
3847 }
3848 if ((!pi->mclk_dpm_key_disabled) &&
3849 pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3850 levels = ci_get_lowest_enabled_level(rdev,
3851 pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
3852 ret = ci_dpm_force_state_mclk(rdev, levels);
3853 if (ret)
3854 return ret;
3855 for (i = 0; i < rdev->usec_timeout; i++) {
3856 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) &
3857 CURR_MCLK_INDEX_MASK) >> CURR_MCLK_INDEX_SHIFT;
3858 if (tmp == levels)
3859 break;
3860 udelay(1);
3861 }
3862 }
3863 if ((!pi->pcie_dpm_key_disabled) &&
3864 pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3865 levels = ci_get_lowest_enabled_level(rdev,
3866 pi->dpm_level_enable_mask.pcie_dpm_enable_mask);
3867 ret = ci_dpm_force_state_pcie(rdev, levels);
3868 if (ret)
3869 return ret;
3870 for (i = 0; i < rdev->usec_timeout; i++) {
3871 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX_1) &
3872 CURR_PCIE_INDEX_MASK) >> CURR_PCIE_INDEX_SHIFT;
3873 if (tmp == levels)
3874 break;
3875 udelay(1);
3876 }
3877 }
3878 } else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) {
1c52279f
AD		 3879 ret = ci_upload_dpm_level_enable_mask(rdev);
3880 if (ret)
3881 return ret;
89536fd6
AD		 3882 }
3883
3884 rdev->pm.dpm.forced_level = level;
3885
3886 return 0;
3887}
3888
cc8dbbb4
AD		 3889static int ci_set_mc_special_registers(struct radeon_device *rdev,
3890 struct ci_mc_reg_table *table)
3891{
3892 struct ci_power_info *pi = ci_get_pi(rdev);
3893 u8 i, j, k;
3894 u32 temp_reg;
3895
3896 for (i = 0, j = table->last; i < table->last; i++) {
3897 if (j >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
3898 return -EINVAL;
3899 switch(table->mc_reg_address[i].s1 << 2) {
3900 case MC_SEQ_MISC1:
3901 temp_reg = RREG32(MC_PMG_CMD_EMRS);
3902 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2;
3903 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
3904 for (k = 0; k < table->num_entries; k++) {
3905 table->mc_reg_table_entry[k].mc_data[j] =
3906 ((temp_reg & 0xffff0000)) | ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
3907 }
3908 j++;
3909 if (j >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
3910 return -EINVAL;
3911
3912 temp_reg = RREG32(MC_PMG_CMD_MRS);
3913 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2;
3914 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2;
3915 for (k = 0; k < table->num_entries; k++) {
3916 table->mc_reg_table_entry[k].mc_data[j] =
3917 (temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
3918 if (!pi->mem_gddr5)
3919 table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
3920 }
3921 j++;
3922 if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
3923 return -EINVAL;
3924
3925 if (!pi->mem_gddr5) {
3926 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD >> 2;
3927 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD >> 2;
3928 for (k = 0; k < table->num_entries; k++) {
3929 table->mc_reg_table_entry[k].mc_data[j] =
3930 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
3931 }
3932 j++;
3933 if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
3934 return -EINVAL;
3935 }
3936 break;
3937 case MC_SEQ_RESERVE_M:
3938 temp_reg = RREG32(MC_PMG_CMD_MRS1);
3939 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2;
3940 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
3941 for (k = 0; k < table->num_entries; k++) {
3942 table->mc_reg_table_entry[k].mc_data[j] =
3943 (temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
3944 }
3945 j++;
3946 if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
3947 return -EINVAL;
3948 break;
3949 default:
3950 break;
3951 }
3952
3953 }
3954
3955 table->last = j;
3956
3957 return 0;
3958}
3959
3960static bool ci_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg)
3961{
3962 bool result = true;
3963
3964 switch(in_reg) {
3965 case MC_SEQ_RAS_TIMING >> 2:
3966 *out_reg = MC_SEQ_RAS_TIMING_LP >> 2;
3967 break;
3968 case MC_SEQ_DLL_STBY >> 2:
3969 *out_reg = MC_SEQ_DLL_STBY_LP >> 2;
3970 break;
3971 case MC_SEQ_G5PDX_CMD0 >> 2:
3972 *out_reg = MC_SEQ_G5PDX_CMD0_LP >> 2;
3973 break;
3974 case MC_SEQ_G5PDX_CMD1 >> 2:
3975 *out_reg = MC_SEQ_G5PDX_CMD1_LP >> 2;
3976 break;
3977 case MC_SEQ_G5PDX_CTRL >> 2:
3978 *out_reg = MC_SEQ_G5PDX_CTRL_LP >> 2;
3979 break;
3980 case MC_SEQ_CAS_TIMING >> 2:
3981 *out_reg = MC_SEQ_CAS_TIMING_LP >> 2;
3982 break;
3983 case MC_SEQ_MISC_TIMING >> 2:
3984 *out_reg = MC_SEQ_MISC_TIMING_LP >> 2;
3985 break;
3986 case MC_SEQ_MISC_TIMING2 >> 2:
3987 *out_reg = MC_SEQ_MISC_TIMING2_LP >> 2;
3988 break;
3989 case MC_SEQ_PMG_DVS_CMD >> 2:
3990 *out_reg = MC_SEQ_PMG_DVS_CMD_LP >> 2;
3991 break;
3992 case MC_SEQ_PMG_DVS_CTL >> 2:
3993 *out_reg = MC_SEQ_PMG_DVS_CTL_LP >> 2;
3994 break;
3995 case MC_SEQ_RD_CTL_D0 >> 2:
3996 *out_reg = MC_SEQ_RD_CTL_D0_LP >> 2;
3997 break;
3998 case MC_SEQ_RD_CTL_D1 >> 2:
3999 *out_reg = MC_SEQ_RD_CTL_D1_LP >> 2;
4000 break;
4001 case MC_SEQ_WR_CTL_D0 >> 2:
4002 *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2;
4003 break;
4004 case MC_SEQ_WR_CTL_D1 >> 2:
4005 *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2;
4006 break;
4007 case MC_PMG_CMD_EMRS >> 2:
4008 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
4009 break;
4010 case MC_PMG_CMD_MRS >> 2:
4011 *out_reg = MC_SEQ_PMG_CMD_MRS_LP >> 2;
4012 break;
4013 case MC_PMG_CMD_MRS1 >> 2:
4014 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
4015 break;
4016 case MC_SEQ_PMG_TIMING >> 2:
4017 *out_reg = MC_SEQ_PMG_TIMING_LP >> 2;
4018 break;
4019 case MC_PMG_CMD_MRS2 >> 2:
4020 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP >> 2;
4021 break;
4022 case MC_SEQ_WR_CTL_2 >> 2:
4023 *out_reg = MC_SEQ_WR_CTL_2_LP >> 2;
4024 break;
4025 default:
4026 result = false;
4027 break;
4028 }
4029
4030 return result;
4031}
4032
4033static void ci_set_valid_flag(struct ci_mc_reg_table *table)
4034{
4035 u8 i, j;
4036
4037 for (i = 0; i < table->last; i++) {
4038 for (j = 1; j < table->num_entries; j++) {
4039 if (table->mc_reg_table_entry[j-1].mc_data[i] !=
4040 table->mc_reg_table_entry[j].mc_data[i]) {
4041 table->valid_flag |= 1 << i;
4042 break;
4043 }
4044 }
4045 }
4046}
4047
4048static void ci_set_s0_mc_reg_index(struct ci_mc_reg_table *table)
4049{
4050 u32 i;
4051 u16 address;
4052
4053 for (i = 0; i < table->last; i++) {
4054 table->mc_reg_address[i].s0 =
4055 ci_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ?
4056 address : table->mc_reg_address[i].s1;
4057 }
4058}
4059
4060static int ci_copy_vbios_mc_reg_table(const struct atom_mc_reg_table *table,
4061 struct ci_mc_reg_table *ci_table)
4062{
4063 u8 i, j;
4064
4065 if (table->last > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4066 return -EINVAL;
4067 if (table->num_entries > MAX_AC_TIMING_ENTRIES)
4068 return -EINVAL;
4069
4070 for (i = 0; i < table->last; i++)
4071 ci_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
4072
4073 ci_table->last = table->last;
4074
4075 for (i = 0; i < table->num_entries; i++) {
4076 ci_table->mc_reg_table_entry[i].mclk_max =
4077 table->mc_reg_table_entry[i].mclk_max;
4078 for (j = 0; j < table->last; j++)
4079 ci_table->mc_reg_table_entry[i].mc_data[j] =
4080 table->mc_reg_table_entry[i].mc_data[j];
4081 }
4082 ci_table->num_entries = table->num_entries;
4083
4084 return 0;
4085}
4086
4087static int ci_initialize_mc_reg_table(struct radeon_device *rdev)
4088{
4089 struct ci_power_info *pi = ci_get_pi(rdev);
4090 struct atom_mc_reg_table *table;
4091 struct ci_mc_reg_table *ci_table = &pi->mc_reg_table;
4092 u8 module_index = rv770_get_memory_module_index(rdev);
4093 int ret;
4094
4095 table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL);
4096 if (!table)
4097 return -ENOMEM;
4098
4099 WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));
4100 WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));
4101 WREG32(MC_SEQ_DLL_STBY_LP, RREG32(MC_SEQ_DLL_STBY));
4102 WREG32(MC_SEQ_G5PDX_CMD0_LP, RREG32(MC_SEQ_G5PDX_CMD0));
4103 WREG32(MC_SEQ_G5PDX_CMD1_LP, RREG32(MC_SEQ_G5PDX_CMD1));
4104 WREG32(MC_SEQ_G5PDX_CTRL_LP, RREG32(MC_SEQ_G5PDX_CTRL));
4105 WREG32(MC_SEQ_PMG_DVS_CMD_LP, RREG32(MC_SEQ_PMG_DVS_CMD));
4106 WREG32(MC_SEQ_PMG_DVS_CTL_LP, RREG32(MC_SEQ_PMG_DVS_CTL));
4107 WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));
4108 WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));
4109 WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS));
4110 WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS));
4111 WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));
4112 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));
4113 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
4114 WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));
4115 WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));
4116 WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING));
4117 WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2));
4118 WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2));
4119
4120 ret = radeon_atom_init_mc_reg_table(rdev, module_index, table);
4121 if (ret)
4122 goto init_mc_done;
4123
4124 ret = ci_copy_vbios_mc_reg_table(table, ci_table);
4125 if (ret)
4126 goto init_mc_done;
4127
4128 ci_set_s0_mc_reg_index(ci_table);
4129
4130 ret = ci_set_mc_special_registers(rdev, ci_table);
4131 if (ret)
4132 goto init_mc_done;
4133
4134 ci_set_valid_flag(ci_table);
4135
4136init_mc_done:
4137 kfree(table);
4138
4139 return ret;
4140}
4141
4142static int ci_populate_mc_reg_addresses(struct radeon_device *rdev,
4143 SMU7_Discrete_MCRegisters *mc_reg_table)
4144{
4145 struct ci_power_info *pi = ci_get_pi(rdev);
4146 u32 i, j;
4147
4148 for (i = 0, j = 0; j < pi->mc_reg_table.last; j++) {
4149 if (pi->mc_reg_table.valid_flag & (1 << j)) {
4150 if (i >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4151 return -EINVAL;
4152 mc_reg_table->address[i].s0 = cpu_to_be16(pi->mc_reg_table.mc_reg_address[j].s0);
4153 mc_reg_table->address[i].s1 = cpu_to_be16(pi->mc_reg_table.mc_reg_address[j].s1);
4154 i++;
4155 }
4156 }
4157
4158 mc_reg_table->last = (u8)i;
4159
4160 return 0;
4161}
4162
4163static void ci_convert_mc_registers(const struct ci_mc_reg_entry *entry,
4164 SMU7_Discrete_MCRegisterSet *data,
4165 u32 num_entries, u32 valid_flag)
4166{
4167 u32 i, j;
4168
4169 for (i = 0, j = 0; j < num_entries; j++) {
4170 if (valid_flag & (1 << j)) {
4171 data->value[i] = cpu_to_be32(entry->mc_data[j]);
4172 i++;
4173 }
4174 }
4175}
4176
4177static void ci_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev,
4178 const u32 memory_clock,
4179 SMU7_Discrete_MCRegisterSet *mc_reg_table_data)
4180{
4181 struct ci_power_info *pi = ci_get_pi(rdev);
4182 u32 i = 0;
4183
4184 for(i = 0; i < pi->mc_reg_table.num_entries; i++) {
4185 if (memory_clock <= pi->mc_reg_table.mc_reg_table_entry[i].mclk_max)
4186 break;
4187 }
4188
4189 if ((i == pi->mc_reg_table.num_entries) && (i > 0))
4190 --i;
4191
4192 ci_convert_mc_registers(&pi->mc_reg_table.mc_reg_table_entry[i],
4193 mc_reg_table_data, pi->mc_reg_table.last,
4194 pi->mc_reg_table.valid_flag);
4195}
4196
4197static void ci_convert_mc_reg_table_to_smc(struct radeon_device *rdev,
4198 SMU7_Discrete_MCRegisters *mc_reg_table)
4199{
4200 struct ci_power_info *pi = ci_get_pi(rdev);
4201 u32 i;
4202
4203 for (i = 0; i < pi->dpm_table.mclk_table.count; i++)
4204 ci_convert_mc_reg_table_entry_to_smc(rdev,
4205 pi->dpm_table.mclk_table.dpm_levels[i].value,
4206 &mc_reg_table->data[i]);
4207}
4208
4209static int ci_populate_initial_mc_reg_table(struct radeon_device *rdev)
4210{
4211 struct ci_power_info *pi = ci_get_pi(rdev);
4212 int ret;
4213
4214 memset(&pi->smc_mc_reg_table, 0, sizeof(SMU7_Discrete_MCRegisters));
4215
4216 ret = ci_populate_mc_reg_addresses(rdev, &pi->smc_mc_reg_table);
4217 if (ret)
4218 return ret;
4219 ci_convert_mc_reg_table_to_smc(rdev, &pi->smc_mc_reg_table);
4220
4221 return ci_copy_bytes_to_smc(rdev,
4222 pi->mc_reg_table_start,
4223 (u8 *)&pi->smc_mc_reg_table,
4224 sizeof(SMU7_Discrete_MCRegisters),
4225 pi->sram_end);
4226}
4227
4228static int ci_update_and_upload_mc_reg_table(struct radeon_device *rdev)
4229{
4230 struct ci_power_info *pi = ci_get_pi(rdev);
4231
4232 if (!(pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK))
4233 return 0;
4234
4235 memset(&pi->smc_mc_reg_table, 0, sizeof(SMU7_Discrete_MCRegisters));
4236
4237 ci_convert_mc_reg_table_to_smc(rdev, &pi->smc_mc_reg_table);
4238
4239 return ci_copy_bytes_to_smc(rdev,
4240 pi->mc_reg_table_start +
4241 offsetof(SMU7_Discrete_MCRegisters, data[0]),
4242 (u8 *)&pi->smc_mc_reg_table.data[0],
4243 sizeof(SMU7_Discrete_MCRegisterSet) *
4244 pi->dpm_table.mclk_table.count,
4245 pi->sram_end);
4246}
4247
4248static void ci_enable_voltage_control(struct radeon_device *rdev)
4249{
4250 u32 tmp = RREG32_SMC(GENERAL_PWRMGT);
4251
4252 tmp |= VOLT_PWRMGT_EN;
4253 WREG32_SMC(GENERAL_PWRMGT, tmp);
4254}
4255
4256static enum radeon_pcie_gen ci_get_maximum_link_speed(struct radeon_device *rdev,
4257 struct radeon_ps *radeon_state)
4258{
4259 struct ci_ps *state = ci_get_ps(radeon_state);
4260 int i;
4261 u16 pcie_speed, max_speed = 0;
4262
4263 for (i = 0; i < state->performance_level_count; i++) {
4264 pcie_speed = state->performance_levels[i].pcie_gen;
4265 if (max_speed < pcie_speed)
4266 max_speed = pcie_speed;
4267 }
4268
4269 return max_speed;
4270}
4271
4272static u16 ci_get_current_pcie_speed(struct radeon_device *rdev)
4273{
4274 u32 speed_cntl = 0;
4275
4276 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK;
4277 speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT;
4278
4279 return (u16)speed_cntl;
4280}
4281
4282static int ci_get_current_pcie_lane_number(struct radeon_device *rdev)
4283{
4284 u32 link_width = 0;
4285
4286 link_width = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL) & LC_LINK_WIDTH_RD_MASK;
4287 link_width >>= LC_LINK_WIDTH_RD_SHIFT;
4288
4289 switch (link_width) {
4290 case RADEON_PCIE_LC_LINK_WIDTH_X1:
4291 return 1;
4292 case RADEON_PCIE_LC_LINK_WIDTH_X2:
4293 return 2;
4294 case RADEON_PCIE_LC_LINK_WIDTH_X4:
4295 return 4;
4296 case RADEON_PCIE_LC_LINK_WIDTH_X8:
4297 return 8;
4298 case RADEON_PCIE_LC_LINK_WIDTH_X12:
4299 /* not actually supported */
4300 return 12;
4301 case RADEON_PCIE_LC_LINK_WIDTH_X0:
4302 case RADEON_PCIE_LC_LINK_WIDTH_X16:
4303 default:
4304 return 16;
4305 }
4306}
4307
4308static void ci_request_link_speed_change_before_state_change(struct radeon_device *rdev,
4309 struct radeon_ps *radeon_new_state,
4310 struct radeon_ps *radeon_current_state)
4311{
4312 struct ci_power_info *pi = ci_get_pi(rdev);
4313 enum radeon_pcie_gen target_link_speed =
4314 ci_get_maximum_link_speed(rdev, radeon_new_state);
4315 enum radeon_pcie_gen current_link_speed;
4316
4317 if (pi->force_pcie_gen == RADEON_PCIE_GEN_INVALID)
4318 current_link_speed = ci_get_maximum_link_speed(rdev, radeon_current_state);
4319 else
4320 current_link_speed = pi->force_pcie_gen;
4321
4322 pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;
4323 pi->pspp_notify_required = false;
4324 if (target_link_speed > current_link_speed) {
4325 switch (target_link_speed) {
ab62e768 4326#ifdef CONFIG_ACPI
cc8dbbb4
AD		 4327 case RADEON_PCIE_GEN3:
4328 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN3, false) == 0)
4329 break;
4330 pi->force_pcie_gen = RADEON_PCIE_GEN2;
4331 if (current_link_speed == RADEON_PCIE_GEN2)
4332 break;
4333 case RADEON_PCIE_GEN2:
4334 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, false) == 0)
4335 break;
ab62e768 4336#endif
cc8dbbb4
AD		 4337 default:
4338 pi->force_pcie_gen = ci_get_current_pcie_speed(rdev);
4339 break;
4340 }
4341 } else {
4342 if (target_link_speed < current_link_speed)
4343 pi->pspp_notify_required = true;
4344 }
4345}
4346
4347static void ci_notify_link_speed_change_after_state_change(struct radeon_device *rdev,
4348 struct radeon_ps *radeon_new_state,
4349 struct radeon_ps *radeon_current_state)
4350{
4351 struct ci_power_info *pi = ci_get_pi(rdev);
4352 enum radeon_pcie_gen target_link_speed =
4353 ci_get_maximum_link_speed(rdev, radeon_new_state);
4354 u8 request;
4355
4356 if (pi->pspp_notify_required) {
4357 if (target_link_speed == RADEON_PCIE_GEN3)
4358 request = PCIE_PERF_REQ_PECI_GEN3;
4359 else if (target_link_speed == RADEON_PCIE_GEN2)
4360 request = PCIE_PERF_REQ_PECI_GEN2;
4361 else
4362 request = PCIE_PERF_REQ_PECI_GEN1;
4363
4364 if ((request == PCIE_PERF_REQ_PECI_GEN1) &&
4365 (ci_get_current_pcie_speed(rdev) > 0))
4366 return;
4367
ab62e768 4368#ifdef CONFIG_ACPI
cc8dbbb4 4369 radeon_acpi_pcie_performance_request(rdev, request, false);
ab62e768 4370#endif
cc8dbbb4
AD		 4371 }
4372}
4373
4374static int ci_set_private_data_variables_based_on_pptable(struct radeon_device *rdev)
4375{
4376 struct ci_power_info *pi = ci_get_pi(rdev);
4377 struct radeon_clock_voltage_dependency_table *allowed_sclk_vddc_table =
4378 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
4379 struct radeon_clock_voltage_dependency_table *allowed_mclk_vddc_table =
4380 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk;
4381 struct radeon_clock_voltage_dependency_table *allowed_mclk_vddci_table =
4382 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk;
4383
4384 if (allowed_sclk_vddc_table == NULL)
4385 return -EINVAL;
4386 if (allowed_sclk_vddc_table->count < 1)
4387 return -EINVAL;
4388 if (allowed_mclk_vddc_table == NULL)
4389 return -EINVAL;
4390 if (allowed_mclk_vddc_table->count < 1)
4391 return -EINVAL;
4392 if (allowed_mclk_vddci_table == NULL)
4393 return -EINVAL;
4394 if (allowed_mclk_vddci_table->count < 1)
4395 return -EINVAL;
4396
4397 pi->min_vddc_in_pp_table = allowed_sclk_vddc_table->entries[0].v;
4398 pi->max_vddc_in_pp_table =
4399 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v;
4400
4401 pi->min_vddci_in_pp_table = allowed_mclk_vddci_table->entries[0].v;
4402 pi->max_vddci_in_pp_table =
4403 allowed_mclk_vddci_table->entries[allowed_mclk_vddci_table->count - 1].v;
4404
4405 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk =
4406 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk;
4407 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk =
4408 allowed_mclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk;
4409 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc =
4410 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v;
4411 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci =
4412 allowed_mclk_vddci_table->entries[allowed_mclk_vddci_table->count - 1].v;
4413
4414 return 0;
4415}
4416
4417static void ci_patch_with_vddc_leakage(struct radeon_device *rdev, u16 *vddc)
4418{
4419 struct ci_power_info *pi = ci_get_pi(rdev);
4420 struct ci_leakage_voltage *leakage_table = &pi->vddc_leakage;
4421 u32 leakage_index;
4422
4423 for (leakage_index = 0; leakage_index < leakage_table->count; leakage_index++) {
4424 if (leakage_table->leakage_id[leakage_index] == *vddc) {
4425 *vddc = leakage_table->actual_voltage[leakage_index];
4426 break;
4427 }
4428 }
4429}
4430
4431static void ci_patch_with_vddci_leakage(struct radeon_device *rdev, u16 *vddci)
4432{
4433 struct ci_power_info *pi = ci_get_pi(rdev);
4434 struct ci_leakage_voltage *leakage_table = &pi->vddci_leakage;
4435 u32 leakage_index;
4436
4437 for (leakage_index = 0; leakage_index < leakage_table->count; leakage_index++) {
4438 if (leakage_table->leakage_id[leakage_index] == *vddci) {
4439 *vddci = leakage_table->actual_voltage[leakage_index];
4440 break;
4441 }
4442 }
4443}
4444
4445static void ci_patch_clock_voltage_dependency_table_with_vddc_leakage(struct radeon_device *rdev,
4446 struct radeon_clock_voltage_dependency_table *table)
4447{
4448 u32 i;
4449
4450 if (table) {
4451 for (i = 0; i < table->count; i++)
4452 ci_patch_with_vddc_leakage(rdev, &table->entries[i].v);
4453 }
4454}
4455
4456static void ci_patch_clock_voltage_dependency_table_with_vddci_leakage(struct radeon_device *rdev,
4457 struct radeon_clock_voltage_dependency_table *table)
4458{
4459 u32 i;
4460
4461 if (table) {
4462 for (i = 0; i < table->count; i++)
4463 ci_patch_with_vddci_leakage(rdev, &table->entries[i].v);
4464 }
4465}
4466
4467static void ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage(struct radeon_device *rdev,
4468 struct radeon_vce_clock_voltage_dependency_table *table)
4469{
4470 u32 i;
4471
4472 if (table) {
4473 for (i = 0; i < table->count; i++)
4474 ci_patch_with_vddc_leakage(rdev, &table->entries[i].v);
4475 }
4476}
4477
4478static void ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage(struct radeon_device *rdev,
4479 struct radeon_uvd_clock_voltage_dependency_table *table)
4480{
4481 u32 i;
4482
4483 if (table) {
4484 for (i = 0; i < table->count; i++)
4485 ci_patch_with_vddc_leakage(rdev, &table->entries[i].v);
4486 }
4487}
4488
4489static void ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage(struct radeon_device *rdev,
4490 struct radeon_phase_shedding_limits_table *table)
4491{
4492 u32 i;
4493
4494 if (table) {
4495 for (i = 0; i < table->count; i++)
4496 ci_patch_with_vddc_leakage(rdev, &table->entries[i].voltage);
4497 }
4498}
4499
4500static void ci_patch_clock_voltage_limits_with_vddc_leakage(struct radeon_device *rdev,
4501 struct radeon_clock_and_voltage_limits *table)
4502{
4503 if (table) {
4504 ci_patch_with_vddc_leakage(rdev, (u16 *)&table->vddc);
4505 ci_patch_with_vddci_leakage(rdev, (u16 *)&table->vddci);
4506 }
4507}
4508
4509static void ci_patch_cac_leakage_table_with_vddc_leakage(struct radeon_device *rdev,
4510 struct radeon_cac_leakage_table *table)
4511{
4512 u32 i;
4513
4514 if (table) {
4515 for (i = 0; i < table->count; i++)
4516 ci_patch_with_vddc_leakage(rdev, &table->entries[i].vddc);
4517 }
4518}
4519
4520static void ci_patch_dependency_tables_with_leakage(struct radeon_device *rdev)
4521{
4522
4523 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev,
4524 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk);
4525 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev,
4526 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk);
4527 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev,
4528 &rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk);
4529 ci_patch_clock_voltage_dependency_table_with_vddci_leakage(rdev,
4530 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk);
4531 ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage(rdev,
4532 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table);
4533 ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage(rdev,
4534 &rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table);
4535 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev,
4536 &rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table);
4537 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev,
4538 &rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table);
4539 ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage(rdev,
4540 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table);
4541 ci_patch_clock_voltage_limits_with_vddc_leakage(rdev,
4542 &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac);
4543 ci_patch_clock_voltage_limits_with_vddc_leakage(rdev,
4544 &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc);
4545 ci_patch_cac_leakage_table_with_vddc_leakage(rdev,
4546 &rdev->pm.dpm.dyn_state.cac_leakage_table);
4547
4548}
4549
4550static void ci_get_memory_type(struct radeon_device *rdev)
4551{
4552 struct ci_power_info *pi = ci_get_pi(rdev);
4553 u32 tmp;
4554
4555 tmp = RREG32(MC_SEQ_MISC0);
4556
4557 if (((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT) ==
4558 MC_SEQ_MISC0_GDDR5_VALUE)
4559 pi->mem_gddr5 = true;
4560 else
4561 pi->mem_gddr5 = false;
4562
4563}
4564
9a04dad3
AD		 4565static void ci_update_current_ps(struct radeon_device *rdev,
4566 struct radeon_ps *rps)
cc8dbbb4
AD		 4567{
4568 struct ci_ps *new_ps = ci_get_ps(rps);
4569 struct ci_power_info *pi = ci_get_pi(rdev);
4570
4571 pi->current_rps = *rps;
4572 pi->current_ps = *new_ps;
4573 pi->current_rps.ps_priv = &pi->current_ps;
4574}
4575
9a04dad3
AD		 4576static void ci_update_requested_ps(struct radeon_device *rdev,
4577 struct radeon_ps *rps)
cc8dbbb4
AD		 4578{
4579 struct ci_ps *new_ps = ci_get_ps(rps);
4580 struct ci_power_info *pi = ci_get_pi(rdev);
4581
4582 pi->requested_rps = *rps;
4583 pi->requested_ps = *new_ps;
4584 pi->requested_rps.ps_priv = &pi->requested_ps;
4585}
4586
4587int ci_dpm_pre_set_power_state(struct radeon_device *rdev)
4588{
4589 struct ci_power_info *pi = ci_get_pi(rdev);
4590 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps;
4591 struct radeon_ps *new_ps = &requested_ps;
4592
4593 ci_update_requested_ps(rdev, new_ps);
4594
4595 ci_apply_state_adjust_rules(rdev, &pi->requested_rps);
4596
4597 return 0;
4598}
4599
4600void ci_dpm_post_set_power_state(struct radeon_device *rdev)
4601{
4602 struct ci_power_info *pi = ci_get_pi(rdev);
4603 struct radeon_ps *new_ps = &pi->requested_rps;
4604
4605 ci_update_current_ps(rdev, new_ps);
4606}
4607
4608
4609void ci_dpm_setup_asic(struct radeon_device *rdev)
4610{
6c7bccea
AD		 4611 int r;
4612
4613 r = ci_mc_load_microcode(rdev);
4614 if (r)
4615 DRM_ERROR("Failed to load MC firmware!\n");
cc8dbbb4
AD		 4616 ci_read_clock_registers(rdev);
4617 ci_get_memory_type(rdev);
4618 ci_enable_acpi_power_management(rdev);
4619 ci_init_sclk_t(rdev);
4620}
4621
4622int ci_dpm_enable(struct radeon_device *rdev)
4623{
4624 struct ci_power_info *pi = ci_get_pi(rdev);
4625 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
4626 int ret;
4627
4628 if (ci_is_smc_running(rdev))
4629 return -EINVAL;
4630 if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE) {
4631 ci_enable_voltage_control(rdev);
4632 ret = ci_construct_voltage_tables(rdev);
4633 if (ret) {
4634 DRM_ERROR("ci_construct_voltage_tables failed\n");
4635 return ret;
4636 }
4637 }
4638 if (pi->caps_dynamic_ac_timing) {
4639 ret = ci_initialize_mc_reg_table(rdev);
4640 if (ret)
4641 pi->caps_dynamic_ac_timing = false;
4642 }
4643 if (pi->dynamic_ss)
4644 ci_enable_spread_spectrum(rdev, true);
4645 if (pi->thermal_protection)
4646 ci_enable_thermal_protection(rdev, true);
4647 ci_program_sstp(rdev);
4648 ci_enable_display_gap(rdev);
4649 ci_program_vc(rdev);
4650 ret = ci_upload_firmware(rdev);
4651 if (ret) {
4652 DRM_ERROR("ci_upload_firmware failed\n");
4653 return ret;
4654 }
4655 ret = ci_process_firmware_header(rdev);
4656 if (ret) {
4657 DRM_ERROR("ci_process_firmware_header failed\n");
4658 return ret;
4659 }
4660 ret = ci_initial_switch_from_arb_f0_to_f1(rdev);
4661 if (ret) {
4662 DRM_ERROR("ci_initial_switch_from_arb_f0_to_f1 failed\n");
4663 return ret;
4664 }
4665 ret = ci_init_smc_table(rdev);
4666 if (ret) {
4667 DRM_ERROR("ci_init_smc_table failed\n");
4668 return ret;
4669 }
4670 ret = ci_init_arb_table_index(rdev);
4671 if (ret) {
4672 DRM_ERROR("ci_init_arb_table_index failed\n");
4673 return ret;
4674 }
4675 if (pi->caps_dynamic_ac_timing) {
4676 ret = ci_populate_initial_mc_reg_table(rdev);
4677 if (ret) {
4678 DRM_ERROR("ci_populate_initial_mc_reg_table failed\n");
4679 return ret;
4680 }
4681 }
4682 ret = ci_populate_pm_base(rdev);
4683 if (ret) {
4684 DRM_ERROR("ci_populate_pm_base failed\n");
4685 return ret;
4686 }
4687 ci_dpm_start_smc(rdev);
4688 ci_enable_vr_hot_gpio_interrupt(rdev);
4689 ret = ci_notify_smc_display_change(rdev, false);
4690 if (ret) {
4691 DRM_ERROR("ci_notify_smc_display_change failed\n");
4692 return ret;
4693 }
4694 ci_enable_sclk_control(rdev, true);
4695 ret = ci_enable_ulv(rdev, true);
4696 if (ret) {
4697 DRM_ERROR("ci_enable_ulv failed\n");
4698 return ret;
4699 }
4700 ret = ci_enable_ds_master_switch(rdev, true);
4701 if (ret) {
4702 DRM_ERROR("ci_enable_ds_master_switch failed\n");
4703 return ret;
4704 }
4705 ret = ci_start_dpm(rdev);
4706 if (ret) {
4707 DRM_ERROR("ci_start_dpm failed\n");
4708 return ret;
4709 }
4710 ret = ci_enable_didt(rdev, true);
4711 if (ret) {
4712 DRM_ERROR("ci_enable_didt failed\n");
4713 return ret;
4714 }
4715 ret = ci_enable_smc_cac(rdev, true);
4716 if (ret) {
4717 DRM_ERROR("ci_enable_smc_cac failed\n");
4718 return ret;
4719 }
4720 ret = ci_enable_power_containment(rdev, true);
4721 if (ret) {
4722 DRM_ERROR("ci_enable_power_containment failed\n");
4723 return ret;
4724 }
cc8dbbb4
AD		 4725
4726 ci_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
4727
4728 ci_update_current_ps(rdev, boot_ps);
4729
4730 return 0;
4731}
4732
1955f107 4733static int ci_set_temperature_range(struct radeon_device *rdev)
90208427
AD		 4734{
4735 int ret;
4736
1955f107
AD		 4737 ret = ci_thermal_enable_alert(rdev, false);
4738 if (ret)
4739 return ret;
4740 ret = ci_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
4741 if (ret)
4742 return ret;
4743 ret = ci_thermal_enable_alert(rdev, true);
4744 if (ret)
4745 return ret;
90208427 4746
1955f107
AD		 4747 return ret;
4748}
4749
4750int ci_dpm_late_enable(struct radeon_device *rdev)
4751{
4752 int ret;
4753
4754 ret = ci_set_temperature_range(rdev);
4755 if (ret)
4756 return ret;
90208427
AD		 4757
4758 ci_dpm_powergate_uvd(rdev, true);
4759
4760 return 0;
4761}
4762
cc8dbbb4
AD		 4763void ci_dpm_disable(struct radeon_device *rdev)
4764{
4765 struct ci_power_info *pi = ci_get_pi(rdev);
4766 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
4767
47acb1ff
AD		 4768 ci_dpm_powergate_uvd(rdev, false);
4769
cc8dbbb4
AD		 4770 if (!ci_is_smc_running(rdev))
4771 return;
4772
4773 if (pi->thermal_protection)
4774 ci_enable_thermal_protection(rdev, false);
4775 ci_enable_power_containment(rdev, false);
4776 ci_enable_smc_cac(rdev, false);
4777 ci_enable_didt(rdev, false);
4778 ci_enable_spread_spectrum(rdev, false);
4779 ci_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, false);
4780 ci_stop_dpm(rdev);
129acb7c 4781 ci_enable_ds_master_switch(rdev, false);
cc8dbbb4
AD		 4782 ci_enable_ulv(rdev, false);
4783 ci_clear_vc(rdev);
4784 ci_reset_to_default(rdev);
4785 ci_dpm_stop_smc(rdev);
4786 ci_force_switch_to_arb_f0(rdev);
4787
4788 ci_update_current_ps(rdev, boot_ps);
4789}
4790
4791int ci_dpm_set_power_state(struct radeon_device *rdev)
4792{
4793 struct ci_power_info *pi = ci_get_pi(rdev);
4794 struct radeon_ps *new_ps = &pi->requested_rps;
4795 struct radeon_ps *old_ps = &pi->current_rps;
4796 int ret;
4797
4798 ci_find_dpm_states_clocks_in_dpm_table(rdev, new_ps);
4799 if (pi->pcie_performance_request)
4800 ci_request_link_speed_change_before_state_change(rdev, new_ps, old_ps);
4801 ret = ci_freeze_sclk_mclk_dpm(rdev);
4802 if (ret) {
4803 DRM_ERROR("ci_freeze_sclk_mclk_dpm failed\n");
4804 return ret;
4805 }
4806 ret = ci_populate_and_upload_sclk_mclk_dpm_levels(rdev, new_ps);
4807 if (ret) {
4808 DRM_ERROR("ci_populate_and_upload_sclk_mclk_dpm_levels failed\n");
4809 return ret;
4810 }
4811 ret = ci_generate_dpm_level_enable_mask(rdev, new_ps);
4812 if (ret) {
4813 DRM_ERROR("ci_generate_dpm_level_enable_mask failed\n");
4814 return ret;
4815 }
8cd36682 4816
cc8dbbb4
AD		 4817 ret = ci_update_vce_dpm(rdev, new_ps, old_ps);
4818 if (ret) {
4819 DRM_ERROR("ci_update_vce_dpm failed\n");
4820 return ret;
4821 }
8cd36682 4822
cc8dbbb4
AD		 4823 ret = ci_update_sclk_t(rdev);
4824 if (ret) {
4825 DRM_ERROR("ci_update_sclk_t failed\n");
4826 return ret;
4827 }
4828 if (pi->caps_dynamic_ac_timing) {
4829 ret = ci_update_and_upload_mc_reg_table(rdev);
4830 if (ret) {
4831 DRM_ERROR("ci_update_and_upload_mc_reg_table failed\n");
4832 return ret;
4833 }
4834 }
4835 ret = ci_program_memory_timing_parameters(rdev);
4836 if (ret) {
4837 DRM_ERROR("ci_program_memory_timing_parameters failed\n");
4838 return ret;
4839 }
4840 ret = ci_unfreeze_sclk_mclk_dpm(rdev);
4841 if (ret) {
4842 DRM_ERROR("ci_unfreeze_sclk_mclk_dpm failed\n");
4843 return ret;
4844 }
4845 ret = ci_upload_dpm_level_enable_mask(rdev);
4846 if (ret) {
4847 DRM_ERROR("ci_upload_dpm_level_enable_mask failed\n");
4848 return ret;
4849 }
4850 if (pi->pcie_performance_request)
4851 ci_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps);
4852
4853 return 0;
4854}
4855
4856int ci_dpm_power_control_set_level(struct radeon_device *rdev)
4857{
4858 return ci_power_control_set_level(rdev);
4859}
4860
4861void ci_dpm_reset_asic(struct radeon_device *rdev)
4862{
4863 ci_set_boot_state(rdev);
4864}
4865
4866void ci_dpm_display_configuration_changed(struct radeon_device *rdev)
4867{
4868 ci_program_display_gap(rdev);
4869}
4870
4871union power_info {
4872 struct _ATOM_POWERPLAY_INFO info;
4873 struct _ATOM_POWERPLAY_INFO_V2 info_2;
4874 struct _ATOM_POWERPLAY_INFO_V3 info_3;
4875 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
4876 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
4877 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
4878};
4879
4880union pplib_clock_info {
4881 struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
4882 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
4883 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
4884 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
4885 struct _ATOM_PPLIB_SI_CLOCK_INFO si;
4886 struct _ATOM_PPLIB_CI_CLOCK_INFO ci;
4887};
4888
4889union pplib_power_state {
4890 struct _ATOM_PPLIB_STATE v1;
4891 struct _ATOM_PPLIB_STATE_V2 v2;
4892};
4893
4894static void ci_parse_pplib_non_clock_info(struct radeon_device *rdev,
4895 struct radeon_ps *rps,
4896 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
4897 u8 table_rev)
4898{
4899 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
4900 rps->class = le16_to_cpu(non_clock_info->usClassification);
4901 rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
4902
4903 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
4904 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
4905 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
4906 } else {
4907 rps->vclk = 0;
4908 rps->dclk = 0;
4909 }
4910
4911 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
4912 rdev->pm.dpm.boot_ps = rps;
4913 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
4914 rdev->pm.dpm.uvd_ps = rps;
4915}
4916
4917static void ci_parse_pplib_clock_info(struct radeon_device *rdev,
4918 struct radeon_ps *rps, int index,
4919 union pplib_clock_info *clock_info)
4920{
4921 struct ci_power_info *pi = ci_get_pi(rdev);
4922 struct ci_ps *ps = ci_get_ps(rps);
4923 struct ci_pl *pl = &ps->performance_levels[index];
4924
4925 ps->performance_level_count = index + 1;
4926
4927 pl->sclk = le16_to_cpu(clock_info->ci.usEngineClockLow);
4928 pl->sclk |= clock_info->ci.ucEngineClockHigh << 16;
4929 pl->mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow);
4930 pl->mclk |= clock_info->ci.ucMemoryClockHigh << 16;
4931
4932 pl->pcie_gen = r600_get_pcie_gen_support(rdev,
4933 pi->sys_pcie_mask,
4934 pi->vbios_boot_state.pcie_gen_bootup_value,
4935 clock_info->ci.ucPCIEGen);
4936 pl->pcie_lane = r600_get_pcie_lane_support(rdev,
4937 pi->vbios_boot_state.pcie_lane_bootup_value,
4938 le16_to_cpu(clock_info->ci.usPCIELane));
4939
4940 if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) {
4941 pi->acpi_pcie_gen = pl->pcie_gen;
4942 }
4943
4944 if (rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) {
4945 pi->ulv.supported = true;
4946 pi->ulv.pl = *pl;
4947 pi->ulv.cg_ulv_parameter = CISLANDS_CGULVPARAMETER_DFLT;
4948 }
4949
4950 /* patch up boot state */
4951 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
4952 pl->mclk = pi->vbios_boot_state.mclk_bootup_value;
4953 pl->sclk = pi->vbios_boot_state.sclk_bootup_value;
4954 pl->pcie_gen = pi->vbios_boot_state.pcie_gen_bootup_value;
4955 pl->pcie_lane = pi->vbios_boot_state.pcie_lane_bootup_value;
4956 }
4957
4958 switch (rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
4959 case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
4960 pi->use_pcie_powersaving_levels = true;
4961 if (pi->pcie_gen_powersaving.max < pl->pcie_gen)
4962 pi->pcie_gen_powersaving.max = pl->pcie_gen;
4963 if (pi->pcie_gen_powersaving.min > pl->pcie_gen)
4964 pi->pcie_gen_powersaving.min = pl->pcie_gen;
4965 if (pi->pcie_lane_powersaving.max < pl->pcie_lane)
4966 pi->pcie_lane_powersaving.max = pl->pcie_lane;
4967 if (pi->pcie_lane_powersaving.min > pl->pcie_lane)
4968 pi->pcie_lane_powersaving.min = pl->pcie_lane;
4969 break;
4970 case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
4971 pi->use_pcie_performance_levels = true;
4972 if (pi->pcie_gen_performance.max < pl->pcie_gen)
4973 pi->pcie_gen_performance.max = pl->pcie_gen;
4974 if (pi->pcie_gen_performance.min > pl->pcie_gen)
4975 pi->pcie_gen_performance.min = pl->pcie_gen;
4976 if (pi->pcie_lane_performance.max < pl->pcie_lane)
4977 pi->pcie_lane_performance.max = pl->pcie_lane;
4978 if (pi->pcie_lane_performance.min > pl->pcie_lane)
4979 pi->pcie_lane_performance.min = pl->pcie_lane;
4980 break;
4981 default:
4982 break;
4983 }
4984}
4985
4986static int ci_parse_power_table(struct radeon_device *rdev)
4987{
4988 struct radeon_mode_info *mode_info = &rdev->mode_info;
4989 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
4990 union pplib_power_state *power_state;
4991 int i, j, k, non_clock_array_index, clock_array_index;
4992 union pplib_clock_info *clock_info;
4993 struct _StateArray *state_array;
4994 struct _ClockInfoArray *clock_info_array;
4995 struct _NonClockInfoArray *non_clock_info_array;
4996 union power_info *power_info;
4997 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
4998 u16 data_offset;
4999 u8 frev, crev;
5000 u8 *power_state_offset;
5001 struct ci_ps *ps;
5002
5003 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
5004 &frev, &crev, &data_offset))
5005 return -EINVAL;
5006 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
5007
5008 state_array = (struct _StateArray *)
5009 (mode_info->atom_context->bios + data_offset +
5010 le16_to_cpu(power_info->pplib.usStateArrayOffset));
5011 clock_info_array = (struct _ClockInfoArray *)
5012 (mode_info->atom_context->bios + data_offset +
5013 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
5014 non_clock_info_array = (struct _NonClockInfoArray *)
5015 (mode_info->atom_context->bios + data_offset +
5016 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
5017
5018 rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) *
5019 state_array->ucNumEntries, GFP_KERNEL);
5020 if (!rdev->pm.dpm.ps)
5021 return -ENOMEM;
5022 power_state_offset = (u8 *)state_array->states;
cc8dbbb4 5023 for (i = 0; i < state_array->ucNumEntries; i++) {
b309ed98 5024 u8 *idx;
cc8dbbb4
AD		 5025 power_state = (union pplib_power_state *)power_state_offset;
5026 non_clock_array_index = power_state->v2.nonClockInfoIndex;
5027 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
5028 &non_clock_info_array->nonClockInfo[non_clock_array_index];
5029 if (!rdev->pm.power_state[i].clock_info)
5030 return -EINVAL;
5031 ps = kzalloc(sizeof(struct ci_ps), GFP_KERNEL);
5032 if (ps == NULL) {
5033 kfree(rdev->pm.dpm.ps);
5034 return -ENOMEM;
5035 }
5036 rdev->pm.dpm.ps[i].ps_priv = ps;
5037 ci_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],
5038 non_clock_info,
5039 non_clock_info_array->ucEntrySize);
5040 k = 0;
b309ed98 5041 idx = (u8 *)&power_state->v2.clockInfoIndex[0];
cc8dbbb4 5042 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
b309ed98 5043 clock_array_index = idx[j];
cc8dbbb4
AD		 5044 if (clock_array_index >= clock_info_array->ucNumEntries)
5045 continue;
5046 if (k >= CISLANDS_MAX_HARDWARE_POWERLEVELS)
5047 break;
5048 clock_info = (union pplib_clock_info *)
b309ed98
AD		 5049 ((u8 *)&clock_info_array->clockInfo[0] +
5050 (clock_array_index * clock_info_array->ucEntrySize));
cc8dbbb4
AD		 5051 ci_parse_pplib_clock_info(rdev,
5052 &rdev->pm.dpm.ps[i], k,
5053 clock_info);
5054 k++;
5055 }
5056 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
5057 }
5058 rdev->pm.dpm.num_ps = state_array->ucNumEntries;
8cd36682
AD		 5059
5060 /* fill in the vce power states */
5061 for (i = 0; i < RADEON_MAX_VCE_LEVELS; i++) {
5062 u32 sclk, mclk;
5063 clock_array_index = rdev->pm.dpm.vce_states[i].clk_idx;
5064 clock_info = (union pplib_clock_info *)
5065 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
5066 sclk = le16_to_cpu(clock_info->ci.usEngineClockLow);
5067 sclk |= clock_info->ci.ucEngineClockHigh << 16;
5068 mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow);
5069 mclk |= clock_info->ci.ucMemoryClockHigh << 16;
5070 rdev->pm.dpm.vce_states[i].sclk = sclk;
5071 rdev->pm.dpm.vce_states[i].mclk = mclk;
5072 }
5073
cc8dbbb4
AD		 5074 return 0;
5075}
5076
9a04dad3
AD		 5077static int ci_get_vbios_boot_values(struct radeon_device *rdev,
5078 struct ci_vbios_boot_state *boot_state)
cc8dbbb4
AD		 5079{
5080 struct radeon_mode_info *mode_info = &rdev->mode_info;
5081 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
5082 ATOM_FIRMWARE_INFO_V2_2 *firmware_info;
5083 u8 frev, crev;
5084 u16 data_offset;
5085
5086 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
5087 &frev, &crev, &data_offset)) {
5088 firmware_info =
5089 (ATOM_FIRMWARE_INFO_V2_2 *)(mode_info->atom_context->bios +
5090 data_offset);
5091 boot_state->mvdd_bootup_value = le16_to_cpu(firmware_info->usBootUpMVDDCVoltage);
5092 boot_state->vddc_bootup_value = le16_to_cpu(firmware_info->usBootUpVDDCVoltage);
5093 boot_state->vddci_bootup_value = le16_to_cpu(firmware_info->usBootUpVDDCIVoltage);
5094 boot_state->pcie_gen_bootup_value = ci_get_current_pcie_speed(rdev);
5095 boot_state->pcie_lane_bootup_value = ci_get_current_pcie_lane_number(rdev);
5096 boot_state->sclk_bootup_value = le32_to_cpu(firmware_info->ulDefaultEngineClock);
5097 boot_state->mclk_bootup_value = le32_to_cpu(firmware_info->ulDefaultMemoryClock);
5098
5099 return 0;
5100 }
5101 return -EINVAL;
5102}
5103
5104void ci_dpm_fini(struct radeon_device *rdev)
5105{
5106 int i;
5107
5108 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
5109 kfree(rdev->pm.dpm.ps[i].ps_priv);
5110 }
5111 kfree(rdev->pm.dpm.ps);
5112 kfree(rdev->pm.dpm.priv);
5113 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries);
5114 r600_free_extended_power_table(rdev);
5115}
5116
5117int ci_dpm_init(struct radeon_device *rdev)
5118{
5119 int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
34fc0b58
AD		 5120 SMU7_Discrete_DpmTable *dpm_table;
5121 struct radeon_gpio_rec gpio;
cc8dbbb4
AD		 5122 u16 data_offset, size;
5123 u8 frev, crev;
5124 struct ci_power_info *pi;
5125 int ret;
5126 u32 mask;
5127
5128 pi = kzalloc(sizeof(struct ci_power_info), GFP_KERNEL);
5129 if (pi == NULL)
5130 return -ENOMEM;
5131 rdev->pm.dpm.priv = pi;
5132
5133 ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
5134 if (ret)
5135 pi->sys_pcie_mask = 0;
5136 else
5137 pi->sys_pcie_mask = mask;
5138 pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;
5139
5140 pi->pcie_gen_performance.max = RADEON_PCIE_GEN1;
5141 pi->pcie_gen_performance.min = RADEON_PCIE_GEN3;
5142 pi->pcie_gen_powersaving.max = RADEON_PCIE_GEN1;
5143 pi->pcie_gen_powersaving.min = RADEON_PCIE_GEN3;
5144
5145 pi->pcie_lane_performance.max = 0;
5146 pi->pcie_lane_performance.min = 16;
5147 pi->pcie_lane_powersaving.max = 0;
5148 pi->pcie_lane_powersaving.min = 16;
5149
5150 ret = ci_get_vbios_boot_values(rdev, &pi->vbios_boot_state);
5151 if (ret) {
5152 ci_dpm_fini(rdev);
5153 return ret;
5154 }
82f79cc5
AD		 5155
5156 ret = r600_get_platform_caps(rdev);
5157 if (ret) {
5158 ci_dpm_fini(rdev);
5159 return ret;
5160 }
8cd36682
AD		 5161
5162 ret = r600_parse_extended_power_table(rdev);
cc8dbbb4
AD		 5163 if (ret) {
5164 ci_dpm_fini(rdev);
5165 return ret;
5166 }
8cd36682
AD		 5167
5168 ret = ci_parse_power_table(rdev);
cc8dbbb4
AD		 5169 if (ret) {
5170 ci_dpm_fini(rdev);
5171 return ret;
5172 }
5173
5174 pi->dll_default_on = false;
5175 pi->sram_end = SMC_RAM_END;
5176
5177 pi->activity_target[0] = CISLAND_TARGETACTIVITY_DFLT;
5178 pi->activity_target[1] = CISLAND_TARGETACTIVITY_DFLT;
5179 pi->activity_target[2] = CISLAND_TARGETACTIVITY_DFLT;
5180 pi->activity_target[3] = CISLAND_TARGETACTIVITY_DFLT;
5181 pi->activity_target[4] = CISLAND_TARGETACTIVITY_DFLT;
5182 pi->activity_target[5] = CISLAND_TARGETACTIVITY_DFLT;
5183 pi->activity_target[6] = CISLAND_TARGETACTIVITY_DFLT;
5184 pi->activity_target[7] = CISLAND_TARGETACTIVITY_DFLT;
5185
5186 pi->mclk_activity_target = CISLAND_MCLK_TARGETACTIVITY_DFLT;
5187
5188 pi->sclk_dpm_key_disabled = 0;
5189 pi->mclk_dpm_key_disabled = 0;
5190 pi->pcie_dpm_key_disabled = 0;
5191
7e1858f9
AD		 5192 /* mclk dpm is unstable on some R7 260X cards with the old mc ucode */
5193 if ((rdev->pdev->device == 0x6658) &&
5194 (rdev->mc_fw->size == (BONAIRE_MC_UCODE_SIZE * 4))) {
57700ad1 5195 pi->mclk_dpm_key_disabled = 1;
7e1858f9 5196 }
57700ad1 5197
cc8dbbb4
AD		 5198 pi->caps_sclk_ds = true;
5199
5200 pi->mclk_strobe_mode_threshold = 40000;
5201 pi->mclk_stutter_mode_threshold = 40000;
5202 pi->mclk_edc_enable_threshold = 40000;
5203 pi->mclk_edc_wr_enable_threshold = 40000;
5204
5205 ci_initialize_powertune_defaults(rdev);
5206
5207 pi->caps_fps = false;
5208
5209 pi->caps_sclk_throttle_low_notification = false;
5210
9597fe1e 5211 pi->caps_uvd_dpm = true;
ee35b002 5212 pi->caps_vce_dpm = true;
9597fe1e 5213
cc8dbbb4
AD		 5214 ci_get_leakage_voltages(rdev);
5215 ci_patch_dependency_tables_with_leakage(rdev);
5216 ci_set_private_data_variables_based_on_pptable(rdev);
5217
5218 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries =
5219 kzalloc(4 * sizeof(struct radeon_clock_voltage_dependency_entry), GFP_KERNEL);
5220 if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) {
5221 ci_dpm_fini(rdev);
5222 return -ENOMEM;
5223 }
5224 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4;
5225 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;
5226 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0;
5227 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000;
5228 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720;
5229 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000;
5230 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810;
5231 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000;
5232 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900;
5233
5234 rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4;
5235 rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000;
5236 rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200;
5237
5238 rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0;
5239 rdev->pm.dpm.dyn_state.valid_sclk_values.values = NULL;
5240 rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0;
5241 rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL;
5242
2d40038d
AD		 5243 if (rdev->family == CHIP_HAWAII) {
5244 pi->thermal_temp_setting.temperature_low = 94500;
5245 pi->thermal_temp_setting.temperature_high = 95000;
5246 pi->thermal_temp_setting.temperature_shutdown = 104000;
5247 } else {
5248 pi->thermal_temp_setting.temperature_low = 99500;
5249 pi->thermal_temp_setting.temperature_high = 100000;
5250 pi->thermal_temp_setting.temperature_shutdown = 104000;
5251 }
cc8dbbb4
AD		 5252
5253 pi->uvd_enabled = false;
5254
34fc0b58
AD		 5255 dpm_table = &pi->smc_state_table;
5256
5257 gpio = radeon_atombios_lookup_gpio(rdev, VDDC_VRHOT_GPIO_PINID);
5258 if (gpio.valid) {
5259 dpm_table->VRHotGpio = gpio.shift;
5260 rdev->pm.dpm.platform_caps |= ATOM_PP_PLATFORM_CAP_REGULATOR_HOT;
5261 } else {
5262 dpm_table->VRHotGpio = CISLANDS_UNUSED_GPIO_PIN;
5263 rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_REGULATOR_HOT;
5264 }
5265
5266 gpio = radeon_atombios_lookup_gpio(rdev, PP_AC_DC_SWITCH_GPIO_PINID);
5267 if (gpio.valid) {
5268 dpm_table->AcDcGpio = gpio.shift;
5269 rdev->pm.dpm.platform_caps |= ATOM_PP_PLATFORM_CAP_HARDWAREDC;
5270 } else {
5271 dpm_table->AcDcGpio = CISLANDS_UNUSED_GPIO_PIN;
5272 rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_HARDWAREDC;
5273 }
5274
5275 gpio = radeon_atombios_lookup_gpio(rdev, VDDC_PCC_GPIO_PINID);
5276 if (gpio.valid) {
5277 u32 tmp = RREG32_SMC(CNB_PWRMGT_CNTL);
5278
5279 switch (gpio.shift) {
5280 case 0:
5281 tmp &= ~GNB_SLOW_MODE_MASK;
5282 tmp |= GNB_SLOW_MODE(1);
5283 break;
5284 case 1:
5285 tmp &= ~GNB_SLOW_MODE_MASK;
5286 tmp |= GNB_SLOW_MODE(2);
5287 break;
5288 case 2:
5289 tmp |= GNB_SLOW;
5290 break;
5291 case 3:
5292 tmp |= FORCE_NB_PS1;
5293 break;
5294 case 4:
5295 tmp |= DPM_ENABLED;
5296 break;
5297 default:
5298 DRM_ERROR("Invalid PCC GPIO!");
5299 break;
5300 }
5301 WREG32_SMC(CNB_PWRMGT_CNTL, tmp);
5302 }
5303
cc8dbbb4
AD		 5304 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_NONE;
5305 pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_NONE;
5306 pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_NONE;
5307 if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_GPIO_LUT))
5308 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO;
5309 else if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2))
5310 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2;
5311
5312 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL) {
5313 if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT))
5314 pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO;
5315 else if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2))
5316 pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2;
5317 else
5318 rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL;
5319 }
5320
5321 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_MVDDCONTROL) {
5322 if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT))
5323 pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO;
5324 else if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2))
5325 pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2;
5326 else
5327 rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_MVDDCONTROL;
5328 }
5329
5330 pi->vddc_phase_shed_control = true;
5331
5332#if defined(CONFIG_ACPI)
5333 pi->pcie_performance_request =
5334 radeon_acpi_is_pcie_performance_request_supported(rdev);
5335#else
5336 pi->pcie_performance_request = false;
5337#endif
5338
5339 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
5340 &frev, &crev, &data_offset)) {
5341 pi->caps_sclk_ss_support = true;
5342 pi->caps_mclk_ss_support = true;
5343 pi->dynamic_ss = true;
5344 } else {
5345 pi->caps_sclk_ss_support = false;
5346 pi->caps_mclk_ss_support = false;
5347 pi->dynamic_ss = true;
5348 }
5349
5350 if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE)
5351 pi->thermal_protection = true;
5352 else
5353 pi->thermal_protection = false;
5354
5355 pi->caps_dynamic_ac_timing = true;
5356
47acb1ff
AD		 5357 pi->uvd_power_gated = false;
5358
679fe80f
AD		 5359 /* make sure dc limits are valid */
5360 if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) ||
5361 (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0))
5362 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc =
5363 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
5364
cc8dbbb4
AD		 5365 return 0;
5366}
5367
94b4adc5
AD		 5368void ci_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
5369 struct seq_file *m)
5370{
3e15c353
AD		 5371 struct ci_power_info *pi = ci_get_pi(rdev);
5372 struct radeon_ps *rps = &pi->current_rps;
94b4adc5
AD		 5373 u32 sclk = ci_get_average_sclk_freq(rdev);
5374 u32 mclk = ci_get_average_mclk_freq(rdev);
5375
3e15c353
AD		 5376 seq_printf(m, "uvd %sabled\n", pi->uvd_enabled ? "en" : "dis");
5377 seq_printf(m, "vce %sabled\n", rps->vce_active ? "en" : "dis");
94b4adc5
AD		 5378 seq_printf(m, "power level avg sclk: %u mclk: %u\n",
5379 sclk, mclk);
5380}
5381
cc8dbbb4
AD		 5382void ci_dpm_print_power_state(struct radeon_device *rdev,
5383 struct radeon_ps *rps)
5384{
5385 struct ci_ps *ps = ci_get_ps(rps);
5386 struct ci_pl *pl;
5387 int i;
5388
5389 r600_dpm_print_class_info(rps->class, rps->class2);
5390 r600_dpm_print_cap_info(rps->caps);
5391 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
5392 for (i = 0; i < ps->performance_level_count; i++) {
5393 pl = &ps->performance_levels[i];
5394 printk("\t\tpower level %d sclk: %u mclk: %u pcie gen: %u pcie lanes: %u\n",
5395 i, pl->sclk, pl->mclk, pl->pcie_gen + 1, pl->pcie_lane);
5396 }
5397 r600_dpm_print_ps_status(rdev, rps);
5398}
5399
5400u32 ci_dpm_get_sclk(struct radeon_device *rdev, bool low)
5401{
5402 struct ci_power_info *pi = ci_get_pi(rdev);
5403 struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps);
5404
5405 if (low)
5406 return requested_state->performance_levels[0].sclk;
5407 else
5408 return requested_state->performance_levels[requested_state->performance_level_count - 1].sclk;
5409}
5410
5411u32 ci_dpm_get_mclk(struct radeon_device *rdev, bool low)
5412{
5413 struct ci_power_info *pi = ci_get_pi(rdev);
5414 struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps);
5415
5416 if (low)
5417 return requested_state->performance_levels[0].mclk;
5418 else
5419 return requested_state->performance_levels[requested_state->performance_level_count - 1].mclk;
5420}
Linux kernel - Deliverables
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