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2483b4ea CK |
1 | /* |
2 | * Copyright 2013 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Alex Deucher | |
23 | */ | |
24 | #include <linux/firmware.h> | |
25 | #include <drm/drmP.h> | |
26 | #include "radeon.h" | |
f2c6b0f4 | 27 | #include "radeon_ucode.h" |
2483b4ea | 28 | #include "radeon_asic.h" |
74d360f6 | 29 | #include "radeon_trace.h" |
2483b4ea CK |
30 | #include "cikd.h" |
31 | ||
32 | /* sdma */ | |
33 | #define CIK_SDMA_UCODE_SIZE 1050 | |
34 | #define CIK_SDMA_UCODE_VERSION 64 | |
35 | ||
36 | u32 cik_gpu_check_soft_reset(struct radeon_device *rdev); | |
37 | ||
38 | /* | |
39 | * sDMA - System DMA | |
40 | * Starting with CIK, the GPU has new asynchronous | |
41 | * DMA engines. These engines are used for compute | |
42 | * and gfx. There are two DMA engines (SDMA0, SDMA1) | |
43 | * and each one supports 1 ring buffer used for gfx | |
44 | * and 2 queues used for compute. | |
45 | * | |
46 | * The programming model is very similar to the CP | |
47 | * (ring buffer, IBs, etc.), but sDMA has it's own | |
48 | * packet format that is different from the PM4 format | |
49 | * used by the CP. sDMA supports copying data, writing | |
50 | * embedded data, solid fills, and a number of other | |
51 | * things. It also has support for tiling/detiling of | |
52 | * buffers. | |
53 | */ | |
54 | ||
ea31bf69 AD |
55 | /** |
56 | * cik_sdma_get_rptr - get the current read pointer | |
57 | * | |
58 | * @rdev: radeon_device pointer | |
59 | * @ring: radeon ring pointer | |
60 | * | |
61 | * Get the current rptr from the hardware (CIK+). | |
62 | */ | |
63 | uint32_t cik_sdma_get_rptr(struct radeon_device *rdev, | |
64 | struct radeon_ring *ring) | |
65 | { | |
66 | u32 rptr, reg; | |
67 | ||
68 | if (rdev->wb.enabled) { | |
69 | rptr = rdev->wb.wb[ring->rptr_offs/4]; | |
70 | } else { | |
71 | if (ring->idx == R600_RING_TYPE_DMA_INDEX) | |
72 | reg = SDMA0_GFX_RB_RPTR + SDMA0_REGISTER_OFFSET; | |
73 | else | |
74 | reg = SDMA0_GFX_RB_RPTR + SDMA1_REGISTER_OFFSET; | |
75 | ||
76 | rptr = RREG32(reg); | |
77 | } | |
78 | ||
79 | return (rptr & 0x3fffc) >> 2; | |
80 | } | |
81 | ||
82 | /** | |
83 | * cik_sdma_get_wptr - get the current write pointer | |
84 | * | |
85 | * @rdev: radeon_device pointer | |
86 | * @ring: radeon ring pointer | |
87 | * | |
88 | * Get the current wptr from the hardware (CIK+). | |
89 | */ | |
90 | uint32_t cik_sdma_get_wptr(struct radeon_device *rdev, | |
91 | struct radeon_ring *ring) | |
92 | { | |
93 | u32 reg; | |
94 | ||
95 | if (ring->idx == R600_RING_TYPE_DMA_INDEX) | |
96 | reg = SDMA0_GFX_RB_WPTR + SDMA0_REGISTER_OFFSET; | |
97 | else | |
98 | reg = SDMA0_GFX_RB_WPTR + SDMA1_REGISTER_OFFSET; | |
99 | ||
100 | return (RREG32(reg) & 0x3fffc) >> 2; | |
101 | } | |
102 | ||
103 | /** | |
104 | * cik_sdma_set_wptr - commit the write pointer | |
105 | * | |
106 | * @rdev: radeon_device pointer | |
107 | * @ring: radeon ring pointer | |
108 | * | |
109 | * Write the wptr back to the hardware (CIK+). | |
110 | */ | |
111 | void cik_sdma_set_wptr(struct radeon_device *rdev, | |
112 | struct radeon_ring *ring) | |
113 | { | |
114 | u32 reg; | |
115 | ||
116 | if (ring->idx == R600_RING_TYPE_DMA_INDEX) | |
117 | reg = SDMA0_GFX_RB_WPTR + SDMA0_REGISTER_OFFSET; | |
118 | else | |
119 | reg = SDMA0_GFX_RB_WPTR + SDMA1_REGISTER_OFFSET; | |
120 | ||
121 | WREG32(reg, (ring->wptr << 2) & 0x3fffc); | |
f069dc1d | 122 | (void)RREG32(reg); |
ea31bf69 AD |
123 | } |
124 | ||
2483b4ea CK |
125 | /** |
126 | * cik_sdma_ring_ib_execute - Schedule an IB on the DMA engine | |
127 | * | |
128 | * @rdev: radeon_device pointer | |
129 | * @ib: IB object to schedule | |
130 | * | |
131 | * Schedule an IB in the DMA ring (CIK). | |
132 | */ | |
133 | void cik_sdma_ring_ib_execute(struct radeon_device *rdev, | |
134 | struct radeon_ib *ib) | |
135 | { | |
136 | struct radeon_ring *ring = &rdev->ring[ib->ring]; | |
7c42bc1a | 137 | u32 extra_bits = (ib->vm ? ib->vm->ids[ib->ring].id : 0) & 0xf; |
2483b4ea CK |
138 | |
139 | if (rdev->wb.enabled) { | |
140 | u32 next_rptr = ring->wptr + 5; | |
141 | while ((next_rptr & 7) != 4) | |
142 | next_rptr++; | |
143 | next_rptr += 4; | |
144 | radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0)); | |
145 | radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); | |
5e167cdb | 146 | radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr)); |
2483b4ea CK |
147 | radeon_ring_write(ring, 1); /* number of DWs to follow */ |
148 | radeon_ring_write(ring, next_rptr); | |
149 | } | |
150 | ||
151 | /* IB packet must end on a 8 DW boundary */ | |
152 | while ((ring->wptr & 7) != 4) | |
153 | radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0)); | |
154 | radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_INDIRECT_BUFFER, 0, extra_bits)); | |
155 | radeon_ring_write(ring, ib->gpu_addr & 0xffffffe0); /* base must be 32 byte aligned */ | |
5e167cdb | 156 | radeon_ring_write(ring, upper_32_bits(ib->gpu_addr)); |
2483b4ea CK |
157 | radeon_ring_write(ring, ib->length_dw); |
158 | ||
159 | } | |
160 | ||
ca113f6b AD |
161 | /** |
162 | * cik_sdma_hdp_flush_ring_emit - emit an hdp flush on the DMA ring | |
163 | * | |
164 | * @rdev: radeon_device pointer | |
165 | * @ridx: radeon ring index | |
166 | * | |
167 | * Emit an hdp flush packet on the requested DMA ring. | |
168 | */ | |
169 | static void cik_sdma_hdp_flush_ring_emit(struct radeon_device *rdev, | |
170 | int ridx) | |
171 | { | |
172 | struct radeon_ring *ring = &rdev->ring[ridx]; | |
da9e07e6 AD |
173 | u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(1) | |
174 | SDMA_POLL_REG_MEM_EXTRA_FUNC(3)); /* == */ | |
175 | u32 ref_and_mask; | |
ca113f6b | 176 | |
da9e07e6 AD |
177 | if (ridx == R600_RING_TYPE_DMA_INDEX) |
178 | ref_and_mask = SDMA0; | |
179 | else | |
180 | ref_and_mask = SDMA1; | |
181 | ||
182 | radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits)); | |
183 | radeon_ring_write(ring, GPU_HDP_FLUSH_DONE); | |
184 | radeon_ring_write(ring, GPU_HDP_FLUSH_REQ); | |
185 | radeon_ring_write(ring, ref_and_mask); /* reference */ | |
186 | radeon_ring_write(ring, ref_and_mask); /* mask */ | |
187 | radeon_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */ | |
ca113f6b AD |
188 | } |
189 | ||
2483b4ea CK |
190 | /** |
191 | * cik_sdma_fence_ring_emit - emit a fence on the DMA ring | |
192 | * | |
193 | * @rdev: radeon_device pointer | |
194 | * @fence: radeon fence object | |
195 | * | |
196 | * Add a DMA fence packet to the ring to write | |
197 | * the fence seq number and DMA trap packet to generate | |
198 | * an interrupt if needed (CIK). | |
199 | */ | |
200 | void cik_sdma_fence_ring_emit(struct radeon_device *rdev, | |
201 | struct radeon_fence *fence) | |
202 | { | |
203 | struct radeon_ring *ring = &rdev->ring[fence->ring]; | |
204 | u64 addr = rdev->fence_drv[fence->ring].gpu_addr; | |
2483b4ea CK |
205 | |
206 | /* write the fence */ | |
207 | radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0)); | |
5e167cdb CK |
208 | radeon_ring_write(ring, lower_32_bits(addr)); |
209 | radeon_ring_write(ring, upper_32_bits(addr)); | |
2483b4ea CK |
210 | radeon_ring_write(ring, fence->seq); |
211 | /* generate an interrupt */ | |
212 | radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_TRAP, 0, 0)); | |
213 | /* flush HDP */ | |
ca113f6b | 214 | cik_sdma_hdp_flush_ring_emit(rdev, fence->ring); |
2483b4ea CK |
215 | } |
216 | ||
217 | /** | |
218 | * cik_sdma_semaphore_ring_emit - emit a semaphore on the dma ring | |
219 | * | |
220 | * @rdev: radeon_device pointer | |
221 | * @ring: radeon_ring structure holding ring information | |
222 | * @semaphore: radeon semaphore object | |
223 | * @emit_wait: wait or signal semaphore | |
224 | * | |
225 | * Add a DMA semaphore packet to the ring wait on or signal | |
226 | * other rings (CIK). | |
227 | */ | |
1654b817 | 228 | bool cik_sdma_semaphore_ring_emit(struct radeon_device *rdev, |
2483b4ea CK |
229 | struct radeon_ring *ring, |
230 | struct radeon_semaphore *semaphore, | |
231 | bool emit_wait) | |
232 | { | |
233 | u64 addr = semaphore->gpu_addr; | |
234 | u32 extra_bits = emit_wait ? 0 : SDMA_SEMAPHORE_EXTRA_S; | |
235 | ||
236 | radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SEMAPHORE, 0, extra_bits)); | |
237 | radeon_ring_write(ring, addr & 0xfffffff8); | |
5e167cdb | 238 | radeon_ring_write(ring, upper_32_bits(addr)); |
1654b817 CK |
239 | |
240 | return true; | |
2483b4ea CK |
241 | } |
242 | ||
243 | /** | |
244 | * cik_sdma_gfx_stop - stop the gfx async dma engines | |
245 | * | |
246 | * @rdev: radeon_device pointer | |
247 | * | |
248 | * Stop the gfx async dma ring buffers (CIK). | |
249 | */ | |
250 | static void cik_sdma_gfx_stop(struct radeon_device *rdev) | |
251 | { | |
252 | u32 rb_cntl, reg_offset; | |
253 | int i; | |
254 | ||
50efa51a AD |
255 | if ((rdev->asic->copy.copy_ring_index == R600_RING_TYPE_DMA_INDEX) || |
256 | (rdev->asic->copy.copy_ring_index == CAYMAN_RING_TYPE_DMA1_INDEX)) | |
257 | radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); | |
2483b4ea CK |
258 | |
259 | for (i = 0; i < 2; i++) { | |
260 | if (i == 0) | |
261 | reg_offset = SDMA0_REGISTER_OFFSET; | |
262 | else | |
263 | reg_offset = SDMA1_REGISTER_OFFSET; | |
264 | rb_cntl = RREG32(SDMA0_GFX_RB_CNTL + reg_offset); | |
265 | rb_cntl &= ~SDMA_RB_ENABLE; | |
266 | WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl); | |
267 | WREG32(SDMA0_GFX_IB_CNTL + reg_offset, 0); | |
268 | } | |
7b1bbe88 AD |
269 | rdev->ring[R600_RING_TYPE_DMA_INDEX].ready = false; |
270 | rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX].ready = false; | |
2483b4ea CK |
271 | } |
272 | ||
273 | /** | |
274 | * cik_sdma_rlc_stop - stop the compute async dma engines | |
275 | * | |
276 | * @rdev: radeon_device pointer | |
277 | * | |
278 | * Stop the compute async dma queues (CIK). | |
279 | */ | |
280 | static void cik_sdma_rlc_stop(struct radeon_device *rdev) | |
281 | { | |
282 | /* XXX todo */ | |
283 | } | |
284 | ||
d7a60d8e BG |
285 | /** |
286 | * cik_sdma_ctx_switch_enable - enable/disable sdma engine preemption | |
287 | * | |
288 | * @rdev: radeon_device pointer | |
289 | * @enable: enable/disable preemption. | |
290 | * | |
291 | * Halt or unhalt the async dma engines (CIK). | |
292 | */ | |
55e3ad34 | 293 | static void cik_sdma_ctx_switch_enable(struct radeon_device *rdev, bool enable) |
d7a60d8e BG |
294 | { |
295 | uint32_t reg_offset, value; | |
296 | int i; | |
297 | ||
298 | for (i = 0; i < 2; i++) { | |
299 | if (i == 0) | |
300 | reg_offset = SDMA0_REGISTER_OFFSET; | |
301 | else | |
302 | reg_offset = SDMA1_REGISTER_OFFSET; | |
303 | value = RREG32(SDMA0_CNTL + reg_offset); | |
304 | if (enable) | |
305 | value |= AUTO_CTXSW_ENABLE; | |
306 | else | |
307 | value &= ~AUTO_CTXSW_ENABLE; | |
308 | WREG32(SDMA0_CNTL + reg_offset, value); | |
309 | } | |
310 | } | |
311 | ||
2483b4ea CK |
312 | /** |
313 | * cik_sdma_enable - stop the async dma engines | |
314 | * | |
315 | * @rdev: radeon_device pointer | |
316 | * @enable: enable/disable the DMA MEs. | |
317 | * | |
318 | * Halt or unhalt the async dma engines (CIK). | |
319 | */ | |
320 | void cik_sdma_enable(struct radeon_device *rdev, bool enable) | |
321 | { | |
322 | u32 me_cntl, reg_offset; | |
323 | int i; | |
324 | ||
07ae78c9 AD |
325 | if (enable == false) { |
326 | cik_sdma_gfx_stop(rdev); | |
327 | cik_sdma_rlc_stop(rdev); | |
328 | } | |
329 | ||
2483b4ea CK |
330 | for (i = 0; i < 2; i++) { |
331 | if (i == 0) | |
332 | reg_offset = SDMA0_REGISTER_OFFSET; | |
333 | else | |
334 | reg_offset = SDMA1_REGISTER_OFFSET; | |
335 | me_cntl = RREG32(SDMA0_ME_CNTL + reg_offset); | |
336 | if (enable) | |
337 | me_cntl &= ~SDMA_HALT; | |
338 | else | |
339 | me_cntl |= SDMA_HALT; | |
340 | WREG32(SDMA0_ME_CNTL + reg_offset, me_cntl); | |
341 | } | |
d7a60d8e BG |
342 | |
343 | cik_sdma_ctx_switch_enable(rdev, enable); | |
2483b4ea CK |
344 | } |
345 | ||
346 | /** | |
347 | * cik_sdma_gfx_resume - setup and start the async dma engines | |
348 | * | |
349 | * @rdev: radeon_device pointer | |
350 | * | |
351 | * Set up the gfx DMA ring buffers and enable them (CIK). | |
352 | * Returns 0 for success, error for failure. | |
353 | */ | |
354 | static int cik_sdma_gfx_resume(struct radeon_device *rdev) | |
355 | { | |
356 | struct radeon_ring *ring; | |
357 | u32 rb_cntl, ib_cntl; | |
358 | u32 rb_bufsz; | |
359 | u32 reg_offset, wb_offset; | |
360 | int i, r; | |
361 | ||
362 | for (i = 0; i < 2; i++) { | |
363 | if (i == 0) { | |
364 | ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; | |
365 | reg_offset = SDMA0_REGISTER_OFFSET; | |
366 | wb_offset = R600_WB_DMA_RPTR_OFFSET; | |
367 | } else { | |
368 | ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]; | |
369 | reg_offset = SDMA1_REGISTER_OFFSET; | |
370 | wb_offset = CAYMAN_WB_DMA1_RPTR_OFFSET; | |
371 | } | |
372 | ||
373 | WREG32(SDMA0_SEM_INCOMPLETE_TIMER_CNTL + reg_offset, 0); | |
374 | WREG32(SDMA0_SEM_WAIT_FAIL_TIMER_CNTL + reg_offset, 0); | |
375 | ||
376 | /* Set ring buffer size in dwords */ | |
9c725e5b | 377 | rb_bufsz = order_base_2(ring->ring_size / 4); |
2483b4ea CK |
378 | rb_cntl = rb_bufsz << 1; |
379 | #ifdef __BIG_ENDIAN | |
380 | rb_cntl |= SDMA_RB_SWAP_ENABLE | SDMA_RPTR_WRITEBACK_SWAP_ENABLE; | |
381 | #endif | |
382 | WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl); | |
383 | ||
384 | /* Initialize the ring buffer's read and write pointers */ | |
385 | WREG32(SDMA0_GFX_RB_RPTR + reg_offset, 0); | |
386 | WREG32(SDMA0_GFX_RB_WPTR + reg_offset, 0); | |
387 | ||
388 | /* set the wb address whether it's enabled or not */ | |
389 | WREG32(SDMA0_GFX_RB_RPTR_ADDR_HI + reg_offset, | |
390 | upper_32_bits(rdev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); | |
391 | WREG32(SDMA0_GFX_RB_RPTR_ADDR_LO + reg_offset, | |
392 | ((rdev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC)); | |
393 | ||
394 | if (rdev->wb.enabled) | |
395 | rb_cntl |= SDMA_RPTR_WRITEBACK_ENABLE; | |
396 | ||
397 | WREG32(SDMA0_GFX_RB_BASE + reg_offset, ring->gpu_addr >> 8); | |
398 | WREG32(SDMA0_GFX_RB_BASE_HI + reg_offset, ring->gpu_addr >> 40); | |
399 | ||
400 | ring->wptr = 0; | |
401 | WREG32(SDMA0_GFX_RB_WPTR + reg_offset, ring->wptr << 2); | |
402 | ||
2483b4ea CK |
403 | /* enable DMA RB */ |
404 | WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl | SDMA_RB_ENABLE); | |
405 | ||
406 | ib_cntl = SDMA_IB_ENABLE; | |
407 | #ifdef __BIG_ENDIAN | |
408 | ib_cntl |= SDMA_IB_SWAP_ENABLE; | |
409 | #endif | |
410 | /* enable DMA IBs */ | |
411 | WREG32(SDMA0_GFX_IB_CNTL + reg_offset, ib_cntl); | |
412 | ||
413 | ring->ready = true; | |
414 | ||
415 | r = radeon_ring_test(rdev, ring->idx, ring); | |
416 | if (r) { | |
417 | ring->ready = false; | |
418 | return r; | |
419 | } | |
420 | } | |
421 | ||
50efa51a AD |
422 | if ((rdev->asic->copy.copy_ring_index == R600_RING_TYPE_DMA_INDEX) || |
423 | (rdev->asic->copy.copy_ring_index == CAYMAN_RING_TYPE_DMA1_INDEX)) | |
424 | radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size); | |
2483b4ea CK |
425 | |
426 | return 0; | |
427 | } | |
428 | ||
429 | /** | |
430 | * cik_sdma_rlc_resume - setup and start the async dma engines | |
431 | * | |
432 | * @rdev: radeon_device pointer | |
433 | * | |
434 | * Set up the compute DMA queues and enable them (CIK). | |
435 | * Returns 0 for success, error for failure. | |
436 | */ | |
437 | static int cik_sdma_rlc_resume(struct radeon_device *rdev) | |
438 | { | |
439 | /* XXX todo */ | |
440 | return 0; | |
441 | } | |
442 | ||
443 | /** | |
444 | * cik_sdma_load_microcode - load the sDMA ME ucode | |
445 | * | |
446 | * @rdev: radeon_device pointer | |
447 | * | |
448 | * Loads the sDMA0/1 ucode. | |
449 | * Returns 0 for success, -EINVAL if the ucode is not available. | |
450 | */ | |
451 | static int cik_sdma_load_microcode(struct radeon_device *rdev) | |
452 | { | |
2483b4ea CK |
453 | int i; |
454 | ||
455 | if (!rdev->sdma_fw) | |
456 | return -EINVAL; | |
457 | ||
2483b4ea CK |
458 | /* halt the MEs */ |
459 | cik_sdma_enable(rdev, false); | |
460 | ||
f2c6b0f4 AD |
461 | if (rdev->new_fw) { |
462 | const struct sdma_firmware_header_v1_0 *hdr = | |
463 | (const struct sdma_firmware_header_v1_0 *)rdev->sdma_fw->data; | |
464 | const __le32 *fw_data; | |
465 | u32 fw_size; | |
466 | ||
467 | radeon_ucode_print_sdma_hdr(&hdr->header); | |
468 | ||
469 | /* sdma0 */ | |
470 | fw_data = (const __le32 *) | |
471 | (rdev->sdma_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); | |
472 | fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; | |
473 | WREG32(SDMA0_UCODE_ADDR + SDMA0_REGISTER_OFFSET, 0); | |
474 | for (i = 0; i < fw_size; i++) | |
475 | WREG32(SDMA0_UCODE_DATA + SDMA0_REGISTER_OFFSET, le32_to_cpup(fw_data++)); | |
476 | WREG32(SDMA0_UCODE_DATA + SDMA0_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION); | |
477 | ||
478 | /* sdma1 */ | |
479 | fw_data = (const __le32 *) | |
480 | (rdev->sdma_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); | |
481 | fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; | |
482 | WREG32(SDMA0_UCODE_ADDR + SDMA1_REGISTER_OFFSET, 0); | |
483 | for (i = 0; i < fw_size; i++) | |
484 | WREG32(SDMA0_UCODE_DATA + SDMA1_REGISTER_OFFSET, le32_to_cpup(fw_data++)); | |
485 | WREG32(SDMA0_UCODE_DATA + SDMA1_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION); | |
486 | } else { | |
487 | const __be32 *fw_data; | |
488 | ||
489 | /* sdma0 */ | |
490 | fw_data = (const __be32 *)rdev->sdma_fw->data; | |
491 | WREG32(SDMA0_UCODE_ADDR + SDMA0_REGISTER_OFFSET, 0); | |
492 | for (i = 0; i < CIK_SDMA_UCODE_SIZE; i++) | |
493 | WREG32(SDMA0_UCODE_DATA + SDMA0_REGISTER_OFFSET, be32_to_cpup(fw_data++)); | |
494 | WREG32(SDMA0_UCODE_DATA + SDMA0_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION); | |
495 | ||
496 | /* sdma1 */ | |
497 | fw_data = (const __be32 *)rdev->sdma_fw->data; | |
498 | WREG32(SDMA0_UCODE_ADDR + SDMA1_REGISTER_OFFSET, 0); | |
499 | for (i = 0; i < CIK_SDMA_UCODE_SIZE; i++) | |
500 | WREG32(SDMA0_UCODE_DATA + SDMA1_REGISTER_OFFSET, be32_to_cpup(fw_data++)); | |
501 | WREG32(SDMA0_UCODE_DATA + SDMA1_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION); | |
502 | } | |
2483b4ea CK |
503 | |
504 | WREG32(SDMA0_UCODE_ADDR + SDMA0_REGISTER_OFFSET, 0); | |
505 | WREG32(SDMA0_UCODE_ADDR + SDMA1_REGISTER_OFFSET, 0); | |
506 | return 0; | |
507 | } | |
508 | ||
509 | /** | |
510 | * cik_sdma_resume - setup and start the async dma engines | |
511 | * | |
512 | * @rdev: radeon_device pointer | |
513 | * | |
514 | * Set up the DMA engines and enable them (CIK). | |
515 | * Returns 0 for success, error for failure. | |
516 | */ | |
517 | int cik_sdma_resume(struct radeon_device *rdev) | |
518 | { | |
519 | int r; | |
520 | ||
2483b4ea CK |
521 | r = cik_sdma_load_microcode(rdev); |
522 | if (r) | |
523 | return r; | |
524 | ||
525 | /* unhalt the MEs */ | |
526 | cik_sdma_enable(rdev, true); | |
527 | ||
528 | /* start the gfx rings and rlc compute queues */ | |
529 | r = cik_sdma_gfx_resume(rdev); | |
530 | if (r) | |
531 | return r; | |
532 | r = cik_sdma_rlc_resume(rdev); | |
533 | if (r) | |
534 | return r; | |
535 | ||
536 | return 0; | |
537 | } | |
538 | ||
539 | /** | |
540 | * cik_sdma_fini - tear down the async dma engines | |
541 | * | |
542 | * @rdev: radeon_device pointer | |
543 | * | |
544 | * Stop the async dma engines and free the rings (CIK). | |
545 | */ | |
546 | void cik_sdma_fini(struct radeon_device *rdev) | |
547 | { | |
2483b4ea CK |
548 | /* halt the MEs */ |
549 | cik_sdma_enable(rdev, false); | |
550 | radeon_ring_fini(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX]); | |
551 | radeon_ring_fini(rdev, &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]); | |
552 | /* XXX - compute dma queue tear down */ | |
553 | } | |
554 | ||
555 | /** | |
556 | * cik_copy_dma - copy pages using the DMA engine | |
557 | * | |
558 | * @rdev: radeon_device pointer | |
559 | * @src_offset: src GPU address | |
560 | * @dst_offset: dst GPU address | |
561 | * @num_gpu_pages: number of GPU pages to xfer | |
57d20a43 | 562 | * @resv: reservation object to sync to |
2483b4ea CK |
563 | * |
564 | * Copy GPU paging using the DMA engine (CIK). | |
565 | * Used by the radeon ttm implementation to move pages if | |
566 | * registered as the asic copy callback. | |
567 | */ | |
57d20a43 CK |
568 | struct radeon_fence *cik_copy_dma(struct radeon_device *rdev, |
569 | uint64_t src_offset, uint64_t dst_offset, | |
570 | unsigned num_gpu_pages, | |
571 | struct reservation_object *resv) | |
2483b4ea | 572 | { |
57d20a43 | 573 | struct radeon_fence *fence; |
975700d2 | 574 | struct radeon_sync sync; |
2483b4ea CK |
575 | int ring_index = rdev->asic->copy.dma_ring_index; |
576 | struct radeon_ring *ring = &rdev->ring[ring_index]; | |
577 | u32 size_in_bytes, cur_size_in_bytes; | |
578 | int i, num_loops; | |
579 | int r = 0; | |
580 | ||
975700d2 | 581 | radeon_sync_create(&sync); |
2483b4ea CK |
582 | |
583 | size_in_bytes = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT); | |
584 | num_loops = DIV_ROUND_UP(size_in_bytes, 0x1fffff); | |
585 | r = radeon_ring_lock(rdev, ring, num_loops * 7 + 14); | |
586 | if (r) { | |
587 | DRM_ERROR("radeon: moving bo (%d).\n", r); | |
975700d2 | 588 | radeon_sync_free(rdev, &sync, NULL); |
57d20a43 | 589 | return ERR_PTR(r); |
2483b4ea CK |
590 | } |
591 | ||
975700d2 CK |
592 | radeon_sync_resv(rdev, &sync, resv, false); |
593 | radeon_sync_rings(rdev, &sync, ring->idx); | |
2483b4ea CK |
594 | |
595 | for (i = 0; i < num_loops; i++) { | |
596 | cur_size_in_bytes = size_in_bytes; | |
597 | if (cur_size_in_bytes > 0x1fffff) | |
598 | cur_size_in_bytes = 0x1fffff; | |
599 | size_in_bytes -= cur_size_in_bytes; | |
600 | radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_COPY_SUB_OPCODE_LINEAR, 0)); | |
601 | radeon_ring_write(ring, cur_size_in_bytes); | |
602 | radeon_ring_write(ring, 0); /* src/dst endian swap */ | |
5e167cdb CK |
603 | radeon_ring_write(ring, lower_32_bits(src_offset)); |
604 | radeon_ring_write(ring, upper_32_bits(src_offset)); | |
605 | radeon_ring_write(ring, lower_32_bits(dst_offset)); | |
606 | radeon_ring_write(ring, upper_32_bits(dst_offset)); | |
2483b4ea CK |
607 | src_offset += cur_size_in_bytes; |
608 | dst_offset += cur_size_in_bytes; | |
609 | } | |
610 | ||
57d20a43 | 611 | r = radeon_fence_emit(rdev, &fence, ring->idx); |
2483b4ea CK |
612 | if (r) { |
613 | radeon_ring_unlock_undo(rdev, ring); | |
975700d2 | 614 | radeon_sync_free(rdev, &sync, NULL); |
57d20a43 | 615 | return ERR_PTR(r); |
2483b4ea CK |
616 | } |
617 | ||
1538a9e0 | 618 | radeon_ring_unlock_commit(rdev, ring, false); |
975700d2 | 619 | radeon_sync_free(rdev, &sync, fence); |
2483b4ea | 620 | |
57d20a43 | 621 | return fence; |
2483b4ea CK |
622 | } |
623 | ||
624 | /** | |
625 | * cik_sdma_ring_test - simple async dma engine test | |
626 | * | |
627 | * @rdev: radeon_device pointer | |
628 | * @ring: radeon_ring structure holding ring information | |
629 | * | |
630 | * Test the DMA engine by writing using it to write an | |
631 | * value to memory. (CIK). | |
632 | * Returns 0 for success, error for failure. | |
633 | */ | |
634 | int cik_sdma_ring_test(struct radeon_device *rdev, | |
635 | struct radeon_ring *ring) | |
636 | { | |
637 | unsigned i; | |
638 | int r; | |
adfed2b0 | 639 | unsigned index; |
2483b4ea | 640 | u32 tmp; |
adfed2b0 | 641 | u64 gpu_addr; |
2483b4ea | 642 | |
adfed2b0 AD |
643 | if (ring->idx == R600_RING_TYPE_DMA_INDEX) |
644 | index = R600_WB_DMA_RING_TEST_OFFSET; | |
645 | else | |
646 | index = CAYMAN_WB_DMA1_RING_TEST_OFFSET; | |
647 | ||
648 | gpu_addr = rdev->wb.gpu_addr + index; | |
2483b4ea CK |
649 | |
650 | tmp = 0xCAFEDEAD; | |
adfed2b0 | 651 | rdev->wb.wb[index/4] = cpu_to_le32(tmp); |
2483b4ea | 652 | |
7e95cfb0 | 653 | r = radeon_ring_lock(rdev, ring, 5); |
2483b4ea CK |
654 | if (r) { |
655 | DRM_ERROR("radeon: dma failed to lock ring %d (%d).\n", ring->idx, r); | |
656 | return r; | |
657 | } | |
658 | radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0)); | |
adfed2b0 AD |
659 | radeon_ring_write(ring, lower_32_bits(gpu_addr)); |
660 | radeon_ring_write(ring, upper_32_bits(gpu_addr)); | |
2483b4ea CK |
661 | radeon_ring_write(ring, 1); /* number of DWs to follow */ |
662 | radeon_ring_write(ring, 0xDEADBEEF); | |
1538a9e0 | 663 | radeon_ring_unlock_commit(rdev, ring, false); |
2483b4ea CK |
664 | |
665 | for (i = 0; i < rdev->usec_timeout; i++) { | |
adfed2b0 | 666 | tmp = le32_to_cpu(rdev->wb.wb[index/4]); |
2483b4ea CK |
667 | if (tmp == 0xDEADBEEF) |
668 | break; | |
669 | DRM_UDELAY(1); | |
670 | } | |
671 | ||
672 | if (i < rdev->usec_timeout) { | |
673 | DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i); | |
674 | } else { | |
675 | DRM_ERROR("radeon: ring %d test failed (0x%08X)\n", | |
676 | ring->idx, tmp); | |
677 | r = -EINVAL; | |
678 | } | |
679 | return r; | |
680 | } | |
681 | ||
682 | /** | |
683 | * cik_sdma_ib_test - test an IB on the DMA engine | |
684 | * | |
685 | * @rdev: radeon_device pointer | |
686 | * @ring: radeon_ring structure holding ring information | |
687 | * | |
688 | * Test a simple IB in the DMA ring (CIK). | |
689 | * Returns 0 on success, error on failure. | |
690 | */ | |
691 | int cik_sdma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring) | |
692 | { | |
693 | struct radeon_ib ib; | |
694 | unsigned i; | |
0b021c58 | 695 | unsigned index; |
2483b4ea | 696 | int r; |
2483b4ea | 697 | u32 tmp = 0; |
0b021c58 | 698 | u64 gpu_addr; |
2483b4ea | 699 | |
0b021c58 AD |
700 | if (ring->idx == R600_RING_TYPE_DMA_INDEX) |
701 | index = R600_WB_DMA_RING_TEST_OFFSET; | |
702 | else | |
703 | index = CAYMAN_WB_DMA1_RING_TEST_OFFSET; | |
704 | ||
705 | gpu_addr = rdev->wb.gpu_addr + index; | |
2483b4ea CK |
706 | |
707 | tmp = 0xCAFEDEAD; | |
0b021c58 | 708 | rdev->wb.wb[index/4] = cpu_to_le32(tmp); |
2483b4ea CK |
709 | |
710 | r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256); | |
711 | if (r) { | |
712 | DRM_ERROR("radeon: failed to get ib (%d).\n", r); | |
713 | return r; | |
714 | } | |
715 | ||
716 | ib.ptr[0] = SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0); | |
0b021c58 AD |
717 | ib.ptr[1] = lower_32_bits(gpu_addr); |
718 | ib.ptr[2] = upper_32_bits(gpu_addr); | |
2483b4ea CK |
719 | ib.ptr[3] = 1; |
720 | ib.ptr[4] = 0xDEADBEEF; | |
721 | ib.length_dw = 5; | |
722 | ||
1538a9e0 | 723 | r = radeon_ib_schedule(rdev, &ib, NULL, false); |
2483b4ea CK |
724 | if (r) { |
725 | radeon_ib_free(rdev, &ib); | |
726 | DRM_ERROR("radeon: failed to schedule ib (%d).\n", r); | |
727 | return r; | |
728 | } | |
729 | r = radeon_fence_wait(ib.fence, false); | |
730 | if (r) { | |
731 | DRM_ERROR("radeon: fence wait failed (%d).\n", r); | |
732 | return r; | |
733 | } | |
734 | for (i = 0; i < rdev->usec_timeout; i++) { | |
0b021c58 | 735 | tmp = le32_to_cpu(rdev->wb.wb[index/4]); |
2483b4ea CK |
736 | if (tmp == 0xDEADBEEF) |
737 | break; | |
738 | DRM_UDELAY(1); | |
739 | } | |
740 | if (i < rdev->usec_timeout) { | |
741 | DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i); | |
742 | } else { | |
743 | DRM_ERROR("radeon: ib test failed (0x%08X)\n", tmp); | |
744 | r = -EINVAL; | |
745 | } | |
746 | radeon_ib_free(rdev, &ib); | |
747 | return r; | |
748 | } | |
749 | ||
750 | /** | |
751 | * cik_sdma_is_lockup - Check if the DMA engine is locked up | |
752 | * | |
753 | * @rdev: radeon_device pointer | |
754 | * @ring: radeon_ring structure holding ring information | |
755 | * | |
756 | * Check if the async DMA engine is locked up (CIK). | |
757 | * Returns true if the engine appears to be locked up, false if not. | |
758 | */ | |
759 | bool cik_sdma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) | |
760 | { | |
761 | u32 reset_mask = cik_gpu_check_soft_reset(rdev); | |
762 | u32 mask; | |
763 | ||
764 | if (ring->idx == R600_RING_TYPE_DMA_INDEX) | |
765 | mask = RADEON_RESET_DMA; | |
766 | else | |
767 | mask = RADEON_RESET_DMA1; | |
768 | ||
769 | if (!(reset_mask & mask)) { | |
ff212f25 | 770 | radeon_ring_lockup_update(rdev, ring); |
2483b4ea CK |
771 | return false; |
772 | } | |
2483b4ea CK |
773 | return radeon_ring_test_lockup(rdev, ring); |
774 | } | |
775 | ||
776 | /** | |
03f62abd CK |
777 | * cik_sdma_vm_copy_pages - update PTEs by copying them from the GART |
778 | * | |
779 | * @rdev: radeon_device pointer | |
780 | * @ib: indirect buffer to fill with commands | |
781 | * @pe: addr of the page entry | |
782 | * @src: src addr to copy from | |
783 | * @count: number of page entries to update | |
784 | * | |
785 | * Update PTEs by copying them from the GART using sDMA (CIK). | |
786 | */ | |
787 | void cik_sdma_vm_copy_pages(struct radeon_device *rdev, | |
788 | struct radeon_ib *ib, | |
789 | uint64_t pe, uint64_t src, | |
790 | unsigned count) | |
791 | { | |
792 | while (count) { | |
793 | unsigned bytes = count * 8; | |
794 | if (bytes > 0x1FFFF8) | |
795 | bytes = 0x1FFFF8; | |
796 | ||
797 | ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY, | |
798 | SDMA_WRITE_SUB_OPCODE_LINEAR, 0); | |
799 | ib->ptr[ib->length_dw++] = bytes; | |
800 | ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ | |
801 | ib->ptr[ib->length_dw++] = lower_32_bits(src); | |
802 | ib->ptr[ib->length_dw++] = upper_32_bits(src); | |
803 | ib->ptr[ib->length_dw++] = lower_32_bits(pe); | |
804 | ib->ptr[ib->length_dw++] = upper_32_bits(pe); | |
805 | ||
806 | pe += bytes; | |
807 | src += bytes; | |
808 | count -= bytes / 8; | |
809 | } | |
810 | } | |
811 | ||
812 | /** | |
813 | * cik_sdma_vm_write_pages - update PTEs by writing them manually | |
2483b4ea CK |
814 | * |
815 | * @rdev: radeon_device pointer | |
816 | * @ib: indirect buffer to fill with commands | |
817 | * @pe: addr of the page entry | |
818 | * @addr: dst addr to write into pe | |
819 | * @count: number of page entries to update | |
820 | * @incr: increase next addr by incr bytes | |
821 | * @flags: access flags | |
822 | * | |
03f62abd | 823 | * Update PTEs by writing them manually using sDMA (CIK). |
2483b4ea | 824 | */ |
03f62abd CK |
825 | void cik_sdma_vm_write_pages(struct radeon_device *rdev, |
826 | struct radeon_ib *ib, | |
827 | uint64_t pe, | |
828 | uint64_t addr, unsigned count, | |
829 | uint32_t incr, uint32_t flags) | |
2483b4ea | 830 | { |
2483b4ea CK |
831 | uint64_t value; |
832 | unsigned ndw; | |
833 | ||
03f62abd CK |
834 | while (count) { |
835 | ndw = count * 2; | |
836 | if (ndw > 0xFFFFE) | |
837 | ndw = 0xFFFFE; | |
838 | ||
839 | /* for non-physically contiguous pages (system) */ | |
840 | ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_WRITE, | |
841 | SDMA_WRITE_SUB_OPCODE_LINEAR, 0); | |
842 | ib->ptr[ib->length_dw++] = pe; | |
843 | ib->ptr[ib->length_dw++] = upper_32_bits(pe); | |
844 | ib->ptr[ib->length_dw++] = ndw; | |
845 | for (; ndw > 0; ndw -= 2, --count, pe += 8) { | |
846 | if (flags & R600_PTE_SYSTEM) { | |
24c16439 | 847 | value = radeon_vm_map_gart(rdev, addr); |
03f62abd | 848 | } else if (flags & R600_PTE_VALID) { |
2483b4ea | 849 | value = addr; |
03f62abd | 850 | } else { |
2483b4ea | 851 | value = 0; |
03f62abd CK |
852 | } |
853 | addr += incr; | |
854 | value |= flags; | |
855 | ib->ptr[ib->length_dw++] = value; | |
2483b4ea | 856 | ib->ptr[ib->length_dw++] = upper_32_bits(value); |
2483b4ea CK |
857 | } |
858 | } | |
03f62abd CK |
859 | } |
860 | ||
861 | /** | |
862 | * cik_sdma_vm_set_pages - update the page tables using sDMA | |
863 | * | |
864 | * @rdev: radeon_device pointer | |
865 | * @ib: indirect buffer to fill with commands | |
866 | * @pe: addr of the page entry | |
867 | * @addr: dst addr to write into pe | |
868 | * @count: number of page entries to update | |
869 | * @incr: increase next addr by incr bytes | |
870 | * @flags: access flags | |
871 | * | |
872 | * Update the page tables using sDMA (CIK). | |
873 | */ | |
874 | void cik_sdma_vm_set_pages(struct radeon_device *rdev, | |
875 | struct radeon_ib *ib, | |
876 | uint64_t pe, | |
877 | uint64_t addr, unsigned count, | |
878 | uint32_t incr, uint32_t flags) | |
879 | { | |
880 | uint64_t value; | |
881 | unsigned ndw; | |
882 | ||
883 | while (count) { | |
884 | ndw = count; | |
885 | if (ndw > 0x7FFFF) | |
886 | ndw = 0x7FFFF; | |
887 | ||
888 | if (flags & R600_PTE_VALID) | |
889 | value = addr; | |
890 | else | |
891 | value = 0; | |
892 | ||
893 | /* for physically contiguous pages (vram) */ | |
894 | ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_GENERATE_PTE_PDE, 0, 0); | |
895 | ib->ptr[ib->length_dw++] = pe; /* dst addr */ | |
896 | ib->ptr[ib->length_dw++] = upper_32_bits(pe); | |
897 | ib->ptr[ib->length_dw++] = flags; /* mask */ | |
898 | ib->ptr[ib->length_dw++] = 0; | |
899 | ib->ptr[ib->length_dw++] = value; /* value */ | |
900 | ib->ptr[ib->length_dw++] = upper_32_bits(value); | |
901 | ib->ptr[ib->length_dw++] = incr; /* increment size */ | |
902 | ib->ptr[ib->length_dw++] = 0; | |
903 | ib->ptr[ib->length_dw++] = ndw; /* number of entries */ | |
904 | ||
905 | pe += ndw * 8; | |
906 | addr += ndw * incr; | |
907 | count -= ndw; | |
908 | } | |
909 | } | |
910 | ||
911 | /** | |
912 | * cik_sdma_vm_pad_ib - pad the IB to the required number of dw | |
913 | * | |
914 | * @ib: indirect buffer to fill with padding | |
915 | * | |
916 | */ | |
917 | void cik_sdma_vm_pad_ib(struct radeon_ib *ib) | |
918 | { | |
2483b4ea CK |
919 | while (ib->length_dw & 0x7) |
920 | ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0); | |
921 | } | |
922 | ||
923 | /** | |
924 | * cik_dma_vm_flush - cik vm flush using sDMA | |
925 | * | |
926 | * @rdev: radeon_device pointer | |
927 | * | |
928 | * Update the page table base and flush the VM TLB | |
929 | * using sDMA (CIK). | |
930 | */ | |
faffaf62 CK |
931 | void cik_dma_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring, |
932 | unsigned vm_id, uint64_t pd_addr) | |
2483b4ea | 933 | { |
3a01fd36 AD |
934 | u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(0) | |
935 | SDMA_POLL_REG_MEM_EXTRA_FUNC(0)); /* always */ | |
936 | ||
2483b4ea | 937 | radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); |
faffaf62 CK |
938 | if (vm_id < 8) { |
939 | radeon_ring_write(ring, (VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm_id << 2)) >> 2); | |
2483b4ea | 940 | } else { |
faffaf62 | 941 | radeon_ring_write(ring, (VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((vm_id - 8) << 2)) >> 2); |
2483b4ea | 942 | } |
faffaf62 | 943 | radeon_ring_write(ring, pd_addr >> 12); |
2483b4ea CK |
944 | |
945 | /* update SH_MEM_* regs */ | |
946 | radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); | |
947 | radeon_ring_write(ring, SRBM_GFX_CNTL >> 2); | |
faffaf62 | 948 | radeon_ring_write(ring, VMID(vm_id)); |
2483b4ea CK |
949 | |
950 | radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); | |
951 | radeon_ring_write(ring, SH_MEM_BASES >> 2); | |
952 | radeon_ring_write(ring, 0); | |
953 | ||
954 | radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); | |
955 | radeon_ring_write(ring, SH_MEM_CONFIG >> 2); | |
956 | radeon_ring_write(ring, 0); | |
957 | ||
958 | radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); | |
959 | radeon_ring_write(ring, SH_MEM_APE1_BASE >> 2); | |
960 | radeon_ring_write(ring, 1); | |
961 | ||
962 | radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); | |
963 | radeon_ring_write(ring, SH_MEM_APE1_LIMIT >> 2); | |
964 | radeon_ring_write(ring, 0); | |
965 | ||
966 | radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); | |
967 | radeon_ring_write(ring, SRBM_GFX_CNTL >> 2); | |
968 | radeon_ring_write(ring, VMID(0)); | |
969 | ||
970 | /* flush HDP */ | |
faffaf62 | 971 | cik_sdma_hdp_flush_ring_emit(rdev, ring->idx); |
2483b4ea CK |
972 | |
973 | /* flush TLB */ | |
974 | radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); | |
975 | radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2); | |
faffaf62 | 976 | radeon_ring_write(ring, 1 << vm_id); |
3a01fd36 AD |
977 | |
978 | radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits)); | |
979 | radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2); | |
980 | radeon_ring_write(ring, 0); | |
981 | radeon_ring_write(ring, 0); /* reference */ | |
982 | radeon_ring_write(ring, 0); /* mask */ | |
983 | radeon_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */ | |
2483b4ea CK |
984 | } |
985 |