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drm/radeon: Use write-combined CPU mappings of IBs on >= CIK
[deliverable/linux.git] / drivers / gpu / drm / radeon / cik_sdma.c
CommitLineData
2483b4ea
CK		 1/*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24#include <linux/firmware.h>
25#include <drm/drmP.h>
26#include "radeon.h"
f2c6b0f4 27#include "radeon_ucode.h"
2483b4ea 28#include "radeon_asic.h"
74d360f6 29#include "radeon_trace.h"
2483b4ea
CK		 30#include "cikd.h"
31
32/* sdma */
33#define CIK_SDMA_UCODE_SIZE 1050
34#define CIK_SDMA_UCODE_VERSION 64
35
36u32 cik_gpu_check_soft_reset(struct radeon_device *rdev);
37
38/*
39 * sDMA - System DMA
40 * Starting with CIK, the GPU has new asynchronous
41 * DMA engines. These engines are used for compute
42 * and gfx. There are two DMA engines (SDMA0, SDMA1)
43 * and each one supports 1 ring buffer used for gfx
44 * and 2 queues used for compute.
45 *
46 * The programming model is very similar to the CP
47 * (ring buffer, IBs, etc.), but sDMA has it's own
48 * packet format that is different from the PM4 format
49 * used by the CP. sDMA supports copying data, writing
50 * embedded data, solid fills, and a number of other
51 * things. It also has support for tiling/detiling of
52 * buffers.
53 */
54
ea31bf69
AD		 55/**
56 * cik_sdma_get_rptr - get the current read pointer
57 *
58 * @rdev: radeon_device pointer
59 * @ring: radeon ring pointer
60 *
61 * Get the current rptr from the hardware (CIK+).
62 */
63uint32_t cik_sdma_get_rptr(struct radeon_device *rdev,
64 struct radeon_ring *ring)
65{
66 u32 rptr, reg;
67
68 if (rdev->wb.enabled) {
69 rptr = rdev->wb.wb[ring->rptr_offs/4];
70 } else {
71 if (ring->idx == R600_RING_TYPE_DMA_INDEX)
72 reg = SDMA0_GFX_RB_RPTR + SDMA0_REGISTER_OFFSET;
73 else
74 reg = SDMA0_GFX_RB_RPTR + SDMA1_REGISTER_OFFSET;
75
76 rptr = RREG32(reg);
77 }
78
79 return (rptr & 0x3fffc) >> 2;
80}
81
82/**
83 * cik_sdma_get_wptr - get the current write pointer
84 *
85 * @rdev: radeon_device pointer
86 * @ring: radeon ring pointer
87 *
88 * Get the current wptr from the hardware (CIK+).
89 */
90uint32_t cik_sdma_get_wptr(struct radeon_device *rdev,
91 struct radeon_ring *ring)
92{
93 u32 reg;
94
95 if (ring->idx == R600_RING_TYPE_DMA_INDEX)
96 reg = SDMA0_GFX_RB_WPTR + SDMA0_REGISTER_OFFSET;
97 else
98 reg = SDMA0_GFX_RB_WPTR + SDMA1_REGISTER_OFFSET;
99
100 return (RREG32(reg) & 0x3fffc) >> 2;
101}
102
103/**
104 * cik_sdma_set_wptr - commit the write pointer
105 *
106 * @rdev: radeon_device pointer
107 * @ring: radeon ring pointer
108 *
109 * Write the wptr back to the hardware (CIK+).
110 */
111void cik_sdma_set_wptr(struct radeon_device *rdev,
112 struct radeon_ring *ring)
113{
114 u32 reg;
115
116 if (ring->idx == R600_RING_TYPE_DMA_INDEX)
117 reg = SDMA0_GFX_RB_WPTR + SDMA0_REGISTER_OFFSET;
118 else
119 reg = SDMA0_GFX_RB_WPTR + SDMA1_REGISTER_OFFSET;
120
121 WREG32(reg, (ring->wptr << 2) & 0x3fffc);
122}
123
2483b4ea
CK		 124/**
125 * cik_sdma_ring_ib_execute - Schedule an IB on the DMA engine
126 *
127 * @rdev: radeon_device pointer
128 * @ib: IB object to schedule
129 *
130 * Schedule an IB in the DMA ring (CIK).
131 */
132void cik_sdma_ring_ib_execute(struct radeon_device *rdev,
133 struct radeon_ib *ib)
134{
135 struct radeon_ring *ring = &rdev->ring[ib->ring];
136 u32 extra_bits = (ib->vm ? ib->vm->id : 0) & 0xf;
137
138 if (rdev->wb.enabled) {
139 u32 next_rptr = ring->wptr + 5;
140 while ((next_rptr & 7) != 4)
141 next_rptr++;
142 next_rptr += 4;
143 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0));
144 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
5e167cdb 145 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr));
2483b4ea
CK		 146 radeon_ring_write(ring, 1); /* number of DWs to follow */
147 radeon_ring_write(ring, next_rptr);
148 }
149
150 /* IB packet must end on a 8 DW boundary */
151 while ((ring->wptr & 7) != 4)
152 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0));
153 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_INDIRECT_BUFFER, 0, extra_bits));
154 radeon_ring_write(ring, ib->gpu_addr & 0xffffffe0); /* base must be 32 byte aligned */
5e167cdb 155 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr));
2483b4ea
CK		 156 radeon_ring_write(ring, ib->length_dw);
157
158}
159
ca113f6b
AD		 160/**
161 * cik_sdma_hdp_flush_ring_emit - emit an hdp flush on the DMA ring
162 *
163 * @rdev: radeon_device pointer
164 * @ridx: radeon ring index
165 *
166 * Emit an hdp flush packet on the requested DMA ring.
167 */
168static void cik_sdma_hdp_flush_ring_emit(struct radeon_device *rdev,
169 int ridx)
170{
171 struct radeon_ring *ring = &rdev->ring[ridx];
da9e07e6
AD		 172 u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(1) |
173 SDMA_POLL_REG_MEM_EXTRA_FUNC(3)); /* == */
174 u32 ref_and_mask;
ca113f6b 175
da9e07e6
AD		 176 if (ridx == R600_RING_TYPE_DMA_INDEX)
177 ref_and_mask = SDMA0;
178 else
179 ref_and_mask = SDMA1;
180
181 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits));
182 radeon_ring_write(ring, GPU_HDP_FLUSH_DONE);
183 radeon_ring_write(ring, GPU_HDP_FLUSH_REQ);
184 radeon_ring_write(ring, ref_and_mask); /* reference */
185 radeon_ring_write(ring, ref_and_mask); /* mask */
186 radeon_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */
ca113f6b
AD		 187}
188
2483b4ea
CK		 189/**
190 * cik_sdma_fence_ring_emit - emit a fence on the DMA ring
191 *
192 * @rdev: radeon_device pointer
193 * @fence: radeon fence object
194 *
195 * Add a DMA fence packet to the ring to write
196 * the fence seq number and DMA trap packet to generate
197 * an interrupt if needed (CIK).
198 */
199void cik_sdma_fence_ring_emit(struct radeon_device *rdev,
200 struct radeon_fence *fence)
201{
202 struct radeon_ring *ring = &rdev->ring[fence->ring];
203 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
2483b4ea
CK		 204
205 /* write the fence */
206 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0));
5e167cdb
CK		 207 radeon_ring_write(ring, lower_32_bits(addr));
208 radeon_ring_write(ring, upper_32_bits(addr));
2483b4ea
CK		 209 radeon_ring_write(ring, fence->seq);
210 /* generate an interrupt */
211 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_TRAP, 0, 0));
212 /* flush HDP */
ca113f6b 213 cik_sdma_hdp_flush_ring_emit(rdev, fence->ring);
2483b4ea
CK		 214}
215
216/**
217 * cik_sdma_semaphore_ring_emit - emit a semaphore on the dma ring
218 *
219 * @rdev: radeon_device pointer
220 * @ring: radeon_ring structure holding ring information
221 * @semaphore: radeon semaphore object
222 * @emit_wait: wait or signal semaphore
223 *
224 * Add a DMA semaphore packet to the ring wait on or signal
225 * other rings (CIK).
226 */
1654b817 227bool cik_sdma_semaphore_ring_emit(struct radeon_device *rdev,
2483b4ea
CK		 228 struct radeon_ring *ring,
229 struct radeon_semaphore *semaphore,
230 bool emit_wait)
231{
232 u64 addr = semaphore->gpu_addr;
233 u32 extra_bits = emit_wait ? 0 : SDMA_SEMAPHORE_EXTRA_S;
234
235 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SEMAPHORE, 0, extra_bits));
236 radeon_ring_write(ring, addr & 0xfffffff8);
5e167cdb 237 radeon_ring_write(ring, upper_32_bits(addr));
1654b817
CK		 238
239 return true;
2483b4ea
CK		 240}
241
242/**
243 * cik_sdma_gfx_stop - stop the gfx async dma engines
244 *
245 * @rdev: radeon_device pointer
246 *
247 * Stop the gfx async dma ring buffers (CIK).
248 */
249static void cik_sdma_gfx_stop(struct radeon_device *rdev)
250{
251 u32 rb_cntl, reg_offset;
252 int i;
253
50efa51a
AD		 254 if ((rdev->asic->copy.copy_ring_index == R600_RING_TYPE_DMA_INDEX) ||
255 (rdev->asic->copy.copy_ring_index == CAYMAN_RING_TYPE_DMA1_INDEX))
256 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
2483b4ea
CK		 257
258 for (i = 0; i < 2; i++) {
259 if (i == 0)
260 reg_offset = SDMA0_REGISTER_OFFSET;
261 else
262 reg_offset = SDMA1_REGISTER_OFFSET;
263 rb_cntl = RREG32(SDMA0_GFX_RB_CNTL + reg_offset);
264 rb_cntl &= ~SDMA_RB_ENABLE;
265 WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl);
266 WREG32(SDMA0_GFX_IB_CNTL + reg_offset, 0);
267 }
7b1bbe88
AD		 268 rdev->ring[R600_RING_TYPE_DMA_INDEX].ready = false;
269 rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX].ready = false;
2483b4ea
CK		 270}
271
272/**
273 * cik_sdma_rlc_stop - stop the compute async dma engines
274 *
275 * @rdev: radeon_device pointer
276 *
277 * Stop the compute async dma queues (CIK).
278 */
279static void cik_sdma_rlc_stop(struct radeon_device *rdev)
280{
281 /* XXX todo */
282}
283
284/**
285 * cik_sdma_enable - stop the async dma engines
286 *
287 * @rdev: radeon_device pointer
288 * @enable: enable/disable the DMA MEs.
289 *
290 * Halt or unhalt the async dma engines (CIK).
291 */
292void cik_sdma_enable(struct radeon_device *rdev, bool enable)
293{
294 u32 me_cntl, reg_offset;
295 int i;
296
07ae78c9
AD		 297 if (enable == false) {
298 cik_sdma_gfx_stop(rdev);
299 cik_sdma_rlc_stop(rdev);
300 }
301
2483b4ea
CK		 302 for (i = 0; i < 2; i++) {
303 if (i == 0)
304 reg_offset = SDMA0_REGISTER_OFFSET;
305 else
306 reg_offset = SDMA1_REGISTER_OFFSET;
307 me_cntl = RREG32(SDMA0_ME_CNTL + reg_offset);
308 if (enable)
309 me_cntl &= ~SDMA_HALT;
310 else
311 me_cntl |= SDMA_HALT;
312 WREG32(SDMA0_ME_CNTL + reg_offset, me_cntl);
313 }
314}
315
316/**
317 * cik_sdma_gfx_resume - setup and start the async dma engines
318 *
319 * @rdev: radeon_device pointer
320 *
321 * Set up the gfx DMA ring buffers and enable them (CIK).
322 * Returns 0 for success, error for failure.
323 */
324static int cik_sdma_gfx_resume(struct radeon_device *rdev)
325{
326 struct radeon_ring *ring;
327 u32 rb_cntl, ib_cntl;
328 u32 rb_bufsz;
329 u32 reg_offset, wb_offset;
330 int i, r;
331
332 for (i = 0; i < 2; i++) {
333 if (i == 0) {
334 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
335 reg_offset = SDMA0_REGISTER_OFFSET;
336 wb_offset = R600_WB_DMA_RPTR_OFFSET;
337 } else {
338 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
339 reg_offset = SDMA1_REGISTER_OFFSET;
340 wb_offset = CAYMAN_WB_DMA1_RPTR_OFFSET;
341 }
342
343 WREG32(SDMA0_SEM_INCOMPLETE_TIMER_CNTL + reg_offset, 0);
344 WREG32(SDMA0_SEM_WAIT_FAIL_TIMER_CNTL + reg_offset, 0);
345
346 /* Set ring buffer size in dwords */
9c725e5b 347 rb_bufsz = order_base_2(ring->ring_size / 4);
2483b4ea
CK		 348 rb_cntl = rb_bufsz << 1;
349#ifdef __BIG_ENDIAN
350 rb_cntl |= SDMA_RB_SWAP_ENABLE | SDMA_RPTR_WRITEBACK_SWAP_ENABLE;
351#endif
352 WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl);
353
354 /* Initialize the ring buffer's read and write pointers */
355 WREG32(SDMA0_GFX_RB_RPTR + reg_offset, 0);
356 WREG32(SDMA0_GFX_RB_WPTR + reg_offset, 0);
357
358 /* set the wb address whether it's enabled or not */
359 WREG32(SDMA0_GFX_RB_RPTR_ADDR_HI + reg_offset,
360 upper_32_bits(rdev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
361 WREG32(SDMA0_GFX_RB_RPTR_ADDR_LO + reg_offset,
362 ((rdev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC));
363
364 if (rdev->wb.enabled)
365 rb_cntl |= SDMA_RPTR_WRITEBACK_ENABLE;
366
367 WREG32(SDMA0_GFX_RB_BASE + reg_offset, ring->gpu_addr >> 8);
368 WREG32(SDMA0_GFX_RB_BASE_HI + reg_offset, ring->gpu_addr >> 40);
369
370 ring->wptr = 0;
371 WREG32(SDMA0_GFX_RB_WPTR + reg_offset, ring->wptr << 2);
372
2483b4ea
CK		 373 /* enable DMA RB */
374 WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl | SDMA_RB_ENABLE);
375
376 ib_cntl = SDMA_IB_ENABLE;
377#ifdef __BIG_ENDIAN
378 ib_cntl |= SDMA_IB_SWAP_ENABLE;
379#endif
380 /* enable DMA IBs */
381 WREG32(SDMA0_GFX_IB_CNTL + reg_offset, ib_cntl);
382
383 ring->ready = true;
384
385 r = radeon_ring_test(rdev, ring->idx, ring);
386 if (r) {
387 ring->ready = false;
388 return r;
389 }
390 }
391
50efa51a
AD		 392 if ((rdev->asic->copy.copy_ring_index == R600_RING_TYPE_DMA_INDEX) ||
393 (rdev->asic->copy.copy_ring_index == CAYMAN_RING_TYPE_DMA1_INDEX))
394 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
2483b4ea
CK		 395
396 return 0;
397}
398
399/**
400 * cik_sdma_rlc_resume - setup and start the async dma engines
401 *
402 * @rdev: radeon_device pointer
403 *
404 * Set up the compute DMA queues and enable them (CIK).
405 * Returns 0 for success, error for failure.
406 */
407static int cik_sdma_rlc_resume(struct radeon_device *rdev)
408{
409 /* XXX todo */
410 return 0;
411}
412
413/**
414 * cik_sdma_load_microcode - load the sDMA ME ucode
415 *
416 * @rdev: radeon_device pointer
417 *
418 * Loads the sDMA0/1 ucode.
419 * Returns 0 for success, -EINVAL if the ucode is not available.
420 */
421static int cik_sdma_load_microcode(struct radeon_device *rdev)
422{
2483b4ea
CK		 423 int i;
424
425 if (!rdev->sdma_fw)
426 return -EINVAL;
427
2483b4ea
CK		 428 /* halt the MEs */
429 cik_sdma_enable(rdev, false);
430
f2c6b0f4
AD		 431 if (rdev->new_fw) {
432 const struct sdma_firmware_header_v1_0 *hdr =
433 (const struct sdma_firmware_header_v1_0 *)rdev->sdma_fw->data;
434 const __le32 *fw_data;
435 u32 fw_size;
436
437 radeon_ucode_print_sdma_hdr(&hdr->header);
438
439 /* sdma0 */
440 fw_data = (const __le32 *)
441 (rdev->sdma_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
442 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
443 WREG32(SDMA0_UCODE_ADDR + SDMA0_REGISTER_OFFSET, 0);
444 for (i = 0; i < fw_size; i++)
445 WREG32(SDMA0_UCODE_DATA + SDMA0_REGISTER_OFFSET, le32_to_cpup(fw_data++));
446 WREG32(SDMA0_UCODE_DATA + SDMA0_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION);
447
448 /* sdma1 */
449 fw_data = (const __le32 *)
450 (rdev->sdma_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
451 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
452 WREG32(SDMA0_UCODE_ADDR + SDMA1_REGISTER_OFFSET, 0);
453 for (i = 0; i < fw_size; i++)
454 WREG32(SDMA0_UCODE_DATA + SDMA1_REGISTER_OFFSET, le32_to_cpup(fw_data++));
455 WREG32(SDMA0_UCODE_DATA + SDMA1_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION);
456 } else {
457 const __be32 *fw_data;
458
459 /* sdma0 */
460 fw_data = (const __be32 *)rdev->sdma_fw->data;
461 WREG32(SDMA0_UCODE_ADDR + SDMA0_REGISTER_OFFSET, 0);
462 for (i = 0; i < CIK_SDMA_UCODE_SIZE; i++)
463 WREG32(SDMA0_UCODE_DATA + SDMA0_REGISTER_OFFSET, be32_to_cpup(fw_data++));
464 WREG32(SDMA0_UCODE_DATA + SDMA0_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION);
465
466 /* sdma1 */
467 fw_data = (const __be32 *)rdev->sdma_fw->data;
468 WREG32(SDMA0_UCODE_ADDR + SDMA1_REGISTER_OFFSET, 0);
469 for (i = 0; i < CIK_SDMA_UCODE_SIZE; i++)
470 WREG32(SDMA0_UCODE_DATA + SDMA1_REGISTER_OFFSET, be32_to_cpup(fw_data++));
471 WREG32(SDMA0_UCODE_DATA + SDMA1_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION);
472 }
2483b4ea
CK		 473
474 WREG32(SDMA0_UCODE_ADDR + SDMA0_REGISTER_OFFSET, 0);
475 WREG32(SDMA0_UCODE_ADDR + SDMA1_REGISTER_OFFSET, 0);
476 return 0;
477}
478
479/**
480 * cik_sdma_resume - setup and start the async dma engines
481 *
482 * @rdev: radeon_device pointer
483 *
484 * Set up the DMA engines and enable them (CIK).
485 * Returns 0 for success, error for failure.
486 */
487int cik_sdma_resume(struct radeon_device *rdev)
488{
489 int r;
490
491 /* Reset dma */
492 WREG32(SRBM_SOFT_RESET, SOFT_RESET_SDMA | SOFT_RESET_SDMA1);
493 RREG32(SRBM_SOFT_RESET);
494 udelay(50);
495 WREG32(SRBM_SOFT_RESET, 0);
496 RREG32(SRBM_SOFT_RESET);
497
498 r = cik_sdma_load_microcode(rdev);
499 if (r)
500 return r;
501
502 /* unhalt the MEs */
503 cik_sdma_enable(rdev, true);
504
505 /* start the gfx rings and rlc compute queues */
506 r = cik_sdma_gfx_resume(rdev);
507 if (r)
508 return r;
509 r = cik_sdma_rlc_resume(rdev);
510 if (r)
511 return r;
512
513 return 0;
514}
515
516/**
517 * cik_sdma_fini - tear down the async dma engines
518 *
519 * @rdev: radeon_device pointer
520 *
521 * Stop the async dma engines and free the rings (CIK).
522 */
523void cik_sdma_fini(struct radeon_device *rdev)
524{
2483b4ea
CK		 525 /* halt the MEs */
526 cik_sdma_enable(rdev, false);
527 radeon_ring_fini(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX]);
528 radeon_ring_fini(rdev, &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]);
529 /* XXX - compute dma queue tear down */
530}
531
532/**
533 * cik_copy_dma - copy pages using the DMA engine
534 *
535 * @rdev: radeon_device pointer
536 * @src_offset: src GPU address
537 * @dst_offset: dst GPU address
538 * @num_gpu_pages: number of GPU pages to xfer
539 * @fence: radeon fence object
540 *
541 * Copy GPU paging using the DMA engine (CIK).
542 * Used by the radeon ttm implementation to move pages if
543 * registered as the asic copy callback.
544 */
545int cik_copy_dma(struct radeon_device *rdev,
546 uint64_t src_offset, uint64_t dst_offset,
547 unsigned num_gpu_pages,
548 struct radeon_fence **fence)
549{
550 struct radeon_semaphore *sem = NULL;
551 int ring_index = rdev->asic->copy.dma_ring_index;
552 struct radeon_ring *ring = &rdev->ring[ring_index];
553 u32 size_in_bytes, cur_size_in_bytes;
554 int i, num_loops;
555 int r = 0;
556
557 r = radeon_semaphore_create(rdev, &sem);
558 if (r) {
559 DRM_ERROR("radeon: moving bo (%d).\n", r);
560 return r;
561 }
562
563 size_in_bytes = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT);
564 num_loops = DIV_ROUND_UP(size_in_bytes, 0x1fffff);
565 r = radeon_ring_lock(rdev, ring, num_loops * 7 + 14);
566 if (r) {
567 DRM_ERROR("radeon: moving bo (%d).\n", r);
568 radeon_semaphore_free(rdev, &sem, NULL);
569 return r;
570 }
571
1654b817
CK		 572 radeon_semaphore_sync_to(sem, *fence);
573 radeon_semaphore_sync_rings(rdev, sem, ring->idx);
2483b4ea
CK		 574
575 for (i = 0; i < num_loops; i++) {
576 cur_size_in_bytes = size_in_bytes;
577 if (cur_size_in_bytes > 0x1fffff)
578 cur_size_in_bytes = 0x1fffff;
579 size_in_bytes -= cur_size_in_bytes;
580 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_COPY_SUB_OPCODE_LINEAR, 0));
581 radeon_ring_write(ring, cur_size_in_bytes);
582 radeon_ring_write(ring, 0); /* src/dst endian swap */
5e167cdb
CK		 583 radeon_ring_write(ring, lower_32_bits(src_offset));
584 radeon_ring_write(ring, upper_32_bits(src_offset));
585 radeon_ring_write(ring, lower_32_bits(dst_offset));
586 radeon_ring_write(ring, upper_32_bits(dst_offset));
2483b4ea
CK		 587 src_offset += cur_size_in_bytes;
588 dst_offset += cur_size_in_bytes;
589 }
590
591 r = radeon_fence_emit(rdev, fence, ring->idx);
592 if (r) {
593 radeon_ring_unlock_undo(rdev, ring);
aa4c8b36 594 radeon_semaphore_free(rdev, &sem, NULL);
2483b4ea
CK		 595 return r;
596 }
597
598 radeon_ring_unlock_commit(rdev, ring);
599 radeon_semaphore_free(rdev, &sem, *fence);
600
601 return r;
602}
603
604/**
605 * cik_sdma_ring_test - simple async dma engine test
606 *
607 * @rdev: radeon_device pointer
608 * @ring: radeon_ring structure holding ring information
609 *
610 * Test the DMA engine by writing using it to write an
611 * value to memory. (CIK).
612 * Returns 0 for success, error for failure.
613 */
614int cik_sdma_ring_test(struct radeon_device *rdev,
615 struct radeon_ring *ring)
616{
617 unsigned i;
618 int r;
619 void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
620 u32 tmp;
621
622 if (!ptr) {
623 DRM_ERROR("invalid vram scratch pointer\n");
624 return -EINVAL;
625 }
626
627 tmp = 0xCAFEDEAD;
628 writel(tmp, ptr);
629
7e95cfb0 630 r = radeon_ring_lock(rdev, ring, 5);
2483b4ea
CK		 631 if (r) {
632 DRM_ERROR("radeon: dma failed to lock ring %d (%d).\n", ring->idx, r);
633 return r;
634 }
635 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0));
636 radeon_ring_write(ring, rdev->vram_scratch.gpu_addr & 0xfffffffc);
5e167cdb 637 radeon_ring_write(ring, upper_32_bits(rdev->vram_scratch.gpu_addr));
2483b4ea
CK		 638 radeon_ring_write(ring, 1); /* number of DWs to follow */
639 radeon_ring_write(ring, 0xDEADBEEF);
640 radeon_ring_unlock_commit(rdev, ring);
641
642 for (i = 0; i < rdev->usec_timeout; i++) {
643 tmp = readl(ptr);
644 if (tmp == 0xDEADBEEF)
645 break;
646 DRM_UDELAY(1);
647 }
648
649 if (i < rdev->usec_timeout) {
650 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
651 } else {
652 DRM_ERROR("radeon: ring %d test failed (0x%08X)\n",
653 ring->idx, tmp);
654 r = -EINVAL;
655 }
656 return r;
657}
658
659/**
660 * cik_sdma_ib_test - test an IB on the DMA engine
661 *
662 * @rdev: radeon_device pointer
663 * @ring: radeon_ring structure holding ring information
664 *
665 * Test a simple IB in the DMA ring (CIK).
666 * Returns 0 on success, error on failure.
667 */
668int cik_sdma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
669{
670 struct radeon_ib ib;
671 unsigned i;
672 int r;
673 void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
674 u32 tmp = 0;
675
676 if (!ptr) {
677 DRM_ERROR("invalid vram scratch pointer\n");
678 return -EINVAL;
679 }
680
681 tmp = 0xCAFEDEAD;
682 writel(tmp, ptr);
683
684 r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256);
685 if (r) {
686 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
687 return r;
688 }
689
690 ib.ptr[0] = SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
691 ib.ptr[1] = rdev->vram_scratch.gpu_addr & 0xfffffffc;
5e167cdb 692 ib.ptr[2] = upper_32_bits(rdev->vram_scratch.gpu_addr);
2483b4ea
CK		 693 ib.ptr[3] = 1;
694 ib.ptr[4] = 0xDEADBEEF;
695 ib.length_dw = 5;
696
697 r = radeon_ib_schedule(rdev, &ib, NULL);
698 if (r) {
699 radeon_ib_free(rdev, &ib);
700 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
701 return r;
702 }
703 r = radeon_fence_wait(ib.fence, false);
704 if (r) {
705 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
706 return r;
707 }
708 for (i = 0; i < rdev->usec_timeout; i++) {
709 tmp = readl(ptr);
710 if (tmp == 0xDEADBEEF)
711 break;
712 DRM_UDELAY(1);
713 }
714 if (i < rdev->usec_timeout) {
715 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i);
716 } else {
717 DRM_ERROR("radeon: ib test failed (0x%08X)\n", tmp);
718 r = -EINVAL;
719 }
720 radeon_ib_free(rdev, &ib);
721 return r;
722}
723
724/**
725 * cik_sdma_is_lockup - Check if the DMA engine is locked up
726 *
727 * @rdev: radeon_device pointer
728 * @ring: radeon_ring structure holding ring information
729 *
730 * Check if the async DMA engine is locked up (CIK).
731 * Returns true if the engine appears to be locked up, false if not.
732 */
733bool cik_sdma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
734{
735 u32 reset_mask = cik_gpu_check_soft_reset(rdev);
736 u32 mask;
737
738 if (ring->idx == R600_RING_TYPE_DMA_INDEX)
739 mask = RADEON_RESET_DMA;
740 else
741 mask = RADEON_RESET_DMA1;
742
743 if (!(reset_mask & mask)) {
ff212f25 744 radeon_ring_lockup_update(rdev, ring);
2483b4ea
CK		 745 return false;
746 }
2483b4ea
CK		 747 return radeon_ring_test_lockup(rdev, ring);
748}
749
750/**
751 * cik_sdma_vm_set_page - update the page tables using sDMA
752 *
753 * @rdev: radeon_device pointer
754 * @ib: indirect buffer to fill with commands
755 * @pe: addr of the page entry
756 * @addr: dst addr to write into pe
757 * @count: number of page entries to update
758 * @incr: increase next addr by incr bytes
759 * @flags: access flags
760 *
761 * Update the page tables using sDMA (CIK).
762 */
763void cik_sdma_vm_set_page(struct radeon_device *rdev,
764 struct radeon_ib *ib,
765 uint64_t pe,
766 uint64_t addr, unsigned count,
767 uint32_t incr, uint32_t flags)
768{
2483b4ea
CK		 769 uint64_t value;
770 unsigned ndw;
771
24c16439 772 trace_radeon_vm_set_page(pe, addr, count, incr, flags);
74d360f6 773
33fa9fe3 774 if ((flags & R600_PTE_GART_MASK) == R600_PTE_GART_MASK) {
3d7938fa
CK		 775 uint64_t src = rdev->gart.table_addr + (addr >> 12) * 8;
776 while (count) {
777 unsigned bytes = count * 8;
778 if (bytes > 0x1FFFF8)
779 bytes = 0x1FFFF8;
780
781 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
782 ib->ptr[ib->length_dw++] = bytes;
783 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
5e167cdb 784 ib->ptr[ib->length_dw++] = lower_32_bits(src);
3d7938fa 785 ib->ptr[ib->length_dw++] = upper_32_bits(src);
5e167cdb 786 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
3d7938fa
CK		 787 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
788
789 pe += bytes;
790 src += bytes;
791 count -= bytes / 8;
792 }
793 } else if (flags & R600_PTE_SYSTEM) {
2483b4ea
CK		 794 while (count) {
795 ndw = count * 2;
796 if (ndw > 0xFFFFE)
797 ndw = 0xFFFFE;
798
799 /* for non-physically contiguous pages (system) */
800 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
801 ib->ptr[ib->length_dw++] = pe;
802 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
803 ib->ptr[ib->length_dw++] = ndw;
804 for (; ndw > 0; ndw -= 2, --count, pe += 8) {
24c16439
CK		 805 value = radeon_vm_map_gart(rdev, addr);
806 value &= 0xFFFFFFFFFFFFF000ULL;
2483b4ea 807 addr += incr;
24c16439 808 value |= flags;
2483b4ea
CK		 809 ib->ptr[ib->length_dw++] = value;
810 ib->ptr[ib->length_dw++] = upper_32_bits(value);
811 }
812 }
813 } else {
814 while (count) {
815 ndw = count;
816 if (ndw > 0x7FFFF)
817 ndw = 0x7FFFF;
818
24c16439 819 if (flags & R600_PTE_VALID)
2483b4ea
CK		 820 value = addr;
821 else
822 value = 0;
823 /* for physically contiguous pages (vram) */
824 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_GENERATE_PTE_PDE, 0, 0);
825 ib->ptr[ib->length_dw++] = pe; /* dst addr */
826 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
24c16439 827 ib->ptr[ib->length_dw++] = flags; /* mask */
2483b4ea
CK		 828 ib->ptr[ib->length_dw++] = 0;
829 ib->ptr[ib->length_dw++] = value; /* value */
830 ib->ptr[ib->length_dw++] = upper_32_bits(value);
831 ib->ptr[ib->length_dw++] = incr; /* increment size */
832 ib->ptr[ib->length_dw++] = 0;
833 ib->ptr[ib->length_dw++] = ndw; /* number of entries */
834 pe += ndw * 8;
835 addr += ndw * incr;
836 count -= ndw;
837 }
838 }
839 while (ib->length_dw & 0x7)
840 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0);
841}
842
843/**
844 * cik_dma_vm_flush - cik vm flush using sDMA
845 *
846 * @rdev: radeon_device pointer
847 *
848 * Update the page table base and flush the VM TLB
849 * using sDMA (CIK).
850 */
851void cik_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm)
852{
853 struct radeon_ring *ring = &rdev->ring[ridx];
2483b4ea
CK		 854
855 if (vm == NULL)
856 return;
857
2483b4ea
CK		 858 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
859 if (vm->id < 8) {
860 radeon_ring_write(ring, (VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2)) >> 2);
861 } else {
862 radeon_ring_write(ring, (VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((vm->id - 8) << 2)) >> 2);
863 }
864 radeon_ring_write(ring, vm->pd_gpu_addr >> 12);
865
866 /* update SH_MEM_* regs */
867 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
868 radeon_ring_write(ring, SRBM_GFX_CNTL >> 2);
869 radeon_ring_write(ring, VMID(vm->id));
870
871 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
872 radeon_ring_write(ring, SH_MEM_BASES >> 2);
873 radeon_ring_write(ring, 0);
874
875 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
876 radeon_ring_write(ring, SH_MEM_CONFIG >> 2);
877 radeon_ring_write(ring, 0);
878
879 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
880 radeon_ring_write(ring, SH_MEM_APE1_BASE >> 2);
881 radeon_ring_write(ring, 1);
882
883 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
884 radeon_ring_write(ring, SH_MEM_APE1_LIMIT >> 2);
885 radeon_ring_write(ring, 0);
886
887 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
888 radeon_ring_write(ring, SRBM_GFX_CNTL >> 2);
889 radeon_ring_write(ring, VMID(0));
890
891 /* flush HDP */
ca113f6b 892 cik_sdma_hdp_flush_ring_emit(rdev, ridx);
2483b4ea
CK		 893
894 /* flush TLB */
895 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
896 radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2);
897 radeon_ring_write(ring, 1 << vm->id);
898}
899
Linux kernel - Deliverables
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