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2483b4ea CK |
1 | /* |
2 | * Copyright 2013 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Alex Deucher | |
23 | */ | |
24 | #include <linux/firmware.h> | |
25 | #include <drm/drmP.h> | |
26 | #include "radeon.h" | |
27 | #include "radeon_asic.h" | |
74d360f6 | 28 | #include "radeon_trace.h" |
2483b4ea CK |
29 | #include "cikd.h" |
30 | ||
31 | /* sdma */ | |
32 | #define CIK_SDMA_UCODE_SIZE 1050 | |
33 | #define CIK_SDMA_UCODE_VERSION 64 | |
34 | ||
35 | u32 cik_gpu_check_soft_reset(struct radeon_device *rdev); | |
36 | ||
37 | /* | |
38 | * sDMA - System DMA | |
39 | * Starting with CIK, the GPU has new asynchronous | |
40 | * DMA engines. These engines are used for compute | |
41 | * and gfx. There are two DMA engines (SDMA0, SDMA1) | |
42 | * and each one supports 1 ring buffer used for gfx | |
43 | * and 2 queues used for compute. | |
44 | * | |
45 | * The programming model is very similar to the CP | |
46 | * (ring buffer, IBs, etc.), but sDMA has it's own | |
47 | * packet format that is different from the PM4 format | |
48 | * used by the CP. sDMA supports copying data, writing | |
49 | * embedded data, solid fills, and a number of other | |
50 | * things. It also has support for tiling/detiling of | |
51 | * buffers. | |
52 | */ | |
53 | ||
ea31bf69 AD |
54 | /** |
55 | * cik_sdma_get_rptr - get the current read pointer | |
56 | * | |
57 | * @rdev: radeon_device pointer | |
58 | * @ring: radeon ring pointer | |
59 | * | |
60 | * Get the current rptr from the hardware (CIK+). | |
61 | */ | |
62 | uint32_t cik_sdma_get_rptr(struct radeon_device *rdev, | |
63 | struct radeon_ring *ring) | |
64 | { | |
65 | u32 rptr, reg; | |
66 | ||
67 | if (rdev->wb.enabled) { | |
68 | rptr = rdev->wb.wb[ring->rptr_offs/4]; | |
69 | } else { | |
70 | if (ring->idx == R600_RING_TYPE_DMA_INDEX) | |
71 | reg = SDMA0_GFX_RB_RPTR + SDMA0_REGISTER_OFFSET; | |
72 | else | |
73 | reg = SDMA0_GFX_RB_RPTR + SDMA1_REGISTER_OFFSET; | |
74 | ||
75 | rptr = RREG32(reg); | |
76 | } | |
77 | ||
78 | return (rptr & 0x3fffc) >> 2; | |
79 | } | |
80 | ||
81 | /** | |
82 | * cik_sdma_get_wptr - get the current write pointer | |
83 | * | |
84 | * @rdev: radeon_device pointer | |
85 | * @ring: radeon ring pointer | |
86 | * | |
87 | * Get the current wptr from the hardware (CIK+). | |
88 | */ | |
89 | uint32_t cik_sdma_get_wptr(struct radeon_device *rdev, | |
90 | struct radeon_ring *ring) | |
91 | { | |
92 | u32 reg; | |
93 | ||
94 | if (ring->idx == R600_RING_TYPE_DMA_INDEX) | |
95 | reg = SDMA0_GFX_RB_WPTR + SDMA0_REGISTER_OFFSET; | |
96 | else | |
97 | reg = SDMA0_GFX_RB_WPTR + SDMA1_REGISTER_OFFSET; | |
98 | ||
99 | return (RREG32(reg) & 0x3fffc) >> 2; | |
100 | } | |
101 | ||
102 | /** | |
103 | * cik_sdma_set_wptr - commit the write pointer | |
104 | * | |
105 | * @rdev: radeon_device pointer | |
106 | * @ring: radeon ring pointer | |
107 | * | |
108 | * Write the wptr back to the hardware (CIK+). | |
109 | */ | |
110 | void cik_sdma_set_wptr(struct radeon_device *rdev, | |
111 | struct radeon_ring *ring) | |
112 | { | |
113 | u32 reg; | |
114 | ||
115 | if (ring->idx == R600_RING_TYPE_DMA_INDEX) | |
116 | reg = SDMA0_GFX_RB_WPTR + SDMA0_REGISTER_OFFSET; | |
117 | else | |
118 | reg = SDMA0_GFX_RB_WPTR + SDMA1_REGISTER_OFFSET; | |
119 | ||
120 | WREG32(reg, (ring->wptr << 2) & 0x3fffc); | |
121 | } | |
122 | ||
2483b4ea CK |
123 | /** |
124 | * cik_sdma_ring_ib_execute - Schedule an IB on the DMA engine | |
125 | * | |
126 | * @rdev: radeon_device pointer | |
127 | * @ib: IB object to schedule | |
128 | * | |
129 | * Schedule an IB in the DMA ring (CIK). | |
130 | */ | |
131 | void cik_sdma_ring_ib_execute(struct radeon_device *rdev, | |
132 | struct radeon_ib *ib) | |
133 | { | |
134 | struct radeon_ring *ring = &rdev->ring[ib->ring]; | |
135 | u32 extra_bits = (ib->vm ? ib->vm->id : 0) & 0xf; | |
136 | ||
137 | if (rdev->wb.enabled) { | |
138 | u32 next_rptr = ring->wptr + 5; | |
139 | while ((next_rptr & 7) != 4) | |
140 | next_rptr++; | |
141 | next_rptr += 4; | |
142 | radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0)); | |
143 | radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); | |
144 | radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff); | |
145 | radeon_ring_write(ring, 1); /* number of DWs to follow */ | |
146 | radeon_ring_write(ring, next_rptr); | |
147 | } | |
148 | ||
149 | /* IB packet must end on a 8 DW boundary */ | |
150 | while ((ring->wptr & 7) != 4) | |
151 | radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0)); | |
152 | radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_INDIRECT_BUFFER, 0, extra_bits)); | |
153 | radeon_ring_write(ring, ib->gpu_addr & 0xffffffe0); /* base must be 32 byte aligned */ | |
154 | radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xffffffff); | |
155 | radeon_ring_write(ring, ib->length_dw); | |
156 | ||
157 | } | |
158 | ||
ca113f6b AD |
159 | /** |
160 | * cik_sdma_hdp_flush_ring_emit - emit an hdp flush on the DMA ring | |
161 | * | |
162 | * @rdev: radeon_device pointer | |
163 | * @ridx: radeon ring index | |
164 | * | |
165 | * Emit an hdp flush packet on the requested DMA ring. | |
166 | */ | |
167 | static void cik_sdma_hdp_flush_ring_emit(struct radeon_device *rdev, | |
168 | int ridx) | |
169 | { | |
170 | struct radeon_ring *ring = &rdev->ring[ridx]; | |
da9e07e6 AD |
171 | u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(1) | |
172 | SDMA_POLL_REG_MEM_EXTRA_FUNC(3)); /* == */ | |
173 | u32 ref_and_mask; | |
ca113f6b | 174 | |
da9e07e6 AD |
175 | if (ridx == R600_RING_TYPE_DMA_INDEX) |
176 | ref_and_mask = SDMA0; | |
177 | else | |
178 | ref_and_mask = SDMA1; | |
179 | ||
180 | radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits)); | |
181 | radeon_ring_write(ring, GPU_HDP_FLUSH_DONE); | |
182 | radeon_ring_write(ring, GPU_HDP_FLUSH_REQ); | |
183 | radeon_ring_write(ring, ref_and_mask); /* reference */ | |
184 | radeon_ring_write(ring, ref_and_mask); /* mask */ | |
185 | radeon_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */ | |
ca113f6b AD |
186 | } |
187 | ||
2483b4ea CK |
188 | /** |
189 | * cik_sdma_fence_ring_emit - emit a fence on the DMA ring | |
190 | * | |
191 | * @rdev: radeon_device pointer | |
192 | * @fence: radeon fence object | |
193 | * | |
194 | * Add a DMA fence packet to the ring to write | |
195 | * the fence seq number and DMA trap packet to generate | |
196 | * an interrupt if needed (CIK). | |
197 | */ | |
198 | void cik_sdma_fence_ring_emit(struct radeon_device *rdev, | |
199 | struct radeon_fence *fence) | |
200 | { | |
201 | struct radeon_ring *ring = &rdev->ring[fence->ring]; | |
202 | u64 addr = rdev->fence_drv[fence->ring].gpu_addr; | |
2483b4ea CK |
203 | |
204 | /* write the fence */ | |
205 | radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0)); | |
206 | radeon_ring_write(ring, addr & 0xffffffff); | |
207 | radeon_ring_write(ring, upper_32_bits(addr) & 0xffffffff); | |
208 | radeon_ring_write(ring, fence->seq); | |
209 | /* generate an interrupt */ | |
210 | radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_TRAP, 0, 0)); | |
211 | /* flush HDP */ | |
ca113f6b | 212 | cik_sdma_hdp_flush_ring_emit(rdev, fence->ring); |
2483b4ea CK |
213 | } |
214 | ||
215 | /** | |
216 | * cik_sdma_semaphore_ring_emit - emit a semaphore on the dma ring | |
217 | * | |
218 | * @rdev: radeon_device pointer | |
219 | * @ring: radeon_ring structure holding ring information | |
220 | * @semaphore: radeon semaphore object | |
221 | * @emit_wait: wait or signal semaphore | |
222 | * | |
223 | * Add a DMA semaphore packet to the ring wait on or signal | |
224 | * other rings (CIK). | |
225 | */ | |
1654b817 | 226 | bool cik_sdma_semaphore_ring_emit(struct radeon_device *rdev, |
2483b4ea CK |
227 | struct radeon_ring *ring, |
228 | struct radeon_semaphore *semaphore, | |
229 | bool emit_wait) | |
230 | { | |
231 | u64 addr = semaphore->gpu_addr; | |
232 | u32 extra_bits = emit_wait ? 0 : SDMA_SEMAPHORE_EXTRA_S; | |
233 | ||
234 | radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SEMAPHORE, 0, extra_bits)); | |
235 | radeon_ring_write(ring, addr & 0xfffffff8); | |
236 | radeon_ring_write(ring, upper_32_bits(addr) & 0xffffffff); | |
1654b817 CK |
237 | |
238 | return true; | |
2483b4ea CK |
239 | } |
240 | ||
241 | /** | |
242 | * cik_sdma_gfx_stop - stop the gfx async dma engines | |
243 | * | |
244 | * @rdev: radeon_device pointer | |
245 | * | |
246 | * Stop the gfx async dma ring buffers (CIK). | |
247 | */ | |
248 | static void cik_sdma_gfx_stop(struct radeon_device *rdev) | |
249 | { | |
250 | u32 rb_cntl, reg_offset; | |
251 | int i; | |
252 | ||
253 | radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); | |
254 | ||
255 | for (i = 0; i < 2; i++) { | |
256 | if (i == 0) | |
257 | reg_offset = SDMA0_REGISTER_OFFSET; | |
258 | else | |
259 | reg_offset = SDMA1_REGISTER_OFFSET; | |
260 | rb_cntl = RREG32(SDMA0_GFX_RB_CNTL + reg_offset); | |
261 | rb_cntl &= ~SDMA_RB_ENABLE; | |
262 | WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl); | |
263 | WREG32(SDMA0_GFX_IB_CNTL + reg_offset, 0); | |
264 | } | |
265 | } | |
266 | ||
267 | /** | |
268 | * cik_sdma_rlc_stop - stop the compute async dma engines | |
269 | * | |
270 | * @rdev: radeon_device pointer | |
271 | * | |
272 | * Stop the compute async dma queues (CIK). | |
273 | */ | |
274 | static void cik_sdma_rlc_stop(struct radeon_device *rdev) | |
275 | { | |
276 | /* XXX todo */ | |
277 | } | |
278 | ||
279 | /** | |
280 | * cik_sdma_enable - stop the async dma engines | |
281 | * | |
282 | * @rdev: radeon_device pointer | |
283 | * @enable: enable/disable the DMA MEs. | |
284 | * | |
285 | * Halt or unhalt the async dma engines (CIK). | |
286 | */ | |
287 | void cik_sdma_enable(struct radeon_device *rdev, bool enable) | |
288 | { | |
289 | u32 me_cntl, reg_offset; | |
290 | int i; | |
291 | ||
292 | for (i = 0; i < 2; i++) { | |
293 | if (i == 0) | |
294 | reg_offset = SDMA0_REGISTER_OFFSET; | |
295 | else | |
296 | reg_offset = SDMA1_REGISTER_OFFSET; | |
297 | me_cntl = RREG32(SDMA0_ME_CNTL + reg_offset); | |
298 | if (enable) | |
299 | me_cntl &= ~SDMA_HALT; | |
300 | else | |
301 | me_cntl |= SDMA_HALT; | |
302 | WREG32(SDMA0_ME_CNTL + reg_offset, me_cntl); | |
303 | } | |
304 | } | |
305 | ||
306 | /** | |
307 | * cik_sdma_gfx_resume - setup and start the async dma engines | |
308 | * | |
309 | * @rdev: radeon_device pointer | |
310 | * | |
311 | * Set up the gfx DMA ring buffers and enable them (CIK). | |
312 | * Returns 0 for success, error for failure. | |
313 | */ | |
314 | static int cik_sdma_gfx_resume(struct radeon_device *rdev) | |
315 | { | |
316 | struct radeon_ring *ring; | |
317 | u32 rb_cntl, ib_cntl; | |
318 | u32 rb_bufsz; | |
319 | u32 reg_offset, wb_offset; | |
320 | int i, r; | |
321 | ||
322 | for (i = 0; i < 2; i++) { | |
323 | if (i == 0) { | |
324 | ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; | |
325 | reg_offset = SDMA0_REGISTER_OFFSET; | |
326 | wb_offset = R600_WB_DMA_RPTR_OFFSET; | |
327 | } else { | |
328 | ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]; | |
329 | reg_offset = SDMA1_REGISTER_OFFSET; | |
330 | wb_offset = CAYMAN_WB_DMA1_RPTR_OFFSET; | |
331 | } | |
332 | ||
333 | WREG32(SDMA0_SEM_INCOMPLETE_TIMER_CNTL + reg_offset, 0); | |
334 | WREG32(SDMA0_SEM_WAIT_FAIL_TIMER_CNTL + reg_offset, 0); | |
335 | ||
336 | /* Set ring buffer size in dwords */ | |
9c725e5b | 337 | rb_bufsz = order_base_2(ring->ring_size / 4); |
2483b4ea CK |
338 | rb_cntl = rb_bufsz << 1; |
339 | #ifdef __BIG_ENDIAN | |
340 | rb_cntl |= SDMA_RB_SWAP_ENABLE | SDMA_RPTR_WRITEBACK_SWAP_ENABLE; | |
341 | #endif | |
342 | WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl); | |
343 | ||
344 | /* Initialize the ring buffer's read and write pointers */ | |
345 | WREG32(SDMA0_GFX_RB_RPTR + reg_offset, 0); | |
346 | WREG32(SDMA0_GFX_RB_WPTR + reg_offset, 0); | |
347 | ||
348 | /* set the wb address whether it's enabled or not */ | |
349 | WREG32(SDMA0_GFX_RB_RPTR_ADDR_HI + reg_offset, | |
350 | upper_32_bits(rdev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); | |
351 | WREG32(SDMA0_GFX_RB_RPTR_ADDR_LO + reg_offset, | |
352 | ((rdev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC)); | |
353 | ||
354 | if (rdev->wb.enabled) | |
355 | rb_cntl |= SDMA_RPTR_WRITEBACK_ENABLE; | |
356 | ||
357 | WREG32(SDMA0_GFX_RB_BASE + reg_offset, ring->gpu_addr >> 8); | |
358 | WREG32(SDMA0_GFX_RB_BASE_HI + reg_offset, ring->gpu_addr >> 40); | |
359 | ||
360 | ring->wptr = 0; | |
361 | WREG32(SDMA0_GFX_RB_WPTR + reg_offset, ring->wptr << 2); | |
362 | ||
363 | ring->rptr = RREG32(SDMA0_GFX_RB_RPTR + reg_offset) >> 2; | |
364 | ||
365 | /* enable DMA RB */ | |
366 | WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl | SDMA_RB_ENABLE); | |
367 | ||
368 | ib_cntl = SDMA_IB_ENABLE; | |
369 | #ifdef __BIG_ENDIAN | |
370 | ib_cntl |= SDMA_IB_SWAP_ENABLE; | |
371 | #endif | |
372 | /* enable DMA IBs */ | |
373 | WREG32(SDMA0_GFX_IB_CNTL + reg_offset, ib_cntl); | |
374 | ||
375 | ring->ready = true; | |
376 | ||
377 | r = radeon_ring_test(rdev, ring->idx, ring); | |
378 | if (r) { | |
379 | ring->ready = false; | |
380 | return r; | |
381 | } | |
382 | } | |
383 | ||
384 | radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size); | |
385 | ||
386 | return 0; | |
387 | } | |
388 | ||
389 | /** | |
390 | * cik_sdma_rlc_resume - setup and start the async dma engines | |
391 | * | |
392 | * @rdev: radeon_device pointer | |
393 | * | |
394 | * Set up the compute DMA queues and enable them (CIK). | |
395 | * Returns 0 for success, error for failure. | |
396 | */ | |
397 | static int cik_sdma_rlc_resume(struct radeon_device *rdev) | |
398 | { | |
399 | /* XXX todo */ | |
400 | return 0; | |
401 | } | |
402 | ||
403 | /** | |
404 | * cik_sdma_load_microcode - load the sDMA ME ucode | |
405 | * | |
406 | * @rdev: radeon_device pointer | |
407 | * | |
408 | * Loads the sDMA0/1 ucode. | |
409 | * Returns 0 for success, -EINVAL if the ucode is not available. | |
410 | */ | |
411 | static int cik_sdma_load_microcode(struct radeon_device *rdev) | |
412 | { | |
413 | const __be32 *fw_data; | |
414 | int i; | |
415 | ||
416 | if (!rdev->sdma_fw) | |
417 | return -EINVAL; | |
418 | ||
419 | /* stop the gfx rings and rlc compute queues */ | |
420 | cik_sdma_gfx_stop(rdev); | |
421 | cik_sdma_rlc_stop(rdev); | |
422 | ||
423 | /* halt the MEs */ | |
424 | cik_sdma_enable(rdev, false); | |
425 | ||
426 | /* sdma0 */ | |
427 | fw_data = (const __be32 *)rdev->sdma_fw->data; | |
428 | WREG32(SDMA0_UCODE_ADDR + SDMA0_REGISTER_OFFSET, 0); | |
429 | for (i = 0; i < CIK_SDMA_UCODE_SIZE; i++) | |
430 | WREG32(SDMA0_UCODE_DATA + SDMA0_REGISTER_OFFSET, be32_to_cpup(fw_data++)); | |
431 | WREG32(SDMA0_UCODE_DATA + SDMA0_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION); | |
432 | ||
433 | /* sdma1 */ | |
434 | fw_data = (const __be32 *)rdev->sdma_fw->data; | |
435 | WREG32(SDMA0_UCODE_ADDR + SDMA1_REGISTER_OFFSET, 0); | |
436 | for (i = 0; i < CIK_SDMA_UCODE_SIZE; i++) | |
437 | WREG32(SDMA0_UCODE_DATA + SDMA1_REGISTER_OFFSET, be32_to_cpup(fw_data++)); | |
438 | WREG32(SDMA0_UCODE_DATA + SDMA1_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION); | |
439 | ||
440 | WREG32(SDMA0_UCODE_ADDR + SDMA0_REGISTER_OFFSET, 0); | |
441 | WREG32(SDMA0_UCODE_ADDR + SDMA1_REGISTER_OFFSET, 0); | |
442 | return 0; | |
443 | } | |
444 | ||
445 | /** | |
446 | * cik_sdma_resume - setup and start the async dma engines | |
447 | * | |
448 | * @rdev: radeon_device pointer | |
449 | * | |
450 | * Set up the DMA engines and enable them (CIK). | |
451 | * Returns 0 for success, error for failure. | |
452 | */ | |
453 | int cik_sdma_resume(struct radeon_device *rdev) | |
454 | { | |
455 | int r; | |
456 | ||
457 | /* Reset dma */ | |
458 | WREG32(SRBM_SOFT_RESET, SOFT_RESET_SDMA | SOFT_RESET_SDMA1); | |
459 | RREG32(SRBM_SOFT_RESET); | |
460 | udelay(50); | |
461 | WREG32(SRBM_SOFT_RESET, 0); | |
462 | RREG32(SRBM_SOFT_RESET); | |
463 | ||
464 | r = cik_sdma_load_microcode(rdev); | |
465 | if (r) | |
466 | return r; | |
467 | ||
468 | /* unhalt the MEs */ | |
469 | cik_sdma_enable(rdev, true); | |
470 | ||
471 | /* start the gfx rings and rlc compute queues */ | |
472 | r = cik_sdma_gfx_resume(rdev); | |
473 | if (r) | |
474 | return r; | |
475 | r = cik_sdma_rlc_resume(rdev); | |
476 | if (r) | |
477 | return r; | |
478 | ||
479 | return 0; | |
480 | } | |
481 | ||
482 | /** | |
483 | * cik_sdma_fini - tear down the async dma engines | |
484 | * | |
485 | * @rdev: radeon_device pointer | |
486 | * | |
487 | * Stop the async dma engines and free the rings (CIK). | |
488 | */ | |
489 | void cik_sdma_fini(struct radeon_device *rdev) | |
490 | { | |
491 | /* stop the gfx rings and rlc compute queues */ | |
492 | cik_sdma_gfx_stop(rdev); | |
493 | cik_sdma_rlc_stop(rdev); | |
494 | /* halt the MEs */ | |
495 | cik_sdma_enable(rdev, false); | |
496 | radeon_ring_fini(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX]); | |
497 | radeon_ring_fini(rdev, &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]); | |
498 | /* XXX - compute dma queue tear down */ | |
499 | } | |
500 | ||
501 | /** | |
502 | * cik_copy_dma - copy pages using the DMA engine | |
503 | * | |
504 | * @rdev: radeon_device pointer | |
505 | * @src_offset: src GPU address | |
506 | * @dst_offset: dst GPU address | |
507 | * @num_gpu_pages: number of GPU pages to xfer | |
508 | * @fence: radeon fence object | |
509 | * | |
510 | * Copy GPU paging using the DMA engine (CIK). | |
511 | * Used by the radeon ttm implementation to move pages if | |
512 | * registered as the asic copy callback. | |
513 | */ | |
514 | int cik_copy_dma(struct radeon_device *rdev, | |
515 | uint64_t src_offset, uint64_t dst_offset, | |
516 | unsigned num_gpu_pages, | |
517 | struct radeon_fence **fence) | |
518 | { | |
519 | struct radeon_semaphore *sem = NULL; | |
520 | int ring_index = rdev->asic->copy.dma_ring_index; | |
521 | struct radeon_ring *ring = &rdev->ring[ring_index]; | |
522 | u32 size_in_bytes, cur_size_in_bytes; | |
523 | int i, num_loops; | |
524 | int r = 0; | |
525 | ||
526 | r = radeon_semaphore_create(rdev, &sem); | |
527 | if (r) { | |
528 | DRM_ERROR("radeon: moving bo (%d).\n", r); | |
529 | return r; | |
530 | } | |
531 | ||
532 | size_in_bytes = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT); | |
533 | num_loops = DIV_ROUND_UP(size_in_bytes, 0x1fffff); | |
534 | r = radeon_ring_lock(rdev, ring, num_loops * 7 + 14); | |
535 | if (r) { | |
536 | DRM_ERROR("radeon: moving bo (%d).\n", r); | |
537 | radeon_semaphore_free(rdev, &sem, NULL); | |
538 | return r; | |
539 | } | |
540 | ||
1654b817 CK |
541 | radeon_semaphore_sync_to(sem, *fence); |
542 | radeon_semaphore_sync_rings(rdev, sem, ring->idx); | |
2483b4ea CK |
543 | |
544 | for (i = 0; i < num_loops; i++) { | |
545 | cur_size_in_bytes = size_in_bytes; | |
546 | if (cur_size_in_bytes > 0x1fffff) | |
547 | cur_size_in_bytes = 0x1fffff; | |
548 | size_in_bytes -= cur_size_in_bytes; | |
549 | radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_COPY_SUB_OPCODE_LINEAR, 0)); | |
550 | radeon_ring_write(ring, cur_size_in_bytes); | |
551 | radeon_ring_write(ring, 0); /* src/dst endian swap */ | |
552 | radeon_ring_write(ring, src_offset & 0xffffffff); | |
553 | radeon_ring_write(ring, upper_32_bits(src_offset) & 0xffffffff); | |
1b3abef8 | 554 | radeon_ring_write(ring, dst_offset & 0xffffffff); |
2483b4ea CK |
555 | radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xffffffff); |
556 | src_offset += cur_size_in_bytes; | |
557 | dst_offset += cur_size_in_bytes; | |
558 | } | |
559 | ||
560 | r = radeon_fence_emit(rdev, fence, ring->idx); | |
561 | if (r) { | |
562 | radeon_ring_unlock_undo(rdev, ring); | |
563 | return r; | |
564 | } | |
565 | ||
566 | radeon_ring_unlock_commit(rdev, ring); | |
567 | radeon_semaphore_free(rdev, &sem, *fence); | |
568 | ||
569 | return r; | |
570 | } | |
571 | ||
572 | /** | |
573 | * cik_sdma_ring_test - simple async dma engine test | |
574 | * | |
575 | * @rdev: radeon_device pointer | |
576 | * @ring: radeon_ring structure holding ring information | |
577 | * | |
578 | * Test the DMA engine by writing using it to write an | |
579 | * value to memory. (CIK). | |
580 | * Returns 0 for success, error for failure. | |
581 | */ | |
582 | int cik_sdma_ring_test(struct radeon_device *rdev, | |
583 | struct radeon_ring *ring) | |
584 | { | |
585 | unsigned i; | |
586 | int r; | |
587 | void __iomem *ptr = (void *)rdev->vram_scratch.ptr; | |
588 | u32 tmp; | |
589 | ||
590 | if (!ptr) { | |
591 | DRM_ERROR("invalid vram scratch pointer\n"); | |
592 | return -EINVAL; | |
593 | } | |
594 | ||
595 | tmp = 0xCAFEDEAD; | |
596 | writel(tmp, ptr); | |
597 | ||
598 | r = radeon_ring_lock(rdev, ring, 4); | |
599 | if (r) { | |
600 | DRM_ERROR("radeon: dma failed to lock ring %d (%d).\n", ring->idx, r); | |
601 | return r; | |
602 | } | |
603 | radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0)); | |
604 | radeon_ring_write(ring, rdev->vram_scratch.gpu_addr & 0xfffffffc); | |
605 | radeon_ring_write(ring, upper_32_bits(rdev->vram_scratch.gpu_addr) & 0xffffffff); | |
606 | radeon_ring_write(ring, 1); /* number of DWs to follow */ | |
607 | radeon_ring_write(ring, 0xDEADBEEF); | |
608 | radeon_ring_unlock_commit(rdev, ring); | |
609 | ||
610 | for (i = 0; i < rdev->usec_timeout; i++) { | |
611 | tmp = readl(ptr); | |
612 | if (tmp == 0xDEADBEEF) | |
613 | break; | |
614 | DRM_UDELAY(1); | |
615 | } | |
616 | ||
617 | if (i < rdev->usec_timeout) { | |
618 | DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i); | |
619 | } else { | |
620 | DRM_ERROR("radeon: ring %d test failed (0x%08X)\n", | |
621 | ring->idx, tmp); | |
622 | r = -EINVAL; | |
623 | } | |
624 | return r; | |
625 | } | |
626 | ||
627 | /** | |
628 | * cik_sdma_ib_test - test an IB on the DMA engine | |
629 | * | |
630 | * @rdev: radeon_device pointer | |
631 | * @ring: radeon_ring structure holding ring information | |
632 | * | |
633 | * Test a simple IB in the DMA ring (CIK). | |
634 | * Returns 0 on success, error on failure. | |
635 | */ | |
636 | int cik_sdma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring) | |
637 | { | |
638 | struct radeon_ib ib; | |
639 | unsigned i; | |
640 | int r; | |
641 | void __iomem *ptr = (void *)rdev->vram_scratch.ptr; | |
642 | u32 tmp = 0; | |
643 | ||
644 | if (!ptr) { | |
645 | DRM_ERROR("invalid vram scratch pointer\n"); | |
646 | return -EINVAL; | |
647 | } | |
648 | ||
649 | tmp = 0xCAFEDEAD; | |
650 | writel(tmp, ptr); | |
651 | ||
652 | r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256); | |
653 | if (r) { | |
654 | DRM_ERROR("radeon: failed to get ib (%d).\n", r); | |
655 | return r; | |
656 | } | |
657 | ||
658 | ib.ptr[0] = SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0); | |
659 | ib.ptr[1] = rdev->vram_scratch.gpu_addr & 0xfffffffc; | |
660 | ib.ptr[2] = upper_32_bits(rdev->vram_scratch.gpu_addr) & 0xffffffff; | |
661 | ib.ptr[3] = 1; | |
662 | ib.ptr[4] = 0xDEADBEEF; | |
663 | ib.length_dw = 5; | |
664 | ||
665 | r = radeon_ib_schedule(rdev, &ib, NULL); | |
666 | if (r) { | |
667 | radeon_ib_free(rdev, &ib); | |
668 | DRM_ERROR("radeon: failed to schedule ib (%d).\n", r); | |
669 | return r; | |
670 | } | |
671 | r = radeon_fence_wait(ib.fence, false); | |
672 | if (r) { | |
673 | DRM_ERROR("radeon: fence wait failed (%d).\n", r); | |
674 | return r; | |
675 | } | |
676 | for (i = 0; i < rdev->usec_timeout; i++) { | |
677 | tmp = readl(ptr); | |
678 | if (tmp == 0xDEADBEEF) | |
679 | break; | |
680 | DRM_UDELAY(1); | |
681 | } | |
682 | if (i < rdev->usec_timeout) { | |
683 | DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i); | |
684 | } else { | |
685 | DRM_ERROR("radeon: ib test failed (0x%08X)\n", tmp); | |
686 | r = -EINVAL; | |
687 | } | |
688 | radeon_ib_free(rdev, &ib); | |
689 | return r; | |
690 | } | |
691 | ||
692 | /** | |
693 | * cik_sdma_is_lockup - Check if the DMA engine is locked up | |
694 | * | |
695 | * @rdev: radeon_device pointer | |
696 | * @ring: radeon_ring structure holding ring information | |
697 | * | |
698 | * Check if the async DMA engine is locked up (CIK). | |
699 | * Returns true if the engine appears to be locked up, false if not. | |
700 | */ | |
701 | bool cik_sdma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) | |
702 | { | |
703 | u32 reset_mask = cik_gpu_check_soft_reset(rdev); | |
704 | u32 mask; | |
705 | ||
706 | if (ring->idx == R600_RING_TYPE_DMA_INDEX) | |
707 | mask = RADEON_RESET_DMA; | |
708 | else | |
709 | mask = RADEON_RESET_DMA1; | |
710 | ||
711 | if (!(reset_mask & mask)) { | |
712 | radeon_ring_lockup_update(ring); | |
713 | return false; | |
714 | } | |
715 | /* force ring activities */ | |
716 | radeon_ring_force_activity(rdev, ring); | |
717 | return radeon_ring_test_lockup(rdev, ring); | |
718 | } | |
719 | ||
720 | /** | |
721 | * cik_sdma_vm_set_page - update the page tables using sDMA | |
722 | * | |
723 | * @rdev: radeon_device pointer | |
724 | * @ib: indirect buffer to fill with commands | |
725 | * @pe: addr of the page entry | |
726 | * @addr: dst addr to write into pe | |
727 | * @count: number of page entries to update | |
728 | * @incr: increase next addr by incr bytes | |
729 | * @flags: access flags | |
730 | * | |
731 | * Update the page tables using sDMA (CIK). | |
732 | */ | |
733 | void cik_sdma_vm_set_page(struct radeon_device *rdev, | |
734 | struct radeon_ib *ib, | |
735 | uint64_t pe, | |
736 | uint64_t addr, unsigned count, | |
737 | uint32_t incr, uint32_t flags) | |
738 | { | |
2483b4ea CK |
739 | uint64_t value; |
740 | unsigned ndw; | |
741 | ||
24c16439 | 742 | trace_radeon_vm_set_page(pe, addr, count, incr, flags); |
74d360f6 | 743 | |
24c16439 | 744 | if (flags & R600_PTE_SYSTEM) { |
2483b4ea CK |
745 | while (count) { |
746 | ndw = count * 2; | |
747 | if (ndw > 0xFFFFE) | |
748 | ndw = 0xFFFFE; | |
749 | ||
750 | /* for non-physically contiguous pages (system) */ | |
751 | ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0); | |
752 | ib->ptr[ib->length_dw++] = pe; | |
753 | ib->ptr[ib->length_dw++] = upper_32_bits(pe); | |
754 | ib->ptr[ib->length_dw++] = ndw; | |
755 | for (; ndw > 0; ndw -= 2, --count, pe += 8) { | |
24c16439 CK |
756 | value = radeon_vm_map_gart(rdev, addr); |
757 | value &= 0xFFFFFFFFFFFFF000ULL; | |
2483b4ea | 758 | addr += incr; |
24c16439 | 759 | value |= flags; |
2483b4ea CK |
760 | ib->ptr[ib->length_dw++] = value; |
761 | ib->ptr[ib->length_dw++] = upper_32_bits(value); | |
762 | } | |
763 | } | |
764 | } else { | |
765 | while (count) { | |
766 | ndw = count; | |
767 | if (ndw > 0x7FFFF) | |
768 | ndw = 0x7FFFF; | |
769 | ||
24c16439 | 770 | if (flags & R600_PTE_VALID) |
2483b4ea CK |
771 | value = addr; |
772 | else | |
773 | value = 0; | |
774 | /* for physically contiguous pages (vram) */ | |
775 | ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_GENERATE_PTE_PDE, 0, 0); | |
776 | ib->ptr[ib->length_dw++] = pe; /* dst addr */ | |
777 | ib->ptr[ib->length_dw++] = upper_32_bits(pe); | |
24c16439 | 778 | ib->ptr[ib->length_dw++] = flags; /* mask */ |
2483b4ea CK |
779 | ib->ptr[ib->length_dw++] = 0; |
780 | ib->ptr[ib->length_dw++] = value; /* value */ | |
781 | ib->ptr[ib->length_dw++] = upper_32_bits(value); | |
782 | ib->ptr[ib->length_dw++] = incr; /* increment size */ | |
783 | ib->ptr[ib->length_dw++] = 0; | |
784 | ib->ptr[ib->length_dw++] = ndw; /* number of entries */ | |
785 | pe += ndw * 8; | |
786 | addr += ndw * incr; | |
787 | count -= ndw; | |
788 | } | |
789 | } | |
790 | while (ib->length_dw & 0x7) | |
791 | ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0); | |
792 | } | |
793 | ||
794 | /** | |
795 | * cik_dma_vm_flush - cik vm flush using sDMA | |
796 | * | |
797 | * @rdev: radeon_device pointer | |
798 | * | |
799 | * Update the page table base and flush the VM TLB | |
800 | * using sDMA (CIK). | |
801 | */ | |
802 | void cik_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm) | |
803 | { | |
804 | struct radeon_ring *ring = &rdev->ring[ridx]; | |
2483b4ea CK |
805 | |
806 | if (vm == NULL) | |
807 | return; | |
808 | ||
2483b4ea CK |
809 | radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); |
810 | if (vm->id < 8) { | |
811 | radeon_ring_write(ring, (VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2)) >> 2); | |
812 | } else { | |
813 | radeon_ring_write(ring, (VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((vm->id - 8) << 2)) >> 2); | |
814 | } | |
815 | radeon_ring_write(ring, vm->pd_gpu_addr >> 12); | |
816 | ||
817 | /* update SH_MEM_* regs */ | |
818 | radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); | |
819 | radeon_ring_write(ring, SRBM_GFX_CNTL >> 2); | |
820 | radeon_ring_write(ring, VMID(vm->id)); | |
821 | ||
822 | radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); | |
823 | radeon_ring_write(ring, SH_MEM_BASES >> 2); | |
824 | radeon_ring_write(ring, 0); | |
825 | ||
826 | radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); | |
827 | radeon_ring_write(ring, SH_MEM_CONFIG >> 2); | |
828 | radeon_ring_write(ring, 0); | |
829 | ||
830 | radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); | |
831 | radeon_ring_write(ring, SH_MEM_APE1_BASE >> 2); | |
832 | radeon_ring_write(ring, 1); | |
833 | ||
834 | radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); | |
835 | radeon_ring_write(ring, SH_MEM_APE1_LIMIT >> 2); | |
836 | radeon_ring_write(ring, 0); | |
837 | ||
838 | radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); | |
839 | radeon_ring_write(ring, SRBM_GFX_CNTL >> 2); | |
840 | radeon_ring_write(ring, VMID(0)); | |
841 | ||
842 | /* flush HDP */ | |
ca113f6b | 843 | cik_sdma_hdp_flush_ring_emit(rdev, ridx); |
2483b4ea CK |
844 | |
845 | /* flush TLB */ | |
846 | radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); | |
847 | radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2); | |
848 | radeon_ring_write(ring, 1 << vm->id); | |
849 | } | |
850 |