projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 8cc1a532 AD |
1 | /* |
| 2 | * Copyright 2012 Advanced Micro Devices, Inc. | |
| 3 | * | |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
| 5 | * copy of this software and associated documentation files (the "Software"), | |
| 6 | * to deal in the Software without restriction, including without limitation | |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the | |
| 9 | * Software is furnished to do so, subject to the following conditions: | |
| 10 | * | |
| 11 | * The above copyright notice and this permission notice shall be included in | |
| 12 | * all copies or substantial portions of the Software. | |
| 13 | * | |
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 20 | * OTHER DEALINGS IN THE SOFTWARE. | |
| 21 | * | |
| 22 | * Authors: Alex Deucher | |
| 23 | */ | |
| 24 | #ifndef CIK_H | |
| 25 | #define CIK_H | |
| 26 | ||
| 27 | #define BONAIRE_GB_ADDR_CONFIG_GOLDEN 0x12010001 | |
| 28 | ||
| 29 | #define CIK_RB_BITMAP_WIDTH_PER_SH 2 | |
| 30 | ||
| 2c67912c AD |
31 | /* SMC IND registers */ |
| 32 | #define GENERAL_PWRMGT 0xC0200000 | |
| 33 | # define GPU_COUNTER_CLK (1 << 15) | |
| 34 | ||
| 35 | #define CG_CLKPIN_CNTL 0xC05001A0 | |
| 36 | # define XTALIN_DIVIDE (1 << 1) | |
| 37 | ||
| 6e2c3c0a AD |
38 | #define PCIE_INDEX 0x38 |
| 39 | #define PCIE_DATA 0x3C | |
| 40 | ||
| 1c49165d AD |
41 | #define VGA_HDP_CONTROL 0x328 |
| 42 | #define VGA_MEMORY_DISABLE (1 << 4) | |
| 43 | ||
| 8cc1a532 AD |
44 | #define DMIF_ADDR_CALC 0xC00 |
| 45 | ||
| 1c49165d AD |
46 | #define SRBM_GFX_CNTL 0xE44 |
| 47 | #define PIPEID(x) ((x) << 0) | |
| 48 | #define MEID(x) ((x) << 2) | |
| 49 | #define VMID(x) ((x) << 4) | |
| 50 | #define QUEUEID(x) ((x) << 8) | |
| 51 | ||
| 6f2043ce | 52 | #define SRBM_STATUS2 0xE4C |
| cc066715 AD |
53 | #define SDMA_BUSY (1 << 5) |
| 54 | #define SDMA1_BUSY (1 << 6) | |
| 6f2043ce | 55 | #define SRBM_STATUS 0xE50 |
| cc066715 AD |
56 | #define UVD_RQ_PENDING (1 << 1) |
| 57 | #define GRBM_RQ_PENDING (1 << 5) | |
| 58 | #define VMC_BUSY (1 << 8) | |
| 59 | #define MCB_BUSY (1 << 9) | |
| 60 | #define MCB_NON_DISPLAY_BUSY (1 << 10) | |
| 61 | #define MCC_BUSY (1 << 11) | |
| 62 | #define MCD_BUSY (1 << 12) | |
| 63 | #define SEM_BUSY (1 << 14) | |
| 64 | #define IH_BUSY (1 << 17) | |
| 65 | #define UVD_BUSY (1 << 19) | |
| 6f2043ce | 66 | |
| 21a93e13 AD |
67 | #define SRBM_SOFT_RESET 0xE60 |
| 68 | #define SOFT_RESET_BIF (1 << 1) | |
| 69 | #define SOFT_RESET_R0PLL (1 << 4) | |
| 70 | #define SOFT_RESET_DC (1 << 5) | |
| 71 | #define SOFT_RESET_SDMA1 (1 << 6) | |
| 72 | #define SOFT_RESET_GRBM (1 << 8) | |
| 73 | #define SOFT_RESET_HDP (1 << 9) | |
| 74 | #define SOFT_RESET_IH (1 << 10) | |
| 75 | #define SOFT_RESET_MC (1 << 11) | |
| 76 | #define SOFT_RESET_ROM (1 << 14) | |
| 77 | #define SOFT_RESET_SEM (1 << 15) | |
| 78 | #define SOFT_RESET_VMC (1 << 17) | |
| 79 | #define SOFT_RESET_SDMA (1 << 20) | |
| 80 | #define SOFT_RESET_TST (1 << 21) | |
| 81 | #define SOFT_RESET_REGBB (1 << 22) | |
| 82 | #define SOFT_RESET_ORB (1 << 23) | |
| 83 | #define SOFT_RESET_VCE (1 << 24) | |
| 84 | ||
| 1c49165d AD |
85 | #define VM_L2_CNTL 0x1400 |
| 86 | #define ENABLE_L2_CACHE (1 << 0) | |
| 87 | #define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1) | |
| 88 | #define L2_CACHE_PTE_ENDIAN_SWAP_MODE(x) ((x) << 2) | |
| 89 | #define L2_CACHE_PDE_ENDIAN_SWAP_MODE(x) ((x) << 4) | |
| 90 | #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) | |
| 91 | #define ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE (1 << 10) | |
| 92 | #define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 15) | |
| 93 | #define CONTEXT1_IDENTITY_ACCESS_MODE(x) (((x) & 3) << 19) | |
| 94 | #define VM_L2_CNTL2 0x1404 | |
| 95 | #define INVALIDATE_ALL_L1_TLBS (1 << 0) | |
| 96 | #define INVALIDATE_L2_CACHE (1 << 1) | |
| 97 | #define INVALIDATE_CACHE_MODE(x) ((x) << 26) | |
| 98 | #define INVALIDATE_PTE_AND_PDE_CACHES 0 | |
| 99 | #define INVALIDATE_ONLY_PTE_CACHES 1 | |
| 100 | #define INVALIDATE_ONLY_PDE_CACHES 2 | |
| 101 | #define VM_L2_CNTL3 0x1408 | |
| 102 | #define BANK_SELECT(x) ((x) << 0) | |
| 103 | #define L2_CACHE_UPDATE_MODE(x) ((x) << 6) | |
| 104 | #define L2_CACHE_BIGK_FRAGMENT_SIZE(x) ((x) << 15) | |
| 105 | #define L2_CACHE_BIGK_ASSOCIATIVITY (1 << 20) | |
| 106 | #define VM_L2_STATUS 0x140C | |
| 107 | #define L2_BUSY (1 << 0) | |
| 108 | #define VM_CONTEXT0_CNTL 0x1410 | |
| 109 | #define ENABLE_CONTEXT (1 << 0) | |
| 110 | #define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1) | |
| a00024b0 | 111 | #define RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 3) |
| 1c49165d | 112 | #define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4) |
| a00024b0 AD |
113 | #define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 6) |
| 114 | #define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 7) | |
| 115 | #define PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 9) | |
| 116 | #define PDE0_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 10) | |
| 117 | #define VALID_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 12) | |
| 118 | #define VALID_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 13) | |
| 119 | #define READ_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 15) | |
| 120 | #define READ_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 16) | |
| 121 | #define WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 18) | |
| 122 | #define WRITE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 19) | |
| 1c49165d AD |
123 | #define VM_CONTEXT1_CNTL 0x1414 |
| 124 | #define VM_CONTEXT0_CNTL2 0x1430 | |
| 125 | #define VM_CONTEXT1_CNTL2 0x1434 | |
| 126 | #define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR 0x1438 | |
| 127 | #define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR 0x143c | |
| 128 | #define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR 0x1440 | |
| 129 | #define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR 0x1444 | |
| 130 | #define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR 0x1448 | |
| 131 | #define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR 0x144c | |
| 132 | #define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR 0x1450 | |
| 133 | #define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR 0x1454 | |
| 134 | ||
| 135 | #define VM_INVALIDATE_REQUEST 0x1478 | |
| 136 | #define VM_INVALIDATE_RESPONSE 0x147c | |
| 137 | ||
| 9d97c99b AD |
138 | #define VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x14DC |
| 139 | ||
| 140 | #define VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x14FC | |
| 141 | ||
| 1c49165d AD |
142 | #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518 |
| 143 | #define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR 0x151c | |
| 144 | ||
| 145 | #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153c | |
| 146 | #define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR 0x1540 | |
| 147 | #define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR 0x1544 | |
| 148 | #define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR 0x1548 | |
| 149 | #define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR 0x154c | |
| 150 | #define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR 0x1550 | |
| 151 | #define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR 0x1554 | |
| 152 | #define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR 0x1558 | |
| 153 | #define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155c | |
| 154 | #define VM_CONTEXT1_PAGE_TABLE_START_ADDR 0x1560 | |
| 155 | ||
| 156 | #define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C | |
| 157 | #define VM_CONTEXT1_PAGE_TABLE_END_ADDR 0x1580 | |
| 158 | ||
| 8cc1a532 AD |
159 | #define MC_SHARED_CHMAP 0x2004 |
| 160 | #define NOOFCHAN_SHIFT 12 | |
| 161 | #define NOOFCHAN_MASK 0x0000f000 | |
| 162 | #define MC_SHARED_CHREMAP 0x2008 | |
| 163 | ||
| 1c49165d AD |
164 | #define CHUB_CONTROL 0x1864 |
| 165 | #define BYPASS_VM (1 << 0) | |
| 166 | ||
| 167 | #define MC_VM_FB_LOCATION 0x2024 | |
| 168 | #define MC_VM_AGP_TOP 0x2028 | |
| 169 | #define MC_VM_AGP_BOT 0x202C | |
| 170 | #define MC_VM_AGP_BASE 0x2030 | |
| 171 | #define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034 | |
| 172 | #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038 | |
| 173 | #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C | |
| 174 | ||
| 175 | #define MC_VM_MX_L1_TLB_CNTL 0x2064 | |
| 176 | #define ENABLE_L1_TLB (1 << 0) | |
| 177 | #define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) | |
| 178 | #define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3) | |
| 179 | #define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3) | |
| 180 | #define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3) | |
| 181 | #define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3) | |
| 182 | #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5) | |
| 183 | #define ENABLE_ADVANCED_DRIVER_MODEL (1 << 6) | |
| 184 | #define MC_VM_FB_OFFSET 0x2068 | |
| 185 | ||
| bc8273fe AD |
186 | #define MC_SHARED_BLACKOUT_CNTL 0x20ac |
| 187 | ||
| 8cc1a532 AD |
188 | #define MC_ARB_RAMCFG 0x2760 |
| 189 | #define NOOFBANK_SHIFT 0 | |
| 190 | #define NOOFBANK_MASK 0x00000003 | |
| 191 | #define NOOFRANK_SHIFT 2 | |
| 192 | #define NOOFRANK_MASK 0x00000004 | |
| 193 | #define NOOFROWS_SHIFT 3 | |
| 194 | #define NOOFROWS_MASK 0x00000038 | |
| 195 | #define NOOFCOLS_SHIFT 6 | |
| 196 | #define NOOFCOLS_MASK 0x000000C0 | |
| 197 | #define CHANSIZE_SHIFT 8 | |
| 198 | #define CHANSIZE_MASK 0x00000100 | |
| 199 | #define NOOFGROUPS_SHIFT 12 | |
| 200 | #define NOOFGROUPS_MASK 0x00001000 | |
| 201 | ||
| bc8273fe AD |
202 | #define MC_SEQ_SUP_CNTL 0x28c8 |
| 203 | #define RUN_MASK (1 << 0) | |
| 204 | #define MC_SEQ_SUP_PGM 0x28cc | |
| 205 | ||
| 206 | #define MC_SEQ_TRAIN_WAKEUP_CNTL 0x28e8 | |
| 207 | #define TRAIN_DONE_D0 (1 << 30) | |
| 208 | #define TRAIN_DONE_D1 (1 << 31) | |
| 209 | ||
| 210 | #define MC_IO_PAD_CNTL_D0 0x29d0 | |
| 211 | #define MEM_FALL_OUT_CMD (1 << 8) | |
| 212 | ||
| 213 | #define MC_SEQ_IO_DEBUG_INDEX 0x2a44 | |
| 214 | #define MC_SEQ_IO_DEBUG_DATA 0x2a48 | |
| 215 | ||
| 8cc1a532 AD |
216 | #define HDP_HOST_PATH_CNTL 0x2C00 |
| 217 | #define HDP_NONSURFACE_BASE 0x2C04 | |
| 218 | #define HDP_NONSURFACE_INFO 0x2C08 | |
| 219 | #define HDP_NONSURFACE_SIZE 0x2C0C | |
| 220 | ||
| 221 | #define HDP_ADDR_CONFIG 0x2F48 | |
| 222 | #define HDP_MISC_CNTL 0x2F4C | |
| 223 | #define HDP_FLUSH_INVALIDATE_CACHE (1 << 0) | |
| 224 | ||
| a59781bb AD |
225 | #define IH_RB_CNTL 0x3e00 |
| 226 | # define IH_RB_ENABLE (1 << 0) | |
| 227 | # define IH_RB_SIZE(x) ((x) << 1) /* log2 */ | |
| 228 | # define IH_RB_FULL_DRAIN_ENABLE (1 << 6) | |
| 229 | # define IH_WPTR_WRITEBACK_ENABLE (1 << 8) | |
| 230 | # define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */ | |
| 231 | # define IH_WPTR_OVERFLOW_ENABLE (1 << 16) | |
| 232 | # define IH_WPTR_OVERFLOW_CLEAR (1 << 31) | |
| 233 | #define IH_RB_BASE 0x3e04 | |
| 234 | #define IH_RB_RPTR 0x3e08 | |
| 235 | #define IH_RB_WPTR 0x3e0c | |
| 236 | # define RB_OVERFLOW (1 << 0) | |
| 237 | # define WPTR_OFFSET_MASK 0x3fffc | |
| 238 | #define IH_RB_WPTR_ADDR_HI 0x3e10 | |
| 239 | #define IH_RB_WPTR_ADDR_LO 0x3e14 | |
| 240 | #define IH_CNTL 0x3e18 | |
| 241 | # define ENABLE_INTR (1 << 0) | |
| 242 | # define IH_MC_SWAP(x) ((x) << 1) | |
| 243 | # define IH_MC_SWAP_NONE 0 | |
| 244 | # define IH_MC_SWAP_16BIT 1 | |
| 245 | # define IH_MC_SWAP_32BIT 2 | |
| 246 | # define IH_MC_SWAP_64BIT 3 | |
| 247 | # define RPTR_REARM (1 << 4) | |
| 248 | # define MC_WRREQ_CREDIT(x) ((x) << 15) | |
| 249 | # define MC_WR_CLEAN_CNT(x) ((x) << 20) | |
| 250 | # define MC_VMID(x) ((x) << 25) | |
| 251 | ||
| 1c49165d AD |
252 | #define CONFIG_MEMSIZE 0x5428 |
| 253 | ||
| a59781bb AD |
254 | #define INTERRUPT_CNTL 0x5468 |
| 255 | # define IH_DUMMY_RD_OVERRIDE (1 << 0) | |
| 256 | # define IH_DUMMY_RD_EN (1 << 1) | |
| 257 | # define IH_REQ_NONSNOOP_EN (1 << 3) | |
| 258 | # define GEN_IH_INT_EN (1 << 8) | |
| 259 | #define INTERRUPT_CNTL2 0x546c | |
| 260 | ||
| 1c49165d AD |
261 | #define HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480 |
| 262 | ||
| 8cc1a532 AD |
263 | #define BIF_FB_EN 0x5490 |
| 264 | #define FB_READ_EN (1 << 0) | |
| 265 | #define FB_WRITE_EN (1 << 1) | |
| 266 | ||
| 1c49165d AD |
267 | #define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 |
| 268 | ||
| 2cae3bc3 AD |
269 | #define GPU_HDP_FLUSH_REQ 0x54DC |
| 270 | #define GPU_HDP_FLUSH_DONE 0x54E0 | |
| 271 | #define CP0 (1 << 0) | |
| 272 | #define CP1 (1 << 1) | |
| 273 | #define CP2 (1 << 2) | |
| 274 | #define CP3 (1 << 3) | |
| 275 | #define CP4 (1 << 4) | |
| 276 | #define CP5 (1 << 5) | |
| 277 | #define CP6 (1 << 6) | |
| 278 | #define CP7 (1 << 7) | |
| 279 | #define CP8 (1 << 8) | |
| 280 | #define CP9 (1 << 9) | |
| 281 | #define SDMA0 (1 << 10) | |
| 282 | #define SDMA1 (1 << 11) | |
| 283 | ||
| cd84a27d AD |
284 | /* 0x6b04, 0x7704, 0x10304, 0x10f04, 0x11b04, 0x12704 */ |
| 285 | #define LB_MEMORY_CTRL 0x6b04 | |
| 286 | #define LB_MEMORY_SIZE(x) ((x) << 0) | |
| 287 | #define LB_MEMORY_CONFIG(x) ((x) << 20) | |
| 288 | ||
| 289 | #define DPG_WATERMARK_MASK_CONTROL 0x6cc8 | |
| 290 | # define LATENCY_WATERMARK_MASK(x) ((x) << 8) | |
| 291 | #define DPG_PIPE_LATENCY_CONTROL 0x6ccc | |
| 292 | # define LATENCY_LOW_WATERMARK(x) ((x) << 0) | |
| 293 | # define LATENCY_HIGH_WATERMARK(x) ((x) << 16) | |
| 294 | ||
| a59781bb AD |
295 | /* 0x6b24, 0x7724, 0x10324, 0x10f24, 0x11b24, 0x12724 */ |
| 296 | #define LB_VLINE_STATUS 0x6b24 | |
| 297 | # define VLINE_OCCURRED (1 << 0) | |
| 298 | # define VLINE_ACK (1 << 4) | |
| 299 | # define VLINE_STAT (1 << 12) | |
| 300 | # define VLINE_INTERRUPT (1 << 16) | |
| 301 | # define VLINE_INTERRUPT_TYPE (1 << 17) | |
| 302 | /* 0x6b2c, 0x772c, 0x1032c, 0x10f2c, 0x11b2c, 0x1272c */ | |
| 303 | #define LB_VBLANK_STATUS 0x6b2c | |
| 304 | # define VBLANK_OCCURRED (1 << 0) | |
| 305 | # define VBLANK_ACK (1 << 4) | |
| 306 | # define VBLANK_STAT (1 << 12) | |
| 307 | # define VBLANK_INTERRUPT (1 << 16) | |
| 308 | # define VBLANK_INTERRUPT_TYPE (1 << 17) | |
| 309 | ||
| 310 | /* 0x6b20, 0x7720, 0x10320, 0x10f20, 0x11b20, 0x12720 */ | |
| 311 | #define LB_INTERRUPT_MASK 0x6b20 | |
| 312 | # define VBLANK_INTERRUPT_MASK (1 << 0) | |
| 313 | # define VLINE_INTERRUPT_MASK (1 << 4) | |
| 314 | # define VLINE2_INTERRUPT_MASK (1 << 8) | |
| 315 | ||
| 316 | #define DISP_INTERRUPT_STATUS 0x60f4 | |
| 317 | # define LB_D1_VLINE_INTERRUPT (1 << 2) | |
| 318 | # define LB_D1_VBLANK_INTERRUPT (1 << 3) | |
| 319 | # define DC_HPD1_INTERRUPT (1 << 17) | |
| 320 | # define DC_HPD1_RX_INTERRUPT (1 << 18) | |
| 321 | # define DACA_AUTODETECT_INTERRUPT (1 << 22) | |
| 322 | # define DACB_AUTODETECT_INTERRUPT (1 << 23) | |
| 323 | # define DC_I2C_SW_DONE_INTERRUPT (1 << 24) | |
| 324 | # define DC_I2C_HW_DONE_INTERRUPT (1 << 25) | |
| 325 | #define DISP_INTERRUPT_STATUS_CONTINUE 0x60f8 | |
| 326 | # define LB_D2_VLINE_INTERRUPT (1 << 2) | |
| 327 | # define LB_D2_VBLANK_INTERRUPT (1 << 3) | |
| 328 | # define DC_HPD2_INTERRUPT (1 << 17) | |
| 329 | # define DC_HPD2_RX_INTERRUPT (1 << 18) | |
| 330 | # define DISP_TIMER_INTERRUPT (1 << 24) | |
| 331 | #define DISP_INTERRUPT_STATUS_CONTINUE2 0x60fc | |
| 332 | # define LB_D3_VLINE_INTERRUPT (1 << 2) | |
| 333 | # define LB_D3_VBLANK_INTERRUPT (1 << 3) | |
| 334 | # define DC_HPD3_INTERRUPT (1 << 17) | |
| 335 | # define DC_HPD3_RX_INTERRUPT (1 << 18) | |
| 336 | #define DISP_INTERRUPT_STATUS_CONTINUE3 0x6100 | |
| 337 | # define LB_D4_VLINE_INTERRUPT (1 << 2) | |
| 338 | # define LB_D4_VBLANK_INTERRUPT (1 << 3) | |
| 339 | # define DC_HPD4_INTERRUPT (1 << 17) | |
| 340 | # define DC_HPD4_RX_INTERRUPT (1 << 18) | |
| 341 | #define DISP_INTERRUPT_STATUS_CONTINUE4 0x614c | |
| 342 | # define LB_D5_VLINE_INTERRUPT (1 << 2) | |
| 343 | # define LB_D5_VBLANK_INTERRUPT (1 << 3) | |
| 344 | # define DC_HPD5_INTERRUPT (1 << 17) | |
| 345 | # define DC_HPD5_RX_INTERRUPT (1 << 18) | |
| 346 | #define DISP_INTERRUPT_STATUS_CONTINUE5 0x6150 | |
| 347 | # define LB_D6_VLINE_INTERRUPT (1 << 2) | |
| 348 | # define LB_D6_VBLANK_INTERRUPT (1 << 3) | |
| 349 | # define DC_HPD6_INTERRUPT (1 << 17) | |
| 350 | # define DC_HPD6_RX_INTERRUPT (1 << 18) | |
| 351 | #define DISP_INTERRUPT_STATUS_CONTINUE6 0x6780 | |
| 352 | ||
| 353 | #define DAC_AUTODETECT_INT_CONTROL 0x67c8 | |
| 354 | ||
| 355 | #define DC_HPD1_INT_STATUS 0x601c | |
| 356 | #define DC_HPD2_INT_STATUS 0x6028 | |
| 357 | #define DC_HPD3_INT_STATUS 0x6034 | |
| 358 | #define DC_HPD4_INT_STATUS 0x6040 | |
| 359 | #define DC_HPD5_INT_STATUS 0x604c | |
| 360 | #define DC_HPD6_INT_STATUS 0x6058 | |
| 361 | # define DC_HPDx_INT_STATUS (1 << 0) | |
| 362 | # define DC_HPDx_SENSE (1 << 1) | |
| 363 | # define DC_HPDx_SENSE_DELAYED (1 << 4) | |
| 364 | # define DC_HPDx_RX_INT_STATUS (1 << 8) | |
| 365 | ||
| 366 | #define DC_HPD1_INT_CONTROL 0x6020 | |
| 367 | #define DC_HPD2_INT_CONTROL 0x602c | |
| 368 | #define DC_HPD3_INT_CONTROL 0x6038 | |
| 369 | #define DC_HPD4_INT_CONTROL 0x6044 | |
| 370 | #define DC_HPD5_INT_CONTROL 0x6050 | |
| 371 | #define DC_HPD6_INT_CONTROL 0x605c | |
| 372 | # define DC_HPDx_INT_ACK (1 << 0) | |
| 373 | # define DC_HPDx_INT_POLARITY (1 << 8) | |
| 374 | # define DC_HPDx_INT_EN (1 << 16) | |
| 375 | # define DC_HPDx_RX_INT_ACK (1 << 20) | |
| 376 | # define DC_HPDx_RX_INT_EN (1 << 24) | |
| 377 | ||
| 378 | #define DC_HPD1_CONTROL 0x6024 | |
| 379 | #define DC_HPD2_CONTROL 0x6030 | |
| 380 | #define DC_HPD3_CONTROL 0x603c | |
| 381 | #define DC_HPD4_CONTROL 0x6048 | |
| 382 | #define DC_HPD5_CONTROL 0x6054 | |
| 383 | #define DC_HPD6_CONTROL 0x6060 | |
| 384 | # define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0) | |
| 385 | # define DC_HPDx_RX_INT_TIMER(x) ((x) << 16) | |
| 386 | # define DC_HPDx_EN (1 << 28) | |
| 387 | ||
| 8cc1a532 AD |
388 | #define GRBM_CNTL 0x8000 |
| 389 | #define GRBM_READ_TIMEOUT(x) ((x) << 0) | |
| 390 | ||
| 6f2043ce AD |
391 | #define GRBM_STATUS2 0x8008 |
| 392 | #define ME0PIPE1_CMDFIFO_AVAIL_MASK 0x0000000F | |
| 393 | #define ME0PIPE1_CF_RQ_PENDING (1 << 4) | |
| 394 | #define ME0PIPE1_PF_RQ_PENDING (1 << 5) | |
| 395 | #define ME1PIPE0_RQ_PENDING (1 << 6) | |
| 396 | #define ME1PIPE1_RQ_PENDING (1 << 7) | |
| 397 | #define ME1PIPE2_RQ_PENDING (1 << 8) | |
| 398 | #define ME1PIPE3_RQ_PENDING (1 << 9) | |
| 399 | #define ME2PIPE0_RQ_PENDING (1 << 10) | |
| 400 | #define ME2PIPE1_RQ_PENDING (1 << 11) | |
| 401 | #define ME2PIPE2_RQ_PENDING (1 << 12) | |
| 402 | #define ME2PIPE3_RQ_PENDING (1 << 13) | |
| 403 | #define RLC_RQ_PENDING (1 << 14) | |
| 404 | #define RLC_BUSY (1 << 24) | |
| 405 | #define TC_BUSY (1 << 25) | |
| 406 | #define CPF_BUSY (1 << 28) | |
| 407 | #define CPC_BUSY (1 << 29) | |
| 408 | #define CPG_BUSY (1 << 30) | |
| 409 | ||
| 410 | #define GRBM_STATUS 0x8010 | |
| 411 | #define ME0PIPE0_CMDFIFO_AVAIL_MASK 0x0000000F | |
| 412 | #define SRBM_RQ_PENDING (1 << 5) | |
| 413 | #define ME0PIPE0_CF_RQ_PENDING (1 << 7) | |
| 414 | #define ME0PIPE0_PF_RQ_PENDING (1 << 8) | |
| 415 | #define GDS_DMA_RQ_PENDING (1 << 9) | |
| 416 | #define DB_CLEAN (1 << 12) | |
| 417 | #define CB_CLEAN (1 << 13) | |
| 418 | #define TA_BUSY (1 << 14) | |
| 419 | #define GDS_BUSY (1 << 15) | |
| 420 | #define WD_BUSY_NO_DMA (1 << 16) | |
| 421 | #define VGT_BUSY (1 << 17) | |
| 422 | #define IA_BUSY_NO_DMA (1 << 18) | |
| 423 | #define IA_BUSY (1 << 19) | |
| 424 | #define SX_BUSY (1 << 20) | |
| 425 | #define WD_BUSY (1 << 21) | |
| 426 | #define SPI_BUSY (1 << 22) | |
| 427 | #define BCI_BUSY (1 << 23) | |
| 428 | #define SC_BUSY (1 << 24) | |
| 429 | #define PA_BUSY (1 << 25) | |
| 430 | #define DB_BUSY (1 << 26) | |
| 431 | #define CP_COHERENCY_BUSY (1 << 28) | |
| 432 | #define CP_BUSY (1 << 29) | |
| 433 | #define CB_BUSY (1 << 30) | |
| 434 | #define GUI_ACTIVE (1 << 31) | |
| 435 | #define GRBM_STATUS_SE0 0x8014 | |
| 436 | #define GRBM_STATUS_SE1 0x8018 | |
| 437 | #define GRBM_STATUS_SE2 0x8038 | |
| 438 | #define GRBM_STATUS_SE3 0x803C | |
| 439 | #define SE_DB_CLEAN (1 << 1) | |
| 440 | #define SE_CB_CLEAN (1 << 2) | |
| 441 | #define SE_BCI_BUSY (1 << 22) | |
| 442 | #define SE_VGT_BUSY (1 << 23) | |
| 443 | #define SE_PA_BUSY (1 << 24) | |
| 444 | #define SE_TA_BUSY (1 << 25) | |
| 445 | #define SE_SX_BUSY (1 << 26) | |
| 446 | #define SE_SPI_BUSY (1 << 27) | |
| 447 | #define SE_SC_BUSY (1 << 29) | |
| 448 | #define SE_DB_BUSY (1 << 30) | |
| 449 | #define SE_CB_BUSY (1 << 31) | |
| 450 | ||
| 451 | #define GRBM_SOFT_RESET 0x8020 | |
| 452 | #define SOFT_RESET_CP (1 << 0) /* All CP blocks */ | |
| 453 | #define SOFT_RESET_RLC (1 << 2) /* RLC */ | |
| 454 | #define SOFT_RESET_GFX (1 << 16) /* GFX */ | |
| 455 | #define SOFT_RESET_CPF (1 << 17) /* CP fetcher shared by gfx and compute */ | |
| 456 | #define SOFT_RESET_CPC (1 << 18) /* CP Compute (MEC1/2) */ | |
| 457 | #define SOFT_RESET_CPG (1 << 19) /* CP GFX (PFP, ME, CE) */ | |
| 458 | ||
| a59781bb AD |
459 | #define GRBM_INT_CNTL 0x8060 |
| 460 | # define RDERR_INT_ENABLE (1 << 0) | |
| 461 | # define GUI_IDLE_INT_ENABLE (1 << 19) | |
| 462 | ||
| 963e81f9 AD |
463 | #define CP_CPC_STATUS 0x8210 |
| 464 | #define CP_CPC_BUSY_STAT 0x8214 | |
| 465 | #define CP_CPC_STALLED_STAT1 0x8218 | |
| 466 | #define CP_CPF_STATUS 0x821c | |
| 467 | #define CP_CPF_BUSY_STAT 0x8220 | |
| 468 | #define CP_CPF_STALLED_STAT1 0x8224 | |
| 469 | ||
| 6f2043ce AD |
470 | #define CP_MEC_CNTL 0x8234 |
| 471 | #define MEC_ME2_HALT (1 << 28) | |
| 472 | #define MEC_ME1_HALT (1 << 30) | |
| 473 | ||
| 841cf442 AD |
474 | #define CP_MEC_CNTL 0x8234 |
| 475 | #define MEC_ME2_HALT (1 << 28) | |
| 476 | #define MEC_ME1_HALT (1 << 30) | |
| 477 | ||
| 963e81f9 AD |
478 | #define CP_STALLED_STAT3 0x8670 |
| 479 | #define CP_STALLED_STAT1 0x8674 | |
| 480 | #define CP_STALLED_STAT2 0x8678 | |
| 481 | ||
| 482 | #define CP_STAT 0x8680 | |
| 483 | ||
| 6f2043ce AD |
484 | #define CP_ME_CNTL 0x86D8 |
| 485 | #define CP_CE_HALT (1 << 24) | |
| 486 | #define CP_PFP_HALT (1 << 26) | |
| 487 | #define CP_ME_HALT (1 << 28) | |
| 488 | ||
| 841cf442 AD |
489 | #define CP_RB0_RPTR 0x8700 |
| 490 | #define CP_RB_WPTR_DELAY 0x8704 | |
| 491 | ||
| 8cc1a532 AD |
492 | #define CP_MEQ_THRESHOLDS 0x8764 |
| 493 | #define MEQ1_START(x) ((x) << 0) | |
| 494 | #define MEQ2_START(x) ((x) << 8) | |
| 495 | ||
| 496 | #define VGT_VTX_VECT_EJECT_REG 0x88B0 | |
| 497 | ||
| 498 | #define VGT_CACHE_INVALIDATION 0x88C4 | |
| 499 | #define CACHE_INVALIDATION(x) ((x) << 0) | |
| 500 | #define VC_ONLY 0 | |
| 501 | #define TC_ONLY 1 | |
| 502 | #define VC_AND_TC 2 | |
| 503 | #define AUTO_INVLD_EN(x) ((x) << 6) | |
| 504 | #define NO_AUTO 0 | |
| 505 | #define ES_AUTO 1 | |
| 506 | #define GS_AUTO 2 | |
| 507 | #define ES_AND_GS_AUTO 3 | |
| 508 | ||
| 509 | #define VGT_GS_VERTEX_REUSE 0x88D4 | |
| 510 | ||
| 511 | #define CC_GC_SHADER_ARRAY_CONFIG 0x89bc | |
| 512 | #define INACTIVE_CUS_MASK 0xFFFF0000 | |
| 513 | #define INACTIVE_CUS_SHIFT 16 | |
| 514 | #define GC_USER_SHADER_ARRAY_CONFIG 0x89c0 | |
| 515 | ||
| 516 | #define PA_CL_ENHANCE 0x8A14 | |
| 517 | #define CLIP_VTX_REORDER_ENA (1 << 0) | |
| 518 | #define NUM_CLIP_SEQ(x) ((x) << 1) | |
| 519 | ||
| 520 | #define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24 | |
| 521 | #define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0) | |
| 522 | #define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16) | |
| 523 | ||
| 524 | #define PA_SC_FIFO_SIZE 0x8BCC | |
| 525 | #define SC_FRONTEND_PRIM_FIFO_SIZE(x) ((x) << 0) | |
| 526 | #define SC_BACKEND_PRIM_FIFO_SIZE(x) ((x) << 6) | |
| 527 | #define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 15) | |
| 528 | #define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 23) | |
| 529 | ||
| 530 | #define PA_SC_ENHANCE 0x8BF0 | |
| 531 | #define ENABLE_PA_SC_OUT_OF_ORDER (1 << 0) | |
| 532 | #define DISABLE_PA_SC_GUIDANCE (1 << 13) | |
| 533 | ||
| 534 | #define SQ_CONFIG 0x8C00 | |
| 535 | ||
| 1c49165d AD |
536 | #define SH_MEM_BASES 0x8C28 |
| 537 | /* if PTR32, these are the bases for scratch and lds */ | |
| 538 | #define PRIVATE_BASE(x) ((x) << 0) /* scratch */ | |
| 539 | #define SHARED_BASE(x) ((x) << 16) /* LDS */ | |
| 540 | #define SH_MEM_APE1_BASE 0x8C2C | |
| 541 | /* if PTR32, this is the base location of GPUVM */ | |
| 542 | #define SH_MEM_APE1_LIMIT 0x8C30 | |
| 543 | /* if PTR32, this is the upper limit of GPUVM */ | |
| 544 | #define SH_MEM_CONFIG 0x8C34 | |
| 545 | #define PTR32 (1 << 0) | |
| 546 | #define ALIGNMENT_MODE(x) ((x) << 2) | |
| 547 | #define SH_MEM_ALIGNMENT_MODE_DWORD 0 | |
| 548 | #define SH_MEM_ALIGNMENT_MODE_DWORD_STRICT 1 | |
| 549 | #define SH_MEM_ALIGNMENT_MODE_STRICT 2 | |
| 550 | #define SH_MEM_ALIGNMENT_MODE_UNALIGNED 3 | |
| 551 | #define DEFAULT_MTYPE(x) ((x) << 4) | |
| 552 | #define APE1_MTYPE(x) ((x) << 7) | |
| 553 | ||
| 8cc1a532 AD |
554 | #define SX_DEBUG_1 0x9060 |
| 555 | ||
| 556 | #define SPI_CONFIG_CNTL 0x9100 | |
| 557 | ||
| 558 | #define SPI_CONFIG_CNTL_1 0x913C | |
| 559 | #define VTX_DONE_DELAY(x) ((x) << 0) | |
| 560 | #define INTERP_ONE_PRIM_PER_ROW (1 << 4) | |
| 561 | ||
| 562 | #define TA_CNTL_AUX 0x9508 | |
| 563 | ||
| 564 | #define DB_DEBUG 0x9830 | |
| 565 | #define DB_DEBUG2 0x9834 | |
| 566 | #define DB_DEBUG3 0x9838 | |
| 567 | ||
| 568 | #define CC_RB_BACKEND_DISABLE 0x98F4 | |
| 569 | #define BACKEND_DISABLE(x) ((x) << 16) | |
| 570 | #define GB_ADDR_CONFIG 0x98F8 | |
| 571 | #define NUM_PIPES(x) ((x) << 0) | |
| 572 | #define NUM_PIPES_MASK 0x00000007 | |
| 573 | #define NUM_PIPES_SHIFT 0 | |
| 574 | #define PIPE_INTERLEAVE_SIZE(x) ((x) << 4) | |
| 575 | #define PIPE_INTERLEAVE_SIZE_MASK 0x00000070 | |
| 576 | #define PIPE_INTERLEAVE_SIZE_SHIFT 4 | |
| 577 | #define NUM_SHADER_ENGINES(x) ((x) << 12) | |
| 578 | #define NUM_SHADER_ENGINES_MASK 0x00003000 | |
| 579 | #define NUM_SHADER_ENGINES_SHIFT 12 | |
| 580 | #define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16) | |
| 581 | #define SHADER_ENGINE_TILE_SIZE_MASK 0x00070000 | |
| 582 | #define SHADER_ENGINE_TILE_SIZE_SHIFT 16 | |
| 583 | #define ROW_SIZE(x) ((x) << 28) | |
| 584 | #define ROW_SIZE_MASK 0x30000000 | |
| 585 | #define ROW_SIZE_SHIFT 28 | |
| 586 | ||
| 587 | #define GB_TILE_MODE0 0x9910 | |
| 588 | # define ARRAY_MODE(x) ((x) << 2) | |
| 589 | # define ARRAY_LINEAR_GENERAL 0 | |
| 590 | # define ARRAY_LINEAR_ALIGNED 1 | |
| 591 | # define ARRAY_1D_TILED_THIN1 2 | |
| 592 | # define ARRAY_2D_TILED_THIN1 4 | |
| 593 | # define ARRAY_PRT_TILED_THIN1 5 | |
| 594 | # define ARRAY_PRT_2D_TILED_THIN1 6 | |
| 595 | # define PIPE_CONFIG(x) ((x) << 6) | |
| 596 | # define ADDR_SURF_P2 0 | |
| 597 | # define ADDR_SURF_P4_8x16 4 | |
| 598 | # define ADDR_SURF_P4_16x16 5 | |
| 599 | # define ADDR_SURF_P4_16x32 6 | |
| 600 | # define ADDR_SURF_P4_32x32 7 | |
| 601 | # define ADDR_SURF_P8_16x16_8x16 8 | |
| 602 | # define ADDR_SURF_P8_16x32_8x16 9 | |
| 603 | # define ADDR_SURF_P8_32x32_8x16 10 | |
| 604 | # define ADDR_SURF_P8_16x32_16x16 11 | |
| 605 | # define ADDR_SURF_P8_32x32_16x16 12 | |
| 606 | # define ADDR_SURF_P8_32x32_16x32 13 | |
| 607 | # define ADDR_SURF_P8_32x64_32x32 14 | |
| 608 | # define TILE_SPLIT(x) ((x) << 11) | |
| 609 | # define ADDR_SURF_TILE_SPLIT_64B 0 | |
| 610 | # define ADDR_SURF_TILE_SPLIT_128B 1 | |
| 611 | # define ADDR_SURF_TILE_SPLIT_256B 2 | |
| 612 | # define ADDR_SURF_TILE_SPLIT_512B 3 | |
| 613 | # define ADDR_SURF_TILE_SPLIT_1KB 4 | |
| 614 | # define ADDR_SURF_TILE_SPLIT_2KB 5 | |
| 615 | # define ADDR_SURF_TILE_SPLIT_4KB 6 | |
| 616 | # define MICRO_TILE_MODE_NEW(x) ((x) << 22) | |
| 617 | # define ADDR_SURF_DISPLAY_MICRO_TILING 0 | |
| 618 | # define ADDR_SURF_THIN_MICRO_TILING 1 | |
| 619 | # define ADDR_SURF_DEPTH_MICRO_TILING 2 | |
| 620 | # define ADDR_SURF_ROTATED_MICRO_TILING 3 | |
| 621 | # define SAMPLE_SPLIT(x) ((x) << 25) | |
| 622 | # define ADDR_SURF_SAMPLE_SPLIT_1 0 | |
| 623 | # define ADDR_SURF_SAMPLE_SPLIT_2 1 | |
| 624 | # define ADDR_SURF_SAMPLE_SPLIT_4 2 | |
| 625 | # define ADDR_SURF_SAMPLE_SPLIT_8 3 | |
| 626 | ||
| 627 | #define GB_MACROTILE_MODE0 0x9990 | |
| 628 | # define BANK_WIDTH(x) ((x) << 0) | |
| 629 | # define ADDR_SURF_BANK_WIDTH_1 0 | |
| 630 | # define ADDR_SURF_BANK_WIDTH_2 1 | |
| 631 | # define ADDR_SURF_BANK_WIDTH_4 2 | |
| 632 | # define ADDR_SURF_BANK_WIDTH_8 3 | |
| 633 | # define BANK_HEIGHT(x) ((x) << 2) | |
| 634 | # define ADDR_SURF_BANK_HEIGHT_1 0 | |
| 635 | # define ADDR_SURF_BANK_HEIGHT_2 1 | |
| 636 | # define ADDR_SURF_BANK_HEIGHT_4 2 | |
| 637 | # define ADDR_SURF_BANK_HEIGHT_8 3 | |
| 638 | # define MACRO_TILE_ASPECT(x) ((x) << 4) | |
| 639 | # define ADDR_SURF_MACRO_ASPECT_1 0 | |
| 640 | # define ADDR_SURF_MACRO_ASPECT_2 1 | |
| 641 | # define ADDR_SURF_MACRO_ASPECT_4 2 | |
| 642 | # define ADDR_SURF_MACRO_ASPECT_8 3 | |
| 643 | # define NUM_BANKS(x) ((x) << 6) | |
| 644 | # define ADDR_SURF_2_BANK 0 | |
| 645 | # define ADDR_SURF_4_BANK 1 | |
| 646 | # define ADDR_SURF_8_BANK 2 | |
| 647 | # define ADDR_SURF_16_BANK 3 | |
| 648 | ||
| 649 | #define CB_HW_CONTROL 0x9A10 | |
| 650 | ||
| 651 | #define GC_USER_RB_BACKEND_DISABLE 0x9B7C | |
| 652 | #define BACKEND_DISABLE_MASK 0x00FF0000 | |
| 653 | #define BACKEND_DISABLE_SHIFT 16 | |
| 654 | ||
| 655 | #define TCP_CHAN_STEER_LO 0xac0c | |
| 656 | #define TCP_CHAN_STEER_HI 0xac10 | |
| 657 | ||
| 1c49165d AD |
658 | #define TC_CFG_L1_LOAD_POLICY0 0xAC68 |
| 659 | #define TC_CFG_L1_LOAD_POLICY1 0xAC6C | |
| 660 | #define TC_CFG_L1_STORE_POLICY 0xAC70 | |
| 661 | #define TC_CFG_L2_LOAD_POLICY0 0xAC74 | |
| 662 | #define TC_CFG_L2_LOAD_POLICY1 0xAC78 | |
| 663 | #define TC_CFG_L2_STORE_POLICY0 0xAC7C | |
| 664 | #define TC_CFG_L2_STORE_POLICY1 0xAC80 | |
| 665 | #define TC_CFG_L2_ATOMIC_POLICY 0xAC84 | |
| 666 | #define TC_CFG_L1_VOLATILE 0xAC88 | |
| 667 | #define TC_CFG_L2_VOLATILE 0xAC8C | |
| 668 | ||
| 841cf442 AD |
669 | #define CP_RB0_BASE 0xC100 |
| 670 | #define CP_RB0_CNTL 0xC104 | |
| 671 | #define RB_BUFSZ(x) ((x) << 0) | |
| 672 | #define RB_BLKSZ(x) ((x) << 8) | |
| 673 | #define BUF_SWAP_32BIT (2 << 16) | |
| 674 | #define RB_NO_UPDATE (1 << 27) | |
| 675 | #define RB_RPTR_WR_ENA (1 << 31) | |
| 676 | ||
| 677 | #define CP_RB0_RPTR_ADDR 0xC10C | |
| 678 | #define RB_RPTR_SWAP_32BIT (2 << 0) | |
| 679 | #define CP_RB0_RPTR_ADDR_HI 0xC110 | |
| 680 | #define CP_RB0_WPTR 0xC114 | |
| 681 | ||
| 682 | #define CP_DEVICE_ID 0xC12C | |
| 683 | #define CP_ENDIAN_SWAP 0xC140 | |
| 684 | #define CP_RB_VMID 0xC144 | |
| 685 | ||
| 686 | #define CP_PFP_UCODE_ADDR 0xC150 | |
| 687 | #define CP_PFP_UCODE_DATA 0xC154 | |
| 688 | #define CP_ME_RAM_RADDR 0xC158 | |
| 689 | #define CP_ME_RAM_WADDR 0xC15C | |
| 690 | #define CP_ME_RAM_DATA 0xC160 | |
| 691 | ||
| 692 | #define CP_CE_UCODE_ADDR 0xC168 | |
| 693 | #define CP_CE_UCODE_DATA 0xC16C | |
| 694 | #define CP_MEC_ME1_UCODE_ADDR 0xC170 | |
| 695 | #define CP_MEC_ME1_UCODE_DATA 0xC174 | |
| 696 | #define CP_MEC_ME2_UCODE_ADDR 0xC178 | |
| 697 | #define CP_MEC_ME2_UCODE_DATA 0xC17C | |
| 698 | ||
| f6796cae AD |
699 | #define CP_INT_CNTL_RING0 0xC1A8 |
| 700 | # define CNTX_BUSY_INT_ENABLE (1 << 19) | |
| 701 | # define CNTX_EMPTY_INT_ENABLE (1 << 20) | |
| 702 | # define PRIV_INSTR_INT_ENABLE (1 << 22) | |
| 703 | # define PRIV_REG_INT_ENABLE (1 << 23) | |
| 704 | # define TIME_STAMP_INT_ENABLE (1 << 26) | |
| 705 | # define CP_RINGID2_INT_ENABLE (1 << 29) | |
| 706 | # define CP_RINGID1_INT_ENABLE (1 << 30) | |
| 707 | # define CP_RINGID0_INT_ENABLE (1 << 31) | |
| 708 | ||
| a59781bb AD |
709 | #define CP_INT_STATUS_RING0 0xC1B4 |
| 710 | # define PRIV_INSTR_INT_STAT (1 << 22) | |
| 711 | # define PRIV_REG_INT_STAT (1 << 23) | |
| 712 | # define TIME_STAMP_INT_STAT (1 << 26) | |
| 713 | # define CP_RINGID2_INT_STAT (1 << 29) | |
| 714 | # define CP_RINGID1_INT_STAT (1 << 30) | |
| 715 | # define CP_RINGID0_INT_STAT (1 << 31) | |
| 716 | ||
| 963e81f9 AD |
717 | #define CP_CPF_DEBUG 0xC200 |
| 718 | ||
| 719 | #define CP_PQ_WPTR_POLL_CNTL 0xC20C | |
| 720 | #define WPTR_POLL_EN (1 << 31) | |
| 721 | ||
| a59781bb AD |
722 | #define CP_ME1_PIPE0_INT_CNTL 0xC214 |
| 723 | #define CP_ME1_PIPE1_INT_CNTL 0xC218 | |
| 724 | #define CP_ME1_PIPE2_INT_CNTL 0xC21C | |
| 725 | #define CP_ME1_PIPE3_INT_CNTL 0xC220 | |
| 726 | #define CP_ME2_PIPE0_INT_CNTL 0xC224 | |
| 727 | #define CP_ME2_PIPE1_INT_CNTL 0xC228 | |
| 728 | #define CP_ME2_PIPE2_INT_CNTL 0xC22C | |
| 729 | #define CP_ME2_PIPE3_INT_CNTL 0xC230 | |
| 730 | # define DEQUEUE_REQUEST_INT_ENABLE (1 << 13) | |
| 731 | # define WRM_POLL_TIMEOUT_INT_ENABLE (1 << 17) | |
| 732 | # define PRIV_REG_INT_ENABLE (1 << 23) | |
| 733 | # define TIME_STAMP_INT_ENABLE (1 << 26) | |
| 734 | # define GENERIC2_INT_ENABLE (1 << 29) | |
| 735 | # define GENERIC1_INT_ENABLE (1 << 30) | |
| 736 | # define GENERIC0_INT_ENABLE (1 << 31) | |
| 737 | #define CP_ME1_PIPE0_INT_STATUS 0xC214 | |
| 738 | #define CP_ME1_PIPE1_INT_STATUS 0xC218 | |
| 739 | #define CP_ME1_PIPE2_INT_STATUS 0xC21C | |
| 740 | #define CP_ME1_PIPE3_INT_STATUS 0xC220 | |
| 741 | #define CP_ME2_PIPE0_INT_STATUS 0xC224 | |
| 742 | #define CP_ME2_PIPE1_INT_STATUS 0xC228 | |
| 743 | #define CP_ME2_PIPE2_INT_STATUS 0xC22C | |
| 744 | #define CP_ME2_PIPE3_INT_STATUS 0xC230 | |
| 745 | # define DEQUEUE_REQUEST_INT_STATUS (1 << 13) | |
| 746 | # define WRM_POLL_TIMEOUT_INT_STATUS (1 << 17) | |
| 747 | # define PRIV_REG_INT_STATUS (1 << 23) | |
| 748 | # define TIME_STAMP_INT_STATUS (1 << 26) | |
| 749 | # define GENERIC2_INT_STATUS (1 << 29) | |
| 750 | # define GENERIC1_INT_STATUS (1 << 30) | |
| 751 | # define GENERIC0_INT_STATUS (1 << 31) | |
| 752 | ||
| 841cf442 AD |
753 | #define CP_MAX_CONTEXT 0xC2B8 |
| 754 | ||
| 755 | #define CP_RB0_BASE_HI 0xC2C4 | |
| 756 | ||
| f6796cae AD |
757 | #define RLC_CNTL 0xC300 |
| 758 | # define RLC_ENABLE (1 << 0) | |
| 759 | ||
| 760 | #define RLC_MC_CNTL 0xC30C | |
| 761 | ||
| 762 | #define RLC_LB_CNTR_MAX 0xC348 | |
| 763 | ||
| 764 | #define RLC_LB_CNTL 0xC364 | |
| 765 | ||
| 766 | #define RLC_LB_CNTR_INIT 0xC36C | |
| 767 | ||
| 768 | #define RLC_SAVE_AND_RESTORE_BASE 0xC374 | |
| 769 | #define RLC_DRIVER_DMA_STATUS 0xC378 | |
| 770 | ||
| 771 | #define RLC_GPM_UCODE_ADDR 0xC388 | |
| 772 | #define RLC_GPM_UCODE_DATA 0xC38C | |
| 44fa346f AD |
773 | #define RLC_GPU_CLOCK_COUNT_LSB 0xC390 |
| 774 | #define RLC_GPU_CLOCK_COUNT_MSB 0xC394 | |
| 775 | #define RLC_CAPTURE_GPU_CLOCK_COUNT 0xC398 | |
| f6796cae AD |
776 | #define RLC_UCODE_CNTL 0xC39C |
| 777 | ||
| 778 | #define RLC_CGCG_CGLS_CTRL 0xC424 | |
| 779 | ||
| 780 | #define RLC_LB_INIT_CU_MASK 0xC43C | |
| 781 | ||
| 782 | #define RLC_LB_PARAMS 0xC444 | |
| 783 | ||
| 784 | #define RLC_SERDES_CU_MASTER_BUSY 0xC484 | |
| 785 | #define RLC_SERDES_NONCU_MASTER_BUSY 0xC488 | |
| 786 | # define SE_MASTER_BUSY_MASK 0x0000ffff | |
| 787 | # define GC_MASTER_BUSY (1 << 16) | |
| 788 | # define TC0_MASTER_BUSY (1 << 17) | |
| 789 | # define TC1_MASTER_BUSY (1 << 18) | |
| 790 | ||
| 791 | #define RLC_GPM_SCRATCH_ADDR 0xC4B0 | |
| 792 | #define RLC_GPM_SCRATCH_DATA 0xC4B4 | |
| 793 | ||
| 963e81f9 AD |
794 | #define CP_HPD_EOP_BASE_ADDR 0xC904 |
| 795 | #define CP_HPD_EOP_BASE_ADDR_HI 0xC908 | |
| 796 | #define CP_HPD_EOP_VMID 0xC90C | |
| 797 | #define CP_HPD_EOP_CONTROL 0xC910 | |
| 798 | #define EOP_SIZE(x) ((x) << 0) | |
| 799 | #define EOP_SIZE_MASK (0x3f << 0) | |
| 800 | #define CP_MQD_BASE_ADDR 0xC914 | |
| 801 | #define CP_MQD_BASE_ADDR_HI 0xC918 | |
| 802 | #define CP_HQD_ACTIVE 0xC91C | |
| 803 | #define CP_HQD_VMID 0xC920 | |
| 804 | ||
| 805 | #define CP_HQD_PQ_BASE 0xC934 | |
| 806 | #define CP_HQD_PQ_BASE_HI 0xC938 | |
| 807 | #define CP_HQD_PQ_RPTR 0xC93C | |
| 808 | #define CP_HQD_PQ_RPTR_REPORT_ADDR 0xC940 | |
| 809 | #define CP_HQD_PQ_RPTR_REPORT_ADDR_HI 0xC944 | |
| 810 | #define CP_HQD_PQ_WPTR_POLL_ADDR 0xC948 | |
| 811 | #define CP_HQD_PQ_WPTR_POLL_ADDR_HI 0xC94C | |
| 812 | #define CP_HQD_PQ_DOORBELL_CONTROL 0xC950 | |
| 813 | #define DOORBELL_OFFSET(x) ((x) << 2) | |
| 814 | #define DOORBELL_OFFSET_MASK (0x1fffff << 2) | |
| 815 | #define DOORBELL_SOURCE (1 << 28) | |
| 816 | #define DOORBELL_SCHD_HIT (1 << 29) | |
| 817 | #define DOORBELL_EN (1 << 30) | |
| 818 | #define DOORBELL_HIT (1 << 31) | |
| 819 | #define CP_HQD_PQ_WPTR 0xC954 | |
| 820 | #define CP_HQD_PQ_CONTROL 0xC958 | |
| 821 | #define QUEUE_SIZE(x) ((x) << 0) | |
| 822 | #define QUEUE_SIZE_MASK (0x3f << 0) | |
| 823 | #define RPTR_BLOCK_SIZE(x) ((x) << 8) | |
| 824 | #define RPTR_BLOCK_SIZE_MASK (0x3f << 8) | |
| 825 | #define PQ_VOLATILE (1 << 26) | |
| 826 | #define NO_UPDATE_RPTR (1 << 27) | |
| 827 | #define UNORD_DISPATCH (1 << 28) | |
| 828 | #define ROQ_PQ_IB_FLIP (1 << 29) | |
| 829 | #define PRIV_STATE (1 << 30) | |
| 830 | #define KMD_QUEUE (1 << 31) | |
| 831 | ||
| 832 | #define CP_HQD_DEQUEUE_REQUEST 0xC974 | |
| 833 | ||
| 834 | #define CP_MQD_CONTROL 0xC99C | |
| 835 | #define MQD_VMID(x) ((x) << 0) | |
| 836 | #define MQD_VMID_MASK (0xf << 0) | |
| 837 | ||
| 8cc1a532 AD |
838 | #define PA_SC_RASTER_CONFIG 0x28350 |
| 839 | # define RASTER_CONFIG_RB_MAP_0 0 | |
| 840 | # define RASTER_CONFIG_RB_MAP_1 1 | |
| 841 | # define RASTER_CONFIG_RB_MAP_2 2 | |
| 842 | # define RASTER_CONFIG_RB_MAP_3 3 | |
| 843 | ||
| 2cae3bc3 AD |
844 | #define VGT_EVENT_INITIATOR 0x28a90 |
| 845 | # define SAMPLE_STREAMOUTSTATS1 (1 << 0) | |
| 846 | # define SAMPLE_STREAMOUTSTATS2 (2 << 0) | |
| 847 | # define SAMPLE_STREAMOUTSTATS3 (3 << 0) | |
| 848 | # define CACHE_FLUSH_TS (4 << 0) | |
| 849 | # define CACHE_FLUSH (6 << 0) | |
| 850 | # define CS_PARTIAL_FLUSH (7 << 0) | |
| 851 | # define VGT_STREAMOUT_RESET (10 << 0) | |
| 852 | # define END_OF_PIPE_INCR_DE (11 << 0) | |
| 853 | # define END_OF_PIPE_IB_END (12 << 0) | |
| 854 | # define RST_PIX_CNT (13 << 0) | |
| 855 | # define VS_PARTIAL_FLUSH (15 << 0) | |
| 856 | # define PS_PARTIAL_FLUSH (16 << 0) | |
| 857 | # define CACHE_FLUSH_AND_INV_TS_EVENT (20 << 0) | |
| 858 | # define ZPASS_DONE (21 << 0) | |
| 859 | # define CACHE_FLUSH_AND_INV_EVENT (22 << 0) | |
| 860 | # define PERFCOUNTER_START (23 << 0) | |
| 861 | # define PERFCOUNTER_STOP (24 << 0) | |
| 862 | # define PIPELINESTAT_START (25 << 0) | |
| 863 | # define PIPELINESTAT_STOP (26 << 0) | |
| 864 | # define PERFCOUNTER_SAMPLE (27 << 0) | |
| 865 | # define SAMPLE_PIPELINESTAT (30 << 0) | |
| 866 | # define SO_VGT_STREAMOUT_FLUSH (31 << 0) | |
| 867 | # define SAMPLE_STREAMOUTSTATS (32 << 0) | |
| 868 | # define RESET_VTX_CNT (33 << 0) | |
| 869 | # define VGT_FLUSH (36 << 0) | |
| 870 | # define BOTTOM_OF_PIPE_TS (40 << 0) | |
| 871 | # define DB_CACHE_FLUSH_AND_INV (42 << 0) | |
| 872 | # define FLUSH_AND_INV_DB_DATA_TS (43 << 0) | |
| 873 | # define FLUSH_AND_INV_DB_META (44 << 0) | |
| 874 | # define FLUSH_AND_INV_CB_DATA_TS (45 << 0) | |
| 875 | # define FLUSH_AND_INV_CB_META (46 << 0) | |
| 876 | # define CS_DONE (47 << 0) | |
| 877 | # define PS_DONE (48 << 0) | |
| 878 | # define FLUSH_AND_INV_CB_PIXEL_DATA (49 << 0) | |
| 879 | # define THREAD_TRACE_START (51 << 0) | |
| 880 | # define THREAD_TRACE_STOP (52 << 0) | |
| 881 | # define THREAD_TRACE_FLUSH (54 << 0) | |
| 882 | # define THREAD_TRACE_FINISH (55 << 0) | |
| 883 | # define PIXEL_PIPE_STAT_CONTROL (56 << 0) | |
| 884 | # define PIXEL_PIPE_STAT_DUMP (57 << 0) | |
| 885 | # define PIXEL_PIPE_STAT_RESET (58 << 0) | |
| 886 | ||
| 841cf442 AD |
887 | #define SCRATCH_REG0 0x30100 |
| 888 | #define SCRATCH_REG1 0x30104 | |
| 889 | #define SCRATCH_REG2 0x30108 | |
| 890 | #define SCRATCH_REG3 0x3010C | |
| 891 | #define SCRATCH_REG4 0x30110 | |
| 892 | #define SCRATCH_REG5 0x30114 | |
| 893 | #define SCRATCH_REG6 0x30118 | |
| 894 | #define SCRATCH_REG7 0x3011C | |
| 895 | ||
| 896 | #define SCRATCH_UMSK 0x30140 | |
| 897 | #define SCRATCH_ADDR 0x30144 | |
| 898 | ||
| 899 | #define CP_SEM_WAIT_TIMER 0x301BC | |
| 900 | ||
| 901 | #define CP_SEM_INCOMPLETE_TIMER_CNTL 0x301C8 | |
| 902 | ||
| 2cae3bc3 AD |
903 | #define CP_WAIT_REG_MEM_TIMEOUT 0x301D0 |
| 904 | ||
| 8cc1a532 AD |
905 | #define GRBM_GFX_INDEX 0x30800 |
| 906 | #define INSTANCE_INDEX(x) ((x) << 0) | |
| 907 | #define SH_INDEX(x) ((x) << 8) | |
| 908 | #define SE_INDEX(x) ((x) << 16) | |
| 909 | #define SH_BROADCAST_WRITES (1 << 29) | |
| 910 | #define INSTANCE_BROADCAST_WRITES (1 << 30) | |
| 911 | #define SE_BROADCAST_WRITES (1 << 31) | |
| 912 | ||
| 913 | #define VGT_ESGS_RING_SIZE 0x30900 | |
| 914 | #define VGT_GSVS_RING_SIZE 0x30904 | |
| 915 | #define VGT_PRIMITIVE_TYPE 0x30908 | |
| 916 | #define VGT_INDEX_TYPE 0x3090C | |
| 917 | ||
| 918 | #define VGT_NUM_INDICES 0x30930 | |
| 919 | #define VGT_NUM_INSTANCES 0x30934 | |
| 920 | #define VGT_TF_RING_SIZE 0x30938 | |
| 921 | #define VGT_HS_OFFCHIP_PARAM 0x3093C | |
| 922 | #define VGT_TF_MEMORY_BASE 0x30940 | |
| 923 | ||
| 924 | #define PA_SU_LINE_STIPPLE_VALUE 0x30a00 | |
| 925 | #define PA_SC_LINE_STIPPLE_STATE 0x30a04 | |
| 926 | ||
| 927 | #define SQC_CACHES 0x30d20 | |
| 928 | ||
| 929 | #define CP_PERFMON_CNTL 0x36020 | |
| 930 | ||
| 931 | #define CGTS_TCC_DISABLE 0x3c00c | |
| 932 | #define CGTS_USER_TCC_DISABLE 0x3c010 | |
| 933 | #define TCC_DISABLE_MASK 0xFFFF0000 | |
| 934 | #define TCC_DISABLE_SHIFT 16 | |
| 935 | ||
| f6796cae AD |
936 | #define CB_CGTT_SCLK_CTRL 0x3c2a0 |
| 937 | ||
| 841cf442 AD |
938 | /* |
| 939 | * PM4 | |
| 940 | */ | |
| 941 | #define PACKET_TYPE0 0 | |
| 942 | #define PACKET_TYPE1 1 | |
| 943 | #define PACKET_TYPE2 2 | |
| 944 | #define PACKET_TYPE3 3 | |
| 945 | ||
| 946 | #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) | |
| 947 | #define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) | |
| 948 | #define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2) | |
| 949 | #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) | |
| 950 | #define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \ | |
| 951 | (((reg) >> 2) & 0xFFFF) | \ | |
| 952 | ((n) & 0x3FFF) << 16) | |
| 953 | #define CP_PACKET2 0x80000000 | |
| 954 | #define PACKET2_PAD_SHIFT 0 | |
| 955 | #define PACKET2_PAD_MASK (0x3fffffff << 0) | |
| 956 | ||
| 957 | #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) | |
| 958 | ||
| 959 | #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ | |
| 960 | (((op) & 0xFF) << 8) | \ | |
| 961 | ((n) & 0x3FFF) << 16) | |
| 962 | ||
| 963 | #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1) | |
| 964 | ||
| 965 | /* Packet 3 types */ | |
| 966 | #define PACKET3_NOP 0x10 | |
| 967 | #define PACKET3_SET_BASE 0x11 | |
| 968 | #define PACKET3_BASE_INDEX(x) ((x) << 0) | |
| 969 | #define CE_PARTITION_BASE 3 | |
| 970 | #define PACKET3_CLEAR_STATE 0x12 | |
| 971 | #define PACKET3_INDEX_BUFFER_SIZE 0x13 | |
| 972 | #define PACKET3_DISPATCH_DIRECT 0x15 | |
| 973 | #define PACKET3_DISPATCH_INDIRECT 0x16 | |
| 974 | #define PACKET3_ATOMIC_GDS 0x1D | |
| 975 | #define PACKET3_ATOMIC_MEM 0x1E | |
| 976 | #define PACKET3_OCCLUSION_QUERY 0x1F | |
| 977 | #define PACKET3_SET_PREDICATION 0x20 | |
| 978 | #define PACKET3_REG_RMW 0x21 | |
| 979 | #define PACKET3_COND_EXEC 0x22 | |
| 980 | #define PACKET3_PRED_EXEC 0x23 | |
| 981 | #define PACKET3_DRAW_INDIRECT 0x24 | |
| 982 | #define PACKET3_DRAW_INDEX_INDIRECT 0x25 | |
| 983 | #define PACKET3_INDEX_BASE 0x26 | |
| 984 | #define PACKET3_DRAW_INDEX_2 0x27 | |
| 985 | #define PACKET3_CONTEXT_CONTROL 0x28 | |
| 986 | #define PACKET3_INDEX_TYPE 0x2A | |
| 987 | #define PACKET3_DRAW_INDIRECT_MULTI 0x2C | |
| 988 | #define PACKET3_DRAW_INDEX_AUTO 0x2D | |
| 989 | #define PACKET3_NUM_INSTANCES 0x2F | |
| 990 | #define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30 | |
| 991 | #define PACKET3_INDIRECT_BUFFER_CONST 0x33 | |
| 992 | #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 | |
| 993 | #define PACKET3_DRAW_INDEX_OFFSET_2 0x35 | |
| 994 | #define PACKET3_DRAW_PREAMBLE 0x36 | |
| 995 | #define PACKET3_WRITE_DATA 0x37 | |
| 2cae3bc3 AD |
996 | #define WRITE_DATA_DST_SEL(x) ((x) << 8) |
| 997 | /* 0 - register | |
| 998 | * 1 - memory (sync - via GRBM) | |
| 999 | * 2 - gl2 | |
| 1000 | * 3 - gds | |
| 1001 | * 4 - reserved | |
| 1002 | * 5 - memory (async - direct) | |
| 1003 | */ | |
| 1004 | #define WR_ONE_ADDR (1 << 16) | |
| 1005 | #define WR_CONFIRM (1 << 20) | |
| 1006 | #define WRITE_DATA_CACHE_POLICY(x) ((x) << 25) | |
| 1007 | /* 0 - LRU | |
| 1008 | * 1 - Stream | |
| 1009 | */ | |
| 1010 | #define WRITE_DATA_ENGINE_SEL(x) ((x) << 30) | |
| 1011 | /* 0 - me | |
| 1012 | * 1 - pfp | |
| 1013 | * 2 - ce | |
| 1014 | */ | |
| 841cf442 AD |
1015 | #define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38 |
| 1016 | #define PACKET3_MEM_SEMAPHORE 0x39 | |
| 2cae3bc3 AD |
1017 | # define PACKET3_SEM_USE_MAILBOX (0x1 << 16) |
| 1018 | # define PACKET3_SEM_SEL_SIGNAL_TYPE (0x1 << 20) /* 0 = increment, 1 = write 1 */ | |
| 1019 | # define PACKET3_SEM_CLIENT_CODE ((x) << 24) /* 0 = CP, 1 = CB, 2 = DB */ | |
| 1020 | # define PACKET3_SEM_SEL_SIGNAL (0x6 << 29) | |
| 1021 | # define PACKET3_SEM_SEL_WAIT (0x7 << 29) | |
| 841cf442 AD |
1022 | #define PACKET3_COPY_DW 0x3B |
| 1023 | #define PACKET3_WAIT_REG_MEM 0x3C | |
| 2cae3bc3 AD |
1024 | #define WAIT_REG_MEM_FUNCTION(x) ((x) << 0) |
| 1025 | /* 0 - always | |
| 1026 | * 1 - < | |
| 1027 | * 2 - <= | |
| 1028 | * 3 - == | |
| 1029 | * 4 - != | |
| 1030 | * 5 - >= | |
| 1031 | * 6 - > | |
| 1032 | */ | |
| 1033 | #define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4) | |
| 1034 | /* 0 - reg | |
| 1035 | * 1 - mem | |
| 1036 | */ | |
| 1037 | #define WAIT_REG_MEM_OPERATION(x) ((x) << 6) | |
| 1038 | /* 0 - wait_reg_mem | |
| 1039 | * 1 - wr_wait_wr_reg | |
| 1040 | */ | |
| 1041 | #define WAIT_REG_MEM_ENGINE(x) ((x) << 8) | |
| 1042 | /* 0 - me | |
| 1043 | * 1 - pfp | |
| 1044 | */ | |
| 841cf442 | 1045 | #define PACKET3_INDIRECT_BUFFER 0x3F |
| 2cae3bc3 AD |
1046 | #define INDIRECT_BUFFER_TCL2_VOLATILE (1 << 22) |
| 1047 | #define INDIRECT_BUFFER_VALID (1 << 23) | |
| 1048 | #define INDIRECT_BUFFER_CACHE_POLICY(x) ((x) << 28) | |
| 1049 | /* 0 - LRU | |
| 1050 | * 1 - Stream | |
| 1051 | * 2 - Bypass | |
| 1052 | */ | |
| 841cf442 AD |
1053 | #define PACKET3_COPY_DATA 0x40 |
| 1054 | #define PACKET3_PFP_SYNC_ME 0x42 | |
| 1055 | #define PACKET3_SURFACE_SYNC 0x43 | |
| 1056 | # define PACKET3_DEST_BASE_0_ENA (1 << 0) | |
| 1057 | # define PACKET3_DEST_BASE_1_ENA (1 << 1) | |
| 1058 | # define PACKET3_CB0_DEST_BASE_ENA (1 << 6) | |
| 1059 | # define PACKET3_CB1_DEST_BASE_ENA (1 << 7) | |
| 1060 | # define PACKET3_CB2_DEST_BASE_ENA (1 << 8) | |
| 1061 | # define PACKET3_CB3_DEST_BASE_ENA (1 << 9) | |
| 1062 | # define PACKET3_CB4_DEST_BASE_ENA (1 << 10) | |
| 1063 | # define PACKET3_CB5_DEST_BASE_ENA (1 << 11) | |
| 1064 | # define PACKET3_CB6_DEST_BASE_ENA (1 << 12) | |
| 1065 | # define PACKET3_CB7_DEST_BASE_ENA (1 << 13) | |
| 1066 | # define PACKET3_DB_DEST_BASE_ENA (1 << 14) | |
| 1067 | # define PACKET3_TCL1_VOL_ACTION_ENA (1 << 15) | |
| 1068 | # define PACKET3_TC_VOL_ACTION_ENA (1 << 16) /* L2 */ | |
| 1069 | # define PACKET3_TC_WB_ACTION_ENA (1 << 18) /* L2 */ | |
| 1070 | # define PACKET3_DEST_BASE_2_ENA (1 << 19) | |
| 1071 | # define PACKET3_DEST_BASE_3_ENA (1 << 21) | |
| 1072 | # define PACKET3_TCL1_ACTION_ENA (1 << 22) | |
| 1073 | # define PACKET3_TC_ACTION_ENA (1 << 23) /* L2 */ | |
| 1074 | # define PACKET3_CB_ACTION_ENA (1 << 25) | |
| 1075 | # define PACKET3_DB_ACTION_ENA (1 << 26) | |
| 1076 | # define PACKET3_SH_KCACHE_ACTION_ENA (1 << 27) | |
| 1077 | # define PACKET3_SH_KCACHE_VOL_ACTION_ENA (1 << 28) | |
| 1078 | # define PACKET3_SH_ICACHE_ACTION_ENA (1 << 29) | |
| 1079 | #define PACKET3_COND_WRITE 0x45 | |
| 1080 | #define PACKET3_EVENT_WRITE 0x46 | |
| 1081 | #define EVENT_TYPE(x) ((x) << 0) | |
| 1082 | #define EVENT_INDEX(x) ((x) << 8) | |
| 1083 | /* 0 - any non-TS event | |
| 1084 | * 1 - ZPASS_DONE, PIXEL_PIPE_STAT_* | |
| 1085 | * 2 - SAMPLE_PIPELINESTAT | |
| 1086 | * 3 - SAMPLE_STREAMOUTSTAT* | |
| 1087 | * 4 - *S_PARTIAL_FLUSH | |
| 1088 | * 5 - EOP events | |
| 1089 | * 6 - EOS events | |
| 1090 | */ | |
| 1091 | #define PACKET3_EVENT_WRITE_EOP 0x47 | |
| 1092 | #define EOP_TCL1_VOL_ACTION_EN (1 << 12) | |
| 1093 | #define EOP_TC_VOL_ACTION_EN (1 << 13) /* L2 */ | |
| 1094 | #define EOP_TC_WB_ACTION_EN (1 << 15) /* L2 */ | |
| 1095 | #define EOP_TCL1_ACTION_EN (1 << 16) | |
| 1096 | #define EOP_TC_ACTION_EN (1 << 17) /* L2 */ | |
| 2cae3bc3 | 1097 | #define EOP_CACHE_POLICY(x) ((x) << 25) |
| 841cf442 AD |
1098 | /* 0 - LRU |
| 1099 | * 1 - Stream | |
| 1100 | * 2 - Bypass | |
| 1101 | */ | |
| 2cae3bc3 | 1102 | #define EOP_TCL2_VOLATILE (1 << 27) |
| 841cf442 AD |
1103 | #define DATA_SEL(x) ((x) << 29) |
| 1104 | /* 0 - discard | |
| 1105 | * 1 - send low 32bit data | |
| 1106 | * 2 - send 64bit data | |
| 1107 | * 3 - send 64bit GPU counter value | |
| 1108 | * 4 - send 64bit sys counter value | |
| 1109 | */ | |
| 1110 | #define INT_SEL(x) ((x) << 24) | |
| 1111 | /* 0 - none | |
| 1112 | * 1 - interrupt only (DATA_SEL = 0) | |
| 1113 | * 2 - interrupt when data write is confirmed | |
| 1114 | */ | |
| 1115 | #define DST_SEL(x) ((x) << 16) | |
| 1116 | /* 0 - MC | |
| 1117 | * 1 - TC/L2 | |
| 1118 | */ | |
| 1119 | #define PACKET3_EVENT_WRITE_EOS 0x48 | |
| 1120 | #define PACKET3_RELEASE_MEM 0x49 | |
| 1121 | #define PACKET3_PREAMBLE_CNTL 0x4A | |
| 1122 | # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) | |
| 1123 | # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) | |
| 1124 | #define PACKET3_DMA_DATA 0x50 | |
| 1125 | #define PACKET3_AQUIRE_MEM 0x58 | |
| 1126 | #define PACKET3_REWIND 0x59 | |
| 1127 | #define PACKET3_LOAD_UCONFIG_REG 0x5E | |
| 1128 | #define PACKET3_LOAD_SH_REG 0x5F | |
| 1129 | #define PACKET3_LOAD_CONFIG_REG 0x60 | |
| 1130 | #define PACKET3_LOAD_CONTEXT_REG 0x61 | |
| 1131 | #define PACKET3_SET_CONFIG_REG 0x68 | |
| 1132 | #define PACKET3_SET_CONFIG_REG_START 0x00008000 | |
| 1133 | #define PACKET3_SET_CONFIG_REG_END 0x0000b000 | |
| 1134 | #define PACKET3_SET_CONTEXT_REG 0x69 | |
| 1135 | #define PACKET3_SET_CONTEXT_REG_START 0x00028000 | |
| 1136 | #define PACKET3_SET_CONTEXT_REG_END 0x00029000 | |
| 1137 | #define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73 | |
| 1138 | #define PACKET3_SET_SH_REG 0x76 | |
| 1139 | #define PACKET3_SET_SH_REG_START 0x0000b000 | |
| 1140 | #define PACKET3_SET_SH_REG_END 0x0000c000 | |
| 1141 | #define PACKET3_SET_SH_REG_OFFSET 0x77 | |
| 1142 | #define PACKET3_SET_QUEUE_REG 0x78 | |
| 1143 | #define PACKET3_SET_UCONFIG_REG 0x79 | |
| 2cae3bc3 AD |
1144 | #define PACKET3_SET_UCONFIG_REG_START 0x00030000 |
| 1145 | #define PACKET3_SET_UCONFIG_REG_END 0x00031000 | |
| 841cf442 AD |
1146 | #define PACKET3_SCRATCH_RAM_WRITE 0x7D |
| 1147 | #define PACKET3_SCRATCH_RAM_READ 0x7E | |
| 1148 | #define PACKET3_LOAD_CONST_RAM 0x80 | |
| 1149 | #define PACKET3_WRITE_CONST_RAM 0x81 | |
| 1150 | #define PACKET3_DUMP_CONST_RAM 0x83 | |
| 1151 | #define PACKET3_INCREMENT_CE_COUNTER 0x84 | |
| 1152 | #define PACKET3_INCREMENT_DE_COUNTER 0x85 | |
| 1153 | #define PACKET3_WAIT_ON_CE_COUNTER 0x86 | |
| 1154 | #define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88 | |
| 2cae3bc3 | 1155 | #define PACKET3_SWITCH_BUFFER 0x8B |
| 841cf442 | 1156 | |
| 21a93e13 AD |
1157 | /* SDMA - first instance at 0xd000, second at 0xd800 */ |
| 1158 | #define SDMA0_REGISTER_OFFSET 0x0 /* not a register */ | |
| 1159 | #define SDMA1_REGISTER_OFFSET 0x800 /* not a register */ | |
| 1160 | ||
| 1161 | #define SDMA0_UCODE_ADDR 0xD000 | |
| 1162 | #define SDMA0_UCODE_DATA 0xD004 | |
| 1163 | ||
| 1164 | #define SDMA0_CNTL 0xD010 | |
| 1165 | # define TRAP_ENABLE (1 << 0) | |
| 1166 | # define SEM_INCOMPLETE_INT_ENABLE (1 << 1) | |
| 1167 | # define SEM_WAIT_INT_ENABLE (1 << 2) | |
| 1168 | # define DATA_SWAP_ENABLE (1 << 3) | |
| 1169 | # define FENCE_SWAP_ENABLE (1 << 4) | |
| 1170 | # define AUTO_CTXSW_ENABLE (1 << 18) | |
| 1171 | # define CTXEMPTY_INT_ENABLE (1 << 28) | |
| 1172 | ||
| 1173 | #define SDMA0_TILING_CONFIG 0xD018 | |
| 1174 | ||
| 1175 | #define SDMA0_SEM_INCOMPLETE_TIMER_CNTL 0xD020 | |
| 1176 | #define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL 0xD024 | |
| 1177 | ||
| 1178 | #define SDMA0_STATUS_REG 0xd034 | |
| 1179 | # define SDMA_IDLE (1 << 0) | |
| 1180 | ||
| 1181 | #define SDMA0_ME_CNTL 0xD048 | |
| 1182 | # define SDMA_HALT (1 << 0) | |
| 1183 | ||
| 1184 | #define SDMA0_GFX_RB_CNTL 0xD200 | |
| 1185 | # define SDMA_RB_ENABLE (1 << 0) | |
| 1186 | # define SDMA_RB_SIZE(x) ((x) << 1) /* log2 */ | |
| 1187 | # define SDMA_RB_SWAP_ENABLE (1 << 9) /* 8IN32 */ | |
| 1188 | # define SDMA_RPTR_WRITEBACK_ENABLE (1 << 12) | |
| 1189 | # define SDMA_RPTR_WRITEBACK_SWAP_ENABLE (1 << 13) /* 8IN32 */ | |
| 1190 | # define SDMA_RPTR_WRITEBACK_TIMER(x) ((x) << 16) /* log2 */ | |
| 1191 | #define SDMA0_GFX_RB_BASE 0xD204 | |
| 1192 | #define SDMA0_GFX_RB_BASE_HI 0xD208 | |
| 1193 | #define SDMA0_GFX_RB_RPTR 0xD20C | |
| 1194 | #define SDMA0_GFX_RB_WPTR 0xD210 | |
| 1195 | ||
| 1196 | #define SDMA0_GFX_RB_RPTR_ADDR_HI 0xD220 | |
| 1197 | #define SDMA0_GFX_RB_RPTR_ADDR_LO 0xD224 | |
| 1198 | #define SDMA0_GFX_IB_CNTL 0xD228 | |
| 1199 | # define SDMA_IB_ENABLE (1 << 0) | |
| 1200 | # define SDMA_IB_SWAP_ENABLE (1 << 4) | |
| 1201 | # define SDMA_SWITCH_INSIDE_IB (1 << 8) | |
| 1202 | # define SDMA_CMD_VMID(x) ((x) << 16) | |
| 1203 | ||
| 1204 | #define SDMA0_GFX_VIRTUAL_ADDR 0xD29C | |
| 1205 | #define SDMA0_GFX_APE1_CNTL 0xD2A0 | |
| 1206 | ||
| 1207 | #define SDMA_PACKET(op, sub_op, e) ((((e) & 0xFFFF) << 16) | \ | |
| 1208 | (((sub_op) & 0xFF) << 8) | \ | |
| 1209 | (((op) & 0xFF) << 0)) | |
| 1210 | /* sDMA opcodes */ | |
| 1211 | #define SDMA_OPCODE_NOP 0 | |
| 1212 | #define SDMA_OPCODE_COPY 1 | |
| 1213 | # define SDMA_COPY_SUB_OPCODE_LINEAR 0 | |
| 1214 | # define SDMA_COPY_SUB_OPCODE_TILED 1 | |
| 1215 | # define SDMA_COPY_SUB_OPCODE_SOA 3 | |
| 1216 | # define SDMA_COPY_SUB_OPCODE_LINEAR_SUB_WINDOW 4 | |
| 1217 | # define SDMA_COPY_SUB_OPCODE_TILED_SUB_WINDOW 5 | |
| 1218 | # define SDMA_COPY_SUB_OPCODE_T2T_SUB_WINDOW 6 | |
| 1219 | #define SDMA_OPCODE_WRITE 2 | |
| 1220 | # define SDMA_WRITE_SUB_OPCODE_LINEAR 0 | |
| 1221 | # define SDMA_WRTIE_SUB_OPCODE_TILED 1 | |
| 1222 | #define SDMA_OPCODE_INDIRECT_BUFFER 4 | |
| 1223 | #define SDMA_OPCODE_FENCE 5 | |
| 1224 | #define SDMA_OPCODE_TRAP 6 | |
| 1225 | #define SDMA_OPCODE_SEMAPHORE 7 | |
| 1226 | # define SDMA_SEMAPHORE_EXTRA_O (1 << 13) | |
| 1227 | /* 0 - increment | |
| 1228 | * 1 - write 1 | |
| 1229 | */ | |
| 1230 | # define SDMA_SEMAPHORE_EXTRA_S (1 << 14) | |
| 1231 | /* 0 - wait | |
| 1232 | * 1 - signal | |
| 1233 | */ | |
| 1234 | # define SDMA_SEMAPHORE_EXTRA_M (1 << 15) | |
| 1235 | /* mailbox */ | |
| 1236 | #define SDMA_OPCODE_POLL_REG_MEM 8 | |
| 1237 | # define SDMA_POLL_REG_MEM_EXTRA_OP(x) ((x) << 10) | |
| 1238 | /* 0 - wait_reg_mem | |
| 1239 | * 1 - wr_wait_wr_reg | |
| 1240 | */ | |
| 1241 | # define SDMA_POLL_REG_MEM_EXTRA_FUNC(x) ((x) << 12) | |
| 1242 | /* 0 - always | |
| 1243 | * 1 - < | |
| 1244 | * 2 - <= | |
| 1245 | * 3 - == | |
| 1246 | * 4 - != | |
| 1247 | * 5 - >= | |
| 1248 | * 6 - > | |
| 1249 | */ | |
| 1250 | # define SDMA_POLL_REG_MEM_EXTRA_M (1 << 15) | |
| 1251 | /* 0 = register | |
| 1252 | * 1 = memory | |
| 1253 | */ | |
| 1254 | #define SDMA_OPCODE_COND_EXEC 9 | |
| 1255 | #define SDMA_OPCODE_CONSTANT_FILL 11 | |
| 1256 | # define SDMA_CONSTANT_FILL_EXTRA_SIZE(x) ((x) << 14) | |
| 1257 | /* 0 = byte fill | |
| 1258 | * 2 = DW fill | |
| 1259 | */ | |
| 1260 | #define SDMA_OPCODE_GENERATE_PTE_PDE 12 | |
| 1261 | #define SDMA_OPCODE_TIMESTAMP 13 | |
| 1262 | # define SDMA_TIMESTAMP_SUB_OPCODE_SET_LOCAL 0 | |
| 1263 | # define SDMA_TIMESTAMP_SUB_OPCODE_GET_LOCAL 1 | |
| 1264 | # define SDMA_TIMESTAMP_SUB_OPCODE_GET_GLOBAL 2 | |
| 1265 | #define SDMA_OPCODE_SRBM_WRITE 14 | |
| 1266 | # define SDMA_SRBM_WRITE_EXTRA_BYTE_ENABLE(x) ((x) << 12) | |
| 1267 | /* byte mask */ | |
| 1268 | ||
| 87167bb1 CK |
1269 | /* UVD */ |
| 1270 | ||
| 1271 | #define UVD_UDEC_ADDR_CONFIG 0xef4c | |
| 1272 | #define UVD_UDEC_DB_ADDR_CONFIG 0xef50 | |
| 1273 | #define UVD_UDEC_DBW_ADDR_CONFIG 0xef54 | |
| 1274 | ||
| 1275 | #define UVD_LMI_EXT40_ADDR 0xf498 | |
| 1276 | #define UVD_LMI_ADDR_EXT 0xf594 | |
| 1277 | #define UVD_VCPU_CACHE_OFFSET0 0xf608 | |
| 1278 | #define UVD_VCPU_CACHE_SIZE0 0xf60c | |
| 1279 | #define UVD_VCPU_CACHE_OFFSET1 0xf610 | |
| 1280 | #define UVD_VCPU_CACHE_SIZE1 0xf614 | |
| 1281 | #define UVD_VCPU_CACHE_OFFSET2 0xf618 | |
| 1282 | #define UVD_VCPU_CACHE_SIZE2 0xf61c | |
| 1283 | ||
| 1284 | #define UVD_RBC_RB_RPTR 0xf690 | |
| 1285 | #define UVD_RBC_RB_WPTR 0xf694 | |
| 1286 | ||
| 1287 | /* UVD clocks */ | |
| 1288 | ||
| 1289 | #define CG_DCLK_CNTL 0xC050009C | |
| 1290 | # define DCLK_DIVIDER_MASK 0x7f | |
| 1291 | # define DCLK_DIR_CNTL_EN (1 << 8) | |
| 1292 | #define CG_DCLK_STATUS 0xC05000A0 | |
| 1293 | # define DCLK_STATUS (1 << 0) | |
| 1294 | #define CG_VCLK_CNTL 0xC05000A4 | |
| 1295 | #define CG_VCLK_STATUS 0xC05000A8 | |
| 1296 | ||
| 8cc1a532 | 1297 | #endif |