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drm/radeon/dpm: fixup dynamic state adjust for btc (v2)
[deliverable/linux.git] / drivers / gpu / drm / radeon / cypress_dpm.c
CommitLineData
dc50ba7f
AD		 1/*
2 * Copyright 2011 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24
25#include "drmP.h"
26#include "radeon.h"
27#include "evergreend.h"
28#include "r600_dpm.h"
29#include "cypress_dpm.h"
30#include "atom.h"
31
32#define SMC_RAM_END 0x8000
33
34#define MC_CG_ARB_FREQ_F0 0x0a
35#define MC_CG_ARB_FREQ_F1 0x0b
36#define MC_CG_ARB_FREQ_F2 0x0c
37#define MC_CG_ARB_FREQ_F3 0x0d
38
39#define MC_CG_SEQ_DRAMCONF_S0 0x05
40#define MC_CG_SEQ_DRAMCONF_S1 0x06
41#define MC_CG_SEQ_YCLK_SUSPEND 0x04
42#define MC_CG_SEQ_YCLK_RESUME 0x0a
43
44struct rv7xx_ps *rv770_get_ps(struct radeon_ps *rps);
45struct rv7xx_power_info *rv770_get_pi(struct radeon_device *rdev);
46struct evergreen_power_info *evergreen_get_pi(struct radeon_device *rdev);
47
48static u8 cypress_get_mclk_frequency_ratio(struct radeon_device *rdev,
49 u32 memory_clock, bool strobe_mode);
50
51static void cypress_enable_bif_dynamic_pcie_gen2(struct radeon_device *rdev,
52 bool enable)
53{
54 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
55 u32 tmp, bif;
56
57 tmp = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
58 if (enable) {
59 if ((tmp & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
60 (tmp & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
61 if (!pi->boot_in_gen2) {
62 bif = RREG32(CG_BIF_REQ_AND_RSP) & ~CG_CLIENT_REQ_MASK;
63 bif |= CG_CLIENT_REQ(0xd);
64 WREG32(CG_BIF_REQ_AND_RSP, bif);
65
66 tmp &= ~LC_HW_VOLTAGE_IF_CONTROL_MASK;
67 tmp |= LC_HW_VOLTAGE_IF_CONTROL(1);
68 tmp |= LC_GEN2_EN_STRAP;
69
70 tmp |= LC_CLR_FAILED_SPD_CHANGE_CNT;
71 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp);
72 udelay(10);
73 tmp &= ~LC_CLR_FAILED_SPD_CHANGE_CNT;
74 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp);
75 }
76 }
77 } else {
78 if (!pi->boot_in_gen2) {
79 tmp &= ~LC_HW_VOLTAGE_IF_CONTROL_MASK;
80 tmp &= ~LC_GEN2_EN_STRAP;
81 }
82 if ((tmp & LC_OTHER_SIDE_EVER_SENT_GEN2) ||
83 (tmp & LC_OTHER_SIDE_SUPPORTS_GEN2))
84 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp);
85 }
86}
87
88static void cypress_enable_dynamic_pcie_gen2(struct radeon_device *rdev,
89 bool enable)
90{
91 cypress_enable_bif_dynamic_pcie_gen2(rdev, enable);
92
93 if (enable)
94 WREG32_P(GENERAL_PWRMGT, ENABLE_GEN2PCIE, ~ENABLE_GEN2PCIE);
95 else
96 WREG32_P(GENERAL_PWRMGT, 0, ~ENABLE_GEN2PCIE);
97}
98
99#if 0
100static int cypress_enter_ulp_state(struct radeon_device *rdev)
101{
102 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
103
104 if (pi->gfx_clock_gating) {
105 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN);
106 WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON);
107 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON);
108
109 RREG32(GB_ADDR_CONFIG);
110 }
111
112 WREG32_P(SMC_MSG, HOST_SMC_MSG(PPSMC_MSG_SwitchToMinimumPower),
113 ~HOST_SMC_MSG_MASK);
114
115 udelay(7000);
116
117 return 0;
118}
119#endif
120
121static void cypress_gfx_clock_gating_enable(struct radeon_device *rdev,
122 bool enable)
123{
124 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
125
126 if (enable) {
127 if (eg_pi->light_sleep) {
128 WREG32(GRBM_GFX_INDEX, 0xC0000000);
129
130 WREG32_CG(CG_CGLS_TILE_0, 0xFFFFFFFF);
131 WREG32_CG(CG_CGLS_TILE_1, 0xFFFFFFFF);
132 WREG32_CG(CG_CGLS_TILE_2, 0xFFFFFFFF);
133 WREG32_CG(CG_CGLS_TILE_3, 0xFFFFFFFF);
134 WREG32_CG(CG_CGLS_TILE_4, 0xFFFFFFFF);
135 WREG32_CG(CG_CGLS_TILE_5, 0xFFFFFFFF);
136 WREG32_CG(CG_CGLS_TILE_6, 0xFFFFFFFF);
137 WREG32_CG(CG_CGLS_TILE_7, 0xFFFFFFFF);
138 WREG32_CG(CG_CGLS_TILE_8, 0xFFFFFFFF);
139 WREG32_CG(CG_CGLS_TILE_9, 0xFFFFFFFF);
140 WREG32_CG(CG_CGLS_TILE_10, 0xFFFFFFFF);
141 WREG32_CG(CG_CGLS_TILE_11, 0xFFFFFFFF);
142
143 WREG32_P(SCLK_PWRMGT_CNTL, DYN_LIGHT_SLEEP_EN, ~DYN_LIGHT_SLEEP_EN);
144 }
145 WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN);
146 } else {
147 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN);
148 WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON);
149 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON);
150 RREG32(GB_ADDR_CONFIG);
151
152 if (eg_pi->light_sleep) {
153 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_LIGHT_SLEEP_EN);
154
155 WREG32(GRBM_GFX_INDEX, 0xC0000000);
156
157 WREG32_CG(CG_CGLS_TILE_0, 0);
158 WREG32_CG(CG_CGLS_TILE_1, 0);
159 WREG32_CG(CG_CGLS_TILE_2, 0);
160 WREG32_CG(CG_CGLS_TILE_3, 0);
161 WREG32_CG(CG_CGLS_TILE_4, 0);
162 WREG32_CG(CG_CGLS_TILE_5, 0);
163 WREG32_CG(CG_CGLS_TILE_6, 0);
164 WREG32_CG(CG_CGLS_TILE_7, 0);
165 WREG32_CG(CG_CGLS_TILE_8, 0);
166 WREG32_CG(CG_CGLS_TILE_9, 0);
167 WREG32_CG(CG_CGLS_TILE_10, 0);
168 WREG32_CG(CG_CGLS_TILE_11, 0);
169 }
170 }
171}
172
173static void cypress_mg_clock_gating_enable(struct radeon_device *rdev,
174 bool enable)
175{
176 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
177 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
178
179 if (enable) {
180 u32 cgts_sm_ctrl_reg;
181
182 if (rdev->family == CHIP_CEDAR)
183 cgts_sm_ctrl_reg = CEDAR_MGCGCGTSSMCTRL_DFLT;
184 else if (rdev->family == CHIP_REDWOOD)
185 cgts_sm_ctrl_reg = REDWOOD_MGCGCGTSSMCTRL_DFLT;
186 else
187 cgts_sm_ctrl_reg = CYPRESS_MGCGCGTSSMCTRL_DFLT;
188
189 WREG32(GRBM_GFX_INDEX, 0xC0000000);
190
191 WREG32_CG(CG_CGTT_LOCAL_0, CYPRESS_MGCGTTLOCAL0_DFLT);
192 WREG32_CG(CG_CGTT_LOCAL_1, CYPRESS_MGCGTTLOCAL1_DFLT & 0xFFFFCFFF);
193 WREG32_CG(CG_CGTT_LOCAL_2, CYPRESS_MGCGTTLOCAL2_DFLT);
194 WREG32_CG(CG_CGTT_LOCAL_3, CYPRESS_MGCGTTLOCAL3_DFLT);
195
196 if (pi->mgcgtssm)
197 WREG32(CGTS_SM_CTRL_REG, cgts_sm_ctrl_reg);
198
199 if (eg_pi->mcls) {
200 WREG32_P(MC_CITF_MISC_RD_CG, MEM_LS_ENABLE, ~MEM_LS_ENABLE);
201 WREG32_P(MC_CITF_MISC_WR_CG, MEM_LS_ENABLE, ~MEM_LS_ENABLE);
202 WREG32_P(MC_CITF_MISC_VM_CG, MEM_LS_ENABLE, ~MEM_LS_ENABLE);
203 WREG32_P(MC_HUB_MISC_HUB_CG, MEM_LS_ENABLE, ~MEM_LS_ENABLE);
204 WREG32_P(MC_HUB_MISC_VM_CG, MEM_LS_ENABLE, ~MEM_LS_ENABLE);
205 WREG32_P(MC_HUB_MISC_SIP_CG, MEM_LS_ENABLE, ~MEM_LS_ENABLE);
206 WREG32_P(MC_XPB_CLK_GAT, MEM_LS_ENABLE, ~MEM_LS_ENABLE);
207 WREG32_P(VM_L2_CG, MEM_LS_ENABLE, ~MEM_LS_ENABLE);
208 }
209 } else {
210 WREG32(GRBM_GFX_INDEX, 0xC0000000);
211
212 WREG32_CG(CG_CGTT_LOCAL_0, 0xFFFFFFFF);
213 WREG32_CG(CG_CGTT_LOCAL_1, 0xFFFFFFFF);
214 WREG32_CG(CG_CGTT_LOCAL_2, 0xFFFFFFFF);
215 WREG32_CG(CG_CGTT_LOCAL_3, 0xFFFFFFFF);
216
217 if (pi->mgcgtssm)
218 WREG32(CGTS_SM_CTRL_REG, 0x81f44bc0);
219 }
220}
221
222void cypress_enable_spread_spectrum(struct radeon_device *rdev,
223 bool enable)
224{
225 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
226
227 if (enable) {
228 if (pi->sclk_ss)
229 WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN);
230
231 if (pi->mclk_ss)
232 WREG32_P(MPLL_CNTL_MODE, SS_SSEN, ~SS_SSEN);
233 } else {
234 WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN);
235 WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN);
236 WREG32_P(MPLL_CNTL_MODE, 0, ~SS_SSEN);
237 WREG32_P(MPLL_CNTL_MODE, 0, ~SS_DSMODE_EN);
238 }
239}
240
241void cypress_start_dpm(struct radeon_device *rdev)
242{
243 WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN);
244}
245
246void cypress_enable_sclk_control(struct radeon_device *rdev,
247 bool enable)
248{
249 if (enable)
250 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF);
251 else
252 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF);
253}
254
255void cypress_enable_mclk_control(struct radeon_device *rdev,
256 bool enable)
257{
258 if (enable)
259 WREG32_P(MCLK_PWRMGT_CNTL, 0, ~MPLL_PWRMGT_OFF);
260 else
261 WREG32_P(MCLK_PWRMGT_CNTL, MPLL_PWRMGT_OFF, ~MPLL_PWRMGT_OFF);
262}
263
264int cypress_notify_smc_display_change(struct radeon_device *rdev,
265 bool has_display)
266{
267 PPSMC_Msg msg = has_display ?
268 (PPSMC_Msg)PPSMC_MSG_HasDisplay : (PPSMC_Msg)PPSMC_MSG_NoDisplay;
269
270 if (rv770_send_msg_to_smc(rdev, msg) != PPSMC_Result_OK)
271 return -EINVAL;
272
273 return 0;
274}
275
276void cypress_program_response_times(struct radeon_device *rdev)
277{
278 u32 reference_clock;
279 u32 mclk_switch_limit;
280
281 reference_clock = radeon_get_xclk(rdev);
282 mclk_switch_limit = (460 * reference_clock) / 100;
283
284 rv770_write_smc_soft_register(rdev,
285 RV770_SMC_SOFT_REGISTER_mclk_switch_lim,
286 mclk_switch_limit);
287
288 rv770_write_smc_soft_register(rdev,
289 RV770_SMC_SOFT_REGISTER_mvdd_chg_time, 1);
290
291 rv770_write_smc_soft_register(rdev,
292 RV770_SMC_SOFT_REGISTER_mc_block_delay, 0xAA);
293
294 rv770_program_response_times(rdev);
295
296 if (ASIC_IS_LOMBOK(rdev))
297 rv770_write_smc_soft_register(rdev,
298 RV770_SMC_SOFT_REGISTER_is_asic_lombok, 1);
299
300}
301
302static int cypress_pcie_performance_request(struct radeon_device *rdev,
303 u8 perf_req, bool advertise)
304{
305 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
306 u32 tmp;
307
308 udelay(10);
309 tmp = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
310 if ((perf_req == PCIE_PERF_REQ_PECI_GEN1) && (tmp & LC_CURRENT_DATA_RATE))
311 return 0;
312
313#if defined(CONFIG_ACPI)
314 if ((perf_req == PCIE_PERF_REQ_PECI_GEN1) ||
315 (perf_req == PCIE_PERF_REQ_PECI_GEN2)) {
316 eg_pi->pcie_performance_request_registered = true;
317 return radeon_acpi_pcie_performance_request(rdev, perf_req, advertise);
318 } else if ((perf_req == PCIE_PERF_REQ_REMOVE_REGISTRY) &&
319 eg_pi->pcie_performance_request_registered) {
320 eg_pi->pcie_performance_request_registered = false;
321 return radeon_acpi_pcie_performance_request(rdev, perf_req, advertise);
322 }
323#endif
324
325 return 0;
326}
327
328void cypress_advertise_gen2_capability(struct radeon_device *rdev)
329{
330 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
331 u32 tmp;
332
333#if defined(CONFIG_ACPI)
334 radeon_acpi_pcie_notify_device_ready(rdev);
335#endif
336
337 tmp = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
338
339 if ((tmp & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
340 (tmp & LC_OTHER_SIDE_SUPPORTS_GEN2))
341 pi->pcie_gen2 = true;
342 else
343 pi->pcie_gen2 = false;
344
345 if (!pi->pcie_gen2)
346 cypress_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, true);
347
348}
349
350static u32 cypress_get_maximum_link_speed(struct radeon_ps *radeon_state)
351{
352 struct rv7xx_ps *state = rv770_get_ps(radeon_state);
353
354 if (state->high.flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2)
355 return 1;
356 return 0;
357}
358
359void cypress_notify_link_speed_change_after_state_change(struct radeon_device *rdev)
360{
361 struct radeon_ps *radeon_new_state = rdev->pm.dpm.requested_ps;
362 struct radeon_ps *radeon_current_state = rdev->pm.dpm.current_ps;
363 u32 pcie_link_speed_target = cypress_get_maximum_link_speed(radeon_new_state);
364 u32 pcie_link_speed_current = cypress_get_maximum_link_speed(radeon_current_state);
365 u8 request;
366
367 if (pcie_link_speed_target < pcie_link_speed_current) {
368 if (pcie_link_speed_target == 0)
369 request = PCIE_PERF_REQ_PECI_GEN1;
370 else if (pcie_link_speed_target == 1)
371 request = PCIE_PERF_REQ_PECI_GEN2;
372 else
373 request = PCIE_PERF_REQ_PECI_GEN3;
374
375 cypress_pcie_performance_request(rdev, request, false);
376 }
377}
378
379void cypress_notify_link_speed_change_before_state_change(struct radeon_device *rdev)
380{
381 struct radeon_ps *radeon_new_state = rdev->pm.dpm.requested_ps;
382 struct radeon_ps *radeon_current_state = rdev->pm.dpm.current_ps;
383 u32 pcie_link_speed_target = cypress_get_maximum_link_speed(radeon_new_state);
384 u32 pcie_link_speed_current = cypress_get_maximum_link_speed(radeon_current_state);
385 u8 request;
386
387 if (pcie_link_speed_target > pcie_link_speed_current) {
388 if (pcie_link_speed_target == 0)
389 request = PCIE_PERF_REQ_PECI_GEN1;
390 else if (pcie_link_speed_target == 1)
391 request = PCIE_PERF_REQ_PECI_GEN2;
392 else
393 request = PCIE_PERF_REQ_PECI_GEN3;
394
395 cypress_pcie_performance_request(rdev, request, false);
396 }
397}
398
399static int cypress_populate_voltage_value(struct radeon_device *rdev,
400 struct atom_voltage_table *table,
401 u16 value, RV770_SMC_VOLTAGE_VALUE *voltage)
402{
403 unsigned int i;
404
405 for (i = 0; i < table->count; i++) {
406 if (value <= table->entries[i].value) {
407 voltage->index = (u8)i;
408 voltage->value = cpu_to_be16(table->entries[i].value);
409 break;
410 }
411 }
412
413 if (i == table->count)
414 return -EINVAL;
415
416 return 0;
417}
418
419static u8 cypress_get_strobe_mode_settings(struct radeon_device *rdev, u32 mclk)
420{
421 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
422 u8 result = 0;
423 bool strobe_mode = false;
424
425 if (pi->mem_gddr5) {
426 if (mclk <= pi->mclk_strobe_mode_threshold)
427 strobe_mode = true;
428 result = cypress_get_mclk_frequency_ratio(rdev, mclk, strobe_mode);
429
430 if (strobe_mode)
431 result |= SMC_STROBE_ENABLE;
432 }
433
434 return result;
435}
436
437static u32 cypress_map_clkf_to_ibias(struct radeon_device *rdev, u32 clkf)
438{
439 u32 ref_clk = rdev->clock.mpll.reference_freq;
440 u32 vco = clkf * ref_clk;
441
442 /* 100 Mhz ref clk */
443 if (ref_clk == 10000) {
444 if (vco > 500000)
445 return 0xC6;
446 if (vco > 400000)
447 return 0x9D;
448 if (vco > 330000)
449 return 0x6C;
450 if (vco > 250000)
451 return 0x2B;
452 if (vco > 160000)
453 return 0x5B;
454 if (vco > 120000)
455 return 0x0A;
456 return 0x4B;
457 }
458
459 /* 27 Mhz ref clk */
460 if (vco > 250000)
461 return 0x8B;
462 if (vco > 200000)
463 return 0xCC;
464 if (vco > 150000)
465 return 0x9B;
466 return 0x6B;
467}
468
469static int cypress_populate_mclk_value(struct radeon_device *rdev,
470 u32 engine_clock, u32 memory_clock,
471 RV7XX_SMC_MCLK_VALUE *mclk,
472 bool strobe_mode, bool dll_state_on)
473{
474 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
475
476 u32 mpll_ad_func_cntl =
477 pi->clk_regs.rv770.mpll_ad_func_cntl;
478 u32 mpll_ad_func_cntl_2 =
479 pi->clk_regs.rv770.mpll_ad_func_cntl_2;
480 u32 mpll_dq_func_cntl =
481 pi->clk_regs.rv770.mpll_dq_func_cntl;
482 u32 mpll_dq_func_cntl_2 =
483 pi->clk_regs.rv770.mpll_dq_func_cntl_2;
484 u32 mclk_pwrmgt_cntl =
485 pi->clk_regs.rv770.mclk_pwrmgt_cntl;
486 u32 dll_cntl =
487 pi->clk_regs.rv770.dll_cntl;
488 u32 mpll_ss1 = pi->clk_regs.rv770.mpll_ss1;
489 u32 mpll_ss2 = pi->clk_regs.rv770.mpll_ss2;
490 struct atom_clock_dividers dividers;
491 u32 ibias;
492 u32 dll_speed;
493 int ret;
494 u32 mc_seq_misc7;
495
496 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_MEMORY_PLL_PARAM,
497 memory_clock, strobe_mode, &dividers);
498 if (ret)
499 return ret;
500
501 if (!strobe_mode) {
502 mc_seq_misc7 = RREG32(MC_SEQ_MISC7);
503
504 if(mc_seq_misc7 & 0x8000000)
505 dividers.post_div = 1;
506 }
507
508 ibias = cypress_map_clkf_to_ibias(rdev, dividers.whole_fb_div);
509
510 mpll_ad_func_cntl &= ~(CLKR_MASK |
511 YCLK_POST_DIV_MASK |
512 CLKF_MASK |
513 CLKFRAC_MASK |
514 IBIAS_MASK);
515 mpll_ad_func_cntl |= CLKR(dividers.ref_div);
516 mpll_ad_func_cntl |= YCLK_POST_DIV(dividers.post_div);
517 mpll_ad_func_cntl |= CLKF(dividers.whole_fb_div);
518 mpll_ad_func_cntl |= CLKFRAC(dividers.frac_fb_div);
519 mpll_ad_func_cntl |= IBIAS(ibias);
520
521 if (dividers.vco_mode)
522 mpll_ad_func_cntl_2 |= VCO_MODE;
523 else
524 mpll_ad_func_cntl_2 &= ~VCO_MODE;
525
526 if (pi->mem_gddr5) {
527 mpll_dq_func_cntl &= ~(CLKR_MASK |
528 YCLK_POST_DIV_MASK |
529 CLKF_MASK |
530 CLKFRAC_MASK |
531 IBIAS_MASK);
532 mpll_dq_func_cntl |= CLKR(dividers.ref_div);
533 mpll_dq_func_cntl |= YCLK_POST_DIV(dividers.post_div);
534 mpll_dq_func_cntl |= CLKF(dividers.whole_fb_div);
535 mpll_dq_func_cntl |= CLKFRAC(dividers.frac_fb_div);
536 mpll_dq_func_cntl |= IBIAS(ibias);
537
538 if (strobe_mode)
539 mpll_dq_func_cntl &= ~PDNB;
540 else
541 mpll_dq_func_cntl |= PDNB;
542
543 if (dividers.vco_mode)
544 mpll_dq_func_cntl_2 |= VCO_MODE;
545 else
546 mpll_dq_func_cntl_2 &= ~VCO_MODE;
547 }
548
549 if (pi->mclk_ss) {
550 struct radeon_atom_ss ss;
551 u32 vco_freq = memory_clock * dividers.post_div;
552
553 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
554 ASIC_INTERNAL_MEMORY_SS, vco_freq)) {
555 u32 reference_clock = rdev->clock.mpll.reference_freq;
556 u32 decoded_ref = rv740_get_decoded_reference_divider(dividers.ref_div);
557 u32 clk_s = reference_clock * 5 / (decoded_ref * ss.rate);
558 u32 clk_v = ss.percentage *
559 (0x4000 * dividers.whole_fb_div + 0x800 * dividers.frac_fb_div) / (clk_s * 625);
560
561 mpll_ss1 &= ~CLKV_MASK;
562 mpll_ss1 |= CLKV(clk_v);
563
564 mpll_ss2 &= ~CLKS_MASK;
565 mpll_ss2 |= CLKS(clk_s);
566 }
567 }
568
569 dll_speed = rv740_get_dll_speed(pi->mem_gddr5,
570 memory_clock);
571
572 mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK;
573 mclk_pwrmgt_cntl |= DLL_SPEED(dll_speed);
574 if (dll_state_on)
575 mclk_pwrmgt_cntl |= (MRDCKA0_PDNB |
576 MRDCKA1_PDNB |
577 MRDCKB0_PDNB |
578 MRDCKB1_PDNB |
579 MRDCKC0_PDNB |
580 MRDCKC1_PDNB |
581 MRDCKD0_PDNB |
582 MRDCKD1_PDNB);
583 else
584 mclk_pwrmgt_cntl &= ~(MRDCKA0_PDNB |
585 MRDCKA1_PDNB |
586 MRDCKB0_PDNB |
587 MRDCKB1_PDNB |
588 MRDCKC0_PDNB |
589 MRDCKC1_PDNB |
590 MRDCKD0_PDNB |
591 MRDCKD1_PDNB);
592
593 mclk->mclk770.mclk_value = cpu_to_be32(memory_clock);
594 mclk->mclk770.vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl);
595 mclk->mclk770.vMPLL_AD_FUNC_CNTL_2 = cpu_to_be32(mpll_ad_func_cntl_2);
596 mclk->mclk770.vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl);
597 mclk->mclk770.vMPLL_DQ_FUNC_CNTL_2 = cpu_to_be32(mpll_dq_func_cntl_2);
598 mclk->mclk770.vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl);
599 mclk->mclk770.vDLL_CNTL = cpu_to_be32(dll_cntl);
600 mclk->mclk770.vMPLL_SS = cpu_to_be32(mpll_ss1);
601 mclk->mclk770.vMPLL_SS2 = cpu_to_be32(mpll_ss2);
602
603 return 0;
604}
605
606static u8 cypress_get_mclk_frequency_ratio(struct radeon_device *rdev,
607 u32 memory_clock, bool strobe_mode)
608{
609 u8 mc_para_index;
610
611 if (rdev->family >= CHIP_BARTS) {
612 if (strobe_mode) {
613 if (memory_clock < 10000)
614 mc_para_index = 0x00;
615 else if (memory_clock > 47500)
616 mc_para_index = 0x0f;
617 else
618 mc_para_index = (u8)((memory_clock - 10000) / 2500);
619 } else {
620 if (memory_clock < 65000)
621 mc_para_index = 0x00;
622 else if (memory_clock > 135000)
623 mc_para_index = 0x0f;
624 else
625 mc_para_index = (u8)((memory_clock - 60000) / 5000);
626 }
627 } else {
628 if (strobe_mode) {
629 if (memory_clock < 10000)
630 mc_para_index = 0x00;
631 else if (memory_clock > 47500)
632 mc_para_index = 0x0f;
633 else
634 mc_para_index = (u8)((memory_clock - 10000) / 2500);
635 } else {
636 if (memory_clock < 40000)
637 mc_para_index = 0x00;
638 else if (memory_clock > 115000)
639 mc_para_index = 0x0f;
640 else
641 mc_para_index = (u8)((memory_clock - 40000) / 5000);
642 }
643 }
644 return mc_para_index;
645}
646
647static int cypress_populate_mvdd_value(struct radeon_device *rdev,
648 u32 mclk,
649 RV770_SMC_VOLTAGE_VALUE *voltage)
650{
651 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
652 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
653
654 if (!pi->mvdd_control) {
655 voltage->index = eg_pi->mvdd_high_index;
656 voltage->value = cpu_to_be16(MVDD_HIGH_VALUE);
657 return 0;
658 }
659
660 if (mclk <= pi->mvdd_split_frequency) {
661 voltage->index = eg_pi->mvdd_low_index;
662 voltage->value = cpu_to_be16(MVDD_LOW_VALUE);
663 } else {
664 voltage->index = eg_pi->mvdd_high_index;
665 voltage->value = cpu_to_be16(MVDD_HIGH_VALUE);
666 }
667
668 return 0;
669}
670
671int cypress_convert_power_level_to_smc(struct radeon_device *rdev,
672 struct rv7xx_pl *pl,
673 RV770_SMC_HW_PERFORMANCE_LEVEL *level,
674 u8 watermark_level)
675{
676 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
677 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
678 int ret;
679 bool dll_state_on;
680
681 level->gen2PCIE = pi->pcie_gen2 ?
682 ((pl->flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2) ? 1 : 0) : 0;
683 level->gen2XSP = (pl->flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2) ? 1 : 0;
684 level->backbias = (pl->flags & ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE) ? 1 : 0;
685 level->displayWatermark = watermark_level;
686
687 ret = rv740_populate_sclk_value(rdev, pl->sclk, &level->sclk);
688 if (ret)
689 return ret;
690
691 level->mcFlags = 0;
692 if (pi->mclk_stutter_mode_threshold &&
f85392bc
AD		 693 (pl->mclk <= pi->mclk_stutter_mode_threshold) &&
694 !eg_pi->uvd_enabled) {
dc50ba7f
AD		 695 level->mcFlags |= SMC_MC_STUTTER_EN;
696 if (eg_pi->sclk_deep_sleep)
697 level->stateFlags |= PPSMC_STATEFLAG_AUTO_PULSE_SKIP;
698 else
699 level->stateFlags &= ~PPSMC_STATEFLAG_AUTO_PULSE_SKIP;
700 }
701
702 if (pi->mem_gddr5) {
703 if (pl->mclk > pi->mclk_edc_enable_threshold)
704 level->mcFlags |= SMC_MC_EDC_RD_FLAG;
705
706 if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold)
707 level->mcFlags |= SMC_MC_EDC_WR_FLAG;
708
709 level->strobeMode = cypress_get_strobe_mode_settings(rdev, pl->mclk);
710
711 if (level->strobeMode & SMC_STROBE_ENABLE) {
712 if (cypress_get_mclk_frequency_ratio(rdev, pl->mclk, true) >=
713 ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf))
714 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
715 else
716 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
717 } else
718 dll_state_on = eg_pi->dll_default_on;
719
720 ret = cypress_populate_mclk_value(rdev,
721 pl->sclk,
722 pl->mclk,
723 &level->mclk,
724 (level->strobeMode & SMC_STROBE_ENABLE) != 0,
725 dll_state_on);
726 } else {
727 ret = cypress_populate_mclk_value(rdev,
728 pl->sclk,
729 pl->mclk,
730 &level->mclk,
731 true,
732 true);
733 }
734 if (ret)
735 return ret;
736
737 ret = cypress_populate_voltage_value(rdev,
738 &eg_pi->vddc_voltage_table,
739 pl->vddc,
740 &level->vddc);
741 if (ret)
742 return ret;
743
744 if (eg_pi->vddci_control) {
745 ret = cypress_populate_voltage_value(rdev,
746 &eg_pi->vddci_voltage_table,
747 pl->vddci,
748 &level->vddci);
749 if (ret)
750 return ret;
751 }
752
753 ret = cypress_populate_mvdd_value(rdev, pl->mclk, &level->mvdd);
754
755 return ret;
756}
757
758static int cypress_convert_power_state_to_smc(struct radeon_device *rdev,
759 struct radeon_ps *radeon_state,
760 RV770_SMC_SWSTATE *smc_state)
761{
762 struct rv7xx_ps *state = rv770_get_ps(radeon_state);
763 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
764 int ret;
765
766 if (!(radeon_state->caps & ATOM_PPLIB_DISALLOW_ON_DC))
767 smc_state->flags |= PPSMC_SWSTATE_FLAG_DC;
768
769 ret = cypress_convert_power_level_to_smc(rdev,
770 &state->low,
771 &smc_state->levels[0],
772 PPSMC_DISPLAY_WATERMARK_LOW);
773 if (ret)
774 return ret;
775
776 ret = cypress_convert_power_level_to_smc(rdev,
777 &state->medium,
778 &smc_state->levels[1],
779 PPSMC_DISPLAY_WATERMARK_LOW);
780 if (ret)
781 return ret;
782
783 ret = cypress_convert_power_level_to_smc(rdev,
784 &state->high,
785 &smc_state->levels[2],
786 PPSMC_DISPLAY_WATERMARK_HIGH);
787 if (ret)
788 return ret;
789
790 smc_state->levels[0].arbValue = MC_CG_ARB_FREQ_F1;
791 smc_state->levels[1].arbValue = MC_CG_ARB_FREQ_F2;
792 smc_state->levels[2].arbValue = MC_CG_ARB_FREQ_F3;
793
794 if (eg_pi->dynamic_ac_timing) {
795 smc_state->levels[0].ACIndex = 2;
796 smc_state->levels[1].ACIndex = 3;
797 smc_state->levels[2].ACIndex = 4;
798 } else {
799 smc_state->levels[0].ACIndex = 0;
800 smc_state->levels[1].ACIndex = 0;
801 smc_state->levels[2].ACIndex = 0;
802 }
803
804 rv770_populate_smc_sp(rdev, radeon_state, smc_state);
805
806 return rv770_populate_smc_t(rdev, radeon_state, smc_state);
807}
808
809static void cypress_convert_mc_registers(struct evergreen_mc_reg_entry *entry,
810 SMC_Evergreen_MCRegisterSet *data,
811 u32 num_entries, u32 valid_flag)
812{
813 u32 i, j;
814
815 for (i = 0, j = 0; j < num_entries; j++) {
816 if (valid_flag & (1 << j)) {
817 data->value[i] = cpu_to_be32(entry->mc_data[j]);
818 i++;
819 }
820 }
821}
822
823static void cypress_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev,
824 struct rv7xx_pl *pl,
825 SMC_Evergreen_MCRegisterSet *mc_reg_table_data)
826{
827 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
828 u32 i = 0;
829
830 for (i = 0; i < eg_pi->mc_reg_table.num_entries; i++) {
831 if (pl->mclk <=
832 eg_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max)
833 break;
834 }
835
836 if ((i == eg_pi->mc_reg_table.num_entries) && (i > 0))
837 --i;
838
839 cypress_convert_mc_registers(&eg_pi->mc_reg_table.mc_reg_table_entry[i],
840 mc_reg_table_data,
841 eg_pi->mc_reg_table.last,
842 eg_pi->mc_reg_table.valid_flag);
843}
844
845static void cypress_convert_mc_reg_table_to_smc(struct radeon_device *rdev,
846 struct radeon_ps *radeon_state,
847 SMC_Evergreen_MCRegisters *mc_reg_table)
848{
849 struct rv7xx_ps *state = rv770_get_ps(radeon_state);
850
851 cypress_convert_mc_reg_table_entry_to_smc(rdev,
852 &state->low,
853 &mc_reg_table->data[2]);
854 cypress_convert_mc_reg_table_entry_to_smc(rdev,
855 &state->medium,
856 &mc_reg_table->data[3]);
857 cypress_convert_mc_reg_table_entry_to_smc(rdev,
858 &state->high,
859 &mc_reg_table->data[4]);
860}
861
862int cypress_upload_sw_state(struct radeon_device *rdev)
863{
864 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
865 struct radeon_ps *radeon_new_state = rdev->pm.dpm.requested_ps;
866 u16 address = pi->state_table_start +
867 offsetof(RV770_SMC_STATETABLE, driverState);
868 RV770_SMC_SWSTATE state = { 0 };
869 int ret;
870
871 ret = cypress_convert_power_state_to_smc(rdev, radeon_new_state, &state);
872 if (ret)
873 return ret;
874
875 return rv770_copy_bytes_to_smc(rdev, address, (u8 *)&state,
876 sizeof(RV770_SMC_SWSTATE),
877 pi->sram_end);
878}
879
880int cypress_upload_mc_reg_table(struct radeon_device *rdev)
881{
882 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
883 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
884 struct radeon_ps *radeon_new_state = rdev->pm.dpm.requested_ps;
885 SMC_Evergreen_MCRegisters mc_reg_table = { 0 };
886 u16 address;
887
888 cypress_convert_mc_reg_table_to_smc(rdev, radeon_new_state, &mc_reg_table);
889
890 address = eg_pi->mc_reg_table_start +
891 (u16)offsetof(SMC_Evergreen_MCRegisters, data[2]);
892
893 return rv770_copy_bytes_to_smc(rdev, address,
894 (u8 *)&mc_reg_table.data[2],
895 sizeof(SMC_Evergreen_MCRegisterSet) * 3,
896 pi->sram_end);
897}
898
899u32 cypress_calculate_burst_time(struct radeon_device *rdev,
900 u32 engine_clock, u32 memory_clock)
901{
902 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
903 u32 multiplier = pi->mem_gddr5 ? 1 : 2;
904 u32 result = (4 * multiplier * engine_clock) / (memory_clock / 2);
905 u32 burst_time;
906
907 if (result <= 4)
908 burst_time = 0;
909 else if (result < 8)
910 burst_time = result - 4;
911 else {
912 burst_time = result / 2 ;
913 if (burst_time > 18)
914 burst_time = 18;
915 }
916
917 return burst_time;
918}
919
920void cypress_program_memory_timing_parameters(struct radeon_device *rdev)
921{
922 struct radeon_ps *radeon_new_state = rdev->pm.dpm.requested_ps;
923 struct rv7xx_ps *new_state = rv770_get_ps(radeon_new_state);
924 u32 mc_arb_burst_time = RREG32(MC_ARB_BURST_TIME);
925
926 mc_arb_burst_time &= ~(STATE1_MASK | STATE2_MASK | STATE3_MASK);
927
928 mc_arb_burst_time |= STATE1(cypress_calculate_burst_time(rdev,
929 new_state->low.sclk,
930 new_state->low.mclk));
931 mc_arb_burst_time |= STATE2(cypress_calculate_burst_time(rdev,
932 new_state->medium.sclk,
933 new_state->medium.mclk));
934 mc_arb_burst_time |= STATE3(cypress_calculate_burst_time(rdev,
935 new_state->high.sclk,
936 new_state->high.mclk));
937
938 rv730_program_memory_timing_parameters(rdev, radeon_new_state);
939
940 WREG32(MC_ARB_BURST_TIME, mc_arb_burst_time);
941}
942
943static void cypress_populate_mc_reg_addresses(struct radeon_device *rdev,
944 SMC_Evergreen_MCRegisters *mc_reg_table)
945{
946 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
947 u32 i, j;
948
949 for (i = 0, j = 0; j < eg_pi->mc_reg_table.last; j++) {
950 if (eg_pi->mc_reg_table.valid_flag & (1 << j)) {
951 mc_reg_table->address[i].s0 =
952 cpu_to_be16(eg_pi->mc_reg_table.mc_reg_address[j].s0);
953 mc_reg_table->address[i].s1 =
954 cpu_to_be16(eg_pi->mc_reg_table.mc_reg_address[j].s1);
955 i++;
956 }
957 }
958
959 mc_reg_table->last = (u8)i;
960}
961
962static void cypress_set_mc_reg_address_table(struct radeon_device *rdev)
963{
964 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
965 u32 i = 0;
966
967 eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_RAS_TIMING_LP >> 2;
968 eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_RAS_TIMING >> 2;
969 i++;
970
971 eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_CAS_TIMING_LP >> 2;
972 eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_CAS_TIMING >> 2;
973 i++;
974
975 eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_MISC_TIMING_LP >> 2;
976 eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_MISC_TIMING >> 2;
977 i++;
978
979 eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_MISC_TIMING2_LP >> 2;
980 eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_MISC_TIMING2 >> 2;
981 i++;
982
983 eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_RD_CTL_D0_LP >> 2;
984 eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_RD_CTL_D0 >> 2;
985 i++;
986
987 eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_RD_CTL_D1_LP >> 2;
988 eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_RD_CTL_D1 >> 2;
989 i++;
990
991 eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_WR_CTL_D0_LP >> 2;
992 eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_WR_CTL_D0 >> 2;
993 i++;
994
995 eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_WR_CTL_D1_LP >> 2;
996 eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_WR_CTL_D1 >> 2;
997 i++;
998
999 eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
1000 eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_PMG_CMD_EMRS >> 2;
1001 i++;
1002
1003 eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2;
1004 eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_PMG_CMD_MRS >> 2;
1005 i++;
1006
1007 eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
1008 eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_PMG_CMD_MRS1 >> 2;
1009 i++;
1010
1011 eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_MISC1 >> 2;
1012 eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_MISC1 >> 2;
1013 i++;
1014
1015 eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_RESERVE_M >> 2;
1016 eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_RESERVE_M >> 2;
1017 i++;
1018
1019 eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_MISC3 >> 2;
1020 eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_MISC3 >> 2;
1021 i++;
1022
1023 eg_pi->mc_reg_table.last = (u8)i;
1024}
1025
1026static void cypress_retrieve_ac_timing_for_one_entry(struct radeon_device *rdev,
1027 struct evergreen_mc_reg_entry *entry)
1028{
1029 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1030 u32 i;
1031
1032 for (i = 0; i < eg_pi->mc_reg_table.last; i++)
1033 entry->mc_data[i] =
1034 RREG32(eg_pi->mc_reg_table.mc_reg_address[i].s1 << 2);
1035
1036}
1037
1038static void cypress_retrieve_ac_timing_for_all_ranges(struct radeon_device *rdev,
1039 struct atom_memory_clock_range_table *range_table)
1040{
1041 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1042 u32 i, j;
1043
1044 for (i = 0; i < range_table->num_entries; i++) {
1045 eg_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max =
1046 range_table->mclk[i];
1047 radeon_atom_set_ac_timing(rdev, range_table->mclk[i]);
1048 cypress_retrieve_ac_timing_for_one_entry(rdev,
1049 &eg_pi->mc_reg_table.mc_reg_table_entry[i]);
1050 }
1051
1052 eg_pi->mc_reg_table.num_entries = range_table->num_entries;
1053 eg_pi->mc_reg_table.valid_flag = 0;
1054
1055 for (i = 0; i < eg_pi->mc_reg_table.last; i++) {
1056 for (j = 1; j < range_table->num_entries; j++) {
1057 if (eg_pi->mc_reg_table.mc_reg_table_entry[j-1].mc_data[i] !=
1058 eg_pi->mc_reg_table.mc_reg_table_entry[j].mc_data[i]) {
1059 eg_pi->mc_reg_table.valid_flag |= (1 << i);
1060 break;
1061 }
1062 }
1063 }
1064}
1065
1066static int cypress_initialize_mc_reg_table(struct radeon_device *rdev)
1067{
1068 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1069 u8 module_index = rv770_get_memory_module_index(rdev);
1070 struct atom_memory_clock_range_table range_table = { 0 };
1071 int ret;
1072
1073 ret = radeon_atom_get_mclk_range_table(rdev,
1074 pi->mem_gddr5,
1075 module_index, &range_table);
1076 if (ret)
1077 return ret;
1078
1079 cypress_retrieve_ac_timing_for_all_ranges(rdev, &range_table);
1080
1081 return 0;
1082}
1083
1084static void cypress_wait_for_mc_sequencer(struct radeon_device *rdev, u8 value)
1085{
1086 u32 i, j;
1087 u32 channels = 2;
1088
1089 if ((rdev->family == CHIP_CYPRESS) ||
1090 (rdev->family == CHIP_HEMLOCK))
1091 channels = 4;
1092 else if (rdev->family == CHIP_CEDAR)
1093 channels = 1;
1094
1095 for (i = 0; i < channels; i++) {
1096 if ((rdev->family == CHIP_CYPRESS) ||
1097 (rdev->family == CHIP_HEMLOCK)) {
1098 WREG32_P(MC_CONFIG_MCD, MC_RD_ENABLE_MCD(i), ~MC_RD_ENABLE_MCD_MASK);
1099 WREG32_P(MC_CG_CONFIG_MCD, MC_RD_ENABLE_MCD(i), ~MC_RD_ENABLE_MCD_MASK);
1100 } else {
1101 WREG32_P(MC_CONFIG, MC_RD_ENABLE(i), ~MC_RD_ENABLE_MASK);
1102 WREG32_P(MC_CG_CONFIG, MC_RD_ENABLE(i), ~MC_RD_ENABLE_MASK);
1103 }
1104 for (j = 0; j < rdev->usec_timeout; j++) {
1105 if (((RREG32(MC_SEQ_CG) & CG_SEQ_RESP_MASK) >> CG_SEQ_RESP_SHIFT) == value)
1106 break;
1107 udelay(1);
1108 }
1109 }
1110}
1111
1112static void cypress_force_mc_use_s1(struct radeon_device *rdev)
1113{
1114 struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps;
1115 struct rv7xx_ps *boot_state = rv770_get_ps(radeon_boot_state);
1116 u32 strobe_mode;
1117 u32 mc_seq_cg;
1118 int i;
1119
1120 if (RREG32(MC_SEQ_STATUS_M) & PMG_PWRSTATE)
1121 return;
1122
1123 radeon_atom_set_ac_timing(rdev, boot_state->low.mclk);
1124 radeon_mc_wait_for_idle(rdev);
1125
1126 if ((rdev->family == CHIP_CYPRESS) ||
1127 (rdev->family == CHIP_HEMLOCK)) {
1128 WREG32(MC_CONFIG_MCD, 0xf);
1129 WREG32(MC_CG_CONFIG_MCD, 0xf);
1130 } else {
1131 WREG32(MC_CONFIG, 0xf);
1132 WREG32(MC_CG_CONFIG, 0xf);
1133 }
1134
1135 for (i = 0; i < rdev->num_crtc; i++)
1136 radeon_wait_for_vblank(rdev, i);
1137
1138 WREG32(MC_SEQ_CG, MC_CG_SEQ_YCLK_SUSPEND);
1139 cypress_wait_for_mc_sequencer(rdev, MC_CG_SEQ_YCLK_SUSPEND);
1140
1141 strobe_mode = cypress_get_strobe_mode_settings(rdev,
1142 boot_state->low.mclk);
1143
1144 mc_seq_cg = CG_SEQ_REQ(MC_CG_SEQ_DRAMCONF_S1);
1145 mc_seq_cg |= SEQ_CG_RESP(strobe_mode);
1146 WREG32(MC_SEQ_CG, mc_seq_cg);
1147
1148 for (i = 0; i < rdev->usec_timeout; i++) {
1149 if (RREG32(MC_SEQ_STATUS_M) & PMG_PWRSTATE)
1150 break;
1151 udelay(1);
1152 }
1153
1154 mc_seq_cg &= ~CG_SEQ_REQ_MASK;
1155 mc_seq_cg |= CG_SEQ_REQ(MC_CG_SEQ_YCLK_RESUME);
1156 WREG32(MC_SEQ_CG, mc_seq_cg);
1157
1158 cypress_wait_for_mc_sequencer(rdev, MC_CG_SEQ_YCLK_RESUME);
1159}
1160
1161static void cypress_copy_ac_timing_from_s1_to_s0(struct radeon_device *rdev)
1162{
1163 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1164 u32 value;
1165 u32 i;
1166
1167 for (i = 0; i < eg_pi->mc_reg_table.last; i++) {
1168 value = RREG32(eg_pi->mc_reg_table.mc_reg_address[i].s1 << 2);
1169 WREG32(eg_pi->mc_reg_table.mc_reg_address[i].s0 << 2, value);
1170 }
1171}
1172
1173static void cypress_force_mc_use_s0(struct radeon_device *rdev)
1174{
1175 struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps;
1176 struct rv7xx_ps *boot_state = rv770_get_ps(radeon_boot_state);
1177 u32 strobe_mode;
1178 u32 mc_seq_cg;
1179 int i;
1180
1181 cypress_copy_ac_timing_from_s1_to_s0(rdev);
1182 radeon_mc_wait_for_idle(rdev);
1183
1184 if ((rdev->family == CHIP_CYPRESS) ||
1185 (rdev->family == CHIP_HEMLOCK)) {
1186 WREG32(MC_CONFIG_MCD, 0xf);
1187 WREG32(MC_CG_CONFIG_MCD, 0xf);
1188 } else {
1189 WREG32(MC_CONFIG, 0xf);
1190 WREG32(MC_CG_CONFIG, 0xf);
1191 }
1192
1193 for (i = 0; i < rdev->num_crtc; i++)
1194 radeon_wait_for_vblank(rdev, i);
1195
1196 WREG32(MC_SEQ_CG, MC_CG_SEQ_YCLK_SUSPEND);
1197 cypress_wait_for_mc_sequencer(rdev, MC_CG_SEQ_YCLK_SUSPEND);
1198
1199 strobe_mode = cypress_get_strobe_mode_settings(rdev,
1200 boot_state->low.mclk);
1201
1202 mc_seq_cg = CG_SEQ_REQ(MC_CG_SEQ_DRAMCONF_S0);
1203 mc_seq_cg |= SEQ_CG_RESP(strobe_mode);
1204 WREG32(MC_SEQ_CG, mc_seq_cg);
1205
1206 for (i = 0; i < rdev->usec_timeout; i++) {
1207 if (!(RREG32(MC_SEQ_STATUS_M) & PMG_PWRSTATE))
1208 break;
1209 udelay(1);
1210 }
1211
1212 mc_seq_cg &= ~CG_SEQ_REQ_MASK;
1213 mc_seq_cg |= CG_SEQ_REQ(MC_CG_SEQ_YCLK_RESUME);
1214 WREG32(MC_SEQ_CG, mc_seq_cg);
1215
1216 cypress_wait_for_mc_sequencer(rdev, MC_CG_SEQ_YCLK_RESUME);
1217}
1218
1219static int cypress_populate_initial_mvdd_value(struct radeon_device *rdev,
1220 RV770_SMC_VOLTAGE_VALUE *voltage)
1221{
1222 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1223
1224 voltage->index = eg_pi->mvdd_high_index;
1225 voltage->value = cpu_to_be16(MVDD_HIGH_VALUE);
1226
1227 return 0;
1228}
1229
1230int cypress_populate_smc_initial_state(struct radeon_device *rdev,
1231 struct radeon_ps *radeon_initial_state,
1232 RV770_SMC_STATETABLE *table)
1233{
1234 struct rv7xx_ps *initial_state = rv770_get_ps(radeon_initial_state);
1235 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1236 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1237 u32 a_t;
1238
1239 table->initialState.levels[0].mclk.mclk770.vMPLL_AD_FUNC_CNTL =
1240 cpu_to_be32(pi->clk_regs.rv770.mpll_ad_func_cntl);
1241 table->initialState.levels[0].mclk.mclk770.vMPLL_AD_FUNC_CNTL_2 =
1242 cpu_to_be32(pi->clk_regs.rv770.mpll_ad_func_cntl_2);
1243 table->initialState.levels[0].mclk.mclk770.vMPLL_DQ_FUNC_CNTL =
1244 cpu_to_be32(pi->clk_regs.rv770.mpll_dq_func_cntl);
1245 table->initialState.levels[0].mclk.mclk770.vMPLL_DQ_FUNC_CNTL_2 =
1246 cpu_to_be32(pi->clk_regs.rv770.mpll_dq_func_cntl_2);
1247 table->initialState.levels[0].mclk.mclk770.vMCLK_PWRMGT_CNTL =
1248 cpu_to_be32(pi->clk_regs.rv770.mclk_pwrmgt_cntl);
1249 table->initialState.levels[0].mclk.mclk770.vDLL_CNTL =
1250 cpu_to_be32(pi->clk_regs.rv770.dll_cntl);
1251
1252 table->initialState.levels[0].mclk.mclk770.vMPLL_SS =
1253 cpu_to_be32(pi->clk_regs.rv770.mpll_ss1);
1254 table->initialState.levels[0].mclk.mclk770.vMPLL_SS2 =
1255 cpu_to_be32(pi->clk_regs.rv770.mpll_ss2);
1256
1257 table->initialState.levels[0].mclk.mclk770.mclk_value =
1258 cpu_to_be32(initial_state->low.mclk);
1259
1260 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
1261 cpu_to_be32(pi->clk_regs.rv770.cg_spll_func_cntl);
1262 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
1263 cpu_to_be32(pi->clk_regs.rv770.cg_spll_func_cntl_2);
1264 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
1265 cpu_to_be32(pi->clk_regs.rv770.cg_spll_func_cntl_3);
1266 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM =
1267 cpu_to_be32(pi->clk_regs.rv770.cg_spll_spread_spectrum);
1268 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2 =
1269 cpu_to_be32(pi->clk_regs.rv770.cg_spll_spread_spectrum_2);
1270
1271 table->initialState.levels[0].sclk.sclk_value =
1272 cpu_to_be32(initial_state->low.sclk);
1273
1274 table->initialState.levels[0].arbValue = MC_CG_ARB_FREQ_F0;
1275
1276 table->initialState.levels[0].ACIndex = 0;
1277
1278 cypress_populate_voltage_value(rdev,
1279 &eg_pi->vddc_voltage_table,
1280 initial_state->low.vddc,
1281 &table->initialState.levels[0].vddc);
1282
1283 if (eg_pi->vddci_control)
1284 cypress_populate_voltage_value(rdev,
1285 &eg_pi->vddci_voltage_table,
1286 initial_state->low.vddci,
1287 &table->initialState.levels[0].vddci);
1288
1289 cypress_populate_initial_mvdd_value(rdev,
1290 &table->initialState.levels[0].mvdd);
1291
1292 a_t = CG_R(0xffff) | CG_L(0);
1293 table->initialState.levels[0].aT = cpu_to_be32(a_t);
1294
1295 table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp);
1296
1297
1298 if (pi->boot_in_gen2)
1299 table->initialState.levels[0].gen2PCIE = 1;
1300 else
1301 table->initialState.levels[0].gen2PCIE = 0;
1302 if (initial_state->low.flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2)
1303 table->initialState.levels[0].gen2XSP = 1;
1304 else
1305 table->initialState.levels[0].gen2XSP = 0;
1306
1307 if (pi->mem_gddr5) {
1308 table->initialState.levels[0].strobeMode =
1309 cypress_get_strobe_mode_settings(rdev,
1310 initial_state->low.mclk);
1311
1312 if (initial_state->low.mclk > pi->mclk_edc_enable_threshold)
1313 table->initialState.levels[0].mcFlags = SMC_MC_EDC_RD_FLAG | SMC_MC_EDC_WR_FLAG;
1314 else
1315 table->initialState.levels[0].mcFlags = 0;
1316 }
1317
1318 table->initialState.levels[1] = table->initialState.levels[0];
1319 table->initialState.levels[2] = table->initialState.levels[0];
1320
1321 table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC;
1322
1323 return 0;
1324}
1325
1326int cypress_populate_smc_acpi_state(struct radeon_device *rdev,
1327 RV770_SMC_STATETABLE *table)
1328{
1329 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1330 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1331 u32 mpll_ad_func_cntl =
1332 pi->clk_regs.rv770.mpll_ad_func_cntl;
1333 u32 mpll_ad_func_cntl_2 =
1334 pi->clk_regs.rv770.mpll_ad_func_cntl_2;
1335 u32 mpll_dq_func_cntl =
1336 pi->clk_regs.rv770.mpll_dq_func_cntl;
1337 u32 mpll_dq_func_cntl_2 =
1338 pi->clk_regs.rv770.mpll_dq_func_cntl_2;
1339 u32 spll_func_cntl =
1340 pi->clk_regs.rv770.cg_spll_func_cntl;
1341 u32 spll_func_cntl_2 =
1342 pi->clk_regs.rv770.cg_spll_func_cntl_2;
1343 u32 spll_func_cntl_3 =
1344 pi->clk_regs.rv770.cg_spll_func_cntl_3;
1345 u32 mclk_pwrmgt_cntl =
1346 pi->clk_regs.rv770.mclk_pwrmgt_cntl;
1347 u32 dll_cntl =
1348 pi->clk_regs.rv770.dll_cntl;
1349
1350 table->ACPIState = table->initialState;
1351
1352 table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC;
1353
1354 if (pi->acpi_vddc) {
1355 cypress_populate_voltage_value(rdev,
1356 &eg_pi->vddc_voltage_table,
1357 pi->acpi_vddc,
1358 &table->ACPIState.levels[0].vddc);
1359 if (pi->pcie_gen2) {
1360 if (pi->acpi_pcie_gen2)
1361 table->ACPIState.levels[0].gen2PCIE = 1;
1362 else
1363 table->ACPIState.levels[0].gen2PCIE = 0;
1364 } else
1365 table->ACPIState.levels[0].gen2PCIE = 0;
1366 if (pi->acpi_pcie_gen2)
1367 table->ACPIState.levels[0].gen2XSP = 1;
1368 else
1369 table->ACPIState.levels[0].gen2XSP = 0;
1370 } else {
1371 cypress_populate_voltage_value(rdev,
1372 &eg_pi->vddc_voltage_table,
1373 pi->min_vddc_in_table,
1374 &table->ACPIState.levels[0].vddc);
1375 table->ACPIState.levels[0].gen2PCIE = 0;
1376 }
1377
1378 if (eg_pi->acpi_vddci) {
1379 if (eg_pi->vddci_control) {
1380 cypress_populate_voltage_value(rdev,
1381 &eg_pi->vddci_voltage_table,
1382 eg_pi->acpi_vddci,
1383 &table->ACPIState.levels[0].vddci);
1384 }
1385 }
1386
1387 mpll_ad_func_cntl &= ~PDNB;
1388
1389 mpll_ad_func_cntl_2 |= BIAS_GEN_PDNB | RESET_EN;
1390
1391 if (pi->mem_gddr5)
1392 mpll_dq_func_cntl &= ~PDNB;
1393 mpll_dq_func_cntl_2 |= BIAS_GEN_PDNB | RESET_EN | BYPASS;
1394
1395 mclk_pwrmgt_cntl |= (MRDCKA0_RESET |
1396 MRDCKA1_RESET |
1397 MRDCKB0_RESET |
1398 MRDCKB1_RESET |
1399 MRDCKC0_RESET |
1400 MRDCKC1_RESET |
1401 MRDCKD0_RESET |
1402 MRDCKD1_RESET);
1403
1404 mclk_pwrmgt_cntl &= ~(MRDCKA0_PDNB |
1405 MRDCKA1_PDNB |
1406 MRDCKB0_PDNB |
1407 MRDCKB1_PDNB |
1408 MRDCKC0_PDNB |
1409 MRDCKC1_PDNB |
1410 MRDCKD0_PDNB |
1411 MRDCKD1_PDNB);
1412
1413 dll_cntl |= (MRDCKA0_BYPASS |
1414 MRDCKA1_BYPASS |
1415 MRDCKB0_BYPASS |
1416 MRDCKB1_BYPASS |
1417 MRDCKC0_BYPASS |
1418 MRDCKC1_BYPASS |
1419 MRDCKD0_BYPASS |
1420 MRDCKD1_BYPASS);
1421
1422 /* evergreen only */
1423 if (rdev->family <= CHIP_HEMLOCK)
1424 spll_func_cntl |= SPLL_RESET | SPLL_SLEEP | SPLL_BYPASS_EN;
1425
1426 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
1427 spll_func_cntl_2 |= SCLK_MUX_SEL(4);
1428
1429 table->ACPIState.levels[0].mclk.mclk770.vMPLL_AD_FUNC_CNTL =
1430 cpu_to_be32(mpll_ad_func_cntl);
1431 table->ACPIState.levels[0].mclk.mclk770.vMPLL_AD_FUNC_CNTL_2 =
1432 cpu_to_be32(mpll_ad_func_cntl_2);
1433 table->ACPIState.levels[0].mclk.mclk770.vMPLL_DQ_FUNC_CNTL =
1434 cpu_to_be32(mpll_dq_func_cntl);
1435 table->ACPIState.levels[0].mclk.mclk770.vMPLL_DQ_FUNC_CNTL_2 =
1436 cpu_to_be32(mpll_dq_func_cntl_2);
1437 table->ACPIState.levels[0].mclk.mclk770.vMCLK_PWRMGT_CNTL =
1438 cpu_to_be32(mclk_pwrmgt_cntl);
1439 table->ACPIState.levels[0].mclk.mclk770.vDLL_CNTL = cpu_to_be32(dll_cntl);
1440
1441 table->ACPIState.levels[0].mclk.mclk770.mclk_value = 0;
1442
1443 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
1444 cpu_to_be32(spll_func_cntl);
1445 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
1446 cpu_to_be32(spll_func_cntl_2);
1447 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
1448 cpu_to_be32(spll_func_cntl_3);
1449
1450 table->ACPIState.levels[0].sclk.sclk_value = 0;
1451
1452 cypress_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd);
1453
1454 if (eg_pi->dynamic_ac_timing)
1455 table->ACPIState.levels[0].ACIndex = 1;
1456
1457 table->ACPIState.levels[1] = table->ACPIState.levels[0];
1458 table->ACPIState.levels[2] = table->ACPIState.levels[0];
1459
1460 return 0;
1461}
1462
1463static void cypress_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev,
1464 struct atom_voltage_table *voltage_table)
1465{
1466 unsigned int i, diff;
1467
1468 if (voltage_table->count <= MAX_NO_VREG_STEPS)
1469 return;
1470
1471 diff = voltage_table->count - MAX_NO_VREG_STEPS;
1472
1473 for (i= 0; i < MAX_NO_VREG_STEPS; i++)
1474 voltage_table->entries[i] = voltage_table->entries[i + diff];
1475
1476 voltage_table->count = MAX_NO_VREG_STEPS;
1477}
1478
1479int cypress_construct_voltage_tables(struct radeon_device *rdev)
1480{
1481 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1482 int ret;
1483
1484 ret = radeon_atom_get_voltage_table(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
1485 &eg_pi->vddc_voltage_table);
1486 if (ret)
1487 return ret;
1488
1489 if (eg_pi->vddc_voltage_table.count > MAX_NO_VREG_STEPS)
1490 cypress_trim_voltage_table_to_fit_state_table(rdev,
1491 &eg_pi->vddc_voltage_table);
1492
1493 if (eg_pi->vddci_control) {
1494 ret = radeon_atom_get_voltage_table(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI,
1495 &eg_pi->vddci_voltage_table);
1496 if (ret)
1497 return ret;
1498
1499 if (eg_pi->vddci_voltage_table.count > MAX_NO_VREG_STEPS)
1500 cypress_trim_voltage_table_to_fit_state_table(rdev,
1501 &eg_pi->vddci_voltage_table);
1502 }
1503
1504 return 0;
1505}
1506
1507static void cypress_populate_smc_voltage_table(struct radeon_device *rdev,
1508 struct atom_voltage_table *voltage_table,
1509 RV770_SMC_STATETABLE *table)
1510{
1511 unsigned int i;
1512
1513 for (i = 0; i < voltage_table->count; i++) {
1514 table->highSMIO[i] = 0;
1515 table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low);
1516 }
1517}
1518
1519int cypress_populate_smc_voltage_tables(struct radeon_device *rdev,
1520 RV770_SMC_STATETABLE *table)
1521{
1522 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1523 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1524 unsigned char i;
1525
1526 if (eg_pi->vddc_voltage_table.count) {
1527 cypress_populate_smc_voltage_table(rdev,
1528 &eg_pi->vddc_voltage_table,
1529 table);
1530
1531 table->voltageMaskTable.highMask[RV770_SMC_VOLTAGEMASK_VDDC] = 0;
1532 table->voltageMaskTable.lowMask[RV770_SMC_VOLTAGEMASK_VDDC] =
1533 cpu_to_be32(eg_pi->vddc_voltage_table.mask_low);
1534
1535 for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) {
1536 if (pi->max_vddc_in_table <=
1537 eg_pi->vddc_voltage_table.entries[i].value) {
1538 table->maxVDDCIndexInPPTable = i;
1539 break;
1540 }
1541 }
1542 }
1543
1544 if (eg_pi->vddci_voltage_table.count) {
1545 cypress_populate_smc_voltage_table(rdev,
1546 &eg_pi->vddci_voltage_table,
1547 table);
1548
1549 table->voltageMaskTable.highMask[RV770_SMC_VOLTAGEMASK_VDDCI] = 0;
1550 table->voltageMaskTable.lowMask[RV770_SMC_VOLTAGEMASK_VDDCI] =
1551 cpu_to_be32(eg_pi->vddc_voltage_table.mask_low);
1552 }
1553
1554 return 0;
1555}
1556
1557static u32 cypress_get_mclk_split_point(struct atom_memory_info *memory_info)
1558{
1559 if ((memory_info->mem_type == MEM_TYPE_GDDR3) ||
1560 (memory_info->mem_type == MEM_TYPE_DDR3))
1561 return 30000;
1562
1563 return 0;
1564}
1565
1566int cypress_get_mvdd_configuration(struct radeon_device *rdev)
1567{
1568 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1569 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1570 u8 module_index;
1571 struct atom_memory_info memory_info;
1572 u32 tmp = RREG32(GENERAL_PWRMGT);
1573
1574 if (!(tmp & BACKBIAS_PAD_EN)) {
1575 eg_pi->mvdd_high_index = 0;
1576 eg_pi->mvdd_low_index = 1;
1577 pi->mvdd_control = false;
1578 return 0;
1579 }
1580
1581 if (tmp & BACKBIAS_VALUE)
1582 eg_pi->mvdd_high_index = 1;
1583 else
1584 eg_pi->mvdd_high_index = 0;
1585
1586 eg_pi->mvdd_low_index =
1587 (eg_pi->mvdd_high_index == 0) ? 1 : 0;
1588
1589 module_index = rv770_get_memory_module_index(rdev);
1590
1591 if (radeon_atom_get_memory_info(rdev, module_index, &memory_info)) {
1592 pi->mvdd_control = false;
1593 return 0;
1594 }
1595
1596 pi->mvdd_split_frequency =
1597 cypress_get_mclk_split_point(&memory_info);
1598
1599 if (pi->mvdd_split_frequency == 0) {
1600 pi->mvdd_control = false;
1601 return 0;
1602 }
1603
1604 return 0;
1605}
1606
1607static int cypress_init_smc_table(struct radeon_device *rdev)
1608{
1609 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1610 struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps;
1611 RV770_SMC_STATETABLE *table = &pi->smc_statetable;
1612 int ret;
1613
1614 memset(table, 0, sizeof(RV770_SMC_STATETABLE));
1615
1616 cypress_populate_smc_voltage_tables(rdev, table);
1617
1618 switch (rdev->pm.int_thermal_type) {
1619 case THERMAL_TYPE_EVERGREEN:
1620 case THERMAL_TYPE_EMC2103_WITH_INTERNAL:
1621 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL;
1622 break;
1623 case THERMAL_TYPE_NONE:
1624 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE;
1625 break;
1626 default:
1627 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL;
1628 break;
1629 }
1630
1631 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)
1632 table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
1633
1634 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT)
1635 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT;
1636
1637 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
1638 table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
1639
1640 if (pi->mem_gddr5)
1641 table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
1642
1643 ret = cypress_populate_smc_initial_state(rdev, radeon_boot_state, table);
1644 if (ret)
1645 return ret;
1646
1647 ret = cypress_populate_smc_acpi_state(rdev, table);
1648 if (ret)
1649 return ret;
1650
1651 table->driverState = table->initialState;
1652
1653 return rv770_copy_bytes_to_smc(rdev,
1654 pi->state_table_start,
1655 (u8 *)table, sizeof(RV770_SMC_STATETABLE),
1656 pi->sram_end);
1657}
1658
1659int cypress_populate_mc_reg_table(struct radeon_device *rdev)
1660{
1661 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1662 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1663 struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps;
1664 struct rv7xx_ps *boot_state = rv770_get_ps(radeon_boot_state);
1665 SMC_Evergreen_MCRegisters mc_reg_table = { 0 };
1666
1667 rv770_write_smc_soft_register(rdev,
1668 RV770_SMC_SOFT_REGISTER_seq_index, 1);
1669
1670 cypress_populate_mc_reg_addresses(rdev, &mc_reg_table);
1671
1672 cypress_convert_mc_reg_table_entry_to_smc(rdev,
1673 &boot_state->low,
1674 &mc_reg_table.data[0]);
1675
1676 cypress_convert_mc_registers(&eg_pi->mc_reg_table.mc_reg_table_entry[0],
1677 &mc_reg_table.data[1], eg_pi->mc_reg_table.last,
1678 eg_pi->mc_reg_table.valid_flag);
1679
1680 cypress_convert_mc_reg_table_to_smc(rdev, radeon_boot_state, &mc_reg_table);
1681
1682 return rv770_copy_bytes_to_smc(rdev, eg_pi->mc_reg_table_start,
1683 (u8 *)&mc_reg_table, sizeof(SMC_Evergreen_MCRegisters),
1684 pi->sram_end);
1685}
1686
1687int cypress_get_table_locations(struct radeon_device *rdev)
1688{
1689 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1690 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1691 u32 tmp;
1692 int ret;
1693
1694 ret = rv770_read_smc_sram_dword(rdev,
1695 EVERGREEN_SMC_FIRMWARE_HEADER_LOCATION +
1696 EVERGREEN_SMC_FIRMWARE_HEADER_stateTable,
1697 &tmp, pi->sram_end);
1698 if (ret)
1699 return ret;
1700
1701 pi->state_table_start = (u16)tmp;
1702
1703 ret = rv770_read_smc_sram_dword(rdev,
1704 EVERGREEN_SMC_FIRMWARE_HEADER_LOCATION +
1705 EVERGREEN_SMC_FIRMWARE_HEADER_softRegisters,
1706 &tmp, pi->sram_end);
1707 if (ret)
1708 return ret;
1709
1710 pi->soft_regs_start = (u16)tmp;
1711
1712 ret = rv770_read_smc_sram_dword(rdev,
1713 EVERGREEN_SMC_FIRMWARE_HEADER_LOCATION +
1714 EVERGREEN_SMC_FIRMWARE_HEADER_mcRegisterTable,
1715 &tmp, pi->sram_end);
1716 if (ret)
1717 return ret;
1718
1719 eg_pi->mc_reg_table_start = (u16)tmp;
1720
1721 return 0;
1722}
1723
1724void cypress_enable_display_gap(struct radeon_device *rdev)
1725{
1726 u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);
1727
1728 tmp &= ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
1729 tmp |= (DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE) |
1730 DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE));
1731
1732 tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK);
1733 tmp |= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK) |
1734 DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE));
1735 WREG32(CG_DISPLAY_GAP_CNTL, tmp);
1736}
1737
1738static void cypress_program_display_gap(struct radeon_device *rdev)
1739{
1740 u32 tmp, pipe;
1741 int i;
1742
1743 tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
1744 if (rdev->pm.dpm.new_active_crtc_count > 0)
1745 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
1746 else
1747 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE);
1748
1749 if (rdev->pm.dpm.new_active_crtc_count > 1)
1750 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
1751 else
1752 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE);
1753
1754 WREG32(CG_DISPLAY_GAP_CNTL, tmp);
1755
1756 tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG);
1757 pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT;
1758
1759 if ((rdev->pm.dpm.new_active_crtc_count > 0) &&
1760 (!(rdev->pm.dpm.new_active_crtcs & (1 << pipe)))) {
1761 /* find the first active crtc */
1762 for (i = 0; i < rdev->num_crtc; i++) {
1763 if (rdev->pm.dpm.new_active_crtcs & (1 << i))
1764 break;
1765 }
1766 if (i == rdev->num_crtc)
1767 pipe = 0;
1768 else
1769 pipe = i;
1770
1771 tmp &= ~DCCG_DISP1_SLOW_SELECT_MASK;
1772 tmp |= DCCG_DISP1_SLOW_SELECT(pipe);
1773 WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp);
1774 }
1775
1776 cypress_notify_smc_display_change(rdev, rdev->pm.dpm.new_active_crtc_count > 0);
1777}
1778
1779void cypress_dpm_setup_asic(struct radeon_device *rdev)
1780{
1781 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1782
1783 rv740_read_clock_registers(rdev);
1784 rv770_read_voltage_smio_registers(rdev);
1785 rv770_get_max_vddc(rdev);
1786 rv770_get_memory_type(rdev);
1787
1788 if (eg_pi->pcie_performance_request)
1789 eg_pi->pcie_performance_request_registered = false;
1790
1791 if (eg_pi->pcie_performance_request)
1792 cypress_advertise_gen2_capability(rdev);
1793
1794 rv770_get_pcie_gen2_status(rdev);
1795
1796 rv770_enable_acpi_pm(rdev);
1797}
1798
1799int cypress_dpm_enable(struct radeon_device *rdev)
1800{
1801 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1802 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1803
1804 if (pi->gfx_clock_gating)
1805 rv770_restore_cgcg(rdev);
1806
1807 if (rv770_dpm_enabled(rdev))
1808 return -EINVAL;
1809
1810 if (pi->voltage_control) {
1811 rv770_enable_voltage_control(rdev, true);
1812 cypress_construct_voltage_tables(rdev);
1813 }
1814
1815 if (pi->mvdd_control)
1816 cypress_get_mvdd_configuration(rdev);
1817
1818 if (eg_pi->dynamic_ac_timing) {
1819 cypress_set_mc_reg_address_table(rdev);
1820 cypress_force_mc_use_s0(rdev);
1821 cypress_initialize_mc_reg_table(rdev);
1822 cypress_force_mc_use_s1(rdev);
1823 }
1824
1825 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_BACKBIAS)
1826 rv770_enable_backbias(rdev, true);
1827
1828 if (pi->dynamic_ss)
1829 cypress_enable_spread_spectrum(rdev, true);
1830
1831 if (pi->thermal_protection)
1832 rv770_enable_thermal_protection(rdev, true);
1833
1834 rv770_setup_bsp(rdev);
1835 rv770_program_git(rdev);
1836 rv770_program_tp(rdev);
1837 rv770_program_tpp(rdev);
1838 rv770_program_sstp(rdev);
1839 rv770_program_engine_speed_parameters(rdev);
1840 cypress_enable_display_gap(rdev);
1841 rv770_program_vc(rdev);
1842
1843 if (pi->dynamic_pcie_gen2)
1844 cypress_enable_dynamic_pcie_gen2(rdev, true);
1845
1846 if (rv770_upload_firmware(rdev))
1847 return -EINVAL;
1848
1849 cypress_get_table_locations(rdev);
1850
1851 if (cypress_init_smc_table(rdev))
1852 return -EINVAL;
1853
1854 if (eg_pi->dynamic_ac_timing)
1855 cypress_populate_mc_reg_table(rdev);
1856
1857 cypress_program_response_times(rdev);
1858
1859 r7xx_start_smc(rdev);
1860
1861 cypress_notify_smc_display_change(rdev, false);
1862
1863 cypress_enable_sclk_control(rdev, true);
1864
1865 if (eg_pi->memory_transition)
1866 cypress_enable_mclk_control(rdev, true);
1867
1868 cypress_start_dpm(rdev);
1869
1870 if (pi->gfx_clock_gating)
1871 cypress_gfx_clock_gating_enable(rdev, true);
1872
1873 if (pi->mg_clock_gating)
1874 cypress_mg_clock_gating_enable(rdev, true);
1875
1876 if (rdev->irq.installed &&
1877 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
1878 PPSMC_Result result;
1879
1880 rv770_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
1881 rdev->irq.dpm_thermal = true;
1882 radeon_irq_set(rdev);
1883 result = rv770_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt);
1884
1885 if (result != PPSMC_Result_OK)
1886 DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
1887 }
1888
1889 rv770_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
1890
1891 return 0;
1892}
1893
1894void cypress_dpm_disable(struct radeon_device *rdev)
1895{
1896 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1897 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1898
1899 if (!rv770_dpm_enabled(rdev))
1900 return;
1901
1902 rv770_clear_vc(rdev);
1903
1904 if (pi->thermal_protection)
1905 rv770_enable_thermal_protection(rdev, false);
1906
1907 if (pi->dynamic_pcie_gen2)
1908 cypress_enable_dynamic_pcie_gen2(rdev, false);
1909
1910 if (rdev->irq.installed &&
1911 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
1912 rdev->irq.dpm_thermal = false;
1913 radeon_irq_set(rdev);
1914 }
1915
1916 if (pi->gfx_clock_gating)
1917 cypress_gfx_clock_gating_enable(rdev, false);
1918
1919 if (pi->mg_clock_gating)
1920 cypress_mg_clock_gating_enable(rdev, false);
1921
1922 rv770_stop_dpm(rdev);
1923 r7xx_stop_smc(rdev);
1924
1925 cypress_enable_spread_spectrum(rdev, false);
1926
1927 if (eg_pi->dynamic_ac_timing)
1928 cypress_force_mc_use_s1(rdev);
1929
1930 rv770_reset_smio_status(rdev);
1931}
1932
1933int cypress_dpm_set_power_state(struct radeon_device *rdev)
1934{
1935 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1936
1937 rv770_restrict_performance_levels_before_switch(rdev);
1938
1939 if (eg_pi->pcie_performance_request)
1940 cypress_notify_link_speed_change_before_state_change(rdev);
1941
f85392bc 1942 rv770_set_uvd_clock_before_set_eng_clock(rdev);
dc50ba7f
AD		 1943 rv770_halt_smc(rdev);
1944 cypress_upload_sw_state(rdev);
1945
1946 if (eg_pi->dynamic_ac_timing)
1947 cypress_upload_mc_reg_table(rdev);
1948
1949 cypress_program_memory_timing_parameters(rdev);
1950
1951 rv770_resume_smc(rdev);
1952 rv770_set_sw_state(rdev);
f85392bc 1953 rv770_set_uvd_clock_after_set_eng_clock(rdev);
dc50ba7f
AD		 1954
1955 if (eg_pi->pcie_performance_request)
1956 cypress_notify_link_speed_change_after_state_change(rdev);
1957
1958 rv770_unrestrict_performance_levels_after_switch(rdev);
1959
1960 return 0;
1961}
1962
1963void cypress_dpm_reset_asic(struct radeon_device *rdev)
1964{
1965 rv770_restrict_performance_levels_before_switch(rdev);
1966 rv770_set_boot_state(rdev);
1967}
1968
1969void cypress_dpm_display_configuration_changed(struct radeon_device *rdev)
1970{
1971 cypress_program_display_gap(rdev);
1972}
1973
1974int cypress_dpm_init(struct radeon_device *rdev)
1975{
1976 struct rv7xx_power_info *pi;
1977 struct evergreen_power_info *eg_pi;
1978 int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
1979 uint16_t data_offset, size;
1980 uint8_t frev, crev;
1981 struct atom_clock_dividers dividers;
1982 int ret;
1983
1984 eg_pi = kzalloc(sizeof(struct evergreen_power_info), GFP_KERNEL);
1985 if (eg_pi == NULL)
1986 return -ENOMEM;
1987 rdev->pm.dpm.priv = eg_pi;
1988 pi = &eg_pi->rv7xx;
1989
1990 rv770_get_max_vddc(rdev);
1991
1992 eg_pi->ulv.supported = false;
1993 pi->acpi_vddc = 0;
1994 eg_pi->acpi_vddci = 0;
1995 pi->min_vddc_in_table = 0;
1996 pi->max_vddc_in_table = 0;
1997
1998 ret = rv7xx_parse_power_table(rdev);
1999 if (ret)
2000 return ret;
2001
2002 if (rdev->pm.dpm.voltage_response_time == 0)
2003 rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT;
2004 if (rdev->pm.dpm.backbias_response_time == 0)
2005 rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT;
2006
2007 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
2008 0, false, &dividers);
2009 if (ret)
2010 pi->ref_div = dividers.ref_div + 1;
2011 else
2012 pi->ref_div = R600_REFERENCEDIVIDER_DFLT;
2013
2014 pi->mclk_strobe_mode_threshold = 40000;
2015 pi->mclk_edc_enable_threshold = 40000;
2016 eg_pi->mclk_edc_wr_enable_threshold = 40000;
2017
f85392bc
AD		 2018 pi->rlp = RV770_RLP_DFLT;
2019 pi->rmp = RV770_RMP_DFLT;
2020 pi->lhp = RV770_LHP_DFLT;
2021 pi->lmp = RV770_LMP_DFLT;
2022
dc50ba7f
AD		 2023 pi->voltage_control =
2024 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC);
2025
2026 pi->mvdd_control =
2027 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_MVDDC);
2028
2029 eg_pi->vddci_control =
2030 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI);
2031
2032 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
2033 &frev, &crev, &data_offset)) {
2034 pi->sclk_ss = true;
2035 pi->mclk_ss = true;
2036 pi->dynamic_ss = true;
2037 } else {
2038 pi->sclk_ss = false;
2039 pi->mclk_ss = false;
2040 pi->dynamic_ss = true;
2041 }
2042
2043 pi->asi = RV770_ASI_DFLT;
2044 pi->pasi = CYPRESS_HASI_DFLT;
2045 pi->vrc = CYPRESS_VRC_DFLT;
2046
2047 pi->power_gating = false;
2048
2049 if ((rdev->family == CHIP_CYPRESS) ||
2050 (rdev->family == CHIP_HEMLOCK))
2051 pi->gfx_clock_gating = false;
2052 else
2053 pi->gfx_clock_gating = true;
2054
2055 pi->mg_clock_gating = true;
2056 pi->mgcgtssm = true;
2057 eg_pi->ls_clock_gating = false;
2058 eg_pi->sclk_deep_sleep = false;
2059
2060 pi->dynamic_pcie_gen2 = true;
2061
2062 if (pi->gfx_clock_gating &&
2063 (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE))
2064 pi->thermal_protection = true;
2065 else
2066 pi->thermal_protection = false;
2067
2068 pi->display_gap = true;
2069
2070 if (rdev->flags & RADEON_IS_MOBILITY)
2071 pi->dcodt = true;
2072 else
2073 pi->dcodt = false;
2074
2075 pi->ulps = true;
2076
2077 eg_pi->dynamic_ac_timing = true;
2078 eg_pi->abm = true;
2079 eg_pi->mcls = true;
2080 eg_pi->light_sleep = true;
2081 eg_pi->memory_transition = true;
2082#if defined(CONFIG_ACPI)
2083 eg_pi->pcie_performance_request =
2084 radeon_acpi_is_pcie_performance_request_supported(rdev);
2085#else
2086 eg_pi->pcie_performance_request = false;
2087#endif
2088
2089 if ((rdev->family == CHIP_CYPRESS) ||
2090 (rdev->family == CHIP_HEMLOCK) ||
2091 (rdev->family == CHIP_JUNIPER))
2092 eg_pi->dll_default_on = true;
2093 else
2094 eg_pi->dll_default_on = false;
2095
2096 eg_pi->sclk_deep_sleep = false;
2097 pi->mclk_stutter_mode_threshold = 0;
2098
2099 pi->sram_end = SMC_RAM_END;
2100
2101 return 0;
2102}
2103
2104void cypress_dpm_fini(struct radeon_device *rdev)
2105{
2106 int i;
2107
2108 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
2109 kfree(rdev->pm.dpm.ps[i].ps_priv);
2110 }
2111 kfree(rdev->pm.dpm.ps);
2112 kfree(rdev->pm.dpm.priv);
2113}
Linux kernel - Deliverables
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