[deliverable/linux.git] / drivers / gpu / drm / radeon / dce3_1_afmt.c

/*
 * Copyright 2013 Advanced Micro Devices, Inc.
 * Copyright 2014 Rafał Miłecki
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 */
#include <linux/hdmi.h>
#include <drm/drmP.h>
#include "radeon.h"
#include "radeon_asic.h"
#include "radeon_audio.h"
#include "r600d.h"

void dce3_2_afmt_hdmi_write_speaker_allocation(struct drm_encoder *encoder,
	u8 *sadb, int sad_count)
{
	struct radeon_device *rdev = encoder->dev->dev_private;
	u32 tmp;

	/* program the speaker allocation */
	tmp = RREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER);
	tmp &= ~(DP_CONNECTION | SPEAKER_ALLOCATION_MASK);
	/* set HDMI mode */
	tmp |= HDMI_CONNECTION;
	if (sad_count)
		tmp |= SPEAKER_ALLOCATION(sadb[0]);
	else
		tmp |= SPEAKER_ALLOCATION(5); /* stereo */
	WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp);
}

void dce3_2_afmt_dp_write_speaker_allocation(struct drm_encoder *encoder,
	u8 *sadb, int sad_count)
{
	struct radeon_device *rdev = encoder->dev->dev_private;
	u32 tmp;

	/* program the speaker allocation */
	tmp = RREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER);
	tmp &= ~(HDMI_CONNECTION | SPEAKER_ALLOCATION_MASK);
	/* set DP mode */
	tmp |= DP_CONNECTION;
	if (sad_count)
		tmp |= SPEAKER_ALLOCATION(sadb[0]);
	else
		tmp |= SPEAKER_ALLOCATION(5); /* stereo */
	WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp);
}

void dce3_2_afmt_write_sad_regs(struct drm_encoder *encoder,
	struct cea_sad *sads, int sad_count)
{
	int i;
	struct radeon_device *rdev = encoder->dev->dev_private;
	static const u16 eld_reg_to_type[][2] = {
		{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
		{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
		{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
		{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
		{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
		{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
		{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
		{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
		{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
		{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
		{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
		{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
	};

	for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
		u32 value = 0;
		u8 stereo_freqs = 0;
		int max_channels = -1;
		int j;

		for (j = 0; j < sad_count; j++) {
			struct cea_sad *sad = &sads[j];

			if (sad->format == eld_reg_to_type[i][1]) {
				if (sad->channels > max_channels) {
					value = MAX_CHANNELS(sad->channels) |
						DESCRIPTOR_BYTE_2(sad->byte2) |
						SUPPORTED_FREQUENCIES(sad->freq);
					max_channels = sad->channels;
				}

				if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
					stereo_freqs |= sad->freq;
				else
					break;
			}
		}

		value |= SUPPORTED_FREQUENCIES_STEREO(stereo_freqs);

		WREG32_ENDPOINT(0, eld_reg_to_type[i][0], value);
	}
}

void dce3_2_audio_set_dto(struct radeon_device *rdev,
	struct radeon_crtc *crtc, unsigned int clock)
{
	struct radeon_encoder *radeon_encoder;
	struct radeon_encoder_atom_dig *dig;
	unsigned int max_ratio = clock / 24000;
	u32 dto_phase;
	u32 wallclock_ratio;
	u32 dto_cntl;

	if (!crtc)
		return;

	radeon_encoder = to_radeon_encoder(crtc->encoder);
	dig = radeon_encoder->enc_priv;

	if (!dig)
		return;

	if (max_ratio >= 8) {
		dto_phase = 192 * 1000;
		wallclock_ratio = 3;
	} else if (max_ratio >= 4) {
		dto_phase = 96 * 1000;
		wallclock_ratio = 2;
	} else if (max_ratio >= 2) {
		dto_phase = 48 * 1000;
		wallclock_ratio = 1;
	} else {
		dto_phase = 24 * 1000;
		wallclock_ratio = 0;
	}

	/* Express [24MHz / target pixel clock] as an exact rational
	 * number (coefficient of two integer numbers.  DCCG_AUDIO_DTOx_PHASE
	 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
	 */
	if (dig->dig_encoder == 0) {
		dto_cntl = RREG32(DCCG_AUDIO_DTO0_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK;
		dto_cntl |= DCCG_AUDIO_DTO_WALLCLOCK_RATIO(wallclock_ratio);
		WREG32(DCCG_AUDIO_DTO0_CNTL, dto_cntl);
		WREG32(DCCG_AUDIO_DTO0_PHASE, dto_phase);
		WREG32(DCCG_AUDIO_DTO0_MODULE, clock);
		WREG32(DCCG_AUDIO_DTO_SELECT, 0); /* select DTO0 */
	} else {
		dto_cntl = RREG32(DCCG_AUDIO_DTO1_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK;
		dto_cntl |= DCCG_AUDIO_DTO_WALLCLOCK_RATIO(wallclock_ratio);
		WREG32(DCCG_AUDIO_DTO1_CNTL, dto_cntl);
		WREG32(DCCG_AUDIO_DTO1_PHASE, dto_phase);
		WREG32(DCCG_AUDIO_DTO1_MODULE, clock);
		WREG32(DCCG_AUDIO_DTO_SELECT, 1); /* select DTO1 */
	}
}

/*
 * update the info frames with the data from the current display mode
 */
void dce3_1_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode)
{
	struct drm_device *dev = encoder->dev;
	struct radeon_device *rdev = dev->dev_private;
	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
	u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
	struct hdmi_avi_infoframe frame;
	uint32_t offset;
	ssize_t err;

	if (!dig || !dig->afmt)
		return;

	/* Silent, r600_hdmi_enable will raise WARN for us */
	if (!dig->afmt->enabled)
		return;
	offset = dig->afmt->offset;

	/* disable audio prior to setting up hw */
	dig->afmt->pin = radeon_audio_get_pin(encoder);
	radeon_audio_enable(rdev, dig->afmt->pin, 0);

	radeon_audio_set_dto(encoder, mode->clock);

	WREG32(HDMI0_VBI_PACKET_CONTROL + offset,
	       HDMI0_NULL_SEND); /* send null packets when required */

	WREG32(HDMI0_AUDIO_CRC_CONTROL + offset, 0x1000);

	if (ASIC_IS_DCE32(rdev)) {
		WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset,
		       HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */
		       HDMI0_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */
		WREG32(AFMT_AUDIO_PACKET_CONTROL + offset,
		       AFMT_AUDIO_SAMPLE_SEND | /* send audio packets */
		       AFMT_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */
	} else {
		WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset,
		       HDMI0_AUDIO_SAMPLE_SEND | /* send audio packets */
		       HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */
		       HDMI0_AUDIO_PACKETS_PER_LINE(3) | /* should be suffient for all audio modes and small enough for all hblanks */
		       HDMI0_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */
	}

	if (ASIC_IS_DCE32(rdev)) {
		radeon_audio_write_speaker_allocation(encoder);
		radeon_audio_write_sad_regs(encoder);
	}

	WREG32(HDMI0_ACR_PACKET_CONTROL + offset,
	       HDMI0_ACR_SOURCE | /* select SW CTS value - XXX verify that hw CTS works on all families */
	       HDMI0_ACR_AUTO_SEND); /* allow hw to sent ACR packets when required */

	WREG32(HDMI0_VBI_PACKET_CONTROL + offset,
	       HDMI0_NULL_SEND | /* send null packets when required */
	       HDMI0_GC_SEND | /* send general control packets */
	       HDMI0_GC_CONT); /* send general control packets every frame */

	/* TODO: HDMI0_AUDIO_INFO_UPDATE */
	WREG32(HDMI0_INFOFRAME_CONTROL0 + offset,
	       HDMI0_AVI_INFO_SEND | /* enable AVI info frames */
	       HDMI0_AVI_INFO_CONT | /* send AVI info frames every frame/field */
	       HDMI0_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */
	       HDMI0_AUDIO_INFO_CONT); /* send audio info frames every frame/field */

	WREG32(HDMI0_INFOFRAME_CONTROL1 + offset,
	       HDMI0_AVI_INFO_LINE(2) | /* anything other than 0 */
	       HDMI0_AUDIO_INFO_LINE(2)); /* anything other than 0 */

	WREG32(HDMI0_GC + offset, 0); /* unset HDMI0_GC_AVMUTE */

	err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
	if (err < 0) {
		DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
		return;
	}

	err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
	if (err < 0) {
		DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
		return;
	}

	radeon_update_avi_infoframe(encoder, buffer, sizeof(buffer));
	r600_hdmi_update_ACR(encoder, mode->clock);

	/* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */
	WREG32(HDMI0_RAMP_CONTROL0 + offset, 0x00FFFFFF);
	WREG32(HDMI0_RAMP_CONTROL1 + offset, 0x007FFFFF);
	WREG32(HDMI0_RAMP_CONTROL2 + offset, 0x00000001);
	WREG32(HDMI0_RAMP_CONTROL3 + offset, 0x00000001);

	r600_hdmi_audio_workaround(encoder);

	/* enable audio after to setting up hw */
	radeon_audio_enable(rdev, dig->afmt->pin, 0xf);
}
Commit	Line	Data
8f33a156 RM	1	/*
	2	* Copyright 2013 Advanced Micro Devices, Inc.
	3	* Copyright 2014 Rafał Miłecki
	4	*
	5	* Permission is hereby granted, free of charge, to any person obtaining a
	6	* copy of this software and associated documentation files (the "Software"),
	7	* to deal in the Software without restriction, including without limitation
	8	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	9	* and/or sell copies of the Software, and to permit persons to whom the
	10	* Software is furnished to do so, subject to the following conditions:
	11	*
	12	* The above copyright notice and this permission notice shall be included in
	13	* all copies or substantial portions of the Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	19	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	20	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	21	* OTHER DEALINGS IN THE SOFTWARE.
	22	*/
	23	#include <linux/hdmi.h>
	24	#include <drm/drmP.h>
	25	#include "radeon.h"
	26	#include "radeon_asic.h"
070a2e63	27	#include "radeon_audio.h"
8f33a156 RM	28	#include "r600d.h"
8f33a156 RM	29
00a9d4bc SG	30	void dce3_2_afmt_hdmi_write_speaker_allocation(struct drm_encoder *encoder,
00a9d4bc SG	31	u8 *sadb, int sad_count)
8f33a156 RM	32	{
8f33a156 RM	33	struct radeon_device *rdev = encoder->dev->dev_private;
8f33a156	34	u32 tmp;
8f33a156 RM	35
8f33a156 RM	36	/* program the speaker allocation */
00a9d4bc	37	tmp = RREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER);
8f33a156 RM	38	tmp &= ~(DP_CONNECTION \| SPEAKER_ALLOCATION_MASK);
	39	/* set HDMI mode */
	40	tmp \|= HDMI_CONNECTION;
	41	if (sad_count)
	42	tmp \|= SPEAKER_ALLOCATION(sadb[0]);
	43	else
	44	tmp \|= SPEAKER_ALLOCATION(5); /* stereo */
00a9d4bc SG	45	WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp);
00a9d4bc SG	46	}
8f33a156	47
00a9d4bc SG	48	void dce3_2_afmt_dp_write_speaker_allocation(struct drm_encoder *encoder,
	49	u8 *sadb, int sad_count)
	50	{
	51	struct radeon_device *rdev = encoder->dev->dev_private;
	52	u32 tmp;
	53
	54	/* program the speaker allocation */
	55	tmp = RREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER);
	56	tmp &= ~(HDMI_CONNECTION \| SPEAKER_ALLOCATION_MASK);
	57	/* set DP mode */
	58	tmp \|= DP_CONNECTION;
	59	if (sad_count)
	60	tmp \|= SPEAKER_ALLOCATION(sadb[0]);
	61	else
	62	tmp \|= SPEAKER_ALLOCATION(5); /* stereo */
	63	WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp);
8f33a156 RM	64	}
8f33a156 RM	65
070a2e63 AD	66	void dce3_2_afmt_write_sad_regs(struct drm_encoder *encoder,
070a2e63 AD	67	struct cea_sad *sads, int sad_count)
8f33a156	68	{
070a2e63	69	int i;
8f33a156	70	struct radeon_device *rdev = encoder->dev->dev_private;
8f33a156 RM	71	static const u16 eld_reg_to_type[][2] = {
	72	{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
	73	{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
	74	{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
	75	{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
	76	{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
	77	{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
	78	{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
	79	{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
	80	{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
	81	{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
	82	{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
	83	{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
	84	};
	85
8f33a156 RM	86	for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
	87	u32 value = 0;
	88	u8 stereo_freqs = 0;
	89	int max_channels = -1;
	90	int j;
	91
	92	for (j = 0; j < sad_count; j++) {
	93	struct cea_sad *sad = &sads[j];
	94
	95	if (sad->format == eld_reg_to_type[i][1]) {
	96	if (sad->channels > max_channels) {
	97	value = MAX_CHANNELS(sad->channels) \|
	98	DESCRIPTOR_BYTE_2(sad->byte2) \|
	99	SUPPORTED_FREQUENCIES(sad->freq);
	100	max_channels = sad->channels;
	101	}
	102
	103	if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
	104	stereo_freqs \|= sad->freq;
	105	else
	106	break;
	107	}
	108	}
	109
	110	value \|= SUPPORTED_FREQUENCIES_STEREO(stereo_freqs);
	111
070a2e63	112	WREG32_ENDPOINT(0, eld_reg_to_type[i][0], value);
8f33a156	113	}
8f33a156 RM	114	}
8f33a156 RM	115
a85d682a SG	116	void dce3_2_audio_set_dto(struct radeon_device *rdev,
	117	struct radeon_crtc *crtc, unsigned int clock)
	118	{
	119	struct radeon_encoder *radeon_encoder;
	120	struct radeon_encoder_atom_dig *dig;
	121	unsigned int max_ratio = clock / 24000;
	122	u32 dto_phase;
	123	u32 wallclock_ratio;
	124	u32 dto_cntl;
	125
	126	if (!crtc)
	127	return;
	128
	129	radeon_encoder = to_radeon_encoder(crtc->encoder);
	130	dig = radeon_encoder->enc_priv;
	131
	132	if (!dig)
	133	return;
	134
	135	if (max_ratio >= 8) {
	136	dto_phase = 192 * 1000;
	137	wallclock_ratio = 3;
	138	} else if (max_ratio >= 4) {
	139	dto_phase = 96 * 1000;
	140	wallclock_ratio = 2;
	141	} else if (max_ratio >= 2) {
	142	dto_phase = 48 * 1000;
	143	wallclock_ratio = 1;
	144	} else {
	145	dto_phase = 24 * 1000;
	146	wallclock_ratio = 0;
	147	}
	148
	149	/* Express [24MHz / target pixel clock] as an exact rational
	150	* number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
	151	* is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
	152	*/
	153	if (dig->dig_encoder == 0) {
	154	dto_cntl = RREG32(DCCG_AUDIO_DTO0_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK;
	155	dto_cntl \|= DCCG_AUDIO_DTO_WALLCLOCK_RATIO(wallclock_ratio);
	156	WREG32(DCCG_AUDIO_DTO0_CNTL, dto_cntl);
	157	WREG32(DCCG_AUDIO_DTO0_PHASE, dto_phase);
	158	WREG32(DCCG_AUDIO_DTO0_MODULE, clock);
	159	WREG32(DCCG_AUDIO_DTO_SELECT, 0); /* select DTO0 */
	160	} else {
	161	dto_cntl = RREG32(DCCG_AUDIO_DTO1_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK;
	162	dto_cntl \|= DCCG_AUDIO_DTO_WALLCLOCK_RATIO(wallclock_ratio);
	163	WREG32(DCCG_AUDIO_DTO1_CNTL, dto_cntl);
	164	WREG32(DCCG_AUDIO_DTO1_PHASE, dto_phase);
	165	WREG32(DCCG_AUDIO_DTO1_MODULE, clock);
	166	WREG32(DCCG_AUDIO_DTO_SELECT, 1); /* select DTO1 */
	167	}
	168	}
	169
8f33a156 RM	170	/*
	171	* update the info frames with the data from the current display mode
	172	*/
	173	void dce3_1_hdmi_setmode(struct drm_encoder encoder, struct drm_display_mode mode)
	174	{
	175	struct drm_device *dev = encoder->dev;
	176	struct radeon_device *rdev = dev->dev_private;
	177	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
	178	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
	179	u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
	180	struct hdmi_avi_infoframe frame;
	181	uint32_t offset;
	182	ssize_t err;
	183
	184	if (!dig \|\| !dig->afmt)
	185	return;
	186
	187	/* Silent, r600_hdmi_enable will raise WARN for us */
	188	if (!dig->afmt->enabled)
	189	return;
	190	offset = dig->afmt->offset;
	191
	192	/* disable audio prior to setting up hw */
3cdde027	193	dig->afmt->pin = radeon_audio_get_pin(encoder);
8bf59820	194	radeon_audio_enable(rdev, dig->afmt->pin, 0);
8f33a156	195
a85d682a	196	radeon_audio_set_dto(encoder, mode->clock);
8f33a156 RM	197
	198	WREG32(HDMI0_VBI_PACKET_CONTROL + offset,
	199	HDMI0_NULL_SEND); /* send null packets when required */
	200
	201	WREG32(HDMI0_AUDIO_CRC_CONTROL + offset, 0x1000);
	202
	203	if (ASIC_IS_DCE32(rdev)) {
	204	WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset,
	205	HDMI0_AUDIO_DELAY_EN(1) \| /* default audio delay */
	206	HDMI0_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */
	207	WREG32(AFMT_AUDIO_PACKET_CONTROL + offset,
	208	AFMT_AUDIO_SAMPLE_SEND \| /* send audio packets */
	209	AFMT_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */
	210	} else {
	211	WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset,
	212	HDMI0_AUDIO_SAMPLE_SEND \| /* send audio packets */
	213	HDMI0_AUDIO_DELAY_EN(1) \| /* default audio delay */
	214	HDMI0_AUDIO_PACKETS_PER_LINE(3) \| /* should be suffient for all audio modes and small enough for all hblanks */
	215	HDMI0_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */
	216	}
	217
	218	if (ASIC_IS_DCE32(rdev)) {
00a9d4bc	219	radeon_audio_write_speaker_allocation(encoder);
070a2e63	220	radeon_audio_write_sad_regs(encoder);
8f33a156 RM	221	}
	222
	223	WREG32(HDMI0_ACR_PACKET_CONTROL + offset,
	224	HDMI0_ACR_SOURCE \| /* select SW CTS value - XXX verify that hw CTS works on all families */
	225	HDMI0_ACR_AUTO_SEND); /* allow hw to sent ACR packets when required */
	226
	227	WREG32(HDMI0_VBI_PACKET_CONTROL + offset,
	228	HDMI0_NULL_SEND \| /* send null packets when required */
	229	HDMI0_GC_SEND \| /* send general control packets */
	230	HDMI0_GC_CONT); /* send general control packets every frame */
	231
	232	/* TODO: HDMI0_AUDIO_INFO_UPDATE */
	233	WREG32(HDMI0_INFOFRAME_CONTROL0 + offset,
	234	HDMI0_AVI_INFO_SEND \| /* enable AVI info frames */
	235	HDMI0_AVI_INFO_CONT \| /* send AVI info frames every frame/field */
	236	HDMI0_AUDIO_INFO_SEND \| /* enable audio info frames (frames won't be set until audio is enabled) */
	237	HDMI0_AUDIO_INFO_CONT); /* send audio info frames every frame/field */
	238
	239	WREG32(HDMI0_INFOFRAME_CONTROL1 + offset,
	240	HDMI0_AVI_INFO_LINE(2) \| /* anything other than 0 */
	241	HDMI0_AUDIO_INFO_LINE(2)); /* anything other than 0 */
	242
	243	WREG32(HDMI0_GC + offset, 0); /* unset HDMI0_GC_AVMUTE */
	244
	245	err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
	246	if (err < 0) {
	247	DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
	248	return;
	249	}
	250
	251	err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
	252	if (err < 0) {
	253	DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
	254	return;
	255	}
	256
96ea7afb	257	radeon_update_avi_infoframe(encoder, buffer, sizeof(buffer));
8f33a156 RM	258	r600_hdmi_update_ACR(encoder, mode->clock);
	259
	260	/* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */
	261	WREG32(HDMI0_RAMP_CONTROL0 + offset, 0x00FFFFFF);
	262	WREG32(HDMI0_RAMP_CONTROL1 + offset, 0x007FFFFF);
	263	WREG32(HDMI0_RAMP_CONTROL2 + offset, 0x00000001);
	264	WREG32(HDMI0_RAMP_CONTROL3 + offset, 0x00000001);
	265
	266	r600_hdmi_audio_workaround(encoder);
	267
	268	/* enable audio after to setting up hw */
8bf59820	269	radeon_audio_enable(rdev, dig->afmt->pin, 0xf);
8f33a156	270	}