[deliverable/linux.git] / drivers / gpu / drm / radeon / dce6_afmt.c

/*
 * Copyright 2013 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */
#include <linux/hdmi.h>
#include <drm/drmP.h>
#include "radeon.h"
#include "sid.h"

static u32 dce6_endpoint_rreg(struct radeon_device *rdev,
			      u32 block_offset, u32 reg)
{
	unsigned long flags;
	u32 r;

	spin_lock_irqsave(&rdev->end_idx_lock, flags);
	WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
	r = RREG32(AZ_F0_CODEC_ENDPOINT_DATA + block_offset);
	spin_unlock_irqrestore(&rdev->end_idx_lock, flags);

	return r;
}

static void dce6_endpoint_wreg(struct radeon_device *rdev,
			       u32 block_offset, u32 reg, u32 v)
{
	unsigned long flags;

	spin_lock_irqsave(&rdev->end_idx_lock, flags);
	if (ASIC_IS_DCE8(rdev))
		WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
	else
		WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset,
		       AZ_ENDPOINT_REG_WRITE_EN | AZ_ENDPOINT_REG_INDEX(reg));
	WREG32(AZ_F0_CODEC_ENDPOINT_DATA + block_offset, v);
	spin_unlock_irqrestore(&rdev->end_idx_lock, flags);
}

#define RREG32_ENDPOINT(block, reg) dce6_endpoint_rreg(rdev, (block), (reg))
#define WREG32_ENDPOINT(block, reg, v) dce6_endpoint_wreg(rdev, (block), (reg), (v))


static void dce6_afmt_get_connected_pins(struct radeon_device *rdev)
{
	int i;
	u32 offset, tmp;

	for (i = 0; i < rdev->audio.num_pins; i++) {
		offset = rdev->audio.pin[i].offset;
		tmp = RREG32_ENDPOINT(offset,
				      AZ_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
		if (((tmp & PORT_CONNECTIVITY_MASK) >> PORT_CONNECTIVITY_SHIFT) == 1)
			rdev->audio.pin[i].connected = false;
		else
			rdev->audio.pin[i].connected = true;
	}
}

struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev)
{
	int i;

	dce6_afmt_get_connected_pins(rdev);

	for (i = 0; i < rdev->audio.num_pins; i++) {
		if (rdev->audio.pin[i].connected)
			return &rdev->audio.pin[i];
	}
	DRM_ERROR("No connected audio pins found!\n");
	return NULL;
}

void dce6_afmt_select_pin(struct drm_encoder *encoder)
{
	struct radeon_device *rdev = encoder->dev->dev_private;
	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
	u32 offset = dig->afmt->offset;

	if (!dig->afmt->pin)
		return;

	WREG32(AFMT_AUDIO_SRC_CONTROL + offset,
	       AFMT_AUDIO_SRC_SELECT(dig->afmt->pin->id));
}

void dce6_afmt_write_latency_fields(struct drm_encoder *encoder,
				    struct drm_display_mode *mode)
{
	struct radeon_device *rdev = encoder->dev->dev_private;
	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
	struct drm_connector *connector;
	struct radeon_connector *radeon_connector = NULL;
	u32 tmp = 0, offset;

	if (!dig->afmt->pin)
		return;

	offset = dig->afmt->pin->offset;

	list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
		if (connector->encoder == encoder) {
			radeon_connector = to_radeon_connector(connector);
			break;
		}
	}

	if (!radeon_connector) {
		DRM_ERROR("Couldn't find encoder's connector\n");
		return;
	}

	if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
		if (connector->latency_present[1])
			tmp = VIDEO_LIPSYNC(connector->video_latency[1]) |
				AUDIO_LIPSYNC(connector->audio_latency[1]);
		else
			tmp = VIDEO_LIPSYNC(255) | AUDIO_LIPSYNC(255);
	} else {
		if (connector->latency_present[0])
			tmp = VIDEO_LIPSYNC(connector->video_latency[0]) |
				AUDIO_LIPSYNC(connector->audio_latency[0]);
		else
			tmp = VIDEO_LIPSYNC(255) | AUDIO_LIPSYNC(255);
	}
	WREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
}

void dce6_afmt_write_speaker_allocation(struct drm_encoder *encoder)
{
	struct radeon_device *rdev = encoder->dev->dev_private;
	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
	struct drm_connector *connector;
	struct radeon_connector *radeon_connector = NULL;
	u32 offset, tmp;
	u8 *sadb;
	int sad_count;

	/* XXX: setting this register causes hangs on some asics */
	return;

	if (!dig->afmt->pin)
		return;

	offset = dig->afmt->pin->offset;

	list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
		if (connector->encoder == encoder)
			radeon_connector = to_radeon_connector(connector);
	}

	if (!radeon_connector) {
		DRM_ERROR("Couldn't find encoder's connector\n");
		return;
	}

	sad_count = drm_edid_to_speaker_allocation(radeon_connector->edid, &sadb);
	if (sad_count < 0) {
		DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
		return;
	}

	/* program the speaker allocation */
	tmp = RREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
	tmp &= ~(DP_CONNECTION | SPEAKER_ALLOCATION_MASK);
	/* set HDMI mode */
	tmp |= HDMI_CONNECTION;
	if (sad_count)
		tmp |= SPEAKER_ALLOCATION(sadb[0]);
	else
		tmp |= SPEAKER_ALLOCATION(5); /* stereo */
	WREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);

	kfree(sadb);
}

void dce6_afmt_write_sad_regs(struct drm_encoder *encoder)
{
	struct radeon_device *rdev = encoder->dev->dev_private;
	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
	u32 offset;
	struct drm_connector *connector;
	struct radeon_connector *radeon_connector = NULL;
	struct cea_sad *sads;
	int i, sad_count;

	static const u16 eld_reg_to_type[][2] = {
		{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
		{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
		{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
		{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
		{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
		{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
		{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
		{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
		{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
		{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
		{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
		{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
	};

	if (!dig->afmt->pin)
		return;

	offset = dig->afmt->pin->offset;

	list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
		if (connector->encoder == encoder)
			radeon_connector = to_radeon_connector(connector);
	}

	if (!radeon_connector) {
		DRM_ERROR("Couldn't find encoder's connector\n");
		return;
	}

	sad_count = drm_edid_to_sad(radeon_connector->edid, &sads);
	if (sad_count < 0) {
		DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
		return;
	}
	BUG_ON(!sads);

	for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
		u32 value = 0;
		u8 stereo_freqs = 0;
		int max_channels = -1;
		int j;

		for (j = 0; j < sad_count; j++) {
			struct cea_sad *sad = &sads[j];

			if (sad->format == eld_reg_to_type[i][1]) {
				if (sad->channels > max_channels) {
					value = MAX_CHANNELS(sad->channels) |
						DESCRIPTOR_BYTE_2(sad->byte2) |
						SUPPORTED_FREQUENCIES(sad->freq);
					max_channels = sad->channels;
				}

				if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
					stereo_freqs |= sad->freq;
				else
					break;
			}
		}

		value |= SUPPORTED_FREQUENCIES_STEREO(stereo_freqs);

		WREG32_ENDPOINT(offset, eld_reg_to_type[i][0], value);
	}

	kfree(sads);
}

static int dce6_audio_chipset_supported(struct radeon_device *rdev)
{
	return !ASIC_IS_NODCE(rdev);
}

static void dce6_audio_enable(struct radeon_device *rdev,
			      struct r600_audio_pin *pin,
			      bool enable)
{
	WREG32_ENDPOINT(pin->offset, AZ_F0_CODEC_PIN_CONTROL_HOTPLUG_CONTROL,
			AUDIO_ENABLED);
	DRM_INFO("%s audio %d support\n", enable ? "Enabling" : "Disabling", pin->id);
}

static const u32 pin_offsets[7] =
{
	(0x5e00 - 0x5e00),
	(0x5e18 - 0x5e00),
	(0x5e30 - 0x5e00),
	(0x5e48 - 0x5e00),
	(0x5e60 - 0x5e00),
	(0x5e78 - 0x5e00),
	(0x5e90 - 0x5e00),
};

int dce6_audio_init(struct radeon_device *rdev)
{
	int i;

	if (!radeon_audio || !dce6_audio_chipset_supported(rdev))
		return 0;

	rdev->audio.enabled = true;

	if (ASIC_IS_DCE8(rdev))
		rdev->audio.num_pins = 7;
	else
		rdev->audio.num_pins = 6;

	for (i = 0; i < rdev->audio.num_pins; i++) {
		rdev->audio.pin[i].channels = -1;
		rdev->audio.pin[i].rate = -1;
		rdev->audio.pin[i].bits_per_sample = -1;
		rdev->audio.pin[i].status_bits = 0;
		rdev->audio.pin[i].category_code = 0;
		rdev->audio.pin[i].connected = false;
		rdev->audio.pin[i].offset = pin_offsets[i];
		rdev->audio.pin[i].id = i;
		dce6_audio_enable(rdev, &rdev->audio.pin[i], true);
	}

	return 0;
}

void dce6_audio_fini(struct radeon_device *rdev)
{
	int i;

	if (!rdev->audio.enabled)
		return;

	for (i = 0; i < rdev->audio.num_pins; i++)
		dce6_audio_enable(rdev, &rdev->audio.pin[i], false);

	rdev->audio.enabled = false;
}
Commit	Line	Data
b530602f AD	1	/*
	2	* Copyright 2013 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	*/
	23	#include <linux/hdmi.h>
	24	#include <drm/drmP.h>
	25	#include "radeon.h"
	26	#include "sid.h"
	27
	28	static u32 dce6_endpoint_rreg(struct radeon_device *rdev,
	29	u32 block_offset, u32 reg)
	30	{
0a5b7b0b	31	unsigned long flags;
b530602f AD	32	u32 r;
b530602f AD	33
0a5b7b0b	34	spin_lock_irqsave(&rdev->end_idx_lock, flags);
b530602f AD	35	WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
b530602f AD	36	r = RREG32(AZ_F0_CODEC_ENDPOINT_DATA + block_offset);
0a5b7b0b AD	37	spin_unlock_irqrestore(&rdev->end_idx_lock, flags);
0a5b7b0b AD	38
b530602f AD	39	return r;
	40	}
	41
	42	static void dce6_endpoint_wreg(struct radeon_device *rdev,
	43	u32 block_offset, u32 reg, u32 v)
	44	{
0a5b7b0b AD	45	unsigned long flags;
	46
	47	spin_lock_irqsave(&rdev->end_idx_lock, flags);
b530602f AD	48	if (ASIC_IS_DCE8(rdev))
	49	WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
	50	else
	51	WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset,
	52	AZ_ENDPOINT_REG_WRITE_EN \| AZ_ENDPOINT_REG_INDEX(reg));
	53	WREG32(AZ_F0_CODEC_ENDPOINT_DATA + block_offset, v);
0a5b7b0b	54	spin_unlock_irqrestore(&rdev->end_idx_lock, flags);
b530602f AD	55	}
	56
	57	#define RREG32_ENDPOINT(block, reg) dce6_endpoint_rreg(rdev, (block), (reg))
	58	#define WREG32_ENDPOINT(block, reg, v) dce6_endpoint_wreg(rdev, (block), (reg), (v))
	59
	60
	61	static void dce6_afmt_get_connected_pins(struct radeon_device *rdev)
	62	{
	63	int i;
	64	u32 offset, tmp;
	65
	66	for (i = 0; i < rdev->audio.num_pins; i++) {
	67	offset = rdev->audio.pin[i].offset;
	68	tmp = RREG32_ENDPOINT(offset,
	69	AZ_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
	70	if (((tmp & PORT_CONNECTIVITY_MASK) >> PORT_CONNECTIVITY_SHIFT) == 1)
	71	rdev->audio.pin[i].connected = false;
	72	else
	73	rdev->audio.pin[i].connected = true;
	74	}
	75	}
	76
	77	struct r600_audio_pin dce6_audio_get_pin(struct radeon_device rdev)
	78	{
	79	int i;
	80
	81	dce6_afmt_get_connected_pins(rdev);
	82
	83	for (i = 0; i < rdev->audio.num_pins; i++) {
	84	if (rdev->audio.pin[i].connected)
	85	return &rdev->audio.pin[i];
	86	}
	87	DRM_ERROR("No connected audio pins found!\n");
	88	return NULL;
	89	}
	90
	91	void dce6_afmt_select_pin(struct drm_encoder *encoder)
	92	{
	93	struct radeon_device *rdev = encoder->dev->dev_private;
	94	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
	95	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
	96	u32 offset = dig->afmt->offset;
b530602f AD	97
	98	if (!dig->afmt->pin)
	99	return;
	100
7cc0a3d8 AD	101	WREG32(AFMT_AUDIO_SRC_CONTROL + offset,
7cc0a3d8 AD	102	AFMT_AUDIO_SRC_SELECT(dig->afmt->pin->id));
b530602f AD	103	}
b530602f AD	104
b1880258 AD	105	void dce6_afmt_write_latency_fields(struct drm_encoder *encoder,
	106	struct drm_display_mode *mode)
	107	{
	108	struct radeon_device *rdev = encoder->dev->dev_private;
	109	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
	110	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
	111	struct drm_connector *connector;
	112	struct radeon_connector *radeon_connector = NULL;
	113	u32 tmp = 0, offset;
	114
	115	if (!dig->afmt->pin)
	116	return;
	117
	118	offset = dig->afmt->pin->offset;
	119
	120	list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
	121	if (connector->encoder == encoder) {
	122	radeon_connector = to_radeon_connector(connector);
	123	break;
	124	}
	125	}
	126
	127	if (!radeon_connector) {
	128	DRM_ERROR("Couldn't find encoder's connector\n");
	129	return;
	130	}
	131
	132	if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
	133	if (connector->latency_present[1])
	134	tmp = VIDEO_LIPSYNC(connector->video_latency[1]) \|
	135	AUDIO_LIPSYNC(connector->audio_latency[1]);
	136	else
	137	tmp = VIDEO_LIPSYNC(255) \| AUDIO_LIPSYNC(255);
	138	} else {
	139	if (connector->latency_present[0])
	140	tmp = VIDEO_LIPSYNC(connector->video_latency[0]) \|
	141	AUDIO_LIPSYNC(connector->audio_latency[0]);
	142	else
	143	tmp = VIDEO_LIPSYNC(255) \| AUDIO_LIPSYNC(255);
	144	}
	145	WREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
	146	}
	147
6159b65a	148	void dce6_afmt_write_speaker_allocation(struct drm_encoder *encoder)
b530602f AD	149	{
	150	struct radeon_device *rdev = encoder->dev->dev_private;
	151	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
	152	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
6159b65a RM	153	struct drm_connector *connector;
6159b65a RM	154	struct radeon_connector *radeon_connector = NULL;
b530602f	155	u32 offset, tmp;
6159b65a RM	156	u8 *sadb;
	157	int sad_count;
	158
555b1b65 AD	159	/* XXX: setting this register causes hangs on some asics */
	160	return;
	161
6159b65a RM	162	if (!dig->afmt->pin)
	163	return;
	164
	165	offset = dig->afmt->pin->offset;
	166
	167	list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
	168	if (connector->encoder == encoder)
	169	radeon_connector = to_radeon_connector(connector);
	170	}
	171
	172	if (!radeon_connector) {
	173	DRM_ERROR("Couldn't find encoder's connector\n");
	174	return;
	175	}
	176
	177	sad_count = drm_edid_to_speaker_allocation(radeon_connector->edid, &sadb);
	178	if (sad_count < 0) {
	179	DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
	180	return;
	181	}
	182
	183	/* program the speaker allocation */
	184	tmp = RREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
	185	tmp &= ~(DP_CONNECTION \| SPEAKER_ALLOCATION_MASK);
	186	/* set HDMI mode */
	187	tmp \|= HDMI_CONNECTION;
	188	if (sad_count)
	189	tmp \|= SPEAKER_ALLOCATION(sadb[0]);
	190	else
	191	tmp \|= SPEAKER_ALLOCATION(5); /* stereo */
	192	WREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
	193
	194	kfree(sadb);
	195	}
	196
	197	void dce6_afmt_write_sad_regs(struct drm_encoder *encoder)
	198	{
	199	struct radeon_device *rdev = encoder->dev->dev_private;
	200	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
	201	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
	202	u32 offset;
b530602f AD	203	struct drm_connector *connector;
	204	struct radeon_connector *radeon_connector = NULL;
	205	struct cea_sad *sads;
6159b65a	206	int i, sad_count;
b530602f AD	207
	208	static const u16 eld_reg_to_type[][2] = {
	209	{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
	210	{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
	211	{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
	212	{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
	213	{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
	214	{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
	215	{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
	216	{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
	217	{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
	218	{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
	219	{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
	220	{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
	221	};
	222
	223	if (!dig->afmt->pin)
	224	return;
	225
	226	offset = dig->afmt->pin->offset;
	227
	228	list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
	229	if (connector->encoder == encoder)
	230	radeon_connector = to_radeon_connector(connector);
	231	}
	232
	233	if (!radeon_connector) {
	234	DRM_ERROR("Couldn't find encoder's connector\n");
	235	return;
	236	}
	237
	238	sad_count = drm_edid_to_sad(radeon_connector->edid, &sads);
	239	if (sad_count < 0) {
	240	DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
	241	return;
	242	}
	243	BUG_ON(!sads);
	244
b530602f AD	245	for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
b530602f AD	246	u32 value = 0;
0f57bca9 AH	247	u8 stereo_freqs = 0;
0f57bca9 AH	248	int max_channels = -1;
b530602f AD	249	int j;
	250
	251	for (j = 0; j < sad_count; j++) {
	252	struct cea_sad *sad = &sads[j];
	253
	254	if (sad->format == eld_reg_to_type[i][1]) {
0f57bca9 AH	255	if (sad->channels > max_channels) {
	256	value = MAX_CHANNELS(sad->channels) \|
	257	DESCRIPTOR_BYTE_2(sad->byte2) \|
	258	SUPPORTED_FREQUENCIES(sad->freq);
	259	max_channels = sad->channels;
	260	}
	261
b530602f	262	if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
0f57bca9 AH	263	stereo_freqs \|= sad->freq;
	264	else
	265	break;
b530602f AD	266	}
b530602f AD	267	}
0f57bca9 AH	268
	269	value \|= SUPPORTED_FREQUENCIES_STEREO(stereo_freqs);
	270
b530602f AD	271	WREG32_ENDPOINT(offset, eld_reg_to_type[i][0], value);
	272	}
	273
	274	kfree(sads);
b530602f AD	275	}
	276
	277	static int dce6_audio_chipset_supported(struct radeon_device *rdev)
	278	{
	279	return !ASIC_IS_NODCE(rdev);
	280	}
	281
	282	static void dce6_audio_enable(struct radeon_device *rdev,
	283	struct r600_audio_pin *pin,
	284	bool enable)
	285	{
	286	WREG32_ENDPOINT(pin->offset, AZ_F0_CODEC_PIN_CONTROL_HOTPLUG_CONTROL,
	287	AUDIO_ENABLED);
	288	DRM_INFO("%s audio %d support\n", enable ? "Enabling" : "Disabling", pin->id);
	289	}
	290
	291	static const u32 pin_offsets[7] =
	292	{
	293	(0x5e00 - 0x5e00),
	294	(0x5e18 - 0x5e00),
	295	(0x5e30 - 0x5e00),
	296	(0x5e48 - 0x5e00),
	297	(0x5e60 - 0x5e00),
	298	(0x5e78 - 0x5e00),
	299	(0x5e90 - 0x5e00),
	300	};
	301
	302	int dce6_audio_init(struct radeon_device *rdev)
	303	{
	304	int i;
	305
	306	if (!radeon_audio \|\| !dce6_audio_chipset_supported(rdev))
	307	return 0;
	308
	309	rdev->audio.enabled = true;
	310
	311	if (ASIC_IS_DCE8(rdev))
	312	rdev->audio.num_pins = 7;
	313	else
	314	rdev->audio.num_pins = 6;
	315
	316	for (i = 0; i < rdev->audio.num_pins; i++) {
	317	rdev->audio.pin[i].channels = -1;
	318	rdev->audio.pin[i].rate = -1;
	319	rdev->audio.pin[i].bits_per_sample = -1;
	320	rdev->audio.pin[i].status_bits = 0;
	321	rdev->audio.pin[i].category_code = 0;
	322	rdev->audio.pin[i].connected = false;
	323	rdev->audio.pin[i].offset = pin_offsets[i];
	324	rdev->audio.pin[i].id = i;
	325	dce6_audio_enable(rdev, &rdev->audio.pin[i], true);
	326	}
	327
	328	return 0;
	329	}
	330
	331	void dce6_audio_fini(struct radeon_device *rdev)
	332	{
	333	int i;
	334
	335	if (!rdev->audio.enabled)
	336	return;
	337
	338	for (i = 0; i < rdev->audio.num_pins; i++)
339	dce6_audio_enable(rdev, &rdev->audio.pin[i], false);
340
341	rdev->audio.enabled = false;
342	}