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b530602f AD |
1 | /* |
2 | * Copyright 2013 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | */ | |
23 | #include <linux/hdmi.h> | |
24 | #include <drm/drmP.h> | |
25 | #include "radeon.h" | |
1a626b68 | 26 | #include "radeon_audio.h" |
b530602f AD |
27 | #include "sid.h" |
28 | ||
2afa3265 SG |
29 | #define DCE8_DCCG_AUDIO_DTO1_PHASE 0x05b8 |
30 | #define DCE8_DCCG_AUDIO_DTO1_MODULE 0x05bc | |
31 | ||
1a626b68 | 32 | u32 dce6_endpoint_rreg(struct radeon_device *rdev, |
b530602f AD |
33 | u32 block_offset, u32 reg) |
34 | { | |
0a5b7b0b | 35 | unsigned long flags; |
b530602f AD |
36 | u32 r; |
37 | ||
0a5b7b0b | 38 | spin_lock_irqsave(&rdev->end_idx_lock, flags); |
b530602f AD |
39 | WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); |
40 | r = RREG32(AZ_F0_CODEC_ENDPOINT_DATA + block_offset); | |
0a5b7b0b AD |
41 | spin_unlock_irqrestore(&rdev->end_idx_lock, flags); |
42 | ||
b530602f AD |
43 | return r; |
44 | } | |
45 | ||
1a626b68 | 46 | void dce6_endpoint_wreg(struct radeon_device *rdev, |
b530602f AD |
47 | u32 block_offset, u32 reg, u32 v) |
48 | { | |
0a5b7b0b AD |
49 | unsigned long flags; |
50 | ||
51 | spin_lock_irqsave(&rdev->end_idx_lock, flags); | |
b530602f AD |
52 | if (ASIC_IS_DCE8(rdev)) |
53 | WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); | |
54 | else | |
55 | WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset, | |
56 | AZ_ENDPOINT_REG_WRITE_EN | AZ_ENDPOINT_REG_INDEX(reg)); | |
57 | WREG32(AZ_F0_CODEC_ENDPOINT_DATA + block_offset, v); | |
0a5b7b0b | 58 | spin_unlock_irqrestore(&rdev->end_idx_lock, flags); |
b530602f AD |
59 | } |
60 | ||
b530602f AD |
61 | static void dce6_afmt_get_connected_pins(struct radeon_device *rdev) |
62 | { | |
63 | int i; | |
64 | u32 offset, tmp; | |
65 | ||
66 | for (i = 0; i < rdev->audio.num_pins; i++) { | |
67 | offset = rdev->audio.pin[i].offset; | |
68 | tmp = RREG32_ENDPOINT(offset, | |
69 | AZ_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT); | |
70 | if (((tmp & PORT_CONNECTIVITY_MASK) >> PORT_CONNECTIVITY_SHIFT) == 1) | |
71 | rdev->audio.pin[i].connected = false; | |
72 | else | |
73 | rdev->audio.pin[i].connected = true; | |
74 | } | |
75 | } | |
76 | ||
77 | struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev) | |
78 | { | |
79 | int i; | |
80 | ||
81 | dce6_afmt_get_connected_pins(rdev); | |
82 | ||
83 | for (i = 0; i < rdev->audio.num_pins; i++) { | |
84 | if (rdev->audio.pin[i].connected) | |
85 | return &rdev->audio.pin[i]; | |
86 | } | |
87 | DRM_ERROR("No connected audio pins found!\n"); | |
88 | return NULL; | |
89 | } | |
90 | ||
91 | void dce6_afmt_select_pin(struct drm_encoder *encoder) | |
92 | { | |
93 | struct radeon_device *rdev = encoder->dev->dev_private; | |
94 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
95 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; | |
53dc0b0c | 96 | u32 offset; |
b530602f | 97 | |
53dc0b0c | 98 | if (!dig || !dig->afmt || !dig->afmt->pin) |
b530602f AD |
99 | return; |
100 | ||
53dc0b0c AD |
101 | offset = dig->afmt->offset; |
102 | ||
7cc0a3d8 AD |
103 | WREG32(AFMT_AUDIO_SRC_CONTROL + offset, |
104 | AFMT_AUDIO_SRC_SELECT(dig->afmt->pin->id)); | |
b530602f AD |
105 | } |
106 | ||
b1880258 | 107 | void dce6_afmt_write_latency_fields(struct drm_encoder *encoder, |
87654f87 | 108 | struct drm_connector *connector, struct drm_display_mode *mode) |
b1880258 AD |
109 | { |
110 | struct radeon_device *rdev = encoder->dev->dev_private; | |
111 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
112 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; | |
b1880258 AD |
113 | u32 tmp = 0, offset; |
114 | ||
53dc0b0c | 115 | if (!dig || !dig->afmt || !dig->afmt->pin) |
b1880258 AD |
116 | return; |
117 | ||
118 | offset = dig->afmt->pin->offset; | |
119 | ||
b1880258 AD |
120 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) { |
121 | if (connector->latency_present[1]) | |
122 | tmp = VIDEO_LIPSYNC(connector->video_latency[1]) | | |
123 | AUDIO_LIPSYNC(connector->audio_latency[1]); | |
124 | else | |
c748990b | 125 | tmp = VIDEO_LIPSYNC(0) | AUDIO_LIPSYNC(0); |
b1880258 AD |
126 | } else { |
127 | if (connector->latency_present[0]) | |
128 | tmp = VIDEO_LIPSYNC(connector->video_latency[0]) | | |
129 | AUDIO_LIPSYNC(connector->audio_latency[0]); | |
130 | else | |
c748990b | 131 | tmp = VIDEO_LIPSYNC(0) | AUDIO_LIPSYNC(0); |
b1880258 AD |
132 | } |
133 | WREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp); | |
134 | } | |
135 | ||
00a9d4bc SG |
136 | void dce6_afmt_hdmi_write_speaker_allocation(struct drm_encoder *encoder, |
137 | u8 *sadb, int sad_count) | |
b530602f AD |
138 | { |
139 | struct radeon_device *rdev = encoder->dev->dev_private; | |
140 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
141 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; | |
142 | u32 offset, tmp; | |
6159b65a | 143 | |
53dc0b0c | 144 | if (!dig || !dig->afmt || !dig->afmt->pin) |
6159b65a RM |
145 | return; |
146 | ||
147 | offset = dig->afmt->pin->offset; | |
148 | ||
6159b65a RM |
149 | /* program the speaker allocation */ |
150 | tmp = RREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER); | |
151 | tmp &= ~(DP_CONNECTION | SPEAKER_ALLOCATION_MASK); | |
152 | /* set HDMI mode */ | |
153 | tmp |= HDMI_CONNECTION; | |
154 | if (sad_count) | |
155 | tmp |= SPEAKER_ALLOCATION(sadb[0]); | |
156 | else | |
157 | tmp |= SPEAKER_ALLOCATION(5); /* stereo */ | |
158 | WREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp); | |
00a9d4bc | 159 | } |
6159b65a | 160 | |
00a9d4bc SG |
161 | void dce6_afmt_dp_write_speaker_allocation(struct drm_encoder *encoder, |
162 | u8 *sadb, int sad_count) | |
163 | { | |
164 | struct radeon_device *rdev = encoder->dev->dev_private; | |
165 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
166 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; | |
167 | u32 offset, tmp; | |
168 | ||
169 | if (!dig || !dig->afmt || !dig->afmt->pin) | |
170 | return; | |
171 | ||
172 | offset = dig->afmt->pin->offset; | |
173 | ||
174 | /* program the speaker allocation */ | |
175 | tmp = RREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER); | |
176 | tmp &= ~(HDMI_CONNECTION | SPEAKER_ALLOCATION_MASK); | |
177 | /* set DP mode */ | |
178 | tmp |= DP_CONNECTION; | |
179 | if (sad_count) | |
180 | tmp |= SPEAKER_ALLOCATION(sadb[0]); | |
181 | else | |
182 | tmp |= SPEAKER_ALLOCATION(5); /* stereo */ | |
183 | WREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp); | |
6159b65a RM |
184 | } |
185 | ||
070a2e63 AD |
186 | void dce6_afmt_write_sad_regs(struct drm_encoder *encoder, |
187 | struct cea_sad *sads, int sad_count) | |
6159b65a | 188 | { |
070a2e63 AD |
189 | u32 offset; |
190 | int i; | |
6159b65a RM |
191 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
192 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; | |
070a2e63 | 193 | struct radeon_device *rdev = encoder->dev->dev_private; |
b530602f AD |
194 | static const u16 eld_reg_to_type[][2] = { |
195 | { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM }, | |
196 | { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 }, | |
197 | { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 }, | |
198 | { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 }, | |
199 | { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 }, | |
200 | { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC }, | |
201 | { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS }, | |
202 | { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC }, | |
203 | { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 }, | |
204 | { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD }, | |
205 | { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP }, | |
206 | { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO }, | |
207 | }; | |
208 | ||
53dc0b0c | 209 | if (!dig || !dig->afmt || !dig->afmt->pin) |
b530602f AD |
210 | return; |
211 | ||
212 | offset = dig->afmt->pin->offset; | |
213 | ||
b530602f AD |
214 | for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) { |
215 | u32 value = 0; | |
0f57bca9 AH |
216 | u8 stereo_freqs = 0; |
217 | int max_channels = -1; | |
b530602f AD |
218 | int j; |
219 | ||
220 | for (j = 0; j < sad_count; j++) { | |
221 | struct cea_sad *sad = &sads[j]; | |
222 | ||
223 | if (sad->format == eld_reg_to_type[i][1]) { | |
0f57bca9 AH |
224 | if (sad->channels > max_channels) { |
225 | value = MAX_CHANNELS(sad->channels) | | |
226 | DESCRIPTOR_BYTE_2(sad->byte2) | | |
227 | SUPPORTED_FREQUENCIES(sad->freq); | |
228 | max_channels = sad->channels; | |
229 | } | |
230 | ||
b530602f | 231 | if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM) |
0f57bca9 AH |
232 | stereo_freqs |= sad->freq; |
233 | else | |
234 | break; | |
b530602f AD |
235 | } |
236 | } | |
0f57bca9 AH |
237 | |
238 | value |= SUPPORTED_FREQUENCIES_STEREO(stereo_freqs); | |
239 | ||
b530602f AD |
240 | WREG32_ENDPOINT(offset, eld_reg_to_type[i][0], value); |
241 | } | |
b530602f AD |
242 | } |
243 | ||
832eafaf AD |
244 | void dce6_audio_enable(struct radeon_device *rdev, |
245 | struct r600_audio_pin *pin, | |
d3d8c141 | 246 | u8 enable_mask) |
b530602f | 247 | { |
832eafaf AD |
248 | if (!pin) |
249 | return; | |
250 | ||
f68fdbe4 | 251 | WREG32_ENDPOINT(pin->offset, AZ_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, |
d3d8c141 | 252 | enable_mask ? AUDIO_ENABLED : 0); |
b530602f | 253 | } |
a85d682a SG |
254 | |
255 | void dce6_hdmi_audio_set_dto(struct radeon_device *rdev, | |
256 | struct radeon_crtc *crtc, unsigned int clock) | |
257 | { | |
b983a8f4 | 258 | /* Two dtos; generally use dto0 for HDMI */ |
a85d682a SG |
259 | u32 value = 0; |
260 | ||
b983a8f4 | 261 | if (crtc) |
a85d682a SG |
262 | value |= DCCG_AUDIO_DTO0_SOURCE_SEL(crtc->crtc_id); |
263 | ||
264 | WREG32(DCCG_AUDIO_DTO_SOURCE, value); | |
265 | ||
b983a8f4 SG |
266 | /* Express [24MHz / target pixel clock] as an exact rational |
267 | * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE | |
268 | * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator | |
269 | */ | |
270 | WREG32(DCCG_AUDIO_DTO0_PHASE, 24000); | |
271 | WREG32(DCCG_AUDIO_DTO0_MODULE, clock); | |
a85d682a SG |
272 | } |
273 | ||
274 | void dce6_dp_audio_set_dto(struct radeon_device *rdev, | |
275 | struct radeon_crtc *crtc, unsigned int clock) | |
276 | { | |
b983a8f4 | 277 | /* Two dtos; generally use dto1 for DP */ |
a85d682a SG |
278 | u32 value = 0; |
279 | value |= DCCG_AUDIO_DTO_SEL; | |
280 | ||
b983a8f4 | 281 | if (crtc) |
a85d682a SG |
282 | value |= DCCG_AUDIO_DTO0_SOURCE_SEL(crtc->crtc_id); |
283 | ||
284 | WREG32(DCCG_AUDIO_DTO_SOURCE, value); | |
285 | ||
b983a8f4 SG |
286 | /* Express [24MHz / target pixel clock] as an exact rational |
287 | * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE | |
288 | * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator | |
289 | */ | |
2afa3265 SG |
290 | if (ASIC_IS_DCE8(rdev)) { |
291 | WREG32(DCE8_DCCG_AUDIO_DTO1_PHASE, 24000); | |
292 | WREG32(DCE8_DCCG_AUDIO_DTO1_MODULE, clock); | |
293 | } else { | |
294 | WREG32(DCCG_AUDIO_DTO1_PHASE, 24000); | |
295 | WREG32(DCCG_AUDIO_DTO1_MODULE, clock); | |
296 | } | |
a85d682a | 297 | } |
e55bca26 | 298 | |
add7d759 | 299 | void dce6_dp_enable(struct drm_encoder *encoder, bool enable) |
e55bca26 SG |
300 | { |
301 | struct drm_device *dev = encoder->dev; | |
302 | struct radeon_device *rdev = dev->dev_private; | |
303 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
304 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; | |
e55bca26 SG |
305 | |
306 | if (!dig || !dig->afmt) | |
307 | return; | |
308 | ||
e55bca26 | 309 | if (enable) { |
add7d759 AD |
310 | WREG32(EVERGREEN_DP_SEC_TIMESTAMP + dig->afmt->offset, |
311 | EVERGREEN_DP_SEC_TIMESTAMP_MODE(1)); | |
312 | WREG32(EVERGREEN_DP_SEC_CNTL + dig->afmt->offset, | |
313 | EVERGREEN_DP_SEC_ASP_ENABLE | /* Audio packet transmission */ | |
314 | EVERGREEN_DP_SEC_ATP_ENABLE | /* Audio timestamp packet transmission */ | |
315 | EVERGREEN_DP_SEC_AIP_ENABLE | /* Audio infoframe packet transmission */ | |
316 | EVERGREEN_DP_SEC_STREAM_ENABLE); /* Master enable for secondary stream engine */ | |
e55bca26 | 317 | } else { |
add7d759 | 318 | WREG32(EVERGREEN_DP_SEC_CNTL + dig->afmt->offset, 0); |
e55bca26 SG |
319 | } |
320 | ||
321 | dig->afmt->enabled = enable; | |
322 | } |