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drm/radeon/kms/pm: track current voltage (v2)
[deliverable/linux.git] / drivers / gpu / drm / radeon / evergreen.c
CommitLineData
bcc1c2a1
AD		 1/*
2 * Copyright 2010 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24#include <linux/firmware.h>
25#include <linux/platform_device.h>
5a0e3ad6 26#include <linux/slab.h>
bcc1c2a1
AD		 27#include "drmP.h"
28#include "radeon.h"
e6990375 29#include "radeon_asic.h"
bcc1c2a1 30#include "radeon_drm.h"
0fcdb61e 31#include "evergreend.h"
bcc1c2a1
AD		 32#include "atom.h"
33#include "avivod.h"
34#include "evergreen_reg.h"
35
fe251e2f
AD		 36#define EVERGREEN_PFP_UCODE_SIZE 1120
37#define EVERGREEN_PM4_UCODE_SIZE 1376
38
bcc1c2a1
AD		 39static void evergreen_gpu_init(struct radeon_device *rdev);
40void evergreen_fini(struct radeon_device *rdev);
41
49e02b73
AD		 42void evergreen_pm_misc(struct radeon_device *rdev)
43{
9349d5cc
AD		 44 int requested_index = rdev->pm.requested_power_state_index;
45 struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
46 struct radeon_voltage *voltage = &ps->clock_info[0].voltage;
49e02b73 47
4d60173f
AD		 48 if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
49 if (voltage->voltage != rdev->pm.current_vddc) {
50 radeon_atom_set_voltage(rdev, voltage->voltage);
51 rdev->pm.current_vddc = voltage->voltage;
52 }
53 }
49e02b73
AD		 54}
55
56void evergreen_pm_prepare(struct radeon_device *rdev)
57{
58 struct drm_device *ddev = rdev->ddev;
59 struct drm_crtc *crtc;
60 struct radeon_crtc *radeon_crtc;
61 u32 tmp;
62
63 /* disable any active CRTCs */
64 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
65 radeon_crtc = to_radeon_crtc(crtc);
66 if (radeon_crtc->enabled) {
67 tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
68 tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
69 WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
70 }
71 }
72}
73
74void evergreen_pm_finish(struct radeon_device *rdev)
75{
76 struct drm_device *ddev = rdev->ddev;
77 struct drm_crtc *crtc;
78 struct radeon_crtc *radeon_crtc;
79 u32 tmp;
80
81 /* enable any active CRTCs */
82 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
83 radeon_crtc = to_radeon_crtc(crtc);
84 if (radeon_crtc->enabled) {
85 tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
86 tmp &= ~EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
87 WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
88 }
89 }
90}
91
bcc1c2a1
AD		 92bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
93{
94 bool connected = false;
0ca2ab52
AD		 95
96 switch (hpd) {
97 case RADEON_HPD_1:
98 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
99 connected = true;
100 break;
101 case RADEON_HPD_2:
102 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
103 connected = true;
104 break;
105 case RADEON_HPD_3:
106 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
107 connected = true;
108 break;
109 case RADEON_HPD_4:
110 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
111 connected = true;
112 break;
113 case RADEON_HPD_5:
114 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
115 connected = true;
116 break;
117 case RADEON_HPD_6:
118 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
119 connected = true;
120 break;
121 default:
122 break;
123 }
124
bcc1c2a1
AD		 125 return connected;
126}
127
128void evergreen_hpd_set_polarity(struct radeon_device *rdev,
129 enum radeon_hpd_id hpd)
130{
0ca2ab52
AD		 131 u32 tmp;
132 bool connected = evergreen_hpd_sense(rdev, hpd);
133
134 switch (hpd) {
135 case RADEON_HPD_1:
136 tmp = RREG32(DC_HPD1_INT_CONTROL);
137 if (connected)
138 tmp &= ~DC_HPDx_INT_POLARITY;
139 else
140 tmp |= DC_HPDx_INT_POLARITY;
141 WREG32(DC_HPD1_INT_CONTROL, tmp);
142 break;
143 case RADEON_HPD_2:
144 tmp = RREG32(DC_HPD2_INT_CONTROL);
145 if (connected)
146 tmp &= ~DC_HPDx_INT_POLARITY;
147 else
148 tmp |= DC_HPDx_INT_POLARITY;
149 WREG32(DC_HPD2_INT_CONTROL, tmp);
150 break;
151 case RADEON_HPD_3:
152 tmp = RREG32(DC_HPD3_INT_CONTROL);
153 if (connected)
154 tmp &= ~DC_HPDx_INT_POLARITY;
155 else
156 tmp |= DC_HPDx_INT_POLARITY;
157 WREG32(DC_HPD3_INT_CONTROL, tmp);
158 break;
159 case RADEON_HPD_4:
160 tmp = RREG32(DC_HPD4_INT_CONTROL);
161 if (connected)
162 tmp &= ~DC_HPDx_INT_POLARITY;
163 else
164 tmp |= DC_HPDx_INT_POLARITY;
165 WREG32(DC_HPD4_INT_CONTROL, tmp);
166 break;
167 case RADEON_HPD_5:
168 tmp = RREG32(DC_HPD5_INT_CONTROL);
169 if (connected)
170 tmp &= ~DC_HPDx_INT_POLARITY;
171 else
172 tmp |= DC_HPDx_INT_POLARITY;
173 WREG32(DC_HPD5_INT_CONTROL, tmp);
174 break;
175 case RADEON_HPD_6:
176 tmp = RREG32(DC_HPD6_INT_CONTROL);
177 if (connected)
178 tmp &= ~DC_HPDx_INT_POLARITY;
179 else
180 tmp |= DC_HPDx_INT_POLARITY;
181 WREG32(DC_HPD6_INT_CONTROL, tmp);
182 break;
183 default:
184 break;
185 }
bcc1c2a1
AD		 186}
187
188void evergreen_hpd_init(struct radeon_device *rdev)
189{
0ca2ab52
AD		 190 struct drm_device *dev = rdev->ddev;
191 struct drm_connector *connector;
192 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) |
193 DC_HPDx_RX_INT_TIMER(0xfa) | DC_HPDx_EN;
bcc1c2a1 194
0ca2ab52
AD		 195 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
196 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
197 switch (radeon_connector->hpd.hpd) {
198 case RADEON_HPD_1:
199 WREG32(DC_HPD1_CONTROL, tmp);
200 rdev->irq.hpd[0] = true;
201 break;
202 case RADEON_HPD_2:
203 WREG32(DC_HPD2_CONTROL, tmp);
204 rdev->irq.hpd[1] = true;
205 break;
206 case RADEON_HPD_3:
207 WREG32(DC_HPD3_CONTROL, tmp);
208 rdev->irq.hpd[2] = true;
209 break;
210 case RADEON_HPD_4:
211 WREG32(DC_HPD4_CONTROL, tmp);
212 rdev->irq.hpd[3] = true;
213 break;
214 case RADEON_HPD_5:
215 WREG32(DC_HPD5_CONTROL, tmp);
216 rdev->irq.hpd[4] = true;
217 break;
218 case RADEON_HPD_6:
219 WREG32(DC_HPD6_CONTROL, tmp);
220 rdev->irq.hpd[5] = true;
221 break;
222 default:
223 break;
224 }
225 }
226 if (rdev->irq.installed)
227 evergreen_irq_set(rdev);
bcc1c2a1
AD		 228}
229
0ca2ab52 230void evergreen_hpd_fini(struct radeon_device *rdev)
bcc1c2a1 231{
0ca2ab52
AD		 232 struct drm_device *dev = rdev->ddev;
233 struct drm_connector *connector;
234
235 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
236 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
237 switch (radeon_connector->hpd.hpd) {
238 case RADEON_HPD_1:
239 WREG32(DC_HPD1_CONTROL, 0);
240 rdev->irq.hpd[0] = false;
241 break;
242 case RADEON_HPD_2:
243 WREG32(DC_HPD2_CONTROL, 0);
244 rdev->irq.hpd[1] = false;
245 break;
246 case RADEON_HPD_3:
247 WREG32(DC_HPD3_CONTROL, 0);
248 rdev->irq.hpd[2] = false;
249 break;
250 case RADEON_HPD_4:
251 WREG32(DC_HPD4_CONTROL, 0);
252 rdev->irq.hpd[3] = false;
253 break;
254 case RADEON_HPD_5:
255 WREG32(DC_HPD5_CONTROL, 0);
256 rdev->irq.hpd[4] = false;
257 break;
258 case RADEON_HPD_6:
259 WREG32(DC_HPD6_CONTROL, 0);
260 rdev->irq.hpd[5] = false;
261 break;
262 default:
263 break;
264 }
265 }
bcc1c2a1
AD		 266}
267
0ca2ab52 268void evergreen_bandwidth_update(struct radeon_device *rdev)
bcc1c2a1
AD		 269{
270 /* XXX */
271}
272
273static int evergreen_mc_wait_for_idle(struct radeon_device *rdev)
274{
275 unsigned i;
276 u32 tmp;
277
278 for (i = 0; i < rdev->usec_timeout; i++) {
279 /* read MC_STATUS */
280 tmp = RREG32(SRBM_STATUS) & 0x1F00;
281 if (!tmp)
282 return 0;
283 udelay(1);
284 }
285 return -1;
286}
287
288/*
289 * GART
290 */
0fcdb61e
AD		 291void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev)
292{
293 unsigned i;
294 u32 tmp;
295
296 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
297 for (i = 0; i < rdev->usec_timeout; i++) {
298 /* read MC_STATUS */
299 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
300 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
301 if (tmp == 2) {
302 printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
303 return;
304 }
305 if (tmp) {
306 return;
307 }
308 udelay(1);
309 }
310}
311
bcc1c2a1
AD		 312int evergreen_pcie_gart_enable(struct radeon_device *rdev)
313{
314 u32 tmp;
0fcdb61e 315 int r;
bcc1c2a1
AD		 316
317 if (rdev->gart.table.vram.robj == NULL) {
318 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
319 return -EINVAL;
320 }
321 r = radeon_gart_table_vram_pin(rdev);
322 if (r)
323 return r;
82568565 324 radeon_gart_restore(rdev);
bcc1c2a1
AD		 325 /* Setup L2 cache */
326 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
327 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
328 EFFECTIVE_L2_QUEUE_SIZE(7));
329 WREG32(VM_L2_CNTL2, 0);
330 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
331 /* Setup TLB control */
332 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
333 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
334 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
335 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
336 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
337 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
338 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
339 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
340 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
341 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
342 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
343 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
344 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
345 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
346 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
347 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
348 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
349 (u32)(rdev->dummy_page.addr >> 12));
0fcdb61e 350 WREG32(VM_CONTEXT1_CNTL, 0);
bcc1c2a1 351
0fcdb61e 352 evergreen_pcie_gart_tlb_flush(rdev);
bcc1c2a1
AD		 353 rdev->gart.ready = true;
354 return 0;
355}
356
357void evergreen_pcie_gart_disable(struct radeon_device *rdev)
358{
359 u32 tmp;
0fcdb61e 360 int r;
bcc1c2a1
AD		 361
362 /* Disable all tables */
0fcdb61e
AD		 363 WREG32(VM_CONTEXT0_CNTL, 0);
364 WREG32(VM_CONTEXT1_CNTL, 0);
bcc1c2a1
AD		 365
366 /* Setup L2 cache */
367 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
368 EFFECTIVE_L2_QUEUE_SIZE(7));
369 WREG32(VM_L2_CNTL2, 0);
370 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
371 /* Setup TLB control */
372 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
373 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
374 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
375 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
376 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
377 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
378 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
379 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
380 if (rdev->gart.table.vram.robj) {
381 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
382 if (likely(r == 0)) {
383 radeon_bo_kunmap(rdev->gart.table.vram.robj);
384 radeon_bo_unpin(rdev->gart.table.vram.robj);
385 radeon_bo_unreserve(rdev->gart.table.vram.robj);
386 }
387 }
388}
389
390void evergreen_pcie_gart_fini(struct radeon_device *rdev)
391{
392 evergreen_pcie_gart_disable(rdev);
393 radeon_gart_table_vram_free(rdev);
394 radeon_gart_fini(rdev);
395}
396
397
398void evergreen_agp_enable(struct radeon_device *rdev)
399{
400 u32 tmp;
bcc1c2a1
AD		 401
402 /* Setup L2 cache */
403 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
404 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
405 EFFECTIVE_L2_QUEUE_SIZE(7));
406 WREG32(VM_L2_CNTL2, 0);
407 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
408 /* Setup TLB control */
409 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
410 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
411 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
412 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
413 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
414 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
415 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
416 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
417 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
418 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
419 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
0fcdb61e
AD		 420 WREG32(VM_CONTEXT0_CNTL, 0);
421 WREG32(VM_CONTEXT1_CNTL, 0);
bcc1c2a1
AD		 422}
423
424static void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save)
425{
426 save->vga_control[0] = RREG32(D1VGA_CONTROL);
427 save->vga_control[1] = RREG32(D2VGA_CONTROL);
428 save->vga_control[2] = RREG32(EVERGREEN_D3VGA_CONTROL);
429 save->vga_control[3] = RREG32(EVERGREEN_D4VGA_CONTROL);
430 save->vga_control[4] = RREG32(EVERGREEN_D5VGA_CONTROL);
431 save->vga_control[5] = RREG32(EVERGREEN_D6VGA_CONTROL);
432 save->vga_render_control = RREG32(VGA_RENDER_CONTROL);
433 save->vga_hdp_control = RREG32(VGA_HDP_CONTROL);
434 save->crtc_control[0] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET);
435 save->crtc_control[1] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
436 save->crtc_control[2] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET);
437 save->crtc_control[3] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
438 save->crtc_control[4] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET);
439 save->crtc_control[5] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
440
441 /* Stop all video */
442 WREG32(VGA_RENDER_CONTROL, 0);
443 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);
444 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);
445 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
446 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
447 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
448 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
449 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
450 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
451 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
452 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
453 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
454 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
455 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
456 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
457 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
458 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
459 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
460 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
461
462 WREG32(D1VGA_CONTROL, 0);
463 WREG32(D2VGA_CONTROL, 0);
464 WREG32(EVERGREEN_D3VGA_CONTROL, 0);
465 WREG32(EVERGREEN_D4VGA_CONTROL, 0);
466 WREG32(EVERGREEN_D5VGA_CONTROL, 0);
467 WREG32(EVERGREEN_D6VGA_CONTROL, 0);
468}
469
470static void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save)
471{
472 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET,
473 upper_32_bits(rdev->mc.vram_start));
474 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET,
475 upper_32_bits(rdev->mc.vram_start));
476 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC0_REGISTER_OFFSET,
477 (u32)rdev->mc.vram_start);
478 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC0_REGISTER_OFFSET,
479 (u32)rdev->mc.vram_start);
480
481 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET,
482 upper_32_bits(rdev->mc.vram_start));
483 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET,
484 upper_32_bits(rdev->mc.vram_start));
485 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET,
486 (u32)rdev->mc.vram_start);
487 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET,
488 (u32)rdev->mc.vram_start);
489
490 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
491 upper_32_bits(rdev->mc.vram_start));
492 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
493 upper_32_bits(rdev->mc.vram_start));
494 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET,
495 (u32)rdev->mc.vram_start);
496 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET,
497 (u32)rdev->mc.vram_start);
498
499 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET,
500 upper_32_bits(rdev->mc.vram_start));
501 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET,
502 upper_32_bits(rdev->mc.vram_start));
503 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET,
504 (u32)rdev->mc.vram_start);
505 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET,
506 (u32)rdev->mc.vram_start);
507
508 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
509 upper_32_bits(rdev->mc.vram_start));
510 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
511 upper_32_bits(rdev->mc.vram_start));
512 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET,
513 (u32)rdev->mc.vram_start);
514 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET,
515 (u32)rdev->mc.vram_start);
516
517 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET,
518 upper_32_bits(rdev->mc.vram_start));
519 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET,
520 upper_32_bits(rdev->mc.vram_start));
521 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET,
522 (u32)rdev->mc.vram_start);
523 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET,
524 (u32)rdev->mc.vram_start);
525
526 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start));
527 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);
528 /* Unlock host access */
529 WREG32(VGA_HDP_CONTROL, save->vga_hdp_control);
530 mdelay(1);
531 /* Restore video state */
532 WREG32(D1VGA_CONTROL, save->vga_control[0]);
533 WREG32(D2VGA_CONTROL, save->vga_control[1]);
534 WREG32(EVERGREEN_D3VGA_CONTROL, save->vga_control[2]);
535 WREG32(EVERGREEN_D4VGA_CONTROL, save->vga_control[3]);
536 WREG32(EVERGREEN_D5VGA_CONTROL, save->vga_control[4]);
537 WREG32(EVERGREEN_D6VGA_CONTROL, save->vga_control[5]);
538 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);
539 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);
540 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
541 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
542 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
543 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
544 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, save->crtc_control[0]);
545 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, save->crtc_control[1]);
546 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, save->crtc_control[2]);
547 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, save->crtc_control[3]);
548 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, save->crtc_control[4]);
549 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, save->crtc_control[5]);
550 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
551 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
552 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
553 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
554 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
555 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
556 WREG32(VGA_RENDER_CONTROL, save->vga_render_control);
557}
558
559static void evergreen_mc_program(struct radeon_device *rdev)
560{
561 struct evergreen_mc_save save;
562 u32 tmp;
563 int i, j;
564
565 /* Initialize HDP */
566 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
567 WREG32((0x2c14 + j), 0x00000000);
568 WREG32((0x2c18 + j), 0x00000000);
569 WREG32((0x2c1c + j), 0x00000000);
570 WREG32((0x2c20 + j), 0x00000000);
571 WREG32((0x2c24 + j), 0x00000000);
572 }
573 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
574
575 evergreen_mc_stop(rdev, &save);
576 if (evergreen_mc_wait_for_idle(rdev)) {
577 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
578 }
579 /* Lockout access through VGA aperture*/
580 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
581 /* Update configuration */
582 if (rdev->flags & RADEON_IS_AGP) {
583 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
584 /* VRAM before AGP */
585 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
586 rdev->mc.vram_start >> 12);
587 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
588 rdev->mc.gtt_end >> 12);
589 } else {
590 /* VRAM after AGP */
591 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
592 rdev->mc.gtt_start >> 12);
593 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
594 rdev->mc.vram_end >> 12);
595 }
596 } else {
597 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
598 rdev->mc.vram_start >> 12);
599 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
600 rdev->mc.vram_end >> 12);
601 }
602 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
603 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
604 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
605 WREG32(MC_VM_FB_LOCATION, tmp);
606 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
607 WREG32(HDP_NONSURFACE_INFO, (2 << 7));
608 WREG32(HDP_NONSURFACE_SIZE, (rdev->mc.mc_vram_size - 1) | 0x3FF);
609 if (rdev->flags & RADEON_IS_AGP) {
610 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
611 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
612 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
613 } else {
614 WREG32(MC_VM_AGP_BASE, 0);
615 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
616 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
617 }
618 if (evergreen_mc_wait_for_idle(rdev)) {
619 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
620 }
621 evergreen_mc_resume(rdev, &save);
622 /* we need to own VRAM, so turn off the VGA renderer here
623 * to stop it overwriting our objects */
624 rv515_vga_render_disable(rdev);
625}
626
bcc1c2a1
AD		 627/*
628 * CP.
629 */
bcc1c2a1
AD		 630
631static int evergreen_cp_load_microcode(struct radeon_device *rdev)
632{
fe251e2f
AD		 633 const __be32 *fw_data;
634 int i;
635
636 if (!rdev->me_fw || !rdev->pfp_fw)
637 return -EINVAL;
bcc1c2a1 638
fe251e2f
AD		 639 r700_cp_stop(rdev);
640 WREG32(CP_RB_CNTL, RB_NO_UPDATE | (15 << 8) | (3 << 0));
641
642 fw_data = (const __be32 *)rdev->pfp_fw->data;
643 WREG32(CP_PFP_UCODE_ADDR, 0);
644 for (i = 0; i < EVERGREEN_PFP_UCODE_SIZE; i++)
645 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
646 WREG32(CP_PFP_UCODE_ADDR, 0);
647
648 fw_data = (const __be32 *)rdev->me_fw->data;
649 WREG32(CP_ME_RAM_WADDR, 0);
650 for (i = 0; i < EVERGREEN_PM4_UCODE_SIZE; i++)
651 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
652
653 WREG32(CP_PFP_UCODE_ADDR, 0);
654 WREG32(CP_ME_RAM_WADDR, 0);
655 WREG32(CP_ME_RAM_RADDR, 0);
bcc1c2a1
AD		 656 return 0;
657}
658
fe251e2f
AD		 659int evergreen_cp_resume(struct radeon_device *rdev)
660{
661 u32 tmp;
662 u32 rb_bufsz;
663 int r;
664
665 /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
666 WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
667 SOFT_RESET_PA |
668 SOFT_RESET_SH |
669 SOFT_RESET_VGT |
670 SOFT_RESET_SX));
671 RREG32(GRBM_SOFT_RESET);
672 mdelay(15);
673 WREG32(GRBM_SOFT_RESET, 0);
674 RREG32(GRBM_SOFT_RESET);
675
676 /* Set ring buffer size */
677 rb_bufsz = drm_order(rdev->cp.ring_size / 8);
678 tmp = RB_NO_UPDATE | (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
679#ifdef __BIG_ENDIAN
680 tmp |= BUF_SWAP_32BIT;
32fcdbf4 681#endif
fe251e2f
AD		 682 WREG32(CP_RB_CNTL, tmp);
683 WREG32(CP_SEM_WAIT_TIMER, 0x4);
684
685 /* Set the write pointer delay */
686 WREG32(CP_RB_WPTR_DELAY, 0);
687
688 /* Initialize the ring buffer's read and write pointers */
689 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
690 WREG32(CP_RB_RPTR_WR, 0);
691 WREG32(CP_RB_WPTR, 0);
692 WREG32(CP_RB_RPTR_ADDR, rdev->cp.gpu_addr & 0xFFFFFFFF);
693 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->cp.gpu_addr));
694 mdelay(1);
695 WREG32(CP_RB_CNTL, tmp);
696
697 WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8);
698 WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
699
700 rdev->cp.rptr = RREG32(CP_RB_RPTR);
701 rdev->cp.wptr = RREG32(CP_RB_WPTR);
702
703 r600_cp_start(rdev);
704 rdev->cp.ready = true;
705 r = radeon_ring_test(rdev);
706 if (r) {
707 rdev->cp.ready = false;
708 return r;
709 }
710 return 0;
711}
bcc1c2a1
AD		 712
713/*
714 * Core functions
715 */
32fcdbf4
AD		 716static u32 evergreen_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
717 u32 num_tile_pipes,
bcc1c2a1
AD		 718 u32 num_backends,
719 u32 backend_disable_mask)
720{
721 u32 backend_map = 0;
32fcdbf4
AD		 722 u32 enabled_backends_mask = 0;
723 u32 enabled_backends_count = 0;
724 u32 cur_pipe;
725 u32 swizzle_pipe[EVERGREEN_MAX_PIPES];
726 u32 cur_backend = 0;
727 u32 i;
728 bool force_no_swizzle;
729
730 if (num_tile_pipes > EVERGREEN_MAX_PIPES)
731 num_tile_pipes = EVERGREEN_MAX_PIPES;
732 if (num_tile_pipes < 1)
733 num_tile_pipes = 1;
734 if (num_backends > EVERGREEN_MAX_BACKENDS)
735 num_backends = EVERGREEN_MAX_BACKENDS;
736 if (num_backends < 1)
737 num_backends = 1;
738
739 for (i = 0; i < EVERGREEN_MAX_BACKENDS; ++i) {
740 if (((backend_disable_mask >> i) & 1) == 0) {
741 enabled_backends_mask |= (1 << i);
742 ++enabled_backends_count;
743 }
744 if (enabled_backends_count == num_backends)
745 break;
746 }
747
748 if (enabled_backends_count == 0) {
749 enabled_backends_mask = 1;
750 enabled_backends_count = 1;
751 }
752
753 if (enabled_backends_count != num_backends)
754 num_backends = enabled_backends_count;
755
756 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * EVERGREEN_MAX_PIPES);
757 switch (rdev->family) {
758 case CHIP_CEDAR:
759 case CHIP_REDWOOD:
760 force_no_swizzle = false;
761 break;
762 case CHIP_CYPRESS:
763 case CHIP_HEMLOCK:
764 case CHIP_JUNIPER:
765 default:
766 force_no_swizzle = true;
767 break;
768 }
769 if (force_no_swizzle) {
770 bool last_backend_enabled = false;
771
772 force_no_swizzle = false;
773 for (i = 0; i < EVERGREEN_MAX_BACKENDS; ++i) {
774 if (((enabled_backends_mask >> i) & 1) == 1) {
775 if (last_backend_enabled)
776 force_no_swizzle = true;
777 last_backend_enabled = true;
778 } else
779 last_backend_enabled = false;
780 }
781 }
782
783 switch (num_tile_pipes) {
784 case 1:
785 case 3:
786 case 5:
787 case 7:
788 DRM_ERROR("odd number of pipes!\n");
789 break;
790 case 2:
791 swizzle_pipe[0] = 0;
792 swizzle_pipe[1] = 1;
793 break;
794 case 4:
795 if (force_no_swizzle) {
796 swizzle_pipe[0] = 0;
797 swizzle_pipe[1] = 1;
798 swizzle_pipe[2] = 2;
799 swizzle_pipe[3] = 3;
800 } else {
801 swizzle_pipe[0] = 0;
802 swizzle_pipe[1] = 2;
803 swizzle_pipe[2] = 1;
804 swizzle_pipe[3] = 3;
805 }
806 break;
807 case 6:
808 if (force_no_swizzle) {
809 swizzle_pipe[0] = 0;
810 swizzle_pipe[1] = 1;
811 swizzle_pipe[2] = 2;
812 swizzle_pipe[3] = 3;
813 swizzle_pipe[4] = 4;
814 swizzle_pipe[5] = 5;
815 } else {
816 swizzle_pipe[0] = 0;
817 swizzle_pipe[1] = 2;
818 swizzle_pipe[2] = 4;
819 swizzle_pipe[3] = 1;
820 swizzle_pipe[4] = 3;
821 swizzle_pipe[5] = 5;
822 }
823 break;
824 case 8:
825 if (force_no_swizzle) {
826 swizzle_pipe[0] = 0;
827 swizzle_pipe[1] = 1;
828 swizzle_pipe[2] = 2;
829 swizzle_pipe[3] = 3;
830 swizzle_pipe[4] = 4;
831 swizzle_pipe[5] = 5;
832 swizzle_pipe[6] = 6;
833 swizzle_pipe[7] = 7;
834 } else {
835 swizzle_pipe[0] = 0;
836 swizzle_pipe[1] = 2;
837 swizzle_pipe[2] = 4;
838 swizzle_pipe[3] = 6;
839 swizzle_pipe[4] = 1;
840 swizzle_pipe[5] = 3;
841 swizzle_pipe[6] = 5;
842 swizzle_pipe[7] = 7;
843 }
844 break;
845 }
846
847 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
848 while (((1 << cur_backend) & enabled_backends_mask) == 0)
849 cur_backend = (cur_backend + 1) % EVERGREEN_MAX_BACKENDS;
850
851 backend_map |= (((cur_backend & 0xf) << (swizzle_pipe[cur_pipe] * 4)));
852
853 cur_backend = (cur_backend + 1) % EVERGREEN_MAX_BACKENDS;
854 }
bcc1c2a1
AD		 855
856 return backend_map;
857}
bcc1c2a1
AD		 858
859static void evergreen_gpu_init(struct radeon_device *rdev)
860{
32fcdbf4
AD		 861 u32 cc_rb_backend_disable = 0;
862 u32 cc_gc_shader_pipe_config;
863 u32 gb_addr_config = 0;
864 u32 mc_shared_chmap, mc_arb_ramcfg;
865 u32 gb_backend_map;
866 u32 grbm_gfx_index;
867 u32 sx_debug_1;
868 u32 smx_dc_ctl0;
869 u32 sq_config;
870 u32 sq_lds_resource_mgmt;
871 u32 sq_gpr_resource_mgmt_1;
872 u32 sq_gpr_resource_mgmt_2;
873 u32 sq_gpr_resource_mgmt_3;
874 u32 sq_thread_resource_mgmt;
875 u32 sq_thread_resource_mgmt_2;
876 u32 sq_stack_resource_mgmt_1;
877 u32 sq_stack_resource_mgmt_2;
878 u32 sq_stack_resource_mgmt_3;
879 u32 vgt_cache_invalidation;
880 u32 hdp_host_path_cntl;
881 int i, j, num_shader_engines, ps_thread_count;
882
883 switch (rdev->family) {
884 case CHIP_CYPRESS:
885 case CHIP_HEMLOCK:
886 rdev->config.evergreen.num_ses = 2;
887 rdev->config.evergreen.max_pipes = 4;
888 rdev->config.evergreen.max_tile_pipes = 8;
889 rdev->config.evergreen.max_simds = 10;
890 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
891 rdev->config.evergreen.max_gprs = 256;
892 rdev->config.evergreen.max_threads = 248;
893 rdev->config.evergreen.max_gs_threads = 32;
894 rdev->config.evergreen.max_stack_entries = 512;
895 rdev->config.evergreen.sx_num_of_sets = 4;
896 rdev->config.evergreen.sx_max_export_size = 256;
897 rdev->config.evergreen.sx_max_export_pos_size = 64;
898 rdev->config.evergreen.sx_max_export_smx_size = 192;
899 rdev->config.evergreen.max_hw_contexts = 8;
900 rdev->config.evergreen.sq_num_cf_insts = 2;
901
902 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
903 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
904 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
905 break;
906 case CHIP_JUNIPER:
907 rdev->config.evergreen.num_ses = 1;
908 rdev->config.evergreen.max_pipes = 4;
909 rdev->config.evergreen.max_tile_pipes = 4;
910 rdev->config.evergreen.max_simds = 10;
911 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
912 rdev->config.evergreen.max_gprs = 256;
913 rdev->config.evergreen.max_threads = 248;
914 rdev->config.evergreen.max_gs_threads = 32;
915 rdev->config.evergreen.max_stack_entries = 512;
916 rdev->config.evergreen.sx_num_of_sets = 4;
917 rdev->config.evergreen.sx_max_export_size = 256;
918 rdev->config.evergreen.sx_max_export_pos_size = 64;
919 rdev->config.evergreen.sx_max_export_smx_size = 192;
920 rdev->config.evergreen.max_hw_contexts = 8;
921 rdev->config.evergreen.sq_num_cf_insts = 2;
922
923 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
924 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
925 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
926 break;
927 case CHIP_REDWOOD:
928 rdev->config.evergreen.num_ses = 1;
929 rdev->config.evergreen.max_pipes = 4;
930 rdev->config.evergreen.max_tile_pipes = 4;
931 rdev->config.evergreen.max_simds = 5;
932 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
933 rdev->config.evergreen.max_gprs = 256;
934 rdev->config.evergreen.max_threads = 248;
935 rdev->config.evergreen.max_gs_threads = 32;
936 rdev->config.evergreen.max_stack_entries = 256;
937 rdev->config.evergreen.sx_num_of_sets = 4;
938 rdev->config.evergreen.sx_max_export_size = 256;
939 rdev->config.evergreen.sx_max_export_pos_size = 64;
940 rdev->config.evergreen.sx_max_export_smx_size = 192;
941 rdev->config.evergreen.max_hw_contexts = 8;
942 rdev->config.evergreen.sq_num_cf_insts = 2;
943
944 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
945 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
946 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
947 break;
948 case CHIP_CEDAR:
949 default:
950 rdev->config.evergreen.num_ses = 1;
951 rdev->config.evergreen.max_pipes = 2;
952 rdev->config.evergreen.max_tile_pipes = 2;
953 rdev->config.evergreen.max_simds = 2;
954 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
955 rdev->config.evergreen.max_gprs = 256;
956 rdev->config.evergreen.max_threads = 192;
957 rdev->config.evergreen.max_gs_threads = 16;
958 rdev->config.evergreen.max_stack_entries = 256;
959 rdev->config.evergreen.sx_num_of_sets = 4;
960 rdev->config.evergreen.sx_max_export_size = 128;
961 rdev->config.evergreen.sx_max_export_pos_size = 32;
962 rdev->config.evergreen.sx_max_export_smx_size = 96;
963 rdev->config.evergreen.max_hw_contexts = 4;
964 rdev->config.evergreen.sq_num_cf_insts = 1;
965
966 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
967 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
968 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
969 break;
970 }
971
972 /* Initialize HDP */
973 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
974 WREG32((0x2c14 + j), 0x00000000);
975 WREG32((0x2c18 + j), 0x00000000);
976 WREG32((0x2c1c + j), 0x00000000);
977 WREG32((0x2c20 + j), 0x00000000);
978 WREG32((0x2c24 + j), 0x00000000);
979 }
980
981 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
982
983 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & ~2;
984
985 cc_gc_shader_pipe_config |=
986 INACTIVE_QD_PIPES((EVERGREEN_MAX_PIPES_MASK << rdev->config.evergreen.max_pipes)
987 & EVERGREEN_MAX_PIPES_MASK);
988 cc_gc_shader_pipe_config |=
989 INACTIVE_SIMDS((EVERGREEN_MAX_SIMDS_MASK << rdev->config.evergreen.max_simds)
990 & EVERGREEN_MAX_SIMDS_MASK);
991
992 cc_rb_backend_disable =
993 BACKEND_DISABLE((EVERGREEN_MAX_BACKENDS_MASK << rdev->config.evergreen.max_backends)
994 & EVERGREEN_MAX_BACKENDS_MASK);
995
996
997 mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
998 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
999
1000 switch (rdev->config.evergreen.max_tile_pipes) {
1001 case 1:
1002 default:
1003 gb_addr_config |= NUM_PIPES(0);
1004 break;
1005 case 2:
1006 gb_addr_config |= NUM_PIPES(1);
1007 break;
1008 case 4:
1009 gb_addr_config |= NUM_PIPES(2);
1010 break;
1011 case 8:
1012 gb_addr_config |= NUM_PIPES(3);
1013 break;
1014 }
1015
1016 gb_addr_config |= PIPE_INTERLEAVE_SIZE((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
1017 gb_addr_config |= BANK_INTERLEAVE_SIZE(0);
1018 gb_addr_config |= NUM_SHADER_ENGINES(rdev->config.evergreen.num_ses - 1);
1019 gb_addr_config |= SHADER_ENGINE_TILE_SIZE(1);
1020 gb_addr_config |= NUM_GPUS(0); /* Hemlock? */
1021 gb_addr_config |= MULTI_GPU_TILE_SIZE(2);
1022
1023 if (((mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) > 2)
1024 gb_addr_config |= ROW_SIZE(2);
1025 else
1026 gb_addr_config |= ROW_SIZE((mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT);
1027
1028 if (rdev->ddev->pdev->device == 0x689e) {
1029 u32 efuse_straps_4;
1030 u32 efuse_straps_3;
1031 u8 efuse_box_bit_131_124;
1032
1033 WREG32(RCU_IND_INDEX, 0x204);
1034 efuse_straps_4 = RREG32(RCU_IND_DATA);
1035 WREG32(RCU_IND_INDEX, 0x203);
1036 efuse_straps_3 = RREG32(RCU_IND_DATA);
1037 efuse_box_bit_131_124 = (u8)(((efuse_straps_4 & 0xf) << 4) | ((efuse_straps_3 & 0xf0000000) >> 28));
1038
1039 switch(efuse_box_bit_131_124) {
1040 case 0x00:
1041 gb_backend_map = 0x76543210;
1042 break;
1043 case 0x55:
1044 gb_backend_map = 0x77553311;
1045 break;
1046 case 0x56:
1047 gb_backend_map = 0x77553300;
1048 break;
1049 case 0x59:
1050 gb_backend_map = 0x77552211;
1051 break;
1052 case 0x66:
1053 gb_backend_map = 0x77443300;
1054 break;
1055 case 0x99:
1056 gb_backend_map = 0x66552211;
1057 break;
1058 case 0x5a:
1059 gb_backend_map = 0x77552200;
1060 break;
1061 case 0xaa:
1062 gb_backend_map = 0x66442200;
1063 break;
1064 case 0x95:
1065 gb_backend_map = 0x66553311;
1066 break;
1067 default:
1068 DRM_ERROR("bad backend map, using default\n");
1069 gb_backend_map =
1070 evergreen_get_tile_pipe_to_backend_map(rdev,
1071 rdev->config.evergreen.max_tile_pipes,
1072 rdev->config.evergreen.max_backends,
1073 ((EVERGREEN_MAX_BACKENDS_MASK <<
1074 rdev->config.evergreen.max_backends) &
1075 EVERGREEN_MAX_BACKENDS_MASK));
1076 break;
1077 }
1078 } else if (rdev->ddev->pdev->device == 0x68b9) {
1079 u32 efuse_straps_3;
1080 u8 efuse_box_bit_127_124;
1081
1082 WREG32(RCU_IND_INDEX, 0x203);
1083 efuse_straps_3 = RREG32(RCU_IND_DATA);
1084 efuse_box_bit_127_124 = (u8)(efuse_straps_3 & 0xF0000000) >> 28;
1085
1086 switch(efuse_box_bit_127_124) {
1087 case 0x0:
1088 gb_backend_map = 0x00003210;
1089 break;
1090 case 0x5:
1091 case 0x6:
1092 case 0x9:
1093 case 0xa:
1094 gb_backend_map = 0x00003311;
1095 break;
1096 default:
1097 DRM_ERROR("bad backend map, using default\n");
1098 gb_backend_map =
1099 evergreen_get_tile_pipe_to_backend_map(rdev,
1100 rdev->config.evergreen.max_tile_pipes,
1101 rdev->config.evergreen.max_backends,
1102 ((EVERGREEN_MAX_BACKENDS_MASK <<
1103 rdev->config.evergreen.max_backends) &
1104 EVERGREEN_MAX_BACKENDS_MASK));
1105 break;
1106 }
1107 } else
1108 gb_backend_map =
1109 evergreen_get_tile_pipe_to_backend_map(rdev,
1110 rdev->config.evergreen.max_tile_pipes,
1111 rdev->config.evergreen.max_backends,
1112 ((EVERGREEN_MAX_BACKENDS_MASK <<
1113 rdev->config.evergreen.max_backends) &
1114 EVERGREEN_MAX_BACKENDS_MASK));
1115
1116 WREG32(GB_BACKEND_MAP, gb_backend_map);
1117 WREG32(GB_ADDR_CONFIG, gb_addr_config);
1118 WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
1119 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
1120
1121 num_shader_engines = ((RREG32(GB_ADDR_CONFIG) & NUM_SHADER_ENGINES(3)) >> 12) + 1;
1122 grbm_gfx_index = INSTANCE_BROADCAST_WRITES;
1123
1124 for (i = 0; i < rdev->config.evergreen.num_ses; i++) {
1125 u32 rb = cc_rb_backend_disable | (0xf0 << 16);
1126 u32 sp = cc_gc_shader_pipe_config;
1127 u32 gfx = grbm_gfx_index | SE_INDEX(i);
1128
1129 if (i == num_shader_engines) {
1130 rb |= BACKEND_DISABLE(EVERGREEN_MAX_BACKENDS_MASK);
1131 sp |= INACTIVE_SIMDS(EVERGREEN_MAX_SIMDS_MASK);
1132 }
1133
1134 WREG32(GRBM_GFX_INDEX, gfx);
1135 WREG32(RLC_GFX_INDEX, gfx);
1136
1137 WREG32(CC_RB_BACKEND_DISABLE, rb);
1138 WREG32(CC_SYS_RB_BACKEND_DISABLE, rb);
1139 WREG32(GC_USER_RB_BACKEND_DISABLE, rb);
1140 WREG32(CC_GC_SHADER_PIPE_CONFIG, sp);
1141 }
1142
1143 grbm_gfx_index |= SE_BROADCAST_WRITES;
1144 WREG32(GRBM_GFX_INDEX, grbm_gfx_index);
1145 WREG32(RLC_GFX_INDEX, grbm_gfx_index);
1146
1147 WREG32(CGTS_SYS_TCC_DISABLE, 0);
1148 WREG32(CGTS_TCC_DISABLE, 0);
1149 WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
1150 WREG32(CGTS_USER_TCC_DISABLE, 0);
1151
1152 /* set HW defaults for 3D engine */
1153 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
1154 ROQ_IB2_START(0x2b)));
1155
1156 WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
1157
1158 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO |
1159 SYNC_GRADIENT |
1160 SYNC_WALKER |
1161 SYNC_ALIGNER));
1162
1163 sx_debug_1 = RREG32(SX_DEBUG_1);
1164 sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
1165 WREG32(SX_DEBUG_1, sx_debug_1);
1166
1167
1168 smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
1169 smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff);
1170 smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.evergreen.sx_num_of_sets);
1171 WREG32(SMX_DC_CTL0, smx_dc_ctl0);
1172
1173 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_size / 4) - 1) |
1174 POSITION_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_pos_size / 4) - 1) |
1175 SMX_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_smx_size / 4) - 1)));
1176
1177 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.evergreen.sc_prim_fifo_size) |
1178 SC_HIZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_hiz_tile_fifo_size) |
1179 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_earlyz_tile_fifo_size)));
1180
1181 WREG32(VGT_NUM_INSTANCES, 1);
1182 WREG32(SPI_CONFIG_CNTL, 0);
1183 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
1184 WREG32(CP_PERFMON_CNTL, 0);
1185
1186 WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.evergreen.sq_num_cf_insts) |
1187 FETCH_FIFO_HIWATER(0x4) |
1188 DONE_FIFO_HIWATER(0xe0) |
1189 ALU_UPDATE_FIFO_HIWATER(0x8)));
1190
1191 sq_config = RREG32(SQ_CONFIG);
1192 sq_config &= ~(PS_PRIO(3) |
1193 VS_PRIO(3) |
1194 GS_PRIO(3) |
1195 ES_PRIO(3));
1196 sq_config |= (VC_ENABLE |
1197 EXPORT_SRC_C |
1198 PS_PRIO(0) |
1199 VS_PRIO(1) |
1200 GS_PRIO(2) |
1201 ES_PRIO(3));
1202
1203 if (rdev->family == CHIP_CEDAR)
1204 /* no vertex cache */
1205 sq_config &= ~VC_ENABLE;
1206
1207 sq_lds_resource_mgmt = RREG32(SQ_LDS_RESOURCE_MGMT);
1208
1209 sq_gpr_resource_mgmt_1 = NUM_PS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2))* 12 / 32);
1210 sq_gpr_resource_mgmt_1 |= NUM_VS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 6 / 32);
1211 sq_gpr_resource_mgmt_1 |= NUM_CLAUSE_TEMP_GPRS(4);
1212 sq_gpr_resource_mgmt_2 = NUM_GS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
1213 sq_gpr_resource_mgmt_2 |= NUM_ES_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
1214 sq_gpr_resource_mgmt_3 = NUM_HS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
1215 sq_gpr_resource_mgmt_3 |= NUM_LS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
1216
1217 if (rdev->family == CHIP_CEDAR)
1218 ps_thread_count = 96;
1219 else
1220 ps_thread_count = 128;
1221
1222 sq_thread_resource_mgmt = NUM_PS_THREADS(ps_thread_count);
1223 sq_thread_resource_mgmt |= NUM_VS_THREADS(((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8;
1224 sq_thread_resource_mgmt |= NUM_GS_THREADS(((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8;
1225 sq_thread_resource_mgmt |= NUM_ES_THREADS(((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8;
1226 sq_thread_resource_mgmt_2 = NUM_HS_THREADS(((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8;
1227 sq_thread_resource_mgmt_2 |= NUM_LS_THREADS(((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8;
1228
1229 sq_stack_resource_mgmt_1 = NUM_PS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
1230 sq_stack_resource_mgmt_1 |= NUM_VS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
1231 sq_stack_resource_mgmt_2 = NUM_GS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
1232 sq_stack_resource_mgmt_2 |= NUM_ES_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
1233 sq_stack_resource_mgmt_3 = NUM_HS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
1234 sq_stack_resource_mgmt_3 |= NUM_LS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
1235
1236 WREG32(SQ_CONFIG, sq_config);
1237 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
1238 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
1239 WREG32(SQ_GPR_RESOURCE_MGMT_3, sq_gpr_resource_mgmt_3);
1240 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1241 WREG32(SQ_THREAD_RESOURCE_MGMT_2, sq_thread_resource_mgmt_2);
1242 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
1243 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
1244 WREG32(SQ_STACK_RESOURCE_MGMT_3, sq_stack_resource_mgmt_3);
1245 WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
1246 WREG32(SQ_LDS_RESOURCE_MGMT, sq_lds_resource_mgmt);
1247
1248 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
1249 FORCE_EOV_MAX_REZ_CNT(255)));
1250
1251 if (rdev->family == CHIP_CEDAR)
1252 vgt_cache_invalidation = CACHE_INVALIDATION(TC_ONLY);
1253 else
1254 vgt_cache_invalidation = CACHE_INVALIDATION(VC_AND_TC);
1255 vgt_cache_invalidation |= AUTO_INVLD_EN(ES_AND_GS_AUTO);
1256 WREG32(VGT_CACHE_INVALIDATION, vgt_cache_invalidation);
1257
1258 WREG32(VGT_GS_VERTEX_REUSE, 16);
1259 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1260
1261 WREG32(CB_PERF_CTR0_SEL_0, 0);
1262 WREG32(CB_PERF_CTR0_SEL_1, 0);
1263 WREG32(CB_PERF_CTR1_SEL_0, 0);
1264 WREG32(CB_PERF_CTR1_SEL_1, 0);
1265 WREG32(CB_PERF_CTR2_SEL_0, 0);
1266 WREG32(CB_PERF_CTR2_SEL_1, 0);
1267 WREG32(CB_PERF_CTR3_SEL_0, 0);
1268 WREG32(CB_PERF_CTR3_SEL_1, 0);
1269
1270 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
1271 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1272
1273 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
1274
1275 udelay(50);
1276
bcc1c2a1
AD		 1277}
1278
1279int evergreen_mc_init(struct radeon_device *rdev)
1280{
bcc1c2a1
AD		 1281 u32 tmp;
1282 int chansize, numchan;
bcc1c2a1
AD		 1283
1284 /* Get VRAM informations */
1285 rdev->mc.vram_is_ddr = true;
1286 tmp = RREG32(MC_ARB_RAMCFG);
1287 if (tmp & CHANSIZE_OVERRIDE) {
1288 chansize = 16;
1289 } else if (tmp & CHANSIZE_MASK) {
1290 chansize = 64;
1291 } else {
1292 chansize = 32;
1293 }
1294 tmp = RREG32(MC_SHARED_CHMAP);
1295 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1296 case 0:
1297 default:
1298 numchan = 1;
1299 break;
1300 case 1:
1301 numchan = 2;
1302 break;
1303 case 2:
1304 numchan = 4;
1305 break;
1306 case 3:
1307 numchan = 8;
1308 break;
1309 }
1310 rdev->mc.vram_width = numchan * chansize;
1311 /* Could aper size report 0 ? */
1312 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
1313 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
1314 /* Setup GPU memory space */
1315 /* size in MB on evergreen */
1316 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
1317 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
51e5fcd3 1318 rdev->mc.visible_vram_size = rdev->mc.aper_size;
d594e46a 1319 r600_vram_gtt_location(rdev, &rdev->mc);
f47299c5
AD		 1320 radeon_update_bandwidth_info(rdev);
1321
bcc1c2a1
AD		 1322 return 0;
1323}
d594e46a 1324
225758d8
JG		 1325bool evergreen_gpu_is_lockup(struct radeon_device *rdev)
1326{
1327 /* FIXME: implement for evergreen */
1328 return false;
1329}
1330
747943ea 1331static int evergreen_gpu_soft_reset(struct radeon_device *rdev)
bcc1c2a1 1332{
747943ea
AD		 1333 struct evergreen_mc_save save;
1334 u32 srbm_reset = 0;
1335 u32 grbm_reset = 0;
1336
1337 dev_info(rdev->dev, "GPU softreset \n");
1338 dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
1339 RREG32(GRBM_STATUS));
1340 dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
1341 RREG32(GRBM_STATUS_SE0));
1342 dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
1343 RREG32(GRBM_STATUS_SE1));
1344 dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
1345 RREG32(SRBM_STATUS));
1346 evergreen_mc_stop(rdev, &save);
1347 if (evergreen_mc_wait_for_idle(rdev)) {
1348 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1349 }
1350 /* Disable CP parsing/prefetching */
1351 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
1352
1353 /* reset all the gfx blocks */
1354 grbm_reset = (SOFT_RESET_CP |
1355 SOFT_RESET_CB |
1356 SOFT_RESET_DB |
1357 SOFT_RESET_PA |
1358 SOFT_RESET_SC |
1359 SOFT_RESET_SPI |
1360 SOFT_RESET_SH |
1361 SOFT_RESET_SX |
1362 SOFT_RESET_TC |
1363 SOFT_RESET_TA |
1364 SOFT_RESET_VC |
1365 SOFT_RESET_VGT);
1366
1367 dev_info(rdev->dev, " GRBM_SOFT_RESET=0x%08X\n", grbm_reset);
1368 WREG32(GRBM_SOFT_RESET, grbm_reset);
1369 (void)RREG32(GRBM_SOFT_RESET);
1370 udelay(50);
1371 WREG32(GRBM_SOFT_RESET, 0);
1372 (void)RREG32(GRBM_SOFT_RESET);
1373
1374 /* reset all the system blocks */
1375 srbm_reset = SRBM_SOFT_RESET_ALL_MASK;
1376
1377 dev_info(rdev->dev, " SRBM_SOFT_RESET=0x%08X\n", srbm_reset);
1378 WREG32(SRBM_SOFT_RESET, srbm_reset);
1379 (void)RREG32(SRBM_SOFT_RESET);
1380 udelay(50);
1381 WREG32(SRBM_SOFT_RESET, 0);
1382 (void)RREG32(SRBM_SOFT_RESET);
1383 /* Wait a little for things to settle down */
1384 udelay(50);
1385 dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
1386 RREG32(GRBM_STATUS));
1387 dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
1388 RREG32(GRBM_STATUS_SE0));
1389 dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
1390 RREG32(GRBM_STATUS_SE1));
1391 dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
1392 RREG32(SRBM_STATUS));
1393 /* After reset we need to reinit the asic as GPU often endup in an
1394 * incoherent state.
1395 */
1396 atom_asic_init(rdev->mode_info.atom_context);
1397 evergreen_mc_resume(rdev, &save);
bcc1c2a1
AD		 1398 return 0;
1399}
1400
a2d07b74 1401int evergreen_asic_reset(struct radeon_device *rdev)
bcc1c2a1 1402{
747943ea
AD		 1403 return evergreen_gpu_soft_reset(rdev);
1404}
1405
45f9a39b
AD		 1406/* Interrupts */
1407
1408u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc)
1409{
1410 switch (crtc) {
1411 case 0:
1412 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC0_REGISTER_OFFSET);
1413 case 1:
1414 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC1_REGISTER_OFFSET);
1415 case 2:
1416 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC2_REGISTER_OFFSET);
1417 case 3:
1418 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC3_REGISTER_OFFSET);
1419 case 4:
1420 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC4_REGISTER_OFFSET);
1421 case 5:
1422 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC5_REGISTER_OFFSET);
1423 default:
1424 return 0;
1425 }
1426}
1427
1428void evergreen_disable_interrupt_state(struct radeon_device *rdev)
1429{
1430 u32 tmp;
1431
1432 WREG32(CP_INT_CNTL, 0);
1433 WREG32(GRBM_INT_CNTL, 0);
1434 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1435 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
1436 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1437 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
1438 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1439 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1440
1441 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1442 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
1443 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1444 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
1445 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1446 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1447
1448 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
1449 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
1450
1451 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
1452 WREG32(DC_HPD1_INT_CONTROL, tmp);
1453 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
1454 WREG32(DC_HPD2_INT_CONTROL, tmp);
1455 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
1456 WREG32(DC_HPD3_INT_CONTROL, tmp);
1457 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
1458 WREG32(DC_HPD4_INT_CONTROL, tmp);
1459 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
1460 WREG32(DC_HPD5_INT_CONTROL, tmp);
1461 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
1462 WREG32(DC_HPD6_INT_CONTROL, tmp);
1463
1464}
1465
1466int evergreen_irq_set(struct radeon_device *rdev)
1467{
1468 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
1469 u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0;
1470 u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6;
2031f77c 1471 u32 grbm_int_cntl = 0;
45f9a39b
AD		 1472
1473 if (!rdev->irq.installed) {
1474 WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n");
1475 return -EINVAL;
1476 }
1477 /* don't enable anything if the ih is disabled */
1478 if (!rdev->ih.enabled) {
1479 r600_disable_interrupts(rdev);
1480 /* force the active interrupt state to all disabled */
1481 evergreen_disable_interrupt_state(rdev);
1482 return 0;
1483 }
1484
1485 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
1486 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
1487 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
1488 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
1489 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
1490 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
1491
1492 if (rdev->irq.sw_int) {
1493 DRM_DEBUG("evergreen_irq_set: sw int\n");
1494 cp_int_cntl |= RB_INT_ENABLE;
1495 }
1496 if (rdev->irq.crtc_vblank_int[0]) {
1497 DRM_DEBUG("evergreen_irq_set: vblank 0\n");
1498 crtc1 |= VBLANK_INT_MASK;
1499 }
1500 if (rdev->irq.crtc_vblank_int[1]) {
1501 DRM_DEBUG("evergreen_irq_set: vblank 1\n");
1502 crtc2 |= VBLANK_INT_MASK;
1503 }
1504 if (rdev->irq.crtc_vblank_int[2]) {
1505 DRM_DEBUG("evergreen_irq_set: vblank 2\n");
1506 crtc3 |= VBLANK_INT_MASK;
1507 }
1508 if (rdev->irq.crtc_vblank_int[3]) {
1509 DRM_DEBUG("evergreen_irq_set: vblank 3\n");
1510 crtc4 |= VBLANK_INT_MASK;
1511 }
1512 if (rdev->irq.crtc_vblank_int[4]) {
1513 DRM_DEBUG("evergreen_irq_set: vblank 4\n");
1514 crtc5 |= VBLANK_INT_MASK;
1515 }
1516 if (rdev->irq.crtc_vblank_int[5]) {
1517 DRM_DEBUG("evergreen_irq_set: vblank 5\n");
1518 crtc6 |= VBLANK_INT_MASK;
1519 }
1520 if (rdev->irq.hpd[0]) {
1521 DRM_DEBUG("evergreen_irq_set: hpd 1\n");
1522 hpd1 |= DC_HPDx_INT_EN;
1523 }
1524 if (rdev->irq.hpd[1]) {
1525 DRM_DEBUG("evergreen_irq_set: hpd 2\n");
1526 hpd2 |= DC_HPDx_INT_EN;
1527 }
1528 if (rdev->irq.hpd[2]) {
1529 DRM_DEBUG("evergreen_irq_set: hpd 3\n");
1530 hpd3 |= DC_HPDx_INT_EN;
1531 }
1532 if (rdev->irq.hpd[3]) {
1533 DRM_DEBUG("evergreen_irq_set: hpd 4\n");
1534 hpd4 |= DC_HPDx_INT_EN;
1535 }
1536 if (rdev->irq.hpd[4]) {
1537 DRM_DEBUG("evergreen_irq_set: hpd 5\n");
1538 hpd5 |= DC_HPDx_INT_EN;
1539 }
1540 if (rdev->irq.hpd[5]) {
1541 DRM_DEBUG("evergreen_irq_set: hpd 6\n");
1542 hpd6 |= DC_HPDx_INT_EN;
1543 }
2031f77c
AD		 1544 if (rdev->irq.gui_idle) {
1545 DRM_DEBUG("gui idle\n");
1546 grbm_int_cntl |= GUI_IDLE_INT_ENABLE;
1547 }
45f9a39b
AD		 1548
1549 WREG32(CP_INT_CNTL, cp_int_cntl);
2031f77c 1550 WREG32(GRBM_INT_CNTL, grbm_int_cntl);
45f9a39b
AD		 1551
1552 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);
1553 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2);
1554 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3);
1555 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4);
1556 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5);
1557 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);
1558
1559 WREG32(DC_HPD1_INT_CONTROL, hpd1);
1560 WREG32(DC_HPD2_INT_CONTROL, hpd2);
1561 WREG32(DC_HPD3_INT_CONTROL, hpd3);
1562 WREG32(DC_HPD4_INT_CONTROL, hpd4);
1563 WREG32(DC_HPD5_INT_CONTROL, hpd5);
1564 WREG32(DC_HPD6_INT_CONTROL, hpd6);
1565
bcc1c2a1
AD		 1566 return 0;
1567}
1568
45f9a39b
AD		 1569static inline void evergreen_irq_ack(struct radeon_device *rdev,
1570 u32 *disp_int,
1571 u32 *disp_int_cont,
1572 u32 *disp_int_cont2,
1573 u32 *disp_int_cont3,
1574 u32 *disp_int_cont4,
1575 u32 *disp_int_cont5)
1576{
1577 u32 tmp;
1578
1579 *disp_int = RREG32(DISP_INTERRUPT_STATUS);
1580 *disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
1581 *disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2);
1582 *disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3);
1583 *disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4);
1584 *disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5);
1585
1586 if (*disp_int & LB_D1_VBLANK_INTERRUPT)
1587 WREG32(VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK);
1588 if (*disp_int & LB_D1_VLINE_INTERRUPT)
1589 WREG32(VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK);
1590
1591 if (*disp_int_cont & LB_D2_VBLANK_INTERRUPT)
1592 WREG32(VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK);
1593 if (*disp_int_cont & LB_D2_VLINE_INTERRUPT)
1594 WREG32(VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK);
1595
1596 if (*disp_int_cont2 & LB_D3_VBLANK_INTERRUPT)
1597 WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK);
1598 if (*disp_int_cont2 & LB_D3_VLINE_INTERRUPT)
1599 WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK);
1600
1601 if (*disp_int_cont3 & LB_D4_VBLANK_INTERRUPT)
1602 WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK);
1603 if (*disp_int_cont3 & LB_D4_VLINE_INTERRUPT)
1604 WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK);
1605
1606 if (*disp_int_cont4 & LB_D5_VBLANK_INTERRUPT)
1607 WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK);
1608 if (*disp_int_cont4 & LB_D5_VLINE_INTERRUPT)
1609 WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK);
1610
1611 if (*disp_int_cont5 & LB_D6_VBLANK_INTERRUPT)
1612 WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK);
1613 if (*disp_int_cont5 & LB_D6_VLINE_INTERRUPT)
1614 WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK);
1615
1616 if (*disp_int & DC_HPD1_INTERRUPT) {
1617 tmp = RREG32(DC_HPD1_INT_CONTROL);
1618 tmp |= DC_HPDx_INT_ACK;
1619 WREG32(DC_HPD1_INT_CONTROL, tmp);
1620 }
1621 if (*disp_int_cont & DC_HPD2_INTERRUPT) {
1622 tmp = RREG32(DC_HPD2_INT_CONTROL);
1623 tmp |= DC_HPDx_INT_ACK;
1624 WREG32(DC_HPD2_INT_CONTROL, tmp);
1625 }
1626 if (*disp_int_cont2 & DC_HPD3_INTERRUPT) {
1627 tmp = RREG32(DC_HPD3_INT_CONTROL);
1628 tmp |= DC_HPDx_INT_ACK;
1629 WREG32(DC_HPD3_INT_CONTROL, tmp);
1630 }
1631 if (*disp_int_cont3 & DC_HPD4_INTERRUPT) {
1632 tmp = RREG32(DC_HPD4_INT_CONTROL);
1633 tmp |= DC_HPDx_INT_ACK;
1634 WREG32(DC_HPD4_INT_CONTROL, tmp);
1635 }
1636 if (*disp_int_cont4 & DC_HPD5_INTERRUPT) {
1637 tmp = RREG32(DC_HPD5_INT_CONTROL);
1638 tmp |= DC_HPDx_INT_ACK;
1639 WREG32(DC_HPD5_INT_CONTROL, tmp);
1640 }
1641 if (*disp_int_cont5 & DC_HPD6_INTERRUPT) {
1642 tmp = RREG32(DC_HPD5_INT_CONTROL);
1643 tmp |= DC_HPDx_INT_ACK;
1644 WREG32(DC_HPD6_INT_CONTROL, tmp);
1645 }
1646}
1647
1648void evergreen_irq_disable(struct radeon_device *rdev)
1649{
1650 u32 disp_int, disp_int_cont, disp_int_cont2;
1651 u32 disp_int_cont3, disp_int_cont4, disp_int_cont5;
1652
1653 r600_disable_interrupts(rdev);
1654 /* Wait and acknowledge irq */
1655 mdelay(1);
1656 evergreen_irq_ack(rdev, &disp_int, &disp_int_cont, &disp_int_cont2,
1657 &disp_int_cont3, &disp_int_cont4, &disp_int_cont5);
1658 evergreen_disable_interrupt_state(rdev);
1659}
1660
1661static void evergreen_irq_suspend(struct radeon_device *rdev)
1662{
1663 evergreen_irq_disable(rdev);
1664 r600_rlc_stop(rdev);
1665}
1666
1667static inline u32 evergreen_get_ih_wptr(struct radeon_device *rdev)
1668{
1669 u32 wptr, tmp;
1670
1671 /* XXX use writeback */
1672 wptr = RREG32(IH_RB_WPTR);
1673
1674 if (wptr & RB_OVERFLOW) {
1675 /* When a ring buffer overflow happen start parsing interrupt
1676 * from the last not overwritten vector (wptr + 16). Hopefully
1677 * this should allow us to catchup.
1678 */
1679 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
1680 wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
1681 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
1682 tmp = RREG32(IH_RB_CNTL);
1683 tmp |= IH_WPTR_OVERFLOW_CLEAR;
1684 WREG32(IH_RB_CNTL, tmp);
1685 }
1686 return (wptr & rdev->ih.ptr_mask);
1687}
1688
1689int evergreen_irq_process(struct radeon_device *rdev)
1690{
1691 u32 wptr = evergreen_get_ih_wptr(rdev);
1692 u32 rptr = rdev->ih.rptr;
1693 u32 src_id, src_data;
1694 u32 ring_index;
1695 u32 disp_int, disp_int_cont, disp_int_cont2;
1696 u32 disp_int_cont3, disp_int_cont4, disp_int_cont5;
1697 unsigned long flags;
1698 bool queue_hotplug = false;
1699
1700 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
1701 if (!rdev->ih.enabled)
1702 return IRQ_NONE;
1703
1704 spin_lock_irqsave(&rdev->ih.lock, flags);
1705
1706 if (rptr == wptr) {
1707 spin_unlock_irqrestore(&rdev->ih.lock, flags);
1708 return IRQ_NONE;
1709 }
1710 if (rdev->shutdown) {
1711 spin_unlock_irqrestore(&rdev->ih.lock, flags);
1712 return IRQ_NONE;
1713 }
1714
1715restart_ih:
1716 /* display interrupts */
1717 evergreen_irq_ack(rdev, &disp_int, &disp_int_cont, &disp_int_cont2,
1718 &disp_int_cont3, &disp_int_cont4, &disp_int_cont5);
1719
1720 rdev->ih.wptr = wptr;
1721 while (rptr != wptr) {
1722 /* wptr/rptr are in bytes! */
1723 ring_index = rptr / 4;
1724 src_id = rdev->ih.ring[ring_index] & 0xff;
1725 src_data = rdev->ih.ring[ring_index + 1] & 0xfffffff;
1726
1727 switch (src_id) {
1728 case 1: /* D1 vblank/vline */
1729 switch (src_data) {
1730 case 0: /* D1 vblank */
1731 if (disp_int & LB_D1_VBLANK_INTERRUPT) {
1732 drm_handle_vblank(rdev->ddev, 0);
1733 wake_up(&rdev->irq.vblank_queue);
1734 disp_int &= ~LB_D1_VBLANK_INTERRUPT;
1735 DRM_DEBUG("IH: D1 vblank\n");
1736 }
1737 break;
1738 case 1: /* D1 vline */
1739 if (disp_int & LB_D1_VLINE_INTERRUPT) {
1740 disp_int &= ~LB_D1_VLINE_INTERRUPT;
1741 DRM_DEBUG("IH: D1 vline\n");
1742 }
1743 break;
1744 default:
1745 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
1746 break;
1747 }
1748 break;
1749 case 2: /* D2 vblank/vline */
1750 switch (src_data) {
1751 case 0: /* D2 vblank */
1752 if (disp_int_cont & LB_D2_VBLANK_INTERRUPT) {
1753 drm_handle_vblank(rdev->ddev, 1);
1754 wake_up(&rdev->irq.vblank_queue);
1755 disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT;
1756 DRM_DEBUG("IH: D2 vblank\n");
1757 }
1758 break;
1759 case 1: /* D2 vline */
1760 if (disp_int_cont & LB_D2_VLINE_INTERRUPT) {
1761 disp_int_cont &= ~LB_D2_VLINE_INTERRUPT;
1762 DRM_DEBUG("IH: D2 vline\n");
1763 }
1764 break;
1765 default:
1766 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
1767 break;
1768 }
1769 break;
1770 case 3: /* D3 vblank/vline */
1771 switch (src_data) {
1772 case 0: /* D3 vblank */
1773 if (disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) {
1774 drm_handle_vblank(rdev->ddev, 2);
1775 wake_up(&rdev->irq.vblank_queue);
1776 disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT;
1777 DRM_DEBUG("IH: D3 vblank\n");
1778 }
1779 break;
1780 case 1: /* D3 vline */
1781 if (disp_int_cont2 & LB_D3_VLINE_INTERRUPT) {
1782 disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT;
1783 DRM_DEBUG("IH: D3 vline\n");
1784 }
1785 break;
1786 default:
1787 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
1788 break;
1789 }
1790 break;
1791 case 4: /* D4 vblank/vline */
1792 switch (src_data) {
1793 case 0: /* D4 vblank */
1794 if (disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) {
1795 drm_handle_vblank(rdev->ddev, 3);
1796 wake_up(&rdev->irq.vblank_queue);
1797 disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT;
1798 DRM_DEBUG("IH: D4 vblank\n");
1799 }
1800 break;
1801 case 1: /* D4 vline */
1802 if (disp_int_cont3 & LB_D4_VLINE_INTERRUPT) {
1803 disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT;
1804 DRM_DEBUG("IH: D4 vline\n");
1805 }
1806 break;
1807 default:
1808 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
1809 break;
1810 }
1811 break;
1812 case 5: /* D5 vblank/vline */
1813 switch (src_data) {
1814 case 0: /* D5 vblank */
1815 if (disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) {
1816 drm_handle_vblank(rdev->ddev, 4);
1817 wake_up(&rdev->irq.vblank_queue);
1818 disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT;
1819 DRM_DEBUG("IH: D5 vblank\n");
1820 }
1821 break;
1822 case 1: /* D5 vline */
1823 if (disp_int_cont4 & LB_D5_VLINE_INTERRUPT) {
1824 disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT;
1825 DRM_DEBUG("IH: D5 vline\n");
1826 }
1827 break;
1828 default:
1829 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
1830 break;
1831 }
1832 break;
1833 case 6: /* D6 vblank/vline */
1834 switch (src_data) {
1835 case 0: /* D6 vblank */
1836 if (disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) {
1837 drm_handle_vblank(rdev->ddev, 5);
1838 wake_up(&rdev->irq.vblank_queue);
1839 disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT;
1840 DRM_DEBUG("IH: D6 vblank\n");
1841 }
1842 break;
1843 case 1: /* D6 vline */
1844 if (disp_int_cont5 & LB_D6_VLINE_INTERRUPT) {
1845 disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT;
1846 DRM_DEBUG("IH: D6 vline\n");
1847 }
1848 break;
1849 default:
1850 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
1851 break;
1852 }
1853 break;
1854 case 42: /* HPD hotplug */
1855 switch (src_data) {
1856 case 0:
1857 if (disp_int & DC_HPD1_INTERRUPT) {
1858 disp_int &= ~DC_HPD1_INTERRUPT;
1859 queue_hotplug = true;
1860 DRM_DEBUG("IH: HPD1\n");
1861 }
1862 break;
1863 case 1:
1864 if (disp_int_cont & DC_HPD2_INTERRUPT) {
1865 disp_int_cont &= ~DC_HPD2_INTERRUPT;
1866 queue_hotplug = true;
1867 DRM_DEBUG("IH: HPD2\n");
1868 }
1869 break;
1870 case 2:
1871 if (disp_int_cont2 & DC_HPD3_INTERRUPT) {
1872 disp_int_cont2 &= ~DC_HPD3_INTERRUPT;
1873 queue_hotplug = true;
1874 DRM_DEBUG("IH: HPD3\n");
1875 }
1876 break;
1877 case 3:
1878 if (disp_int_cont3 & DC_HPD4_INTERRUPT) {
1879 disp_int_cont3 &= ~DC_HPD4_INTERRUPT;
1880 queue_hotplug = true;
1881 DRM_DEBUG("IH: HPD4\n");
1882 }
1883 break;
1884 case 4:
1885 if (disp_int_cont4 & DC_HPD5_INTERRUPT) {
1886 disp_int_cont4 &= ~DC_HPD5_INTERRUPT;
1887 queue_hotplug = true;
1888 DRM_DEBUG("IH: HPD5\n");
1889 }
1890 break;
1891 case 5:
1892 if (disp_int_cont5 & DC_HPD6_INTERRUPT) {
1893 disp_int_cont5 &= ~DC_HPD6_INTERRUPT;
1894 queue_hotplug = true;
1895 DRM_DEBUG("IH: HPD6\n");
1896 }
1897 break;
1898 default:
1899 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
1900 break;
1901 }
1902 break;
1903 case 176: /* CP_INT in ring buffer */
1904 case 177: /* CP_INT in IB1 */
1905 case 178: /* CP_INT in IB2 */
1906 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
1907 radeon_fence_process(rdev);
1908 break;
1909 case 181: /* CP EOP event */
1910 DRM_DEBUG("IH: CP EOP\n");
1911 break;
2031f77c
AD		 1912 case 233: /* GUI IDLE */
1913 DRM_DEBUG("IH: CP EOP\n");
1914 rdev->pm.gui_idle = true;
1915 wake_up(&rdev->irq.idle_queue);
1916 break;
45f9a39b
AD		 1917 default:
1918 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
1919 break;
1920 }
1921
1922 /* wptr/rptr are in bytes! */
1923 rptr += 16;
1924 rptr &= rdev->ih.ptr_mask;
1925 }
1926 /* make sure wptr hasn't changed while processing */
1927 wptr = evergreen_get_ih_wptr(rdev);
1928 if (wptr != rdev->ih.wptr)
1929 goto restart_ih;
1930 if (queue_hotplug)
1931 queue_work(rdev->wq, &rdev->hotplug_work);
1932 rdev->ih.rptr = rptr;
1933 WREG32(IH_RB_RPTR, rdev->ih.rptr);
1934 spin_unlock_irqrestore(&rdev->ih.lock, flags);
1935 return IRQ_HANDLED;
1936}
1937
bcc1c2a1
AD		 1938static int evergreen_startup(struct radeon_device *rdev)
1939{
bcc1c2a1
AD		 1940 int r;
1941
1942 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
1943 r = r600_init_microcode(rdev);
1944 if (r) {
1945 DRM_ERROR("Failed to load firmware!\n");
1946 return r;
1947 }
1948 }
fe251e2f 1949
bcc1c2a1 1950 evergreen_mc_program(rdev);
bcc1c2a1 1951 if (rdev->flags & RADEON_IS_AGP) {
0fcdb61e 1952 evergreen_agp_enable(rdev);
bcc1c2a1
AD		 1953 } else {
1954 r = evergreen_pcie_gart_enable(rdev);
1955 if (r)
1956 return r;
1957 }
bcc1c2a1
AD		 1958 evergreen_gpu_init(rdev);
1959#if 0
1960 if (!rdev->r600_blit.shader_obj) {
1961 r = r600_blit_init(rdev);
1962 if (r) {
1963 DRM_ERROR("radeon: failed blitter (%d).\n", r);
1964 return r;
1965 }
1966 }
1967
1968 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
1969 if (unlikely(r != 0))
1970 return r;
1971 r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
1972 &rdev->r600_blit.shader_gpu_addr);
1973 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
1974 if (r) {
1975 DRM_ERROR("failed to pin blit object %d\n", r);
1976 return r;
1977 }
45f9a39b 1978#endif
bcc1c2a1
AD		 1979
1980 /* Enable IRQ */
1981 r = r600_irq_init(rdev);
1982 if (r) {
1983 DRM_ERROR("radeon: IH init failed (%d).\n", r);
1984 radeon_irq_kms_fini(rdev);
1985 return r;
1986 }
45f9a39b 1987 evergreen_irq_set(rdev);
bcc1c2a1
AD		 1988
1989 r = radeon_ring_init(rdev, rdev->cp.ring_size);
1990 if (r)
1991 return r;
1992 r = evergreen_cp_load_microcode(rdev);
1993 if (r)
1994 return r;
fe251e2f 1995 r = evergreen_cp_resume(rdev);
bcc1c2a1
AD		 1996 if (r)
1997 return r;
1998 /* write back buffer are not vital so don't worry about failure */
1999 r600_wb_enable(rdev);
fe251e2f 2000
bcc1c2a1
AD		 2001 return 0;
2002}
2003
2004int evergreen_resume(struct radeon_device *rdev)
2005{
2006 int r;
2007
2008 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
2009 * posting will perform necessary task to bring back GPU into good
2010 * shape.
2011 */
2012 /* post card */
2013 atom_asic_init(rdev->mode_info.atom_context);
2014 /* Initialize clocks */
2015 r = radeon_clocks_init(rdev);
2016 if (r) {
2017 return r;
2018 }
2019
2020 r = evergreen_startup(rdev);
2021 if (r) {
2022 DRM_ERROR("r600 startup failed on resume\n");
2023 return r;
2024 }
fe251e2f 2025
bcc1c2a1
AD		 2026 r = r600_ib_test(rdev);
2027 if (r) {
2028 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
2029 return r;
2030 }
fe251e2f 2031
bcc1c2a1
AD		 2032 return r;
2033
2034}
2035
2036int evergreen_suspend(struct radeon_device *rdev)
2037{
2038#if 0
2039 int r;
fe251e2f 2040#endif
bcc1c2a1
AD		 2041 /* FIXME: we should wait for ring to be empty */
2042 r700_cp_stop(rdev);
2043 rdev->cp.ready = false;
45f9a39b 2044 evergreen_irq_suspend(rdev);
bcc1c2a1
AD		 2045 r600_wb_disable(rdev);
2046 evergreen_pcie_gart_disable(rdev);
0fcdb61e 2047#if 0
bcc1c2a1
AD		 2048 /* unpin shaders bo */
2049 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
2050 if (likely(r == 0)) {
2051 radeon_bo_unpin(rdev->r600_blit.shader_obj);
2052 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
2053 }
2054#endif
2055 return 0;
2056}
2057
2058static bool evergreen_card_posted(struct radeon_device *rdev)
2059{
2060 u32 reg;
2061
2062 /* first check CRTCs */
2063 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
2064 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) |
2065 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |
2066 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) |
2067 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) |
2068 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
2069 if (reg & EVERGREEN_CRTC_MASTER_EN)
2070 return true;
2071
2072 /* then check MEM_SIZE, in case the crtcs are off */
2073 if (RREG32(CONFIG_MEMSIZE))
2074 return true;
2075
2076 return false;
2077}
2078
2079/* Plan is to move initialization in that function and use
2080 * helper function so that radeon_device_init pretty much
2081 * do nothing more than calling asic specific function. This
2082 * should also allow to remove a bunch of callback function
2083 * like vram_info.
2084 */
2085int evergreen_init(struct radeon_device *rdev)
2086{
2087 int r;
2088
2089 r = radeon_dummy_page_init(rdev);
2090 if (r)
2091 return r;
2092 /* This don't do much */
2093 r = radeon_gem_init(rdev);
2094 if (r)
2095 return r;
2096 /* Read BIOS */
2097 if (!radeon_get_bios(rdev)) {
2098 if (ASIC_IS_AVIVO(rdev))
2099 return -EINVAL;
2100 }
2101 /* Must be an ATOMBIOS */
2102 if (!rdev->is_atom_bios) {
2103 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
2104 return -EINVAL;
2105 }
2106 r = radeon_atombios_init(rdev);
2107 if (r)
2108 return r;
2109 /* Post card if necessary */
2110 if (!evergreen_card_posted(rdev)) {
2111 if (!rdev->bios) {
2112 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
2113 return -EINVAL;
2114 }
2115 DRM_INFO("GPU not posted. posting now...\n");
2116 atom_asic_init(rdev->mode_info.atom_context);
2117 }
2118 /* Initialize scratch registers */
2119 r600_scratch_init(rdev);
2120 /* Initialize surface registers */
2121 radeon_surface_init(rdev);
2122 /* Initialize clocks */
2123 radeon_get_clock_info(rdev->ddev);
2124 r = radeon_clocks_init(rdev);
2125 if (r)
2126 return r;
bcc1c2a1
AD		 2127 /* Fence driver */
2128 r = radeon_fence_driver_init(rdev);
2129 if (r)
2130 return r;
d594e46a
JG		 2131 /* initialize AGP */
2132 if (rdev->flags & RADEON_IS_AGP) {
2133 r = radeon_agp_init(rdev);
2134 if (r)
2135 radeon_agp_disable(rdev);
2136 }
2137 /* initialize memory controller */
bcc1c2a1
AD		 2138 r = evergreen_mc_init(rdev);
2139 if (r)
2140 return r;
2141 /* Memory manager */
2142 r = radeon_bo_init(rdev);
2143 if (r)
2144 return r;
45f9a39b 2145
bcc1c2a1
AD		 2146 r = radeon_irq_kms_init(rdev);
2147 if (r)
2148 return r;
2149
2150 rdev->cp.ring_obj = NULL;
2151 r600_ring_init(rdev, 1024 * 1024);
2152
2153 rdev->ih.ring_obj = NULL;
2154 r600_ih_ring_init(rdev, 64 * 1024);
2155
2156 r = r600_pcie_gart_init(rdev);
2157 if (r)
2158 return r;
0fcdb61e 2159
148a03bc 2160 rdev->accel_working = true;
bcc1c2a1
AD		 2161 r = evergreen_startup(rdev);
2162 if (r) {
fe251e2f
AD		 2163 dev_err(rdev->dev, "disabling GPU acceleration\n");
2164 r700_cp_fini(rdev);
2165 r600_wb_fini(rdev);
fe251e2f
AD		 2166 r600_irq_fini(rdev);
2167 radeon_irq_kms_fini(rdev);
0fcdb61e 2168 evergreen_pcie_gart_fini(rdev);
bcc1c2a1
AD		 2169 rdev->accel_working = false;
2170 }
2171 if (rdev->accel_working) {
2172 r = radeon_ib_pool_init(rdev);
2173 if (r) {
2174 DRM_ERROR("radeon: failed initializing IB pool (%d).\n", r);
2175 rdev->accel_working = false;
2176 }
2177 r = r600_ib_test(rdev);
2178 if (r) {
2179 DRM_ERROR("radeon: failed testing IB (%d).\n", r);
2180 rdev->accel_working = false;
2181 }
2182 }
2183 return 0;
2184}
2185
2186void evergreen_fini(struct radeon_device *rdev)
2187{
45f9a39b
AD		 2188 /*r600_blit_fini(rdev);*/
2189 r700_cp_fini(rdev);
2190 r600_wb_fini(rdev);
bcc1c2a1
AD		 2191 r600_irq_fini(rdev);
2192 radeon_irq_kms_fini(rdev);
bcc1c2a1 2193 evergreen_pcie_gart_fini(rdev);
bcc1c2a1
AD		 2194 radeon_gem_fini(rdev);
2195 radeon_fence_driver_fini(rdev);
2196 radeon_clocks_fini(rdev);
2197 radeon_agp_fini(rdev);
2198 radeon_bo_fini(rdev);
2199 radeon_atombios_fini(rdev);
2200 kfree(rdev->bios);
2201 rdev->bios = NULL;
2202 radeon_dummy_page_fini(rdev);
2203}
Linux kernel - Deliverables
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