projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/radeon/kms: add pageflip ioctl support (v3)
[deliverable/linux.git] / drivers / gpu / drm / radeon / evergreen.c
CommitLineData
bcc1c2a1
AD		 1/*
2 * Copyright 2010 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24#include <linux/firmware.h>
25#include <linux/platform_device.h>
5a0e3ad6 26#include <linux/slab.h>
bcc1c2a1
AD		 27#include "drmP.h"
28#include "radeon.h"
e6990375 29#include "radeon_asic.h"
bcc1c2a1 30#include "radeon_drm.h"
0fcdb61e 31#include "evergreend.h"
bcc1c2a1
AD		 32#include "atom.h"
33#include "avivod.h"
34#include "evergreen_reg.h"
2281a378 35#include "evergreen_blit_shaders.h"
bcc1c2a1 36
fe251e2f
AD		 37#define EVERGREEN_PFP_UCODE_SIZE 1120
38#define EVERGREEN_PM4_UCODE_SIZE 1376
39
bcc1c2a1
AD		 40static void evergreen_gpu_init(struct radeon_device *rdev);
41void evergreen_fini(struct radeon_device *rdev);
42
6f34be50
AD		 43void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc)
44{
45 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc];
46 u32 tmp;
47
48 /* make sure flip is at vb rather than hb */
49 tmp = RREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset);
50 tmp &= ~EVERGREEN_GRPH_SURFACE_UPDATE_H_RETRACE_EN;
51 WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp);
52
53 /* set pageflip to happen anywhere in vblank interval */
54 WREG32(EVERGREEN_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0);
55
56 /* enable the pflip int */
57 radeon_irq_kms_pflip_irq_get(rdev, crtc);
58}
59
60void evergreen_post_page_flip(struct radeon_device *rdev, int crtc)
61{
62 /* disable the pflip int */
63 radeon_irq_kms_pflip_irq_put(rdev, crtc);
64}
65
66u32 evergreen_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
67{
68 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
69 u32 tmp = RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset);
70
71 /* Lock the graphics update lock */
72 tmp |= EVERGREEN_GRPH_UPDATE_LOCK;
73 WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
74
75 /* update the scanout addresses */
76 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
77 upper_32_bits(crtc_base));
78 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
79 (u32)crtc_base);
80
81 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
82 upper_32_bits(crtc_base));
83 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
84 (u32)crtc_base);
85
86 /* Wait for update_pending to go high. */
87 while (!(RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING));
88 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
89
90 /* Unlock the lock, so double-buffering can take place inside vblank */
91 tmp &= ~EVERGREEN_GRPH_UPDATE_LOCK;
92 WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
93
94 /* Return current update_pending status: */
95 return RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING;
96}
97
21a8122a
AD		 98/* get temperature in millidegrees */
99u32 evergreen_get_temp(struct radeon_device *rdev)
100{
101 u32 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >>
102 ASIC_T_SHIFT;
103 u32 actual_temp = 0;
104
105 if ((temp >> 10) & 1)
106 actual_temp = 0;
107 else if ((temp >> 9) & 1)
108 actual_temp = 255;
109 else
110 actual_temp = (temp >> 1) & 0xff;
111
112 return actual_temp * 1000;
113}
114
49e02b73
AD		 115void evergreen_pm_misc(struct radeon_device *rdev)
116{
a081a9d6
RM		 117 int req_ps_idx = rdev->pm.requested_power_state_index;
118 int req_cm_idx = rdev->pm.requested_clock_mode_index;
119 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
120 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
49e02b73 121
4d60173f
AD		 122 if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
123 if (voltage->voltage != rdev->pm.current_vddc) {
124 radeon_atom_set_voltage(rdev, voltage->voltage);
125 rdev->pm.current_vddc = voltage->voltage;
0fcbe947 126 DRM_DEBUG("Setting: v: %d\n", voltage->voltage);
4d60173f
AD		 127 }
128 }
49e02b73
AD		 129}
130
131void evergreen_pm_prepare(struct radeon_device *rdev)
132{
133 struct drm_device *ddev = rdev->ddev;
134 struct drm_crtc *crtc;
135 struct radeon_crtc *radeon_crtc;
136 u32 tmp;
137
138 /* disable any active CRTCs */
139 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
140 radeon_crtc = to_radeon_crtc(crtc);
141 if (radeon_crtc->enabled) {
142 tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
143 tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
144 WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
145 }
146 }
147}
148
149void evergreen_pm_finish(struct radeon_device *rdev)
150{
151 struct drm_device *ddev = rdev->ddev;
152 struct drm_crtc *crtc;
153 struct radeon_crtc *radeon_crtc;
154 u32 tmp;
155
156 /* enable any active CRTCs */
157 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
158 radeon_crtc = to_radeon_crtc(crtc);
159 if (radeon_crtc->enabled) {
160 tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
161 tmp &= ~EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
162 WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
163 }
164 }
165}
166
bcc1c2a1
AD		 167bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
168{
169 bool connected = false;
0ca2ab52
AD		 170
171 switch (hpd) {
172 case RADEON_HPD_1:
173 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
174 connected = true;
175 break;
176 case RADEON_HPD_2:
177 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
178 connected = true;
179 break;
180 case RADEON_HPD_3:
181 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
182 connected = true;
183 break;
184 case RADEON_HPD_4:
185 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
186 connected = true;
187 break;
188 case RADEON_HPD_5:
189 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
190 connected = true;
191 break;
192 case RADEON_HPD_6:
193 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
194 connected = true;
195 break;
196 default:
197 break;
198 }
199
bcc1c2a1
AD		 200 return connected;
201}
202
203void evergreen_hpd_set_polarity(struct radeon_device *rdev,
204 enum radeon_hpd_id hpd)
205{
0ca2ab52
AD		 206 u32 tmp;
207 bool connected = evergreen_hpd_sense(rdev, hpd);
208
209 switch (hpd) {
210 case RADEON_HPD_1:
211 tmp = RREG32(DC_HPD1_INT_CONTROL);
212 if (connected)
213 tmp &= ~DC_HPDx_INT_POLARITY;
214 else
215 tmp |= DC_HPDx_INT_POLARITY;
216 WREG32(DC_HPD1_INT_CONTROL, tmp);
217 break;
218 case RADEON_HPD_2:
219 tmp = RREG32(DC_HPD2_INT_CONTROL);
220 if (connected)
221 tmp &= ~DC_HPDx_INT_POLARITY;
222 else
223 tmp |= DC_HPDx_INT_POLARITY;
224 WREG32(DC_HPD2_INT_CONTROL, tmp);
225 break;
226 case RADEON_HPD_3:
227 tmp = RREG32(DC_HPD3_INT_CONTROL);
228 if (connected)
229 tmp &= ~DC_HPDx_INT_POLARITY;
230 else
231 tmp |= DC_HPDx_INT_POLARITY;
232 WREG32(DC_HPD3_INT_CONTROL, tmp);
233 break;
234 case RADEON_HPD_4:
235 tmp = RREG32(DC_HPD4_INT_CONTROL);
236 if (connected)
237 tmp &= ~DC_HPDx_INT_POLARITY;
238 else
239 tmp |= DC_HPDx_INT_POLARITY;
240 WREG32(DC_HPD4_INT_CONTROL, tmp);
241 break;
242 case RADEON_HPD_5:
243 tmp = RREG32(DC_HPD5_INT_CONTROL);
244 if (connected)
245 tmp &= ~DC_HPDx_INT_POLARITY;
246 else
247 tmp |= DC_HPDx_INT_POLARITY;
248 WREG32(DC_HPD5_INT_CONTROL, tmp);
249 break;
250 case RADEON_HPD_6:
251 tmp = RREG32(DC_HPD6_INT_CONTROL);
252 if (connected)
253 tmp &= ~DC_HPDx_INT_POLARITY;
254 else
255 tmp |= DC_HPDx_INT_POLARITY;
256 WREG32(DC_HPD6_INT_CONTROL, tmp);
257 break;
258 default:
259 break;
260 }
bcc1c2a1
AD		 261}
262
263void evergreen_hpd_init(struct radeon_device *rdev)
264{
0ca2ab52
AD		 265 struct drm_device *dev = rdev->ddev;
266 struct drm_connector *connector;
267 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) |
268 DC_HPDx_RX_INT_TIMER(0xfa) | DC_HPDx_EN;
bcc1c2a1 269
0ca2ab52
AD		 270 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
271 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
272 switch (radeon_connector->hpd.hpd) {
273 case RADEON_HPD_1:
274 WREG32(DC_HPD1_CONTROL, tmp);
275 rdev->irq.hpd[0] = true;
276 break;
277 case RADEON_HPD_2:
278 WREG32(DC_HPD2_CONTROL, tmp);
279 rdev->irq.hpd[1] = true;
280 break;
281 case RADEON_HPD_3:
282 WREG32(DC_HPD3_CONTROL, tmp);
283 rdev->irq.hpd[2] = true;
284 break;
285 case RADEON_HPD_4:
286 WREG32(DC_HPD4_CONTROL, tmp);
287 rdev->irq.hpd[3] = true;
288 break;
289 case RADEON_HPD_5:
290 WREG32(DC_HPD5_CONTROL, tmp);
291 rdev->irq.hpd[4] = true;
292 break;
293 case RADEON_HPD_6:
294 WREG32(DC_HPD6_CONTROL, tmp);
295 rdev->irq.hpd[5] = true;
296 break;
297 default:
298 break;
299 }
300 }
301 if (rdev->irq.installed)
302 evergreen_irq_set(rdev);
bcc1c2a1
AD		 303}
304
0ca2ab52 305void evergreen_hpd_fini(struct radeon_device *rdev)
bcc1c2a1 306{
0ca2ab52
AD		 307 struct drm_device *dev = rdev->ddev;
308 struct drm_connector *connector;
309
310 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
311 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
312 switch (radeon_connector->hpd.hpd) {
313 case RADEON_HPD_1:
314 WREG32(DC_HPD1_CONTROL, 0);
315 rdev->irq.hpd[0] = false;
316 break;
317 case RADEON_HPD_2:
318 WREG32(DC_HPD2_CONTROL, 0);
319 rdev->irq.hpd[1] = false;
320 break;
321 case RADEON_HPD_3:
322 WREG32(DC_HPD3_CONTROL, 0);
323 rdev->irq.hpd[2] = false;
324 break;
325 case RADEON_HPD_4:
326 WREG32(DC_HPD4_CONTROL, 0);
327 rdev->irq.hpd[3] = false;
328 break;
329 case RADEON_HPD_5:
330 WREG32(DC_HPD5_CONTROL, 0);
331 rdev->irq.hpd[4] = false;
332 break;
333 case RADEON_HPD_6:
334 WREG32(DC_HPD6_CONTROL, 0);
335 rdev->irq.hpd[5] = false;
336 break;
337 default:
338 break;
339 }
340 }
bcc1c2a1
AD		 341}
342
f9d9c362
AD		 343/* watermark setup */
344
345static u32 evergreen_line_buffer_adjust(struct radeon_device *rdev,
346 struct radeon_crtc *radeon_crtc,
347 struct drm_display_mode *mode,
348 struct drm_display_mode *other_mode)
349{
350 u32 tmp = 0;
351 /*
352 * Line Buffer Setup
353 * There are 3 line buffers, each one shared by 2 display controllers.
354 * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
355 * the display controllers. The paritioning is done via one of four
356 * preset allocations specified in bits 2:0:
357 * first display controller
358 * 0 - first half of lb (3840 * 2)
359 * 1 - first 3/4 of lb (5760 * 2)
360 * 2 - whole lb (7680 * 2)
361 * 3 - first 1/4 of lb (1920 * 2)
362 * second display controller
363 * 4 - second half of lb (3840 * 2)
364 * 5 - second 3/4 of lb (5760 * 2)
365 * 6 - whole lb (7680 * 2)
366 * 7 - last 1/4 of lb (1920 * 2)
367 */
368 if (mode && other_mode) {
369 if (mode->hdisplay > other_mode->hdisplay) {
370 if (mode->hdisplay > 2560)
371 tmp = 1; /* 3/4 */
372 else
373 tmp = 0; /* 1/2 */
374 } else if (other_mode->hdisplay > mode->hdisplay) {
375 if (other_mode->hdisplay > 2560)
376 tmp = 3; /* 1/4 */
377 else
378 tmp = 0; /* 1/2 */
379 } else
380 tmp = 0; /* 1/2 */
381 } else if (mode)
382 tmp = 2; /* whole */
383 else if (other_mode)
384 tmp = 3; /* 1/4 */
385
386 /* second controller of the pair uses second half of the lb */
387 if (radeon_crtc->crtc_id % 2)
388 tmp += 4;
389 WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, tmp);
390
391 switch (tmp) {
392 case 0:
393 case 4:
394 default:
395 return 3840 * 2;
396 case 1:
397 case 5:
398 return 5760 * 2;
399 case 2:
400 case 6:
401 return 7680 * 2;
402 case 3:
403 case 7:
404 return 1920 * 2;
405 }
406}
407
408static u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev)
409{
410 u32 tmp = RREG32(MC_SHARED_CHMAP);
411
412 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
413 case 0:
414 default:
415 return 1;
416 case 1:
417 return 2;
418 case 2:
419 return 4;
420 case 3:
421 return 8;
422 }
423}
424
425struct evergreen_wm_params {
426 u32 dram_channels; /* number of dram channels */
427 u32 yclk; /* bandwidth per dram data pin in kHz */
428 u32 sclk; /* engine clock in kHz */
429 u32 disp_clk; /* display clock in kHz */
430 u32 src_width; /* viewport width */
431 u32 active_time; /* active display time in ns */
432 u32 blank_time; /* blank time in ns */
433 bool interlaced; /* mode is interlaced */
434 fixed20_12 vsc; /* vertical scale ratio */
435 u32 num_heads; /* number of active crtcs */
436 u32 bytes_per_pixel; /* bytes per pixel display + overlay */
437 u32 lb_size; /* line buffer allocated to pipe */
438 u32 vtaps; /* vertical scaler taps */
439};
440
441static u32 evergreen_dram_bandwidth(struct evergreen_wm_params *wm)
442{
443 /* Calculate DRAM Bandwidth and the part allocated to display. */
444 fixed20_12 dram_efficiency; /* 0.7 */
445 fixed20_12 yclk, dram_channels, bandwidth;
446 fixed20_12 a;
447
448 a.full = dfixed_const(1000);
449 yclk.full = dfixed_const(wm->yclk);
450 yclk.full = dfixed_div(yclk, a);
451 dram_channels.full = dfixed_const(wm->dram_channels * 4);
452 a.full = dfixed_const(10);
453 dram_efficiency.full = dfixed_const(7);
454 dram_efficiency.full = dfixed_div(dram_efficiency, a);
455 bandwidth.full = dfixed_mul(dram_channels, yclk);
456 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
457
458 return dfixed_trunc(bandwidth);
459}
460
461static u32 evergreen_dram_bandwidth_for_display(struct evergreen_wm_params *wm)
462{
463 /* Calculate DRAM Bandwidth and the part allocated to display. */
464 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
465 fixed20_12 yclk, dram_channels, bandwidth;
466 fixed20_12 a;
467
468 a.full = dfixed_const(1000);
469 yclk.full = dfixed_const(wm->yclk);
470 yclk.full = dfixed_div(yclk, a);
471 dram_channels.full = dfixed_const(wm->dram_channels * 4);
472 a.full = dfixed_const(10);
473 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
474 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
475 bandwidth.full = dfixed_mul(dram_channels, yclk);
476 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
477
478 return dfixed_trunc(bandwidth);
479}
480
481static u32 evergreen_data_return_bandwidth(struct evergreen_wm_params *wm)
482{
483 /* Calculate the display Data return Bandwidth */
484 fixed20_12 return_efficiency; /* 0.8 */
485 fixed20_12 sclk, bandwidth;
486 fixed20_12 a;
487
488 a.full = dfixed_const(1000);
489 sclk.full = dfixed_const(wm->sclk);
490 sclk.full = dfixed_div(sclk, a);
491 a.full = dfixed_const(10);
492 return_efficiency.full = dfixed_const(8);
493 return_efficiency.full = dfixed_div(return_efficiency, a);
494 a.full = dfixed_const(32);
495 bandwidth.full = dfixed_mul(a, sclk);
496 bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
497
498 return dfixed_trunc(bandwidth);
499}
500
501static u32 evergreen_dmif_request_bandwidth(struct evergreen_wm_params *wm)
502{
503 /* Calculate the DMIF Request Bandwidth */
504 fixed20_12 disp_clk_request_efficiency; /* 0.8 */
505 fixed20_12 disp_clk, bandwidth;
506 fixed20_12 a;
507
508 a.full = dfixed_const(1000);
509 disp_clk.full = dfixed_const(wm->disp_clk);
510 disp_clk.full = dfixed_div(disp_clk, a);
511 a.full = dfixed_const(10);
512 disp_clk_request_efficiency.full = dfixed_const(8);
513 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
514 a.full = dfixed_const(32);
515 bandwidth.full = dfixed_mul(a, disp_clk);
516 bandwidth.full = dfixed_mul(bandwidth, disp_clk_request_efficiency);
517
518 return dfixed_trunc(bandwidth);
519}
520
521static u32 evergreen_available_bandwidth(struct evergreen_wm_params *wm)
522{
523 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
524 u32 dram_bandwidth = evergreen_dram_bandwidth(wm);
525 u32 data_return_bandwidth = evergreen_data_return_bandwidth(wm);
526 u32 dmif_req_bandwidth = evergreen_dmif_request_bandwidth(wm);
527
528 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
529}
530
531static u32 evergreen_average_bandwidth(struct evergreen_wm_params *wm)
532{
533 /* Calculate the display mode Average Bandwidth
534 * DisplayMode should contain the source and destination dimensions,
535 * timing, etc.
536 */
537 fixed20_12 bpp;
538 fixed20_12 line_time;
539 fixed20_12 src_width;
540 fixed20_12 bandwidth;
541 fixed20_12 a;
542
543 a.full = dfixed_const(1000);
544 line_time.full = dfixed_const(wm->active_time + wm->blank_time);
545 line_time.full = dfixed_div(line_time, a);
546 bpp.full = dfixed_const(wm->bytes_per_pixel);
547 src_width.full = dfixed_const(wm->src_width);
548 bandwidth.full = dfixed_mul(src_width, bpp);
549 bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
550 bandwidth.full = dfixed_div(bandwidth, line_time);
551
552 return dfixed_trunc(bandwidth);
553}
554
555static u32 evergreen_latency_watermark(struct evergreen_wm_params *wm)
556{
557 /* First calcualte the latency in ns */
558 u32 mc_latency = 2000; /* 2000 ns. */
559 u32 available_bandwidth = evergreen_available_bandwidth(wm);
560 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
561 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
562 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
563 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
564 (wm->num_heads * cursor_line_pair_return_time);
565 u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
566 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
567 fixed20_12 a, b, c;
568
569 if (wm->num_heads == 0)
570 return 0;
571
572 a.full = dfixed_const(2);
573 b.full = dfixed_const(1);
574 if ((wm->vsc.full > a.full) ||
575 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
576 (wm->vtaps >= 5) ||
577 ((wm->vsc.full >= a.full) && wm->interlaced))
578 max_src_lines_per_dst_line = 4;
579 else
580 max_src_lines_per_dst_line = 2;
581
582 a.full = dfixed_const(available_bandwidth);
583 b.full = dfixed_const(wm->num_heads);
584 a.full = dfixed_div(a, b);
585
586 b.full = dfixed_const(1000);
587 c.full = dfixed_const(wm->disp_clk);
588 b.full = dfixed_div(c, b);
589 c.full = dfixed_const(wm->bytes_per_pixel);
590 b.full = dfixed_mul(b, c);
591
592 lb_fill_bw = min(dfixed_trunc(a), dfixed_trunc(b));
593
594 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
595 b.full = dfixed_const(1000);
596 c.full = dfixed_const(lb_fill_bw);
597 b.full = dfixed_div(c, b);
598 a.full = dfixed_div(a, b);
599 line_fill_time = dfixed_trunc(a);
600
601 if (line_fill_time < wm->active_time)
602 return latency;
603 else
604 return latency + (line_fill_time - wm->active_time);
605
606}
607
608static bool evergreen_average_bandwidth_vs_dram_bandwidth_for_display(struct evergreen_wm_params *wm)
609{
610 if (evergreen_average_bandwidth(wm) <=
611 (evergreen_dram_bandwidth_for_display(wm) / wm->num_heads))
612 return true;
613 else
614 return false;
615};
616
617static bool evergreen_average_bandwidth_vs_available_bandwidth(struct evergreen_wm_params *wm)
618{
619 if (evergreen_average_bandwidth(wm) <=
620 (evergreen_available_bandwidth(wm) / wm->num_heads))
621 return true;
622 else
623 return false;
624};
625
626static bool evergreen_check_latency_hiding(struct evergreen_wm_params *wm)
627{
628 u32 lb_partitions = wm->lb_size / wm->src_width;
629 u32 line_time = wm->active_time + wm->blank_time;
630 u32 latency_tolerant_lines;
631 u32 latency_hiding;
632 fixed20_12 a;
633
634 a.full = dfixed_const(1);
635 if (wm->vsc.full > a.full)
636 latency_tolerant_lines = 1;
637 else {
638 if (lb_partitions <= (wm->vtaps + 1))
639 latency_tolerant_lines = 1;
640 else
641 latency_tolerant_lines = 2;
642 }
643
644 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
645
646 if (evergreen_latency_watermark(wm) <= latency_hiding)
647 return true;
648 else
649 return false;
650}
651
652static void evergreen_program_watermarks(struct radeon_device *rdev,
653 struct radeon_crtc *radeon_crtc,
654 u32 lb_size, u32 num_heads)
655{
656 struct drm_display_mode *mode = &radeon_crtc->base.mode;
657 struct evergreen_wm_params wm;
658 u32 pixel_period;
659 u32 line_time = 0;
660 u32 latency_watermark_a = 0, latency_watermark_b = 0;
661 u32 priority_a_mark = 0, priority_b_mark = 0;
662 u32 priority_a_cnt = PRIORITY_OFF;
663 u32 priority_b_cnt = PRIORITY_OFF;
664 u32 pipe_offset = radeon_crtc->crtc_id * 16;
665 u32 tmp, arb_control3;
666 fixed20_12 a, b, c;
667
668 if (radeon_crtc->base.enabled && num_heads && mode) {
669 pixel_period = 1000000 / (u32)mode->clock;
670 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
671 priority_a_cnt = 0;
672 priority_b_cnt = 0;
673
674 wm.yclk = rdev->pm.current_mclk * 10;
675 wm.sclk = rdev->pm.current_sclk * 10;
676 wm.disp_clk = mode->clock;
677 wm.src_width = mode->crtc_hdisplay;
678 wm.active_time = mode->crtc_hdisplay * pixel_period;
679 wm.blank_time = line_time - wm.active_time;
680 wm.interlaced = false;
681 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
682 wm.interlaced = true;
683 wm.vsc = radeon_crtc->vsc;
684 wm.vtaps = 1;
685 if (radeon_crtc->rmx_type != RMX_OFF)
686 wm.vtaps = 2;
687 wm.bytes_per_pixel = 4; /* XXX: get this from fb config */
688 wm.lb_size = lb_size;
689 wm.dram_channels = evergreen_get_number_of_dram_channels(rdev);
690 wm.num_heads = num_heads;
691
692 /* set for high clocks */
693 latency_watermark_a = min(evergreen_latency_watermark(&wm), (u32)65535);
694 /* set for low clocks */
695 /* wm.yclk = low clk; wm.sclk = low clk */
696 latency_watermark_b = min(evergreen_latency_watermark(&wm), (u32)65535);
697
698 /* possibly force display priority to high */
699 /* should really do this at mode validation time... */
700 if (!evergreen_average_bandwidth_vs_dram_bandwidth_for_display(&wm) ||
701 !evergreen_average_bandwidth_vs_available_bandwidth(&wm) ||
702 !evergreen_check_latency_hiding(&wm) ||
703 (rdev->disp_priority == 2)) {
704 DRM_INFO("force priority to high\n");
705 priority_a_cnt |= PRIORITY_ALWAYS_ON;
706 priority_b_cnt |= PRIORITY_ALWAYS_ON;
707 }
708
709 a.full = dfixed_const(1000);
710 b.full = dfixed_const(mode->clock);
711 b.full = dfixed_div(b, a);
712 c.full = dfixed_const(latency_watermark_a);
713 c.full = dfixed_mul(c, b);
714 c.full = dfixed_mul(c, radeon_crtc->hsc);
715 c.full = dfixed_div(c, a);
716 a.full = dfixed_const(16);
717 c.full = dfixed_div(c, a);
718 priority_a_mark = dfixed_trunc(c);
719 priority_a_cnt |= priority_a_mark & PRIORITY_MARK_MASK;
720
721 a.full = dfixed_const(1000);
722 b.full = dfixed_const(mode->clock);
723 b.full = dfixed_div(b, a);
724 c.full = dfixed_const(latency_watermark_b);
725 c.full = dfixed_mul(c, b);
726 c.full = dfixed_mul(c, radeon_crtc->hsc);
727 c.full = dfixed_div(c, a);
728 a.full = dfixed_const(16);
729 c.full = dfixed_div(c, a);
730 priority_b_mark = dfixed_trunc(c);
731 priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK;
732 }
733
734 /* select wm A */
735 arb_control3 = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
736 tmp = arb_control3;
737 tmp &= ~LATENCY_WATERMARK_MASK(3);
738 tmp |= LATENCY_WATERMARK_MASK(1);
739 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
740 WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,
741 (LATENCY_LOW_WATERMARK(latency_watermark_a) |
742 LATENCY_HIGH_WATERMARK(line_time)));
743 /* select wm B */
744 tmp = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
745 tmp &= ~LATENCY_WATERMARK_MASK(3);
746 tmp |= LATENCY_WATERMARK_MASK(2);
747 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
748 WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,
749 (LATENCY_LOW_WATERMARK(latency_watermark_b) |
750 LATENCY_HIGH_WATERMARK(line_time)));
751 /* restore original selection */
752 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, arb_control3);
753
754 /* write the priority marks */
755 WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt);
756 WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt);
757
758}
759
0ca2ab52 760void evergreen_bandwidth_update(struct radeon_device *rdev)
bcc1c2a1 761{
f9d9c362
AD		 762 struct drm_display_mode *mode0 = NULL;
763 struct drm_display_mode *mode1 = NULL;
764 u32 num_heads = 0, lb_size;
765 int i;
766
767 radeon_update_display_priority(rdev);
768
769 for (i = 0; i < rdev->num_crtc; i++) {
770 if (rdev->mode_info.crtcs[i]->base.enabled)
771 num_heads++;
772 }
773 for (i = 0; i < rdev->num_crtc; i += 2) {
774 mode0 = &rdev->mode_info.crtcs[i]->base.mode;
775 mode1 = &rdev->mode_info.crtcs[i+1]->base.mode;
776 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode0, mode1);
777 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i], lb_size, num_heads);
778 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i+1], mode1, mode0);
779 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i+1], lb_size, num_heads);
780 }
bcc1c2a1
AD		 781}
782
783static int evergreen_mc_wait_for_idle(struct radeon_device *rdev)
784{
785 unsigned i;
786 u32 tmp;
787
788 for (i = 0; i < rdev->usec_timeout; i++) {
789 /* read MC_STATUS */
790 tmp = RREG32(SRBM_STATUS) & 0x1F00;
791 if (!tmp)
792 return 0;
793 udelay(1);
794 }
795 return -1;
796}
797
798/*
799 * GART
800 */
0fcdb61e
AD		 801void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev)
802{
803 unsigned i;
804 u32 tmp;
805
806 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
807 for (i = 0; i < rdev->usec_timeout; i++) {
808 /* read MC_STATUS */
809 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
810 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
811 if (tmp == 2) {
812 printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
813 return;
814 }
815 if (tmp) {
816 return;
817 }
818 udelay(1);
819 }
820}
821
bcc1c2a1
AD		 822int evergreen_pcie_gart_enable(struct radeon_device *rdev)
823{
824 u32 tmp;
0fcdb61e 825 int r;
bcc1c2a1
AD		 826
827 if (rdev->gart.table.vram.robj == NULL) {
828 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
829 return -EINVAL;
830 }
831 r = radeon_gart_table_vram_pin(rdev);
832 if (r)
833 return r;
82568565 834 radeon_gart_restore(rdev);
bcc1c2a1
AD		 835 /* Setup L2 cache */
836 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
837 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
838 EFFECTIVE_L2_QUEUE_SIZE(7));
839 WREG32(VM_L2_CNTL2, 0);
840 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
841 /* Setup TLB control */
842 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
843 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
844 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
845 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
846 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
847 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
848 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
849 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
850 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
851 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
852 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
853 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
854 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
855 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
856 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
857 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
858 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
859 (u32)(rdev->dummy_page.addr >> 12));
0fcdb61e 860 WREG32(VM_CONTEXT1_CNTL, 0);
bcc1c2a1 861
0fcdb61e 862 evergreen_pcie_gart_tlb_flush(rdev);
bcc1c2a1
AD		 863 rdev->gart.ready = true;
864 return 0;
865}
866
867void evergreen_pcie_gart_disable(struct radeon_device *rdev)
868{
869 u32 tmp;
0fcdb61e 870 int r;
bcc1c2a1
AD		 871
872 /* Disable all tables */
0fcdb61e
AD		 873 WREG32(VM_CONTEXT0_CNTL, 0);
874 WREG32(VM_CONTEXT1_CNTL, 0);
bcc1c2a1
AD		 875
876 /* Setup L2 cache */
877 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
878 EFFECTIVE_L2_QUEUE_SIZE(7));
879 WREG32(VM_L2_CNTL2, 0);
880 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
881 /* Setup TLB control */
882 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
883 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
884 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
885 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
886 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
887 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
888 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
889 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
890 if (rdev->gart.table.vram.robj) {
891 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
892 if (likely(r == 0)) {
893 radeon_bo_kunmap(rdev->gart.table.vram.robj);
894 radeon_bo_unpin(rdev->gart.table.vram.robj);
895 radeon_bo_unreserve(rdev->gart.table.vram.robj);
896 }
897 }
898}
899
900void evergreen_pcie_gart_fini(struct radeon_device *rdev)
901{
902 evergreen_pcie_gart_disable(rdev);
903 radeon_gart_table_vram_free(rdev);
904 radeon_gart_fini(rdev);
905}
906
907
908void evergreen_agp_enable(struct radeon_device *rdev)
909{
910 u32 tmp;
bcc1c2a1
AD		 911
912 /* Setup L2 cache */
913 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
914 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
915 EFFECTIVE_L2_QUEUE_SIZE(7));
916 WREG32(VM_L2_CNTL2, 0);
917 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
918 /* Setup TLB control */
919 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
920 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
921 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
922 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
923 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
924 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
925 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
926 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
927 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
928 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
929 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
0fcdb61e
AD		 930 WREG32(VM_CONTEXT0_CNTL, 0);
931 WREG32(VM_CONTEXT1_CNTL, 0);
bcc1c2a1
AD		 932}
933
934static void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save)
935{
936 save->vga_control[0] = RREG32(D1VGA_CONTROL);
937 save->vga_control[1] = RREG32(D2VGA_CONTROL);
938 save->vga_control[2] = RREG32(EVERGREEN_D3VGA_CONTROL);
939 save->vga_control[3] = RREG32(EVERGREEN_D4VGA_CONTROL);
940 save->vga_control[4] = RREG32(EVERGREEN_D5VGA_CONTROL);
941 save->vga_control[5] = RREG32(EVERGREEN_D6VGA_CONTROL);
942 save->vga_render_control = RREG32(VGA_RENDER_CONTROL);
943 save->vga_hdp_control = RREG32(VGA_HDP_CONTROL);
944 save->crtc_control[0] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET);
945 save->crtc_control[1] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
946 save->crtc_control[2] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET);
947 save->crtc_control[3] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
948 save->crtc_control[4] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET);
949 save->crtc_control[5] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
950
951 /* Stop all video */
952 WREG32(VGA_RENDER_CONTROL, 0);
953 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);
954 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);
955 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
956 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
957 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
958 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
959 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
960 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
961 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
962 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
963 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
964 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
965 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
966 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
967 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
968 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
969 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
970 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
971
972 WREG32(D1VGA_CONTROL, 0);
973 WREG32(D2VGA_CONTROL, 0);
974 WREG32(EVERGREEN_D3VGA_CONTROL, 0);
975 WREG32(EVERGREEN_D4VGA_CONTROL, 0);
976 WREG32(EVERGREEN_D5VGA_CONTROL, 0);
977 WREG32(EVERGREEN_D6VGA_CONTROL, 0);
978}
979
980static void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save)
981{
982 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET,
983 upper_32_bits(rdev->mc.vram_start));
984 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET,
985 upper_32_bits(rdev->mc.vram_start));
986 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC0_REGISTER_OFFSET,
987 (u32)rdev->mc.vram_start);
988 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC0_REGISTER_OFFSET,
989 (u32)rdev->mc.vram_start);
990
991 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET,
992 upper_32_bits(rdev->mc.vram_start));
993 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET,
994 upper_32_bits(rdev->mc.vram_start));
995 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET,
996 (u32)rdev->mc.vram_start);
997 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET,
998 (u32)rdev->mc.vram_start);
999
1000 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
1001 upper_32_bits(rdev->mc.vram_start));
1002 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
1003 upper_32_bits(rdev->mc.vram_start));
1004 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET,
1005 (u32)rdev->mc.vram_start);
1006 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET,
1007 (u32)rdev->mc.vram_start);
1008
1009 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET,
1010 upper_32_bits(rdev->mc.vram_start));
1011 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET,
1012 upper_32_bits(rdev->mc.vram_start));
1013 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET,
1014 (u32)rdev->mc.vram_start);
1015 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET,
1016 (u32)rdev->mc.vram_start);
1017
1018 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
1019 upper_32_bits(rdev->mc.vram_start));
1020 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
1021 upper_32_bits(rdev->mc.vram_start));
1022 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET,
1023 (u32)rdev->mc.vram_start);
1024 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET,
1025 (u32)rdev->mc.vram_start);
1026
1027 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET,
1028 upper_32_bits(rdev->mc.vram_start));
1029 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET,
1030 upper_32_bits(rdev->mc.vram_start));
1031 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET,
1032 (u32)rdev->mc.vram_start);
1033 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET,
1034 (u32)rdev->mc.vram_start);
1035
1036 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start));
1037 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);
1038 /* Unlock host access */
1039 WREG32(VGA_HDP_CONTROL, save->vga_hdp_control);
1040 mdelay(1);
1041 /* Restore video state */
1042 WREG32(D1VGA_CONTROL, save->vga_control[0]);
1043 WREG32(D2VGA_CONTROL, save->vga_control[1]);
1044 WREG32(EVERGREEN_D3VGA_CONTROL, save->vga_control[2]);
1045 WREG32(EVERGREEN_D4VGA_CONTROL, save->vga_control[3]);
1046 WREG32(EVERGREEN_D5VGA_CONTROL, save->vga_control[4]);
1047 WREG32(EVERGREEN_D6VGA_CONTROL, save->vga_control[5]);
1048 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);
1049 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);
1050 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
1051 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
1052 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
1053 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
1054 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, save->crtc_control[0]);
1055 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, save->crtc_control[1]);
1056 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, save->crtc_control[2]);
1057 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, save->crtc_control[3]);
1058 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, save->crtc_control[4]);
1059 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, save->crtc_control[5]);
1060 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1061 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
1062 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1063 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
1064 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1065 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1066 WREG32(VGA_RENDER_CONTROL, save->vga_render_control);
1067}
1068
1069static void evergreen_mc_program(struct radeon_device *rdev)
1070{
1071 struct evergreen_mc_save save;
1072 u32 tmp;
1073 int i, j;
1074
1075 /* Initialize HDP */
1076 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1077 WREG32((0x2c14 + j), 0x00000000);
1078 WREG32((0x2c18 + j), 0x00000000);
1079 WREG32((0x2c1c + j), 0x00000000);
1080 WREG32((0x2c20 + j), 0x00000000);
1081 WREG32((0x2c24 + j), 0x00000000);
1082 }
1083 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
1084
1085 evergreen_mc_stop(rdev, &save);
1086 if (evergreen_mc_wait_for_idle(rdev)) {
1087 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1088 }
1089 /* Lockout access through VGA aperture*/
1090 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
1091 /* Update configuration */
1092 if (rdev->flags & RADEON_IS_AGP) {
1093 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1094 /* VRAM before AGP */
1095 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1096 rdev->mc.vram_start >> 12);
1097 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1098 rdev->mc.gtt_end >> 12);
1099 } else {
1100 /* VRAM after AGP */
1101 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1102 rdev->mc.gtt_start >> 12);
1103 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1104 rdev->mc.vram_end >> 12);
1105 }
1106 } else {
1107 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1108 rdev->mc.vram_start >> 12);
1109 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1110 rdev->mc.vram_end >> 12);
1111 }
1112 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
1113 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
1114 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1115 WREG32(MC_VM_FB_LOCATION, tmp);
1116 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1117 WREG32(HDP_NONSURFACE_INFO, (2 << 7));
46fcd2b3 1118 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
bcc1c2a1
AD		 1119 if (rdev->flags & RADEON_IS_AGP) {
1120 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
1121 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
1122 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1123 } else {
1124 WREG32(MC_VM_AGP_BASE, 0);
1125 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1126 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1127 }
1128 if (evergreen_mc_wait_for_idle(rdev)) {
1129 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1130 }
1131 evergreen_mc_resume(rdev, &save);
1132 /* we need to own VRAM, so turn off the VGA renderer here
1133 * to stop it overwriting our objects */
1134 rv515_vga_render_disable(rdev);
1135}
1136
bcc1c2a1
AD		 1137/*
1138 * CP.
1139 */
bcc1c2a1
AD		 1140
1141static int evergreen_cp_load_microcode(struct radeon_device *rdev)
1142{
fe251e2f
AD		 1143 const __be32 *fw_data;
1144 int i;
1145
1146 if (!rdev->me_fw || !rdev->pfp_fw)
1147 return -EINVAL;
bcc1c2a1 1148
fe251e2f
AD		 1149 r700_cp_stop(rdev);
1150 WREG32(CP_RB_CNTL, RB_NO_UPDATE | (15 << 8) | (3 << 0));
1151
1152 fw_data = (const __be32 *)rdev->pfp_fw->data;
1153 WREG32(CP_PFP_UCODE_ADDR, 0);
1154 for (i = 0; i < EVERGREEN_PFP_UCODE_SIZE; i++)
1155 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
1156 WREG32(CP_PFP_UCODE_ADDR, 0);
1157
1158 fw_data = (const __be32 *)rdev->me_fw->data;
1159 WREG32(CP_ME_RAM_WADDR, 0);
1160 for (i = 0; i < EVERGREEN_PM4_UCODE_SIZE; i++)
1161 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
1162
1163 WREG32(CP_PFP_UCODE_ADDR, 0);
1164 WREG32(CP_ME_RAM_WADDR, 0);
1165 WREG32(CP_ME_RAM_RADDR, 0);
bcc1c2a1
AD		 1166 return 0;
1167}
1168
7e7b41d2
AD		 1169static int evergreen_cp_start(struct radeon_device *rdev)
1170{
2281a378 1171 int r, i;
7e7b41d2
AD		 1172 uint32_t cp_me;
1173
1174 r = radeon_ring_lock(rdev, 7);
1175 if (r) {
1176 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1177 return r;
1178 }
1179 radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5));
1180 radeon_ring_write(rdev, 0x1);
1181 radeon_ring_write(rdev, 0x0);
1182 radeon_ring_write(rdev, rdev->config.evergreen.max_hw_contexts - 1);
1183 radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1184 radeon_ring_write(rdev, 0);
1185 radeon_ring_write(rdev, 0);
1186 radeon_ring_unlock_commit(rdev);
1187
1188 cp_me = 0xff;
1189 WREG32(CP_ME_CNTL, cp_me);
1190
2281a378 1191 r = radeon_ring_lock(rdev, evergreen_default_size + 15);
7e7b41d2
AD		 1192 if (r) {
1193 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1194 return r;
1195 }
2281a378
AD		 1196
1197 /* setup clear context state */
1198 radeon_ring_write(rdev, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1199 radeon_ring_write(rdev, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
1200
1201 for (i = 0; i < evergreen_default_size; i++)
1202 radeon_ring_write(rdev, evergreen_default_state[i]);
1203
1204 radeon_ring_write(rdev, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1205 radeon_ring_write(rdev, PACKET3_PREAMBLE_END_CLEAR_STATE);
1206
1207 /* set clear context state */
1208 radeon_ring_write(rdev, PACKET3(PACKET3_CLEAR_STATE, 0));
1209 radeon_ring_write(rdev, 0);
1210
1211 /* SQ_VTX_BASE_VTX_LOC */
1212 radeon_ring_write(rdev, 0xc0026f00);
1213 radeon_ring_write(rdev, 0x00000000);
1214 radeon_ring_write(rdev, 0x00000000);
1215 radeon_ring_write(rdev, 0x00000000);
1216
1217 /* Clear consts */
1218 radeon_ring_write(rdev, 0xc0036f00);
1219 radeon_ring_write(rdev, 0x00000bc4);
1220 radeon_ring_write(rdev, 0xffffffff);
1221 radeon_ring_write(rdev, 0xffffffff);
1222 radeon_ring_write(rdev, 0xffffffff);
1223
7e7b41d2
AD		 1224 radeon_ring_unlock_commit(rdev);
1225
1226 return 0;
1227}
1228
fe251e2f
AD		 1229int evergreen_cp_resume(struct radeon_device *rdev)
1230{
1231 u32 tmp;
1232 u32 rb_bufsz;
1233 int r;
1234
1235 /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
1236 WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
1237 SOFT_RESET_PA |
1238 SOFT_RESET_SH |
1239 SOFT_RESET_VGT |
1240 SOFT_RESET_SX));
1241 RREG32(GRBM_SOFT_RESET);
1242 mdelay(15);
1243 WREG32(GRBM_SOFT_RESET, 0);
1244 RREG32(GRBM_SOFT_RESET);
1245
1246 /* Set ring buffer size */
1247 rb_bufsz = drm_order(rdev->cp.ring_size / 8);
724c80e1 1248 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
fe251e2f
AD		 1249#ifdef __BIG_ENDIAN
1250 tmp |= BUF_SWAP_32BIT;
32fcdbf4 1251#endif
fe251e2f
AD		 1252 WREG32(CP_RB_CNTL, tmp);
1253 WREG32(CP_SEM_WAIT_TIMER, 0x4);
1254
1255 /* Set the write pointer delay */
1256 WREG32(CP_RB_WPTR_DELAY, 0);
1257
1258 /* Initialize the ring buffer's read and write pointers */
1259 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
1260 WREG32(CP_RB_RPTR_WR, 0);
1261 WREG32(CP_RB_WPTR, 0);
724c80e1
AD		 1262
1263 /* set the wb address wether it's enabled or not */
1264 WREG32(CP_RB_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC);
1265 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
1266 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
1267
1268 if (rdev->wb.enabled)
1269 WREG32(SCRATCH_UMSK, 0xff);
1270 else {
1271 tmp |= RB_NO_UPDATE;
1272 WREG32(SCRATCH_UMSK, 0);
1273 }
1274
fe251e2f
AD		 1275 mdelay(1);
1276 WREG32(CP_RB_CNTL, tmp);
1277
1278 WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8);
1279 WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
1280
1281 rdev->cp.rptr = RREG32(CP_RB_RPTR);
1282 rdev->cp.wptr = RREG32(CP_RB_WPTR);
1283
7e7b41d2 1284 evergreen_cp_start(rdev);
fe251e2f
AD		 1285 rdev->cp.ready = true;
1286 r = radeon_ring_test(rdev);
1287 if (r) {
1288 rdev->cp.ready = false;
1289 return r;
1290 }
1291 return 0;
1292}
bcc1c2a1
AD		 1293
1294/*
1295 * Core functions
1296 */
32fcdbf4
AD		 1297static u32 evergreen_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
1298 u32 num_tile_pipes,
bcc1c2a1
AD		 1299 u32 num_backends,
1300 u32 backend_disable_mask)
1301{
1302 u32 backend_map = 0;
32fcdbf4
AD		 1303 u32 enabled_backends_mask = 0;
1304 u32 enabled_backends_count = 0;
1305 u32 cur_pipe;
1306 u32 swizzle_pipe[EVERGREEN_MAX_PIPES];
1307 u32 cur_backend = 0;
1308 u32 i;
1309 bool force_no_swizzle;
1310
1311 if (num_tile_pipes > EVERGREEN_MAX_PIPES)
1312 num_tile_pipes = EVERGREEN_MAX_PIPES;
1313 if (num_tile_pipes < 1)
1314 num_tile_pipes = 1;
1315 if (num_backends > EVERGREEN_MAX_BACKENDS)
1316 num_backends = EVERGREEN_MAX_BACKENDS;
1317 if (num_backends < 1)
1318 num_backends = 1;
1319
1320 for (i = 0; i < EVERGREEN_MAX_BACKENDS; ++i) {
1321 if (((backend_disable_mask >> i) & 1) == 0) {
1322 enabled_backends_mask |= (1 << i);
1323 ++enabled_backends_count;
1324 }
1325 if (enabled_backends_count == num_backends)
1326 break;
1327 }
1328
1329 if (enabled_backends_count == 0) {
1330 enabled_backends_mask = 1;
1331 enabled_backends_count = 1;
1332 }
1333
1334 if (enabled_backends_count != num_backends)
1335 num_backends = enabled_backends_count;
1336
1337 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * EVERGREEN_MAX_PIPES);
1338 switch (rdev->family) {
1339 case CHIP_CEDAR:
1340 case CHIP_REDWOOD:
1341 force_no_swizzle = false;
1342 break;
1343 case CHIP_CYPRESS:
1344 case CHIP_HEMLOCK:
1345 case CHIP_JUNIPER:
1346 default:
1347 force_no_swizzle = true;
1348 break;
1349 }
1350 if (force_no_swizzle) {
1351 bool last_backend_enabled = false;
1352
1353 force_no_swizzle = false;
1354 for (i = 0; i < EVERGREEN_MAX_BACKENDS; ++i) {
1355 if (((enabled_backends_mask >> i) & 1) == 1) {
1356 if (last_backend_enabled)
1357 force_no_swizzle = true;
1358 last_backend_enabled = true;
1359 } else
1360 last_backend_enabled = false;
1361 }
1362 }
1363
1364 switch (num_tile_pipes) {
1365 case 1:
1366 case 3:
1367 case 5:
1368 case 7:
1369 DRM_ERROR("odd number of pipes!\n");
1370 break;
1371 case 2:
1372 swizzle_pipe[0] = 0;
1373 swizzle_pipe[1] = 1;
1374 break;
1375 case 4:
1376 if (force_no_swizzle) {
1377 swizzle_pipe[0] = 0;
1378 swizzle_pipe[1] = 1;
1379 swizzle_pipe[2] = 2;
1380 swizzle_pipe[3] = 3;
1381 } else {
1382 swizzle_pipe[0] = 0;
1383 swizzle_pipe[1] = 2;
1384 swizzle_pipe[2] = 1;
1385 swizzle_pipe[3] = 3;
1386 }
1387 break;
1388 case 6:
1389 if (force_no_swizzle) {
1390 swizzle_pipe[0] = 0;
1391 swizzle_pipe[1] = 1;
1392 swizzle_pipe[2] = 2;
1393 swizzle_pipe[3] = 3;
1394 swizzle_pipe[4] = 4;
1395 swizzle_pipe[5] = 5;
1396 } else {
1397 swizzle_pipe[0] = 0;
1398 swizzle_pipe[1] = 2;
1399 swizzle_pipe[2] = 4;
1400 swizzle_pipe[3] = 1;
1401 swizzle_pipe[4] = 3;
1402 swizzle_pipe[5] = 5;
1403 }
1404 break;
1405 case 8:
1406 if (force_no_swizzle) {
1407 swizzle_pipe[0] = 0;
1408 swizzle_pipe[1] = 1;
1409 swizzle_pipe[2] = 2;
1410 swizzle_pipe[3] = 3;
1411 swizzle_pipe[4] = 4;
1412 swizzle_pipe[5] = 5;
1413 swizzle_pipe[6] = 6;
1414 swizzle_pipe[7] = 7;
1415 } else {
1416 swizzle_pipe[0] = 0;
1417 swizzle_pipe[1] = 2;
1418 swizzle_pipe[2] = 4;
1419 swizzle_pipe[3] = 6;
1420 swizzle_pipe[4] = 1;
1421 swizzle_pipe[5] = 3;
1422 swizzle_pipe[6] = 5;
1423 swizzle_pipe[7] = 7;
1424 }
1425 break;
1426 }
1427
1428 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
1429 while (((1 << cur_backend) & enabled_backends_mask) == 0)
1430 cur_backend = (cur_backend + 1) % EVERGREEN_MAX_BACKENDS;
1431
1432 backend_map |= (((cur_backend & 0xf) << (swizzle_pipe[cur_pipe] * 4)));
1433
1434 cur_backend = (cur_backend + 1) % EVERGREEN_MAX_BACKENDS;
1435 }
bcc1c2a1
AD		 1436
1437 return backend_map;
1438}
bcc1c2a1
AD		 1439
1440static void evergreen_gpu_init(struct radeon_device *rdev)
1441{
32fcdbf4
AD		 1442 u32 cc_rb_backend_disable = 0;
1443 u32 cc_gc_shader_pipe_config;
1444 u32 gb_addr_config = 0;
1445 u32 mc_shared_chmap, mc_arb_ramcfg;
1446 u32 gb_backend_map;
1447 u32 grbm_gfx_index;
1448 u32 sx_debug_1;
1449 u32 smx_dc_ctl0;
1450 u32 sq_config;
1451 u32 sq_lds_resource_mgmt;
1452 u32 sq_gpr_resource_mgmt_1;
1453 u32 sq_gpr_resource_mgmt_2;
1454 u32 sq_gpr_resource_mgmt_3;
1455 u32 sq_thread_resource_mgmt;
1456 u32 sq_thread_resource_mgmt_2;
1457 u32 sq_stack_resource_mgmt_1;
1458 u32 sq_stack_resource_mgmt_2;
1459 u32 sq_stack_resource_mgmt_3;
1460 u32 vgt_cache_invalidation;
1461 u32 hdp_host_path_cntl;
1462 int i, j, num_shader_engines, ps_thread_count;
1463
1464 switch (rdev->family) {
1465 case CHIP_CYPRESS:
1466 case CHIP_HEMLOCK:
1467 rdev->config.evergreen.num_ses = 2;
1468 rdev->config.evergreen.max_pipes = 4;
1469 rdev->config.evergreen.max_tile_pipes = 8;
1470 rdev->config.evergreen.max_simds = 10;
1471 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1472 rdev->config.evergreen.max_gprs = 256;
1473 rdev->config.evergreen.max_threads = 248;
1474 rdev->config.evergreen.max_gs_threads = 32;
1475 rdev->config.evergreen.max_stack_entries = 512;
1476 rdev->config.evergreen.sx_num_of_sets = 4;
1477 rdev->config.evergreen.sx_max_export_size = 256;
1478 rdev->config.evergreen.sx_max_export_pos_size = 64;
1479 rdev->config.evergreen.sx_max_export_smx_size = 192;
1480 rdev->config.evergreen.max_hw_contexts = 8;
1481 rdev->config.evergreen.sq_num_cf_insts = 2;
1482
1483 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1484 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1485 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1486 break;
1487 case CHIP_JUNIPER:
1488 rdev->config.evergreen.num_ses = 1;
1489 rdev->config.evergreen.max_pipes = 4;
1490 rdev->config.evergreen.max_tile_pipes = 4;
1491 rdev->config.evergreen.max_simds = 10;
1492 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1493 rdev->config.evergreen.max_gprs = 256;
1494 rdev->config.evergreen.max_threads = 248;
1495 rdev->config.evergreen.max_gs_threads = 32;
1496 rdev->config.evergreen.max_stack_entries = 512;
1497 rdev->config.evergreen.sx_num_of_sets = 4;
1498 rdev->config.evergreen.sx_max_export_size = 256;
1499 rdev->config.evergreen.sx_max_export_pos_size = 64;
1500 rdev->config.evergreen.sx_max_export_smx_size = 192;
1501 rdev->config.evergreen.max_hw_contexts = 8;
1502 rdev->config.evergreen.sq_num_cf_insts = 2;
1503
1504 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1505 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1506 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1507 break;
1508 case CHIP_REDWOOD:
1509 rdev->config.evergreen.num_ses = 1;
1510 rdev->config.evergreen.max_pipes = 4;
1511 rdev->config.evergreen.max_tile_pipes = 4;
1512 rdev->config.evergreen.max_simds = 5;
1513 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1514 rdev->config.evergreen.max_gprs = 256;
1515 rdev->config.evergreen.max_threads = 248;
1516 rdev->config.evergreen.max_gs_threads = 32;
1517 rdev->config.evergreen.max_stack_entries = 256;
1518 rdev->config.evergreen.sx_num_of_sets = 4;
1519 rdev->config.evergreen.sx_max_export_size = 256;
1520 rdev->config.evergreen.sx_max_export_pos_size = 64;
1521 rdev->config.evergreen.sx_max_export_smx_size = 192;
1522 rdev->config.evergreen.max_hw_contexts = 8;
1523 rdev->config.evergreen.sq_num_cf_insts = 2;
1524
1525 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1526 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1527 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1528 break;
1529 case CHIP_CEDAR:
1530 default:
1531 rdev->config.evergreen.num_ses = 1;
1532 rdev->config.evergreen.max_pipes = 2;
1533 rdev->config.evergreen.max_tile_pipes = 2;
1534 rdev->config.evergreen.max_simds = 2;
1535 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1536 rdev->config.evergreen.max_gprs = 256;
1537 rdev->config.evergreen.max_threads = 192;
1538 rdev->config.evergreen.max_gs_threads = 16;
1539 rdev->config.evergreen.max_stack_entries = 256;
1540 rdev->config.evergreen.sx_num_of_sets = 4;
1541 rdev->config.evergreen.sx_max_export_size = 128;
1542 rdev->config.evergreen.sx_max_export_pos_size = 32;
1543 rdev->config.evergreen.sx_max_export_smx_size = 96;
1544 rdev->config.evergreen.max_hw_contexts = 4;
1545 rdev->config.evergreen.sq_num_cf_insts = 1;
1546
1547 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1548 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1549 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1550 break;
1551 }
1552
1553 /* Initialize HDP */
1554 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1555 WREG32((0x2c14 + j), 0x00000000);
1556 WREG32((0x2c18 + j), 0x00000000);
1557 WREG32((0x2c1c + j), 0x00000000);
1558 WREG32((0x2c20 + j), 0x00000000);
1559 WREG32((0x2c24 + j), 0x00000000);
1560 }
1561
1562 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1563
1564 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & ~2;
1565
1566 cc_gc_shader_pipe_config |=
1567 INACTIVE_QD_PIPES((EVERGREEN_MAX_PIPES_MASK << rdev->config.evergreen.max_pipes)
1568 & EVERGREEN_MAX_PIPES_MASK);
1569 cc_gc_shader_pipe_config |=
1570 INACTIVE_SIMDS((EVERGREEN_MAX_SIMDS_MASK << rdev->config.evergreen.max_simds)
1571 & EVERGREEN_MAX_SIMDS_MASK);
1572
1573 cc_rb_backend_disable =
1574 BACKEND_DISABLE((EVERGREEN_MAX_BACKENDS_MASK << rdev->config.evergreen.max_backends)
1575 & EVERGREEN_MAX_BACKENDS_MASK);
1576
1577
1578 mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
1579 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
1580
1581 switch (rdev->config.evergreen.max_tile_pipes) {
1582 case 1:
1583 default:
1584 gb_addr_config |= NUM_PIPES(0);
1585 break;
1586 case 2:
1587 gb_addr_config |= NUM_PIPES(1);
1588 break;
1589 case 4:
1590 gb_addr_config |= NUM_PIPES(2);
1591 break;
1592 case 8:
1593 gb_addr_config |= NUM_PIPES(3);
1594 break;
1595 }
1596
1597 gb_addr_config |= PIPE_INTERLEAVE_SIZE((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
1598 gb_addr_config |= BANK_INTERLEAVE_SIZE(0);
1599 gb_addr_config |= NUM_SHADER_ENGINES(rdev->config.evergreen.num_ses - 1);
1600 gb_addr_config |= SHADER_ENGINE_TILE_SIZE(1);
1601 gb_addr_config |= NUM_GPUS(0); /* Hemlock? */
1602 gb_addr_config |= MULTI_GPU_TILE_SIZE(2);
1603
1604 if (((mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) > 2)
1605 gb_addr_config |= ROW_SIZE(2);
1606 else
1607 gb_addr_config |= ROW_SIZE((mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT);
1608
1609 if (rdev->ddev->pdev->device == 0x689e) {
1610 u32 efuse_straps_4;
1611 u32 efuse_straps_3;
1612 u8 efuse_box_bit_131_124;
1613
1614 WREG32(RCU_IND_INDEX, 0x204);
1615 efuse_straps_4 = RREG32(RCU_IND_DATA);
1616 WREG32(RCU_IND_INDEX, 0x203);
1617 efuse_straps_3 = RREG32(RCU_IND_DATA);
1618 efuse_box_bit_131_124 = (u8)(((efuse_straps_4 & 0xf) << 4) | ((efuse_straps_3 & 0xf0000000) >> 28));
1619
1620 switch(efuse_box_bit_131_124) {
1621 case 0x00:
1622 gb_backend_map = 0x76543210;
1623 break;
1624 case 0x55:
1625 gb_backend_map = 0x77553311;
1626 break;
1627 case 0x56:
1628 gb_backend_map = 0x77553300;
1629 break;
1630 case 0x59:
1631 gb_backend_map = 0x77552211;
1632 break;
1633 case 0x66:
1634 gb_backend_map = 0x77443300;
1635 break;
1636 case 0x99:
1637 gb_backend_map = 0x66552211;
1638 break;
1639 case 0x5a:
1640 gb_backend_map = 0x77552200;
1641 break;
1642 case 0xaa:
1643 gb_backend_map = 0x66442200;
1644 break;
1645 case 0x95:
1646 gb_backend_map = 0x66553311;
1647 break;
1648 default:
1649 DRM_ERROR("bad backend map, using default\n");
1650 gb_backend_map =
1651 evergreen_get_tile_pipe_to_backend_map(rdev,
1652 rdev->config.evergreen.max_tile_pipes,
1653 rdev->config.evergreen.max_backends,
1654 ((EVERGREEN_MAX_BACKENDS_MASK <<
1655 rdev->config.evergreen.max_backends) &
1656 EVERGREEN_MAX_BACKENDS_MASK));
1657 break;
1658 }
1659 } else if (rdev->ddev->pdev->device == 0x68b9) {
1660 u32 efuse_straps_3;
1661 u8 efuse_box_bit_127_124;
1662
1663 WREG32(RCU_IND_INDEX, 0x203);
1664 efuse_straps_3 = RREG32(RCU_IND_DATA);
d31dba58 1665 efuse_box_bit_127_124 = (u8)((efuse_straps_3 & 0xF0000000) >> 28);
32fcdbf4
AD		 1666
1667 switch(efuse_box_bit_127_124) {
1668 case 0x0:
1669 gb_backend_map = 0x00003210;
1670 break;
1671 case 0x5:
1672 case 0x6:
1673 case 0x9:
1674 case 0xa:
1675 gb_backend_map = 0x00003311;
1676 break;
1677 default:
1678 DRM_ERROR("bad backend map, using default\n");
1679 gb_backend_map =
1680 evergreen_get_tile_pipe_to_backend_map(rdev,
1681 rdev->config.evergreen.max_tile_pipes,
1682 rdev->config.evergreen.max_backends,
1683 ((EVERGREEN_MAX_BACKENDS_MASK <<
1684 rdev->config.evergreen.max_backends) &
1685 EVERGREEN_MAX_BACKENDS_MASK));
1686 break;
1687 }
b741be82
AD		 1688 } else {
1689 switch (rdev->family) {
1690 case CHIP_CYPRESS:
1691 case CHIP_HEMLOCK:
1692 gb_backend_map = 0x66442200;
1693 break;
1694 case CHIP_JUNIPER:
1695 gb_backend_map = 0x00006420;
1696 break;
1697 default:
1698 gb_backend_map =
1699 evergreen_get_tile_pipe_to_backend_map(rdev,
1700 rdev->config.evergreen.max_tile_pipes,
1701 rdev->config.evergreen.max_backends,
1702 ((EVERGREEN_MAX_BACKENDS_MASK <<
1703 rdev->config.evergreen.max_backends) &
1704 EVERGREEN_MAX_BACKENDS_MASK));
1705 }
1706 }
32fcdbf4 1707
1aa52bd3
AD		 1708 /* setup tiling info dword. gb_addr_config is not adequate since it does
1709 * not have bank info, so create a custom tiling dword.
1710 * bits 3:0 num_pipes
1711 * bits 7:4 num_banks
1712 * bits 11:8 group_size
1713 * bits 15:12 row_size
1714 */
1715 rdev->config.evergreen.tile_config = 0;
1716 switch (rdev->config.evergreen.max_tile_pipes) {
1717 case 1:
1718 default:
1719 rdev->config.evergreen.tile_config |= (0 << 0);
1720 break;
1721 case 2:
1722 rdev->config.evergreen.tile_config |= (1 << 0);
1723 break;
1724 case 4:
1725 rdev->config.evergreen.tile_config |= (2 << 0);
1726 break;
1727 case 8:
1728 rdev->config.evergreen.tile_config |= (3 << 0);
1729 break;
1730 }
1731 rdev->config.evergreen.tile_config |=
1732 ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) << 4;
1733 rdev->config.evergreen.tile_config |=
1734 ((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT) << 8;
1735 rdev->config.evergreen.tile_config |=
1736 ((gb_addr_config & 0x30000000) >> 28) << 12;
1737
32fcdbf4
AD		 1738 WREG32(GB_BACKEND_MAP, gb_backend_map);
1739 WREG32(GB_ADDR_CONFIG, gb_addr_config);
1740 WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
1741 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
1742
1743 num_shader_engines = ((RREG32(GB_ADDR_CONFIG) & NUM_SHADER_ENGINES(3)) >> 12) + 1;
1744 grbm_gfx_index = INSTANCE_BROADCAST_WRITES;
1745
1746 for (i = 0; i < rdev->config.evergreen.num_ses; i++) {
1747 u32 rb = cc_rb_backend_disable | (0xf0 << 16);
1748 u32 sp = cc_gc_shader_pipe_config;
1749 u32 gfx = grbm_gfx_index | SE_INDEX(i);
1750
1751 if (i == num_shader_engines) {
1752 rb |= BACKEND_DISABLE(EVERGREEN_MAX_BACKENDS_MASK);
1753 sp |= INACTIVE_SIMDS(EVERGREEN_MAX_SIMDS_MASK);
1754 }
1755
1756 WREG32(GRBM_GFX_INDEX, gfx);
1757 WREG32(RLC_GFX_INDEX, gfx);
1758
1759 WREG32(CC_RB_BACKEND_DISABLE, rb);
1760 WREG32(CC_SYS_RB_BACKEND_DISABLE, rb);
1761 WREG32(GC_USER_RB_BACKEND_DISABLE, rb);
1762 WREG32(CC_GC_SHADER_PIPE_CONFIG, sp);
1763 }
1764
1765 grbm_gfx_index |= SE_BROADCAST_WRITES;
1766 WREG32(GRBM_GFX_INDEX, grbm_gfx_index);
1767 WREG32(RLC_GFX_INDEX, grbm_gfx_index);
1768
1769 WREG32(CGTS_SYS_TCC_DISABLE, 0);
1770 WREG32(CGTS_TCC_DISABLE, 0);
1771 WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
1772 WREG32(CGTS_USER_TCC_DISABLE, 0);
1773
1774 /* set HW defaults for 3D engine */
1775 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
1776 ROQ_IB2_START(0x2b)));
1777
1778 WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
1779
1780 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO |
1781 SYNC_GRADIENT |
1782 SYNC_WALKER |
1783 SYNC_ALIGNER));
1784
1785 sx_debug_1 = RREG32(SX_DEBUG_1);
1786 sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
1787 WREG32(SX_DEBUG_1, sx_debug_1);
1788
1789
1790 smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
1791 smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff);
1792 smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.evergreen.sx_num_of_sets);
1793 WREG32(SMX_DC_CTL0, smx_dc_ctl0);
1794
1795 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_size / 4) - 1) |
1796 POSITION_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_pos_size / 4) - 1) |
1797 SMX_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_smx_size / 4) - 1)));
1798
1799 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.evergreen.sc_prim_fifo_size) |
1800 SC_HIZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_hiz_tile_fifo_size) |
1801 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_earlyz_tile_fifo_size)));
1802
1803 WREG32(VGT_NUM_INSTANCES, 1);
1804 WREG32(SPI_CONFIG_CNTL, 0);
1805 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
1806 WREG32(CP_PERFMON_CNTL, 0);
1807
1808 WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.evergreen.sq_num_cf_insts) |
1809 FETCH_FIFO_HIWATER(0x4) |
1810 DONE_FIFO_HIWATER(0xe0) |
1811 ALU_UPDATE_FIFO_HIWATER(0x8)));
1812
1813 sq_config = RREG32(SQ_CONFIG);
1814 sq_config &= ~(PS_PRIO(3) |
1815 VS_PRIO(3) |
1816 GS_PRIO(3) |
1817 ES_PRIO(3));
1818 sq_config |= (VC_ENABLE |
1819 EXPORT_SRC_C |
1820 PS_PRIO(0) |
1821 VS_PRIO(1) |
1822 GS_PRIO(2) |
1823 ES_PRIO(3));
1824
1825 if (rdev->family == CHIP_CEDAR)
1826 /* no vertex cache */
1827 sq_config &= ~VC_ENABLE;
1828
1829 sq_lds_resource_mgmt = RREG32(SQ_LDS_RESOURCE_MGMT);
1830
1831 sq_gpr_resource_mgmt_1 = NUM_PS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2))* 12 / 32);
1832 sq_gpr_resource_mgmt_1 |= NUM_VS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 6 / 32);
1833 sq_gpr_resource_mgmt_1 |= NUM_CLAUSE_TEMP_GPRS(4);
1834 sq_gpr_resource_mgmt_2 = NUM_GS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
1835 sq_gpr_resource_mgmt_2 |= NUM_ES_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
1836 sq_gpr_resource_mgmt_3 = NUM_HS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
1837 sq_gpr_resource_mgmt_3 |= NUM_LS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
1838
1839 if (rdev->family == CHIP_CEDAR)
1840 ps_thread_count = 96;
1841 else
1842 ps_thread_count = 128;
1843
1844 sq_thread_resource_mgmt = NUM_PS_THREADS(ps_thread_count);
f96b35cd
AD		 1845 sq_thread_resource_mgmt |= NUM_VS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
1846 sq_thread_resource_mgmt |= NUM_GS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
1847 sq_thread_resource_mgmt |= NUM_ES_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
1848 sq_thread_resource_mgmt_2 = NUM_HS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
1849 sq_thread_resource_mgmt_2 |= NUM_LS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
32fcdbf4
AD		 1850
1851 sq_stack_resource_mgmt_1 = NUM_PS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
1852 sq_stack_resource_mgmt_1 |= NUM_VS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
1853 sq_stack_resource_mgmt_2 = NUM_GS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
1854 sq_stack_resource_mgmt_2 |= NUM_ES_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
1855 sq_stack_resource_mgmt_3 = NUM_HS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
1856 sq_stack_resource_mgmt_3 |= NUM_LS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
1857
1858 WREG32(SQ_CONFIG, sq_config);
1859 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
1860 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
1861 WREG32(SQ_GPR_RESOURCE_MGMT_3, sq_gpr_resource_mgmt_3);
1862 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1863 WREG32(SQ_THREAD_RESOURCE_MGMT_2, sq_thread_resource_mgmt_2);
1864 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
1865 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
1866 WREG32(SQ_STACK_RESOURCE_MGMT_3, sq_stack_resource_mgmt_3);
1867 WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
1868 WREG32(SQ_LDS_RESOURCE_MGMT, sq_lds_resource_mgmt);
1869
1870 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
1871 FORCE_EOV_MAX_REZ_CNT(255)));
1872
1873 if (rdev->family == CHIP_CEDAR)
1874 vgt_cache_invalidation = CACHE_INVALIDATION(TC_ONLY);
1875 else
1876 vgt_cache_invalidation = CACHE_INVALIDATION(VC_AND_TC);
1877 vgt_cache_invalidation |= AUTO_INVLD_EN(ES_AND_GS_AUTO);
1878 WREG32(VGT_CACHE_INVALIDATION, vgt_cache_invalidation);
1879
1880 WREG32(VGT_GS_VERTEX_REUSE, 16);
1881 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1882
60a4a3e0
AD		 1883 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
1884 WREG32(VGT_OUT_DEALLOC_CNTL, 16);
1885
32fcdbf4
AD		 1886 WREG32(CB_PERF_CTR0_SEL_0, 0);
1887 WREG32(CB_PERF_CTR0_SEL_1, 0);
1888 WREG32(CB_PERF_CTR1_SEL_0, 0);
1889 WREG32(CB_PERF_CTR1_SEL_1, 0);
1890 WREG32(CB_PERF_CTR2_SEL_0, 0);
1891 WREG32(CB_PERF_CTR2_SEL_1, 0);
1892 WREG32(CB_PERF_CTR3_SEL_0, 0);
1893 WREG32(CB_PERF_CTR3_SEL_1, 0);
1894
60a4a3e0
AD		 1895 /* clear render buffer base addresses */
1896 WREG32(CB_COLOR0_BASE, 0);
1897 WREG32(CB_COLOR1_BASE, 0);
1898 WREG32(CB_COLOR2_BASE, 0);
1899 WREG32(CB_COLOR3_BASE, 0);
1900 WREG32(CB_COLOR4_BASE, 0);
1901 WREG32(CB_COLOR5_BASE, 0);
1902 WREG32(CB_COLOR6_BASE, 0);
1903 WREG32(CB_COLOR7_BASE, 0);
1904 WREG32(CB_COLOR8_BASE, 0);
1905 WREG32(CB_COLOR9_BASE, 0);
1906 WREG32(CB_COLOR10_BASE, 0);
1907 WREG32(CB_COLOR11_BASE, 0);
1908
1909 /* set the shader const cache sizes to 0 */
1910 for (i = SQ_ALU_CONST_BUFFER_SIZE_PS_0; i < 0x28200; i += 4)
1911 WREG32(i, 0);
1912 for (i = SQ_ALU_CONST_BUFFER_SIZE_HS_0; i < 0x29000; i += 4)
1913 WREG32(i, 0);
1914
32fcdbf4
AD		 1915 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
1916 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1917
1918 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
1919
1920 udelay(50);
1921
bcc1c2a1
AD		 1922}
1923
1924int evergreen_mc_init(struct radeon_device *rdev)
1925{
bcc1c2a1
AD		 1926 u32 tmp;
1927 int chansize, numchan;
bcc1c2a1
AD		 1928
1929 /* Get VRAM informations */
1930 rdev->mc.vram_is_ddr = true;
1931 tmp = RREG32(MC_ARB_RAMCFG);
1932 if (tmp & CHANSIZE_OVERRIDE) {
1933 chansize = 16;
1934 } else if (tmp & CHANSIZE_MASK) {
1935 chansize = 64;
1936 } else {
1937 chansize = 32;
1938 }
1939 tmp = RREG32(MC_SHARED_CHMAP);
1940 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1941 case 0:
1942 default:
1943 numchan = 1;
1944 break;
1945 case 1:
1946 numchan = 2;
1947 break;
1948 case 2:
1949 numchan = 4;
1950 break;
1951 case 3:
1952 numchan = 8;
1953 break;
1954 }
1955 rdev->mc.vram_width = numchan * chansize;
1956 /* Could aper size report 0 ? */
01d73a69
JC		 1957 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
1958 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
bcc1c2a1
AD		 1959 /* Setup GPU memory space */
1960 /* size in MB on evergreen */
1961 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
1962 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
51e5fcd3 1963 rdev->mc.visible_vram_size = rdev->mc.aper_size;
c919b371 1964 rdev->mc.active_vram_size = rdev->mc.visible_vram_size;
d594e46a 1965 r600_vram_gtt_location(rdev, &rdev->mc);
f47299c5
AD		 1966 radeon_update_bandwidth_info(rdev);
1967
bcc1c2a1
AD		 1968 return 0;
1969}
d594e46a 1970
225758d8
JG		 1971bool evergreen_gpu_is_lockup(struct radeon_device *rdev)
1972{
1973 /* FIXME: implement for evergreen */
1974 return false;
1975}
1976
747943ea 1977static int evergreen_gpu_soft_reset(struct radeon_device *rdev)
bcc1c2a1 1978{
747943ea
AD		 1979 struct evergreen_mc_save save;
1980 u32 srbm_reset = 0;
1981 u32 grbm_reset = 0;
1982
1983 dev_info(rdev->dev, "GPU softreset \n");
1984 dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
1985 RREG32(GRBM_STATUS));
1986 dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
1987 RREG32(GRBM_STATUS_SE0));
1988 dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
1989 RREG32(GRBM_STATUS_SE1));
1990 dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
1991 RREG32(SRBM_STATUS));
1992 evergreen_mc_stop(rdev, &save);
1993 if (evergreen_mc_wait_for_idle(rdev)) {
1994 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1995 }
1996 /* Disable CP parsing/prefetching */
1997 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
1998
1999 /* reset all the gfx blocks */
2000 grbm_reset = (SOFT_RESET_CP |
2001 SOFT_RESET_CB |
2002 SOFT_RESET_DB |
2003 SOFT_RESET_PA |
2004 SOFT_RESET_SC |
2005 SOFT_RESET_SPI |
2006 SOFT_RESET_SH |
2007 SOFT_RESET_SX |
2008 SOFT_RESET_TC |
2009 SOFT_RESET_TA |
2010 SOFT_RESET_VC |
2011 SOFT_RESET_VGT);
2012
2013 dev_info(rdev->dev, " GRBM_SOFT_RESET=0x%08X\n", grbm_reset);
2014 WREG32(GRBM_SOFT_RESET, grbm_reset);
2015 (void)RREG32(GRBM_SOFT_RESET);
2016 udelay(50);
2017 WREG32(GRBM_SOFT_RESET, 0);
2018 (void)RREG32(GRBM_SOFT_RESET);
2019
2020 /* reset all the system blocks */
2021 srbm_reset = SRBM_SOFT_RESET_ALL_MASK;
2022
2023 dev_info(rdev->dev, " SRBM_SOFT_RESET=0x%08X\n", srbm_reset);
2024 WREG32(SRBM_SOFT_RESET, srbm_reset);
2025 (void)RREG32(SRBM_SOFT_RESET);
2026 udelay(50);
2027 WREG32(SRBM_SOFT_RESET, 0);
2028 (void)RREG32(SRBM_SOFT_RESET);
2029 /* Wait a little for things to settle down */
2030 udelay(50);
2031 dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
2032 RREG32(GRBM_STATUS));
2033 dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
2034 RREG32(GRBM_STATUS_SE0));
2035 dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
2036 RREG32(GRBM_STATUS_SE1));
2037 dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
2038 RREG32(SRBM_STATUS));
2039 /* After reset we need to reinit the asic as GPU often endup in an
2040 * incoherent state.
2041 */
2042 atom_asic_init(rdev->mode_info.atom_context);
2043 evergreen_mc_resume(rdev, &save);
bcc1c2a1
AD		 2044 return 0;
2045}
2046
a2d07b74 2047int evergreen_asic_reset(struct radeon_device *rdev)
bcc1c2a1 2048{
747943ea
AD		 2049 return evergreen_gpu_soft_reset(rdev);
2050}
2051
45f9a39b
AD		 2052/* Interrupts */
2053
2054u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc)
2055{
2056 switch (crtc) {
2057 case 0:
2058 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC0_REGISTER_OFFSET);
2059 case 1:
2060 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC1_REGISTER_OFFSET);
2061 case 2:
2062 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC2_REGISTER_OFFSET);
2063 case 3:
2064 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC3_REGISTER_OFFSET);
2065 case 4:
2066 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC4_REGISTER_OFFSET);
2067 case 5:
2068 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC5_REGISTER_OFFSET);
2069 default:
2070 return 0;
2071 }
2072}
2073
2074void evergreen_disable_interrupt_state(struct radeon_device *rdev)
2075{
2076 u32 tmp;
2077
3555e53b 2078 WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
45f9a39b
AD		 2079 WREG32(GRBM_INT_CNTL, 0);
2080 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2081 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
2082 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2083 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
2084 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2085 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2086
2087 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2088 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
2089 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2090 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
2091 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2092 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2093
2094 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
2095 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
2096
2097 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2098 WREG32(DC_HPD1_INT_CONTROL, tmp);
2099 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2100 WREG32(DC_HPD2_INT_CONTROL, tmp);
2101 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2102 WREG32(DC_HPD3_INT_CONTROL, tmp);
2103 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2104 WREG32(DC_HPD4_INT_CONTROL, tmp);
2105 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2106 WREG32(DC_HPD5_INT_CONTROL, tmp);
2107 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2108 WREG32(DC_HPD6_INT_CONTROL, tmp);
2109
2110}
2111
2112int evergreen_irq_set(struct radeon_device *rdev)
2113{
2114 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
2115 u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0;
2116 u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6;
2031f77c 2117 u32 grbm_int_cntl = 0;
6f34be50 2118 u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0;
45f9a39b
AD		 2119
2120 if (!rdev->irq.installed) {
fce7d61b 2121 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
45f9a39b
AD		 2122 return -EINVAL;
2123 }
2124 /* don't enable anything if the ih is disabled */
2125 if (!rdev->ih.enabled) {
2126 r600_disable_interrupts(rdev);
2127 /* force the active interrupt state to all disabled */
2128 evergreen_disable_interrupt_state(rdev);
2129 return 0;
2130 }
2131
2132 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
2133 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
2134 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
2135 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
2136 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
2137 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
2138
2139 if (rdev->irq.sw_int) {
2140 DRM_DEBUG("evergreen_irq_set: sw int\n");
2141 cp_int_cntl |= RB_INT_ENABLE;
d0f8a854 2142 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
45f9a39b 2143 }
6f34be50
AD		 2144 if (rdev->irq.crtc_vblank_int[0] ||
2145 rdev->irq.pflip[0]) {
45f9a39b
AD		 2146 DRM_DEBUG("evergreen_irq_set: vblank 0\n");
2147 crtc1 |= VBLANK_INT_MASK;
2148 }
6f34be50
AD		 2149 if (rdev->irq.crtc_vblank_int[1] ||
2150 rdev->irq.pflip[1]) {
45f9a39b
AD		 2151 DRM_DEBUG("evergreen_irq_set: vblank 1\n");
2152 crtc2 |= VBLANK_INT_MASK;
2153 }
6f34be50
AD		 2154 if (rdev->irq.crtc_vblank_int[2] ||
2155 rdev->irq.pflip[2]) {
45f9a39b
AD		 2156 DRM_DEBUG("evergreen_irq_set: vblank 2\n");
2157 crtc3 |= VBLANK_INT_MASK;
2158 }
6f34be50
AD		 2159 if (rdev->irq.crtc_vblank_int[3] ||
2160 rdev->irq.pflip[3]) {
45f9a39b
AD		 2161 DRM_DEBUG("evergreen_irq_set: vblank 3\n");
2162 crtc4 |= VBLANK_INT_MASK;
2163 }
6f34be50
AD		 2164 if (rdev->irq.crtc_vblank_int[4] ||
2165 rdev->irq.pflip[4]) {
45f9a39b
AD		 2166 DRM_DEBUG("evergreen_irq_set: vblank 4\n");
2167 crtc5 |= VBLANK_INT_MASK;
2168 }
6f34be50
AD		 2169 if (rdev->irq.crtc_vblank_int[5] ||
2170 rdev->irq.pflip[5]) {
45f9a39b
AD		 2171 DRM_DEBUG("evergreen_irq_set: vblank 5\n");
2172 crtc6 |= VBLANK_INT_MASK;
2173 }
2174 if (rdev->irq.hpd[0]) {
2175 DRM_DEBUG("evergreen_irq_set: hpd 1\n");
2176 hpd1 |= DC_HPDx_INT_EN;
2177 }
2178 if (rdev->irq.hpd[1]) {
2179 DRM_DEBUG("evergreen_irq_set: hpd 2\n");
2180 hpd2 |= DC_HPDx_INT_EN;
2181 }
2182 if (rdev->irq.hpd[2]) {
2183 DRM_DEBUG("evergreen_irq_set: hpd 3\n");
2184 hpd3 |= DC_HPDx_INT_EN;
2185 }
2186 if (rdev->irq.hpd[3]) {
2187 DRM_DEBUG("evergreen_irq_set: hpd 4\n");
2188 hpd4 |= DC_HPDx_INT_EN;
2189 }
2190 if (rdev->irq.hpd[4]) {
2191 DRM_DEBUG("evergreen_irq_set: hpd 5\n");
2192 hpd5 |= DC_HPDx_INT_EN;
2193 }
2194 if (rdev->irq.hpd[5]) {
2195 DRM_DEBUG("evergreen_irq_set: hpd 6\n");
2196 hpd6 |= DC_HPDx_INT_EN;
2197 }
2031f77c
AD		 2198 if (rdev->irq.gui_idle) {
2199 DRM_DEBUG("gui idle\n");
2200 grbm_int_cntl |= GUI_IDLE_INT_ENABLE;
2201 }
45f9a39b
AD		 2202
2203 WREG32(CP_INT_CNTL, cp_int_cntl);
2031f77c 2204 WREG32(GRBM_INT_CNTL, grbm_int_cntl);
45f9a39b
AD		 2205
2206 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);
2207 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2);
2208 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3);
2209 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4);
2210 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5);
2211 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);
2212
6f34be50
AD		 2213 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1);
2214 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2);
2215 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3);
2216 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4);
2217 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, grph5);
2218 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6);
2219
45f9a39b
AD		 2220 WREG32(DC_HPD1_INT_CONTROL, hpd1);
2221 WREG32(DC_HPD2_INT_CONTROL, hpd2);
2222 WREG32(DC_HPD3_INT_CONTROL, hpd3);
2223 WREG32(DC_HPD4_INT_CONTROL, hpd4);
2224 WREG32(DC_HPD5_INT_CONTROL, hpd5);
2225 WREG32(DC_HPD6_INT_CONTROL, hpd6);
2226
bcc1c2a1
AD		 2227 return 0;
2228}
2229
6f34be50 2230static inline void evergreen_irq_ack(struct radeon_device *rdev)
45f9a39b
AD		 2231{
2232 u32 tmp;
2233
6f34be50
AD		 2234 rdev->irq.stat_regs.evergreen.disp_int = RREG32(DISP_INTERRUPT_STATUS);
2235 rdev->irq.stat_regs.evergreen.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
2236 rdev->irq.stat_regs.evergreen.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2);
2237 rdev->irq.stat_regs.evergreen.disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3);
2238 rdev->irq.stat_regs.evergreen.disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4);
2239 rdev->irq.stat_regs.evergreen.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5);
2240 rdev->irq.stat_regs.evergreen.d1grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET);
2241 rdev->irq.stat_regs.evergreen.d2grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET);
2242 rdev->irq.stat_regs.evergreen.d3grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET);
2243 rdev->irq.stat_regs.evergreen.d4grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET);
2244 rdev->irq.stat_regs.evergreen.d5grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET);
2245 rdev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
2246
2247 if (rdev->irq.stat_regs.evergreen.d1grph_int & GRPH_PFLIP_INT_OCCURRED)
2248 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2249 if (rdev->irq.stat_regs.evergreen.d2grph_int & GRPH_PFLIP_INT_OCCURRED)
2250 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2251 if (rdev->irq.stat_regs.evergreen.d3grph_int & GRPH_PFLIP_INT_OCCURRED)
2252 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2253 if (rdev->irq.stat_regs.evergreen.d4grph_int & GRPH_PFLIP_INT_OCCURRED)
2254 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2255 if (rdev->irq.stat_regs.evergreen.d5grph_int & GRPH_PFLIP_INT_OCCURRED)
2256 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2257 if (rdev->irq.stat_regs.evergreen.d6grph_int & GRPH_PFLIP_INT_OCCURRED)
2258 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2259
2260 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT)
45f9a39b 2261 WREG32(VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK);
6f34be50 2262 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT)
45f9a39b
AD		 2263 WREG32(VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK);
2264
6f34be50 2265 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT)
45f9a39b 2266 WREG32(VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK);
6f34be50 2267 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT)
45f9a39b
AD		 2268 WREG32(VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK);
2269
6f34be50 2270 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT)
45f9a39b 2271 WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK);
6f34be50 2272 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT)
45f9a39b
AD		 2273 WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK);
2274
6f34be50 2275 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT)
45f9a39b 2276 WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK);
6f34be50 2277 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT)
45f9a39b
AD		 2278 WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK);
2279
6f34be50 2280 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT)
45f9a39b 2281 WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK);
6f34be50 2282 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT)
45f9a39b
AD		 2283 WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK);
2284
6f34be50 2285 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT)
45f9a39b 2286 WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK);
6f34be50 2287 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT)
45f9a39b
AD		 2288 WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK);
2289
6f34be50 2290 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
45f9a39b
AD		 2291 tmp = RREG32(DC_HPD1_INT_CONTROL);
2292 tmp |= DC_HPDx_INT_ACK;
2293 WREG32(DC_HPD1_INT_CONTROL, tmp);
2294 }
6f34be50 2295 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
45f9a39b
AD		 2296 tmp = RREG32(DC_HPD2_INT_CONTROL);
2297 tmp |= DC_HPDx_INT_ACK;
2298 WREG32(DC_HPD2_INT_CONTROL, tmp);
2299 }
6f34be50 2300 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
45f9a39b
AD		 2301 tmp = RREG32(DC_HPD3_INT_CONTROL);
2302 tmp |= DC_HPDx_INT_ACK;
2303 WREG32(DC_HPD3_INT_CONTROL, tmp);
2304 }
6f34be50 2305 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
45f9a39b
AD		 2306 tmp = RREG32(DC_HPD4_INT_CONTROL);
2307 tmp |= DC_HPDx_INT_ACK;
2308 WREG32(DC_HPD4_INT_CONTROL, tmp);
2309 }
6f34be50 2310 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
45f9a39b
AD		 2311 tmp = RREG32(DC_HPD5_INT_CONTROL);
2312 tmp |= DC_HPDx_INT_ACK;
2313 WREG32(DC_HPD5_INT_CONTROL, tmp);
2314 }
6f34be50 2315 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
45f9a39b
AD		 2316 tmp = RREG32(DC_HPD5_INT_CONTROL);
2317 tmp |= DC_HPDx_INT_ACK;
2318 WREG32(DC_HPD6_INT_CONTROL, tmp);
2319 }
2320}
2321
2322void evergreen_irq_disable(struct radeon_device *rdev)
2323{
45f9a39b
AD		 2324 r600_disable_interrupts(rdev);
2325 /* Wait and acknowledge irq */
2326 mdelay(1);
6f34be50 2327 evergreen_irq_ack(rdev);
45f9a39b
AD		 2328 evergreen_disable_interrupt_state(rdev);
2329}
2330
2331static void evergreen_irq_suspend(struct radeon_device *rdev)
2332{
2333 evergreen_irq_disable(rdev);
2334 r600_rlc_stop(rdev);
2335}
2336
2337static inline u32 evergreen_get_ih_wptr(struct radeon_device *rdev)
2338{
2339 u32 wptr, tmp;
2340
724c80e1
AD		 2341 if (rdev->wb.enabled)
2342 wptr = rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4];
2343 else
2344 wptr = RREG32(IH_RB_WPTR);
45f9a39b
AD		 2345
2346 if (wptr & RB_OVERFLOW) {
2347 /* When a ring buffer overflow happen start parsing interrupt
2348 * from the last not overwritten vector (wptr + 16). Hopefully
2349 * this should allow us to catchup.
2350 */
2351 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
2352 wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
2353 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
2354 tmp = RREG32(IH_RB_CNTL);
2355 tmp |= IH_WPTR_OVERFLOW_CLEAR;
2356 WREG32(IH_RB_CNTL, tmp);
2357 }
2358 return (wptr & rdev->ih.ptr_mask);
2359}
2360
2361int evergreen_irq_process(struct radeon_device *rdev)
2362{
2363 u32 wptr = evergreen_get_ih_wptr(rdev);
2364 u32 rptr = rdev->ih.rptr;
2365 u32 src_id, src_data;
2366 u32 ring_index;
45f9a39b
AD		 2367 unsigned long flags;
2368 bool queue_hotplug = false;
2369
2370 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
2371 if (!rdev->ih.enabled)
2372 return IRQ_NONE;
2373
2374 spin_lock_irqsave(&rdev->ih.lock, flags);
2375
2376 if (rptr == wptr) {
2377 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2378 return IRQ_NONE;
2379 }
2380 if (rdev->shutdown) {
2381 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2382 return IRQ_NONE;
2383 }
2384
2385restart_ih:
2386 /* display interrupts */
6f34be50 2387 evergreen_irq_ack(rdev);
45f9a39b
AD		 2388
2389 rdev->ih.wptr = wptr;
2390 while (rptr != wptr) {
2391 /* wptr/rptr are in bytes! */
2392 ring_index = rptr / 4;
2393 src_id = rdev->ih.ring[ring_index] & 0xff;
2394 src_data = rdev->ih.ring[ring_index + 1] & 0xfffffff;
2395
2396 switch (src_id) {
2397 case 1: /* D1 vblank/vline */
2398 switch (src_data) {
2399 case 0: /* D1 vblank */
6f34be50
AD		 2400 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT) {
2401 if (rdev->irq.pflip[0])
2402 radeon_crtc_handle_flip(rdev, 0);
2403 if (rdev->irq.crtc_vblank_int[0]) {
2404 drm_handle_vblank(rdev->ddev, 0);
2405 rdev->pm.vblank_sync = true;
2406 wake_up(&rdev->irq.vblank_queue);
2407 }
2408 rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
45f9a39b
AD		 2409 DRM_DEBUG("IH: D1 vblank\n");
2410 }
2411 break;
2412 case 1: /* D1 vline */
6f34be50
AD		 2413 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT) {
2414 rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VLINE_INTERRUPT;
45f9a39b
AD		 2415 DRM_DEBUG("IH: D1 vline\n");
2416 }
2417 break;
2418 default:
2419 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2420 break;
2421 }
2422 break;
2423 case 2: /* D2 vblank/vline */
2424 switch (src_data) {
2425 case 0: /* D2 vblank */
6f34be50
AD		 2426 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT) {
2427 if (rdev->irq.pflip[1])
2428 radeon_crtc_handle_flip(rdev, 1);
2429 if (rdev->irq.crtc_vblank_int[1]) {
2430 drm_handle_vblank(rdev->ddev, 1);
2431 rdev->pm.vblank_sync = true;
2432 wake_up(&rdev->irq.vblank_queue);
2433 }
2434 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT;
45f9a39b
AD		 2435 DRM_DEBUG("IH: D2 vblank\n");
2436 }
2437 break;
2438 case 1: /* D2 vline */
6f34be50
AD		 2439 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT) {
2440 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT;
45f9a39b
AD		 2441 DRM_DEBUG("IH: D2 vline\n");
2442 }
2443 break;
2444 default:
2445 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2446 break;
2447 }
2448 break;
2449 case 3: /* D3 vblank/vline */
2450 switch (src_data) {
2451 case 0: /* D3 vblank */
6f34be50
AD		 2452 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) {
2453 if (rdev->irq.crtc_vblank_int[2]) {
2454 drm_handle_vblank(rdev->ddev, 2);
2455 rdev->pm.vblank_sync = true;
2456 wake_up(&rdev->irq.vblank_queue);
2457 }
2458 if (rdev->irq.pflip[2])
2459 radeon_crtc_handle_flip(rdev, 2);
2460 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT;
45f9a39b
AD		 2461 DRM_DEBUG("IH: D3 vblank\n");
2462 }
2463 break;
2464 case 1: /* D3 vline */
6f34be50
AD		 2465 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) {
2466 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT;
45f9a39b
AD		 2467 DRM_DEBUG("IH: D3 vline\n");
2468 }
2469 break;
2470 default:
2471 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2472 break;
2473 }
2474 break;
2475 case 4: /* D4 vblank/vline */
2476 switch (src_data) {
2477 case 0: /* D4 vblank */
6f34be50
AD		 2478 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) {
2479 if (rdev->irq.crtc_vblank_int[3]) {
2480 drm_handle_vblank(rdev->ddev, 3);
2481 rdev->pm.vblank_sync = true;
2482 wake_up(&rdev->irq.vblank_queue);
2483 }
2484 if (rdev->irq.pflip[3])
2485 radeon_crtc_handle_flip(rdev, 3);
2486 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT;
45f9a39b
AD		 2487 DRM_DEBUG("IH: D4 vblank\n");
2488 }
2489 break;
2490 case 1: /* D4 vline */
6f34be50
AD		 2491 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) {
2492 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT;
45f9a39b
AD		 2493 DRM_DEBUG("IH: D4 vline\n");
2494 }
2495 break;
2496 default:
2497 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2498 break;
2499 }
2500 break;
2501 case 5: /* D5 vblank/vline */
2502 switch (src_data) {
2503 case 0: /* D5 vblank */
6f34be50
AD		 2504 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) {
2505 if (rdev->irq.crtc_vblank_int[4]) {
2506 drm_handle_vblank(rdev->ddev, 4);
2507 rdev->pm.vblank_sync = true;
2508 wake_up(&rdev->irq.vblank_queue);
2509 }
2510 if (rdev->irq.pflip[4])
2511 radeon_crtc_handle_flip(rdev, 4);
2512 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT;
45f9a39b
AD		 2513 DRM_DEBUG("IH: D5 vblank\n");
2514 }
2515 break;
2516 case 1: /* D5 vline */
6f34be50
AD		 2517 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) {
2518 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT;
45f9a39b
AD		 2519 DRM_DEBUG("IH: D5 vline\n");
2520 }
2521 break;
2522 default:
2523 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2524 break;
2525 }
2526 break;
2527 case 6: /* D6 vblank/vline */
2528 switch (src_data) {
2529 case 0: /* D6 vblank */
6f34be50
AD		 2530 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) {
2531 if (rdev->irq.crtc_vblank_int[5]) {
2532 drm_handle_vblank(rdev->ddev, 5);
2533 rdev->pm.vblank_sync = true;
2534 wake_up(&rdev->irq.vblank_queue);
2535 }
2536 if (rdev->irq.pflip[5])
2537 radeon_crtc_handle_flip(rdev, 5);
2538 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT;
45f9a39b
AD		 2539 DRM_DEBUG("IH: D6 vblank\n");
2540 }
2541 break;
2542 case 1: /* D6 vline */
6f34be50
AD		 2543 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) {
2544 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT;
45f9a39b
AD		 2545 DRM_DEBUG("IH: D6 vline\n");
2546 }
2547 break;
2548 default:
2549 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2550 break;
2551 }
2552 break;
2553 case 42: /* HPD hotplug */
2554 switch (src_data) {
2555 case 0:
6f34be50
AD		 2556 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
2557 rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_INTERRUPT;
45f9a39b
AD		 2558 queue_hotplug = true;
2559 DRM_DEBUG("IH: HPD1\n");
2560 }
2561 break;
2562 case 1:
6f34be50
AD		 2563 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
2564 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_INTERRUPT;
45f9a39b
AD		 2565 queue_hotplug = true;
2566 DRM_DEBUG("IH: HPD2\n");
2567 }
2568 break;
2569 case 2:
6f34be50
AD		 2570 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
2571 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_INTERRUPT;
45f9a39b
AD		 2572 queue_hotplug = true;
2573 DRM_DEBUG("IH: HPD3\n");
2574 }
2575 break;
2576 case 3:
6f34be50
AD		 2577 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
2578 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_INTERRUPT;
45f9a39b
AD		 2579 queue_hotplug = true;
2580 DRM_DEBUG("IH: HPD4\n");
2581 }
2582 break;
2583 case 4:
6f34be50
AD		 2584 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
2585 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_INTERRUPT;
45f9a39b
AD		 2586 queue_hotplug = true;
2587 DRM_DEBUG("IH: HPD5\n");
2588 }
2589 break;
2590 case 5:
6f34be50
AD		 2591 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
2592 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_INTERRUPT;
45f9a39b
AD		 2593 queue_hotplug = true;
2594 DRM_DEBUG("IH: HPD6\n");
2595 }
2596 break;
2597 default:
2598 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2599 break;
2600 }
2601 break;
2602 case 176: /* CP_INT in ring buffer */
2603 case 177: /* CP_INT in IB1 */
2604 case 178: /* CP_INT in IB2 */
2605 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
2606 radeon_fence_process(rdev);
2607 break;
2608 case 181: /* CP EOP event */
2609 DRM_DEBUG("IH: CP EOP\n");
d0f8a854 2610 radeon_fence_process(rdev);
45f9a39b 2611 break;
2031f77c
AD		 2612 case 233: /* GUI IDLE */
2613 DRM_DEBUG("IH: CP EOP\n");
2614 rdev->pm.gui_idle = true;
2615 wake_up(&rdev->irq.idle_queue);
2616 break;
45f9a39b
AD		 2617 default:
2618 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2619 break;
2620 }
2621
2622 /* wptr/rptr are in bytes! */
2623 rptr += 16;
2624 rptr &= rdev->ih.ptr_mask;
2625 }
2626 /* make sure wptr hasn't changed while processing */
2627 wptr = evergreen_get_ih_wptr(rdev);
2628 if (wptr != rdev->ih.wptr)
2629 goto restart_ih;
2630 if (queue_hotplug)
2631 queue_work(rdev->wq, &rdev->hotplug_work);
2632 rdev->ih.rptr = rptr;
2633 WREG32(IH_RB_RPTR, rdev->ih.rptr);
2634 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2635 return IRQ_HANDLED;
2636}
2637
bcc1c2a1
AD		 2638static int evergreen_startup(struct radeon_device *rdev)
2639{
bcc1c2a1
AD		 2640 int r;
2641
2642 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
2643 r = r600_init_microcode(rdev);
2644 if (r) {
2645 DRM_ERROR("Failed to load firmware!\n");
2646 return r;
2647 }
2648 }
fe251e2f 2649
bcc1c2a1 2650 evergreen_mc_program(rdev);
bcc1c2a1 2651 if (rdev->flags & RADEON_IS_AGP) {
0fcdb61e 2652 evergreen_agp_enable(rdev);
bcc1c2a1
AD		 2653 } else {
2654 r = evergreen_pcie_gart_enable(rdev);
2655 if (r)
2656 return r;
2657 }
bcc1c2a1 2658 evergreen_gpu_init(rdev);
bcc1c2a1 2659
d7ccd8fc 2660 r = evergreen_blit_init(rdev);
bcc1c2a1 2661 if (r) {
d7ccd8fc
AD		 2662 evergreen_blit_fini(rdev);
2663 rdev->asic->copy = NULL;
2664 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
bcc1c2a1
AD		 2665 }
2666
724c80e1
AD		 2667 /* allocate wb buffer */
2668 r = radeon_wb_init(rdev);
2669 if (r)
2670 return r;
2671
bcc1c2a1
AD		 2672 /* Enable IRQ */
2673 r = r600_irq_init(rdev);
2674 if (r) {
2675 DRM_ERROR("radeon: IH init failed (%d).\n", r);
2676 radeon_irq_kms_fini(rdev);
2677 return r;
2678 }
45f9a39b 2679 evergreen_irq_set(rdev);
bcc1c2a1
AD		 2680
2681 r = radeon_ring_init(rdev, rdev->cp.ring_size);
2682 if (r)
2683 return r;
2684 r = evergreen_cp_load_microcode(rdev);
2685 if (r)
2686 return r;
fe251e2f 2687 r = evergreen_cp_resume(rdev);
bcc1c2a1
AD		 2688 if (r)
2689 return r;
fe251e2f 2690
bcc1c2a1
AD		 2691 return 0;
2692}
2693
2694int evergreen_resume(struct radeon_device *rdev)
2695{
2696 int r;
2697
2698 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
2699 * posting will perform necessary task to bring back GPU into good
2700 * shape.
2701 */
2702 /* post card */
2703 atom_asic_init(rdev->mode_info.atom_context);
bcc1c2a1
AD		 2704
2705 r = evergreen_startup(rdev);
2706 if (r) {
2707 DRM_ERROR("r600 startup failed on resume\n");
2708 return r;
2709 }
fe251e2f 2710
bcc1c2a1
AD		 2711 r = r600_ib_test(rdev);
2712 if (r) {
2713 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
2714 return r;
2715 }
fe251e2f 2716
bcc1c2a1
AD		 2717 return r;
2718
2719}
2720
2721int evergreen_suspend(struct radeon_device *rdev)
2722{
bcc1c2a1 2723 int r;
d7ccd8fc 2724
bcc1c2a1
AD		 2725 /* FIXME: we should wait for ring to be empty */
2726 r700_cp_stop(rdev);
2727 rdev->cp.ready = false;
45f9a39b 2728 evergreen_irq_suspend(rdev);
724c80e1 2729 radeon_wb_disable(rdev);
bcc1c2a1 2730 evergreen_pcie_gart_disable(rdev);
d7ccd8fc 2731
bcc1c2a1
AD		 2732 /* unpin shaders bo */
2733 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
2734 if (likely(r == 0)) {
2735 radeon_bo_unpin(rdev->r600_blit.shader_obj);
2736 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
2737 }
d7ccd8fc
AD		 2738
2739 return 0;
2740}
2741
2742int evergreen_copy_blit(struct radeon_device *rdev,
2743 uint64_t src_offset, uint64_t dst_offset,
2744 unsigned num_pages, struct radeon_fence *fence)
2745{
2746 int r;
2747
2748 mutex_lock(&rdev->r600_blit.mutex);
2749 rdev->r600_blit.vb_ib = NULL;
2750 r = evergreen_blit_prepare_copy(rdev, num_pages * RADEON_GPU_PAGE_SIZE);
2751 if (r) {
2752 if (rdev->r600_blit.vb_ib)
2753 radeon_ib_free(rdev, &rdev->r600_blit.vb_ib);
2754 mutex_unlock(&rdev->r600_blit.mutex);
2755 return r;
2756 }
2757 evergreen_kms_blit_copy(rdev, src_offset, dst_offset, num_pages * RADEON_GPU_PAGE_SIZE);
2758 evergreen_blit_done_copy(rdev, fence);
2759 mutex_unlock(&rdev->r600_blit.mutex);
bcc1c2a1
AD		 2760 return 0;
2761}
2762
2763static bool evergreen_card_posted(struct radeon_device *rdev)
2764{
2765 u32 reg;
2766
2767 /* first check CRTCs */
2768 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
2769 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) |
2770 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |
2771 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) |
2772 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) |
2773 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
2774 if (reg & EVERGREEN_CRTC_MASTER_EN)
2775 return true;
2776
2777 /* then check MEM_SIZE, in case the crtcs are off */
2778 if (RREG32(CONFIG_MEMSIZE))
2779 return true;
2780
2781 return false;
2782}
2783
2784/* Plan is to move initialization in that function and use
2785 * helper function so that radeon_device_init pretty much
2786 * do nothing more than calling asic specific function. This
2787 * should also allow to remove a bunch of callback function
2788 * like vram_info.
2789 */
2790int evergreen_init(struct radeon_device *rdev)
2791{
2792 int r;
2793
2794 r = radeon_dummy_page_init(rdev);
2795 if (r)
2796 return r;
2797 /* This don't do much */
2798 r = radeon_gem_init(rdev);
2799 if (r)
2800 return r;
2801 /* Read BIOS */
2802 if (!radeon_get_bios(rdev)) {
2803 if (ASIC_IS_AVIVO(rdev))
2804 return -EINVAL;
2805 }
2806 /* Must be an ATOMBIOS */
2807 if (!rdev->is_atom_bios) {
2808 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
2809 return -EINVAL;
2810 }
2811 r = radeon_atombios_init(rdev);
2812 if (r)
2813 return r;
2814 /* Post card if necessary */
2815 if (!evergreen_card_posted(rdev)) {
2816 if (!rdev->bios) {
2817 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
2818 return -EINVAL;
2819 }
2820 DRM_INFO("GPU not posted. posting now...\n");
2821 atom_asic_init(rdev->mode_info.atom_context);
2822 }
2823 /* Initialize scratch registers */
2824 r600_scratch_init(rdev);
2825 /* Initialize surface registers */
2826 radeon_surface_init(rdev);
2827 /* Initialize clocks */
2828 radeon_get_clock_info(rdev->ddev);
bcc1c2a1
AD		 2829 /* Fence driver */
2830 r = radeon_fence_driver_init(rdev);
2831 if (r)
2832 return r;
d594e46a
JG		 2833 /* initialize AGP */
2834 if (rdev->flags & RADEON_IS_AGP) {
2835 r = radeon_agp_init(rdev);
2836 if (r)
2837 radeon_agp_disable(rdev);
2838 }
2839 /* initialize memory controller */
bcc1c2a1
AD		 2840 r = evergreen_mc_init(rdev);
2841 if (r)
2842 return r;
2843 /* Memory manager */
2844 r = radeon_bo_init(rdev);
2845 if (r)
2846 return r;
45f9a39b 2847
bcc1c2a1
AD		 2848 r = radeon_irq_kms_init(rdev);
2849 if (r)
2850 return r;
2851
2852 rdev->cp.ring_obj = NULL;
2853 r600_ring_init(rdev, 1024 * 1024);
2854
2855 rdev->ih.ring_obj = NULL;
2856 r600_ih_ring_init(rdev, 64 * 1024);
2857
2858 r = r600_pcie_gart_init(rdev);
2859 if (r)
2860 return r;
0fcdb61e 2861
148a03bc 2862 rdev->accel_working = true;
bcc1c2a1
AD		 2863 r = evergreen_startup(rdev);
2864 if (r) {
fe251e2f
AD		 2865 dev_err(rdev->dev, "disabling GPU acceleration\n");
2866 r700_cp_fini(rdev);
fe251e2f 2867 r600_irq_fini(rdev);
724c80e1 2868 radeon_wb_fini(rdev);
fe251e2f 2869 radeon_irq_kms_fini(rdev);
0fcdb61e 2870 evergreen_pcie_gart_fini(rdev);
bcc1c2a1
AD		 2871 rdev->accel_working = false;
2872 }
2873 if (rdev->accel_working) {
2874 r = radeon_ib_pool_init(rdev);
2875 if (r) {
2876 DRM_ERROR("radeon: failed initializing IB pool (%d).\n", r);
2877 rdev->accel_working = false;
2878 }
2879 r = r600_ib_test(rdev);
2880 if (r) {
2881 DRM_ERROR("radeon: failed testing IB (%d).\n", r);
2882 rdev->accel_working = false;
2883 }
2884 }
2885 return 0;
2886}
2887
2888void evergreen_fini(struct radeon_device *rdev)
2889{
d7ccd8fc 2890 evergreen_blit_fini(rdev);
45f9a39b 2891 r700_cp_fini(rdev);
bcc1c2a1 2892 r600_irq_fini(rdev);
724c80e1 2893 radeon_wb_fini(rdev);
bcc1c2a1 2894 radeon_irq_kms_fini(rdev);
bcc1c2a1 2895 evergreen_pcie_gart_fini(rdev);
bcc1c2a1
AD		 2896 radeon_gem_fini(rdev);
2897 radeon_fence_driver_fini(rdev);
bcc1c2a1
AD		 2898 radeon_agp_fini(rdev);
2899 radeon_bo_fini(rdev);
2900 radeon_atombios_fini(rdev);
2901 kfree(rdev->bios);
2902 rdev->bios = NULL;
2903 radeon_dummy_page_fini(rdev);
2904}
Linux kernel - Deliverables
This page took 0.22083 seconds and 5 git commands to generate.