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drm/radeon/kms: enable writeback (v2)
[deliverable/linux.git] / drivers / gpu / drm / radeon / evergreen.c
CommitLineData
bcc1c2a1
AD		 1/*
2 * Copyright 2010 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24#include <linux/firmware.h>
25#include <linux/platform_device.h>
5a0e3ad6 26#include <linux/slab.h>
bcc1c2a1
AD		 27#include "drmP.h"
28#include "radeon.h"
e6990375 29#include "radeon_asic.h"
bcc1c2a1 30#include "radeon_drm.h"
0fcdb61e 31#include "evergreend.h"
bcc1c2a1
AD		 32#include "atom.h"
33#include "avivod.h"
34#include "evergreen_reg.h"
35
fe251e2f
AD		 36#define EVERGREEN_PFP_UCODE_SIZE 1120
37#define EVERGREEN_PM4_UCODE_SIZE 1376
38
bcc1c2a1
AD		 39static void evergreen_gpu_init(struct radeon_device *rdev);
40void evergreen_fini(struct radeon_device *rdev);
41
21a8122a
AD		 42/* get temperature in millidegrees */
43u32 evergreen_get_temp(struct radeon_device *rdev)
44{
45 u32 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >>
46 ASIC_T_SHIFT;
47 u32 actual_temp = 0;
48
49 if ((temp >> 10) & 1)
50 actual_temp = 0;
51 else if ((temp >> 9) & 1)
52 actual_temp = 255;
53 else
54 actual_temp = (temp >> 1) & 0xff;
55
56 return actual_temp * 1000;
57}
58
49e02b73
AD		 59void evergreen_pm_misc(struct radeon_device *rdev)
60{
a081a9d6
RM		 61 int req_ps_idx = rdev->pm.requested_power_state_index;
62 int req_cm_idx = rdev->pm.requested_clock_mode_index;
63 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
64 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
49e02b73 65
4d60173f
AD		 66 if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
67 if (voltage->voltage != rdev->pm.current_vddc) {
68 radeon_atom_set_voltage(rdev, voltage->voltage);
69 rdev->pm.current_vddc = voltage->voltage;
0fcbe947 70 DRM_DEBUG("Setting: v: %d\n", voltage->voltage);
4d60173f
AD		 71 }
72 }
49e02b73
AD		 73}
74
75void evergreen_pm_prepare(struct radeon_device *rdev)
76{
77 struct drm_device *ddev = rdev->ddev;
78 struct drm_crtc *crtc;
79 struct radeon_crtc *radeon_crtc;
80 u32 tmp;
81
82 /* disable any active CRTCs */
83 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
84 radeon_crtc = to_radeon_crtc(crtc);
85 if (radeon_crtc->enabled) {
86 tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
87 tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
88 WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
89 }
90 }
91}
92
93void evergreen_pm_finish(struct radeon_device *rdev)
94{
95 struct drm_device *ddev = rdev->ddev;
96 struct drm_crtc *crtc;
97 struct radeon_crtc *radeon_crtc;
98 u32 tmp;
99
100 /* enable any active CRTCs */
101 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
102 radeon_crtc = to_radeon_crtc(crtc);
103 if (radeon_crtc->enabled) {
104 tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
105 tmp &= ~EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
106 WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
107 }
108 }
109}
110
bcc1c2a1
AD		 111bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
112{
113 bool connected = false;
0ca2ab52
AD		 114
115 switch (hpd) {
116 case RADEON_HPD_1:
117 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
118 connected = true;
119 break;
120 case RADEON_HPD_2:
121 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
122 connected = true;
123 break;
124 case RADEON_HPD_3:
125 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
126 connected = true;
127 break;
128 case RADEON_HPD_4:
129 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
130 connected = true;
131 break;
132 case RADEON_HPD_5:
133 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
134 connected = true;
135 break;
136 case RADEON_HPD_6:
137 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
138 connected = true;
139 break;
140 default:
141 break;
142 }
143
bcc1c2a1
AD		 144 return connected;
145}
146
147void evergreen_hpd_set_polarity(struct radeon_device *rdev,
148 enum radeon_hpd_id hpd)
149{
0ca2ab52
AD		 150 u32 tmp;
151 bool connected = evergreen_hpd_sense(rdev, hpd);
152
153 switch (hpd) {
154 case RADEON_HPD_1:
155 tmp = RREG32(DC_HPD1_INT_CONTROL);
156 if (connected)
157 tmp &= ~DC_HPDx_INT_POLARITY;
158 else
159 tmp |= DC_HPDx_INT_POLARITY;
160 WREG32(DC_HPD1_INT_CONTROL, tmp);
161 break;
162 case RADEON_HPD_2:
163 tmp = RREG32(DC_HPD2_INT_CONTROL);
164 if (connected)
165 tmp &= ~DC_HPDx_INT_POLARITY;
166 else
167 tmp |= DC_HPDx_INT_POLARITY;
168 WREG32(DC_HPD2_INT_CONTROL, tmp);
169 break;
170 case RADEON_HPD_3:
171 tmp = RREG32(DC_HPD3_INT_CONTROL);
172 if (connected)
173 tmp &= ~DC_HPDx_INT_POLARITY;
174 else
175 tmp |= DC_HPDx_INT_POLARITY;
176 WREG32(DC_HPD3_INT_CONTROL, tmp);
177 break;
178 case RADEON_HPD_4:
179 tmp = RREG32(DC_HPD4_INT_CONTROL);
180 if (connected)
181 tmp &= ~DC_HPDx_INT_POLARITY;
182 else
183 tmp |= DC_HPDx_INT_POLARITY;
184 WREG32(DC_HPD4_INT_CONTROL, tmp);
185 break;
186 case RADEON_HPD_5:
187 tmp = RREG32(DC_HPD5_INT_CONTROL);
188 if (connected)
189 tmp &= ~DC_HPDx_INT_POLARITY;
190 else
191 tmp |= DC_HPDx_INT_POLARITY;
192 WREG32(DC_HPD5_INT_CONTROL, tmp);
193 break;
194 case RADEON_HPD_6:
195 tmp = RREG32(DC_HPD6_INT_CONTROL);
196 if (connected)
197 tmp &= ~DC_HPDx_INT_POLARITY;
198 else
199 tmp |= DC_HPDx_INT_POLARITY;
200 WREG32(DC_HPD6_INT_CONTROL, tmp);
201 break;
202 default:
203 break;
204 }
bcc1c2a1
AD		 205}
206
207void evergreen_hpd_init(struct radeon_device *rdev)
208{
0ca2ab52
AD		 209 struct drm_device *dev = rdev->ddev;
210 struct drm_connector *connector;
211 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) |
212 DC_HPDx_RX_INT_TIMER(0xfa) | DC_HPDx_EN;
bcc1c2a1 213
0ca2ab52
AD		 214 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
215 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
216 switch (radeon_connector->hpd.hpd) {
217 case RADEON_HPD_1:
218 WREG32(DC_HPD1_CONTROL, tmp);
219 rdev->irq.hpd[0] = true;
220 break;
221 case RADEON_HPD_2:
222 WREG32(DC_HPD2_CONTROL, tmp);
223 rdev->irq.hpd[1] = true;
224 break;
225 case RADEON_HPD_3:
226 WREG32(DC_HPD3_CONTROL, tmp);
227 rdev->irq.hpd[2] = true;
228 break;
229 case RADEON_HPD_4:
230 WREG32(DC_HPD4_CONTROL, tmp);
231 rdev->irq.hpd[3] = true;
232 break;
233 case RADEON_HPD_5:
234 WREG32(DC_HPD5_CONTROL, tmp);
235 rdev->irq.hpd[4] = true;
236 break;
237 case RADEON_HPD_6:
238 WREG32(DC_HPD6_CONTROL, tmp);
239 rdev->irq.hpd[5] = true;
240 break;
241 default:
242 break;
243 }
244 }
245 if (rdev->irq.installed)
246 evergreen_irq_set(rdev);
bcc1c2a1
AD		 247}
248
0ca2ab52 249void evergreen_hpd_fini(struct radeon_device *rdev)
bcc1c2a1 250{
0ca2ab52
AD		 251 struct drm_device *dev = rdev->ddev;
252 struct drm_connector *connector;
253
254 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
255 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
256 switch (radeon_connector->hpd.hpd) {
257 case RADEON_HPD_1:
258 WREG32(DC_HPD1_CONTROL, 0);
259 rdev->irq.hpd[0] = false;
260 break;
261 case RADEON_HPD_2:
262 WREG32(DC_HPD2_CONTROL, 0);
263 rdev->irq.hpd[1] = false;
264 break;
265 case RADEON_HPD_3:
266 WREG32(DC_HPD3_CONTROL, 0);
267 rdev->irq.hpd[2] = false;
268 break;
269 case RADEON_HPD_4:
270 WREG32(DC_HPD4_CONTROL, 0);
271 rdev->irq.hpd[3] = false;
272 break;
273 case RADEON_HPD_5:
274 WREG32(DC_HPD5_CONTROL, 0);
275 rdev->irq.hpd[4] = false;
276 break;
277 case RADEON_HPD_6:
278 WREG32(DC_HPD6_CONTROL, 0);
279 rdev->irq.hpd[5] = false;
280 break;
281 default:
282 break;
283 }
284 }
bcc1c2a1
AD		 285}
286
0ca2ab52 287void evergreen_bandwidth_update(struct radeon_device *rdev)
bcc1c2a1
AD		 288{
289 /* XXX */
290}
291
292static int evergreen_mc_wait_for_idle(struct radeon_device *rdev)
293{
294 unsigned i;
295 u32 tmp;
296
297 for (i = 0; i < rdev->usec_timeout; i++) {
298 /* read MC_STATUS */
299 tmp = RREG32(SRBM_STATUS) & 0x1F00;
300 if (!tmp)
301 return 0;
302 udelay(1);
303 }
304 return -1;
305}
306
307/*
308 * GART
309 */
0fcdb61e
AD		 310void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev)
311{
312 unsigned i;
313 u32 tmp;
314
315 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
316 for (i = 0; i < rdev->usec_timeout; i++) {
317 /* read MC_STATUS */
318 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
319 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
320 if (tmp == 2) {
321 printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
322 return;
323 }
324 if (tmp) {
325 return;
326 }
327 udelay(1);
328 }
329}
330
bcc1c2a1
AD		 331int evergreen_pcie_gart_enable(struct radeon_device *rdev)
332{
333 u32 tmp;
0fcdb61e 334 int r;
bcc1c2a1
AD		 335
336 if (rdev->gart.table.vram.robj == NULL) {
337 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
338 return -EINVAL;
339 }
340 r = radeon_gart_table_vram_pin(rdev);
341 if (r)
342 return r;
82568565 343 radeon_gart_restore(rdev);
bcc1c2a1
AD		 344 /* Setup L2 cache */
345 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
346 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
347 EFFECTIVE_L2_QUEUE_SIZE(7));
348 WREG32(VM_L2_CNTL2, 0);
349 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
350 /* Setup TLB control */
351 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
352 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
353 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
354 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
355 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
356 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
357 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
358 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
359 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
360 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
361 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
362 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
363 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
364 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
365 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
366 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
367 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
368 (u32)(rdev->dummy_page.addr >> 12));
0fcdb61e 369 WREG32(VM_CONTEXT1_CNTL, 0);
bcc1c2a1 370
0fcdb61e 371 evergreen_pcie_gart_tlb_flush(rdev);
bcc1c2a1
AD		 372 rdev->gart.ready = true;
373 return 0;
374}
375
376void evergreen_pcie_gart_disable(struct radeon_device *rdev)
377{
378 u32 tmp;
0fcdb61e 379 int r;
bcc1c2a1
AD		 380
381 /* Disable all tables */
0fcdb61e
AD		 382 WREG32(VM_CONTEXT0_CNTL, 0);
383 WREG32(VM_CONTEXT1_CNTL, 0);
bcc1c2a1
AD		 384
385 /* Setup L2 cache */
386 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
387 EFFECTIVE_L2_QUEUE_SIZE(7));
388 WREG32(VM_L2_CNTL2, 0);
389 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
390 /* Setup TLB control */
391 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
392 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
393 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
394 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
395 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
396 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
397 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
398 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
399 if (rdev->gart.table.vram.robj) {
400 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
401 if (likely(r == 0)) {
402 radeon_bo_kunmap(rdev->gart.table.vram.robj);
403 radeon_bo_unpin(rdev->gart.table.vram.robj);
404 radeon_bo_unreserve(rdev->gart.table.vram.robj);
405 }
406 }
407}
408
409void evergreen_pcie_gart_fini(struct radeon_device *rdev)
410{
411 evergreen_pcie_gart_disable(rdev);
412 radeon_gart_table_vram_free(rdev);
413 radeon_gart_fini(rdev);
414}
415
416
417void evergreen_agp_enable(struct radeon_device *rdev)
418{
419 u32 tmp;
bcc1c2a1
AD		 420
421 /* Setup L2 cache */
422 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
423 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
424 EFFECTIVE_L2_QUEUE_SIZE(7));
425 WREG32(VM_L2_CNTL2, 0);
426 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
427 /* Setup TLB control */
428 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
429 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
430 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
431 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
432 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
433 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
434 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
435 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
436 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
437 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
438 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
0fcdb61e
AD		 439 WREG32(VM_CONTEXT0_CNTL, 0);
440 WREG32(VM_CONTEXT1_CNTL, 0);
bcc1c2a1
AD		 441}
442
443static void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save)
444{
445 save->vga_control[0] = RREG32(D1VGA_CONTROL);
446 save->vga_control[1] = RREG32(D2VGA_CONTROL);
447 save->vga_control[2] = RREG32(EVERGREEN_D3VGA_CONTROL);
448 save->vga_control[3] = RREG32(EVERGREEN_D4VGA_CONTROL);
449 save->vga_control[4] = RREG32(EVERGREEN_D5VGA_CONTROL);
450 save->vga_control[5] = RREG32(EVERGREEN_D6VGA_CONTROL);
451 save->vga_render_control = RREG32(VGA_RENDER_CONTROL);
452 save->vga_hdp_control = RREG32(VGA_HDP_CONTROL);
453 save->crtc_control[0] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET);
454 save->crtc_control[1] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
455 save->crtc_control[2] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET);
456 save->crtc_control[3] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
457 save->crtc_control[4] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET);
458 save->crtc_control[5] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
459
460 /* Stop all video */
461 WREG32(VGA_RENDER_CONTROL, 0);
462 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);
463 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);
464 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
465 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
466 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
467 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
468 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
469 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
470 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
471 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
472 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
473 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
474 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
475 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
476 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
477 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
478 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
479 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
480
481 WREG32(D1VGA_CONTROL, 0);
482 WREG32(D2VGA_CONTROL, 0);
483 WREG32(EVERGREEN_D3VGA_CONTROL, 0);
484 WREG32(EVERGREEN_D4VGA_CONTROL, 0);
485 WREG32(EVERGREEN_D5VGA_CONTROL, 0);
486 WREG32(EVERGREEN_D6VGA_CONTROL, 0);
487}
488
489static void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save)
490{
491 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET,
492 upper_32_bits(rdev->mc.vram_start));
493 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET,
494 upper_32_bits(rdev->mc.vram_start));
495 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC0_REGISTER_OFFSET,
496 (u32)rdev->mc.vram_start);
497 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC0_REGISTER_OFFSET,
498 (u32)rdev->mc.vram_start);
499
500 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET,
501 upper_32_bits(rdev->mc.vram_start));
502 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET,
503 upper_32_bits(rdev->mc.vram_start));
504 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET,
505 (u32)rdev->mc.vram_start);
506 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET,
507 (u32)rdev->mc.vram_start);
508
509 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
510 upper_32_bits(rdev->mc.vram_start));
511 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
512 upper_32_bits(rdev->mc.vram_start));
513 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET,
514 (u32)rdev->mc.vram_start);
515 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET,
516 (u32)rdev->mc.vram_start);
517
518 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET,
519 upper_32_bits(rdev->mc.vram_start));
520 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET,
521 upper_32_bits(rdev->mc.vram_start));
522 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET,
523 (u32)rdev->mc.vram_start);
524 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET,
525 (u32)rdev->mc.vram_start);
526
527 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
528 upper_32_bits(rdev->mc.vram_start));
529 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
530 upper_32_bits(rdev->mc.vram_start));
531 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET,
532 (u32)rdev->mc.vram_start);
533 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET,
534 (u32)rdev->mc.vram_start);
535
536 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET,
537 upper_32_bits(rdev->mc.vram_start));
538 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET,
539 upper_32_bits(rdev->mc.vram_start));
540 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET,
541 (u32)rdev->mc.vram_start);
542 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET,
543 (u32)rdev->mc.vram_start);
544
545 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start));
546 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);
547 /* Unlock host access */
548 WREG32(VGA_HDP_CONTROL, save->vga_hdp_control);
549 mdelay(1);
550 /* Restore video state */
551 WREG32(D1VGA_CONTROL, save->vga_control[0]);
552 WREG32(D2VGA_CONTROL, save->vga_control[1]);
553 WREG32(EVERGREEN_D3VGA_CONTROL, save->vga_control[2]);
554 WREG32(EVERGREEN_D4VGA_CONTROL, save->vga_control[3]);
555 WREG32(EVERGREEN_D5VGA_CONTROL, save->vga_control[4]);
556 WREG32(EVERGREEN_D6VGA_CONTROL, save->vga_control[5]);
557 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);
558 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);
559 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
560 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
561 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
562 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
563 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, save->crtc_control[0]);
564 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, save->crtc_control[1]);
565 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, save->crtc_control[2]);
566 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, save->crtc_control[3]);
567 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, save->crtc_control[4]);
568 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, save->crtc_control[5]);
569 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
570 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
571 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
572 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
573 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
574 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
575 WREG32(VGA_RENDER_CONTROL, save->vga_render_control);
576}
577
578static void evergreen_mc_program(struct radeon_device *rdev)
579{
580 struct evergreen_mc_save save;
581 u32 tmp;
582 int i, j;
583
584 /* Initialize HDP */
585 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
586 WREG32((0x2c14 + j), 0x00000000);
587 WREG32((0x2c18 + j), 0x00000000);
588 WREG32((0x2c1c + j), 0x00000000);
589 WREG32((0x2c20 + j), 0x00000000);
590 WREG32((0x2c24 + j), 0x00000000);
591 }
592 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
593
594 evergreen_mc_stop(rdev, &save);
595 if (evergreen_mc_wait_for_idle(rdev)) {
596 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
597 }
598 /* Lockout access through VGA aperture*/
599 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
600 /* Update configuration */
601 if (rdev->flags & RADEON_IS_AGP) {
602 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
603 /* VRAM before AGP */
604 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
605 rdev->mc.vram_start >> 12);
606 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
607 rdev->mc.gtt_end >> 12);
608 } else {
609 /* VRAM after AGP */
610 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
611 rdev->mc.gtt_start >> 12);
612 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
613 rdev->mc.vram_end >> 12);
614 }
615 } else {
616 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
617 rdev->mc.vram_start >> 12);
618 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
619 rdev->mc.vram_end >> 12);
620 }
621 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
622 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
623 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
624 WREG32(MC_VM_FB_LOCATION, tmp);
625 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
626 WREG32(HDP_NONSURFACE_INFO, (2 << 7));
46fcd2b3 627 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
bcc1c2a1
AD		 628 if (rdev->flags & RADEON_IS_AGP) {
629 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
630 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
631 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
632 } else {
633 WREG32(MC_VM_AGP_BASE, 0);
634 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
635 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
636 }
637 if (evergreen_mc_wait_for_idle(rdev)) {
638 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
639 }
640 evergreen_mc_resume(rdev, &save);
641 /* we need to own VRAM, so turn off the VGA renderer here
642 * to stop it overwriting our objects */
643 rv515_vga_render_disable(rdev);
644}
645
bcc1c2a1
AD		 646/*
647 * CP.
648 */
bcc1c2a1
AD		 649
650static int evergreen_cp_load_microcode(struct radeon_device *rdev)
651{
fe251e2f
AD		 652 const __be32 *fw_data;
653 int i;
654
655 if (!rdev->me_fw || !rdev->pfp_fw)
656 return -EINVAL;
bcc1c2a1 657
fe251e2f
AD		 658 r700_cp_stop(rdev);
659 WREG32(CP_RB_CNTL, RB_NO_UPDATE | (15 << 8) | (3 << 0));
660
661 fw_data = (const __be32 *)rdev->pfp_fw->data;
662 WREG32(CP_PFP_UCODE_ADDR, 0);
663 for (i = 0; i < EVERGREEN_PFP_UCODE_SIZE; i++)
664 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
665 WREG32(CP_PFP_UCODE_ADDR, 0);
666
667 fw_data = (const __be32 *)rdev->me_fw->data;
668 WREG32(CP_ME_RAM_WADDR, 0);
669 for (i = 0; i < EVERGREEN_PM4_UCODE_SIZE; i++)
670 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
671
672 WREG32(CP_PFP_UCODE_ADDR, 0);
673 WREG32(CP_ME_RAM_WADDR, 0);
674 WREG32(CP_ME_RAM_RADDR, 0);
bcc1c2a1
AD		 675 return 0;
676}
677
7e7b41d2
AD		 678static int evergreen_cp_start(struct radeon_device *rdev)
679{
680 int r;
681 uint32_t cp_me;
682
683 r = radeon_ring_lock(rdev, 7);
684 if (r) {
685 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
686 return r;
687 }
688 radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5));
689 radeon_ring_write(rdev, 0x1);
690 radeon_ring_write(rdev, 0x0);
691 radeon_ring_write(rdev, rdev->config.evergreen.max_hw_contexts - 1);
692 radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
693 radeon_ring_write(rdev, 0);
694 radeon_ring_write(rdev, 0);
695 radeon_ring_unlock_commit(rdev);
696
697 cp_me = 0xff;
698 WREG32(CP_ME_CNTL, cp_me);
699
700 r = radeon_ring_lock(rdev, 4);
701 if (r) {
702 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
703 return r;
704 }
705 /* init some VGT regs */
706 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
707 radeon_ring_write(rdev, (VGT_VERTEX_REUSE_BLOCK_CNTL - PACKET3_SET_CONTEXT_REG_START) >> 2);
708 radeon_ring_write(rdev, 0xe);
709 radeon_ring_write(rdev, 0x10);
710 radeon_ring_unlock_commit(rdev);
711
712 return 0;
713}
714
fe251e2f
AD		 715int evergreen_cp_resume(struct radeon_device *rdev)
716{
717 u32 tmp;
718 u32 rb_bufsz;
719 int r;
720
721 /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
722 WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
723 SOFT_RESET_PA |
724 SOFT_RESET_SH |
725 SOFT_RESET_VGT |
726 SOFT_RESET_SX));
727 RREG32(GRBM_SOFT_RESET);
728 mdelay(15);
729 WREG32(GRBM_SOFT_RESET, 0);
730 RREG32(GRBM_SOFT_RESET);
731
732 /* Set ring buffer size */
733 rb_bufsz = drm_order(rdev->cp.ring_size / 8);
724c80e1 734 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
fe251e2f
AD		 735#ifdef __BIG_ENDIAN
736 tmp |= BUF_SWAP_32BIT;
32fcdbf4 737#endif
fe251e2f
AD		 738 WREG32(CP_RB_CNTL, tmp);
739 WREG32(CP_SEM_WAIT_TIMER, 0x4);
740
741 /* Set the write pointer delay */
742 WREG32(CP_RB_WPTR_DELAY, 0);
743
744 /* Initialize the ring buffer's read and write pointers */
745 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
746 WREG32(CP_RB_RPTR_WR, 0);
747 WREG32(CP_RB_WPTR, 0);
724c80e1
AD		 748
749 /* set the wb address wether it's enabled or not */
750 WREG32(CP_RB_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC);
751 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
752 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
753
754 if (rdev->wb.enabled)
755 WREG32(SCRATCH_UMSK, 0xff);
756 else {
757 tmp |= RB_NO_UPDATE;
758 WREG32(SCRATCH_UMSK, 0);
759 }
760
fe251e2f
AD		 761 mdelay(1);
762 WREG32(CP_RB_CNTL, tmp);
763
764 WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8);
765 WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
766
767 rdev->cp.rptr = RREG32(CP_RB_RPTR);
768 rdev->cp.wptr = RREG32(CP_RB_WPTR);
769
7e7b41d2 770 evergreen_cp_start(rdev);
fe251e2f
AD		 771 rdev->cp.ready = true;
772 r = radeon_ring_test(rdev);
773 if (r) {
774 rdev->cp.ready = false;
775 return r;
776 }
777 return 0;
778}
bcc1c2a1
AD		 779
780/*
781 * Core functions
782 */
32fcdbf4
AD		 783static u32 evergreen_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
784 u32 num_tile_pipes,
bcc1c2a1
AD		 785 u32 num_backends,
786 u32 backend_disable_mask)
787{
788 u32 backend_map = 0;
32fcdbf4
AD		 789 u32 enabled_backends_mask = 0;
790 u32 enabled_backends_count = 0;
791 u32 cur_pipe;
792 u32 swizzle_pipe[EVERGREEN_MAX_PIPES];
793 u32 cur_backend = 0;
794 u32 i;
795 bool force_no_swizzle;
796
797 if (num_tile_pipes > EVERGREEN_MAX_PIPES)
798 num_tile_pipes = EVERGREEN_MAX_PIPES;
799 if (num_tile_pipes < 1)
800 num_tile_pipes = 1;
801 if (num_backends > EVERGREEN_MAX_BACKENDS)
802 num_backends = EVERGREEN_MAX_BACKENDS;
803 if (num_backends < 1)
804 num_backends = 1;
805
806 for (i = 0; i < EVERGREEN_MAX_BACKENDS; ++i) {
807 if (((backend_disable_mask >> i) & 1) == 0) {
808 enabled_backends_mask |= (1 << i);
809 ++enabled_backends_count;
810 }
811 if (enabled_backends_count == num_backends)
812 break;
813 }
814
815 if (enabled_backends_count == 0) {
816 enabled_backends_mask = 1;
817 enabled_backends_count = 1;
818 }
819
820 if (enabled_backends_count != num_backends)
821 num_backends = enabled_backends_count;
822
823 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * EVERGREEN_MAX_PIPES);
824 switch (rdev->family) {
825 case CHIP_CEDAR:
826 case CHIP_REDWOOD:
827 force_no_swizzle = false;
828 break;
829 case CHIP_CYPRESS:
830 case CHIP_HEMLOCK:
831 case CHIP_JUNIPER:
832 default:
833 force_no_swizzle = true;
834 break;
835 }
836 if (force_no_swizzle) {
837 bool last_backend_enabled = false;
838
839 force_no_swizzle = false;
840 for (i = 0; i < EVERGREEN_MAX_BACKENDS; ++i) {
841 if (((enabled_backends_mask >> i) & 1) == 1) {
842 if (last_backend_enabled)
843 force_no_swizzle = true;
844 last_backend_enabled = true;
845 } else
846 last_backend_enabled = false;
847 }
848 }
849
850 switch (num_tile_pipes) {
851 case 1:
852 case 3:
853 case 5:
854 case 7:
855 DRM_ERROR("odd number of pipes!\n");
856 break;
857 case 2:
858 swizzle_pipe[0] = 0;
859 swizzle_pipe[1] = 1;
860 break;
861 case 4:
862 if (force_no_swizzle) {
863 swizzle_pipe[0] = 0;
864 swizzle_pipe[1] = 1;
865 swizzle_pipe[2] = 2;
866 swizzle_pipe[3] = 3;
867 } else {
868 swizzle_pipe[0] = 0;
869 swizzle_pipe[1] = 2;
870 swizzle_pipe[2] = 1;
871 swizzle_pipe[3] = 3;
872 }
873 break;
874 case 6:
875 if (force_no_swizzle) {
876 swizzle_pipe[0] = 0;
877 swizzle_pipe[1] = 1;
878 swizzle_pipe[2] = 2;
879 swizzle_pipe[3] = 3;
880 swizzle_pipe[4] = 4;
881 swizzle_pipe[5] = 5;
882 } else {
883 swizzle_pipe[0] = 0;
884 swizzle_pipe[1] = 2;
885 swizzle_pipe[2] = 4;
886 swizzle_pipe[3] = 1;
887 swizzle_pipe[4] = 3;
888 swizzle_pipe[5] = 5;
889 }
890 break;
891 case 8:
892 if (force_no_swizzle) {
893 swizzle_pipe[0] = 0;
894 swizzle_pipe[1] = 1;
895 swizzle_pipe[2] = 2;
896 swizzle_pipe[3] = 3;
897 swizzle_pipe[4] = 4;
898 swizzle_pipe[5] = 5;
899 swizzle_pipe[6] = 6;
900 swizzle_pipe[7] = 7;
901 } else {
902 swizzle_pipe[0] = 0;
903 swizzle_pipe[1] = 2;
904 swizzle_pipe[2] = 4;
905 swizzle_pipe[3] = 6;
906 swizzle_pipe[4] = 1;
907 swizzle_pipe[5] = 3;
908 swizzle_pipe[6] = 5;
909 swizzle_pipe[7] = 7;
910 }
911 break;
912 }
913
914 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
915 while (((1 << cur_backend) & enabled_backends_mask) == 0)
916 cur_backend = (cur_backend + 1) % EVERGREEN_MAX_BACKENDS;
917
918 backend_map |= (((cur_backend & 0xf) << (swizzle_pipe[cur_pipe] * 4)));
919
920 cur_backend = (cur_backend + 1) % EVERGREEN_MAX_BACKENDS;
921 }
bcc1c2a1
AD		 922
923 return backend_map;
924}
bcc1c2a1
AD		 925
926static void evergreen_gpu_init(struct radeon_device *rdev)
927{
32fcdbf4
AD		 928 u32 cc_rb_backend_disable = 0;
929 u32 cc_gc_shader_pipe_config;
930 u32 gb_addr_config = 0;
931 u32 mc_shared_chmap, mc_arb_ramcfg;
932 u32 gb_backend_map;
933 u32 grbm_gfx_index;
934 u32 sx_debug_1;
935 u32 smx_dc_ctl0;
936 u32 sq_config;
937 u32 sq_lds_resource_mgmt;
938 u32 sq_gpr_resource_mgmt_1;
939 u32 sq_gpr_resource_mgmt_2;
940 u32 sq_gpr_resource_mgmt_3;
941 u32 sq_thread_resource_mgmt;
942 u32 sq_thread_resource_mgmt_2;
943 u32 sq_stack_resource_mgmt_1;
944 u32 sq_stack_resource_mgmt_2;
945 u32 sq_stack_resource_mgmt_3;
946 u32 vgt_cache_invalidation;
947 u32 hdp_host_path_cntl;
948 int i, j, num_shader_engines, ps_thread_count;
949
950 switch (rdev->family) {
951 case CHIP_CYPRESS:
952 case CHIP_HEMLOCK:
953 rdev->config.evergreen.num_ses = 2;
954 rdev->config.evergreen.max_pipes = 4;
955 rdev->config.evergreen.max_tile_pipes = 8;
956 rdev->config.evergreen.max_simds = 10;
957 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
958 rdev->config.evergreen.max_gprs = 256;
959 rdev->config.evergreen.max_threads = 248;
960 rdev->config.evergreen.max_gs_threads = 32;
961 rdev->config.evergreen.max_stack_entries = 512;
962 rdev->config.evergreen.sx_num_of_sets = 4;
963 rdev->config.evergreen.sx_max_export_size = 256;
964 rdev->config.evergreen.sx_max_export_pos_size = 64;
965 rdev->config.evergreen.sx_max_export_smx_size = 192;
966 rdev->config.evergreen.max_hw_contexts = 8;
967 rdev->config.evergreen.sq_num_cf_insts = 2;
968
969 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
970 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
971 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
972 break;
973 case CHIP_JUNIPER:
974 rdev->config.evergreen.num_ses = 1;
975 rdev->config.evergreen.max_pipes = 4;
976 rdev->config.evergreen.max_tile_pipes = 4;
977 rdev->config.evergreen.max_simds = 10;
978 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
979 rdev->config.evergreen.max_gprs = 256;
980 rdev->config.evergreen.max_threads = 248;
981 rdev->config.evergreen.max_gs_threads = 32;
982 rdev->config.evergreen.max_stack_entries = 512;
983 rdev->config.evergreen.sx_num_of_sets = 4;
984 rdev->config.evergreen.sx_max_export_size = 256;
985 rdev->config.evergreen.sx_max_export_pos_size = 64;
986 rdev->config.evergreen.sx_max_export_smx_size = 192;
987 rdev->config.evergreen.max_hw_contexts = 8;
988 rdev->config.evergreen.sq_num_cf_insts = 2;
989
990 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
991 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
992 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
993 break;
994 case CHIP_REDWOOD:
995 rdev->config.evergreen.num_ses = 1;
996 rdev->config.evergreen.max_pipes = 4;
997 rdev->config.evergreen.max_tile_pipes = 4;
998 rdev->config.evergreen.max_simds = 5;
999 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1000 rdev->config.evergreen.max_gprs = 256;
1001 rdev->config.evergreen.max_threads = 248;
1002 rdev->config.evergreen.max_gs_threads = 32;
1003 rdev->config.evergreen.max_stack_entries = 256;
1004 rdev->config.evergreen.sx_num_of_sets = 4;
1005 rdev->config.evergreen.sx_max_export_size = 256;
1006 rdev->config.evergreen.sx_max_export_pos_size = 64;
1007 rdev->config.evergreen.sx_max_export_smx_size = 192;
1008 rdev->config.evergreen.max_hw_contexts = 8;
1009 rdev->config.evergreen.sq_num_cf_insts = 2;
1010
1011 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1012 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1013 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1014 break;
1015 case CHIP_CEDAR:
1016 default:
1017 rdev->config.evergreen.num_ses = 1;
1018 rdev->config.evergreen.max_pipes = 2;
1019 rdev->config.evergreen.max_tile_pipes = 2;
1020 rdev->config.evergreen.max_simds = 2;
1021 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1022 rdev->config.evergreen.max_gprs = 256;
1023 rdev->config.evergreen.max_threads = 192;
1024 rdev->config.evergreen.max_gs_threads = 16;
1025 rdev->config.evergreen.max_stack_entries = 256;
1026 rdev->config.evergreen.sx_num_of_sets = 4;
1027 rdev->config.evergreen.sx_max_export_size = 128;
1028 rdev->config.evergreen.sx_max_export_pos_size = 32;
1029 rdev->config.evergreen.sx_max_export_smx_size = 96;
1030 rdev->config.evergreen.max_hw_contexts = 4;
1031 rdev->config.evergreen.sq_num_cf_insts = 1;
1032
1033 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1034 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1035 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1036 break;
1037 }
1038
1039 /* Initialize HDP */
1040 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1041 WREG32((0x2c14 + j), 0x00000000);
1042 WREG32((0x2c18 + j), 0x00000000);
1043 WREG32((0x2c1c + j), 0x00000000);
1044 WREG32((0x2c20 + j), 0x00000000);
1045 WREG32((0x2c24 + j), 0x00000000);
1046 }
1047
1048 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1049
1050 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & ~2;
1051
1052 cc_gc_shader_pipe_config |=
1053 INACTIVE_QD_PIPES((EVERGREEN_MAX_PIPES_MASK << rdev->config.evergreen.max_pipes)
1054 & EVERGREEN_MAX_PIPES_MASK);
1055 cc_gc_shader_pipe_config |=
1056 INACTIVE_SIMDS((EVERGREEN_MAX_SIMDS_MASK << rdev->config.evergreen.max_simds)
1057 & EVERGREEN_MAX_SIMDS_MASK);
1058
1059 cc_rb_backend_disable =
1060 BACKEND_DISABLE((EVERGREEN_MAX_BACKENDS_MASK << rdev->config.evergreen.max_backends)
1061 & EVERGREEN_MAX_BACKENDS_MASK);
1062
1063
1064 mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
1065 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
1066
1067 switch (rdev->config.evergreen.max_tile_pipes) {
1068 case 1:
1069 default:
1070 gb_addr_config |= NUM_PIPES(0);
1071 break;
1072 case 2:
1073 gb_addr_config |= NUM_PIPES(1);
1074 break;
1075 case 4:
1076 gb_addr_config |= NUM_PIPES(2);
1077 break;
1078 case 8:
1079 gb_addr_config |= NUM_PIPES(3);
1080 break;
1081 }
1082
1083 gb_addr_config |= PIPE_INTERLEAVE_SIZE((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
1084 gb_addr_config |= BANK_INTERLEAVE_SIZE(0);
1085 gb_addr_config |= NUM_SHADER_ENGINES(rdev->config.evergreen.num_ses - 1);
1086 gb_addr_config |= SHADER_ENGINE_TILE_SIZE(1);
1087 gb_addr_config |= NUM_GPUS(0); /* Hemlock? */
1088 gb_addr_config |= MULTI_GPU_TILE_SIZE(2);
1089
1090 if (((mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) > 2)
1091 gb_addr_config |= ROW_SIZE(2);
1092 else
1093 gb_addr_config |= ROW_SIZE((mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT);
1094
1095 if (rdev->ddev->pdev->device == 0x689e) {
1096 u32 efuse_straps_4;
1097 u32 efuse_straps_3;
1098 u8 efuse_box_bit_131_124;
1099
1100 WREG32(RCU_IND_INDEX, 0x204);
1101 efuse_straps_4 = RREG32(RCU_IND_DATA);
1102 WREG32(RCU_IND_INDEX, 0x203);
1103 efuse_straps_3 = RREG32(RCU_IND_DATA);
1104 efuse_box_bit_131_124 = (u8)(((efuse_straps_4 & 0xf) << 4) | ((efuse_straps_3 & 0xf0000000) >> 28));
1105
1106 switch(efuse_box_bit_131_124) {
1107 case 0x00:
1108 gb_backend_map = 0x76543210;
1109 break;
1110 case 0x55:
1111 gb_backend_map = 0x77553311;
1112 break;
1113 case 0x56:
1114 gb_backend_map = 0x77553300;
1115 break;
1116 case 0x59:
1117 gb_backend_map = 0x77552211;
1118 break;
1119 case 0x66:
1120 gb_backend_map = 0x77443300;
1121 break;
1122 case 0x99:
1123 gb_backend_map = 0x66552211;
1124 break;
1125 case 0x5a:
1126 gb_backend_map = 0x77552200;
1127 break;
1128 case 0xaa:
1129 gb_backend_map = 0x66442200;
1130 break;
1131 case 0x95:
1132 gb_backend_map = 0x66553311;
1133 break;
1134 default:
1135 DRM_ERROR("bad backend map, using default\n");
1136 gb_backend_map =
1137 evergreen_get_tile_pipe_to_backend_map(rdev,
1138 rdev->config.evergreen.max_tile_pipes,
1139 rdev->config.evergreen.max_backends,
1140 ((EVERGREEN_MAX_BACKENDS_MASK <<
1141 rdev->config.evergreen.max_backends) &
1142 EVERGREEN_MAX_BACKENDS_MASK));
1143 break;
1144 }
1145 } else if (rdev->ddev->pdev->device == 0x68b9) {
1146 u32 efuse_straps_3;
1147 u8 efuse_box_bit_127_124;
1148
1149 WREG32(RCU_IND_INDEX, 0x203);
1150 efuse_straps_3 = RREG32(RCU_IND_DATA);
1151 efuse_box_bit_127_124 = (u8)(efuse_straps_3 & 0xF0000000) >> 28;
1152
1153 switch(efuse_box_bit_127_124) {
1154 case 0x0:
1155 gb_backend_map = 0x00003210;
1156 break;
1157 case 0x5:
1158 case 0x6:
1159 case 0x9:
1160 case 0xa:
1161 gb_backend_map = 0x00003311;
1162 break;
1163 default:
1164 DRM_ERROR("bad backend map, using default\n");
1165 gb_backend_map =
1166 evergreen_get_tile_pipe_to_backend_map(rdev,
1167 rdev->config.evergreen.max_tile_pipes,
1168 rdev->config.evergreen.max_backends,
1169 ((EVERGREEN_MAX_BACKENDS_MASK <<
1170 rdev->config.evergreen.max_backends) &
1171 EVERGREEN_MAX_BACKENDS_MASK));
1172 break;
1173 }
b741be82
AD		 1174 } else {
1175 switch (rdev->family) {
1176 case CHIP_CYPRESS:
1177 case CHIP_HEMLOCK:
1178 gb_backend_map = 0x66442200;
1179 break;
1180 case CHIP_JUNIPER:
1181 gb_backend_map = 0x00006420;
1182 break;
1183 default:
1184 gb_backend_map =
1185 evergreen_get_tile_pipe_to_backend_map(rdev,
1186 rdev->config.evergreen.max_tile_pipes,
1187 rdev->config.evergreen.max_backends,
1188 ((EVERGREEN_MAX_BACKENDS_MASK <<
1189 rdev->config.evergreen.max_backends) &
1190 EVERGREEN_MAX_BACKENDS_MASK));
1191 }
1192 }
32fcdbf4 1193
e7aeeba6 1194 rdev->config.evergreen.tile_config = gb_addr_config;
32fcdbf4
AD		 1195 WREG32(GB_BACKEND_MAP, gb_backend_map);
1196 WREG32(GB_ADDR_CONFIG, gb_addr_config);
1197 WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
1198 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
1199
1200 num_shader_engines = ((RREG32(GB_ADDR_CONFIG) & NUM_SHADER_ENGINES(3)) >> 12) + 1;
1201 grbm_gfx_index = INSTANCE_BROADCAST_WRITES;
1202
1203 for (i = 0; i < rdev->config.evergreen.num_ses; i++) {
1204 u32 rb = cc_rb_backend_disable | (0xf0 << 16);
1205 u32 sp = cc_gc_shader_pipe_config;
1206 u32 gfx = grbm_gfx_index | SE_INDEX(i);
1207
1208 if (i == num_shader_engines) {
1209 rb |= BACKEND_DISABLE(EVERGREEN_MAX_BACKENDS_MASK);
1210 sp |= INACTIVE_SIMDS(EVERGREEN_MAX_SIMDS_MASK);
1211 }
1212
1213 WREG32(GRBM_GFX_INDEX, gfx);
1214 WREG32(RLC_GFX_INDEX, gfx);
1215
1216 WREG32(CC_RB_BACKEND_DISABLE, rb);
1217 WREG32(CC_SYS_RB_BACKEND_DISABLE, rb);
1218 WREG32(GC_USER_RB_BACKEND_DISABLE, rb);
1219 WREG32(CC_GC_SHADER_PIPE_CONFIG, sp);
1220 }
1221
1222 grbm_gfx_index |= SE_BROADCAST_WRITES;
1223 WREG32(GRBM_GFX_INDEX, grbm_gfx_index);
1224 WREG32(RLC_GFX_INDEX, grbm_gfx_index);
1225
1226 WREG32(CGTS_SYS_TCC_DISABLE, 0);
1227 WREG32(CGTS_TCC_DISABLE, 0);
1228 WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
1229 WREG32(CGTS_USER_TCC_DISABLE, 0);
1230
1231 /* set HW defaults for 3D engine */
1232 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
1233 ROQ_IB2_START(0x2b)));
1234
1235 WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
1236
1237 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO |
1238 SYNC_GRADIENT |
1239 SYNC_WALKER |
1240 SYNC_ALIGNER));
1241
1242 sx_debug_1 = RREG32(SX_DEBUG_1);
1243 sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
1244 WREG32(SX_DEBUG_1, sx_debug_1);
1245
1246
1247 smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
1248 smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff);
1249 smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.evergreen.sx_num_of_sets);
1250 WREG32(SMX_DC_CTL0, smx_dc_ctl0);
1251
1252 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_size / 4) - 1) |
1253 POSITION_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_pos_size / 4) - 1) |
1254 SMX_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_smx_size / 4) - 1)));
1255
1256 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.evergreen.sc_prim_fifo_size) |
1257 SC_HIZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_hiz_tile_fifo_size) |
1258 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_earlyz_tile_fifo_size)));
1259
1260 WREG32(VGT_NUM_INSTANCES, 1);
1261 WREG32(SPI_CONFIG_CNTL, 0);
1262 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
1263 WREG32(CP_PERFMON_CNTL, 0);
1264
1265 WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.evergreen.sq_num_cf_insts) |
1266 FETCH_FIFO_HIWATER(0x4) |
1267 DONE_FIFO_HIWATER(0xe0) |
1268 ALU_UPDATE_FIFO_HIWATER(0x8)));
1269
1270 sq_config = RREG32(SQ_CONFIG);
1271 sq_config &= ~(PS_PRIO(3) |
1272 VS_PRIO(3) |
1273 GS_PRIO(3) |
1274 ES_PRIO(3));
1275 sq_config |= (VC_ENABLE |
1276 EXPORT_SRC_C |
1277 PS_PRIO(0) |
1278 VS_PRIO(1) |
1279 GS_PRIO(2) |
1280 ES_PRIO(3));
1281
1282 if (rdev->family == CHIP_CEDAR)
1283 /* no vertex cache */
1284 sq_config &= ~VC_ENABLE;
1285
1286 sq_lds_resource_mgmt = RREG32(SQ_LDS_RESOURCE_MGMT);
1287
1288 sq_gpr_resource_mgmt_1 = NUM_PS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2))* 12 / 32);
1289 sq_gpr_resource_mgmt_1 |= NUM_VS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 6 / 32);
1290 sq_gpr_resource_mgmt_1 |= NUM_CLAUSE_TEMP_GPRS(4);
1291 sq_gpr_resource_mgmt_2 = NUM_GS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
1292 sq_gpr_resource_mgmt_2 |= NUM_ES_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
1293 sq_gpr_resource_mgmt_3 = NUM_HS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
1294 sq_gpr_resource_mgmt_3 |= NUM_LS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
1295
1296 if (rdev->family == CHIP_CEDAR)
1297 ps_thread_count = 96;
1298 else
1299 ps_thread_count = 128;
1300
1301 sq_thread_resource_mgmt = NUM_PS_THREADS(ps_thread_count);
f96b35cd
AD		 1302 sq_thread_resource_mgmt |= NUM_VS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
1303 sq_thread_resource_mgmt |= NUM_GS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
1304 sq_thread_resource_mgmt |= NUM_ES_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
1305 sq_thread_resource_mgmt_2 = NUM_HS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
1306 sq_thread_resource_mgmt_2 |= NUM_LS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
32fcdbf4
AD		 1307
1308 sq_stack_resource_mgmt_1 = NUM_PS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
1309 sq_stack_resource_mgmt_1 |= NUM_VS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
1310 sq_stack_resource_mgmt_2 = NUM_GS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
1311 sq_stack_resource_mgmt_2 |= NUM_ES_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
1312 sq_stack_resource_mgmt_3 = NUM_HS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
1313 sq_stack_resource_mgmt_3 |= NUM_LS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
1314
1315 WREG32(SQ_CONFIG, sq_config);
1316 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
1317 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
1318 WREG32(SQ_GPR_RESOURCE_MGMT_3, sq_gpr_resource_mgmt_3);
1319 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1320 WREG32(SQ_THREAD_RESOURCE_MGMT_2, sq_thread_resource_mgmt_2);
1321 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
1322 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
1323 WREG32(SQ_STACK_RESOURCE_MGMT_3, sq_stack_resource_mgmt_3);
1324 WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
1325 WREG32(SQ_LDS_RESOURCE_MGMT, sq_lds_resource_mgmt);
1326
1327 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
1328 FORCE_EOV_MAX_REZ_CNT(255)));
1329
1330 if (rdev->family == CHIP_CEDAR)
1331 vgt_cache_invalidation = CACHE_INVALIDATION(TC_ONLY);
1332 else
1333 vgt_cache_invalidation = CACHE_INVALIDATION(VC_AND_TC);
1334 vgt_cache_invalidation |= AUTO_INVLD_EN(ES_AND_GS_AUTO);
1335 WREG32(VGT_CACHE_INVALIDATION, vgt_cache_invalidation);
1336
1337 WREG32(VGT_GS_VERTEX_REUSE, 16);
1338 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1339
60a4a3e0
AD		 1340 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
1341 WREG32(VGT_OUT_DEALLOC_CNTL, 16);
1342
32fcdbf4
AD		 1343 WREG32(CB_PERF_CTR0_SEL_0, 0);
1344 WREG32(CB_PERF_CTR0_SEL_1, 0);
1345 WREG32(CB_PERF_CTR1_SEL_0, 0);
1346 WREG32(CB_PERF_CTR1_SEL_1, 0);
1347 WREG32(CB_PERF_CTR2_SEL_0, 0);
1348 WREG32(CB_PERF_CTR2_SEL_1, 0);
1349 WREG32(CB_PERF_CTR3_SEL_0, 0);
1350 WREG32(CB_PERF_CTR3_SEL_1, 0);
1351
60a4a3e0
AD		 1352 /* clear render buffer base addresses */
1353 WREG32(CB_COLOR0_BASE, 0);
1354 WREG32(CB_COLOR1_BASE, 0);
1355 WREG32(CB_COLOR2_BASE, 0);
1356 WREG32(CB_COLOR3_BASE, 0);
1357 WREG32(CB_COLOR4_BASE, 0);
1358 WREG32(CB_COLOR5_BASE, 0);
1359 WREG32(CB_COLOR6_BASE, 0);
1360 WREG32(CB_COLOR7_BASE, 0);
1361 WREG32(CB_COLOR8_BASE, 0);
1362 WREG32(CB_COLOR9_BASE, 0);
1363 WREG32(CB_COLOR10_BASE, 0);
1364 WREG32(CB_COLOR11_BASE, 0);
1365
1366 /* set the shader const cache sizes to 0 */
1367 for (i = SQ_ALU_CONST_BUFFER_SIZE_PS_0; i < 0x28200; i += 4)
1368 WREG32(i, 0);
1369 for (i = SQ_ALU_CONST_BUFFER_SIZE_HS_0; i < 0x29000; i += 4)
1370 WREG32(i, 0);
1371
32fcdbf4
AD		 1372 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
1373 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1374
1375 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
1376
1377 udelay(50);
1378
bcc1c2a1
AD		 1379}
1380
1381int evergreen_mc_init(struct radeon_device *rdev)
1382{
bcc1c2a1
AD		 1383 u32 tmp;
1384 int chansize, numchan;
bcc1c2a1
AD		 1385
1386 /* Get VRAM informations */
1387 rdev->mc.vram_is_ddr = true;
1388 tmp = RREG32(MC_ARB_RAMCFG);
1389 if (tmp & CHANSIZE_OVERRIDE) {
1390 chansize = 16;
1391 } else if (tmp & CHANSIZE_MASK) {
1392 chansize = 64;
1393 } else {
1394 chansize = 32;
1395 }
1396 tmp = RREG32(MC_SHARED_CHMAP);
1397 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1398 case 0:
1399 default:
1400 numchan = 1;
1401 break;
1402 case 1:
1403 numchan = 2;
1404 break;
1405 case 2:
1406 numchan = 4;
1407 break;
1408 case 3:
1409 numchan = 8;
1410 break;
1411 }
1412 rdev->mc.vram_width = numchan * chansize;
1413 /* Could aper size report 0 ? */
01d73a69
JC		 1414 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
1415 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
bcc1c2a1
AD		 1416 /* Setup GPU memory space */
1417 /* size in MB on evergreen */
1418 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
1419 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
51e5fcd3 1420 rdev->mc.visible_vram_size = rdev->mc.aper_size;
d594e46a 1421 r600_vram_gtt_location(rdev, &rdev->mc);
f47299c5
AD		 1422 radeon_update_bandwidth_info(rdev);
1423
bcc1c2a1
AD		 1424 return 0;
1425}
d594e46a 1426
225758d8
JG		 1427bool evergreen_gpu_is_lockup(struct radeon_device *rdev)
1428{
1429 /* FIXME: implement for evergreen */
1430 return false;
1431}
1432
747943ea 1433static int evergreen_gpu_soft_reset(struct radeon_device *rdev)
bcc1c2a1 1434{
747943ea
AD		 1435 struct evergreen_mc_save save;
1436 u32 srbm_reset = 0;
1437 u32 grbm_reset = 0;
1438
1439 dev_info(rdev->dev, "GPU softreset \n");
1440 dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
1441 RREG32(GRBM_STATUS));
1442 dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
1443 RREG32(GRBM_STATUS_SE0));
1444 dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
1445 RREG32(GRBM_STATUS_SE1));
1446 dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
1447 RREG32(SRBM_STATUS));
1448 evergreen_mc_stop(rdev, &save);
1449 if (evergreen_mc_wait_for_idle(rdev)) {
1450 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1451 }
1452 /* Disable CP parsing/prefetching */
1453 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
1454
1455 /* reset all the gfx blocks */
1456 grbm_reset = (SOFT_RESET_CP |
1457 SOFT_RESET_CB |
1458 SOFT_RESET_DB |
1459 SOFT_RESET_PA |
1460 SOFT_RESET_SC |
1461 SOFT_RESET_SPI |
1462 SOFT_RESET_SH |
1463 SOFT_RESET_SX |
1464 SOFT_RESET_TC |
1465 SOFT_RESET_TA |
1466 SOFT_RESET_VC |
1467 SOFT_RESET_VGT);
1468
1469 dev_info(rdev->dev, " GRBM_SOFT_RESET=0x%08X\n", grbm_reset);
1470 WREG32(GRBM_SOFT_RESET, grbm_reset);
1471 (void)RREG32(GRBM_SOFT_RESET);
1472 udelay(50);
1473 WREG32(GRBM_SOFT_RESET, 0);
1474 (void)RREG32(GRBM_SOFT_RESET);
1475
1476 /* reset all the system blocks */
1477 srbm_reset = SRBM_SOFT_RESET_ALL_MASK;
1478
1479 dev_info(rdev->dev, " SRBM_SOFT_RESET=0x%08X\n", srbm_reset);
1480 WREG32(SRBM_SOFT_RESET, srbm_reset);
1481 (void)RREG32(SRBM_SOFT_RESET);
1482 udelay(50);
1483 WREG32(SRBM_SOFT_RESET, 0);
1484 (void)RREG32(SRBM_SOFT_RESET);
1485 /* Wait a little for things to settle down */
1486 udelay(50);
1487 dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
1488 RREG32(GRBM_STATUS));
1489 dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
1490 RREG32(GRBM_STATUS_SE0));
1491 dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
1492 RREG32(GRBM_STATUS_SE1));
1493 dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
1494 RREG32(SRBM_STATUS));
1495 /* After reset we need to reinit the asic as GPU often endup in an
1496 * incoherent state.
1497 */
1498 atom_asic_init(rdev->mode_info.atom_context);
1499 evergreen_mc_resume(rdev, &save);
bcc1c2a1
AD		 1500 return 0;
1501}
1502
a2d07b74 1503int evergreen_asic_reset(struct radeon_device *rdev)
bcc1c2a1 1504{
747943ea
AD		 1505 return evergreen_gpu_soft_reset(rdev);
1506}
1507
45f9a39b
AD		 1508/* Interrupts */
1509
1510u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc)
1511{
1512 switch (crtc) {
1513 case 0:
1514 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC0_REGISTER_OFFSET);
1515 case 1:
1516 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC1_REGISTER_OFFSET);
1517 case 2:
1518 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC2_REGISTER_OFFSET);
1519 case 3:
1520 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC3_REGISTER_OFFSET);
1521 case 4:
1522 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC4_REGISTER_OFFSET);
1523 case 5:
1524 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC5_REGISTER_OFFSET);
1525 default:
1526 return 0;
1527 }
1528}
1529
1530void evergreen_disable_interrupt_state(struct radeon_device *rdev)
1531{
1532 u32 tmp;
1533
1534 WREG32(CP_INT_CNTL, 0);
1535 WREG32(GRBM_INT_CNTL, 0);
1536 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1537 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
1538 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1539 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
1540 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1541 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1542
1543 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1544 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
1545 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1546 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
1547 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1548 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1549
1550 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
1551 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
1552
1553 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
1554 WREG32(DC_HPD1_INT_CONTROL, tmp);
1555 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
1556 WREG32(DC_HPD2_INT_CONTROL, tmp);
1557 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
1558 WREG32(DC_HPD3_INT_CONTROL, tmp);
1559 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
1560 WREG32(DC_HPD4_INT_CONTROL, tmp);
1561 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
1562 WREG32(DC_HPD5_INT_CONTROL, tmp);
1563 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
1564 WREG32(DC_HPD6_INT_CONTROL, tmp);
1565
1566}
1567
1568int evergreen_irq_set(struct radeon_device *rdev)
1569{
1570 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
1571 u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0;
1572 u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6;
2031f77c 1573 u32 grbm_int_cntl = 0;
45f9a39b
AD		 1574
1575 if (!rdev->irq.installed) {
1576 WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n");
1577 return -EINVAL;
1578 }
1579 /* don't enable anything if the ih is disabled */
1580 if (!rdev->ih.enabled) {
1581 r600_disable_interrupts(rdev);
1582 /* force the active interrupt state to all disabled */
1583 evergreen_disable_interrupt_state(rdev);
1584 return 0;
1585 }
1586
1587 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
1588 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
1589 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
1590 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
1591 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
1592 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
1593
1594 if (rdev->irq.sw_int) {
1595 DRM_DEBUG("evergreen_irq_set: sw int\n");
1596 cp_int_cntl |= RB_INT_ENABLE;
1597 }
1598 if (rdev->irq.crtc_vblank_int[0]) {
1599 DRM_DEBUG("evergreen_irq_set: vblank 0\n");
1600 crtc1 |= VBLANK_INT_MASK;
1601 }
1602 if (rdev->irq.crtc_vblank_int[1]) {
1603 DRM_DEBUG("evergreen_irq_set: vblank 1\n");
1604 crtc2 |= VBLANK_INT_MASK;
1605 }
1606 if (rdev->irq.crtc_vblank_int[2]) {
1607 DRM_DEBUG("evergreen_irq_set: vblank 2\n");
1608 crtc3 |= VBLANK_INT_MASK;
1609 }
1610 if (rdev->irq.crtc_vblank_int[3]) {
1611 DRM_DEBUG("evergreen_irq_set: vblank 3\n");
1612 crtc4 |= VBLANK_INT_MASK;
1613 }
1614 if (rdev->irq.crtc_vblank_int[4]) {
1615 DRM_DEBUG("evergreen_irq_set: vblank 4\n");
1616 crtc5 |= VBLANK_INT_MASK;
1617 }
1618 if (rdev->irq.crtc_vblank_int[5]) {
1619 DRM_DEBUG("evergreen_irq_set: vblank 5\n");
1620 crtc6 |= VBLANK_INT_MASK;
1621 }
1622 if (rdev->irq.hpd[0]) {
1623 DRM_DEBUG("evergreen_irq_set: hpd 1\n");
1624 hpd1 |= DC_HPDx_INT_EN;
1625 }
1626 if (rdev->irq.hpd[1]) {
1627 DRM_DEBUG("evergreen_irq_set: hpd 2\n");
1628 hpd2 |= DC_HPDx_INT_EN;
1629 }
1630 if (rdev->irq.hpd[2]) {
1631 DRM_DEBUG("evergreen_irq_set: hpd 3\n");
1632 hpd3 |= DC_HPDx_INT_EN;
1633 }
1634 if (rdev->irq.hpd[3]) {
1635 DRM_DEBUG("evergreen_irq_set: hpd 4\n");
1636 hpd4 |= DC_HPDx_INT_EN;
1637 }
1638 if (rdev->irq.hpd[4]) {
1639 DRM_DEBUG("evergreen_irq_set: hpd 5\n");
1640 hpd5 |= DC_HPDx_INT_EN;
1641 }
1642 if (rdev->irq.hpd[5]) {
1643 DRM_DEBUG("evergreen_irq_set: hpd 6\n");
1644 hpd6 |= DC_HPDx_INT_EN;
1645 }
2031f77c
AD		 1646 if (rdev->irq.gui_idle) {
1647 DRM_DEBUG("gui idle\n");
1648 grbm_int_cntl |= GUI_IDLE_INT_ENABLE;
1649 }
45f9a39b
AD		 1650
1651 WREG32(CP_INT_CNTL, cp_int_cntl);
2031f77c 1652 WREG32(GRBM_INT_CNTL, grbm_int_cntl);
45f9a39b
AD		 1653
1654 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);
1655 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2);
1656 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3);
1657 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4);
1658 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5);
1659 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);
1660
1661 WREG32(DC_HPD1_INT_CONTROL, hpd1);
1662 WREG32(DC_HPD2_INT_CONTROL, hpd2);
1663 WREG32(DC_HPD3_INT_CONTROL, hpd3);
1664 WREG32(DC_HPD4_INT_CONTROL, hpd4);
1665 WREG32(DC_HPD5_INT_CONTROL, hpd5);
1666 WREG32(DC_HPD6_INT_CONTROL, hpd6);
1667
bcc1c2a1
AD		 1668 return 0;
1669}
1670
45f9a39b
AD		 1671static inline void evergreen_irq_ack(struct radeon_device *rdev,
1672 u32 *disp_int,
1673 u32 *disp_int_cont,
1674 u32 *disp_int_cont2,
1675 u32 *disp_int_cont3,
1676 u32 *disp_int_cont4,
1677 u32 *disp_int_cont5)
1678{
1679 u32 tmp;
1680
1681 *disp_int = RREG32(DISP_INTERRUPT_STATUS);
1682 *disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
1683 *disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2);
1684 *disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3);
1685 *disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4);
1686 *disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5);
1687
1688 if (*disp_int & LB_D1_VBLANK_INTERRUPT)
1689 WREG32(VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK);
1690 if (*disp_int & LB_D1_VLINE_INTERRUPT)
1691 WREG32(VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK);
1692
1693 if (*disp_int_cont & LB_D2_VBLANK_INTERRUPT)
1694 WREG32(VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK);
1695 if (*disp_int_cont & LB_D2_VLINE_INTERRUPT)
1696 WREG32(VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK);
1697
1698 if (*disp_int_cont2 & LB_D3_VBLANK_INTERRUPT)
1699 WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK);
1700 if (*disp_int_cont2 & LB_D3_VLINE_INTERRUPT)
1701 WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK);
1702
1703 if (*disp_int_cont3 & LB_D4_VBLANK_INTERRUPT)
1704 WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK);
1705 if (*disp_int_cont3 & LB_D4_VLINE_INTERRUPT)
1706 WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK);
1707
1708 if (*disp_int_cont4 & LB_D5_VBLANK_INTERRUPT)
1709 WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK);
1710 if (*disp_int_cont4 & LB_D5_VLINE_INTERRUPT)
1711 WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK);
1712
1713 if (*disp_int_cont5 & LB_D6_VBLANK_INTERRUPT)
1714 WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK);
1715 if (*disp_int_cont5 & LB_D6_VLINE_INTERRUPT)
1716 WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK);
1717
1718 if (*disp_int & DC_HPD1_INTERRUPT) {
1719 tmp = RREG32(DC_HPD1_INT_CONTROL);
1720 tmp |= DC_HPDx_INT_ACK;
1721 WREG32(DC_HPD1_INT_CONTROL, tmp);
1722 }
1723 if (*disp_int_cont & DC_HPD2_INTERRUPT) {
1724 tmp = RREG32(DC_HPD2_INT_CONTROL);
1725 tmp |= DC_HPDx_INT_ACK;
1726 WREG32(DC_HPD2_INT_CONTROL, tmp);
1727 }
1728 if (*disp_int_cont2 & DC_HPD3_INTERRUPT) {
1729 tmp = RREG32(DC_HPD3_INT_CONTROL);
1730 tmp |= DC_HPDx_INT_ACK;
1731 WREG32(DC_HPD3_INT_CONTROL, tmp);
1732 }
1733 if (*disp_int_cont3 & DC_HPD4_INTERRUPT) {
1734 tmp = RREG32(DC_HPD4_INT_CONTROL);
1735 tmp |= DC_HPDx_INT_ACK;
1736 WREG32(DC_HPD4_INT_CONTROL, tmp);
1737 }
1738 if (*disp_int_cont4 & DC_HPD5_INTERRUPT) {
1739 tmp = RREG32(DC_HPD5_INT_CONTROL);
1740 tmp |= DC_HPDx_INT_ACK;
1741 WREG32(DC_HPD5_INT_CONTROL, tmp);
1742 }
1743 if (*disp_int_cont5 & DC_HPD6_INTERRUPT) {
1744 tmp = RREG32(DC_HPD5_INT_CONTROL);
1745 tmp |= DC_HPDx_INT_ACK;
1746 WREG32(DC_HPD6_INT_CONTROL, tmp);
1747 }
1748}
1749
1750void evergreen_irq_disable(struct radeon_device *rdev)
1751{
1752 u32 disp_int, disp_int_cont, disp_int_cont2;
1753 u32 disp_int_cont3, disp_int_cont4, disp_int_cont5;
1754
1755 r600_disable_interrupts(rdev);
1756 /* Wait and acknowledge irq */
1757 mdelay(1);
1758 evergreen_irq_ack(rdev, &disp_int, &disp_int_cont, &disp_int_cont2,
1759 &disp_int_cont3, &disp_int_cont4, &disp_int_cont5);
1760 evergreen_disable_interrupt_state(rdev);
1761}
1762
1763static void evergreen_irq_suspend(struct radeon_device *rdev)
1764{
1765 evergreen_irq_disable(rdev);
1766 r600_rlc_stop(rdev);
1767}
1768
1769static inline u32 evergreen_get_ih_wptr(struct radeon_device *rdev)
1770{
1771 u32 wptr, tmp;
1772
724c80e1
AD		 1773 if (rdev->wb.enabled)
1774 wptr = rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4];
1775 else
1776 wptr = RREG32(IH_RB_WPTR);
45f9a39b
AD		 1777
1778 if (wptr & RB_OVERFLOW) {
1779 /* When a ring buffer overflow happen start parsing interrupt
1780 * from the last not overwritten vector (wptr + 16). Hopefully
1781 * this should allow us to catchup.
1782 */
1783 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
1784 wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
1785 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
1786 tmp = RREG32(IH_RB_CNTL);
1787 tmp |= IH_WPTR_OVERFLOW_CLEAR;
1788 WREG32(IH_RB_CNTL, tmp);
1789 }
1790 return (wptr & rdev->ih.ptr_mask);
1791}
1792
1793int evergreen_irq_process(struct radeon_device *rdev)
1794{
1795 u32 wptr = evergreen_get_ih_wptr(rdev);
1796 u32 rptr = rdev->ih.rptr;
1797 u32 src_id, src_data;
1798 u32 ring_index;
1799 u32 disp_int, disp_int_cont, disp_int_cont2;
1800 u32 disp_int_cont3, disp_int_cont4, disp_int_cont5;
1801 unsigned long flags;
1802 bool queue_hotplug = false;
1803
1804 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
1805 if (!rdev->ih.enabled)
1806 return IRQ_NONE;
1807
1808 spin_lock_irqsave(&rdev->ih.lock, flags);
1809
1810 if (rptr == wptr) {
1811 spin_unlock_irqrestore(&rdev->ih.lock, flags);
1812 return IRQ_NONE;
1813 }
1814 if (rdev->shutdown) {
1815 spin_unlock_irqrestore(&rdev->ih.lock, flags);
1816 return IRQ_NONE;
1817 }
1818
1819restart_ih:
1820 /* display interrupts */
1821 evergreen_irq_ack(rdev, &disp_int, &disp_int_cont, &disp_int_cont2,
1822 &disp_int_cont3, &disp_int_cont4, &disp_int_cont5);
1823
1824 rdev->ih.wptr = wptr;
1825 while (rptr != wptr) {
1826 /* wptr/rptr are in bytes! */
1827 ring_index = rptr / 4;
1828 src_id = rdev->ih.ring[ring_index] & 0xff;
1829 src_data = rdev->ih.ring[ring_index + 1] & 0xfffffff;
1830
1831 switch (src_id) {
1832 case 1: /* D1 vblank/vline */
1833 switch (src_data) {
1834 case 0: /* D1 vblank */
1835 if (disp_int & LB_D1_VBLANK_INTERRUPT) {
1836 drm_handle_vblank(rdev->ddev, 0);
1837 wake_up(&rdev->irq.vblank_queue);
1838 disp_int &= ~LB_D1_VBLANK_INTERRUPT;
1839 DRM_DEBUG("IH: D1 vblank\n");
1840 }
1841 break;
1842 case 1: /* D1 vline */
1843 if (disp_int & LB_D1_VLINE_INTERRUPT) {
1844 disp_int &= ~LB_D1_VLINE_INTERRUPT;
1845 DRM_DEBUG("IH: D1 vline\n");
1846 }
1847 break;
1848 default:
1849 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
1850 break;
1851 }
1852 break;
1853 case 2: /* D2 vblank/vline */
1854 switch (src_data) {
1855 case 0: /* D2 vblank */
1856 if (disp_int_cont & LB_D2_VBLANK_INTERRUPT) {
1857 drm_handle_vblank(rdev->ddev, 1);
1858 wake_up(&rdev->irq.vblank_queue);
1859 disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT;
1860 DRM_DEBUG("IH: D2 vblank\n");
1861 }
1862 break;
1863 case 1: /* D2 vline */
1864 if (disp_int_cont & LB_D2_VLINE_INTERRUPT) {
1865 disp_int_cont &= ~LB_D2_VLINE_INTERRUPT;
1866 DRM_DEBUG("IH: D2 vline\n");
1867 }
1868 break;
1869 default:
1870 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
1871 break;
1872 }
1873 break;
1874 case 3: /* D3 vblank/vline */
1875 switch (src_data) {
1876 case 0: /* D3 vblank */
1877 if (disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) {
1878 drm_handle_vblank(rdev->ddev, 2);
1879 wake_up(&rdev->irq.vblank_queue);
1880 disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT;
1881 DRM_DEBUG("IH: D3 vblank\n");
1882 }
1883 break;
1884 case 1: /* D3 vline */
1885 if (disp_int_cont2 & LB_D3_VLINE_INTERRUPT) {
1886 disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT;
1887 DRM_DEBUG("IH: D3 vline\n");
1888 }
1889 break;
1890 default:
1891 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
1892 break;
1893 }
1894 break;
1895 case 4: /* D4 vblank/vline */
1896 switch (src_data) {
1897 case 0: /* D4 vblank */
1898 if (disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) {
1899 drm_handle_vblank(rdev->ddev, 3);
1900 wake_up(&rdev->irq.vblank_queue);
1901 disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT;
1902 DRM_DEBUG("IH: D4 vblank\n");
1903 }
1904 break;
1905 case 1: /* D4 vline */
1906 if (disp_int_cont3 & LB_D4_VLINE_INTERRUPT) {
1907 disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT;
1908 DRM_DEBUG("IH: D4 vline\n");
1909 }
1910 break;
1911 default:
1912 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
1913 break;
1914 }
1915 break;
1916 case 5: /* D5 vblank/vline */
1917 switch (src_data) {
1918 case 0: /* D5 vblank */
1919 if (disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) {
1920 drm_handle_vblank(rdev->ddev, 4);
1921 wake_up(&rdev->irq.vblank_queue);
1922 disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT;
1923 DRM_DEBUG("IH: D5 vblank\n");
1924 }
1925 break;
1926 case 1: /* D5 vline */
1927 if (disp_int_cont4 & LB_D5_VLINE_INTERRUPT) {
1928 disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT;
1929 DRM_DEBUG("IH: D5 vline\n");
1930 }
1931 break;
1932 default:
1933 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
1934 break;
1935 }
1936 break;
1937 case 6: /* D6 vblank/vline */
1938 switch (src_data) {
1939 case 0: /* D6 vblank */
1940 if (disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) {
1941 drm_handle_vblank(rdev->ddev, 5);
1942 wake_up(&rdev->irq.vblank_queue);
1943 disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT;
1944 DRM_DEBUG("IH: D6 vblank\n");
1945 }
1946 break;
1947 case 1: /* D6 vline */
1948 if (disp_int_cont5 & LB_D6_VLINE_INTERRUPT) {
1949 disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT;
1950 DRM_DEBUG("IH: D6 vline\n");
1951 }
1952 break;
1953 default:
1954 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
1955 break;
1956 }
1957 break;
1958 case 42: /* HPD hotplug */
1959 switch (src_data) {
1960 case 0:
1961 if (disp_int & DC_HPD1_INTERRUPT) {
1962 disp_int &= ~DC_HPD1_INTERRUPT;
1963 queue_hotplug = true;
1964 DRM_DEBUG("IH: HPD1\n");
1965 }
1966 break;
1967 case 1:
1968 if (disp_int_cont & DC_HPD2_INTERRUPT) {
1969 disp_int_cont &= ~DC_HPD2_INTERRUPT;
1970 queue_hotplug = true;
1971 DRM_DEBUG("IH: HPD2\n");
1972 }
1973 break;
1974 case 2:
1975 if (disp_int_cont2 & DC_HPD3_INTERRUPT) {
1976 disp_int_cont2 &= ~DC_HPD3_INTERRUPT;
1977 queue_hotplug = true;
1978 DRM_DEBUG("IH: HPD3\n");
1979 }
1980 break;
1981 case 3:
1982 if (disp_int_cont3 & DC_HPD4_INTERRUPT) {
1983 disp_int_cont3 &= ~DC_HPD4_INTERRUPT;
1984 queue_hotplug = true;
1985 DRM_DEBUG("IH: HPD4\n");
1986 }
1987 break;
1988 case 4:
1989 if (disp_int_cont4 & DC_HPD5_INTERRUPT) {
1990 disp_int_cont4 &= ~DC_HPD5_INTERRUPT;
1991 queue_hotplug = true;
1992 DRM_DEBUG("IH: HPD5\n");
1993 }
1994 break;
1995 case 5:
1996 if (disp_int_cont5 & DC_HPD6_INTERRUPT) {
1997 disp_int_cont5 &= ~DC_HPD6_INTERRUPT;
1998 queue_hotplug = true;
1999 DRM_DEBUG("IH: HPD6\n");
2000 }
2001 break;
2002 default:
2003 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2004 break;
2005 }
2006 break;
2007 case 176: /* CP_INT in ring buffer */
2008 case 177: /* CP_INT in IB1 */
2009 case 178: /* CP_INT in IB2 */
2010 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
2011 radeon_fence_process(rdev);
2012 break;
2013 case 181: /* CP EOP event */
2014 DRM_DEBUG("IH: CP EOP\n");
2015 break;
2031f77c
AD		 2016 case 233: /* GUI IDLE */
2017 DRM_DEBUG("IH: CP EOP\n");
2018 rdev->pm.gui_idle = true;
2019 wake_up(&rdev->irq.idle_queue);
2020 break;
45f9a39b
AD		 2021 default:
2022 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2023 break;
2024 }
2025
2026 /* wptr/rptr are in bytes! */
2027 rptr += 16;
2028 rptr &= rdev->ih.ptr_mask;
2029 }
2030 /* make sure wptr hasn't changed while processing */
2031 wptr = evergreen_get_ih_wptr(rdev);
2032 if (wptr != rdev->ih.wptr)
2033 goto restart_ih;
2034 if (queue_hotplug)
2035 queue_work(rdev->wq, &rdev->hotplug_work);
2036 rdev->ih.rptr = rptr;
2037 WREG32(IH_RB_RPTR, rdev->ih.rptr);
2038 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2039 return IRQ_HANDLED;
2040}
2041
bcc1c2a1
AD		 2042static int evergreen_startup(struct radeon_device *rdev)
2043{
bcc1c2a1
AD		 2044 int r;
2045
2046 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
2047 r = r600_init_microcode(rdev);
2048 if (r) {
2049 DRM_ERROR("Failed to load firmware!\n");
2050 return r;
2051 }
2052 }
fe251e2f 2053
bcc1c2a1 2054 evergreen_mc_program(rdev);
bcc1c2a1 2055 if (rdev->flags & RADEON_IS_AGP) {
0fcdb61e 2056 evergreen_agp_enable(rdev);
bcc1c2a1
AD		 2057 } else {
2058 r = evergreen_pcie_gart_enable(rdev);
2059 if (r)
2060 return r;
2061 }
bcc1c2a1
AD		 2062 evergreen_gpu_init(rdev);
2063#if 0
2064 if (!rdev->r600_blit.shader_obj) {
2065 r = r600_blit_init(rdev);
2066 if (r) {
2067 DRM_ERROR("radeon: failed blitter (%d).\n", r);
2068 return r;
2069 }
2070 }
2071
2072 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
2073 if (unlikely(r != 0))
2074 return r;
2075 r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
2076 &rdev->r600_blit.shader_gpu_addr);
2077 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
2078 if (r) {
2079 DRM_ERROR("failed to pin blit object %d\n", r);
2080 return r;
2081 }
45f9a39b 2082#endif
bcc1c2a1 2083
724c80e1
AD		 2084 /* allocate wb buffer */
2085 r = radeon_wb_init(rdev);
2086 if (r)
2087 return r;
2088
bcc1c2a1
AD		 2089 /* Enable IRQ */
2090 r = r600_irq_init(rdev);
2091 if (r) {
2092 DRM_ERROR("radeon: IH init failed (%d).\n", r);
2093 radeon_irq_kms_fini(rdev);
2094 return r;
2095 }
45f9a39b 2096 evergreen_irq_set(rdev);
bcc1c2a1
AD		 2097
2098 r = radeon_ring_init(rdev, rdev->cp.ring_size);
2099 if (r)
2100 return r;
2101 r = evergreen_cp_load_microcode(rdev);
2102 if (r)
2103 return r;
fe251e2f 2104 r = evergreen_cp_resume(rdev);
bcc1c2a1
AD		 2105 if (r)
2106 return r;
fe251e2f 2107
bcc1c2a1
AD		 2108 return 0;
2109}
2110
2111int evergreen_resume(struct radeon_device *rdev)
2112{
2113 int r;
2114
2115 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
2116 * posting will perform necessary task to bring back GPU into good
2117 * shape.
2118 */
2119 /* post card */
2120 atom_asic_init(rdev->mode_info.atom_context);
bcc1c2a1
AD		 2121
2122 r = evergreen_startup(rdev);
2123 if (r) {
2124 DRM_ERROR("r600 startup failed on resume\n");
2125 return r;
2126 }
fe251e2f 2127
bcc1c2a1
AD		 2128 r = r600_ib_test(rdev);
2129 if (r) {
2130 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
2131 return r;
2132 }
fe251e2f 2133
bcc1c2a1
AD		 2134 return r;
2135
2136}
2137
2138int evergreen_suspend(struct radeon_device *rdev)
2139{
2140#if 0
2141 int r;
fe251e2f 2142#endif
bcc1c2a1
AD		 2143 /* FIXME: we should wait for ring to be empty */
2144 r700_cp_stop(rdev);
2145 rdev->cp.ready = false;
45f9a39b 2146 evergreen_irq_suspend(rdev);
724c80e1 2147 radeon_wb_disable(rdev);
bcc1c2a1 2148 evergreen_pcie_gart_disable(rdev);
0fcdb61e 2149#if 0
bcc1c2a1
AD		 2150 /* unpin shaders bo */
2151 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
2152 if (likely(r == 0)) {
2153 radeon_bo_unpin(rdev->r600_blit.shader_obj);
2154 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
2155 }
2156#endif
2157 return 0;
2158}
2159
2160static bool evergreen_card_posted(struct radeon_device *rdev)
2161{
2162 u32 reg;
2163
2164 /* first check CRTCs */
2165 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
2166 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) |
2167 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |
2168 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) |
2169 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) |
2170 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
2171 if (reg & EVERGREEN_CRTC_MASTER_EN)
2172 return true;
2173
2174 /* then check MEM_SIZE, in case the crtcs are off */
2175 if (RREG32(CONFIG_MEMSIZE))
2176 return true;
2177
2178 return false;
2179}
2180
2181/* Plan is to move initialization in that function and use
2182 * helper function so that radeon_device_init pretty much
2183 * do nothing more than calling asic specific function. This
2184 * should also allow to remove a bunch of callback function
2185 * like vram_info.
2186 */
2187int evergreen_init(struct radeon_device *rdev)
2188{
2189 int r;
2190
2191 r = radeon_dummy_page_init(rdev);
2192 if (r)
2193 return r;
2194 /* This don't do much */
2195 r = radeon_gem_init(rdev);
2196 if (r)
2197 return r;
2198 /* Read BIOS */
2199 if (!radeon_get_bios(rdev)) {
2200 if (ASIC_IS_AVIVO(rdev))
2201 return -EINVAL;
2202 }
2203 /* Must be an ATOMBIOS */
2204 if (!rdev->is_atom_bios) {
2205 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
2206 return -EINVAL;
2207 }
2208 r = radeon_atombios_init(rdev);
2209 if (r)
2210 return r;
2211 /* Post card if necessary */
2212 if (!evergreen_card_posted(rdev)) {
2213 if (!rdev->bios) {
2214 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
2215 return -EINVAL;
2216 }
2217 DRM_INFO("GPU not posted. posting now...\n");
2218 atom_asic_init(rdev->mode_info.atom_context);
2219 }
2220 /* Initialize scratch registers */
2221 r600_scratch_init(rdev);
2222 /* Initialize surface registers */
2223 radeon_surface_init(rdev);
2224 /* Initialize clocks */
2225 radeon_get_clock_info(rdev->ddev);
bcc1c2a1
AD		 2226 /* Fence driver */
2227 r = radeon_fence_driver_init(rdev);
2228 if (r)
2229 return r;
d594e46a
JG		 2230 /* initialize AGP */
2231 if (rdev->flags & RADEON_IS_AGP) {
2232 r = radeon_agp_init(rdev);
2233 if (r)
2234 radeon_agp_disable(rdev);
2235 }
2236 /* initialize memory controller */
bcc1c2a1
AD		 2237 r = evergreen_mc_init(rdev);
2238 if (r)
2239 return r;
2240 /* Memory manager */
2241 r = radeon_bo_init(rdev);
2242 if (r)
2243 return r;
45f9a39b 2244
bcc1c2a1
AD		 2245 r = radeon_irq_kms_init(rdev);
2246 if (r)
2247 return r;
2248
2249 rdev->cp.ring_obj = NULL;
2250 r600_ring_init(rdev, 1024 * 1024);
2251
2252 rdev->ih.ring_obj = NULL;
2253 r600_ih_ring_init(rdev, 64 * 1024);
2254
2255 r = r600_pcie_gart_init(rdev);
2256 if (r)
2257 return r;
0fcdb61e 2258
148a03bc 2259 rdev->accel_working = true;
bcc1c2a1
AD		 2260 r = evergreen_startup(rdev);
2261 if (r) {
fe251e2f
AD		 2262 dev_err(rdev->dev, "disabling GPU acceleration\n");
2263 r700_cp_fini(rdev);
fe251e2f 2264 r600_irq_fini(rdev);
724c80e1 2265 radeon_wb_fini(rdev);
fe251e2f 2266 radeon_irq_kms_fini(rdev);
0fcdb61e 2267 evergreen_pcie_gart_fini(rdev);
bcc1c2a1
AD		 2268 rdev->accel_working = false;
2269 }
2270 if (rdev->accel_working) {
2271 r = radeon_ib_pool_init(rdev);
2272 if (r) {
2273 DRM_ERROR("radeon: failed initializing IB pool (%d).\n", r);
2274 rdev->accel_working = false;
2275 }
2276 r = r600_ib_test(rdev);
2277 if (r) {
2278 DRM_ERROR("radeon: failed testing IB (%d).\n", r);
2279 rdev->accel_working = false;
2280 }
2281 }
2282 return 0;
2283}
2284
2285void evergreen_fini(struct radeon_device *rdev)
2286{
45f9a39b
AD		 2287 /*r600_blit_fini(rdev);*/
2288 r700_cp_fini(rdev);
bcc1c2a1 2289 r600_irq_fini(rdev);
724c80e1 2290 radeon_wb_fini(rdev);
bcc1c2a1 2291 radeon_irq_kms_fini(rdev);
bcc1c2a1 2292 evergreen_pcie_gart_fini(rdev);
bcc1c2a1
AD		 2293 radeon_gem_fini(rdev);
2294 radeon_fence_driver_fini(rdev);
bcc1c2a1
AD		 2295 radeon_agp_fini(rdev);
2296 radeon_bo_fini(rdev);
2297 radeon_atombios_fini(rdev);
2298 kfree(rdev->bios);
2299 rdev->bios = NULL;
2300 radeon_dummy_page_fini(rdev);
2301}
Linux kernel - Deliverables
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