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bcc1c2a1 AD |
1 | /* |
2 | * Copyright 2010 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Alex Deucher | |
23 | */ | |
24 | #include <linux/firmware.h> | |
25 | #include <linux/platform_device.h> | |
5a0e3ad6 | 26 | #include <linux/slab.h> |
bcc1c2a1 AD |
27 | #include "drmP.h" |
28 | #include "radeon.h" | |
e6990375 | 29 | #include "radeon_asic.h" |
bcc1c2a1 | 30 | #include "radeon_drm.h" |
0fcdb61e | 31 | #include "evergreend.h" |
bcc1c2a1 AD |
32 | #include "atom.h" |
33 | #include "avivod.h" | |
34 | #include "evergreen_reg.h" | |
35 | ||
fe251e2f AD |
36 | #define EVERGREEN_PFP_UCODE_SIZE 1120 |
37 | #define EVERGREEN_PM4_UCODE_SIZE 1376 | |
38 | ||
bcc1c2a1 AD |
39 | static void evergreen_gpu_init(struct radeon_device *rdev); |
40 | void evergreen_fini(struct radeon_device *rdev); | |
41 | ||
21a8122a AD |
42 | /* get temperature in millidegrees */ |
43 | u32 evergreen_get_temp(struct radeon_device *rdev) | |
44 | { | |
45 | u32 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >> | |
46 | ASIC_T_SHIFT; | |
47 | u32 actual_temp = 0; | |
48 | ||
49 | if ((temp >> 10) & 1) | |
50 | actual_temp = 0; | |
51 | else if ((temp >> 9) & 1) | |
52 | actual_temp = 255; | |
53 | else | |
54 | actual_temp = (temp >> 1) & 0xff; | |
55 | ||
56 | return actual_temp * 1000; | |
57 | } | |
58 | ||
49e02b73 AD |
59 | void evergreen_pm_misc(struct radeon_device *rdev) |
60 | { | |
a081a9d6 RM |
61 | int req_ps_idx = rdev->pm.requested_power_state_index; |
62 | int req_cm_idx = rdev->pm.requested_clock_mode_index; | |
63 | struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx]; | |
64 | struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage; | |
49e02b73 | 65 | |
4d60173f AD |
66 | if ((voltage->type == VOLTAGE_SW) && voltage->voltage) { |
67 | if (voltage->voltage != rdev->pm.current_vddc) { | |
68 | radeon_atom_set_voltage(rdev, voltage->voltage); | |
69 | rdev->pm.current_vddc = voltage->voltage; | |
0fcbe947 | 70 | DRM_DEBUG("Setting: v: %d\n", voltage->voltage); |
4d60173f AD |
71 | } |
72 | } | |
49e02b73 AD |
73 | } |
74 | ||
75 | void evergreen_pm_prepare(struct radeon_device *rdev) | |
76 | { | |
77 | struct drm_device *ddev = rdev->ddev; | |
78 | struct drm_crtc *crtc; | |
79 | struct radeon_crtc *radeon_crtc; | |
80 | u32 tmp; | |
81 | ||
82 | /* disable any active CRTCs */ | |
83 | list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) { | |
84 | radeon_crtc = to_radeon_crtc(crtc); | |
85 | if (radeon_crtc->enabled) { | |
86 | tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset); | |
87 | tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE; | |
88 | WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp); | |
89 | } | |
90 | } | |
91 | } | |
92 | ||
93 | void evergreen_pm_finish(struct radeon_device *rdev) | |
94 | { | |
95 | struct drm_device *ddev = rdev->ddev; | |
96 | struct drm_crtc *crtc; | |
97 | struct radeon_crtc *radeon_crtc; | |
98 | u32 tmp; | |
99 | ||
100 | /* enable any active CRTCs */ | |
101 | list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) { | |
102 | radeon_crtc = to_radeon_crtc(crtc); | |
103 | if (radeon_crtc->enabled) { | |
104 | tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset); | |
105 | tmp &= ~EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE; | |
106 | WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp); | |
107 | } | |
108 | } | |
109 | } | |
110 | ||
bcc1c2a1 AD |
111 | bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) |
112 | { | |
113 | bool connected = false; | |
0ca2ab52 AD |
114 | |
115 | switch (hpd) { | |
116 | case RADEON_HPD_1: | |
117 | if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE) | |
118 | connected = true; | |
119 | break; | |
120 | case RADEON_HPD_2: | |
121 | if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE) | |
122 | connected = true; | |
123 | break; | |
124 | case RADEON_HPD_3: | |
125 | if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE) | |
126 | connected = true; | |
127 | break; | |
128 | case RADEON_HPD_4: | |
129 | if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE) | |
130 | connected = true; | |
131 | break; | |
132 | case RADEON_HPD_5: | |
133 | if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE) | |
134 | connected = true; | |
135 | break; | |
136 | case RADEON_HPD_6: | |
137 | if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE) | |
138 | connected = true; | |
139 | break; | |
140 | default: | |
141 | break; | |
142 | } | |
143 | ||
bcc1c2a1 AD |
144 | return connected; |
145 | } | |
146 | ||
147 | void evergreen_hpd_set_polarity(struct radeon_device *rdev, | |
148 | enum radeon_hpd_id hpd) | |
149 | { | |
0ca2ab52 AD |
150 | u32 tmp; |
151 | bool connected = evergreen_hpd_sense(rdev, hpd); | |
152 | ||
153 | switch (hpd) { | |
154 | case RADEON_HPD_1: | |
155 | tmp = RREG32(DC_HPD1_INT_CONTROL); | |
156 | if (connected) | |
157 | tmp &= ~DC_HPDx_INT_POLARITY; | |
158 | else | |
159 | tmp |= DC_HPDx_INT_POLARITY; | |
160 | WREG32(DC_HPD1_INT_CONTROL, tmp); | |
161 | break; | |
162 | case RADEON_HPD_2: | |
163 | tmp = RREG32(DC_HPD2_INT_CONTROL); | |
164 | if (connected) | |
165 | tmp &= ~DC_HPDx_INT_POLARITY; | |
166 | else | |
167 | tmp |= DC_HPDx_INT_POLARITY; | |
168 | WREG32(DC_HPD2_INT_CONTROL, tmp); | |
169 | break; | |
170 | case RADEON_HPD_3: | |
171 | tmp = RREG32(DC_HPD3_INT_CONTROL); | |
172 | if (connected) | |
173 | tmp &= ~DC_HPDx_INT_POLARITY; | |
174 | else | |
175 | tmp |= DC_HPDx_INT_POLARITY; | |
176 | WREG32(DC_HPD3_INT_CONTROL, tmp); | |
177 | break; | |
178 | case RADEON_HPD_4: | |
179 | tmp = RREG32(DC_HPD4_INT_CONTROL); | |
180 | if (connected) | |
181 | tmp &= ~DC_HPDx_INT_POLARITY; | |
182 | else | |
183 | tmp |= DC_HPDx_INT_POLARITY; | |
184 | WREG32(DC_HPD4_INT_CONTROL, tmp); | |
185 | break; | |
186 | case RADEON_HPD_5: | |
187 | tmp = RREG32(DC_HPD5_INT_CONTROL); | |
188 | if (connected) | |
189 | tmp &= ~DC_HPDx_INT_POLARITY; | |
190 | else | |
191 | tmp |= DC_HPDx_INT_POLARITY; | |
192 | WREG32(DC_HPD5_INT_CONTROL, tmp); | |
193 | break; | |
194 | case RADEON_HPD_6: | |
195 | tmp = RREG32(DC_HPD6_INT_CONTROL); | |
196 | if (connected) | |
197 | tmp &= ~DC_HPDx_INT_POLARITY; | |
198 | else | |
199 | tmp |= DC_HPDx_INT_POLARITY; | |
200 | WREG32(DC_HPD6_INT_CONTROL, tmp); | |
201 | break; | |
202 | default: | |
203 | break; | |
204 | } | |
bcc1c2a1 AD |
205 | } |
206 | ||
207 | void evergreen_hpd_init(struct radeon_device *rdev) | |
208 | { | |
0ca2ab52 AD |
209 | struct drm_device *dev = rdev->ddev; |
210 | struct drm_connector *connector; | |
211 | u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | | |
212 | DC_HPDx_RX_INT_TIMER(0xfa) | DC_HPDx_EN; | |
bcc1c2a1 | 213 | |
0ca2ab52 AD |
214 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
215 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
216 | switch (radeon_connector->hpd.hpd) { | |
217 | case RADEON_HPD_1: | |
218 | WREG32(DC_HPD1_CONTROL, tmp); | |
219 | rdev->irq.hpd[0] = true; | |
220 | break; | |
221 | case RADEON_HPD_2: | |
222 | WREG32(DC_HPD2_CONTROL, tmp); | |
223 | rdev->irq.hpd[1] = true; | |
224 | break; | |
225 | case RADEON_HPD_3: | |
226 | WREG32(DC_HPD3_CONTROL, tmp); | |
227 | rdev->irq.hpd[2] = true; | |
228 | break; | |
229 | case RADEON_HPD_4: | |
230 | WREG32(DC_HPD4_CONTROL, tmp); | |
231 | rdev->irq.hpd[3] = true; | |
232 | break; | |
233 | case RADEON_HPD_5: | |
234 | WREG32(DC_HPD5_CONTROL, tmp); | |
235 | rdev->irq.hpd[4] = true; | |
236 | break; | |
237 | case RADEON_HPD_6: | |
238 | WREG32(DC_HPD6_CONTROL, tmp); | |
239 | rdev->irq.hpd[5] = true; | |
240 | break; | |
241 | default: | |
242 | break; | |
243 | } | |
244 | } | |
245 | if (rdev->irq.installed) | |
246 | evergreen_irq_set(rdev); | |
bcc1c2a1 AD |
247 | } |
248 | ||
0ca2ab52 | 249 | void evergreen_hpd_fini(struct radeon_device *rdev) |
bcc1c2a1 | 250 | { |
0ca2ab52 AD |
251 | struct drm_device *dev = rdev->ddev; |
252 | struct drm_connector *connector; | |
253 | ||
254 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
255 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
256 | switch (radeon_connector->hpd.hpd) { | |
257 | case RADEON_HPD_1: | |
258 | WREG32(DC_HPD1_CONTROL, 0); | |
259 | rdev->irq.hpd[0] = false; | |
260 | break; | |
261 | case RADEON_HPD_2: | |
262 | WREG32(DC_HPD2_CONTROL, 0); | |
263 | rdev->irq.hpd[1] = false; | |
264 | break; | |
265 | case RADEON_HPD_3: | |
266 | WREG32(DC_HPD3_CONTROL, 0); | |
267 | rdev->irq.hpd[2] = false; | |
268 | break; | |
269 | case RADEON_HPD_4: | |
270 | WREG32(DC_HPD4_CONTROL, 0); | |
271 | rdev->irq.hpd[3] = false; | |
272 | break; | |
273 | case RADEON_HPD_5: | |
274 | WREG32(DC_HPD5_CONTROL, 0); | |
275 | rdev->irq.hpd[4] = false; | |
276 | break; | |
277 | case RADEON_HPD_6: | |
278 | WREG32(DC_HPD6_CONTROL, 0); | |
279 | rdev->irq.hpd[5] = false; | |
280 | break; | |
281 | default: | |
282 | break; | |
283 | } | |
284 | } | |
bcc1c2a1 AD |
285 | } |
286 | ||
0ca2ab52 | 287 | void evergreen_bandwidth_update(struct radeon_device *rdev) |
bcc1c2a1 AD |
288 | { |
289 | /* XXX */ | |
290 | } | |
291 | ||
292 | static int evergreen_mc_wait_for_idle(struct radeon_device *rdev) | |
293 | { | |
294 | unsigned i; | |
295 | u32 tmp; | |
296 | ||
297 | for (i = 0; i < rdev->usec_timeout; i++) { | |
298 | /* read MC_STATUS */ | |
299 | tmp = RREG32(SRBM_STATUS) & 0x1F00; | |
300 | if (!tmp) | |
301 | return 0; | |
302 | udelay(1); | |
303 | } | |
304 | return -1; | |
305 | } | |
306 | ||
307 | /* | |
308 | * GART | |
309 | */ | |
0fcdb61e AD |
310 | void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev) |
311 | { | |
312 | unsigned i; | |
313 | u32 tmp; | |
314 | ||
315 | WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1)); | |
316 | for (i = 0; i < rdev->usec_timeout; i++) { | |
317 | /* read MC_STATUS */ | |
318 | tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE); | |
319 | tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT; | |
320 | if (tmp == 2) { | |
321 | printk(KERN_WARNING "[drm] r600 flush TLB failed\n"); | |
322 | return; | |
323 | } | |
324 | if (tmp) { | |
325 | return; | |
326 | } | |
327 | udelay(1); | |
328 | } | |
329 | } | |
330 | ||
bcc1c2a1 AD |
331 | int evergreen_pcie_gart_enable(struct radeon_device *rdev) |
332 | { | |
333 | u32 tmp; | |
0fcdb61e | 334 | int r; |
bcc1c2a1 AD |
335 | |
336 | if (rdev->gart.table.vram.robj == NULL) { | |
337 | dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); | |
338 | return -EINVAL; | |
339 | } | |
340 | r = radeon_gart_table_vram_pin(rdev); | |
341 | if (r) | |
342 | return r; | |
82568565 | 343 | radeon_gart_restore(rdev); |
bcc1c2a1 AD |
344 | /* Setup L2 cache */ |
345 | WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | | |
346 | ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | | |
347 | EFFECTIVE_L2_QUEUE_SIZE(7)); | |
348 | WREG32(VM_L2_CNTL2, 0); | |
349 | WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); | |
350 | /* Setup TLB control */ | |
351 | tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | | |
352 | SYSTEM_ACCESS_MODE_NOT_IN_SYS | | |
353 | SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU | | |
354 | EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5); | |
355 | WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); | |
356 | WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); | |
357 | WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); | |
358 | WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); | |
359 | WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); | |
360 | WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); | |
361 | WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); | |
362 | WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); | |
363 | WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); | |
364 | WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); | |
365 | WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | | |
366 | RANGE_PROTECTION_FAULT_ENABLE_DEFAULT); | |
367 | WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, | |
368 | (u32)(rdev->dummy_page.addr >> 12)); | |
0fcdb61e | 369 | WREG32(VM_CONTEXT1_CNTL, 0); |
bcc1c2a1 | 370 | |
0fcdb61e | 371 | evergreen_pcie_gart_tlb_flush(rdev); |
bcc1c2a1 AD |
372 | rdev->gart.ready = true; |
373 | return 0; | |
374 | } | |
375 | ||
376 | void evergreen_pcie_gart_disable(struct radeon_device *rdev) | |
377 | { | |
378 | u32 tmp; | |
0fcdb61e | 379 | int r; |
bcc1c2a1 AD |
380 | |
381 | /* Disable all tables */ | |
0fcdb61e AD |
382 | WREG32(VM_CONTEXT0_CNTL, 0); |
383 | WREG32(VM_CONTEXT1_CNTL, 0); | |
bcc1c2a1 AD |
384 | |
385 | /* Setup L2 cache */ | |
386 | WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING | | |
387 | EFFECTIVE_L2_QUEUE_SIZE(7)); | |
388 | WREG32(VM_L2_CNTL2, 0); | |
389 | WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); | |
390 | /* Setup TLB control */ | |
391 | tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5); | |
392 | WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); | |
393 | WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); | |
394 | WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); | |
395 | WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); | |
396 | WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); | |
397 | WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); | |
398 | WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); | |
399 | if (rdev->gart.table.vram.robj) { | |
400 | r = radeon_bo_reserve(rdev->gart.table.vram.robj, false); | |
401 | if (likely(r == 0)) { | |
402 | radeon_bo_kunmap(rdev->gart.table.vram.robj); | |
403 | radeon_bo_unpin(rdev->gart.table.vram.robj); | |
404 | radeon_bo_unreserve(rdev->gart.table.vram.robj); | |
405 | } | |
406 | } | |
407 | } | |
408 | ||
409 | void evergreen_pcie_gart_fini(struct radeon_device *rdev) | |
410 | { | |
411 | evergreen_pcie_gart_disable(rdev); | |
412 | radeon_gart_table_vram_free(rdev); | |
413 | radeon_gart_fini(rdev); | |
414 | } | |
415 | ||
416 | ||
417 | void evergreen_agp_enable(struct radeon_device *rdev) | |
418 | { | |
419 | u32 tmp; | |
bcc1c2a1 AD |
420 | |
421 | /* Setup L2 cache */ | |
422 | WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | | |
423 | ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | | |
424 | EFFECTIVE_L2_QUEUE_SIZE(7)); | |
425 | WREG32(VM_L2_CNTL2, 0); | |
426 | WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); | |
427 | /* Setup TLB control */ | |
428 | tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | | |
429 | SYSTEM_ACCESS_MODE_NOT_IN_SYS | | |
430 | SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU | | |
431 | EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5); | |
432 | WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); | |
433 | WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); | |
434 | WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); | |
435 | WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); | |
436 | WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); | |
437 | WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); | |
438 | WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); | |
0fcdb61e AD |
439 | WREG32(VM_CONTEXT0_CNTL, 0); |
440 | WREG32(VM_CONTEXT1_CNTL, 0); | |
bcc1c2a1 AD |
441 | } |
442 | ||
443 | static void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save) | |
444 | { | |
445 | save->vga_control[0] = RREG32(D1VGA_CONTROL); | |
446 | save->vga_control[1] = RREG32(D2VGA_CONTROL); | |
447 | save->vga_control[2] = RREG32(EVERGREEN_D3VGA_CONTROL); | |
448 | save->vga_control[3] = RREG32(EVERGREEN_D4VGA_CONTROL); | |
449 | save->vga_control[4] = RREG32(EVERGREEN_D5VGA_CONTROL); | |
450 | save->vga_control[5] = RREG32(EVERGREEN_D6VGA_CONTROL); | |
451 | save->vga_render_control = RREG32(VGA_RENDER_CONTROL); | |
452 | save->vga_hdp_control = RREG32(VGA_HDP_CONTROL); | |
453 | save->crtc_control[0] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET); | |
454 | save->crtc_control[1] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET); | |
455 | save->crtc_control[2] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET); | |
456 | save->crtc_control[3] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET); | |
457 | save->crtc_control[4] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET); | |
458 | save->crtc_control[5] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET); | |
459 | ||
460 | /* Stop all video */ | |
461 | WREG32(VGA_RENDER_CONTROL, 0); | |
462 | WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1); | |
463 | WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1); | |
464 | WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1); | |
465 | WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1); | |
466 | WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1); | |
467 | WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1); | |
468 | WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); | |
469 | WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); | |
470 | WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); | |
471 | WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); | |
472 | WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); | |
473 | WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); | |
474 | WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); | |
475 | WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); | |
476 | WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); | |
477 | WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); | |
478 | WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); | |
479 | WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); | |
480 | ||
481 | WREG32(D1VGA_CONTROL, 0); | |
482 | WREG32(D2VGA_CONTROL, 0); | |
483 | WREG32(EVERGREEN_D3VGA_CONTROL, 0); | |
484 | WREG32(EVERGREEN_D4VGA_CONTROL, 0); | |
485 | WREG32(EVERGREEN_D5VGA_CONTROL, 0); | |
486 | WREG32(EVERGREEN_D6VGA_CONTROL, 0); | |
487 | } | |
488 | ||
489 | static void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save) | |
490 | { | |
491 | WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET, | |
492 | upper_32_bits(rdev->mc.vram_start)); | |
493 | WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET, | |
494 | upper_32_bits(rdev->mc.vram_start)); | |
495 | WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC0_REGISTER_OFFSET, | |
496 | (u32)rdev->mc.vram_start); | |
497 | WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC0_REGISTER_OFFSET, | |
498 | (u32)rdev->mc.vram_start); | |
499 | ||
500 | WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET, | |
501 | upper_32_bits(rdev->mc.vram_start)); | |
502 | WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET, | |
503 | upper_32_bits(rdev->mc.vram_start)); | |
504 | WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET, | |
505 | (u32)rdev->mc.vram_start); | |
506 | WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET, | |
507 | (u32)rdev->mc.vram_start); | |
508 | ||
509 | WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET, | |
510 | upper_32_bits(rdev->mc.vram_start)); | |
511 | WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET, | |
512 | upper_32_bits(rdev->mc.vram_start)); | |
513 | WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET, | |
514 | (u32)rdev->mc.vram_start); | |
515 | WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET, | |
516 | (u32)rdev->mc.vram_start); | |
517 | ||
518 | WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET, | |
519 | upper_32_bits(rdev->mc.vram_start)); | |
520 | WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET, | |
521 | upper_32_bits(rdev->mc.vram_start)); | |
522 | WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET, | |
523 | (u32)rdev->mc.vram_start); | |
524 | WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET, | |
525 | (u32)rdev->mc.vram_start); | |
526 | ||
527 | WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET, | |
528 | upper_32_bits(rdev->mc.vram_start)); | |
529 | WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET, | |
530 | upper_32_bits(rdev->mc.vram_start)); | |
531 | WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET, | |
532 | (u32)rdev->mc.vram_start); | |
533 | WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET, | |
534 | (u32)rdev->mc.vram_start); | |
535 | ||
536 | WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET, | |
537 | upper_32_bits(rdev->mc.vram_start)); | |
538 | WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET, | |
539 | upper_32_bits(rdev->mc.vram_start)); | |
540 | WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET, | |
541 | (u32)rdev->mc.vram_start); | |
542 | WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET, | |
543 | (u32)rdev->mc.vram_start); | |
544 | ||
545 | WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start)); | |
546 | WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start); | |
547 | /* Unlock host access */ | |
548 | WREG32(VGA_HDP_CONTROL, save->vga_hdp_control); | |
549 | mdelay(1); | |
550 | /* Restore video state */ | |
551 | WREG32(D1VGA_CONTROL, save->vga_control[0]); | |
552 | WREG32(D2VGA_CONTROL, save->vga_control[1]); | |
553 | WREG32(EVERGREEN_D3VGA_CONTROL, save->vga_control[2]); | |
554 | WREG32(EVERGREEN_D4VGA_CONTROL, save->vga_control[3]); | |
555 | WREG32(EVERGREEN_D5VGA_CONTROL, save->vga_control[4]); | |
556 | WREG32(EVERGREEN_D6VGA_CONTROL, save->vga_control[5]); | |
557 | WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1); | |
558 | WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1); | |
559 | WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1); | |
560 | WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1); | |
561 | WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1); | |
562 | WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1); | |
563 | WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, save->crtc_control[0]); | |
564 | WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, save->crtc_control[1]); | |
565 | WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, save->crtc_control[2]); | |
566 | WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, save->crtc_control[3]); | |
567 | WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, save->crtc_control[4]); | |
568 | WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, save->crtc_control[5]); | |
569 | WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); | |
570 | WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); | |
571 | WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); | |
572 | WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); | |
573 | WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); | |
574 | WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); | |
575 | WREG32(VGA_RENDER_CONTROL, save->vga_render_control); | |
576 | } | |
577 | ||
578 | static void evergreen_mc_program(struct radeon_device *rdev) | |
579 | { | |
580 | struct evergreen_mc_save save; | |
581 | u32 tmp; | |
582 | int i, j; | |
583 | ||
584 | /* Initialize HDP */ | |
585 | for (i = 0, j = 0; i < 32; i++, j += 0x18) { | |
586 | WREG32((0x2c14 + j), 0x00000000); | |
587 | WREG32((0x2c18 + j), 0x00000000); | |
588 | WREG32((0x2c1c + j), 0x00000000); | |
589 | WREG32((0x2c20 + j), 0x00000000); | |
590 | WREG32((0x2c24 + j), 0x00000000); | |
591 | } | |
592 | WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0); | |
593 | ||
594 | evergreen_mc_stop(rdev, &save); | |
595 | if (evergreen_mc_wait_for_idle(rdev)) { | |
596 | dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); | |
597 | } | |
598 | /* Lockout access through VGA aperture*/ | |
599 | WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE); | |
600 | /* Update configuration */ | |
601 | if (rdev->flags & RADEON_IS_AGP) { | |
602 | if (rdev->mc.vram_start < rdev->mc.gtt_start) { | |
603 | /* VRAM before AGP */ | |
604 | WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, | |
605 | rdev->mc.vram_start >> 12); | |
606 | WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, | |
607 | rdev->mc.gtt_end >> 12); | |
608 | } else { | |
609 | /* VRAM after AGP */ | |
610 | WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, | |
611 | rdev->mc.gtt_start >> 12); | |
612 | WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, | |
613 | rdev->mc.vram_end >> 12); | |
614 | } | |
615 | } else { | |
616 | WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, | |
617 | rdev->mc.vram_start >> 12); | |
618 | WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, | |
619 | rdev->mc.vram_end >> 12); | |
620 | } | |
621 | WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0); | |
622 | tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16; | |
623 | tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF); | |
624 | WREG32(MC_VM_FB_LOCATION, tmp); | |
625 | WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); | |
626 | WREG32(HDP_NONSURFACE_INFO, (2 << 7)); | |
46fcd2b3 | 627 | WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF); |
bcc1c2a1 AD |
628 | if (rdev->flags & RADEON_IS_AGP) { |
629 | WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16); | |
630 | WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16); | |
631 | WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22); | |
632 | } else { | |
633 | WREG32(MC_VM_AGP_BASE, 0); | |
634 | WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF); | |
635 | WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF); | |
636 | } | |
637 | if (evergreen_mc_wait_for_idle(rdev)) { | |
638 | dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); | |
639 | } | |
640 | evergreen_mc_resume(rdev, &save); | |
641 | /* we need to own VRAM, so turn off the VGA renderer here | |
642 | * to stop it overwriting our objects */ | |
643 | rv515_vga_render_disable(rdev); | |
644 | } | |
645 | ||
bcc1c2a1 AD |
646 | /* |
647 | * CP. | |
648 | */ | |
bcc1c2a1 AD |
649 | |
650 | static int evergreen_cp_load_microcode(struct radeon_device *rdev) | |
651 | { | |
fe251e2f AD |
652 | const __be32 *fw_data; |
653 | int i; | |
654 | ||
655 | if (!rdev->me_fw || !rdev->pfp_fw) | |
656 | return -EINVAL; | |
bcc1c2a1 | 657 | |
fe251e2f AD |
658 | r700_cp_stop(rdev); |
659 | WREG32(CP_RB_CNTL, RB_NO_UPDATE | (15 << 8) | (3 << 0)); | |
660 | ||
661 | fw_data = (const __be32 *)rdev->pfp_fw->data; | |
662 | WREG32(CP_PFP_UCODE_ADDR, 0); | |
663 | for (i = 0; i < EVERGREEN_PFP_UCODE_SIZE; i++) | |
664 | WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++)); | |
665 | WREG32(CP_PFP_UCODE_ADDR, 0); | |
666 | ||
667 | fw_data = (const __be32 *)rdev->me_fw->data; | |
668 | WREG32(CP_ME_RAM_WADDR, 0); | |
669 | for (i = 0; i < EVERGREEN_PM4_UCODE_SIZE; i++) | |
670 | WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++)); | |
671 | ||
672 | WREG32(CP_PFP_UCODE_ADDR, 0); | |
673 | WREG32(CP_ME_RAM_WADDR, 0); | |
674 | WREG32(CP_ME_RAM_RADDR, 0); | |
bcc1c2a1 AD |
675 | return 0; |
676 | } | |
677 | ||
7e7b41d2 AD |
678 | static int evergreen_cp_start(struct radeon_device *rdev) |
679 | { | |
680 | int r; | |
681 | uint32_t cp_me; | |
682 | ||
683 | r = radeon_ring_lock(rdev, 7); | |
684 | if (r) { | |
685 | DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); | |
686 | return r; | |
687 | } | |
688 | radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5)); | |
689 | radeon_ring_write(rdev, 0x1); | |
690 | radeon_ring_write(rdev, 0x0); | |
691 | radeon_ring_write(rdev, rdev->config.evergreen.max_hw_contexts - 1); | |
692 | radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1)); | |
693 | radeon_ring_write(rdev, 0); | |
694 | radeon_ring_write(rdev, 0); | |
695 | radeon_ring_unlock_commit(rdev); | |
696 | ||
697 | cp_me = 0xff; | |
698 | WREG32(CP_ME_CNTL, cp_me); | |
699 | ||
700 | r = radeon_ring_lock(rdev, 4); | |
701 | if (r) { | |
702 | DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); | |
703 | return r; | |
704 | } | |
705 | /* init some VGT regs */ | |
706 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); | |
707 | radeon_ring_write(rdev, (VGT_VERTEX_REUSE_BLOCK_CNTL - PACKET3_SET_CONTEXT_REG_START) >> 2); | |
708 | radeon_ring_write(rdev, 0xe); | |
709 | radeon_ring_write(rdev, 0x10); | |
710 | radeon_ring_unlock_commit(rdev); | |
711 | ||
712 | return 0; | |
713 | } | |
714 | ||
fe251e2f AD |
715 | int evergreen_cp_resume(struct radeon_device *rdev) |
716 | { | |
717 | u32 tmp; | |
718 | u32 rb_bufsz; | |
719 | int r; | |
720 | ||
721 | /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */ | |
722 | WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP | | |
723 | SOFT_RESET_PA | | |
724 | SOFT_RESET_SH | | |
725 | SOFT_RESET_VGT | | |
726 | SOFT_RESET_SX)); | |
727 | RREG32(GRBM_SOFT_RESET); | |
728 | mdelay(15); | |
729 | WREG32(GRBM_SOFT_RESET, 0); | |
730 | RREG32(GRBM_SOFT_RESET); | |
731 | ||
732 | /* Set ring buffer size */ | |
733 | rb_bufsz = drm_order(rdev->cp.ring_size / 8); | |
734 | tmp = RB_NO_UPDATE | (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; | |
735 | #ifdef __BIG_ENDIAN | |
736 | tmp |= BUF_SWAP_32BIT; | |
32fcdbf4 | 737 | #endif |
fe251e2f AD |
738 | WREG32(CP_RB_CNTL, tmp); |
739 | WREG32(CP_SEM_WAIT_TIMER, 0x4); | |
740 | ||
741 | /* Set the write pointer delay */ | |
742 | WREG32(CP_RB_WPTR_DELAY, 0); | |
743 | ||
744 | /* Initialize the ring buffer's read and write pointers */ | |
745 | WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA); | |
746 | WREG32(CP_RB_RPTR_WR, 0); | |
747 | WREG32(CP_RB_WPTR, 0); | |
748 | WREG32(CP_RB_RPTR_ADDR, rdev->cp.gpu_addr & 0xFFFFFFFF); | |
749 | WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->cp.gpu_addr)); | |
750 | mdelay(1); | |
751 | WREG32(CP_RB_CNTL, tmp); | |
752 | ||
753 | WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8); | |
754 | WREG32(CP_DEBUG, (1 << 27) | (1 << 28)); | |
755 | ||
756 | rdev->cp.rptr = RREG32(CP_RB_RPTR); | |
757 | rdev->cp.wptr = RREG32(CP_RB_WPTR); | |
758 | ||
7e7b41d2 | 759 | evergreen_cp_start(rdev); |
fe251e2f AD |
760 | rdev->cp.ready = true; |
761 | r = radeon_ring_test(rdev); | |
762 | if (r) { | |
763 | rdev->cp.ready = false; | |
764 | return r; | |
765 | } | |
766 | return 0; | |
767 | } | |
bcc1c2a1 AD |
768 | |
769 | /* | |
770 | * Core functions | |
771 | */ | |
32fcdbf4 AD |
772 | static u32 evergreen_get_tile_pipe_to_backend_map(struct radeon_device *rdev, |
773 | u32 num_tile_pipes, | |
bcc1c2a1 AD |
774 | u32 num_backends, |
775 | u32 backend_disable_mask) | |
776 | { | |
777 | u32 backend_map = 0; | |
32fcdbf4 AD |
778 | u32 enabled_backends_mask = 0; |
779 | u32 enabled_backends_count = 0; | |
780 | u32 cur_pipe; | |
781 | u32 swizzle_pipe[EVERGREEN_MAX_PIPES]; | |
782 | u32 cur_backend = 0; | |
783 | u32 i; | |
784 | bool force_no_swizzle; | |
785 | ||
786 | if (num_tile_pipes > EVERGREEN_MAX_PIPES) | |
787 | num_tile_pipes = EVERGREEN_MAX_PIPES; | |
788 | if (num_tile_pipes < 1) | |
789 | num_tile_pipes = 1; | |
790 | if (num_backends > EVERGREEN_MAX_BACKENDS) | |
791 | num_backends = EVERGREEN_MAX_BACKENDS; | |
792 | if (num_backends < 1) | |
793 | num_backends = 1; | |
794 | ||
795 | for (i = 0; i < EVERGREEN_MAX_BACKENDS; ++i) { | |
796 | if (((backend_disable_mask >> i) & 1) == 0) { | |
797 | enabled_backends_mask |= (1 << i); | |
798 | ++enabled_backends_count; | |
799 | } | |
800 | if (enabled_backends_count == num_backends) | |
801 | break; | |
802 | } | |
803 | ||
804 | if (enabled_backends_count == 0) { | |
805 | enabled_backends_mask = 1; | |
806 | enabled_backends_count = 1; | |
807 | } | |
808 | ||
809 | if (enabled_backends_count != num_backends) | |
810 | num_backends = enabled_backends_count; | |
811 | ||
812 | memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * EVERGREEN_MAX_PIPES); | |
813 | switch (rdev->family) { | |
814 | case CHIP_CEDAR: | |
815 | case CHIP_REDWOOD: | |
816 | force_no_swizzle = false; | |
817 | break; | |
818 | case CHIP_CYPRESS: | |
819 | case CHIP_HEMLOCK: | |
820 | case CHIP_JUNIPER: | |
821 | default: | |
822 | force_no_swizzle = true; | |
823 | break; | |
824 | } | |
825 | if (force_no_swizzle) { | |
826 | bool last_backend_enabled = false; | |
827 | ||
828 | force_no_swizzle = false; | |
829 | for (i = 0; i < EVERGREEN_MAX_BACKENDS; ++i) { | |
830 | if (((enabled_backends_mask >> i) & 1) == 1) { | |
831 | if (last_backend_enabled) | |
832 | force_no_swizzle = true; | |
833 | last_backend_enabled = true; | |
834 | } else | |
835 | last_backend_enabled = false; | |
836 | } | |
837 | } | |
838 | ||
839 | switch (num_tile_pipes) { | |
840 | case 1: | |
841 | case 3: | |
842 | case 5: | |
843 | case 7: | |
844 | DRM_ERROR("odd number of pipes!\n"); | |
845 | break; | |
846 | case 2: | |
847 | swizzle_pipe[0] = 0; | |
848 | swizzle_pipe[1] = 1; | |
849 | break; | |
850 | case 4: | |
851 | if (force_no_swizzle) { | |
852 | swizzle_pipe[0] = 0; | |
853 | swizzle_pipe[1] = 1; | |
854 | swizzle_pipe[2] = 2; | |
855 | swizzle_pipe[3] = 3; | |
856 | } else { | |
857 | swizzle_pipe[0] = 0; | |
858 | swizzle_pipe[1] = 2; | |
859 | swizzle_pipe[2] = 1; | |
860 | swizzle_pipe[3] = 3; | |
861 | } | |
862 | break; | |
863 | case 6: | |
864 | if (force_no_swizzle) { | |
865 | swizzle_pipe[0] = 0; | |
866 | swizzle_pipe[1] = 1; | |
867 | swizzle_pipe[2] = 2; | |
868 | swizzle_pipe[3] = 3; | |
869 | swizzle_pipe[4] = 4; | |
870 | swizzle_pipe[5] = 5; | |
871 | } else { | |
872 | swizzle_pipe[0] = 0; | |
873 | swizzle_pipe[1] = 2; | |
874 | swizzle_pipe[2] = 4; | |
875 | swizzle_pipe[3] = 1; | |
876 | swizzle_pipe[4] = 3; | |
877 | swizzle_pipe[5] = 5; | |
878 | } | |
879 | break; | |
880 | case 8: | |
881 | if (force_no_swizzle) { | |
882 | swizzle_pipe[0] = 0; | |
883 | swizzle_pipe[1] = 1; | |
884 | swizzle_pipe[2] = 2; | |
885 | swizzle_pipe[3] = 3; | |
886 | swizzle_pipe[4] = 4; | |
887 | swizzle_pipe[5] = 5; | |
888 | swizzle_pipe[6] = 6; | |
889 | swizzle_pipe[7] = 7; | |
890 | } else { | |
891 | swizzle_pipe[0] = 0; | |
892 | swizzle_pipe[1] = 2; | |
893 | swizzle_pipe[2] = 4; | |
894 | swizzle_pipe[3] = 6; | |
895 | swizzle_pipe[4] = 1; | |
896 | swizzle_pipe[5] = 3; | |
897 | swizzle_pipe[6] = 5; | |
898 | swizzle_pipe[7] = 7; | |
899 | } | |
900 | break; | |
901 | } | |
902 | ||
903 | for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) { | |
904 | while (((1 << cur_backend) & enabled_backends_mask) == 0) | |
905 | cur_backend = (cur_backend + 1) % EVERGREEN_MAX_BACKENDS; | |
906 | ||
907 | backend_map |= (((cur_backend & 0xf) << (swizzle_pipe[cur_pipe] * 4))); | |
908 | ||
909 | cur_backend = (cur_backend + 1) % EVERGREEN_MAX_BACKENDS; | |
910 | } | |
bcc1c2a1 AD |
911 | |
912 | return backend_map; | |
913 | } | |
bcc1c2a1 AD |
914 | |
915 | static void evergreen_gpu_init(struct radeon_device *rdev) | |
916 | { | |
32fcdbf4 AD |
917 | u32 cc_rb_backend_disable = 0; |
918 | u32 cc_gc_shader_pipe_config; | |
919 | u32 gb_addr_config = 0; | |
920 | u32 mc_shared_chmap, mc_arb_ramcfg; | |
921 | u32 gb_backend_map; | |
922 | u32 grbm_gfx_index; | |
923 | u32 sx_debug_1; | |
924 | u32 smx_dc_ctl0; | |
925 | u32 sq_config; | |
926 | u32 sq_lds_resource_mgmt; | |
927 | u32 sq_gpr_resource_mgmt_1; | |
928 | u32 sq_gpr_resource_mgmt_2; | |
929 | u32 sq_gpr_resource_mgmt_3; | |
930 | u32 sq_thread_resource_mgmt; | |
931 | u32 sq_thread_resource_mgmt_2; | |
932 | u32 sq_stack_resource_mgmt_1; | |
933 | u32 sq_stack_resource_mgmt_2; | |
934 | u32 sq_stack_resource_mgmt_3; | |
935 | u32 vgt_cache_invalidation; | |
936 | u32 hdp_host_path_cntl; | |
937 | int i, j, num_shader_engines, ps_thread_count; | |
938 | ||
939 | switch (rdev->family) { | |
940 | case CHIP_CYPRESS: | |
941 | case CHIP_HEMLOCK: | |
942 | rdev->config.evergreen.num_ses = 2; | |
943 | rdev->config.evergreen.max_pipes = 4; | |
944 | rdev->config.evergreen.max_tile_pipes = 8; | |
945 | rdev->config.evergreen.max_simds = 10; | |
946 | rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses; | |
947 | rdev->config.evergreen.max_gprs = 256; | |
948 | rdev->config.evergreen.max_threads = 248; | |
949 | rdev->config.evergreen.max_gs_threads = 32; | |
950 | rdev->config.evergreen.max_stack_entries = 512; | |
951 | rdev->config.evergreen.sx_num_of_sets = 4; | |
952 | rdev->config.evergreen.sx_max_export_size = 256; | |
953 | rdev->config.evergreen.sx_max_export_pos_size = 64; | |
954 | rdev->config.evergreen.sx_max_export_smx_size = 192; | |
955 | rdev->config.evergreen.max_hw_contexts = 8; | |
956 | rdev->config.evergreen.sq_num_cf_insts = 2; | |
957 | ||
958 | rdev->config.evergreen.sc_prim_fifo_size = 0x100; | |
959 | rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; | |
960 | rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; | |
961 | break; | |
962 | case CHIP_JUNIPER: | |
963 | rdev->config.evergreen.num_ses = 1; | |
964 | rdev->config.evergreen.max_pipes = 4; | |
965 | rdev->config.evergreen.max_tile_pipes = 4; | |
966 | rdev->config.evergreen.max_simds = 10; | |
967 | rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses; | |
968 | rdev->config.evergreen.max_gprs = 256; | |
969 | rdev->config.evergreen.max_threads = 248; | |
970 | rdev->config.evergreen.max_gs_threads = 32; | |
971 | rdev->config.evergreen.max_stack_entries = 512; | |
972 | rdev->config.evergreen.sx_num_of_sets = 4; | |
973 | rdev->config.evergreen.sx_max_export_size = 256; | |
974 | rdev->config.evergreen.sx_max_export_pos_size = 64; | |
975 | rdev->config.evergreen.sx_max_export_smx_size = 192; | |
976 | rdev->config.evergreen.max_hw_contexts = 8; | |
977 | rdev->config.evergreen.sq_num_cf_insts = 2; | |
978 | ||
979 | rdev->config.evergreen.sc_prim_fifo_size = 0x100; | |
980 | rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; | |
981 | rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; | |
982 | break; | |
983 | case CHIP_REDWOOD: | |
984 | rdev->config.evergreen.num_ses = 1; | |
985 | rdev->config.evergreen.max_pipes = 4; | |
986 | rdev->config.evergreen.max_tile_pipes = 4; | |
987 | rdev->config.evergreen.max_simds = 5; | |
988 | rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses; | |
989 | rdev->config.evergreen.max_gprs = 256; | |
990 | rdev->config.evergreen.max_threads = 248; | |
991 | rdev->config.evergreen.max_gs_threads = 32; | |
992 | rdev->config.evergreen.max_stack_entries = 256; | |
993 | rdev->config.evergreen.sx_num_of_sets = 4; | |
994 | rdev->config.evergreen.sx_max_export_size = 256; | |
995 | rdev->config.evergreen.sx_max_export_pos_size = 64; | |
996 | rdev->config.evergreen.sx_max_export_smx_size = 192; | |
997 | rdev->config.evergreen.max_hw_contexts = 8; | |
998 | rdev->config.evergreen.sq_num_cf_insts = 2; | |
999 | ||
1000 | rdev->config.evergreen.sc_prim_fifo_size = 0x100; | |
1001 | rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; | |
1002 | rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; | |
1003 | break; | |
1004 | case CHIP_CEDAR: | |
1005 | default: | |
1006 | rdev->config.evergreen.num_ses = 1; | |
1007 | rdev->config.evergreen.max_pipes = 2; | |
1008 | rdev->config.evergreen.max_tile_pipes = 2; | |
1009 | rdev->config.evergreen.max_simds = 2; | |
1010 | rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses; | |
1011 | rdev->config.evergreen.max_gprs = 256; | |
1012 | rdev->config.evergreen.max_threads = 192; | |
1013 | rdev->config.evergreen.max_gs_threads = 16; | |
1014 | rdev->config.evergreen.max_stack_entries = 256; | |
1015 | rdev->config.evergreen.sx_num_of_sets = 4; | |
1016 | rdev->config.evergreen.sx_max_export_size = 128; | |
1017 | rdev->config.evergreen.sx_max_export_pos_size = 32; | |
1018 | rdev->config.evergreen.sx_max_export_smx_size = 96; | |
1019 | rdev->config.evergreen.max_hw_contexts = 4; | |
1020 | rdev->config.evergreen.sq_num_cf_insts = 1; | |
1021 | ||
1022 | rdev->config.evergreen.sc_prim_fifo_size = 0x40; | |
1023 | rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; | |
1024 | rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; | |
1025 | break; | |
1026 | } | |
1027 | ||
1028 | /* Initialize HDP */ | |
1029 | for (i = 0, j = 0; i < 32; i++, j += 0x18) { | |
1030 | WREG32((0x2c14 + j), 0x00000000); | |
1031 | WREG32((0x2c18 + j), 0x00000000); | |
1032 | WREG32((0x2c1c + j), 0x00000000); | |
1033 | WREG32((0x2c20 + j), 0x00000000); | |
1034 | WREG32((0x2c24 + j), 0x00000000); | |
1035 | } | |
1036 | ||
1037 | WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); | |
1038 | ||
1039 | cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & ~2; | |
1040 | ||
1041 | cc_gc_shader_pipe_config |= | |
1042 | INACTIVE_QD_PIPES((EVERGREEN_MAX_PIPES_MASK << rdev->config.evergreen.max_pipes) | |
1043 | & EVERGREEN_MAX_PIPES_MASK); | |
1044 | cc_gc_shader_pipe_config |= | |
1045 | INACTIVE_SIMDS((EVERGREEN_MAX_SIMDS_MASK << rdev->config.evergreen.max_simds) | |
1046 | & EVERGREEN_MAX_SIMDS_MASK); | |
1047 | ||
1048 | cc_rb_backend_disable = | |
1049 | BACKEND_DISABLE((EVERGREEN_MAX_BACKENDS_MASK << rdev->config.evergreen.max_backends) | |
1050 | & EVERGREEN_MAX_BACKENDS_MASK); | |
1051 | ||
1052 | ||
1053 | mc_shared_chmap = RREG32(MC_SHARED_CHMAP); | |
1054 | mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG); | |
1055 | ||
1056 | switch (rdev->config.evergreen.max_tile_pipes) { | |
1057 | case 1: | |
1058 | default: | |
1059 | gb_addr_config |= NUM_PIPES(0); | |
1060 | break; | |
1061 | case 2: | |
1062 | gb_addr_config |= NUM_PIPES(1); | |
1063 | break; | |
1064 | case 4: | |
1065 | gb_addr_config |= NUM_PIPES(2); | |
1066 | break; | |
1067 | case 8: | |
1068 | gb_addr_config |= NUM_PIPES(3); | |
1069 | break; | |
1070 | } | |
1071 | ||
1072 | gb_addr_config |= PIPE_INTERLEAVE_SIZE((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT); | |
1073 | gb_addr_config |= BANK_INTERLEAVE_SIZE(0); | |
1074 | gb_addr_config |= NUM_SHADER_ENGINES(rdev->config.evergreen.num_ses - 1); | |
1075 | gb_addr_config |= SHADER_ENGINE_TILE_SIZE(1); | |
1076 | gb_addr_config |= NUM_GPUS(0); /* Hemlock? */ | |
1077 | gb_addr_config |= MULTI_GPU_TILE_SIZE(2); | |
1078 | ||
1079 | if (((mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) > 2) | |
1080 | gb_addr_config |= ROW_SIZE(2); | |
1081 | else | |
1082 | gb_addr_config |= ROW_SIZE((mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT); | |
1083 | ||
1084 | if (rdev->ddev->pdev->device == 0x689e) { | |
1085 | u32 efuse_straps_4; | |
1086 | u32 efuse_straps_3; | |
1087 | u8 efuse_box_bit_131_124; | |
1088 | ||
1089 | WREG32(RCU_IND_INDEX, 0x204); | |
1090 | efuse_straps_4 = RREG32(RCU_IND_DATA); | |
1091 | WREG32(RCU_IND_INDEX, 0x203); | |
1092 | efuse_straps_3 = RREG32(RCU_IND_DATA); | |
1093 | efuse_box_bit_131_124 = (u8)(((efuse_straps_4 & 0xf) << 4) | ((efuse_straps_3 & 0xf0000000) >> 28)); | |
1094 | ||
1095 | switch(efuse_box_bit_131_124) { | |
1096 | case 0x00: | |
1097 | gb_backend_map = 0x76543210; | |
1098 | break; | |
1099 | case 0x55: | |
1100 | gb_backend_map = 0x77553311; | |
1101 | break; | |
1102 | case 0x56: | |
1103 | gb_backend_map = 0x77553300; | |
1104 | break; | |
1105 | case 0x59: | |
1106 | gb_backend_map = 0x77552211; | |
1107 | break; | |
1108 | case 0x66: | |
1109 | gb_backend_map = 0x77443300; | |
1110 | break; | |
1111 | case 0x99: | |
1112 | gb_backend_map = 0x66552211; | |
1113 | break; | |
1114 | case 0x5a: | |
1115 | gb_backend_map = 0x77552200; | |
1116 | break; | |
1117 | case 0xaa: | |
1118 | gb_backend_map = 0x66442200; | |
1119 | break; | |
1120 | case 0x95: | |
1121 | gb_backend_map = 0x66553311; | |
1122 | break; | |
1123 | default: | |
1124 | DRM_ERROR("bad backend map, using default\n"); | |
1125 | gb_backend_map = | |
1126 | evergreen_get_tile_pipe_to_backend_map(rdev, | |
1127 | rdev->config.evergreen.max_tile_pipes, | |
1128 | rdev->config.evergreen.max_backends, | |
1129 | ((EVERGREEN_MAX_BACKENDS_MASK << | |
1130 | rdev->config.evergreen.max_backends) & | |
1131 | EVERGREEN_MAX_BACKENDS_MASK)); | |
1132 | break; | |
1133 | } | |
1134 | } else if (rdev->ddev->pdev->device == 0x68b9) { | |
1135 | u32 efuse_straps_3; | |
1136 | u8 efuse_box_bit_127_124; | |
1137 | ||
1138 | WREG32(RCU_IND_INDEX, 0x203); | |
1139 | efuse_straps_3 = RREG32(RCU_IND_DATA); | |
1140 | efuse_box_bit_127_124 = (u8)(efuse_straps_3 & 0xF0000000) >> 28; | |
1141 | ||
1142 | switch(efuse_box_bit_127_124) { | |
1143 | case 0x0: | |
1144 | gb_backend_map = 0x00003210; | |
1145 | break; | |
1146 | case 0x5: | |
1147 | case 0x6: | |
1148 | case 0x9: | |
1149 | case 0xa: | |
1150 | gb_backend_map = 0x00003311; | |
1151 | break; | |
1152 | default: | |
1153 | DRM_ERROR("bad backend map, using default\n"); | |
1154 | gb_backend_map = | |
1155 | evergreen_get_tile_pipe_to_backend_map(rdev, | |
1156 | rdev->config.evergreen.max_tile_pipes, | |
1157 | rdev->config.evergreen.max_backends, | |
1158 | ((EVERGREEN_MAX_BACKENDS_MASK << | |
1159 | rdev->config.evergreen.max_backends) & | |
1160 | EVERGREEN_MAX_BACKENDS_MASK)); | |
1161 | break; | |
1162 | } | |
1163 | } else | |
1164 | gb_backend_map = | |
1165 | evergreen_get_tile_pipe_to_backend_map(rdev, | |
1166 | rdev->config.evergreen.max_tile_pipes, | |
1167 | rdev->config.evergreen.max_backends, | |
1168 | ((EVERGREEN_MAX_BACKENDS_MASK << | |
1169 | rdev->config.evergreen.max_backends) & | |
1170 | EVERGREEN_MAX_BACKENDS_MASK)); | |
1171 | ||
e7aeeba6 | 1172 | rdev->config.evergreen.tile_config = gb_addr_config; |
32fcdbf4 AD |
1173 | WREG32(GB_BACKEND_MAP, gb_backend_map); |
1174 | WREG32(GB_ADDR_CONFIG, gb_addr_config); | |
1175 | WREG32(DMIF_ADDR_CONFIG, gb_addr_config); | |
1176 | WREG32(HDP_ADDR_CONFIG, gb_addr_config); | |
1177 | ||
1178 | num_shader_engines = ((RREG32(GB_ADDR_CONFIG) & NUM_SHADER_ENGINES(3)) >> 12) + 1; | |
1179 | grbm_gfx_index = INSTANCE_BROADCAST_WRITES; | |
1180 | ||
1181 | for (i = 0; i < rdev->config.evergreen.num_ses; i++) { | |
1182 | u32 rb = cc_rb_backend_disable | (0xf0 << 16); | |
1183 | u32 sp = cc_gc_shader_pipe_config; | |
1184 | u32 gfx = grbm_gfx_index | SE_INDEX(i); | |
1185 | ||
1186 | if (i == num_shader_engines) { | |
1187 | rb |= BACKEND_DISABLE(EVERGREEN_MAX_BACKENDS_MASK); | |
1188 | sp |= INACTIVE_SIMDS(EVERGREEN_MAX_SIMDS_MASK); | |
1189 | } | |
1190 | ||
1191 | WREG32(GRBM_GFX_INDEX, gfx); | |
1192 | WREG32(RLC_GFX_INDEX, gfx); | |
1193 | ||
1194 | WREG32(CC_RB_BACKEND_DISABLE, rb); | |
1195 | WREG32(CC_SYS_RB_BACKEND_DISABLE, rb); | |
1196 | WREG32(GC_USER_RB_BACKEND_DISABLE, rb); | |
1197 | WREG32(CC_GC_SHADER_PIPE_CONFIG, sp); | |
1198 | } | |
1199 | ||
1200 | grbm_gfx_index |= SE_BROADCAST_WRITES; | |
1201 | WREG32(GRBM_GFX_INDEX, grbm_gfx_index); | |
1202 | WREG32(RLC_GFX_INDEX, grbm_gfx_index); | |
1203 | ||
1204 | WREG32(CGTS_SYS_TCC_DISABLE, 0); | |
1205 | WREG32(CGTS_TCC_DISABLE, 0); | |
1206 | WREG32(CGTS_USER_SYS_TCC_DISABLE, 0); | |
1207 | WREG32(CGTS_USER_TCC_DISABLE, 0); | |
1208 | ||
1209 | /* set HW defaults for 3D engine */ | |
1210 | WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | | |
1211 | ROQ_IB2_START(0x2b))); | |
1212 | ||
1213 | WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30)); | |
1214 | ||
1215 | WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | | |
1216 | SYNC_GRADIENT | | |
1217 | SYNC_WALKER | | |
1218 | SYNC_ALIGNER)); | |
1219 | ||
1220 | sx_debug_1 = RREG32(SX_DEBUG_1); | |
1221 | sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS; | |
1222 | WREG32(SX_DEBUG_1, sx_debug_1); | |
1223 | ||
1224 | ||
1225 | smx_dc_ctl0 = RREG32(SMX_DC_CTL0); | |
1226 | smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff); | |
1227 | smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.evergreen.sx_num_of_sets); | |
1228 | WREG32(SMX_DC_CTL0, smx_dc_ctl0); | |
1229 | ||
1230 | WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_size / 4) - 1) | | |
1231 | POSITION_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_pos_size / 4) - 1) | | |
1232 | SMX_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_smx_size / 4) - 1))); | |
1233 | ||
1234 | WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.evergreen.sc_prim_fifo_size) | | |
1235 | SC_HIZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_hiz_tile_fifo_size) | | |
1236 | SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_earlyz_tile_fifo_size))); | |
1237 | ||
1238 | WREG32(VGT_NUM_INSTANCES, 1); | |
1239 | WREG32(SPI_CONFIG_CNTL, 0); | |
1240 | WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4)); | |
1241 | WREG32(CP_PERFMON_CNTL, 0); | |
1242 | ||
1243 | WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.evergreen.sq_num_cf_insts) | | |
1244 | FETCH_FIFO_HIWATER(0x4) | | |
1245 | DONE_FIFO_HIWATER(0xe0) | | |
1246 | ALU_UPDATE_FIFO_HIWATER(0x8))); | |
1247 | ||
1248 | sq_config = RREG32(SQ_CONFIG); | |
1249 | sq_config &= ~(PS_PRIO(3) | | |
1250 | VS_PRIO(3) | | |
1251 | GS_PRIO(3) | | |
1252 | ES_PRIO(3)); | |
1253 | sq_config |= (VC_ENABLE | | |
1254 | EXPORT_SRC_C | | |
1255 | PS_PRIO(0) | | |
1256 | VS_PRIO(1) | | |
1257 | GS_PRIO(2) | | |
1258 | ES_PRIO(3)); | |
1259 | ||
1260 | if (rdev->family == CHIP_CEDAR) | |
1261 | /* no vertex cache */ | |
1262 | sq_config &= ~VC_ENABLE; | |
1263 | ||
1264 | sq_lds_resource_mgmt = RREG32(SQ_LDS_RESOURCE_MGMT); | |
1265 | ||
1266 | sq_gpr_resource_mgmt_1 = NUM_PS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2))* 12 / 32); | |
1267 | sq_gpr_resource_mgmt_1 |= NUM_VS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 6 / 32); | |
1268 | sq_gpr_resource_mgmt_1 |= NUM_CLAUSE_TEMP_GPRS(4); | |
1269 | sq_gpr_resource_mgmt_2 = NUM_GS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32); | |
1270 | sq_gpr_resource_mgmt_2 |= NUM_ES_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32); | |
1271 | sq_gpr_resource_mgmt_3 = NUM_HS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32); | |
1272 | sq_gpr_resource_mgmt_3 |= NUM_LS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32); | |
1273 | ||
1274 | if (rdev->family == CHIP_CEDAR) | |
1275 | ps_thread_count = 96; | |
1276 | else | |
1277 | ps_thread_count = 128; | |
1278 | ||
1279 | sq_thread_resource_mgmt = NUM_PS_THREADS(ps_thread_count); | |
f96b35cd AD |
1280 | sq_thread_resource_mgmt |= NUM_VS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8); |
1281 | sq_thread_resource_mgmt |= NUM_GS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8); | |
1282 | sq_thread_resource_mgmt |= NUM_ES_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8); | |
1283 | sq_thread_resource_mgmt_2 = NUM_HS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8); | |
1284 | sq_thread_resource_mgmt_2 |= NUM_LS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8); | |
32fcdbf4 AD |
1285 | |
1286 | sq_stack_resource_mgmt_1 = NUM_PS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6); | |
1287 | sq_stack_resource_mgmt_1 |= NUM_VS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6); | |
1288 | sq_stack_resource_mgmt_2 = NUM_GS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6); | |
1289 | sq_stack_resource_mgmt_2 |= NUM_ES_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6); | |
1290 | sq_stack_resource_mgmt_3 = NUM_HS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6); | |
1291 | sq_stack_resource_mgmt_3 |= NUM_LS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6); | |
1292 | ||
1293 | WREG32(SQ_CONFIG, sq_config); | |
1294 | WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1); | |
1295 | WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2); | |
1296 | WREG32(SQ_GPR_RESOURCE_MGMT_3, sq_gpr_resource_mgmt_3); | |
1297 | WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt); | |
1298 | WREG32(SQ_THREAD_RESOURCE_MGMT_2, sq_thread_resource_mgmt_2); | |
1299 | WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1); | |
1300 | WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2); | |
1301 | WREG32(SQ_STACK_RESOURCE_MGMT_3, sq_stack_resource_mgmt_3); | |
1302 | WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0); | |
1303 | WREG32(SQ_LDS_RESOURCE_MGMT, sq_lds_resource_mgmt); | |
1304 | ||
1305 | WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) | | |
1306 | FORCE_EOV_MAX_REZ_CNT(255))); | |
1307 | ||
1308 | if (rdev->family == CHIP_CEDAR) | |
1309 | vgt_cache_invalidation = CACHE_INVALIDATION(TC_ONLY); | |
1310 | else | |
1311 | vgt_cache_invalidation = CACHE_INVALIDATION(VC_AND_TC); | |
1312 | vgt_cache_invalidation |= AUTO_INVLD_EN(ES_AND_GS_AUTO); | |
1313 | WREG32(VGT_CACHE_INVALIDATION, vgt_cache_invalidation); | |
1314 | ||
1315 | WREG32(VGT_GS_VERTEX_REUSE, 16); | |
1316 | WREG32(PA_SC_LINE_STIPPLE_STATE, 0); | |
1317 | ||
60a4a3e0 AD |
1318 | WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, 14); |
1319 | WREG32(VGT_OUT_DEALLOC_CNTL, 16); | |
1320 | ||
32fcdbf4 AD |
1321 | WREG32(CB_PERF_CTR0_SEL_0, 0); |
1322 | WREG32(CB_PERF_CTR0_SEL_1, 0); | |
1323 | WREG32(CB_PERF_CTR1_SEL_0, 0); | |
1324 | WREG32(CB_PERF_CTR1_SEL_1, 0); | |
1325 | WREG32(CB_PERF_CTR2_SEL_0, 0); | |
1326 | WREG32(CB_PERF_CTR2_SEL_1, 0); | |
1327 | WREG32(CB_PERF_CTR3_SEL_0, 0); | |
1328 | WREG32(CB_PERF_CTR3_SEL_1, 0); | |
1329 | ||
60a4a3e0 AD |
1330 | /* clear render buffer base addresses */ |
1331 | WREG32(CB_COLOR0_BASE, 0); | |
1332 | WREG32(CB_COLOR1_BASE, 0); | |
1333 | WREG32(CB_COLOR2_BASE, 0); | |
1334 | WREG32(CB_COLOR3_BASE, 0); | |
1335 | WREG32(CB_COLOR4_BASE, 0); | |
1336 | WREG32(CB_COLOR5_BASE, 0); | |
1337 | WREG32(CB_COLOR6_BASE, 0); | |
1338 | WREG32(CB_COLOR7_BASE, 0); | |
1339 | WREG32(CB_COLOR8_BASE, 0); | |
1340 | WREG32(CB_COLOR9_BASE, 0); | |
1341 | WREG32(CB_COLOR10_BASE, 0); | |
1342 | WREG32(CB_COLOR11_BASE, 0); | |
1343 | ||
1344 | /* set the shader const cache sizes to 0 */ | |
1345 | for (i = SQ_ALU_CONST_BUFFER_SIZE_PS_0; i < 0x28200; i += 4) | |
1346 | WREG32(i, 0); | |
1347 | for (i = SQ_ALU_CONST_BUFFER_SIZE_HS_0; i < 0x29000; i += 4) | |
1348 | WREG32(i, 0); | |
1349 | ||
32fcdbf4 AD |
1350 | hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL); |
1351 | WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl); | |
1352 | ||
1353 | WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3)); | |
1354 | ||
1355 | udelay(50); | |
1356 | ||
bcc1c2a1 AD |
1357 | } |
1358 | ||
1359 | int evergreen_mc_init(struct radeon_device *rdev) | |
1360 | { | |
bcc1c2a1 AD |
1361 | u32 tmp; |
1362 | int chansize, numchan; | |
bcc1c2a1 AD |
1363 | |
1364 | /* Get VRAM informations */ | |
1365 | rdev->mc.vram_is_ddr = true; | |
1366 | tmp = RREG32(MC_ARB_RAMCFG); | |
1367 | if (tmp & CHANSIZE_OVERRIDE) { | |
1368 | chansize = 16; | |
1369 | } else if (tmp & CHANSIZE_MASK) { | |
1370 | chansize = 64; | |
1371 | } else { | |
1372 | chansize = 32; | |
1373 | } | |
1374 | tmp = RREG32(MC_SHARED_CHMAP); | |
1375 | switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) { | |
1376 | case 0: | |
1377 | default: | |
1378 | numchan = 1; | |
1379 | break; | |
1380 | case 1: | |
1381 | numchan = 2; | |
1382 | break; | |
1383 | case 2: | |
1384 | numchan = 4; | |
1385 | break; | |
1386 | case 3: | |
1387 | numchan = 8; | |
1388 | break; | |
1389 | } | |
1390 | rdev->mc.vram_width = numchan * chansize; | |
1391 | /* Could aper size report 0 ? */ | |
01d73a69 JC |
1392 | rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); |
1393 | rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); | |
bcc1c2a1 AD |
1394 | /* Setup GPU memory space */ |
1395 | /* size in MB on evergreen */ | |
1396 | rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024; | |
1397 | rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024; | |
51e5fcd3 | 1398 | rdev->mc.visible_vram_size = rdev->mc.aper_size; |
d594e46a | 1399 | r600_vram_gtt_location(rdev, &rdev->mc); |
f47299c5 AD |
1400 | radeon_update_bandwidth_info(rdev); |
1401 | ||
bcc1c2a1 AD |
1402 | return 0; |
1403 | } | |
d594e46a | 1404 | |
225758d8 JG |
1405 | bool evergreen_gpu_is_lockup(struct radeon_device *rdev) |
1406 | { | |
1407 | /* FIXME: implement for evergreen */ | |
1408 | return false; | |
1409 | } | |
1410 | ||
747943ea | 1411 | static int evergreen_gpu_soft_reset(struct radeon_device *rdev) |
bcc1c2a1 | 1412 | { |
747943ea AD |
1413 | struct evergreen_mc_save save; |
1414 | u32 srbm_reset = 0; | |
1415 | u32 grbm_reset = 0; | |
1416 | ||
1417 | dev_info(rdev->dev, "GPU softreset \n"); | |
1418 | dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n", | |
1419 | RREG32(GRBM_STATUS)); | |
1420 | dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n", | |
1421 | RREG32(GRBM_STATUS_SE0)); | |
1422 | dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n", | |
1423 | RREG32(GRBM_STATUS_SE1)); | |
1424 | dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n", | |
1425 | RREG32(SRBM_STATUS)); | |
1426 | evergreen_mc_stop(rdev, &save); | |
1427 | if (evergreen_mc_wait_for_idle(rdev)) { | |
1428 | dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); | |
1429 | } | |
1430 | /* Disable CP parsing/prefetching */ | |
1431 | WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT); | |
1432 | ||
1433 | /* reset all the gfx blocks */ | |
1434 | grbm_reset = (SOFT_RESET_CP | | |
1435 | SOFT_RESET_CB | | |
1436 | SOFT_RESET_DB | | |
1437 | SOFT_RESET_PA | | |
1438 | SOFT_RESET_SC | | |
1439 | SOFT_RESET_SPI | | |
1440 | SOFT_RESET_SH | | |
1441 | SOFT_RESET_SX | | |
1442 | SOFT_RESET_TC | | |
1443 | SOFT_RESET_TA | | |
1444 | SOFT_RESET_VC | | |
1445 | SOFT_RESET_VGT); | |
1446 | ||
1447 | dev_info(rdev->dev, " GRBM_SOFT_RESET=0x%08X\n", grbm_reset); | |
1448 | WREG32(GRBM_SOFT_RESET, grbm_reset); | |
1449 | (void)RREG32(GRBM_SOFT_RESET); | |
1450 | udelay(50); | |
1451 | WREG32(GRBM_SOFT_RESET, 0); | |
1452 | (void)RREG32(GRBM_SOFT_RESET); | |
1453 | ||
1454 | /* reset all the system blocks */ | |
1455 | srbm_reset = SRBM_SOFT_RESET_ALL_MASK; | |
1456 | ||
1457 | dev_info(rdev->dev, " SRBM_SOFT_RESET=0x%08X\n", srbm_reset); | |
1458 | WREG32(SRBM_SOFT_RESET, srbm_reset); | |
1459 | (void)RREG32(SRBM_SOFT_RESET); | |
1460 | udelay(50); | |
1461 | WREG32(SRBM_SOFT_RESET, 0); | |
1462 | (void)RREG32(SRBM_SOFT_RESET); | |
1463 | /* Wait a little for things to settle down */ | |
1464 | udelay(50); | |
1465 | dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n", | |
1466 | RREG32(GRBM_STATUS)); | |
1467 | dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n", | |
1468 | RREG32(GRBM_STATUS_SE0)); | |
1469 | dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n", | |
1470 | RREG32(GRBM_STATUS_SE1)); | |
1471 | dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n", | |
1472 | RREG32(SRBM_STATUS)); | |
1473 | /* After reset we need to reinit the asic as GPU often endup in an | |
1474 | * incoherent state. | |
1475 | */ | |
1476 | atom_asic_init(rdev->mode_info.atom_context); | |
1477 | evergreen_mc_resume(rdev, &save); | |
bcc1c2a1 AD |
1478 | return 0; |
1479 | } | |
1480 | ||
a2d07b74 | 1481 | int evergreen_asic_reset(struct radeon_device *rdev) |
bcc1c2a1 | 1482 | { |
747943ea AD |
1483 | return evergreen_gpu_soft_reset(rdev); |
1484 | } | |
1485 | ||
45f9a39b AD |
1486 | /* Interrupts */ |
1487 | ||
1488 | u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc) | |
1489 | { | |
1490 | switch (crtc) { | |
1491 | case 0: | |
1492 | return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC0_REGISTER_OFFSET); | |
1493 | case 1: | |
1494 | return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC1_REGISTER_OFFSET); | |
1495 | case 2: | |
1496 | return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC2_REGISTER_OFFSET); | |
1497 | case 3: | |
1498 | return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC3_REGISTER_OFFSET); | |
1499 | case 4: | |
1500 | return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC4_REGISTER_OFFSET); | |
1501 | case 5: | |
1502 | return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC5_REGISTER_OFFSET); | |
1503 | default: | |
1504 | return 0; | |
1505 | } | |
1506 | } | |
1507 | ||
1508 | void evergreen_disable_interrupt_state(struct radeon_device *rdev) | |
1509 | { | |
1510 | u32 tmp; | |
1511 | ||
1512 | WREG32(CP_INT_CNTL, 0); | |
1513 | WREG32(GRBM_INT_CNTL, 0); | |
1514 | WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); | |
1515 | WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); | |
1516 | WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); | |
1517 | WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); | |
1518 | WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); | |
1519 | WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); | |
1520 | ||
1521 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); | |
1522 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); | |
1523 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); | |
1524 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); | |
1525 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); | |
1526 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); | |
1527 | ||
1528 | WREG32(DACA_AUTODETECT_INT_CONTROL, 0); | |
1529 | WREG32(DACB_AUTODETECT_INT_CONTROL, 0); | |
1530 | ||
1531 | tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY; | |
1532 | WREG32(DC_HPD1_INT_CONTROL, tmp); | |
1533 | tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY; | |
1534 | WREG32(DC_HPD2_INT_CONTROL, tmp); | |
1535 | tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY; | |
1536 | WREG32(DC_HPD3_INT_CONTROL, tmp); | |
1537 | tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY; | |
1538 | WREG32(DC_HPD4_INT_CONTROL, tmp); | |
1539 | tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY; | |
1540 | WREG32(DC_HPD5_INT_CONTROL, tmp); | |
1541 | tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY; | |
1542 | WREG32(DC_HPD6_INT_CONTROL, tmp); | |
1543 | ||
1544 | } | |
1545 | ||
1546 | int evergreen_irq_set(struct radeon_device *rdev) | |
1547 | { | |
1548 | u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE; | |
1549 | u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0; | |
1550 | u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6; | |
2031f77c | 1551 | u32 grbm_int_cntl = 0; |
45f9a39b AD |
1552 | |
1553 | if (!rdev->irq.installed) { | |
1554 | WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n"); | |
1555 | return -EINVAL; | |
1556 | } | |
1557 | /* don't enable anything if the ih is disabled */ | |
1558 | if (!rdev->ih.enabled) { | |
1559 | r600_disable_interrupts(rdev); | |
1560 | /* force the active interrupt state to all disabled */ | |
1561 | evergreen_disable_interrupt_state(rdev); | |
1562 | return 0; | |
1563 | } | |
1564 | ||
1565 | hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN; | |
1566 | hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN; | |
1567 | hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN; | |
1568 | hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN; | |
1569 | hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN; | |
1570 | hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN; | |
1571 | ||
1572 | if (rdev->irq.sw_int) { | |
1573 | DRM_DEBUG("evergreen_irq_set: sw int\n"); | |
1574 | cp_int_cntl |= RB_INT_ENABLE; | |
1575 | } | |
1576 | if (rdev->irq.crtc_vblank_int[0]) { | |
1577 | DRM_DEBUG("evergreen_irq_set: vblank 0\n"); | |
1578 | crtc1 |= VBLANK_INT_MASK; | |
1579 | } | |
1580 | if (rdev->irq.crtc_vblank_int[1]) { | |
1581 | DRM_DEBUG("evergreen_irq_set: vblank 1\n"); | |
1582 | crtc2 |= VBLANK_INT_MASK; | |
1583 | } | |
1584 | if (rdev->irq.crtc_vblank_int[2]) { | |
1585 | DRM_DEBUG("evergreen_irq_set: vblank 2\n"); | |
1586 | crtc3 |= VBLANK_INT_MASK; | |
1587 | } | |
1588 | if (rdev->irq.crtc_vblank_int[3]) { | |
1589 | DRM_DEBUG("evergreen_irq_set: vblank 3\n"); | |
1590 | crtc4 |= VBLANK_INT_MASK; | |
1591 | } | |
1592 | if (rdev->irq.crtc_vblank_int[4]) { | |
1593 | DRM_DEBUG("evergreen_irq_set: vblank 4\n"); | |
1594 | crtc5 |= VBLANK_INT_MASK; | |
1595 | } | |
1596 | if (rdev->irq.crtc_vblank_int[5]) { | |
1597 | DRM_DEBUG("evergreen_irq_set: vblank 5\n"); | |
1598 | crtc6 |= VBLANK_INT_MASK; | |
1599 | } | |
1600 | if (rdev->irq.hpd[0]) { | |
1601 | DRM_DEBUG("evergreen_irq_set: hpd 1\n"); | |
1602 | hpd1 |= DC_HPDx_INT_EN; | |
1603 | } | |
1604 | if (rdev->irq.hpd[1]) { | |
1605 | DRM_DEBUG("evergreen_irq_set: hpd 2\n"); | |
1606 | hpd2 |= DC_HPDx_INT_EN; | |
1607 | } | |
1608 | if (rdev->irq.hpd[2]) { | |
1609 | DRM_DEBUG("evergreen_irq_set: hpd 3\n"); | |
1610 | hpd3 |= DC_HPDx_INT_EN; | |
1611 | } | |
1612 | if (rdev->irq.hpd[3]) { | |
1613 | DRM_DEBUG("evergreen_irq_set: hpd 4\n"); | |
1614 | hpd4 |= DC_HPDx_INT_EN; | |
1615 | } | |
1616 | if (rdev->irq.hpd[4]) { | |
1617 | DRM_DEBUG("evergreen_irq_set: hpd 5\n"); | |
1618 | hpd5 |= DC_HPDx_INT_EN; | |
1619 | } | |
1620 | if (rdev->irq.hpd[5]) { | |
1621 | DRM_DEBUG("evergreen_irq_set: hpd 6\n"); | |
1622 | hpd6 |= DC_HPDx_INT_EN; | |
1623 | } | |
2031f77c AD |
1624 | if (rdev->irq.gui_idle) { |
1625 | DRM_DEBUG("gui idle\n"); | |
1626 | grbm_int_cntl |= GUI_IDLE_INT_ENABLE; | |
1627 | } | |
45f9a39b AD |
1628 | |
1629 | WREG32(CP_INT_CNTL, cp_int_cntl); | |
2031f77c | 1630 | WREG32(GRBM_INT_CNTL, grbm_int_cntl); |
45f9a39b AD |
1631 | |
1632 | WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1); | |
1633 | WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2); | |
1634 | WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3); | |
1635 | WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4); | |
1636 | WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5); | |
1637 | WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6); | |
1638 | ||
1639 | WREG32(DC_HPD1_INT_CONTROL, hpd1); | |
1640 | WREG32(DC_HPD2_INT_CONTROL, hpd2); | |
1641 | WREG32(DC_HPD3_INT_CONTROL, hpd3); | |
1642 | WREG32(DC_HPD4_INT_CONTROL, hpd4); | |
1643 | WREG32(DC_HPD5_INT_CONTROL, hpd5); | |
1644 | WREG32(DC_HPD6_INT_CONTROL, hpd6); | |
1645 | ||
bcc1c2a1 AD |
1646 | return 0; |
1647 | } | |
1648 | ||
45f9a39b AD |
1649 | static inline void evergreen_irq_ack(struct radeon_device *rdev, |
1650 | u32 *disp_int, | |
1651 | u32 *disp_int_cont, | |
1652 | u32 *disp_int_cont2, | |
1653 | u32 *disp_int_cont3, | |
1654 | u32 *disp_int_cont4, | |
1655 | u32 *disp_int_cont5) | |
1656 | { | |
1657 | u32 tmp; | |
1658 | ||
1659 | *disp_int = RREG32(DISP_INTERRUPT_STATUS); | |
1660 | *disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE); | |
1661 | *disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2); | |
1662 | *disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3); | |
1663 | *disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4); | |
1664 | *disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5); | |
1665 | ||
1666 | if (*disp_int & LB_D1_VBLANK_INTERRUPT) | |
1667 | WREG32(VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK); | |
1668 | if (*disp_int & LB_D1_VLINE_INTERRUPT) | |
1669 | WREG32(VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK); | |
1670 | ||
1671 | if (*disp_int_cont & LB_D2_VBLANK_INTERRUPT) | |
1672 | WREG32(VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK); | |
1673 | if (*disp_int_cont & LB_D2_VLINE_INTERRUPT) | |
1674 | WREG32(VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK); | |
1675 | ||
1676 | if (*disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) | |
1677 | WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK); | |
1678 | if (*disp_int_cont2 & LB_D3_VLINE_INTERRUPT) | |
1679 | WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK); | |
1680 | ||
1681 | if (*disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) | |
1682 | WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK); | |
1683 | if (*disp_int_cont3 & LB_D4_VLINE_INTERRUPT) | |
1684 | WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK); | |
1685 | ||
1686 | if (*disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) | |
1687 | WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK); | |
1688 | if (*disp_int_cont4 & LB_D5_VLINE_INTERRUPT) | |
1689 | WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK); | |
1690 | ||
1691 | if (*disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) | |
1692 | WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK); | |
1693 | if (*disp_int_cont5 & LB_D6_VLINE_INTERRUPT) | |
1694 | WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK); | |
1695 | ||
1696 | if (*disp_int & DC_HPD1_INTERRUPT) { | |
1697 | tmp = RREG32(DC_HPD1_INT_CONTROL); | |
1698 | tmp |= DC_HPDx_INT_ACK; | |
1699 | WREG32(DC_HPD1_INT_CONTROL, tmp); | |
1700 | } | |
1701 | if (*disp_int_cont & DC_HPD2_INTERRUPT) { | |
1702 | tmp = RREG32(DC_HPD2_INT_CONTROL); | |
1703 | tmp |= DC_HPDx_INT_ACK; | |
1704 | WREG32(DC_HPD2_INT_CONTROL, tmp); | |
1705 | } | |
1706 | if (*disp_int_cont2 & DC_HPD3_INTERRUPT) { | |
1707 | tmp = RREG32(DC_HPD3_INT_CONTROL); | |
1708 | tmp |= DC_HPDx_INT_ACK; | |
1709 | WREG32(DC_HPD3_INT_CONTROL, tmp); | |
1710 | } | |
1711 | if (*disp_int_cont3 & DC_HPD4_INTERRUPT) { | |
1712 | tmp = RREG32(DC_HPD4_INT_CONTROL); | |
1713 | tmp |= DC_HPDx_INT_ACK; | |
1714 | WREG32(DC_HPD4_INT_CONTROL, tmp); | |
1715 | } | |
1716 | if (*disp_int_cont4 & DC_HPD5_INTERRUPT) { | |
1717 | tmp = RREG32(DC_HPD5_INT_CONTROL); | |
1718 | tmp |= DC_HPDx_INT_ACK; | |
1719 | WREG32(DC_HPD5_INT_CONTROL, tmp); | |
1720 | } | |
1721 | if (*disp_int_cont5 & DC_HPD6_INTERRUPT) { | |
1722 | tmp = RREG32(DC_HPD5_INT_CONTROL); | |
1723 | tmp |= DC_HPDx_INT_ACK; | |
1724 | WREG32(DC_HPD6_INT_CONTROL, tmp); | |
1725 | } | |
1726 | } | |
1727 | ||
1728 | void evergreen_irq_disable(struct radeon_device *rdev) | |
1729 | { | |
1730 | u32 disp_int, disp_int_cont, disp_int_cont2; | |
1731 | u32 disp_int_cont3, disp_int_cont4, disp_int_cont5; | |
1732 | ||
1733 | r600_disable_interrupts(rdev); | |
1734 | /* Wait and acknowledge irq */ | |
1735 | mdelay(1); | |
1736 | evergreen_irq_ack(rdev, &disp_int, &disp_int_cont, &disp_int_cont2, | |
1737 | &disp_int_cont3, &disp_int_cont4, &disp_int_cont5); | |
1738 | evergreen_disable_interrupt_state(rdev); | |
1739 | } | |
1740 | ||
1741 | static void evergreen_irq_suspend(struct radeon_device *rdev) | |
1742 | { | |
1743 | evergreen_irq_disable(rdev); | |
1744 | r600_rlc_stop(rdev); | |
1745 | } | |
1746 | ||
1747 | static inline u32 evergreen_get_ih_wptr(struct radeon_device *rdev) | |
1748 | { | |
1749 | u32 wptr, tmp; | |
1750 | ||
1751 | /* XXX use writeback */ | |
1752 | wptr = RREG32(IH_RB_WPTR); | |
1753 | ||
1754 | if (wptr & RB_OVERFLOW) { | |
1755 | /* When a ring buffer overflow happen start parsing interrupt | |
1756 | * from the last not overwritten vector (wptr + 16). Hopefully | |
1757 | * this should allow us to catchup. | |
1758 | */ | |
1759 | dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n", | |
1760 | wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask); | |
1761 | rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask; | |
1762 | tmp = RREG32(IH_RB_CNTL); | |
1763 | tmp |= IH_WPTR_OVERFLOW_CLEAR; | |
1764 | WREG32(IH_RB_CNTL, tmp); | |
1765 | } | |
1766 | return (wptr & rdev->ih.ptr_mask); | |
1767 | } | |
1768 | ||
1769 | int evergreen_irq_process(struct radeon_device *rdev) | |
1770 | { | |
1771 | u32 wptr = evergreen_get_ih_wptr(rdev); | |
1772 | u32 rptr = rdev->ih.rptr; | |
1773 | u32 src_id, src_data; | |
1774 | u32 ring_index; | |
1775 | u32 disp_int, disp_int_cont, disp_int_cont2; | |
1776 | u32 disp_int_cont3, disp_int_cont4, disp_int_cont5; | |
1777 | unsigned long flags; | |
1778 | bool queue_hotplug = false; | |
1779 | ||
1780 | DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr); | |
1781 | if (!rdev->ih.enabled) | |
1782 | return IRQ_NONE; | |
1783 | ||
1784 | spin_lock_irqsave(&rdev->ih.lock, flags); | |
1785 | ||
1786 | if (rptr == wptr) { | |
1787 | spin_unlock_irqrestore(&rdev->ih.lock, flags); | |
1788 | return IRQ_NONE; | |
1789 | } | |
1790 | if (rdev->shutdown) { | |
1791 | spin_unlock_irqrestore(&rdev->ih.lock, flags); | |
1792 | return IRQ_NONE; | |
1793 | } | |
1794 | ||
1795 | restart_ih: | |
1796 | /* display interrupts */ | |
1797 | evergreen_irq_ack(rdev, &disp_int, &disp_int_cont, &disp_int_cont2, | |
1798 | &disp_int_cont3, &disp_int_cont4, &disp_int_cont5); | |
1799 | ||
1800 | rdev->ih.wptr = wptr; | |
1801 | while (rptr != wptr) { | |
1802 | /* wptr/rptr are in bytes! */ | |
1803 | ring_index = rptr / 4; | |
1804 | src_id = rdev->ih.ring[ring_index] & 0xff; | |
1805 | src_data = rdev->ih.ring[ring_index + 1] & 0xfffffff; | |
1806 | ||
1807 | switch (src_id) { | |
1808 | case 1: /* D1 vblank/vline */ | |
1809 | switch (src_data) { | |
1810 | case 0: /* D1 vblank */ | |
1811 | if (disp_int & LB_D1_VBLANK_INTERRUPT) { | |
1812 | drm_handle_vblank(rdev->ddev, 0); | |
1813 | wake_up(&rdev->irq.vblank_queue); | |
1814 | disp_int &= ~LB_D1_VBLANK_INTERRUPT; | |
1815 | DRM_DEBUG("IH: D1 vblank\n"); | |
1816 | } | |
1817 | break; | |
1818 | case 1: /* D1 vline */ | |
1819 | if (disp_int & LB_D1_VLINE_INTERRUPT) { | |
1820 | disp_int &= ~LB_D1_VLINE_INTERRUPT; | |
1821 | DRM_DEBUG("IH: D1 vline\n"); | |
1822 | } | |
1823 | break; | |
1824 | default: | |
1825 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); | |
1826 | break; | |
1827 | } | |
1828 | break; | |
1829 | case 2: /* D2 vblank/vline */ | |
1830 | switch (src_data) { | |
1831 | case 0: /* D2 vblank */ | |
1832 | if (disp_int_cont & LB_D2_VBLANK_INTERRUPT) { | |
1833 | drm_handle_vblank(rdev->ddev, 1); | |
1834 | wake_up(&rdev->irq.vblank_queue); | |
1835 | disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT; | |
1836 | DRM_DEBUG("IH: D2 vblank\n"); | |
1837 | } | |
1838 | break; | |
1839 | case 1: /* D2 vline */ | |
1840 | if (disp_int_cont & LB_D2_VLINE_INTERRUPT) { | |
1841 | disp_int_cont &= ~LB_D2_VLINE_INTERRUPT; | |
1842 | DRM_DEBUG("IH: D2 vline\n"); | |
1843 | } | |
1844 | break; | |
1845 | default: | |
1846 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); | |
1847 | break; | |
1848 | } | |
1849 | break; | |
1850 | case 3: /* D3 vblank/vline */ | |
1851 | switch (src_data) { | |
1852 | case 0: /* D3 vblank */ | |
1853 | if (disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) { | |
1854 | drm_handle_vblank(rdev->ddev, 2); | |
1855 | wake_up(&rdev->irq.vblank_queue); | |
1856 | disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT; | |
1857 | DRM_DEBUG("IH: D3 vblank\n"); | |
1858 | } | |
1859 | break; | |
1860 | case 1: /* D3 vline */ | |
1861 | if (disp_int_cont2 & LB_D3_VLINE_INTERRUPT) { | |
1862 | disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT; | |
1863 | DRM_DEBUG("IH: D3 vline\n"); | |
1864 | } | |
1865 | break; | |
1866 | default: | |
1867 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); | |
1868 | break; | |
1869 | } | |
1870 | break; | |
1871 | case 4: /* D4 vblank/vline */ | |
1872 | switch (src_data) { | |
1873 | case 0: /* D4 vblank */ | |
1874 | if (disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) { | |
1875 | drm_handle_vblank(rdev->ddev, 3); | |
1876 | wake_up(&rdev->irq.vblank_queue); | |
1877 | disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT; | |
1878 | DRM_DEBUG("IH: D4 vblank\n"); | |
1879 | } | |
1880 | break; | |
1881 | case 1: /* D4 vline */ | |
1882 | if (disp_int_cont3 & LB_D4_VLINE_INTERRUPT) { | |
1883 | disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT; | |
1884 | DRM_DEBUG("IH: D4 vline\n"); | |
1885 | } | |
1886 | break; | |
1887 | default: | |
1888 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); | |
1889 | break; | |
1890 | } | |
1891 | break; | |
1892 | case 5: /* D5 vblank/vline */ | |
1893 | switch (src_data) { | |
1894 | case 0: /* D5 vblank */ | |
1895 | if (disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) { | |
1896 | drm_handle_vblank(rdev->ddev, 4); | |
1897 | wake_up(&rdev->irq.vblank_queue); | |
1898 | disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT; | |
1899 | DRM_DEBUG("IH: D5 vblank\n"); | |
1900 | } | |
1901 | break; | |
1902 | case 1: /* D5 vline */ | |
1903 | if (disp_int_cont4 & LB_D5_VLINE_INTERRUPT) { | |
1904 | disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT; | |
1905 | DRM_DEBUG("IH: D5 vline\n"); | |
1906 | } | |
1907 | break; | |
1908 | default: | |
1909 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); | |
1910 | break; | |
1911 | } | |
1912 | break; | |
1913 | case 6: /* D6 vblank/vline */ | |
1914 | switch (src_data) { | |
1915 | case 0: /* D6 vblank */ | |
1916 | if (disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) { | |
1917 | drm_handle_vblank(rdev->ddev, 5); | |
1918 | wake_up(&rdev->irq.vblank_queue); | |
1919 | disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT; | |
1920 | DRM_DEBUG("IH: D6 vblank\n"); | |
1921 | } | |
1922 | break; | |
1923 | case 1: /* D6 vline */ | |
1924 | if (disp_int_cont5 & LB_D6_VLINE_INTERRUPT) { | |
1925 | disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT; | |
1926 | DRM_DEBUG("IH: D6 vline\n"); | |
1927 | } | |
1928 | break; | |
1929 | default: | |
1930 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); | |
1931 | break; | |
1932 | } | |
1933 | break; | |
1934 | case 42: /* HPD hotplug */ | |
1935 | switch (src_data) { | |
1936 | case 0: | |
1937 | if (disp_int & DC_HPD1_INTERRUPT) { | |
1938 | disp_int &= ~DC_HPD1_INTERRUPT; | |
1939 | queue_hotplug = true; | |
1940 | DRM_DEBUG("IH: HPD1\n"); | |
1941 | } | |
1942 | break; | |
1943 | case 1: | |
1944 | if (disp_int_cont & DC_HPD2_INTERRUPT) { | |
1945 | disp_int_cont &= ~DC_HPD2_INTERRUPT; | |
1946 | queue_hotplug = true; | |
1947 | DRM_DEBUG("IH: HPD2\n"); | |
1948 | } | |
1949 | break; | |
1950 | case 2: | |
1951 | if (disp_int_cont2 & DC_HPD3_INTERRUPT) { | |
1952 | disp_int_cont2 &= ~DC_HPD3_INTERRUPT; | |
1953 | queue_hotplug = true; | |
1954 | DRM_DEBUG("IH: HPD3\n"); | |
1955 | } | |
1956 | break; | |
1957 | case 3: | |
1958 | if (disp_int_cont3 & DC_HPD4_INTERRUPT) { | |
1959 | disp_int_cont3 &= ~DC_HPD4_INTERRUPT; | |
1960 | queue_hotplug = true; | |
1961 | DRM_DEBUG("IH: HPD4\n"); | |
1962 | } | |
1963 | break; | |
1964 | case 4: | |
1965 | if (disp_int_cont4 & DC_HPD5_INTERRUPT) { | |
1966 | disp_int_cont4 &= ~DC_HPD5_INTERRUPT; | |
1967 | queue_hotplug = true; | |
1968 | DRM_DEBUG("IH: HPD5\n"); | |
1969 | } | |
1970 | break; | |
1971 | case 5: | |
1972 | if (disp_int_cont5 & DC_HPD6_INTERRUPT) { | |
1973 | disp_int_cont5 &= ~DC_HPD6_INTERRUPT; | |
1974 | queue_hotplug = true; | |
1975 | DRM_DEBUG("IH: HPD6\n"); | |
1976 | } | |
1977 | break; | |
1978 | default: | |
1979 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); | |
1980 | break; | |
1981 | } | |
1982 | break; | |
1983 | case 176: /* CP_INT in ring buffer */ | |
1984 | case 177: /* CP_INT in IB1 */ | |
1985 | case 178: /* CP_INT in IB2 */ | |
1986 | DRM_DEBUG("IH: CP int: 0x%08x\n", src_data); | |
1987 | radeon_fence_process(rdev); | |
1988 | break; | |
1989 | case 181: /* CP EOP event */ | |
1990 | DRM_DEBUG("IH: CP EOP\n"); | |
1991 | break; | |
2031f77c AD |
1992 | case 233: /* GUI IDLE */ |
1993 | DRM_DEBUG("IH: CP EOP\n"); | |
1994 | rdev->pm.gui_idle = true; | |
1995 | wake_up(&rdev->irq.idle_queue); | |
1996 | break; | |
45f9a39b AD |
1997 | default: |
1998 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); | |
1999 | break; | |
2000 | } | |
2001 | ||
2002 | /* wptr/rptr are in bytes! */ | |
2003 | rptr += 16; | |
2004 | rptr &= rdev->ih.ptr_mask; | |
2005 | } | |
2006 | /* make sure wptr hasn't changed while processing */ | |
2007 | wptr = evergreen_get_ih_wptr(rdev); | |
2008 | if (wptr != rdev->ih.wptr) | |
2009 | goto restart_ih; | |
2010 | if (queue_hotplug) | |
2011 | queue_work(rdev->wq, &rdev->hotplug_work); | |
2012 | rdev->ih.rptr = rptr; | |
2013 | WREG32(IH_RB_RPTR, rdev->ih.rptr); | |
2014 | spin_unlock_irqrestore(&rdev->ih.lock, flags); | |
2015 | return IRQ_HANDLED; | |
2016 | } | |
2017 | ||
bcc1c2a1 AD |
2018 | static int evergreen_startup(struct radeon_device *rdev) |
2019 | { | |
bcc1c2a1 AD |
2020 | int r; |
2021 | ||
2022 | if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) { | |
2023 | r = r600_init_microcode(rdev); | |
2024 | if (r) { | |
2025 | DRM_ERROR("Failed to load firmware!\n"); | |
2026 | return r; | |
2027 | } | |
2028 | } | |
fe251e2f | 2029 | |
bcc1c2a1 | 2030 | evergreen_mc_program(rdev); |
bcc1c2a1 | 2031 | if (rdev->flags & RADEON_IS_AGP) { |
0fcdb61e | 2032 | evergreen_agp_enable(rdev); |
bcc1c2a1 AD |
2033 | } else { |
2034 | r = evergreen_pcie_gart_enable(rdev); | |
2035 | if (r) | |
2036 | return r; | |
2037 | } | |
bcc1c2a1 AD |
2038 | evergreen_gpu_init(rdev); |
2039 | #if 0 | |
2040 | if (!rdev->r600_blit.shader_obj) { | |
2041 | r = r600_blit_init(rdev); | |
2042 | if (r) { | |
2043 | DRM_ERROR("radeon: failed blitter (%d).\n", r); | |
2044 | return r; | |
2045 | } | |
2046 | } | |
2047 | ||
2048 | r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false); | |
2049 | if (unlikely(r != 0)) | |
2050 | return r; | |
2051 | r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM, | |
2052 | &rdev->r600_blit.shader_gpu_addr); | |
2053 | radeon_bo_unreserve(rdev->r600_blit.shader_obj); | |
2054 | if (r) { | |
2055 | DRM_ERROR("failed to pin blit object %d\n", r); | |
2056 | return r; | |
2057 | } | |
45f9a39b | 2058 | #endif |
bcc1c2a1 AD |
2059 | |
2060 | /* Enable IRQ */ | |
2061 | r = r600_irq_init(rdev); | |
2062 | if (r) { | |
2063 | DRM_ERROR("radeon: IH init failed (%d).\n", r); | |
2064 | radeon_irq_kms_fini(rdev); | |
2065 | return r; | |
2066 | } | |
45f9a39b | 2067 | evergreen_irq_set(rdev); |
bcc1c2a1 AD |
2068 | |
2069 | r = radeon_ring_init(rdev, rdev->cp.ring_size); | |
2070 | if (r) | |
2071 | return r; | |
2072 | r = evergreen_cp_load_microcode(rdev); | |
2073 | if (r) | |
2074 | return r; | |
fe251e2f | 2075 | r = evergreen_cp_resume(rdev); |
bcc1c2a1 AD |
2076 | if (r) |
2077 | return r; | |
2078 | /* write back buffer are not vital so don't worry about failure */ | |
2079 | r600_wb_enable(rdev); | |
fe251e2f | 2080 | |
bcc1c2a1 AD |
2081 | return 0; |
2082 | } | |
2083 | ||
2084 | int evergreen_resume(struct radeon_device *rdev) | |
2085 | { | |
2086 | int r; | |
2087 | ||
2088 | /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw, | |
2089 | * posting will perform necessary task to bring back GPU into good | |
2090 | * shape. | |
2091 | */ | |
2092 | /* post card */ | |
2093 | atom_asic_init(rdev->mode_info.atom_context); | |
bcc1c2a1 AD |
2094 | |
2095 | r = evergreen_startup(rdev); | |
2096 | if (r) { | |
2097 | DRM_ERROR("r600 startup failed on resume\n"); | |
2098 | return r; | |
2099 | } | |
fe251e2f | 2100 | |
bcc1c2a1 AD |
2101 | r = r600_ib_test(rdev); |
2102 | if (r) { | |
2103 | DRM_ERROR("radeon: failled testing IB (%d).\n", r); | |
2104 | return r; | |
2105 | } | |
fe251e2f | 2106 | |
bcc1c2a1 AD |
2107 | return r; |
2108 | ||
2109 | } | |
2110 | ||
2111 | int evergreen_suspend(struct radeon_device *rdev) | |
2112 | { | |
2113 | #if 0 | |
2114 | int r; | |
fe251e2f | 2115 | #endif |
bcc1c2a1 AD |
2116 | /* FIXME: we should wait for ring to be empty */ |
2117 | r700_cp_stop(rdev); | |
2118 | rdev->cp.ready = false; | |
45f9a39b | 2119 | evergreen_irq_suspend(rdev); |
bcc1c2a1 AD |
2120 | r600_wb_disable(rdev); |
2121 | evergreen_pcie_gart_disable(rdev); | |
0fcdb61e | 2122 | #if 0 |
bcc1c2a1 AD |
2123 | /* unpin shaders bo */ |
2124 | r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false); | |
2125 | if (likely(r == 0)) { | |
2126 | radeon_bo_unpin(rdev->r600_blit.shader_obj); | |
2127 | radeon_bo_unreserve(rdev->r600_blit.shader_obj); | |
2128 | } | |
2129 | #endif | |
2130 | return 0; | |
2131 | } | |
2132 | ||
2133 | static bool evergreen_card_posted(struct radeon_device *rdev) | |
2134 | { | |
2135 | u32 reg; | |
2136 | ||
2137 | /* first check CRTCs */ | |
2138 | reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) | | |
2139 | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) | | |
2140 | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) | | |
2141 | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) | | |
2142 | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) | | |
2143 | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET); | |
2144 | if (reg & EVERGREEN_CRTC_MASTER_EN) | |
2145 | return true; | |
2146 | ||
2147 | /* then check MEM_SIZE, in case the crtcs are off */ | |
2148 | if (RREG32(CONFIG_MEMSIZE)) | |
2149 | return true; | |
2150 | ||
2151 | return false; | |
2152 | } | |
2153 | ||
2154 | /* Plan is to move initialization in that function and use | |
2155 | * helper function so that radeon_device_init pretty much | |
2156 | * do nothing more than calling asic specific function. This | |
2157 | * should also allow to remove a bunch of callback function | |
2158 | * like vram_info. | |
2159 | */ | |
2160 | int evergreen_init(struct radeon_device *rdev) | |
2161 | { | |
2162 | int r; | |
2163 | ||
2164 | r = radeon_dummy_page_init(rdev); | |
2165 | if (r) | |
2166 | return r; | |
2167 | /* This don't do much */ | |
2168 | r = radeon_gem_init(rdev); | |
2169 | if (r) | |
2170 | return r; | |
2171 | /* Read BIOS */ | |
2172 | if (!radeon_get_bios(rdev)) { | |
2173 | if (ASIC_IS_AVIVO(rdev)) | |
2174 | return -EINVAL; | |
2175 | } | |
2176 | /* Must be an ATOMBIOS */ | |
2177 | if (!rdev->is_atom_bios) { | |
2178 | dev_err(rdev->dev, "Expecting atombios for R600 GPU\n"); | |
2179 | return -EINVAL; | |
2180 | } | |
2181 | r = radeon_atombios_init(rdev); | |
2182 | if (r) | |
2183 | return r; | |
2184 | /* Post card if necessary */ | |
2185 | if (!evergreen_card_posted(rdev)) { | |
2186 | if (!rdev->bios) { | |
2187 | dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); | |
2188 | return -EINVAL; | |
2189 | } | |
2190 | DRM_INFO("GPU not posted. posting now...\n"); | |
2191 | atom_asic_init(rdev->mode_info.atom_context); | |
2192 | } | |
2193 | /* Initialize scratch registers */ | |
2194 | r600_scratch_init(rdev); | |
2195 | /* Initialize surface registers */ | |
2196 | radeon_surface_init(rdev); | |
2197 | /* Initialize clocks */ | |
2198 | radeon_get_clock_info(rdev->ddev); | |
bcc1c2a1 AD |
2199 | /* Fence driver */ |
2200 | r = radeon_fence_driver_init(rdev); | |
2201 | if (r) | |
2202 | return r; | |
d594e46a JG |
2203 | /* initialize AGP */ |
2204 | if (rdev->flags & RADEON_IS_AGP) { | |
2205 | r = radeon_agp_init(rdev); | |
2206 | if (r) | |
2207 | radeon_agp_disable(rdev); | |
2208 | } | |
2209 | /* initialize memory controller */ | |
bcc1c2a1 AD |
2210 | r = evergreen_mc_init(rdev); |
2211 | if (r) | |
2212 | return r; | |
2213 | /* Memory manager */ | |
2214 | r = radeon_bo_init(rdev); | |
2215 | if (r) | |
2216 | return r; | |
45f9a39b | 2217 | |
bcc1c2a1 AD |
2218 | r = radeon_irq_kms_init(rdev); |
2219 | if (r) | |
2220 | return r; | |
2221 | ||
2222 | rdev->cp.ring_obj = NULL; | |
2223 | r600_ring_init(rdev, 1024 * 1024); | |
2224 | ||
2225 | rdev->ih.ring_obj = NULL; | |
2226 | r600_ih_ring_init(rdev, 64 * 1024); | |
2227 | ||
2228 | r = r600_pcie_gart_init(rdev); | |
2229 | if (r) | |
2230 | return r; | |
0fcdb61e | 2231 | |
148a03bc | 2232 | rdev->accel_working = true; |
bcc1c2a1 AD |
2233 | r = evergreen_startup(rdev); |
2234 | if (r) { | |
fe251e2f AD |
2235 | dev_err(rdev->dev, "disabling GPU acceleration\n"); |
2236 | r700_cp_fini(rdev); | |
2237 | r600_wb_fini(rdev); | |
fe251e2f AD |
2238 | r600_irq_fini(rdev); |
2239 | radeon_irq_kms_fini(rdev); | |
0fcdb61e | 2240 | evergreen_pcie_gart_fini(rdev); |
bcc1c2a1 AD |
2241 | rdev->accel_working = false; |
2242 | } | |
2243 | if (rdev->accel_working) { | |
2244 | r = radeon_ib_pool_init(rdev); | |
2245 | if (r) { | |
2246 | DRM_ERROR("radeon: failed initializing IB pool (%d).\n", r); | |
2247 | rdev->accel_working = false; | |
2248 | } | |
2249 | r = r600_ib_test(rdev); | |
2250 | if (r) { | |
2251 | DRM_ERROR("radeon: failed testing IB (%d).\n", r); | |
2252 | rdev->accel_working = false; | |
2253 | } | |
2254 | } | |
2255 | return 0; | |
2256 | } | |
2257 | ||
2258 | void evergreen_fini(struct radeon_device *rdev) | |
2259 | { | |
45f9a39b AD |
2260 | /*r600_blit_fini(rdev);*/ |
2261 | r700_cp_fini(rdev); | |
2262 | r600_wb_fini(rdev); | |
bcc1c2a1 AD |
2263 | r600_irq_fini(rdev); |
2264 | radeon_irq_kms_fini(rdev); | |
bcc1c2a1 | 2265 | evergreen_pcie_gart_fini(rdev); |
bcc1c2a1 AD |
2266 | radeon_gem_fini(rdev); |
2267 | radeon_fence_driver_fini(rdev); | |
bcc1c2a1 AD |
2268 | radeon_agp_fini(rdev); |
2269 | radeon_bo_fini(rdev); | |
2270 | radeon_atombios_fini(rdev); | |
2271 | kfree(rdev->bios); | |
2272 | rdev->bios = NULL; | |
2273 | radeon_dummy_page_fini(rdev); | |
2274 | } |