Commit | Line | Data |
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bcc1c2a1 AD |
1 | /* |
2 | * Copyright 2010 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Alex Deucher | |
23 | */ | |
24 | #include <linux/firmware.h> | |
25 | #include <linux/platform_device.h> | |
5a0e3ad6 | 26 | #include <linux/slab.h> |
bcc1c2a1 AD |
27 | #include "drmP.h" |
28 | #include "radeon.h" | |
e6990375 | 29 | #include "radeon_asic.h" |
bcc1c2a1 | 30 | #include "radeon_drm.h" |
0fcdb61e | 31 | #include "evergreend.h" |
bcc1c2a1 AD |
32 | #include "atom.h" |
33 | #include "avivod.h" | |
34 | #include "evergreen_reg.h" | |
2281a378 | 35 | #include "evergreen_blit_shaders.h" |
bcc1c2a1 | 36 | |
fe251e2f AD |
37 | #define EVERGREEN_PFP_UCODE_SIZE 1120 |
38 | #define EVERGREEN_PM4_UCODE_SIZE 1376 | |
39 | ||
bcc1c2a1 AD |
40 | static void evergreen_gpu_init(struct radeon_device *rdev); |
41 | void evergreen_fini(struct radeon_device *rdev); | |
b07759bf | 42 | void evergreen_pcie_gen2_enable(struct radeon_device *rdev); |
bcc1c2a1 | 43 | |
d054ac16 AD |
44 | void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev) |
45 | { | |
46 | u16 ctl, v; | |
47 | int cap, err; | |
48 | ||
49 | cap = pci_pcie_cap(rdev->pdev); | |
50 | if (!cap) | |
51 | return; | |
52 | ||
53 | err = pci_read_config_word(rdev->pdev, cap + PCI_EXP_DEVCTL, &ctl); | |
54 | if (err) | |
55 | return; | |
56 | ||
57 | v = (ctl & PCI_EXP_DEVCTL_READRQ) >> 12; | |
58 | ||
59 | /* if bios or OS sets MAX_READ_REQUEST_SIZE to an invalid value, fix it | |
60 | * to avoid hangs or perfomance issues | |
61 | */ | |
62 | if ((v == 0) || (v == 6) || (v == 7)) { | |
63 | ctl &= ~PCI_EXP_DEVCTL_READRQ; | |
64 | ctl |= (2 << 12); | |
65 | pci_write_config_word(rdev->pdev, cap + PCI_EXP_DEVCTL, ctl); | |
66 | } | |
67 | } | |
68 | ||
6f34be50 AD |
69 | void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc) |
70 | { | |
6f34be50 AD |
71 | /* enable the pflip int */ |
72 | radeon_irq_kms_pflip_irq_get(rdev, crtc); | |
73 | } | |
74 | ||
75 | void evergreen_post_page_flip(struct radeon_device *rdev, int crtc) | |
76 | { | |
77 | /* disable the pflip int */ | |
78 | radeon_irq_kms_pflip_irq_put(rdev, crtc); | |
79 | } | |
80 | ||
81 | u32 evergreen_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base) | |
82 | { | |
83 | struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; | |
84 | u32 tmp = RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset); | |
f6496479 | 85 | int i; |
6f34be50 AD |
86 | |
87 | /* Lock the graphics update lock */ | |
88 | tmp |= EVERGREEN_GRPH_UPDATE_LOCK; | |
89 | WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); | |
90 | ||
91 | /* update the scanout addresses */ | |
92 | WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, | |
93 | upper_32_bits(crtc_base)); | |
94 | WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, | |
95 | (u32)crtc_base); | |
96 | ||
97 | WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, | |
98 | upper_32_bits(crtc_base)); | |
99 | WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, | |
100 | (u32)crtc_base); | |
101 | ||
102 | /* Wait for update_pending to go high. */ | |
f6496479 AD |
103 | for (i = 0; i < rdev->usec_timeout; i++) { |
104 | if (RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING) | |
105 | break; | |
106 | udelay(1); | |
107 | } | |
6f34be50 AD |
108 | DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n"); |
109 | ||
110 | /* Unlock the lock, so double-buffering can take place inside vblank */ | |
111 | tmp &= ~EVERGREEN_GRPH_UPDATE_LOCK; | |
112 | WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); | |
113 | ||
114 | /* Return current update_pending status: */ | |
115 | return RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING; | |
116 | } | |
117 | ||
21a8122a | 118 | /* get temperature in millidegrees */ |
20d391d7 | 119 | int evergreen_get_temp(struct radeon_device *rdev) |
21a8122a | 120 | { |
1c88d74f AD |
121 | u32 temp, toffset; |
122 | int actual_temp = 0; | |
67b3f823 AD |
123 | |
124 | if (rdev->family == CHIP_JUNIPER) { | |
125 | toffset = (RREG32(CG_THERMAL_CTRL) & TOFFSET_MASK) >> | |
126 | TOFFSET_SHIFT; | |
127 | temp = (RREG32(CG_TS0_STATUS) & TS0_ADC_DOUT_MASK) >> | |
128 | TS0_ADC_DOUT_SHIFT; | |
129 | ||
130 | if (toffset & 0x100) | |
131 | actual_temp = temp / 2 - (0x200 - toffset); | |
132 | else | |
133 | actual_temp = temp / 2 + toffset; | |
134 | ||
135 | actual_temp = actual_temp * 1000; | |
136 | ||
137 | } else { | |
138 | temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >> | |
139 | ASIC_T_SHIFT; | |
140 | ||
141 | if (temp & 0x400) | |
142 | actual_temp = -256; | |
143 | else if (temp & 0x200) | |
144 | actual_temp = 255; | |
145 | else if (temp & 0x100) { | |
146 | actual_temp = temp & 0x1ff; | |
147 | actual_temp |= ~0x1ff; | |
148 | } else | |
149 | actual_temp = temp & 0xff; | |
150 | ||
151 | actual_temp = (actual_temp * 1000) / 2; | |
152 | } | |
21a8122a | 153 | |
67b3f823 | 154 | return actual_temp; |
21a8122a AD |
155 | } |
156 | ||
20d391d7 | 157 | int sumo_get_temp(struct radeon_device *rdev) |
e33df25f AD |
158 | { |
159 | u32 temp = RREG32(CG_THERMAL_STATUS) & 0xff; | |
20d391d7 | 160 | int actual_temp = temp - 49; |
e33df25f AD |
161 | |
162 | return actual_temp * 1000; | |
163 | } | |
164 | ||
a4c9e2ee AD |
165 | void sumo_pm_init_profile(struct radeon_device *rdev) |
166 | { | |
167 | int idx; | |
168 | ||
169 | /* default */ | |
170 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; | |
171 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; | |
172 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; | |
173 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; | |
174 | ||
175 | /* low,mid sh/mh */ | |
176 | if (rdev->flags & RADEON_IS_MOBILITY) | |
177 | idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0); | |
178 | else | |
179 | idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0); | |
180 | ||
181 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx; | |
182 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx; | |
183 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; | |
184 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; | |
185 | ||
186 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx; | |
187 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx; | |
188 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; | |
189 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; | |
190 | ||
191 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx; | |
192 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx; | |
193 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; | |
194 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; | |
195 | ||
196 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx; | |
197 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx; | |
198 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; | |
199 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; | |
200 | ||
201 | /* high sh/mh */ | |
202 | idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0); | |
203 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx; | |
204 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx; | |
205 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; | |
206 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = | |
207 | rdev->pm.power_state[idx].num_clock_modes - 1; | |
208 | ||
209 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx; | |
210 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx; | |
211 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; | |
212 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = | |
213 | rdev->pm.power_state[idx].num_clock_modes - 1; | |
214 | } | |
215 | ||
49e02b73 AD |
216 | void evergreen_pm_misc(struct radeon_device *rdev) |
217 | { | |
a081a9d6 RM |
218 | int req_ps_idx = rdev->pm.requested_power_state_index; |
219 | int req_cm_idx = rdev->pm.requested_clock_mode_index; | |
220 | struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx]; | |
221 | struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage; | |
49e02b73 | 222 | |
2feea49a | 223 | if (voltage->type == VOLTAGE_SW) { |
a377e187 AD |
224 | /* 0xff01 is a flag rather then an actual voltage */ |
225 | if (voltage->voltage == 0xff01) | |
226 | return; | |
2feea49a | 227 | if (voltage->voltage && (voltage->voltage != rdev->pm.current_vddc)) { |
8a83ec5e | 228 | radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC); |
4d60173f | 229 | rdev->pm.current_vddc = voltage->voltage; |
2feea49a AD |
230 | DRM_DEBUG("Setting: vddc: %d\n", voltage->voltage); |
231 | } | |
a377e187 AD |
232 | /* 0xff01 is a flag rather then an actual voltage */ |
233 | if (voltage->vddci == 0xff01) | |
234 | return; | |
2feea49a AD |
235 | if (voltage->vddci && (voltage->vddci != rdev->pm.current_vddci)) { |
236 | radeon_atom_set_voltage(rdev, voltage->vddci, SET_VOLTAGE_TYPE_ASIC_VDDCI); | |
237 | rdev->pm.current_vddci = voltage->vddci; | |
238 | DRM_DEBUG("Setting: vddci: %d\n", voltage->vddci); | |
4d60173f AD |
239 | } |
240 | } | |
49e02b73 AD |
241 | } |
242 | ||
243 | void evergreen_pm_prepare(struct radeon_device *rdev) | |
244 | { | |
245 | struct drm_device *ddev = rdev->ddev; | |
246 | struct drm_crtc *crtc; | |
247 | struct radeon_crtc *radeon_crtc; | |
248 | u32 tmp; | |
249 | ||
250 | /* disable any active CRTCs */ | |
251 | list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) { | |
252 | radeon_crtc = to_radeon_crtc(crtc); | |
253 | if (radeon_crtc->enabled) { | |
254 | tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset); | |
255 | tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE; | |
256 | WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp); | |
257 | } | |
258 | } | |
259 | } | |
260 | ||
261 | void evergreen_pm_finish(struct radeon_device *rdev) | |
262 | { | |
263 | struct drm_device *ddev = rdev->ddev; | |
264 | struct drm_crtc *crtc; | |
265 | struct radeon_crtc *radeon_crtc; | |
266 | u32 tmp; | |
267 | ||
268 | /* enable any active CRTCs */ | |
269 | list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) { | |
270 | radeon_crtc = to_radeon_crtc(crtc); | |
271 | if (radeon_crtc->enabled) { | |
272 | tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset); | |
273 | tmp &= ~EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE; | |
274 | WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp); | |
275 | } | |
276 | } | |
277 | } | |
278 | ||
bcc1c2a1 AD |
279 | bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) |
280 | { | |
281 | bool connected = false; | |
0ca2ab52 AD |
282 | |
283 | switch (hpd) { | |
284 | case RADEON_HPD_1: | |
285 | if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE) | |
286 | connected = true; | |
287 | break; | |
288 | case RADEON_HPD_2: | |
289 | if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE) | |
290 | connected = true; | |
291 | break; | |
292 | case RADEON_HPD_3: | |
293 | if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE) | |
294 | connected = true; | |
295 | break; | |
296 | case RADEON_HPD_4: | |
297 | if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE) | |
298 | connected = true; | |
299 | break; | |
300 | case RADEON_HPD_5: | |
301 | if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE) | |
302 | connected = true; | |
303 | break; | |
304 | case RADEON_HPD_6: | |
305 | if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE) | |
306 | connected = true; | |
307 | break; | |
308 | default: | |
309 | break; | |
310 | } | |
311 | ||
bcc1c2a1 AD |
312 | return connected; |
313 | } | |
314 | ||
315 | void evergreen_hpd_set_polarity(struct radeon_device *rdev, | |
316 | enum radeon_hpd_id hpd) | |
317 | { | |
0ca2ab52 AD |
318 | u32 tmp; |
319 | bool connected = evergreen_hpd_sense(rdev, hpd); | |
320 | ||
321 | switch (hpd) { | |
322 | case RADEON_HPD_1: | |
323 | tmp = RREG32(DC_HPD1_INT_CONTROL); | |
324 | if (connected) | |
325 | tmp &= ~DC_HPDx_INT_POLARITY; | |
326 | else | |
327 | tmp |= DC_HPDx_INT_POLARITY; | |
328 | WREG32(DC_HPD1_INT_CONTROL, tmp); | |
329 | break; | |
330 | case RADEON_HPD_2: | |
331 | tmp = RREG32(DC_HPD2_INT_CONTROL); | |
332 | if (connected) | |
333 | tmp &= ~DC_HPDx_INT_POLARITY; | |
334 | else | |
335 | tmp |= DC_HPDx_INT_POLARITY; | |
336 | WREG32(DC_HPD2_INT_CONTROL, tmp); | |
337 | break; | |
338 | case RADEON_HPD_3: | |
339 | tmp = RREG32(DC_HPD3_INT_CONTROL); | |
340 | if (connected) | |
341 | tmp &= ~DC_HPDx_INT_POLARITY; | |
342 | else | |
343 | tmp |= DC_HPDx_INT_POLARITY; | |
344 | WREG32(DC_HPD3_INT_CONTROL, tmp); | |
345 | break; | |
346 | case RADEON_HPD_4: | |
347 | tmp = RREG32(DC_HPD4_INT_CONTROL); | |
348 | if (connected) | |
349 | tmp &= ~DC_HPDx_INT_POLARITY; | |
350 | else | |
351 | tmp |= DC_HPDx_INT_POLARITY; | |
352 | WREG32(DC_HPD4_INT_CONTROL, tmp); | |
353 | break; | |
354 | case RADEON_HPD_5: | |
355 | tmp = RREG32(DC_HPD5_INT_CONTROL); | |
356 | if (connected) | |
357 | tmp &= ~DC_HPDx_INT_POLARITY; | |
358 | else | |
359 | tmp |= DC_HPDx_INT_POLARITY; | |
360 | WREG32(DC_HPD5_INT_CONTROL, tmp); | |
361 | break; | |
362 | case RADEON_HPD_6: | |
363 | tmp = RREG32(DC_HPD6_INT_CONTROL); | |
364 | if (connected) | |
365 | tmp &= ~DC_HPDx_INT_POLARITY; | |
366 | else | |
367 | tmp |= DC_HPDx_INT_POLARITY; | |
368 | WREG32(DC_HPD6_INT_CONTROL, tmp); | |
369 | break; | |
370 | default: | |
371 | break; | |
372 | } | |
bcc1c2a1 AD |
373 | } |
374 | ||
375 | void evergreen_hpd_init(struct radeon_device *rdev) | |
376 | { | |
0ca2ab52 AD |
377 | struct drm_device *dev = rdev->ddev; |
378 | struct drm_connector *connector; | |
379 | u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | | |
380 | DC_HPDx_RX_INT_TIMER(0xfa) | DC_HPDx_EN; | |
bcc1c2a1 | 381 | |
0ca2ab52 AD |
382 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
383 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
384 | switch (radeon_connector->hpd.hpd) { | |
385 | case RADEON_HPD_1: | |
386 | WREG32(DC_HPD1_CONTROL, tmp); | |
387 | rdev->irq.hpd[0] = true; | |
388 | break; | |
389 | case RADEON_HPD_2: | |
390 | WREG32(DC_HPD2_CONTROL, tmp); | |
391 | rdev->irq.hpd[1] = true; | |
392 | break; | |
393 | case RADEON_HPD_3: | |
394 | WREG32(DC_HPD3_CONTROL, tmp); | |
395 | rdev->irq.hpd[2] = true; | |
396 | break; | |
397 | case RADEON_HPD_4: | |
398 | WREG32(DC_HPD4_CONTROL, tmp); | |
399 | rdev->irq.hpd[3] = true; | |
400 | break; | |
401 | case RADEON_HPD_5: | |
402 | WREG32(DC_HPD5_CONTROL, tmp); | |
403 | rdev->irq.hpd[4] = true; | |
404 | break; | |
405 | case RADEON_HPD_6: | |
406 | WREG32(DC_HPD6_CONTROL, tmp); | |
407 | rdev->irq.hpd[5] = true; | |
408 | break; | |
409 | default: | |
410 | break; | |
411 | } | |
64912e99 | 412 | radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd); |
0ca2ab52 AD |
413 | } |
414 | if (rdev->irq.installed) | |
415 | evergreen_irq_set(rdev); | |
bcc1c2a1 AD |
416 | } |
417 | ||
0ca2ab52 | 418 | void evergreen_hpd_fini(struct radeon_device *rdev) |
bcc1c2a1 | 419 | { |
0ca2ab52 AD |
420 | struct drm_device *dev = rdev->ddev; |
421 | struct drm_connector *connector; | |
422 | ||
423 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
424 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
425 | switch (radeon_connector->hpd.hpd) { | |
426 | case RADEON_HPD_1: | |
427 | WREG32(DC_HPD1_CONTROL, 0); | |
428 | rdev->irq.hpd[0] = false; | |
429 | break; | |
430 | case RADEON_HPD_2: | |
431 | WREG32(DC_HPD2_CONTROL, 0); | |
432 | rdev->irq.hpd[1] = false; | |
433 | break; | |
434 | case RADEON_HPD_3: | |
435 | WREG32(DC_HPD3_CONTROL, 0); | |
436 | rdev->irq.hpd[2] = false; | |
437 | break; | |
438 | case RADEON_HPD_4: | |
439 | WREG32(DC_HPD4_CONTROL, 0); | |
440 | rdev->irq.hpd[3] = false; | |
441 | break; | |
442 | case RADEON_HPD_5: | |
443 | WREG32(DC_HPD5_CONTROL, 0); | |
444 | rdev->irq.hpd[4] = false; | |
445 | break; | |
446 | case RADEON_HPD_6: | |
447 | WREG32(DC_HPD6_CONTROL, 0); | |
448 | rdev->irq.hpd[5] = false; | |
449 | break; | |
450 | default: | |
451 | break; | |
452 | } | |
453 | } | |
bcc1c2a1 AD |
454 | } |
455 | ||
f9d9c362 AD |
456 | /* watermark setup */ |
457 | ||
458 | static u32 evergreen_line_buffer_adjust(struct radeon_device *rdev, | |
459 | struct radeon_crtc *radeon_crtc, | |
460 | struct drm_display_mode *mode, | |
461 | struct drm_display_mode *other_mode) | |
462 | { | |
12dfc843 | 463 | u32 tmp; |
f9d9c362 AD |
464 | /* |
465 | * Line Buffer Setup | |
466 | * There are 3 line buffers, each one shared by 2 display controllers. | |
467 | * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between | |
468 | * the display controllers. The paritioning is done via one of four | |
469 | * preset allocations specified in bits 2:0: | |
470 | * first display controller | |
471 | * 0 - first half of lb (3840 * 2) | |
472 | * 1 - first 3/4 of lb (5760 * 2) | |
12dfc843 | 473 | * 2 - whole lb (7680 * 2), other crtc must be disabled |
f9d9c362 AD |
474 | * 3 - first 1/4 of lb (1920 * 2) |
475 | * second display controller | |
476 | * 4 - second half of lb (3840 * 2) | |
477 | * 5 - second 3/4 of lb (5760 * 2) | |
12dfc843 | 478 | * 6 - whole lb (7680 * 2), other crtc must be disabled |
f9d9c362 AD |
479 | * 7 - last 1/4 of lb (1920 * 2) |
480 | */ | |
12dfc843 AD |
481 | /* this can get tricky if we have two large displays on a paired group |
482 | * of crtcs. Ideally for multiple large displays we'd assign them to | |
483 | * non-linked crtcs for maximum line buffer allocation. | |
484 | */ | |
485 | if (radeon_crtc->base.enabled && mode) { | |
486 | if (other_mode) | |
f9d9c362 | 487 | tmp = 0; /* 1/2 */ |
12dfc843 AD |
488 | else |
489 | tmp = 2; /* whole */ | |
490 | } else | |
491 | tmp = 0; | |
f9d9c362 AD |
492 | |
493 | /* second controller of the pair uses second half of the lb */ | |
494 | if (radeon_crtc->crtc_id % 2) | |
495 | tmp += 4; | |
496 | WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, tmp); | |
497 | ||
12dfc843 AD |
498 | if (radeon_crtc->base.enabled && mode) { |
499 | switch (tmp) { | |
500 | case 0: | |
501 | case 4: | |
502 | default: | |
503 | if (ASIC_IS_DCE5(rdev)) | |
504 | return 4096 * 2; | |
505 | else | |
506 | return 3840 * 2; | |
507 | case 1: | |
508 | case 5: | |
509 | if (ASIC_IS_DCE5(rdev)) | |
510 | return 6144 * 2; | |
511 | else | |
512 | return 5760 * 2; | |
513 | case 2: | |
514 | case 6: | |
515 | if (ASIC_IS_DCE5(rdev)) | |
516 | return 8192 * 2; | |
517 | else | |
518 | return 7680 * 2; | |
519 | case 3: | |
520 | case 7: | |
521 | if (ASIC_IS_DCE5(rdev)) | |
522 | return 2048 * 2; | |
523 | else | |
524 | return 1920 * 2; | |
525 | } | |
f9d9c362 | 526 | } |
12dfc843 AD |
527 | |
528 | /* controller not enabled, so no lb used */ | |
529 | return 0; | |
f9d9c362 AD |
530 | } |
531 | ||
532 | static u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev) | |
533 | { | |
534 | u32 tmp = RREG32(MC_SHARED_CHMAP); | |
535 | ||
536 | switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) { | |
537 | case 0: | |
538 | default: | |
539 | return 1; | |
540 | case 1: | |
541 | return 2; | |
542 | case 2: | |
543 | return 4; | |
544 | case 3: | |
545 | return 8; | |
546 | } | |
547 | } | |
548 | ||
549 | struct evergreen_wm_params { | |
550 | u32 dram_channels; /* number of dram channels */ | |
551 | u32 yclk; /* bandwidth per dram data pin in kHz */ | |
552 | u32 sclk; /* engine clock in kHz */ | |
553 | u32 disp_clk; /* display clock in kHz */ | |
554 | u32 src_width; /* viewport width */ | |
555 | u32 active_time; /* active display time in ns */ | |
556 | u32 blank_time; /* blank time in ns */ | |
557 | bool interlaced; /* mode is interlaced */ | |
558 | fixed20_12 vsc; /* vertical scale ratio */ | |
559 | u32 num_heads; /* number of active crtcs */ | |
560 | u32 bytes_per_pixel; /* bytes per pixel display + overlay */ | |
561 | u32 lb_size; /* line buffer allocated to pipe */ | |
562 | u32 vtaps; /* vertical scaler taps */ | |
563 | }; | |
564 | ||
565 | static u32 evergreen_dram_bandwidth(struct evergreen_wm_params *wm) | |
566 | { | |
567 | /* Calculate DRAM Bandwidth and the part allocated to display. */ | |
568 | fixed20_12 dram_efficiency; /* 0.7 */ | |
569 | fixed20_12 yclk, dram_channels, bandwidth; | |
570 | fixed20_12 a; | |
571 | ||
572 | a.full = dfixed_const(1000); | |
573 | yclk.full = dfixed_const(wm->yclk); | |
574 | yclk.full = dfixed_div(yclk, a); | |
575 | dram_channels.full = dfixed_const(wm->dram_channels * 4); | |
576 | a.full = dfixed_const(10); | |
577 | dram_efficiency.full = dfixed_const(7); | |
578 | dram_efficiency.full = dfixed_div(dram_efficiency, a); | |
579 | bandwidth.full = dfixed_mul(dram_channels, yclk); | |
580 | bandwidth.full = dfixed_mul(bandwidth, dram_efficiency); | |
581 | ||
582 | return dfixed_trunc(bandwidth); | |
583 | } | |
584 | ||
585 | static u32 evergreen_dram_bandwidth_for_display(struct evergreen_wm_params *wm) | |
586 | { | |
587 | /* Calculate DRAM Bandwidth and the part allocated to display. */ | |
588 | fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */ | |
589 | fixed20_12 yclk, dram_channels, bandwidth; | |
590 | fixed20_12 a; | |
591 | ||
592 | a.full = dfixed_const(1000); | |
593 | yclk.full = dfixed_const(wm->yclk); | |
594 | yclk.full = dfixed_div(yclk, a); | |
595 | dram_channels.full = dfixed_const(wm->dram_channels * 4); | |
596 | a.full = dfixed_const(10); | |
597 | disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */ | |
598 | disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a); | |
599 | bandwidth.full = dfixed_mul(dram_channels, yclk); | |
600 | bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation); | |
601 | ||
602 | return dfixed_trunc(bandwidth); | |
603 | } | |
604 | ||
605 | static u32 evergreen_data_return_bandwidth(struct evergreen_wm_params *wm) | |
606 | { | |
607 | /* Calculate the display Data return Bandwidth */ | |
608 | fixed20_12 return_efficiency; /* 0.8 */ | |
609 | fixed20_12 sclk, bandwidth; | |
610 | fixed20_12 a; | |
611 | ||
612 | a.full = dfixed_const(1000); | |
613 | sclk.full = dfixed_const(wm->sclk); | |
614 | sclk.full = dfixed_div(sclk, a); | |
615 | a.full = dfixed_const(10); | |
616 | return_efficiency.full = dfixed_const(8); | |
617 | return_efficiency.full = dfixed_div(return_efficiency, a); | |
618 | a.full = dfixed_const(32); | |
619 | bandwidth.full = dfixed_mul(a, sclk); | |
620 | bandwidth.full = dfixed_mul(bandwidth, return_efficiency); | |
621 | ||
622 | return dfixed_trunc(bandwidth); | |
623 | } | |
624 | ||
625 | static u32 evergreen_dmif_request_bandwidth(struct evergreen_wm_params *wm) | |
626 | { | |
627 | /* Calculate the DMIF Request Bandwidth */ | |
628 | fixed20_12 disp_clk_request_efficiency; /* 0.8 */ | |
629 | fixed20_12 disp_clk, bandwidth; | |
630 | fixed20_12 a; | |
631 | ||
632 | a.full = dfixed_const(1000); | |
633 | disp_clk.full = dfixed_const(wm->disp_clk); | |
634 | disp_clk.full = dfixed_div(disp_clk, a); | |
635 | a.full = dfixed_const(10); | |
636 | disp_clk_request_efficiency.full = dfixed_const(8); | |
637 | disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a); | |
638 | a.full = dfixed_const(32); | |
639 | bandwidth.full = dfixed_mul(a, disp_clk); | |
640 | bandwidth.full = dfixed_mul(bandwidth, disp_clk_request_efficiency); | |
641 | ||
642 | return dfixed_trunc(bandwidth); | |
643 | } | |
644 | ||
645 | static u32 evergreen_available_bandwidth(struct evergreen_wm_params *wm) | |
646 | { | |
647 | /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */ | |
648 | u32 dram_bandwidth = evergreen_dram_bandwidth(wm); | |
649 | u32 data_return_bandwidth = evergreen_data_return_bandwidth(wm); | |
650 | u32 dmif_req_bandwidth = evergreen_dmif_request_bandwidth(wm); | |
651 | ||
652 | return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth)); | |
653 | } | |
654 | ||
655 | static u32 evergreen_average_bandwidth(struct evergreen_wm_params *wm) | |
656 | { | |
657 | /* Calculate the display mode Average Bandwidth | |
658 | * DisplayMode should contain the source and destination dimensions, | |
659 | * timing, etc. | |
660 | */ | |
661 | fixed20_12 bpp; | |
662 | fixed20_12 line_time; | |
663 | fixed20_12 src_width; | |
664 | fixed20_12 bandwidth; | |
665 | fixed20_12 a; | |
666 | ||
667 | a.full = dfixed_const(1000); | |
668 | line_time.full = dfixed_const(wm->active_time + wm->blank_time); | |
669 | line_time.full = dfixed_div(line_time, a); | |
670 | bpp.full = dfixed_const(wm->bytes_per_pixel); | |
671 | src_width.full = dfixed_const(wm->src_width); | |
672 | bandwidth.full = dfixed_mul(src_width, bpp); | |
673 | bandwidth.full = dfixed_mul(bandwidth, wm->vsc); | |
674 | bandwidth.full = dfixed_div(bandwidth, line_time); | |
675 | ||
676 | return dfixed_trunc(bandwidth); | |
677 | } | |
678 | ||
679 | static u32 evergreen_latency_watermark(struct evergreen_wm_params *wm) | |
680 | { | |
681 | /* First calcualte the latency in ns */ | |
682 | u32 mc_latency = 2000; /* 2000 ns. */ | |
683 | u32 available_bandwidth = evergreen_available_bandwidth(wm); | |
684 | u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth; | |
685 | u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth; | |
686 | u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */ | |
687 | u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) + | |
688 | (wm->num_heads * cursor_line_pair_return_time); | |
689 | u32 latency = mc_latency + other_heads_data_return_time + dc_latency; | |
690 | u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time; | |
691 | fixed20_12 a, b, c; | |
692 | ||
693 | if (wm->num_heads == 0) | |
694 | return 0; | |
695 | ||
696 | a.full = dfixed_const(2); | |
697 | b.full = dfixed_const(1); | |
698 | if ((wm->vsc.full > a.full) || | |
699 | ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) || | |
700 | (wm->vtaps >= 5) || | |
701 | ((wm->vsc.full >= a.full) && wm->interlaced)) | |
702 | max_src_lines_per_dst_line = 4; | |
703 | else | |
704 | max_src_lines_per_dst_line = 2; | |
705 | ||
706 | a.full = dfixed_const(available_bandwidth); | |
707 | b.full = dfixed_const(wm->num_heads); | |
708 | a.full = dfixed_div(a, b); | |
709 | ||
710 | b.full = dfixed_const(1000); | |
711 | c.full = dfixed_const(wm->disp_clk); | |
712 | b.full = dfixed_div(c, b); | |
713 | c.full = dfixed_const(wm->bytes_per_pixel); | |
714 | b.full = dfixed_mul(b, c); | |
715 | ||
716 | lb_fill_bw = min(dfixed_trunc(a), dfixed_trunc(b)); | |
717 | ||
718 | a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel); | |
719 | b.full = dfixed_const(1000); | |
720 | c.full = dfixed_const(lb_fill_bw); | |
721 | b.full = dfixed_div(c, b); | |
722 | a.full = dfixed_div(a, b); | |
723 | line_fill_time = dfixed_trunc(a); | |
724 | ||
725 | if (line_fill_time < wm->active_time) | |
726 | return latency; | |
727 | else | |
728 | return latency + (line_fill_time - wm->active_time); | |
729 | ||
730 | } | |
731 | ||
732 | static bool evergreen_average_bandwidth_vs_dram_bandwidth_for_display(struct evergreen_wm_params *wm) | |
733 | { | |
734 | if (evergreen_average_bandwidth(wm) <= | |
735 | (evergreen_dram_bandwidth_for_display(wm) / wm->num_heads)) | |
736 | return true; | |
737 | else | |
738 | return false; | |
739 | }; | |
740 | ||
741 | static bool evergreen_average_bandwidth_vs_available_bandwidth(struct evergreen_wm_params *wm) | |
742 | { | |
743 | if (evergreen_average_bandwidth(wm) <= | |
744 | (evergreen_available_bandwidth(wm) / wm->num_heads)) | |
745 | return true; | |
746 | else | |
747 | return false; | |
748 | }; | |
749 | ||
750 | static bool evergreen_check_latency_hiding(struct evergreen_wm_params *wm) | |
751 | { | |
752 | u32 lb_partitions = wm->lb_size / wm->src_width; | |
753 | u32 line_time = wm->active_time + wm->blank_time; | |
754 | u32 latency_tolerant_lines; | |
755 | u32 latency_hiding; | |
756 | fixed20_12 a; | |
757 | ||
758 | a.full = dfixed_const(1); | |
759 | if (wm->vsc.full > a.full) | |
760 | latency_tolerant_lines = 1; | |
761 | else { | |
762 | if (lb_partitions <= (wm->vtaps + 1)) | |
763 | latency_tolerant_lines = 1; | |
764 | else | |
765 | latency_tolerant_lines = 2; | |
766 | } | |
767 | ||
768 | latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time); | |
769 | ||
770 | if (evergreen_latency_watermark(wm) <= latency_hiding) | |
771 | return true; | |
772 | else | |
773 | return false; | |
774 | } | |
775 | ||
776 | static void evergreen_program_watermarks(struct radeon_device *rdev, | |
777 | struct radeon_crtc *radeon_crtc, | |
778 | u32 lb_size, u32 num_heads) | |
779 | { | |
780 | struct drm_display_mode *mode = &radeon_crtc->base.mode; | |
781 | struct evergreen_wm_params wm; | |
782 | u32 pixel_period; | |
783 | u32 line_time = 0; | |
784 | u32 latency_watermark_a = 0, latency_watermark_b = 0; | |
785 | u32 priority_a_mark = 0, priority_b_mark = 0; | |
786 | u32 priority_a_cnt = PRIORITY_OFF; | |
787 | u32 priority_b_cnt = PRIORITY_OFF; | |
788 | u32 pipe_offset = radeon_crtc->crtc_id * 16; | |
789 | u32 tmp, arb_control3; | |
790 | fixed20_12 a, b, c; | |
791 | ||
792 | if (radeon_crtc->base.enabled && num_heads && mode) { | |
793 | pixel_period = 1000000 / (u32)mode->clock; | |
794 | line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535); | |
795 | priority_a_cnt = 0; | |
796 | priority_b_cnt = 0; | |
797 | ||
798 | wm.yclk = rdev->pm.current_mclk * 10; | |
799 | wm.sclk = rdev->pm.current_sclk * 10; | |
800 | wm.disp_clk = mode->clock; | |
801 | wm.src_width = mode->crtc_hdisplay; | |
802 | wm.active_time = mode->crtc_hdisplay * pixel_period; | |
803 | wm.blank_time = line_time - wm.active_time; | |
804 | wm.interlaced = false; | |
805 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) | |
806 | wm.interlaced = true; | |
807 | wm.vsc = radeon_crtc->vsc; | |
808 | wm.vtaps = 1; | |
809 | if (radeon_crtc->rmx_type != RMX_OFF) | |
810 | wm.vtaps = 2; | |
811 | wm.bytes_per_pixel = 4; /* XXX: get this from fb config */ | |
812 | wm.lb_size = lb_size; | |
813 | wm.dram_channels = evergreen_get_number_of_dram_channels(rdev); | |
814 | wm.num_heads = num_heads; | |
815 | ||
816 | /* set for high clocks */ | |
817 | latency_watermark_a = min(evergreen_latency_watermark(&wm), (u32)65535); | |
818 | /* set for low clocks */ | |
819 | /* wm.yclk = low clk; wm.sclk = low clk */ | |
820 | latency_watermark_b = min(evergreen_latency_watermark(&wm), (u32)65535); | |
821 | ||
822 | /* possibly force display priority to high */ | |
823 | /* should really do this at mode validation time... */ | |
824 | if (!evergreen_average_bandwidth_vs_dram_bandwidth_for_display(&wm) || | |
825 | !evergreen_average_bandwidth_vs_available_bandwidth(&wm) || | |
826 | !evergreen_check_latency_hiding(&wm) || | |
827 | (rdev->disp_priority == 2)) { | |
92bdfd4a | 828 | DRM_DEBUG_KMS("force priority to high\n"); |
f9d9c362 AD |
829 | priority_a_cnt |= PRIORITY_ALWAYS_ON; |
830 | priority_b_cnt |= PRIORITY_ALWAYS_ON; | |
831 | } | |
832 | ||
833 | a.full = dfixed_const(1000); | |
834 | b.full = dfixed_const(mode->clock); | |
835 | b.full = dfixed_div(b, a); | |
836 | c.full = dfixed_const(latency_watermark_a); | |
837 | c.full = dfixed_mul(c, b); | |
838 | c.full = dfixed_mul(c, radeon_crtc->hsc); | |
839 | c.full = dfixed_div(c, a); | |
840 | a.full = dfixed_const(16); | |
841 | c.full = dfixed_div(c, a); | |
842 | priority_a_mark = dfixed_trunc(c); | |
843 | priority_a_cnt |= priority_a_mark & PRIORITY_MARK_MASK; | |
844 | ||
845 | a.full = dfixed_const(1000); | |
846 | b.full = dfixed_const(mode->clock); | |
847 | b.full = dfixed_div(b, a); | |
848 | c.full = dfixed_const(latency_watermark_b); | |
849 | c.full = dfixed_mul(c, b); | |
850 | c.full = dfixed_mul(c, radeon_crtc->hsc); | |
851 | c.full = dfixed_div(c, a); | |
852 | a.full = dfixed_const(16); | |
853 | c.full = dfixed_div(c, a); | |
854 | priority_b_mark = dfixed_trunc(c); | |
855 | priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK; | |
856 | } | |
857 | ||
858 | /* select wm A */ | |
859 | arb_control3 = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset); | |
860 | tmp = arb_control3; | |
861 | tmp &= ~LATENCY_WATERMARK_MASK(3); | |
862 | tmp |= LATENCY_WATERMARK_MASK(1); | |
863 | WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp); | |
864 | WREG32(PIPE0_LATENCY_CONTROL + pipe_offset, | |
865 | (LATENCY_LOW_WATERMARK(latency_watermark_a) | | |
866 | LATENCY_HIGH_WATERMARK(line_time))); | |
867 | /* select wm B */ | |
868 | tmp = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset); | |
869 | tmp &= ~LATENCY_WATERMARK_MASK(3); | |
870 | tmp |= LATENCY_WATERMARK_MASK(2); | |
871 | WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp); | |
872 | WREG32(PIPE0_LATENCY_CONTROL + pipe_offset, | |
873 | (LATENCY_LOW_WATERMARK(latency_watermark_b) | | |
874 | LATENCY_HIGH_WATERMARK(line_time))); | |
875 | /* restore original selection */ | |
876 | WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, arb_control3); | |
877 | ||
878 | /* write the priority marks */ | |
879 | WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt); | |
880 | WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt); | |
881 | ||
882 | } | |
883 | ||
0ca2ab52 | 884 | void evergreen_bandwidth_update(struct radeon_device *rdev) |
bcc1c2a1 | 885 | { |
f9d9c362 AD |
886 | struct drm_display_mode *mode0 = NULL; |
887 | struct drm_display_mode *mode1 = NULL; | |
888 | u32 num_heads = 0, lb_size; | |
889 | int i; | |
890 | ||
891 | radeon_update_display_priority(rdev); | |
892 | ||
893 | for (i = 0; i < rdev->num_crtc; i++) { | |
894 | if (rdev->mode_info.crtcs[i]->base.enabled) | |
895 | num_heads++; | |
896 | } | |
897 | for (i = 0; i < rdev->num_crtc; i += 2) { | |
898 | mode0 = &rdev->mode_info.crtcs[i]->base.mode; | |
899 | mode1 = &rdev->mode_info.crtcs[i+1]->base.mode; | |
900 | lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode0, mode1); | |
901 | evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i], lb_size, num_heads); | |
902 | lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i+1], mode1, mode0); | |
903 | evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i+1], lb_size, num_heads); | |
904 | } | |
bcc1c2a1 AD |
905 | } |
906 | ||
b9952a8a | 907 | int evergreen_mc_wait_for_idle(struct radeon_device *rdev) |
bcc1c2a1 AD |
908 | { |
909 | unsigned i; | |
910 | u32 tmp; | |
911 | ||
912 | for (i = 0; i < rdev->usec_timeout; i++) { | |
913 | /* read MC_STATUS */ | |
914 | tmp = RREG32(SRBM_STATUS) & 0x1F00; | |
915 | if (!tmp) | |
916 | return 0; | |
917 | udelay(1); | |
918 | } | |
919 | return -1; | |
920 | } | |
921 | ||
922 | /* | |
923 | * GART | |
924 | */ | |
0fcdb61e AD |
925 | void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev) |
926 | { | |
927 | unsigned i; | |
928 | u32 tmp; | |
929 | ||
6f2f48a9 AD |
930 | WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); |
931 | ||
0fcdb61e AD |
932 | WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1)); |
933 | for (i = 0; i < rdev->usec_timeout; i++) { | |
934 | /* read MC_STATUS */ | |
935 | tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE); | |
936 | tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT; | |
937 | if (tmp == 2) { | |
938 | printk(KERN_WARNING "[drm] r600 flush TLB failed\n"); | |
939 | return; | |
940 | } | |
941 | if (tmp) { | |
942 | return; | |
943 | } | |
944 | udelay(1); | |
945 | } | |
946 | } | |
947 | ||
bcc1c2a1 AD |
948 | int evergreen_pcie_gart_enable(struct radeon_device *rdev) |
949 | { | |
950 | u32 tmp; | |
0fcdb61e | 951 | int r; |
bcc1c2a1 | 952 | |
c9a1be96 | 953 | if (rdev->gart.robj == NULL) { |
bcc1c2a1 AD |
954 | dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); |
955 | return -EINVAL; | |
956 | } | |
957 | r = radeon_gart_table_vram_pin(rdev); | |
958 | if (r) | |
959 | return r; | |
82568565 | 960 | radeon_gart_restore(rdev); |
bcc1c2a1 AD |
961 | /* Setup L2 cache */ |
962 | WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | | |
963 | ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | | |
964 | EFFECTIVE_L2_QUEUE_SIZE(7)); | |
965 | WREG32(VM_L2_CNTL2, 0); | |
966 | WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); | |
967 | /* Setup TLB control */ | |
968 | tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | | |
969 | SYSTEM_ACCESS_MODE_NOT_IN_SYS | | |
970 | SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU | | |
971 | EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5); | |
8aeb96f8 AD |
972 | if (rdev->flags & RADEON_IS_IGP) { |
973 | WREG32(FUS_MC_VM_MD_L1_TLB0_CNTL, tmp); | |
974 | WREG32(FUS_MC_VM_MD_L1_TLB1_CNTL, tmp); | |
975 | WREG32(FUS_MC_VM_MD_L1_TLB2_CNTL, tmp); | |
976 | } else { | |
977 | WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); | |
978 | WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); | |
979 | WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); | |
980 | } | |
bcc1c2a1 AD |
981 | WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); |
982 | WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); | |
983 | WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); | |
984 | WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); | |
985 | WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); | |
986 | WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); | |
987 | WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); | |
988 | WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | | |
989 | RANGE_PROTECTION_FAULT_ENABLE_DEFAULT); | |
990 | WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, | |
991 | (u32)(rdev->dummy_page.addr >> 12)); | |
0fcdb61e | 992 | WREG32(VM_CONTEXT1_CNTL, 0); |
bcc1c2a1 | 993 | |
0fcdb61e | 994 | evergreen_pcie_gart_tlb_flush(rdev); |
fcf4de5a TV |
995 | DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", |
996 | (unsigned)(rdev->mc.gtt_size >> 20), | |
997 | (unsigned long long)rdev->gart.table_addr); | |
bcc1c2a1 AD |
998 | rdev->gart.ready = true; |
999 | return 0; | |
1000 | } | |
1001 | ||
1002 | void evergreen_pcie_gart_disable(struct radeon_device *rdev) | |
1003 | { | |
1004 | u32 tmp; | |
bcc1c2a1 AD |
1005 | |
1006 | /* Disable all tables */ | |
0fcdb61e AD |
1007 | WREG32(VM_CONTEXT0_CNTL, 0); |
1008 | WREG32(VM_CONTEXT1_CNTL, 0); | |
bcc1c2a1 AD |
1009 | |
1010 | /* Setup L2 cache */ | |
1011 | WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING | | |
1012 | EFFECTIVE_L2_QUEUE_SIZE(7)); | |
1013 | WREG32(VM_L2_CNTL2, 0); | |
1014 | WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); | |
1015 | /* Setup TLB control */ | |
1016 | tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5); | |
1017 | WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); | |
1018 | WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); | |
1019 | WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); | |
1020 | WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); | |
1021 | WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); | |
1022 | WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); | |
1023 | WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); | |
c9a1be96 | 1024 | radeon_gart_table_vram_unpin(rdev); |
bcc1c2a1 AD |
1025 | } |
1026 | ||
1027 | void evergreen_pcie_gart_fini(struct radeon_device *rdev) | |
1028 | { | |
1029 | evergreen_pcie_gart_disable(rdev); | |
1030 | radeon_gart_table_vram_free(rdev); | |
1031 | radeon_gart_fini(rdev); | |
1032 | } | |
1033 | ||
1034 | ||
1035 | void evergreen_agp_enable(struct radeon_device *rdev) | |
1036 | { | |
1037 | u32 tmp; | |
bcc1c2a1 AD |
1038 | |
1039 | /* Setup L2 cache */ | |
1040 | WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | | |
1041 | ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | | |
1042 | EFFECTIVE_L2_QUEUE_SIZE(7)); | |
1043 | WREG32(VM_L2_CNTL2, 0); | |
1044 | WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); | |
1045 | /* Setup TLB control */ | |
1046 | tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | | |
1047 | SYSTEM_ACCESS_MODE_NOT_IN_SYS | | |
1048 | SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU | | |
1049 | EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5); | |
1050 | WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); | |
1051 | WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); | |
1052 | WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); | |
1053 | WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); | |
1054 | WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); | |
1055 | WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); | |
1056 | WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); | |
0fcdb61e AD |
1057 | WREG32(VM_CONTEXT0_CNTL, 0); |
1058 | WREG32(VM_CONTEXT1_CNTL, 0); | |
bcc1c2a1 AD |
1059 | } |
1060 | ||
b9952a8a | 1061 | void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save) |
bcc1c2a1 AD |
1062 | { |
1063 | save->vga_control[0] = RREG32(D1VGA_CONTROL); | |
1064 | save->vga_control[1] = RREG32(D2VGA_CONTROL); | |
bcc1c2a1 AD |
1065 | save->vga_render_control = RREG32(VGA_RENDER_CONTROL); |
1066 | save->vga_hdp_control = RREG32(VGA_HDP_CONTROL); | |
1067 | save->crtc_control[0] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET); | |
1068 | save->crtc_control[1] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET); | |
b7eff394 AD |
1069 | if (rdev->num_crtc >= 4) { |
1070 | save->vga_control[2] = RREG32(EVERGREEN_D3VGA_CONTROL); | |
1071 | save->vga_control[3] = RREG32(EVERGREEN_D4VGA_CONTROL); | |
18007401 AD |
1072 | save->crtc_control[2] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET); |
1073 | save->crtc_control[3] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET); | |
b7eff394 AD |
1074 | } |
1075 | if (rdev->num_crtc >= 6) { | |
1076 | save->vga_control[4] = RREG32(EVERGREEN_D5VGA_CONTROL); | |
1077 | save->vga_control[5] = RREG32(EVERGREEN_D6VGA_CONTROL); | |
18007401 AD |
1078 | save->crtc_control[4] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET); |
1079 | save->crtc_control[5] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET); | |
1080 | } | |
bcc1c2a1 AD |
1081 | |
1082 | /* Stop all video */ | |
1083 | WREG32(VGA_RENDER_CONTROL, 0); | |
1084 | WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1); | |
1085 | WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1); | |
b7eff394 | 1086 | if (rdev->num_crtc >= 4) { |
18007401 AD |
1087 | WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1); |
1088 | WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1); | |
b7eff394 AD |
1089 | } |
1090 | if (rdev->num_crtc >= 6) { | |
18007401 AD |
1091 | WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1); |
1092 | WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1); | |
1093 | } | |
bcc1c2a1 AD |
1094 | WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); |
1095 | WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); | |
b7eff394 | 1096 | if (rdev->num_crtc >= 4) { |
18007401 AD |
1097 | WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); |
1098 | WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); | |
b7eff394 AD |
1099 | } |
1100 | if (rdev->num_crtc >= 6) { | |
18007401 AD |
1101 | WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); |
1102 | WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); | |
1103 | } | |
bcc1c2a1 AD |
1104 | WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); |
1105 | WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); | |
b7eff394 | 1106 | if (rdev->num_crtc >= 4) { |
18007401 AD |
1107 | WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); |
1108 | WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); | |
b7eff394 AD |
1109 | } |
1110 | if (rdev->num_crtc >= 6) { | |
18007401 AD |
1111 | WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); |
1112 | WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); | |
1113 | } | |
bcc1c2a1 AD |
1114 | |
1115 | WREG32(D1VGA_CONTROL, 0); | |
1116 | WREG32(D2VGA_CONTROL, 0); | |
b7eff394 AD |
1117 | if (rdev->num_crtc >= 4) { |
1118 | WREG32(EVERGREEN_D3VGA_CONTROL, 0); | |
1119 | WREG32(EVERGREEN_D4VGA_CONTROL, 0); | |
1120 | } | |
1121 | if (rdev->num_crtc >= 6) { | |
1122 | WREG32(EVERGREEN_D5VGA_CONTROL, 0); | |
1123 | WREG32(EVERGREEN_D6VGA_CONTROL, 0); | |
1124 | } | |
bcc1c2a1 AD |
1125 | } |
1126 | ||
b9952a8a | 1127 | void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save) |
bcc1c2a1 AD |
1128 | { |
1129 | WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET, | |
1130 | upper_32_bits(rdev->mc.vram_start)); | |
1131 | WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET, | |
1132 | upper_32_bits(rdev->mc.vram_start)); | |
1133 | WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC0_REGISTER_OFFSET, | |
1134 | (u32)rdev->mc.vram_start); | |
1135 | WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC0_REGISTER_OFFSET, | |
1136 | (u32)rdev->mc.vram_start); | |
1137 | ||
1138 | WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET, | |
1139 | upper_32_bits(rdev->mc.vram_start)); | |
1140 | WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET, | |
1141 | upper_32_bits(rdev->mc.vram_start)); | |
1142 | WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET, | |
1143 | (u32)rdev->mc.vram_start); | |
1144 | WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET, | |
1145 | (u32)rdev->mc.vram_start); | |
1146 | ||
b7eff394 | 1147 | if (rdev->num_crtc >= 4) { |
18007401 AD |
1148 | WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET, |
1149 | upper_32_bits(rdev->mc.vram_start)); | |
1150 | WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET, | |
1151 | upper_32_bits(rdev->mc.vram_start)); | |
1152 | WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET, | |
1153 | (u32)rdev->mc.vram_start); | |
1154 | WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET, | |
1155 | (u32)rdev->mc.vram_start); | |
1156 | ||
1157 | WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET, | |
1158 | upper_32_bits(rdev->mc.vram_start)); | |
1159 | WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET, | |
1160 | upper_32_bits(rdev->mc.vram_start)); | |
1161 | WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET, | |
1162 | (u32)rdev->mc.vram_start); | |
1163 | WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET, | |
1164 | (u32)rdev->mc.vram_start); | |
b7eff394 AD |
1165 | } |
1166 | if (rdev->num_crtc >= 6) { | |
18007401 AD |
1167 | WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET, |
1168 | upper_32_bits(rdev->mc.vram_start)); | |
1169 | WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET, | |
1170 | upper_32_bits(rdev->mc.vram_start)); | |
1171 | WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET, | |
1172 | (u32)rdev->mc.vram_start); | |
1173 | WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET, | |
1174 | (u32)rdev->mc.vram_start); | |
1175 | ||
1176 | WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET, | |
1177 | upper_32_bits(rdev->mc.vram_start)); | |
1178 | WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET, | |
1179 | upper_32_bits(rdev->mc.vram_start)); | |
1180 | WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET, | |
1181 | (u32)rdev->mc.vram_start); | |
1182 | WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET, | |
1183 | (u32)rdev->mc.vram_start); | |
1184 | } | |
bcc1c2a1 AD |
1185 | |
1186 | WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start)); | |
1187 | WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start); | |
1188 | /* Unlock host access */ | |
1189 | WREG32(VGA_HDP_CONTROL, save->vga_hdp_control); | |
1190 | mdelay(1); | |
1191 | /* Restore video state */ | |
1192 | WREG32(D1VGA_CONTROL, save->vga_control[0]); | |
1193 | WREG32(D2VGA_CONTROL, save->vga_control[1]); | |
b7eff394 AD |
1194 | if (rdev->num_crtc >= 4) { |
1195 | WREG32(EVERGREEN_D3VGA_CONTROL, save->vga_control[2]); | |
1196 | WREG32(EVERGREEN_D4VGA_CONTROL, save->vga_control[3]); | |
1197 | } | |
1198 | if (rdev->num_crtc >= 6) { | |
1199 | WREG32(EVERGREEN_D5VGA_CONTROL, save->vga_control[4]); | |
1200 | WREG32(EVERGREEN_D6VGA_CONTROL, save->vga_control[5]); | |
1201 | } | |
bcc1c2a1 AD |
1202 | WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1); |
1203 | WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1); | |
b7eff394 | 1204 | if (rdev->num_crtc >= 4) { |
18007401 AD |
1205 | WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1); |
1206 | WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1); | |
b7eff394 AD |
1207 | } |
1208 | if (rdev->num_crtc >= 6) { | |
18007401 AD |
1209 | WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1); |
1210 | WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1); | |
1211 | } | |
bcc1c2a1 AD |
1212 | WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, save->crtc_control[0]); |
1213 | WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, save->crtc_control[1]); | |
b7eff394 | 1214 | if (rdev->num_crtc >= 4) { |
18007401 AD |
1215 | WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, save->crtc_control[2]); |
1216 | WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, save->crtc_control[3]); | |
b7eff394 AD |
1217 | } |
1218 | if (rdev->num_crtc >= 6) { | |
18007401 AD |
1219 | WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, save->crtc_control[4]); |
1220 | WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, save->crtc_control[5]); | |
1221 | } | |
bcc1c2a1 AD |
1222 | WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); |
1223 | WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); | |
b7eff394 | 1224 | if (rdev->num_crtc >= 4) { |
18007401 AD |
1225 | WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); |
1226 | WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); | |
b7eff394 AD |
1227 | } |
1228 | if (rdev->num_crtc >= 6) { | |
18007401 AD |
1229 | WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); |
1230 | WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); | |
1231 | } | |
bcc1c2a1 AD |
1232 | WREG32(VGA_RENDER_CONTROL, save->vga_render_control); |
1233 | } | |
1234 | ||
755d819e | 1235 | void evergreen_mc_program(struct radeon_device *rdev) |
bcc1c2a1 AD |
1236 | { |
1237 | struct evergreen_mc_save save; | |
1238 | u32 tmp; | |
1239 | int i, j; | |
1240 | ||
1241 | /* Initialize HDP */ | |
1242 | for (i = 0, j = 0; i < 32; i++, j += 0x18) { | |
1243 | WREG32((0x2c14 + j), 0x00000000); | |
1244 | WREG32((0x2c18 + j), 0x00000000); | |
1245 | WREG32((0x2c1c + j), 0x00000000); | |
1246 | WREG32((0x2c20 + j), 0x00000000); | |
1247 | WREG32((0x2c24 + j), 0x00000000); | |
1248 | } | |
1249 | WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0); | |
1250 | ||
1251 | evergreen_mc_stop(rdev, &save); | |
1252 | if (evergreen_mc_wait_for_idle(rdev)) { | |
1253 | dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); | |
1254 | } | |
1255 | /* Lockout access through VGA aperture*/ | |
1256 | WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE); | |
1257 | /* Update configuration */ | |
1258 | if (rdev->flags & RADEON_IS_AGP) { | |
1259 | if (rdev->mc.vram_start < rdev->mc.gtt_start) { | |
1260 | /* VRAM before AGP */ | |
1261 | WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, | |
1262 | rdev->mc.vram_start >> 12); | |
1263 | WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, | |
1264 | rdev->mc.gtt_end >> 12); | |
1265 | } else { | |
1266 | /* VRAM after AGP */ | |
1267 | WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, | |
1268 | rdev->mc.gtt_start >> 12); | |
1269 | WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, | |
1270 | rdev->mc.vram_end >> 12); | |
1271 | } | |
1272 | } else { | |
1273 | WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, | |
1274 | rdev->mc.vram_start >> 12); | |
1275 | WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, | |
1276 | rdev->mc.vram_end >> 12); | |
1277 | } | |
3b9832f6 | 1278 | WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12); |
b4183e30 AD |
1279 | if (rdev->flags & RADEON_IS_IGP) { |
1280 | tmp = RREG32(MC_FUS_VM_FB_OFFSET) & 0x000FFFFF; | |
1281 | tmp |= ((rdev->mc.vram_end >> 20) & 0xF) << 24; | |
1282 | tmp |= ((rdev->mc.vram_start >> 20) & 0xF) << 20; | |
1283 | WREG32(MC_FUS_VM_FB_OFFSET, tmp); | |
1284 | } | |
bcc1c2a1 AD |
1285 | tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16; |
1286 | tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF); | |
1287 | WREG32(MC_VM_FB_LOCATION, tmp); | |
1288 | WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); | |
c46cb4da | 1289 | WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30)); |
46fcd2b3 | 1290 | WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF); |
bcc1c2a1 AD |
1291 | if (rdev->flags & RADEON_IS_AGP) { |
1292 | WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16); | |
1293 | WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16); | |
1294 | WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22); | |
1295 | } else { | |
1296 | WREG32(MC_VM_AGP_BASE, 0); | |
1297 | WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF); | |
1298 | WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF); | |
1299 | } | |
1300 | if (evergreen_mc_wait_for_idle(rdev)) { | |
1301 | dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); | |
1302 | } | |
1303 | evergreen_mc_resume(rdev, &save); | |
1304 | /* we need to own VRAM, so turn off the VGA renderer here | |
1305 | * to stop it overwriting our objects */ | |
1306 | rv515_vga_render_disable(rdev); | |
1307 | } | |
1308 | ||
bcc1c2a1 AD |
1309 | /* |
1310 | * CP. | |
1311 | */ | |
12920591 AD |
1312 | void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) |
1313 | { | |
e32eb50d | 1314 | struct radeon_ring *ring = &rdev->ring[ib->fence->ring]; |
7b1f2485 | 1315 | |
12920591 | 1316 | /* set to DX10/11 mode */ |
e32eb50d CK |
1317 | radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0)); |
1318 | radeon_ring_write(ring, 1); | |
12920591 | 1319 | /* FIXME: implement */ |
e32eb50d CK |
1320 | radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); |
1321 | radeon_ring_write(ring, | |
0f234f5f AD |
1322 | #ifdef __BIG_ENDIAN |
1323 | (2 << 0) | | |
1324 | #endif | |
1325 | (ib->gpu_addr & 0xFFFFFFFC)); | |
e32eb50d CK |
1326 | radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF); |
1327 | radeon_ring_write(ring, ib->length_dw); | |
12920591 AD |
1328 | } |
1329 | ||
bcc1c2a1 AD |
1330 | |
1331 | static int evergreen_cp_load_microcode(struct radeon_device *rdev) | |
1332 | { | |
fe251e2f AD |
1333 | const __be32 *fw_data; |
1334 | int i; | |
1335 | ||
1336 | if (!rdev->me_fw || !rdev->pfp_fw) | |
1337 | return -EINVAL; | |
bcc1c2a1 | 1338 | |
fe251e2f | 1339 | r700_cp_stop(rdev); |
0f234f5f AD |
1340 | WREG32(CP_RB_CNTL, |
1341 | #ifdef __BIG_ENDIAN | |
1342 | BUF_SWAP_32BIT | | |
1343 | #endif | |
1344 | RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3)); | |
fe251e2f AD |
1345 | |
1346 | fw_data = (const __be32 *)rdev->pfp_fw->data; | |
1347 | WREG32(CP_PFP_UCODE_ADDR, 0); | |
1348 | for (i = 0; i < EVERGREEN_PFP_UCODE_SIZE; i++) | |
1349 | WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++)); | |
1350 | WREG32(CP_PFP_UCODE_ADDR, 0); | |
1351 | ||
1352 | fw_data = (const __be32 *)rdev->me_fw->data; | |
1353 | WREG32(CP_ME_RAM_WADDR, 0); | |
1354 | for (i = 0; i < EVERGREEN_PM4_UCODE_SIZE; i++) | |
1355 | WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++)); | |
1356 | ||
1357 | WREG32(CP_PFP_UCODE_ADDR, 0); | |
1358 | WREG32(CP_ME_RAM_WADDR, 0); | |
1359 | WREG32(CP_ME_RAM_RADDR, 0); | |
bcc1c2a1 AD |
1360 | return 0; |
1361 | } | |
1362 | ||
7e7b41d2 AD |
1363 | static int evergreen_cp_start(struct radeon_device *rdev) |
1364 | { | |
e32eb50d | 1365 | struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
2281a378 | 1366 | int r, i; |
7e7b41d2 AD |
1367 | uint32_t cp_me; |
1368 | ||
e32eb50d | 1369 | r = radeon_ring_lock(rdev, ring, 7); |
7e7b41d2 AD |
1370 | if (r) { |
1371 | DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); | |
1372 | return r; | |
1373 | } | |
e32eb50d CK |
1374 | radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5)); |
1375 | radeon_ring_write(ring, 0x1); | |
1376 | radeon_ring_write(ring, 0x0); | |
1377 | radeon_ring_write(ring, rdev->config.evergreen.max_hw_contexts - 1); | |
1378 | radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1)); | |
1379 | radeon_ring_write(ring, 0); | |
1380 | radeon_ring_write(ring, 0); | |
1381 | radeon_ring_unlock_commit(rdev, ring); | |
7e7b41d2 AD |
1382 | |
1383 | cp_me = 0xff; | |
1384 | WREG32(CP_ME_CNTL, cp_me); | |
1385 | ||
e32eb50d | 1386 | r = radeon_ring_lock(rdev, ring, evergreen_default_size + 19); |
7e7b41d2 AD |
1387 | if (r) { |
1388 | DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); | |
1389 | return r; | |
1390 | } | |
2281a378 AD |
1391 | |
1392 | /* setup clear context state */ | |
e32eb50d CK |
1393 | radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); |
1394 | radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); | |
2281a378 AD |
1395 | |
1396 | for (i = 0; i < evergreen_default_size; i++) | |
e32eb50d | 1397 | radeon_ring_write(ring, evergreen_default_state[i]); |
2281a378 | 1398 | |
e32eb50d CK |
1399 | radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); |
1400 | radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); | |
2281a378 AD |
1401 | |
1402 | /* set clear context state */ | |
e32eb50d CK |
1403 | radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); |
1404 | radeon_ring_write(ring, 0); | |
2281a378 AD |
1405 | |
1406 | /* SQ_VTX_BASE_VTX_LOC */ | |
e32eb50d CK |
1407 | radeon_ring_write(ring, 0xc0026f00); |
1408 | radeon_ring_write(ring, 0x00000000); | |
1409 | radeon_ring_write(ring, 0x00000000); | |
1410 | radeon_ring_write(ring, 0x00000000); | |
2281a378 AD |
1411 | |
1412 | /* Clear consts */ | |
e32eb50d CK |
1413 | radeon_ring_write(ring, 0xc0036f00); |
1414 | radeon_ring_write(ring, 0x00000bc4); | |
1415 | radeon_ring_write(ring, 0xffffffff); | |
1416 | radeon_ring_write(ring, 0xffffffff); | |
1417 | radeon_ring_write(ring, 0xffffffff); | |
2281a378 | 1418 | |
e32eb50d CK |
1419 | radeon_ring_write(ring, 0xc0026900); |
1420 | radeon_ring_write(ring, 0x00000316); | |
1421 | radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */ | |
1422 | radeon_ring_write(ring, 0x00000010); /* */ | |
18ff84da | 1423 | |
e32eb50d | 1424 | radeon_ring_unlock_commit(rdev, ring); |
7e7b41d2 AD |
1425 | |
1426 | return 0; | |
1427 | } | |
1428 | ||
fe251e2f AD |
1429 | int evergreen_cp_resume(struct radeon_device *rdev) |
1430 | { | |
e32eb50d | 1431 | struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
fe251e2f AD |
1432 | u32 tmp; |
1433 | u32 rb_bufsz; | |
1434 | int r; | |
1435 | ||
1436 | /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */ | |
1437 | WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP | | |
1438 | SOFT_RESET_PA | | |
1439 | SOFT_RESET_SH | | |
1440 | SOFT_RESET_VGT | | |
a49a50da | 1441 | SOFT_RESET_SPI | |
fe251e2f AD |
1442 | SOFT_RESET_SX)); |
1443 | RREG32(GRBM_SOFT_RESET); | |
1444 | mdelay(15); | |
1445 | WREG32(GRBM_SOFT_RESET, 0); | |
1446 | RREG32(GRBM_SOFT_RESET); | |
1447 | ||
1448 | /* Set ring buffer size */ | |
e32eb50d | 1449 | rb_bufsz = drm_order(ring->ring_size / 8); |
724c80e1 | 1450 | tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; |
fe251e2f AD |
1451 | #ifdef __BIG_ENDIAN |
1452 | tmp |= BUF_SWAP_32BIT; | |
32fcdbf4 | 1453 | #endif |
fe251e2f | 1454 | WREG32(CP_RB_CNTL, tmp); |
15d3332f | 1455 | WREG32(CP_SEM_WAIT_TIMER, 0x0); |
fe251e2f AD |
1456 | |
1457 | /* Set the write pointer delay */ | |
1458 | WREG32(CP_RB_WPTR_DELAY, 0); | |
1459 | ||
1460 | /* Initialize the ring buffer's read and write pointers */ | |
1461 | WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA); | |
1462 | WREG32(CP_RB_RPTR_WR, 0); | |
e32eb50d CK |
1463 | ring->wptr = 0; |
1464 | WREG32(CP_RB_WPTR, ring->wptr); | |
724c80e1 AD |
1465 | |
1466 | /* set the wb address wether it's enabled or not */ | |
0f234f5f | 1467 | WREG32(CP_RB_RPTR_ADDR, |
0f234f5f | 1468 | ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC)); |
724c80e1 AD |
1469 | WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); |
1470 | WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); | |
1471 | ||
1472 | if (rdev->wb.enabled) | |
1473 | WREG32(SCRATCH_UMSK, 0xff); | |
1474 | else { | |
1475 | tmp |= RB_NO_UPDATE; | |
1476 | WREG32(SCRATCH_UMSK, 0); | |
1477 | } | |
1478 | ||
fe251e2f AD |
1479 | mdelay(1); |
1480 | WREG32(CP_RB_CNTL, tmp); | |
1481 | ||
e32eb50d | 1482 | WREG32(CP_RB_BASE, ring->gpu_addr >> 8); |
fe251e2f AD |
1483 | WREG32(CP_DEBUG, (1 << 27) | (1 << 28)); |
1484 | ||
e32eb50d | 1485 | ring->rptr = RREG32(CP_RB_RPTR); |
fe251e2f | 1486 | |
7e7b41d2 | 1487 | evergreen_cp_start(rdev); |
e32eb50d CK |
1488 | ring->ready = true; |
1489 | r = radeon_ring_test(rdev, ring); | |
fe251e2f | 1490 | if (r) { |
e32eb50d | 1491 | ring->ready = false; |
fe251e2f AD |
1492 | return r; |
1493 | } | |
1494 | return 0; | |
1495 | } | |
bcc1c2a1 AD |
1496 | |
1497 | /* | |
1498 | * Core functions | |
1499 | */ | |
32fcdbf4 AD |
1500 | static u32 evergreen_get_tile_pipe_to_backend_map(struct radeon_device *rdev, |
1501 | u32 num_tile_pipes, | |
bcc1c2a1 AD |
1502 | u32 num_backends, |
1503 | u32 backend_disable_mask) | |
1504 | { | |
1505 | u32 backend_map = 0; | |
32fcdbf4 AD |
1506 | u32 enabled_backends_mask = 0; |
1507 | u32 enabled_backends_count = 0; | |
1508 | u32 cur_pipe; | |
1509 | u32 swizzle_pipe[EVERGREEN_MAX_PIPES]; | |
1510 | u32 cur_backend = 0; | |
1511 | u32 i; | |
1512 | bool force_no_swizzle; | |
1513 | ||
1514 | if (num_tile_pipes > EVERGREEN_MAX_PIPES) | |
1515 | num_tile_pipes = EVERGREEN_MAX_PIPES; | |
1516 | if (num_tile_pipes < 1) | |
1517 | num_tile_pipes = 1; | |
1518 | if (num_backends > EVERGREEN_MAX_BACKENDS) | |
1519 | num_backends = EVERGREEN_MAX_BACKENDS; | |
1520 | if (num_backends < 1) | |
1521 | num_backends = 1; | |
1522 | ||
1523 | for (i = 0; i < EVERGREEN_MAX_BACKENDS; ++i) { | |
1524 | if (((backend_disable_mask >> i) & 1) == 0) { | |
1525 | enabled_backends_mask |= (1 << i); | |
1526 | ++enabled_backends_count; | |
1527 | } | |
1528 | if (enabled_backends_count == num_backends) | |
1529 | break; | |
1530 | } | |
1531 | ||
1532 | if (enabled_backends_count == 0) { | |
1533 | enabled_backends_mask = 1; | |
1534 | enabled_backends_count = 1; | |
1535 | } | |
1536 | ||
1537 | if (enabled_backends_count != num_backends) | |
1538 | num_backends = enabled_backends_count; | |
1539 | ||
1540 | memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * EVERGREEN_MAX_PIPES); | |
1541 | switch (rdev->family) { | |
1542 | case CHIP_CEDAR: | |
1543 | case CHIP_REDWOOD: | |
d5e455e4 | 1544 | case CHIP_PALM: |
d5c5a72f AD |
1545 | case CHIP_SUMO: |
1546 | case CHIP_SUMO2: | |
adb68fa2 AD |
1547 | case CHIP_TURKS: |
1548 | case CHIP_CAICOS: | |
32fcdbf4 AD |
1549 | force_no_swizzle = false; |
1550 | break; | |
1551 | case CHIP_CYPRESS: | |
1552 | case CHIP_HEMLOCK: | |
1553 | case CHIP_JUNIPER: | |
adb68fa2 | 1554 | case CHIP_BARTS: |
32fcdbf4 AD |
1555 | default: |
1556 | force_no_swizzle = true; | |
1557 | break; | |
1558 | } | |
1559 | if (force_no_swizzle) { | |
1560 | bool last_backend_enabled = false; | |
1561 | ||
1562 | force_no_swizzle = false; | |
1563 | for (i = 0; i < EVERGREEN_MAX_BACKENDS; ++i) { | |
1564 | if (((enabled_backends_mask >> i) & 1) == 1) { | |
1565 | if (last_backend_enabled) | |
1566 | force_no_swizzle = true; | |
1567 | last_backend_enabled = true; | |
1568 | } else | |
1569 | last_backend_enabled = false; | |
1570 | } | |
1571 | } | |
1572 | ||
1573 | switch (num_tile_pipes) { | |
1574 | case 1: | |
1575 | case 3: | |
1576 | case 5: | |
1577 | case 7: | |
1578 | DRM_ERROR("odd number of pipes!\n"); | |
1579 | break; | |
1580 | case 2: | |
1581 | swizzle_pipe[0] = 0; | |
1582 | swizzle_pipe[1] = 1; | |
1583 | break; | |
1584 | case 4: | |
1585 | if (force_no_swizzle) { | |
1586 | swizzle_pipe[0] = 0; | |
1587 | swizzle_pipe[1] = 1; | |
1588 | swizzle_pipe[2] = 2; | |
1589 | swizzle_pipe[3] = 3; | |
1590 | } else { | |
1591 | swizzle_pipe[0] = 0; | |
1592 | swizzle_pipe[1] = 2; | |
1593 | swizzle_pipe[2] = 1; | |
1594 | swizzle_pipe[3] = 3; | |
1595 | } | |
1596 | break; | |
1597 | case 6: | |
1598 | if (force_no_swizzle) { | |
1599 | swizzle_pipe[0] = 0; | |
1600 | swizzle_pipe[1] = 1; | |
1601 | swizzle_pipe[2] = 2; | |
1602 | swizzle_pipe[3] = 3; | |
1603 | swizzle_pipe[4] = 4; | |
1604 | swizzle_pipe[5] = 5; | |
1605 | } else { | |
1606 | swizzle_pipe[0] = 0; | |
1607 | swizzle_pipe[1] = 2; | |
1608 | swizzle_pipe[2] = 4; | |
1609 | swizzle_pipe[3] = 1; | |
1610 | swizzle_pipe[4] = 3; | |
1611 | swizzle_pipe[5] = 5; | |
1612 | } | |
1613 | break; | |
1614 | case 8: | |
1615 | if (force_no_swizzle) { | |
1616 | swizzle_pipe[0] = 0; | |
1617 | swizzle_pipe[1] = 1; | |
1618 | swizzle_pipe[2] = 2; | |
1619 | swizzle_pipe[3] = 3; | |
1620 | swizzle_pipe[4] = 4; | |
1621 | swizzle_pipe[5] = 5; | |
1622 | swizzle_pipe[6] = 6; | |
1623 | swizzle_pipe[7] = 7; | |
1624 | } else { | |
1625 | swizzle_pipe[0] = 0; | |
1626 | swizzle_pipe[1] = 2; | |
1627 | swizzle_pipe[2] = 4; | |
1628 | swizzle_pipe[3] = 6; | |
1629 | swizzle_pipe[4] = 1; | |
1630 | swizzle_pipe[5] = 3; | |
1631 | swizzle_pipe[6] = 5; | |
1632 | swizzle_pipe[7] = 7; | |
1633 | } | |
1634 | break; | |
1635 | } | |
1636 | ||
1637 | for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) { | |
1638 | while (((1 << cur_backend) & enabled_backends_mask) == 0) | |
1639 | cur_backend = (cur_backend + 1) % EVERGREEN_MAX_BACKENDS; | |
1640 | ||
1641 | backend_map |= (((cur_backend & 0xf) << (swizzle_pipe[cur_pipe] * 4))); | |
1642 | ||
1643 | cur_backend = (cur_backend + 1) % EVERGREEN_MAX_BACKENDS; | |
1644 | } | |
bcc1c2a1 AD |
1645 | |
1646 | return backend_map; | |
1647 | } | |
bcc1c2a1 AD |
1648 | |
1649 | static void evergreen_gpu_init(struct radeon_device *rdev) | |
1650 | { | |
32fcdbf4 AD |
1651 | u32 cc_rb_backend_disable = 0; |
1652 | u32 cc_gc_shader_pipe_config; | |
1653 | u32 gb_addr_config = 0; | |
1654 | u32 mc_shared_chmap, mc_arb_ramcfg; | |
1655 | u32 gb_backend_map; | |
1656 | u32 grbm_gfx_index; | |
1657 | u32 sx_debug_1; | |
1658 | u32 smx_dc_ctl0; | |
1659 | u32 sq_config; | |
1660 | u32 sq_lds_resource_mgmt; | |
1661 | u32 sq_gpr_resource_mgmt_1; | |
1662 | u32 sq_gpr_resource_mgmt_2; | |
1663 | u32 sq_gpr_resource_mgmt_3; | |
1664 | u32 sq_thread_resource_mgmt; | |
1665 | u32 sq_thread_resource_mgmt_2; | |
1666 | u32 sq_stack_resource_mgmt_1; | |
1667 | u32 sq_stack_resource_mgmt_2; | |
1668 | u32 sq_stack_resource_mgmt_3; | |
1669 | u32 vgt_cache_invalidation; | |
f25a5c63 | 1670 | u32 hdp_host_path_cntl, tmp; |
32fcdbf4 AD |
1671 | int i, j, num_shader_engines, ps_thread_count; |
1672 | ||
1673 | switch (rdev->family) { | |
1674 | case CHIP_CYPRESS: | |
1675 | case CHIP_HEMLOCK: | |
1676 | rdev->config.evergreen.num_ses = 2; | |
1677 | rdev->config.evergreen.max_pipes = 4; | |
1678 | rdev->config.evergreen.max_tile_pipes = 8; | |
1679 | rdev->config.evergreen.max_simds = 10; | |
1680 | rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses; | |
1681 | rdev->config.evergreen.max_gprs = 256; | |
1682 | rdev->config.evergreen.max_threads = 248; | |
1683 | rdev->config.evergreen.max_gs_threads = 32; | |
1684 | rdev->config.evergreen.max_stack_entries = 512; | |
1685 | rdev->config.evergreen.sx_num_of_sets = 4; | |
1686 | rdev->config.evergreen.sx_max_export_size = 256; | |
1687 | rdev->config.evergreen.sx_max_export_pos_size = 64; | |
1688 | rdev->config.evergreen.sx_max_export_smx_size = 192; | |
1689 | rdev->config.evergreen.max_hw_contexts = 8; | |
1690 | rdev->config.evergreen.sq_num_cf_insts = 2; | |
1691 | ||
1692 | rdev->config.evergreen.sc_prim_fifo_size = 0x100; | |
1693 | rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; | |
1694 | rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; | |
1695 | break; | |
1696 | case CHIP_JUNIPER: | |
1697 | rdev->config.evergreen.num_ses = 1; | |
1698 | rdev->config.evergreen.max_pipes = 4; | |
1699 | rdev->config.evergreen.max_tile_pipes = 4; | |
1700 | rdev->config.evergreen.max_simds = 10; | |
1701 | rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses; | |
1702 | rdev->config.evergreen.max_gprs = 256; | |
1703 | rdev->config.evergreen.max_threads = 248; | |
1704 | rdev->config.evergreen.max_gs_threads = 32; | |
1705 | rdev->config.evergreen.max_stack_entries = 512; | |
1706 | rdev->config.evergreen.sx_num_of_sets = 4; | |
1707 | rdev->config.evergreen.sx_max_export_size = 256; | |
1708 | rdev->config.evergreen.sx_max_export_pos_size = 64; | |
1709 | rdev->config.evergreen.sx_max_export_smx_size = 192; | |
1710 | rdev->config.evergreen.max_hw_contexts = 8; | |
1711 | rdev->config.evergreen.sq_num_cf_insts = 2; | |
1712 | ||
1713 | rdev->config.evergreen.sc_prim_fifo_size = 0x100; | |
1714 | rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; | |
1715 | rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; | |
1716 | break; | |
1717 | case CHIP_REDWOOD: | |
1718 | rdev->config.evergreen.num_ses = 1; | |
1719 | rdev->config.evergreen.max_pipes = 4; | |
1720 | rdev->config.evergreen.max_tile_pipes = 4; | |
1721 | rdev->config.evergreen.max_simds = 5; | |
1722 | rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses; | |
1723 | rdev->config.evergreen.max_gprs = 256; | |
1724 | rdev->config.evergreen.max_threads = 248; | |
1725 | rdev->config.evergreen.max_gs_threads = 32; | |
1726 | rdev->config.evergreen.max_stack_entries = 256; | |
1727 | rdev->config.evergreen.sx_num_of_sets = 4; | |
1728 | rdev->config.evergreen.sx_max_export_size = 256; | |
1729 | rdev->config.evergreen.sx_max_export_pos_size = 64; | |
1730 | rdev->config.evergreen.sx_max_export_smx_size = 192; | |
1731 | rdev->config.evergreen.max_hw_contexts = 8; | |
1732 | rdev->config.evergreen.sq_num_cf_insts = 2; | |
1733 | ||
1734 | rdev->config.evergreen.sc_prim_fifo_size = 0x100; | |
1735 | rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; | |
1736 | rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; | |
1737 | break; | |
1738 | case CHIP_CEDAR: | |
1739 | default: | |
1740 | rdev->config.evergreen.num_ses = 1; | |
1741 | rdev->config.evergreen.max_pipes = 2; | |
1742 | rdev->config.evergreen.max_tile_pipes = 2; | |
1743 | rdev->config.evergreen.max_simds = 2; | |
1744 | rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses; | |
1745 | rdev->config.evergreen.max_gprs = 256; | |
1746 | rdev->config.evergreen.max_threads = 192; | |
1747 | rdev->config.evergreen.max_gs_threads = 16; | |
1748 | rdev->config.evergreen.max_stack_entries = 256; | |
1749 | rdev->config.evergreen.sx_num_of_sets = 4; | |
1750 | rdev->config.evergreen.sx_max_export_size = 128; | |
1751 | rdev->config.evergreen.sx_max_export_pos_size = 32; | |
1752 | rdev->config.evergreen.sx_max_export_smx_size = 96; | |
1753 | rdev->config.evergreen.max_hw_contexts = 4; | |
1754 | rdev->config.evergreen.sq_num_cf_insts = 1; | |
1755 | ||
d5e455e4 AD |
1756 | rdev->config.evergreen.sc_prim_fifo_size = 0x40; |
1757 | rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; | |
1758 | rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; | |
1759 | break; | |
1760 | case CHIP_PALM: | |
1761 | rdev->config.evergreen.num_ses = 1; | |
1762 | rdev->config.evergreen.max_pipes = 2; | |
1763 | rdev->config.evergreen.max_tile_pipes = 2; | |
1764 | rdev->config.evergreen.max_simds = 2; | |
1765 | rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses; | |
1766 | rdev->config.evergreen.max_gprs = 256; | |
1767 | rdev->config.evergreen.max_threads = 192; | |
1768 | rdev->config.evergreen.max_gs_threads = 16; | |
1769 | rdev->config.evergreen.max_stack_entries = 256; | |
1770 | rdev->config.evergreen.sx_num_of_sets = 4; | |
1771 | rdev->config.evergreen.sx_max_export_size = 128; | |
1772 | rdev->config.evergreen.sx_max_export_pos_size = 32; | |
1773 | rdev->config.evergreen.sx_max_export_smx_size = 96; | |
1774 | rdev->config.evergreen.max_hw_contexts = 4; | |
1775 | rdev->config.evergreen.sq_num_cf_insts = 1; | |
1776 | ||
d5c5a72f AD |
1777 | rdev->config.evergreen.sc_prim_fifo_size = 0x40; |
1778 | rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; | |
1779 | rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; | |
1780 | break; | |
1781 | case CHIP_SUMO: | |
1782 | rdev->config.evergreen.num_ses = 1; | |
1783 | rdev->config.evergreen.max_pipes = 4; | |
1784 | rdev->config.evergreen.max_tile_pipes = 2; | |
1785 | if (rdev->pdev->device == 0x9648) | |
1786 | rdev->config.evergreen.max_simds = 3; | |
1787 | else if ((rdev->pdev->device == 0x9647) || | |
1788 | (rdev->pdev->device == 0x964a)) | |
1789 | rdev->config.evergreen.max_simds = 4; | |
1790 | else | |
1791 | rdev->config.evergreen.max_simds = 5; | |
1792 | rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses; | |
1793 | rdev->config.evergreen.max_gprs = 256; | |
1794 | rdev->config.evergreen.max_threads = 248; | |
1795 | rdev->config.evergreen.max_gs_threads = 32; | |
1796 | rdev->config.evergreen.max_stack_entries = 256; | |
1797 | rdev->config.evergreen.sx_num_of_sets = 4; | |
1798 | rdev->config.evergreen.sx_max_export_size = 256; | |
1799 | rdev->config.evergreen.sx_max_export_pos_size = 64; | |
1800 | rdev->config.evergreen.sx_max_export_smx_size = 192; | |
1801 | rdev->config.evergreen.max_hw_contexts = 8; | |
1802 | rdev->config.evergreen.sq_num_cf_insts = 2; | |
1803 | ||
1804 | rdev->config.evergreen.sc_prim_fifo_size = 0x40; | |
1805 | rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; | |
1806 | rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; | |
1807 | break; | |
1808 | case CHIP_SUMO2: | |
1809 | rdev->config.evergreen.num_ses = 1; | |
1810 | rdev->config.evergreen.max_pipes = 4; | |
1811 | rdev->config.evergreen.max_tile_pipes = 4; | |
1812 | rdev->config.evergreen.max_simds = 2; | |
1813 | rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses; | |
1814 | rdev->config.evergreen.max_gprs = 256; | |
1815 | rdev->config.evergreen.max_threads = 248; | |
1816 | rdev->config.evergreen.max_gs_threads = 32; | |
1817 | rdev->config.evergreen.max_stack_entries = 512; | |
1818 | rdev->config.evergreen.sx_num_of_sets = 4; | |
1819 | rdev->config.evergreen.sx_max_export_size = 256; | |
1820 | rdev->config.evergreen.sx_max_export_pos_size = 64; | |
1821 | rdev->config.evergreen.sx_max_export_smx_size = 192; | |
1822 | rdev->config.evergreen.max_hw_contexts = 8; | |
1823 | rdev->config.evergreen.sq_num_cf_insts = 2; | |
1824 | ||
adb68fa2 AD |
1825 | rdev->config.evergreen.sc_prim_fifo_size = 0x40; |
1826 | rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; | |
1827 | rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; | |
1828 | break; | |
1829 | case CHIP_BARTS: | |
1830 | rdev->config.evergreen.num_ses = 2; | |
1831 | rdev->config.evergreen.max_pipes = 4; | |
1832 | rdev->config.evergreen.max_tile_pipes = 8; | |
1833 | rdev->config.evergreen.max_simds = 7; | |
1834 | rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses; | |
1835 | rdev->config.evergreen.max_gprs = 256; | |
1836 | rdev->config.evergreen.max_threads = 248; | |
1837 | rdev->config.evergreen.max_gs_threads = 32; | |
1838 | rdev->config.evergreen.max_stack_entries = 512; | |
1839 | rdev->config.evergreen.sx_num_of_sets = 4; | |
1840 | rdev->config.evergreen.sx_max_export_size = 256; | |
1841 | rdev->config.evergreen.sx_max_export_pos_size = 64; | |
1842 | rdev->config.evergreen.sx_max_export_smx_size = 192; | |
1843 | rdev->config.evergreen.max_hw_contexts = 8; | |
1844 | rdev->config.evergreen.sq_num_cf_insts = 2; | |
1845 | ||
1846 | rdev->config.evergreen.sc_prim_fifo_size = 0x100; | |
1847 | rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; | |
1848 | rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; | |
1849 | break; | |
1850 | case CHIP_TURKS: | |
1851 | rdev->config.evergreen.num_ses = 1; | |
1852 | rdev->config.evergreen.max_pipes = 4; | |
1853 | rdev->config.evergreen.max_tile_pipes = 4; | |
1854 | rdev->config.evergreen.max_simds = 6; | |
1855 | rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses; | |
1856 | rdev->config.evergreen.max_gprs = 256; | |
1857 | rdev->config.evergreen.max_threads = 248; | |
1858 | rdev->config.evergreen.max_gs_threads = 32; | |
1859 | rdev->config.evergreen.max_stack_entries = 256; | |
1860 | rdev->config.evergreen.sx_num_of_sets = 4; | |
1861 | rdev->config.evergreen.sx_max_export_size = 256; | |
1862 | rdev->config.evergreen.sx_max_export_pos_size = 64; | |
1863 | rdev->config.evergreen.sx_max_export_smx_size = 192; | |
1864 | rdev->config.evergreen.max_hw_contexts = 8; | |
1865 | rdev->config.evergreen.sq_num_cf_insts = 2; | |
1866 | ||
1867 | rdev->config.evergreen.sc_prim_fifo_size = 0x100; | |
1868 | rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; | |
1869 | rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; | |
1870 | break; | |
1871 | case CHIP_CAICOS: | |
1872 | rdev->config.evergreen.num_ses = 1; | |
1873 | rdev->config.evergreen.max_pipes = 4; | |
1874 | rdev->config.evergreen.max_tile_pipes = 2; | |
1875 | rdev->config.evergreen.max_simds = 2; | |
1876 | rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses; | |
1877 | rdev->config.evergreen.max_gprs = 256; | |
1878 | rdev->config.evergreen.max_threads = 192; | |
1879 | rdev->config.evergreen.max_gs_threads = 16; | |
1880 | rdev->config.evergreen.max_stack_entries = 256; | |
1881 | rdev->config.evergreen.sx_num_of_sets = 4; | |
1882 | rdev->config.evergreen.sx_max_export_size = 128; | |
1883 | rdev->config.evergreen.sx_max_export_pos_size = 32; | |
1884 | rdev->config.evergreen.sx_max_export_smx_size = 96; | |
1885 | rdev->config.evergreen.max_hw_contexts = 4; | |
1886 | rdev->config.evergreen.sq_num_cf_insts = 1; | |
1887 | ||
32fcdbf4 AD |
1888 | rdev->config.evergreen.sc_prim_fifo_size = 0x40; |
1889 | rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; | |
1890 | rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; | |
1891 | break; | |
1892 | } | |
1893 | ||
1894 | /* Initialize HDP */ | |
1895 | for (i = 0, j = 0; i < 32; i++, j += 0x18) { | |
1896 | WREG32((0x2c14 + j), 0x00000000); | |
1897 | WREG32((0x2c18 + j), 0x00000000); | |
1898 | WREG32((0x2c1c + j), 0x00000000); | |
1899 | WREG32((0x2c20 + j), 0x00000000); | |
1900 | WREG32((0x2c24 + j), 0x00000000); | |
1901 | } | |
1902 | ||
1903 | WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); | |
1904 | ||
d054ac16 AD |
1905 | evergreen_fix_pci_max_read_req_size(rdev); |
1906 | ||
32fcdbf4 AD |
1907 | cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & ~2; |
1908 | ||
1909 | cc_gc_shader_pipe_config |= | |
1910 | INACTIVE_QD_PIPES((EVERGREEN_MAX_PIPES_MASK << rdev->config.evergreen.max_pipes) | |
1911 | & EVERGREEN_MAX_PIPES_MASK); | |
1912 | cc_gc_shader_pipe_config |= | |
1913 | INACTIVE_SIMDS((EVERGREEN_MAX_SIMDS_MASK << rdev->config.evergreen.max_simds) | |
1914 | & EVERGREEN_MAX_SIMDS_MASK); | |
1915 | ||
1916 | cc_rb_backend_disable = | |
1917 | BACKEND_DISABLE((EVERGREEN_MAX_BACKENDS_MASK << rdev->config.evergreen.max_backends) | |
1918 | & EVERGREEN_MAX_BACKENDS_MASK); | |
1919 | ||
1920 | ||
1921 | mc_shared_chmap = RREG32(MC_SHARED_CHMAP); | |
d9282fca AD |
1922 | if (rdev->flags & RADEON_IS_IGP) |
1923 | mc_arb_ramcfg = RREG32(FUS_MC_ARB_RAMCFG); | |
1924 | else | |
1925 | mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG); | |
32fcdbf4 AD |
1926 | |
1927 | switch (rdev->config.evergreen.max_tile_pipes) { | |
1928 | case 1: | |
1929 | default: | |
1930 | gb_addr_config |= NUM_PIPES(0); | |
1931 | break; | |
1932 | case 2: | |
1933 | gb_addr_config |= NUM_PIPES(1); | |
1934 | break; | |
1935 | case 4: | |
1936 | gb_addr_config |= NUM_PIPES(2); | |
1937 | break; | |
1938 | case 8: | |
1939 | gb_addr_config |= NUM_PIPES(3); | |
1940 | break; | |
1941 | } | |
1942 | ||
1943 | gb_addr_config |= PIPE_INTERLEAVE_SIZE((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT); | |
1944 | gb_addr_config |= BANK_INTERLEAVE_SIZE(0); | |
1945 | gb_addr_config |= NUM_SHADER_ENGINES(rdev->config.evergreen.num_ses - 1); | |
1946 | gb_addr_config |= SHADER_ENGINE_TILE_SIZE(1); | |
1947 | gb_addr_config |= NUM_GPUS(0); /* Hemlock? */ | |
1948 | gb_addr_config |= MULTI_GPU_TILE_SIZE(2); | |
1949 | ||
1950 | if (((mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) > 2) | |
1951 | gb_addr_config |= ROW_SIZE(2); | |
1952 | else | |
1953 | gb_addr_config |= ROW_SIZE((mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT); | |
1954 | ||
1955 | if (rdev->ddev->pdev->device == 0x689e) { | |
1956 | u32 efuse_straps_4; | |
1957 | u32 efuse_straps_3; | |
1958 | u8 efuse_box_bit_131_124; | |
1959 | ||
1960 | WREG32(RCU_IND_INDEX, 0x204); | |
1961 | efuse_straps_4 = RREG32(RCU_IND_DATA); | |
1962 | WREG32(RCU_IND_INDEX, 0x203); | |
1963 | efuse_straps_3 = RREG32(RCU_IND_DATA); | |
1964 | efuse_box_bit_131_124 = (u8)(((efuse_straps_4 & 0xf) << 4) | ((efuse_straps_3 & 0xf0000000) >> 28)); | |
1965 | ||
1966 | switch(efuse_box_bit_131_124) { | |
1967 | case 0x00: | |
1968 | gb_backend_map = 0x76543210; | |
1969 | break; | |
1970 | case 0x55: | |
1971 | gb_backend_map = 0x77553311; | |
1972 | break; | |
1973 | case 0x56: | |
1974 | gb_backend_map = 0x77553300; | |
1975 | break; | |
1976 | case 0x59: | |
1977 | gb_backend_map = 0x77552211; | |
1978 | break; | |
1979 | case 0x66: | |
1980 | gb_backend_map = 0x77443300; | |
1981 | break; | |
1982 | case 0x99: | |
1983 | gb_backend_map = 0x66552211; | |
1984 | break; | |
1985 | case 0x5a: | |
1986 | gb_backend_map = 0x77552200; | |
1987 | break; | |
1988 | case 0xaa: | |
1989 | gb_backend_map = 0x66442200; | |
1990 | break; | |
1991 | case 0x95: | |
1992 | gb_backend_map = 0x66553311; | |
1993 | break; | |
1994 | default: | |
1995 | DRM_ERROR("bad backend map, using default\n"); | |
1996 | gb_backend_map = | |
1997 | evergreen_get_tile_pipe_to_backend_map(rdev, | |
1998 | rdev->config.evergreen.max_tile_pipes, | |
1999 | rdev->config.evergreen.max_backends, | |
2000 | ((EVERGREEN_MAX_BACKENDS_MASK << | |
2001 | rdev->config.evergreen.max_backends) & | |
2002 | EVERGREEN_MAX_BACKENDS_MASK)); | |
2003 | break; | |
2004 | } | |
2005 | } else if (rdev->ddev->pdev->device == 0x68b9) { | |
2006 | u32 efuse_straps_3; | |
2007 | u8 efuse_box_bit_127_124; | |
2008 | ||
2009 | WREG32(RCU_IND_INDEX, 0x203); | |
2010 | efuse_straps_3 = RREG32(RCU_IND_DATA); | |
d31dba58 | 2011 | efuse_box_bit_127_124 = (u8)((efuse_straps_3 & 0xF0000000) >> 28); |
32fcdbf4 AD |
2012 | |
2013 | switch(efuse_box_bit_127_124) { | |
2014 | case 0x0: | |
2015 | gb_backend_map = 0x00003210; | |
2016 | break; | |
2017 | case 0x5: | |
2018 | case 0x6: | |
2019 | case 0x9: | |
2020 | case 0xa: | |
2021 | gb_backend_map = 0x00003311; | |
2022 | break; | |
2023 | default: | |
2024 | DRM_ERROR("bad backend map, using default\n"); | |
2025 | gb_backend_map = | |
2026 | evergreen_get_tile_pipe_to_backend_map(rdev, | |
2027 | rdev->config.evergreen.max_tile_pipes, | |
2028 | rdev->config.evergreen.max_backends, | |
2029 | ((EVERGREEN_MAX_BACKENDS_MASK << | |
2030 | rdev->config.evergreen.max_backends) & | |
2031 | EVERGREEN_MAX_BACKENDS_MASK)); | |
2032 | break; | |
2033 | } | |
b741be82 AD |
2034 | } else { |
2035 | switch (rdev->family) { | |
2036 | case CHIP_CYPRESS: | |
2037 | case CHIP_HEMLOCK: | |
03f40090 | 2038 | case CHIP_BARTS: |
b741be82 AD |
2039 | gb_backend_map = 0x66442200; |
2040 | break; | |
2041 | case CHIP_JUNIPER: | |
9a4a0b9c | 2042 | gb_backend_map = 0x00002200; |
b741be82 AD |
2043 | break; |
2044 | default: | |
2045 | gb_backend_map = | |
2046 | evergreen_get_tile_pipe_to_backend_map(rdev, | |
2047 | rdev->config.evergreen.max_tile_pipes, | |
2048 | rdev->config.evergreen.max_backends, | |
2049 | ((EVERGREEN_MAX_BACKENDS_MASK << | |
2050 | rdev->config.evergreen.max_backends) & | |
2051 | EVERGREEN_MAX_BACKENDS_MASK)); | |
2052 | } | |
2053 | } | |
32fcdbf4 | 2054 | |
1aa52bd3 AD |
2055 | /* setup tiling info dword. gb_addr_config is not adequate since it does |
2056 | * not have bank info, so create a custom tiling dword. | |
2057 | * bits 3:0 num_pipes | |
2058 | * bits 7:4 num_banks | |
2059 | * bits 11:8 group_size | |
2060 | * bits 15:12 row_size | |
2061 | */ | |
2062 | rdev->config.evergreen.tile_config = 0; | |
2063 | switch (rdev->config.evergreen.max_tile_pipes) { | |
2064 | case 1: | |
2065 | default: | |
2066 | rdev->config.evergreen.tile_config |= (0 << 0); | |
2067 | break; | |
2068 | case 2: | |
2069 | rdev->config.evergreen.tile_config |= (1 << 0); | |
2070 | break; | |
2071 | case 4: | |
2072 | rdev->config.evergreen.tile_config |= (2 << 0); | |
2073 | break; | |
2074 | case 8: | |
2075 | rdev->config.evergreen.tile_config |= (3 << 0); | |
2076 | break; | |
2077 | } | |
d698a34d | 2078 | /* num banks is 8 on all fusion asics. 0 = 4, 1 = 8, 2 = 16 */ |
5bfa4879 | 2079 | if (rdev->flags & RADEON_IS_IGP) |
d698a34d | 2080 | rdev->config.evergreen.tile_config |= 1 << 4; |
5bfa4879 AD |
2081 | else |
2082 | rdev->config.evergreen.tile_config |= | |
2083 | ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) << 4; | |
1aa52bd3 AD |
2084 | rdev->config.evergreen.tile_config |= |
2085 | ((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT) << 8; | |
2086 | rdev->config.evergreen.tile_config |= | |
2087 | ((gb_addr_config & 0x30000000) >> 28) << 12; | |
2088 | ||
e55b9422 | 2089 | rdev->config.evergreen.backend_map = gb_backend_map; |
32fcdbf4 AD |
2090 | WREG32(GB_BACKEND_MAP, gb_backend_map); |
2091 | WREG32(GB_ADDR_CONFIG, gb_addr_config); | |
2092 | WREG32(DMIF_ADDR_CONFIG, gb_addr_config); | |
2093 | WREG32(HDP_ADDR_CONFIG, gb_addr_config); | |
2094 | ||
2095 | num_shader_engines = ((RREG32(GB_ADDR_CONFIG) & NUM_SHADER_ENGINES(3)) >> 12) + 1; | |
2096 | grbm_gfx_index = INSTANCE_BROADCAST_WRITES; | |
2097 | ||
2098 | for (i = 0; i < rdev->config.evergreen.num_ses; i++) { | |
2099 | u32 rb = cc_rb_backend_disable | (0xf0 << 16); | |
2100 | u32 sp = cc_gc_shader_pipe_config; | |
2101 | u32 gfx = grbm_gfx_index | SE_INDEX(i); | |
2102 | ||
2103 | if (i == num_shader_engines) { | |
2104 | rb |= BACKEND_DISABLE(EVERGREEN_MAX_BACKENDS_MASK); | |
2105 | sp |= INACTIVE_SIMDS(EVERGREEN_MAX_SIMDS_MASK); | |
2106 | } | |
2107 | ||
2108 | WREG32(GRBM_GFX_INDEX, gfx); | |
2109 | WREG32(RLC_GFX_INDEX, gfx); | |
2110 | ||
2111 | WREG32(CC_RB_BACKEND_DISABLE, rb); | |
2112 | WREG32(CC_SYS_RB_BACKEND_DISABLE, rb); | |
2113 | WREG32(GC_USER_RB_BACKEND_DISABLE, rb); | |
2114 | WREG32(CC_GC_SHADER_PIPE_CONFIG, sp); | |
2115 | } | |
2116 | ||
2117 | grbm_gfx_index |= SE_BROADCAST_WRITES; | |
2118 | WREG32(GRBM_GFX_INDEX, grbm_gfx_index); | |
2119 | WREG32(RLC_GFX_INDEX, grbm_gfx_index); | |
2120 | ||
2121 | WREG32(CGTS_SYS_TCC_DISABLE, 0); | |
2122 | WREG32(CGTS_TCC_DISABLE, 0); | |
2123 | WREG32(CGTS_USER_SYS_TCC_DISABLE, 0); | |
2124 | WREG32(CGTS_USER_TCC_DISABLE, 0); | |
2125 | ||
2126 | /* set HW defaults for 3D engine */ | |
2127 | WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | | |
2128 | ROQ_IB2_START(0x2b))); | |
2129 | ||
2130 | WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30)); | |
2131 | ||
2132 | WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | | |
2133 | SYNC_GRADIENT | | |
2134 | SYNC_WALKER | | |
2135 | SYNC_ALIGNER)); | |
2136 | ||
2137 | sx_debug_1 = RREG32(SX_DEBUG_1); | |
2138 | sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS; | |
2139 | WREG32(SX_DEBUG_1, sx_debug_1); | |
2140 | ||
2141 | ||
2142 | smx_dc_ctl0 = RREG32(SMX_DC_CTL0); | |
2143 | smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff); | |
2144 | smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.evergreen.sx_num_of_sets); | |
2145 | WREG32(SMX_DC_CTL0, smx_dc_ctl0); | |
2146 | ||
2147 | WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_size / 4) - 1) | | |
2148 | POSITION_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_pos_size / 4) - 1) | | |
2149 | SMX_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_smx_size / 4) - 1))); | |
2150 | ||
2151 | WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.evergreen.sc_prim_fifo_size) | | |
2152 | SC_HIZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_hiz_tile_fifo_size) | | |
2153 | SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_earlyz_tile_fifo_size))); | |
2154 | ||
2155 | WREG32(VGT_NUM_INSTANCES, 1); | |
2156 | WREG32(SPI_CONFIG_CNTL, 0); | |
2157 | WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4)); | |
2158 | WREG32(CP_PERFMON_CNTL, 0); | |
2159 | ||
2160 | WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.evergreen.sq_num_cf_insts) | | |
2161 | FETCH_FIFO_HIWATER(0x4) | | |
2162 | DONE_FIFO_HIWATER(0xe0) | | |
2163 | ALU_UPDATE_FIFO_HIWATER(0x8))); | |
2164 | ||
2165 | sq_config = RREG32(SQ_CONFIG); | |
2166 | sq_config &= ~(PS_PRIO(3) | | |
2167 | VS_PRIO(3) | | |
2168 | GS_PRIO(3) | | |
2169 | ES_PRIO(3)); | |
2170 | sq_config |= (VC_ENABLE | | |
2171 | EXPORT_SRC_C | | |
2172 | PS_PRIO(0) | | |
2173 | VS_PRIO(1) | | |
2174 | GS_PRIO(2) | | |
2175 | ES_PRIO(3)); | |
2176 | ||
d5e455e4 AD |
2177 | switch (rdev->family) { |
2178 | case CHIP_CEDAR: | |
2179 | case CHIP_PALM: | |
d5c5a72f AD |
2180 | case CHIP_SUMO: |
2181 | case CHIP_SUMO2: | |
adb68fa2 | 2182 | case CHIP_CAICOS: |
32fcdbf4 AD |
2183 | /* no vertex cache */ |
2184 | sq_config &= ~VC_ENABLE; | |
d5e455e4 AD |
2185 | break; |
2186 | default: | |
2187 | break; | |
2188 | } | |
32fcdbf4 AD |
2189 | |
2190 | sq_lds_resource_mgmt = RREG32(SQ_LDS_RESOURCE_MGMT); | |
2191 | ||
2192 | sq_gpr_resource_mgmt_1 = NUM_PS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2))* 12 / 32); | |
2193 | sq_gpr_resource_mgmt_1 |= NUM_VS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 6 / 32); | |
2194 | sq_gpr_resource_mgmt_1 |= NUM_CLAUSE_TEMP_GPRS(4); | |
2195 | sq_gpr_resource_mgmt_2 = NUM_GS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32); | |
2196 | sq_gpr_resource_mgmt_2 |= NUM_ES_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32); | |
2197 | sq_gpr_resource_mgmt_3 = NUM_HS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32); | |
2198 | sq_gpr_resource_mgmt_3 |= NUM_LS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32); | |
2199 | ||
d5e455e4 AD |
2200 | switch (rdev->family) { |
2201 | case CHIP_CEDAR: | |
2202 | case CHIP_PALM: | |
d5c5a72f AD |
2203 | case CHIP_SUMO: |
2204 | case CHIP_SUMO2: | |
32fcdbf4 | 2205 | ps_thread_count = 96; |
d5e455e4 AD |
2206 | break; |
2207 | default: | |
32fcdbf4 | 2208 | ps_thread_count = 128; |
d5e455e4 AD |
2209 | break; |
2210 | } | |
32fcdbf4 AD |
2211 | |
2212 | sq_thread_resource_mgmt = NUM_PS_THREADS(ps_thread_count); | |
f96b35cd AD |
2213 | sq_thread_resource_mgmt |= NUM_VS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8); |
2214 | sq_thread_resource_mgmt |= NUM_GS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8); | |
2215 | sq_thread_resource_mgmt |= NUM_ES_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8); | |
2216 | sq_thread_resource_mgmt_2 = NUM_HS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8); | |
2217 | sq_thread_resource_mgmt_2 |= NUM_LS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8); | |
32fcdbf4 AD |
2218 | |
2219 | sq_stack_resource_mgmt_1 = NUM_PS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6); | |
2220 | sq_stack_resource_mgmt_1 |= NUM_VS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6); | |
2221 | sq_stack_resource_mgmt_2 = NUM_GS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6); | |
2222 | sq_stack_resource_mgmt_2 |= NUM_ES_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6); | |
2223 | sq_stack_resource_mgmt_3 = NUM_HS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6); | |
2224 | sq_stack_resource_mgmt_3 |= NUM_LS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6); | |
2225 | ||
2226 | WREG32(SQ_CONFIG, sq_config); | |
2227 | WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1); | |
2228 | WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2); | |
2229 | WREG32(SQ_GPR_RESOURCE_MGMT_3, sq_gpr_resource_mgmt_3); | |
2230 | WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt); | |
2231 | WREG32(SQ_THREAD_RESOURCE_MGMT_2, sq_thread_resource_mgmt_2); | |
2232 | WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1); | |
2233 | WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2); | |
2234 | WREG32(SQ_STACK_RESOURCE_MGMT_3, sq_stack_resource_mgmt_3); | |
2235 | WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0); | |
2236 | WREG32(SQ_LDS_RESOURCE_MGMT, sq_lds_resource_mgmt); | |
2237 | ||
2238 | WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) | | |
2239 | FORCE_EOV_MAX_REZ_CNT(255))); | |
2240 | ||
d5e455e4 AD |
2241 | switch (rdev->family) { |
2242 | case CHIP_CEDAR: | |
2243 | case CHIP_PALM: | |
d5c5a72f AD |
2244 | case CHIP_SUMO: |
2245 | case CHIP_SUMO2: | |
adb68fa2 | 2246 | case CHIP_CAICOS: |
32fcdbf4 | 2247 | vgt_cache_invalidation = CACHE_INVALIDATION(TC_ONLY); |
d5e455e4 AD |
2248 | break; |
2249 | default: | |
32fcdbf4 | 2250 | vgt_cache_invalidation = CACHE_INVALIDATION(VC_AND_TC); |
d5e455e4 AD |
2251 | break; |
2252 | } | |
32fcdbf4 AD |
2253 | vgt_cache_invalidation |= AUTO_INVLD_EN(ES_AND_GS_AUTO); |
2254 | WREG32(VGT_CACHE_INVALIDATION, vgt_cache_invalidation); | |
2255 | ||
2256 | WREG32(VGT_GS_VERTEX_REUSE, 16); | |
12920591 | 2257 | WREG32(PA_SU_LINE_STIPPLE_VALUE, 0); |
32fcdbf4 AD |
2258 | WREG32(PA_SC_LINE_STIPPLE_STATE, 0); |
2259 | ||
60a4a3e0 AD |
2260 | WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, 14); |
2261 | WREG32(VGT_OUT_DEALLOC_CNTL, 16); | |
2262 | ||
32fcdbf4 AD |
2263 | WREG32(CB_PERF_CTR0_SEL_0, 0); |
2264 | WREG32(CB_PERF_CTR0_SEL_1, 0); | |
2265 | WREG32(CB_PERF_CTR1_SEL_0, 0); | |
2266 | WREG32(CB_PERF_CTR1_SEL_1, 0); | |
2267 | WREG32(CB_PERF_CTR2_SEL_0, 0); | |
2268 | WREG32(CB_PERF_CTR2_SEL_1, 0); | |
2269 | WREG32(CB_PERF_CTR3_SEL_0, 0); | |
2270 | WREG32(CB_PERF_CTR3_SEL_1, 0); | |
2271 | ||
60a4a3e0 AD |
2272 | /* clear render buffer base addresses */ |
2273 | WREG32(CB_COLOR0_BASE, 0); | |
2274 | WREG32(CB_COLOR1_BASE, 0); | |
2275 | WREG32(CB_COLOR2_BASE, 0); | |
2276 | WREG32(CB_COLOR3_BASE, 0); | |
2277 | WREG32(CB_COLOR4_BASE, 0); | |
2278 | WREG32(CB_COLOR5_BASE, 0); | |
2279 | WREG32(CB_COLOR6_BASE, 0); | |
2280 | WREG32(CB_COLOR7_BASE, 0); | |
2281 | WREG32(CB_COLOR8_BASE, 0); | |
2282 | WREG32(CB_COLOR9_BASE, 0); | |
2283 | WREG32(CB_COLOR10_BASE, 0); | |
2284 | WREG32(CB_COLOR11_BASE, 0); | |
2285 | ||
2286 | /* set the shader const cache sizes to 0 */ | |
2287 | for (i = SQ_ALU_CONST_BUFFER_SIZE_PS_0; i < 0x28200; i += 4) | |
2288 | WREG32(i, 0); | |
2289 | for (i = SQ_ALU_CONST_BUFFER_SIZE_HS_0; i < 0x29000; i += 4) | |
2290 | WREG32(i, 0); | |
2291 | ||
f25a5c63 AD |
2292 | tmp = RREG32(HDP_MISC_CNTL); |
2293 | tmp |= HDP_FLUSH_INVALIDATE_CACHE; | |
2294 | WREG32(HDP_MISC_CNTL, tmp); | |
2295 | ||
32fcdbf4 AD |
2296 | hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL); |
2297 | WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl); | |
2298 | ||
2299 | WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3)); | |
2300 | ||
2301 | udelay(50); | |
2302 | ||
bcc1c2a1 AD |
2303 | } |
2304 | ||
2305 | int evergreen_mc_init(struct radeon_device *rdev) | |
2306 | { | |
bcc1c2a1 AD |
2307 | u32 tmp; |
2308 | int chansize, numchan; | |
bcc1c2a1 AD |
2309 | |
2310 | /* Get VRAM informations */ | |
2311 | rdev->mc.vram_is_ddr = true; | |
8208441b AD |
2312 | if (rdev->flags & RADEON_IS_IGP) |
2313 | tmp = RREG32(FUS_MC_ARB_RAMCFG); | |
2314 | else | |
2315 | tmp = RREG32(MC_ARB_RAMCFG); | |
bcc1c2a1 AD |
2316 | if (tmp & CHANSIZE_OVERRIDE) { |
2317 | chansize = 16; | |
2318 | } else if (tmp & CHANSIZE_MASK) { | |
2319 | chansize = 64; | |
2320 | } else { | |
2321 | chansize = 32; | |
2322 | } | |
2323 | tmp = RREG32(MC_SHARED_CHMAP); | |
2324 | switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) { | |
2325 | case 0: | |
2326 | default: | |
2327 | numchan = 1; | |
2328 | break; | |
2329 | case 1: | |
2330 | numchan = 2; | |
2331 | break; | |
2332 | case 2: | |
2333 | numchan = 4; | |
2334 | break; | |
2335 | case 3: | |
2336 | numchan = 8; | |
2337 | break; | |
2338 | } | |
2339 | rdev->mc.vram_width = numchan * chansize; | |
2340 | /* Could aper size report 0 ? */ | |
01d73a69 JC |
2341 | rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); |
2342 | rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); | |
bcc1c2a1 | 2343 | /* Setup GPU memory space */ |
6eb18f8b AD |
2344 | if (rdev->flags & RADEON_IS_IGP) { |
2345 | /* size in bytes on fusion */ | |
2346 | rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); | |
2347 | rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); | |
2348 | } else { | |
2349 | /* size in MB on evergreen */ | |
2350 | rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024; | |
2351 | rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024; | |
2352 | } | |
51e5fcd3 | 2353 | rdev->mc.visible_vram_size = rdev->mc.aper_size; |
0ef0c1f7 | 2354 | r700_vram_gtt_location(rdev, &rdev->mc); |
f47299c5 AD |
2355 | radeon_update_bandwidth_info(rdev); |
2356 | ||
bcc1c2a1 AD |
2357 | return 0; |
2358 | } | |
d594e46a | 2359 | |
e32eb50d | 2360 | bool evergreen_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) |
225758d8 | 2361 | { |
17db7042 AD |
2362 | u32 srbm_status; |
2363 | u32 grbm_status; | |
2364 | u32 grbm_status_se0, grbm_status_se1; | |
2365 | struct r100_gpu_lockup *lockup = &rdev->config.evergreen.lockup; | |
2366 | int r; | |
2367 | ||
2368 | srbm_status = RREG32(SRBM_STATUS); | |
2369 | grbm_status = RREG32(GRBM_STATUS); | |
2370 | grbm_status_se0 = RREG32(GRBM_STATUS_SE0); | |
2371 | grbm_status_se1 = RREG32(GRBM_STATUS_SE1); | |
2372 | if (!(grbm_status & GUI_ACTIVE)) { | |
e32eb50d | 2373 | r100_gpu_lockup_update(lockup, ring); |
17db7042 AD |
2374 | return false; |
2375 | } | |
2376 | /* force CP activities */ | |
e32eb50d | 2377 | r = radeon_ring_lock(rdev, ring, 2); |
17db7042 AD |
2378 | if (!r) { |
2379 | /* PACKET2 NOP */ | |
e32eb50d CK |
2380 | radeon_ring_write(ring, 0x80000000); |
2381 | radeon_ring_write(ring, 0x80000000); | |
2382 | radeon_ring_unlock_commit(rdev, ring); | |
17db7042 | 2383 | } |
e32eb50d CK |
2384 | ring->rptr = RREG32(CP_RB_RPTR); |
2385 | return r100_gpu_cp_is_lockup(rdev, lockup, ring); | |
225758d8 JG |
2386 | } |
2387 | ||
747943ea | 2388 | static int evergreen_gpu_soft_reset(struct radeon_device *rdev) |
bcc1c2a1 | 2389 | { |
747943ea | 2390 | struct evergreen_mc_save save; |
747943ea AD |
2391 | u32 grbm_reset = 0; |
2392 | ||
8d96fe93 AD |
2393 | if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE)) |
2394 | return 0; | |
2395 | ||
747943ea AD |
2396 | dev_info(rdev->dev, "GPU softreset \n"); |
2397 | dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n", | |
2398 | RREG32(GRBM_STATUS)); | |
2399 | dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n", | |
2400 | RREG32(GRBM_STATUS_SE0)); | |
2401 | dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n", | |
2402 | RREG32(GRBM_STATUS_SE1)); | |
2403 | dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n", | |
2404 | RREG32(SRBM_STATUS)); | |
2405 | evergreen_mc_stop(rdev, &save); | |
2406 | if (evergreen_mc_wait_for_idle(rdev)) { | |
2407 | dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); | |
2408 | } | |
2409 | /* Disable CP parsing/prefetching */ | |
2410 | WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT); | |
2411 | ||
2412 | /* reset all the gfx blocks */ | |
2413 | grbm_reset = (SOFT_RESET_CP | | |
2414 | SOFT_RESET_CB | | |
2415 | SOFT_RESET_DB | | |
2416 | SOFT_RESET_PA | | |
2417 | SOFT_RESET_SC | | |
2418 | SOFT_RESET_SPI | | |
2419 | SOFT_RESET_SH | | |
2420 | SOFT_RESET_SX | | |
2421 | SOFT_RESET_TC | | |
2422 | SOFT_RESET_TA | | |
2423 | SOFT_RESET_VC | | |
2424 | SOFT_RESET_VGT); | |
2425 | ||
2426 | dev_info(rdev->dev, " GRBM_SOFT_RESET=0x%08X\n", grbm_reset); | |
2427 | WREG32(GRBM_SOFT_RESET, grbm_reset); | |
2428 | (void)RREG32(GRBM_SOFT_RESET); | |
2429 | udelay(50); | |
2430 | WREG32(GRBM_SOFT_RESET, 0); | |
2431 | (void)RREG32(GRBM_SOFT_RESET); | |
747943ea AD |
2432 | /* Wait a little for things to settle down */ |
2433 | udelay(50); | |
2434 | dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n", | |
2435 | RREG32(GRBM_STATUS)); | |
2436 | dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n", | |
2437 | RREG32(GRBM_STATUS_SE0)); | |
2438 | dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n", | |
2439 | RREG32(GRBM_STATUS_SE1)); | |
2440 | dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n", | |
2441 | RREG32(SRBM_STATUS)); | |
747943ea | 2442 | evergreen_mc_resume(rdev, &save); |
bcc1c2a1 AD |
2443 | return 0; |
2444 | } | |
2445 | ||
a2d07b74 | 2446 | int evergreen_asic_reset(struct radeon_device *rdev) |
bcc1c2a1 | 2447 | { |
747943ea AD |
2448 | return evergreen_gpu_soft_reset(rdev); |
2449 | } | |
2450 | ||
45f9a39b AD |
2451 | /* Interrupts */ |
2452 | ||
2453 | u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc) | |
2454 | { | |
2455 | switch (crtc) { | |
2456 | case 0: | |
2457 | return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC0_REGISTER_OFFSET); | |
2458 | case 1: | |
2459 | return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC1_REGISTER_OFFSET); | |
2460 | case 2: | |
2461 | return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC2_REGISTER_OFFSET); | |
2462 | case 3: | |
2463 | return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC3_REGISTER_OFFSET); | |
2464 | case 4: | |
2465 | return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC4_REGISTER_OFFSET); | |
2466 | case 5: | |
2467 | return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC5_REGISTER_OFFSET); | |
2468 | default: | |
2469 | return 0; | |
2470 | } | |
2471 | } | |
2472 | ||
2473 | void evergreen_disable_interrupt_state(struct radeon_device *rdev) | |
2474 | { | |
2475 | u32 tmp; | |
2476 | ||
3555e53b | 2477 | WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE); |
45f9a39b AD |
2478 | WREG32(GRBM_INT_CNTL, 0); |
2479 | WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); | |
2480 | WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); | |
b7eff394 | 2481 | if (rdev->num_crtc >= 4) { |
18007401 AD |
2482 | WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); |
2483 | WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); | |
b7eff394 AD |
2484 | } |
2485 | if (rdev->num_crtc >= 6) { | |
18007401 AD |
2486 | WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); |
2487 | WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); | |
2488 | } | |
45f9a39b AD |
2489 | |
2490 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); | |
2491 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); | |
b7eff394 | 2492 | if (rdev->num_crtc >= 4) { |
18007401 AD |
2493 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); |
2494 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); | |
b7eff394 AD |
2495 | } |
2496 | if (rdev->num_crtc >= 6) { | |
18007401 AD |
2497 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); |
2498 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); | |
2499 | } | |
45f9a39b AD |
2500 | |
2501 | WREG32(DACA_AUTODETECT_INT_CONTROL, 0); | |
2502 | WREG32(DACB_AUTODETECT_INT_CONTROL, 0); | |
2503 | ||
2504 | tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY; | |
2505 | WREG32(DC_HPD1_INT_CONTROL, tmp); | |
2506 | tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY; | |
2507 | WREG32(DC_HPD2_INT_CONTROL, tmp); | |
2508 | tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY; | |
2509 | WREG32(DC_HPD3_INT_CONTROL, tmp); | |
2510 | tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY; | |
2511 | WREG32(DC_HPD4_INT_CONTROL, tmp); | |
2512 | tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY; | |
2513 | WREG32(DC_HPD5_INT_CONTROL, tmp); | |
2514 | tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY; | |
2515 | WREG32(DC_HPD6_INT_CONTROL, tmp); | |
2516 | ||
2517 | } | |
2518 | ||
2519 | int evergreen_irq_set(struct radeon_device *rdev) | |
2520 | { | |
2521 | u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE; | |
2522 | u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0; | |
2523 | u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6; | |
2031f77c | 2524 | u32 grbm_int_cntl = 0; |
6f34be50 | 2525 | u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0; |
45f9a39b AD |
2526 | |
2527 | if (!rdev->irq.installed) { | |
fce7d61b | 2528 | WARN(1, "Can't enable IRQ/MSI because no handler is installed\n"); |
45f9a39b AD |
2529 | return -EINVAL; |
2530 | } | |
2531 | /* don't enable anything if the ih is disabled */ | |
2532 | if (!rdev->ih.enabled) { | |
2533 | r600_disable_interrupts(rdev); | |
2534 | /* force the active interrupt state to all disabled */ | |
2535 | evergreen_disable_interrupt_state(rdev); | |
2536 | return 0; | |
2537 | } | |
2538 | ||
2539 | hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN; | |
2540 | hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN; | |
2541 | hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN; | |
2542 | hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN; | |
2543 | hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN; | |
2544 | hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN; | |
2545 | ||
2546 | if (rdev->irq.sw_int) { | |
2547 | DRM_DEBUG("evergreen_irq_set: sw int\n"); | |
2548 | cp_int_cntl |= RB_INT_ENABLE; | |
d0f8a854 | 2549 | cp_int_cntl |= TIME_STAMP_INT_ENABLE; |
45f9a39b | 2550 | } |
6f34be50 AD |
2551 | if (rdev->irq.crtc_vblank_int[0] || |
2552 | rdev->irq.pflip[0]) { | |
45f9a39b AD |
2553 | DRM_DEBUG("evergreen_irq_set: vblank 0\n"); |
2554 | crtc1 |= VBLANK_INT_MASK; | |
2555 | } | |
6f34be50 AD |
2556 | if (rdev->irq.crtc_vblank_int[1] || |
2557 | rdev->irq.pflip[1]) { | |
45f9a39b AD |
2558 | DRM_DEBUG("evergreen_irq_set: vblank 1\n"); |
2559 | crtc2 |= VBLANK_INT_MASK; | |
2560 | } | |
6f34be50 AD |
2561 | if (rdev->irq.crtc_vblank_int[2] || |
2562 | rdev->irq.pflip[2]) { | |
45f9a39b AD |
2563 | DRM_DEBUG("evergreen_irq_set: vblank 2\n"); |
2564 | crtc3 |= VBLANK_INT_MASK; | |
2565 | } | |
6f34be50 AD |
2566 | if (rdev->irq.crtc_vblank_int[3] || |
2567 | rdev->irq.pflip[3]) { | |
45f9a39b AD |
2568 | DRM_DEBUG("evergreen_irq_set: vblank 3\n"); |
2569 | crtc4 |= VBLANK_INT_MASK; | |
2570 | } | |
6f34be50 AD |
2571 | if (rdev->irq.crtc_vblank_int[4] || |
2572 | rdev->irq.pflip[4]) { | |
45f9a39b AD |
2573 | DRM_DEBUG("evergreen_irq_set: vblank 4\n"); |
2574 | crtc5 |= VBLANK_INT_MASK; | |
2575 | } | |
6f34be50 AD |
2576 | if (rdev->irq.crtc_vblank_int[5] || |
2577 | rdev->irq.pflip[5]) { | |
45f9a39b AD |
2578 | DRM_DEBUG("evergreen_irq_set: vblank 5\n"); |
2579 | crtc6 |= VBLANK_INT_MASK; | |
2580 | } | |
2581 | if (rdev->irq.hpd[0]) { | |
2582 | DRM_DEBUG("evergreen_irq_set: hpd 1\n"); | |
2583 | hpd1 |= DC_HPDx_INT_EN; | |
2584 | } | |
2585 | if (rdev->irq.hpd[1]) { | |
2586 | DRM_DEBUG("evergreen_irq_set: hpd 2\n"); | |
2587 | hpd2 |= DC_HPDx_INT_EN; | |
2588 | } | |
2589 | if (rdev->irq.hpd[2]) { | |
2590 | DRM_DEBUG("evergreen_irq_set: hpd 3\n"); | |
2591 | hpd3 |= DC_HPDx_INT_EN; | |
2592 | } | |
2593 | if (rdev->irq.hpd[3]) { | |
2594 | DRM_DEBUG("evergreen_irq_set: hpd 4\n"); | |
2595 | hpd4 |= DC_HPDx_INT_EN; | |
2596 | } | |
2597 | if (rdev->irq.hpd[4]) { | |
2598 | DRM_DEBUG("evergreen_irq_set: hpd 5\n"); | |
2599 | hpd5 |= DC_HPDx_INT_EN; | |
2600 | } | |
2601 | if (rdev->irq.hpd[5]) { | |
2602 | DRM_DEBUG("evergreen_irq_set: hpd 6\n"); | |
2603 | hpd6 |= DC_HPDx_INT_EN; | |
2604 | } | |
2031f77c AD |
2605 | if (rdev->irq.gui_idle) { |
2606 | DRM_DEBUG("gui idle\n"); | |
2607 | grbm_int_cntl |= GUI_IDLE_INT_ENABLE; | |
2608 | } | |
45f9a39b AD |
2609 | |
2610 | WREG32(CP_INT_CNTL, cp_int_cntl); | |
2031f77c | 2611 | WREG32(GRBM_INT_CNTL, grbm_int_cntl); |
45f9a39b AD |
2612 | |
2613 | WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1); | |
2614 | WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2); | |
b7eff394 | 2615 | if (rdev->num_crtc >= 4) { |
18007401 AD |
2616 | WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3); |
2617 | WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4); | |
b7eff394 AD |
2618 | } |
2619 | if (rdev->num_crtc >= 6) { | |
18007401 AD |
2620 | WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5); |
2621 | WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6); | |
2622 | } | |
45f9a39b | 2623 | |
6f34be50 AD |
2624 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1); |
2625 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2); | |
b7eff394 AD |
2626 | if (rdev->num_crtc >= 4) { |
2627 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3); | |
2628 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4); | |
2629 | } | |
2630 | if (rdev->num_crtc >= 6) { | |
2631 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, grph5); | |
2632 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6); | |
2633 | } | |
6f34be50 | 2634 | |
45f9a39b AD |
2635 | WREG32(DC_HPD1_INT_CONTROL, hpd1); |
2636 | WREG32(DC_HPD2_INT_CONTROL, hpd2); | |
2637 | WREG32(DC_HPD3_INT_CONTROL, hpd3); | |
2638 | WREG32(DC_HPD4_INT_CONTROL, hpd4); | |
2639 | WREG32(DC_HPD5_INT_CONTROL, hpd5); | |
2640 | WREG32(DC_HPD6_INT_CONTROL, hpd6); | |
2641 | ||
bcc1c2a1 AD |
2642 | return 0; |
2643 | } | |
2644 | ||
cbdd4501 | 2645 | static void evergreen_irq_ack(struct radeon_device *rdev) |
45f9a39b AD |
2646 | { |
2647 | u32 tmp; | |
2648 | ||
6f34be50 AD |
2649 | rdev->irq.stat_regs.evergreen.disp_int = RREG32(DISP_INTERRUPT_STATUS); |
2650 | rdev->irq.stat_regs.evergreen.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE); | |
2651 | rdev->irq.stat_regs.evergreen.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2); | |
2652 | rdev->irq.stat_regs.evergreen.disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3); | |
2653 | rdev->irq.stat_regs.evergreen.disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4); | |
2654 | rdev->irq.stat_regs.evergreen.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5); | |
2655 | rdev->irq.stat_regs.evergreen.d1grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET); | |
2656 | rdev->irq.stat_regs.evergreen.d2grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET); | |
b7eff394 AD |
2657 | if (rdev->num_crtc >= 4) { |
2658 | rdev->irq.stat_regs.evergreen.d3grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET); | |
2659 | rdev->irq.stat_regs.evergreen.d4grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET); | |
2660 | } | |
2661 | if (rdev->num_crtc >= 6) { | |
2662 | rdev->irq.stat_regs.evergreen.d5grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET); | |
2663 | rdev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET); | |
2664 | } | |
6f34be50 AD |
2665 | |
2666 | if (rdev->irq.stat_regs.evergreen.d1grph_int & GRPH_PFLIP_INT_OCCURRED) | |
2667 | WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); | |
2668 | if (rdev->irq.stat_regs.evergreen.d2grph_int & GRPH_PFLIP_INT_OCCURRED) | |
2669 | WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); | |
6f34be50 | 2670 | if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT) |
45f9a39b | 2671 | WREG32(VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK); |
6f34be50 | 2672 | if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT) |
45f9a39b | 2673 | WREG32(VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK); |
6f34be50 | 2674 | if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT) |
45f9a39b | 2675 | WREG32(VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK); |
6f34be50 | 2676 | if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT) |
45f9a39b AD |
2677 | WREG32(VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK); |
2678 | ||
b7eff394 AD |
2679 | if (rdev->num_crtc >= 4) { |
2680 | if (rdev->irq.stat_regs.evergreen.d3grph_int & GRPH_PFLIP_INT_OCCURRED) | |
2681 | WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); | |
2682 | if (rdev->irq.stat_regs.evergreen.d4grph_int & GRPH_PFLIP_INT_OCCURRED) | |
2683 | WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); | |
2684 | if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) | |
2685 | WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK); | |
2686 | if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) | |
2687 | WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK); | |
2688 | if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) | |
2689 | WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK); | |
2690 | if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) | |
2691 | WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK); | |
2692 | } | |
2693 | ||
2694 | if (rdev->num_crtc >= 6) { | |
2695 | if (rdev->irq.stat_regs.evergreen.d5grph_int & GRPH_PFLIP_INT_OCCURRED) | |
2696 | WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); | |
2697 | if (rdev->irq.stat_regs.evergreen.d6grph_int & GRPH_PFLIP_INT_OCCURRED) | |
2698 | WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); | |
2699 | if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) | |
2700 | WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK); | |
2701 | if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) | |
2702 | WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK); | |
2703 | if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) | |
2704 | WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK); | |
2705 | if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) | |
2706 | WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK); | |
2707 | } | |
45f9a39b | 2708 | |
6f34be50 | 2709 | if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) { |
45f9a39b AD |
2710 | tmp = RREG32(DC_HPD1_INT_CONTROL); |
2711 | tmp |= DC_HPDx_INT_ACK; | |
2712 | WREG32(DC_HPD1_INT_CONTROL, tmp); | |
2713 | } | |
6f34be50 | 2714 | if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) { |
45f9a39b AD |
2715 | tmp = RREG32(DC_HPD2_INT_CONTROL); |
2716 | tmp |= DC_HPDx_INT_ACK; | |
2717 | WREG32(DC_HPD2_INT_CONTROL, tmp); | |
2718 | } | |
6f34be50 | 2719 | if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) { |
45f9a39b AD |
2720 | tmp = RREG32(DC_HPD3_INT_CONTROL); |
2721 | tmp |= DC_HPDx_INT_ACK; | |
2722 | WREG32(DC_HPD3_INT_CONTROL, tmp); | |
2723 | } | |
6f34be50 | 2724 | if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) { |
45f9a39b AD |
2725 | tmp = RREG32(DC_HPD4_INT_CONTROL); |
2726 | tmp |= DC_HPDx_INT_ACK; | |
2727 | WREG32(DC_HPD4_INT_CONTROL, tmp); | |
2728 | } | |
6f34be50 | 2729 | if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) { |
45f9a39b AD |
2730 | tmp = RREG32(DC_HPD5_INT_CONTROL); |
2731 | tmp |= DC_HPDx_INT_ACK; | |
2732 | WREG32(DC_HPD5_INT_CONTROL, tmp); | |
2733 | } | |
6f34be50 | 2734 | if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) { |
45f9a39b AD |
2735 | tmp = RREG32(DC_HPD5_INT_CONTROL); |
2736 | tmp |= DC_HPDx_INT_ACK; | |
2737 | WREG32(DC_HPD6_INT_CONTROL, tmp); | |
2738 | } | |
2739 | } | |
2740 | ||
2741 | void evergreen_irq_disable(struct radeon_device *rdev) | |
2742 | { | |
45f9a39b AD |
2743 | r600_disable_interrupts(rdev); |
2744 | /* Wait and acknowledge irq */ | |
2745 | mdelay(1); | |
6f34be50 | 2746 | evergreen_irq_ack(rdev); |
45f9a39b AD |
2747 | evergreen_disable_interrupt_state(rdev); |
2748 | } | |
2749 | ||
755d819e | 2750 | void evergreen_irq_suspend(struct radeon_device *rdev) |
45f9a39b AD |
2751 | { |
2752 | evergreen_irq_disable(rdev); | |
2753 | r600_rlc_stop(rdev); | |
2754 | } | |
2755 | ||
cbdd4501 | 2756 | static u32 evergreen_get_ih_wptr(struct radeon_device *rdev) |
45f9a39b AD |
2757 | { |
2758 | u32 wptr, tmp; | |
2759 | ||
724c80e1 | 2760 | if (rdev->wb.enabled) |
204ae24d | 2761 | wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]); |
724c80e1 AD |
2762 | else |
2763 | wptr = RREG32(IH_RB_WPTR); | |
45f9a39b AD |
2764 | |
2765 | if (wptr & RB_OVERFLOW) { | |
2766 | /* When a ring buffer overflow happen start parsing interrupt | |
2767 | * from the last not overwritten vector (wptr + 16). Hopefully | |
2768 | * this should allow us to catchup. | |
2769 | */ | |
2770 | dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n", | |
2771 | wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask); | |
2772 | rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask; | |
2773 | tmp = RREG32(IH_RB_CNTL); | |
2774 | tmp |= IH_WPTR_OVERFLOW_CLEAR; | |
2775 | WREG32(IH_RB_CNTL, tmp); | |
2776 | } | |
2777 | return (wptr & rdev->ih.ptr_mask); | |
2778 | } | |
2779 | ||
2780 | int evergreen_irq_process(struct radeon_device *rdev) | |
2781 | { | |
682f1a54 DA |
2782 | u32 wptr; |
2783 | u32 rptr; | |
45f9a39b AD |
2784 | u32 src_id, src_data; |
2785 | u32 ring_index; | |
45f9a39b AD |
2786 | unsigned long flags; |
2787 | bool queue_hotplug = false; | |
2788 | ||
682f1a54 | 2789 | if (!rdev->ih.enabled || rdev->shutdown) |
45f9a39b AD |
2790 | return IRQ_NONE; |
2791 | ||
682f1a54 DA |
2792 | wptr = evergreen_get_ih_wptr(rdev); |
2793 | rptr = rdev->ih.rptr; | |
2794 | DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr); | |
45f9a39b | 2795 | |
682f1a54 | 2796 | spin_lock_irqsave(&rdev->ih.lock, flags); |
45f9a39b AD |
2797 | if (rptr == wptr) { |
2798 | spin_unlock_irqrestore(&rdev->ih.lock, flags); | |
2799 | return IRQ_NONE; | |
2800 | } | |
45f9a39b | 2801 | restart_ih: |
964f6645 BH |
2802 | /* Order reading of wptr vs. reading of IH ring data */ |
2803 | rmb(); | |
2804 | ||
45f9a39b | 2805 | /* display interrupts */ |
6f34be50 | 2806 | evergreen_irq_ack(rdev); |
45f9a39b AD |
2807 | |
2808 | rdev->ih.wptr = wptr; | |
2809 | while (rptr != wptr) { | |
2810 | /* wptr/rptr are in bytes! */ | |
2811 | ring_index = rptr / 4; | |
0f234f5f AD |
2812 | src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff; |
2813 | src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff; | |
45f9a39b AD |
2814 | |
2815 | switch (src_id) { | |
2816 | case 1: /* D1 vblank/vline */ | |
2817 | switch (src_data) { | |
2818 | case 0: /* D1 vblank */ | |
6f34be50 | 2819 | if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT) { |
6f34be50 AD |
2820 | if (rdev->irq.crtc_vblank_int[0]) { |
2821 | drm_handle_vblank(rdev->ddev, 0); | |
2822 | rdev->pm.vblank_sync = true; | |
2823 | wake_up(&rdev->irq.vblank_queue); | |
2824 | } | |
3e4ea742 MK |
2825 | if (rdev->irq.pflip[0]) |
2826 | radeon_crtc_handle_flip(rdev, 0); | |
6f34be50 | 2827 | rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VBLANK_INTERRUPT; |
45f9a39b AD |
2828 | DRM_DEBUG("IH: D1 vblank\n"); |
2829 | } | |
2830 | break; | |
2831 | case 1: /* D1 vline */ | |
6f34be50 AD |
2832 | if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT) { |
2833 | rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VLINE_INTERRUPT; | |
45f9a39b AD |
2834 | DRM_DEBUG("IH: D1 vline\n"); |
2835 | } | |
2836 | break; | |
2837 | default: | |
2838 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); | |
2839 | break; | |
2840 | } | |
2841 | break; | |
2842 | case 2: /* D2 vblank/vline */ | |
2843 | switch (src_data) { | |
2844 | case 0: /* D2 vblank */ | |
6f34be50 | 2845 | if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT) { |
6f34be50 AD |
2846 | if (rdev->irq.crtc_vblank_int[1]) { |
2847 | drm_handle_vblank(rdev->ddev, 1); | |
2848 | rdev->pm.vblank_sync = true; | |
2849 | wake_up(&rdev->irq.vblank_queue); | |
2850 | } | |
3e4ea742 MK |
2851 | if (rdev->irq.pflip[1]) |
2852 | radeon_crtc_handle_flip(rdev, 1); | |
6f34be50 | 2853 | rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT; |
45f9a39b AD |
2854 | DRM_DEBUG("IH: D2 vblank\n"); |
2855 | } | |
2856 | break; | |
2857 | case 1: /* D2 vline */ | |
6f34be50 AD |
2858 | if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT) { |
2859 | rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT; | |
45f9a39b AD |
2860 | DRM_DEBUG("IH: D2 vline\n"); |
2861 | } | |
2862 | break; | |
2863 | default: | |
2864 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); | |
2865 | break; | |
2866 | } | |
2867 | break; | |
2868 | case 3: /* D3 vblank/vline */ | |
2869 | switch (src_data) { | |
2870 | case 0: /* D3 vblank */ | |
6f34be50 AD |
2871 | if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) { |
2872 | if (rdev->irq.crtc_vblank_int[2]) { | |
2873 | drm_handle_vblank(rdev->ddev, 2); | |
2874 | rdev->pm.vblank_sync = true; | |
2875 | wake_up(&rdev->irq.vblank_queue); | |
2876 | } | |
2877 | if (rdev->irq.pflip[2]) | |
2878 | radeon_crtc_handle_flip(rdev, 2); | |
2879 | rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT; | |
45f9a39b AD |
2880 | DRM_DEBUG("IH: D3 vblank\n"); |
2881 | } | |
2882 | break; | |
2883 | case 1: /* D3 vline */ | |
6f34be50 AD |
2884 | if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) { |
2885 | rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT; | |
45f9a39b AD |
2886 | DRM_DEBUG("IH: D3 vline\n"); |
2887 | } | |
2888 | break; | |
2889 | default: | |
2890 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); | |
2891 | break; | |
2892 | } | |
2893 | break; | |
2894 | case 4: /* D4 vblank/vline */ | |
2895 | switch (src_data) { | |
2896 | case 0: /* D4 vblank */ | |
6f34be50 AD |
2897 | if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) { |
2898 | if (rdev->irq.crtc_vblank_int[3]) { | |
2899 | drm_handle_vblank(rdev->ddev, 3); | |
2900 | rdev->pm.vblank_sync = true; | |
2901 | wake_up(&rdev->irq.vblank_queue); | |
2902 | } | |
2903 | if (rdev->irq.pflip[3]) | |
2904 | radeon_crtc_handle_flip(rdev, 3); | |
2905 | rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT; | |
45f9a39b AD |
2906 | DRM_DEBUG("IH: D4 vblank\n"); |
2907 | } | |
2908 | break; | |
2909 | case 1: /* D4 vline */ | |
6f34be50 AD |
2910 | if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) { |
2911 | rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT; | |
45f9a39b AD |
2912 | DRM_DEBUG("IH: D4 vline\n"); |
2913 | } | |
2914 | break; | |
2915 | default: | |
2916 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); | |
2917 | break; | |
2918 | } | |
2919 | break; | |
2920 | case 5: /* D5 vblank/vline */ | |
2921 | switch (src_data) { | |
2922 | case 0: /* D5 vblank */ | |
6f34be50 AD |
2923 | if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) { |
2924 | if (rdev->irq.crtc_vblank_int[4]) { | |
2925 | drm_handle_vblank(rdev->ddev, 4); | |
2926 | rdev->pm.vblank_sync = true; | |
2927 | wake_up(&rdev->irq.vblank_queue); | |
2928 | } | |
2929 | if (rdev->irq.pflip[4]) | |
2930 | radeon_crtc_handle_flip(rdev, 4); | |
2931 | rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT; | |
45f9a39b AD |
2932 | DRM_DEBUG("IH: D5 vblank\n"); |
2933 | } | |
2934 | break; | |
2935 | case 1: /* D5 vline */ | |
6f34be50 AD |
2936 | if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) { |
2937 | rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT; | |
45f9a39b AD |
2938 | DRM_DEBUG("IH: D5 vline\n"); |
2939 | } | |
2940 | break; | |
2941 | default: | |
2942 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); | |
2943 | break; | |
2944 | } | |
2945 | break; | |
2946 | case 6: /* D6 vblank/vline */ | |
2947 | switch (src_data) { | |
2948 | case 0: /* D6 vblank */ | |
6f34be50 AD |
2949 | if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) { |
2950 | if (rdev->irq.crtc_vblank_int[5]) { | |
2951 | drm_handle_vblank(rdev->ddev, 5); | |
2952 | rdev->pm.vblank_sync = true; | |
2953 | wake_up(&rdev->irq.vblank_queue); | |
2954 | } | |
2955 | if (rdev->irq.pflip[5]) | |
2956 | radeon_crtc_handle_flip(rdev, 5); | |
2957 | rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT; | |
45f9a39b AD |
2958 | DRM_DEBUG("IH: D6 vblank\n"); |
2959 | } | |
2960 | break; | |
2961 | case 1: /* D6 vline */ | |
6f34be50 AD |
2962 | if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) { |
2963 | rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT; | |
45f9a39b AD |
2964 | DRM_DEBUG("IH: D6 vline\n"); |
2965 | } | |
2966 | break; | |
2967 | default: | |
2968 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); | |
2969 | break; | |
2970 | } | |
2971 | break; | |
2972 | case 42: /* HPD hotplug */ | |
2973 | switch (src_data) { | |
2974 | case 0: | |
6f34be50 AD |
2975 | if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) { |
2976 | rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_INTERRUPT; | |
45f9a39b AD |
2977 | queue_hotplug = true; |
2978 | DRM_DEBUG("IH: HPD1\n"); | |
2979 | } | |
2980 | break; | |
2981 | case 1: | |
6f34be50 AD |
2982 | if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) { |
2983 | rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_INTERRUPT; | |
45f9a39b AD |
2984 | queue_hotplug = true; |
2985 | DRM_DEBUG("IH: HPD2\n"); | |
2986 | } | |
2987 | break; | |
2988 | case 2: | |
6f34be50 AD |
2989 | if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) { |
2990 | rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_INTERRUPT; | |
45f9a39b AD |
2991 | queue_hotplug = true; |
2992 | DRM_DEBUG("IH: HPD3\n"); | |
2993 | } | |
2994 | break; | |
2995 | case 3: | |
6f34be50 AD |
2996 | if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) { |
2997 | rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_INTERRUPT; | |
45f9a39b AD |
2998 | queue_hotplug = true; |
2999 | DRM_DEBUG("IH: HPD4\n"); | |
3000 | } | |
3001 | break; | |
3002 | case 4: | |
6f34be50 AD |
3003 | if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) { |
3004 | rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_INTERRUPT; | |
45f9a39b AD |
3005 | queue_hotplug = true; |
3006 | DRM_DEBUG("IH: HPD5\n"); | |
3007 | } | |
3008 | break; | |
3009 | case 5: | |
6f34be50 AD |
3010 | if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) { |
3011 | rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_INTERRUPT; | |
45f9a39b AD |
3012 | queue_hotplug = true; |
3013 | DRM_DEBUG("IH: HPD6\n"); | |
3014 | } | |
3015 | break; | |
3016 | default: | |
3017 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); | |
3018 | break; | |
3019 | } | |
3020 | break; | |
3021 | case 176: /* CP_INT in ring buffer */ | |
3022 | case 177: /* CP_INT in IB1 */ | |
3023 | case 178: /* CP_INT in IB2 */ | |
3024 | DRM_DEBUG("IH: CP int: 0x%08x\n", src_data); | |
7465280c | 3025 | radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); |
45f9a39b AD |
3026 | break; |
3027 | case 181: /* CP EOP event */ | |
3028 | DRM_DEBUG("IH: CP EOP\n"); | |
7465280c | 3029 | radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); |
45f9a39b | 3030 | break; |
2031f77c | 3031 | case 233: /* GUI IDLE */ |
303c805c | 3032 | DRM_DEBUG("IH: GUI idle\n"); |
2031f77c AD |
3033 | rdev->pm.gui_idle = true; |
3034 | wake_up(&rdev->irq.idle_queue); | |
3035 | break; | |
45f9a39b AD |
3036 | default: |
3037 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); | |
3038 | break; | |
3039 | } | |
3040 | ||
3041 | /* wptr/rptr are in bytes! */ | |
3042 | rptr += 16; | |
3043 | rptr &= rdev->ih.ptr_mask; | |
3044 | } | |
3045 | /* make sure wptr hasn't changed while processing */ | |
3046 | wptr = evergreen_get_ih_wptr(rdev); | |
3047 | if (wptr != rdev->ih.wptr) | |
3048 | goto restart_ih; | |
3049 | if (queue_hotplug) | |
32c87fca | 3050 | schedule_work(&rdev->hotplug_work); |
45f9a39b AD |
3051 | rdev->ih.rptr = rptr; |
3052 | WREG32(IH_RB_RPTR, rdev->ih.rptr); | |
3053 | spin_unlock_irqrestore(&rdev->ih.lock, flags); | |
3054 | return IRQ_HANDLED; | |
3055 | } | |
3056 | ||
bcc1c2a1 AD |
3057 | static int evergreen_startup(struct radeon_device *rdev) |
3058 | { | |
e32eb50d | 3059 | struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
bcc1c2a1 AD |
3060 | int r; |
3061 | ||
9e46a48d | 3062 | /* enable pcie gen2 link */ |
cd54033a | 3063 | evergreen_pcie_gen2_enable(rdev); |
9e46a48d | 3064 | |
0af62b01 AD |
3065 | if (ASIC_IS_DCE5(rdev)) { |
3066 | if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) { | |
3067 | r = ni_init_microcode(rdev); | |
3068 | if (r) { | |
3069 | DRM_ERROR("Failed to load firmware!\n"); | |
3070 | return r; | |
3071 | } | |
3072 | } | |
755d819e | 3073 | r = ni_mc_load_microcode(rdev); |
bcc1c2a1 | 3074 | if (r) { |
0af62b01 | 3075 | DRM_ERROR("Failed to load MC firmware!\n"); |
bcc1c2a1 AD |
3076 | return r; |
3077 | } | |
0af62b01 AD |
3078 | } else { |
3079 | if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) { | |
3080 | r = r600_init_microcode(rdev); | |
3081 | if (r) { | |
3082 | DRM_ERROR("Failed to load firmware!\n"); | |
3083 | return r; | |
3084 | } | |
3085 | } | |
bcc1c2a1 | 3086 | } |
fe251e2f | 3087 | |
16cdf04d AD |
3088 | r = r600_vram_scratch_init(rdev); |
3089 | if (r) | |
3090 | return r; | |
3091 | ||
bcc1c2a1 | 3092 | evergreen_mc_program(rdev); |
bcc1c2a1 | 3093 | if (rdev->flags & RADEON_IS_AGP) { |
0fcdb61e | 3094 | evergreen_agp_enable(rdev); |
bcc1c2a1 AD |
3095 | } else { |
3096 | r = evergreen_pcie_gart_enable(rdev); | |
3097 | if (r) | |
3098 | return r; | |
3099 | } | |
bcc1c2a1 | 3100 | evergreen_gpu_init(rdev); |
bcc1c2a1 | 3101 | |
d7ccd8fc | 3102 | r = evergreen_blit_init(rdev); |
bcc1c2a1 | 3103 | if (r) { |
fb3d9e97 | 3104 | r600_blit_fini(rdev); |
d7ccd8fc AD |
3105 | rdev->asic->copy = NULL; |
3106 | dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r); | |
bcc1c2a1 AD |
3107 | } |
3108 | ||
724c80e1 AD |
3109 | /* allocate wb buffer */ |
3110 | r = radeon_wb_init(rdev); | |
3111 | if (r) | |
3112 | return r; | |
3113 | ||
bcc1c2a1 AD |
3114 | /* Enable IRQ */ |
3115 | r = r600_irq_init(rdev); | |
3116 | if (r) { | |
3117 | DRM_ERROR("radeon: IH init failed (%d).\n", r); | |
3118 | radeon_irq_kms_fini(rdev); | |
3119 | return r; | |
3120 | } | |
45f9a39b | 3121 | evergreen_irq_set(rdev); |
bcc1c2a1 | 3122 | |
e32eb50d | 3123 | r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET, |
5596a9db | 3124 | R600_CP_RB_RPTR, R600_CP_RB_WPTR); |
bcc1c2a1 AD |
3125 | if (r) |
3126 | return r; | |
3127 | r = evergreen_cp_load_microcode(rdev); | |
3128 | if (r) | |
3129 | return r; | |
fe251e2f | 3130 | r = evergreen_cp_resume(rdev); |
bcc1c2a1 AD |
3131 | if (r) |
3132 | return r; | |
fe251e2f | 3133 | |
bcc1c2a1 AD |
3134 | return 0; |
3135 | } | |
3136 | ||
3137 | int evergreen_resume(struct radeon_device *rdev) | |
3138 | { | |
3139 | int r; | |
3140 | ||
86f5c9ed AD |
3141 | /* reset the asic, the gfx blocks are often in a bad state |
3142 | * after the driver is unloaded or after a resume | |
3143 | */ | |
3144 | if (radeon_asic_reset(rdev)) | |
3145 | dev_warn(rdev->dev, "GPU reset failed !\n"); | |
bcc1c2a1 AD |
3146 | /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw, |
3147 | * posting will perform necessary task to bring back GPU into good | |
3148 | * shape. | |
3149 | */ | |
3150 | /* post card */ | |
3151 | atom_asic_init(rdev->mode_info.atom_context); | |
bcc1c2a1 AD |
3152 | |
3153 | r = evergreen_startup(rdev); | |
3154 | if (r) { | |
755d819e | 3155 | DRM_ERROR("evergreen startup failed on resume\n"); |
bcc1c2a1 AD |
3156 | return r; |
3157 | } | |
fe251e2f | 3158 | |
7b1f2485 | 3159 | r = r600_ib_test(rdev, RADEON_RING_TYPE_GFX_INDEX); |
bcc1c2a1 | 3160 | if (r) { |
ec4f2ac4 | 3161 | DRM_ERROR("radeon: failed testing IB (%d).\n", r); |
bcc1c2a1 AD |
3162 | return r; |
3163 | } | |
fe251e2f | 3164 | |
bcc1c2a1 AD |
3165 | return r; |
3166 | ||
3167 | } | |
3168 | ||
3169 | int evergreen_suspend(struct radeon_device *rdev) | |
3170 | { | |
e32eb50d | 3171 | struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
7b1f2485 | 3172 | |
bcc1c2a1 AD |
3173 | /* FIXME: we should wait for ring to be empty */ |
3174 | r700_cp_stop(rdev); | |
e32eb50d | 3175 | ring->ready = false; |
45f9a39b | 3176 | evergreen_irq_suspend(rdev); |
724c80e1 | 3177 | radeon_wb_disable(rdev); |
bcc1c2a1 | 3178 | evergreen_pcie_gart_disable(rdev); |
6ddddfe7 | 3179 | r600_blit_suspend(rdev); |
d7ccd8fc AD |
3180 | |
3181 | return 0; | |
3182 | } | |
3183 | ||
bcc1c2a1 AD |
3184 | /* Plan is to move initialization in that function and use |
3185 | * helper function so that radeon_device_init pretty much | |
3186 | * do nothing more than calling asic specific function. This | |
3187 | * should also allow to remove a bunch of callback function | |
3188 | * like vram_info. | |
3189 | */ | |
3190 | int evergreen_init(struct radeon_device *rdev) | |
3191 | { | |
3192 | int r; | |
3193 | ||
bcc1c2a1 AD |
3194 | /* This don't do much */ |
3195 | r = radeon_gem_init(rdev); | |
3196 | if (r) | |
3197 | return r; | |
3198 | /* Read BIOS */ | |
3199 | if (!radeon_get_bios(rdev)) { | |
3200 | if (ASIC_IS_AVIVO(rdev)) | |
3201 | return -EINVAL; | |
3202 | } | |
3203 | /* Must be an ATOMBIOS */ | |
3204 | if (!rdev->is_atom_bios) { | |
755d819e | 3205 | dev_err(rdev->dev, "Expecting atombios for evergreen GPU\n"); |
bcc1c2a1 AD |
3206 | return -EINVAL; |
3207 | } | |
3208 | r = radeon_atombios_init(rdev); | |
3209 | if (r) | |
3210 | return r; | |
86f5c9ed AD |
3211 | /* reset the asic, the gfx blocks are often in a bad state |
3212 | * after the driver is unloaded or after a resume | |
3213 | */ | |
3214 | if (radeon_asic_reset(rdev)) | |
3215 | dev_warn(rdev->dev, "GPU reset failed !\n"); | |
bcc1c2a1 | 3216 | /* Post card if necessary */ |
fd909c37 | 3217 | if (!radeon_card_posted(rdev)) { |
bcc1c2a1 AD |
3218 | if (!rdev->bios) { |
3219 | dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); | |
3220 | return -EINVAL; | |
3221 | } | |
3222 | DRM_INFO("GPU not posted. posting now...\n"); | |
3223 | atom_asic_init(rdev->mode_info.atom_context); | |
3224 | } | |
3225 | /* Initialize scratch registers */ | |
3226 | r600_scratch_init(rdev); | |
3227 | /* Initialize surface registers */ | |
3228 | radeon_surface_init(rdev); | |
3229 | /* Initialize clocks */ | |
3230 | radeon_get_clock_info(rdev->ddev); | |
bcc1c2a1 | 3231 | /* Fence driver */ |
7465280c | 3232 | r = radeon_fence_driver_init(rdev, 1); |
bcc1c2a1 AD |
3233 | if (r) |
3234 | return r; | |
d594e46a JG |
3235 | /* initialize AGP */ |
3236 | if (rdev->flags & RADEON_IS_AGP) { | |
3237 | r = radeon_agp_init(rdev); | |
3238 | if (r) | |
3239 | radeon_agp_disable(rdev); | |
3240 | } | |
3241 | /* initialize memory controller */ | |
bcc1c2a1 AD |
3242 | r = evergreen_mc_init(rdev); |
3243 | if (r) | |
3244 | return r; | |
3245 | /* Memory manager */ | |
3246 | r = radeon_bo_init(rdev); | |
3247 | if (r) | |
3248 | return r; | |
45f9a39b | 3249 | |
bcc1c2a1 AD |
3250 | r = radeon_irq_kms_init(rdev); |
3251 | if (r) | |
3252 | return r; | |
3253 | ||
e32eb50d CK |
3254 | rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL; |
3255 | r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024); | |
bcc1c2a1 AD |
3256 | |
3257 | rdev->ih.ring_obj = NULL; | |
3258 | r600_ih_ring_init(rdev, 64 * 1024); | |
3259 | ||
3260 | r = r600_pcie_gart_init(rdev); | |
3261 | if (r) | |
3262 | return r; | |
0fcdb61e | 3263 | |
148a03bc | 3264 | rdev->accel_working = true; |
bcc1c2a1 AD |
3265 | r = evergreen_startup(rdev); |
3266 | if (r) { | |
fe251e2f AD |
3267 | dev_err(rdev->dev, "disabling GPU acceleration\n"); |
3268 | r700_cp_fini(rdev); | |
fe251e2f | 3269 | r600_irq_fini(rdev); |
724c80e1 | 3270 | radeon_wb_fini(rdev); |
fe251e2f | 3271 | radeon_irq_kms_fini(rdev); |
0fcdb61e | 3272 | evergreen_pcie_gart_fini(rdev); |
bcc1c2a1 AD |
3273 | rdev->accel_working = false; |
3274 | } | |
3275 | if (rdev->accel_working) { | |
3276 | r = radeon_ib_pool_init(rdev); | |
3277 | if (r) { | |
3278 | DRM_ERROR("radeon: failed initializing IB pool (%d).\n", r); | |
3279 | rdev->accel_working = false; | |
3280 | } | |
7b1f2485 | 3281 | r = r600_ib_test(rdev, RADEON_RING_TYPE_GFX_INDEX); |
bcc1c2a1 AD |
3282 | if (r) { |
3283 | DRM_ERROR("radeon: failed testing IB (%d).\n", r); | |
3284 | rdev->accel_working = false; | |
3285 | } | |
3286 | } | |
3287 | return 0; | |
3288 | } | |
3289 | ||
3290 | void evergreen_fini(struct radeon_device *rdev) | |
3291 | { | |
fb3d9e97 | 3292 | r600_blit_fini(rdev); |
45f9a39b | 3293 | r700_cp_fini(rdev); |
bcc1c2a1 | 3294 | r600_irq_fini(rdev); |
724c80e1 | 3295 | radeon_wb_fini(rdev); |
ccd6895d | 3296 | radeon_ib_pool_fini(rdev); |
bcc1c2a1 | 3297 | radeon_irq_kms_fini(rdev); |
bcc1c2a1 | 3298 | evergreen_pcie_gart_fini(rdev); |
16cdf04d | 3299 | r600_vram_scratch_fini(rdev); |
bcc1c2a1 | 3300 | radeon_gem_fini(rdev); |
15d3332f | 3301 | radeon_semaphore_driver_fini(rdev); |
bcc1c2a1 | 3302 | radeon_fence_driver_fini(rdev); |
bcc1c2a1 AD |
3303 | radeon_agp_fini(rdev); |
3304 | radeon_bo_fini(rdev); | |
3305 | radeon_atombios_fini(rdev); | |
3306 | kfree(rdev->bios); | |
3307 | rdev->bios = NULL; | |
bcc1c2a1 | 3308 | } |
9e46a48d | 3309 | |
b07759bf | 3310 | void evergreen_pcie_gen2_enable(struct radeon_device *rdev) |
9e46a48d AD |
3311 | { |
3312 | u32 link_width_cntl, speed_cntl; | |
3313 | ||
d42dd579 AD |
3314 | if (radeon_pcie_gen2 == 0) |
3315 | return; | |
3316 | ||
9e46a48d AD |
3317 | if (rdev->flags & RADEON_IS_IGP) |
3318 | return; | |
3319 | ||
3320 | if (!(rdev->flags & RADEON_IS_PCIE)) | |
3321 | return; | |
3322 | ||
3323 | /* x2 cards have a special sequence */ | |
3324 | if (ASIC_IS_X2(rdev)) | |
3325 | return; | |
3326 | ||
3327 | speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); | |
3328 | if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) || | |
3329 | (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) { | |
3330 | ||
3331 | link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL); | |
3332 | link_width_cntl &= ~LC_UPCONFIGURE_DIS; | |
3333 | WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); | |
3334 | ||
3335 | speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); | |
3336 | speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN; | |
3337 | WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); | |
3338 | ||
3339 | speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); | |
3340 | speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT; | |
3341 | WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); | |
3342 | ||
3343 | speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); | |
3344 | speed_cntl &= ~LC_CLR_FAILED_SPD_CHANGE_CNT; | |
3345 | WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); | |
3346 | ||
3347 | speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); | |
3348 | speed_cntl |= LC_GEN2_EN_STRAP; | |
3349 | WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); | |
3350 | ||
3351 | } else { | |
3352 | link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL); | |
3353 | /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */ | |
3354 | if (1) | |
3355 | link_width_cntl |= LC_UPCONFIGURE_DIS; | |
3356 | else | |
3357 | link_width_cntl &= ~LC_UPCONFIGURE_DIS; | |
3358 | WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); | |
3359 | } | |
3360 | } |