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Merge 2.6.38-rc5 into staging-next
[deliverable/linux.git] / drivers / gpu / drm / radeon / evergreen_blit_kms.c
CommitLineData
d7ccd8fc
AD		 1/*
2 * Copyright 2010 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Alex Deucher <alexander.deucher@amd.com>
25 */
26
27#include "drmP.h"
28#include "drm.h"
29#include "radeon_drm.h"
30#include "radeon.h"
31
32#include "evergreend.h"
33#include "evergreen_blit_shaders.h"
34
35#define DI_PT_RECTLIST 0x11
36#define DI_INDEX_SIZE_16_BIT 0x0
37#define DI_SRC_SEL_AUTO_INDEX 0x2
38
39#define FMT_8 0x1
40#define FMT_5_6_5 0x8
41#define FMT_8_8_8_8 0x1a
42#define COLOR_8 0x1
43#define COLOR_5_6_5 0x8
44#define COLOR_8_8_8_8 0x1a
45
46/* emits 17 */
47static void
48set_render_target(struct radeon_device *rdev, int format,
49 int w, int h, u64 gpu_addr)
50{
51 u32 cb_color_info;
52 int pitch, slice;
53
54 h = ALIGN(h, 8);
55 if (h < 8)
56 h = 8;
57
27dcfc10 58 cb_color_info = ((format << 2) | (1 << 24) | (1 << 8));
d7ccd8fc
AD		 59 pitch = (w / 8) - 1;
60 slice = ((w * h) / 64) - 1;
61
62 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 15));
63 radeon_ring_write(rdev, (CB_COLOR0_BASE - PACKET3_SET_CONTEXT_REG_START) >> 2);
64 radeon_ring_write(rdev, gpu_addr >> 8);
65 radeon_ring_write(rdev, pitch);
66 radeon_ring_write(rdev, slice);
67 radeon_ring_write(rdev, 0);
68 radeon_ring_write(rdev, cb_color_info);
69 radeon_ring_write(rdev, (1 << 4));
70 radeon_ring_write(rdev, (w - 1) | ((h - 1) << 16));
71 radeon_ring_write(rdev, 0);
72 radeon_ring_write(rdev, 0);
73 radeon_ring_write(rdev, 0);
74 radeon_ring_write(rdev, 0);
75 radeon_ring_write(rdev, 0);
76 radeon_ring_write(rdev, 0);
77 radeon_ring_write(rdev, 0);
78 radeon_ring_write(rdev, 0);
79}
80
81/* emits 5dw */
82static void
83cp_set_surface_sync(struct radeon_device *rdev,
84 u32 sync_type, u32 size,
85 u64 mc_addr)
86{
87 u32 cp_coher_size;
88
89 if (size == 0xffffffff)
90 cp_coher_size = 0xffffffff;
91 else
92 cp_coher_size = ((size + 255) >> 8);
93
94 radeon_ring_write(rdev, PACKET3(PACKET3_SURFACE_SYNC, 3));
95 radeon_ring_write(rdev, sync_type);
96 radeon_ring_write(rdev, cp_coher_size);
97 radeon_ring_write(rdev, mc_addr >> 8);
98 radeon_ring_write(rdev, 10); /* poll interval */
99}
100
101/* emits 11dw + 1 surface sync = 16dw */
102static void
103set_shaders(struct radeon_device *rdev)
104{
105 u64 gpu_addr;
106
107 /* VS */
108 gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset;
109 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 3));
110 radeon_ring_write(rdev, (SQ_PGM_START_VS - PACKET3_SET_CONTEXT_REG_START) >> 2);
111 radeon_ring_write(rdev, gpu_addr >> 8);
112 radeon_ring_write(rdev, 2);
113 radeon_ring_write(rdev, 0);
114
115 /* PS */
116 gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.ps_offset;
117 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 4));
118 radeon_ring_write(rdev, (SQ_PGM_START_PS - PACKET3_SET_CONTEXT_REG_START) >> 2);
119 radeon_ring_write(rdev, gpu_addr >> 8);
120 radeon_ring_write(rdev, 1);
121 radeon_ring_write(rdev, 0);
122 radeon_ring_write(rdev, 2);
123
124 gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset;
125 cp_set_surface_sync(rdev, PACKET3_SH_ACTION_ENA, 512, gpu_addr);
126}
127
128/* emits 10 + 1 sync (5) = 15 */
129static void
130set_vtx_resource(struct radeon_device *rdev, u64 gpu_addr)
131{
132 u32 sq_vtx_constant_word2, sq_vtx_constant_word3;
133
134 /* high addr, stride */
135 sq_vtx_constant_word2 = ((upper_32_bits(gpu_addr) & 0xff) | (16 << 8));
0f234f5f
AD		 136#ifdef __BIG_ENDIAN
137 sq_vtx_constant_word2 |= (2 << 30);
138#endif
d7ccd8fc
AD		 139 /* xyzw swizzles */
140 sq_vtx_constant_word3 = (0 << 3) | (1 << 6) | (2 << 9) | (3 << 12);
141
142 radeon_ring_write(rdev, PACKET3(PACKET3_SET_RESOURCE, 8));
143 radeon_ring_write(rdev, 0x580);
144 radeon_ring_write(rdev, gpu_addr & 0xffffffff);
145 radeon_ring_write(rdev, 48 - 1); /* size */
146 radeon_ring_write(rdev, sq_vtx_constant_word2);
147 radeon_ring_write(rdev, sq_vtx_constant_word3);
148 radeon_ring_write(rdev, 0);
149 radeon_ring_write(rdev, 0);
150 radeon_ring_write(rdev, 0);
151 radeon_ring_write(rdev, SQ_TEX_VTX_VALID_BUFFER << 30);
152
e719ebd9 153 if ((rdev->family == CHIP_CEDAR) ||
ff5b8562
AD		 154 (rdev->family == CHIP_PALM) ||
155 (rdev->family == CHIP_CAICOS))
d7ccd8fc
AD		 156 cp_set_surface_sync(rdev,
157 PACKET3_TC_ACTION_ENA, 48, gpu_addr);
158 else
159 cp_set_surface_sync(rdev,
160 PACKET3_VC_ACTION_ENA, 48, gpu_addr);
161
162}
163
164/* emits 10 */
165static void
166set_tex_resource(struct radeon_device *rdev,
167 int format, int w, int h, int pitch,
168 u64 gpu_addr)
169{
170 u32 sq_tex_resource_word0, sq_tex_resource_word1;
171 u32 sq_tex_resource_word4, sq_tex_resource_word7;
172
173 if (h < 1)
174 h = 1;
175
176 sq_tex_resource_word0 = (1 << 0); /* 2D */
177 sq_tex_resource_word0 |= ((((pitch >> 3) - 1) << 6) |
178 ((w - 1) << 18));
27dcfc10 179 sq_tex_resource_word1 = ((h - 1) << 0) | (1 << 28);
d7ccd8fc
AD		 180 /* xyzw swizzles */
181 sq_tex_resource_word4 = (0 << 16) | (1 << 19) | (2 << 22) | (3 << 25);
182
183 sq_tex_resource_word7 = format | (SQ_TEX_VTX_VALID_TEXTURE << 30);
184
185 radeon_ring_write(rdev, PACKET3(PACKET3_SET_RESOURCE, 8));
186 radeon_ring_write(rdev, 0);
187 radeon_ring_write(rdev, sq_tex_resource_word0);
188 radeon_ring_write(rdev, sq_tex_resource_word1);
189 radeon_ring_write(rdev, gpu_addr >> 8);
190 radeon_ring_write(rdev, gpu_addr >> 8);
191 radeon_ring_write(rdev, sq_tex_resource_word4);
192 radeon_ring_write(rdev, 0);
193 radeon_ring_write(rdev, 0);
194 radeon_ring_write(rdev, sq_tex_resource_word7);
195}
196
197/* emits 12 */
198static void
199set_scissors(struct radeon_device *rdev, int x1, int y1,
200 int x2, int y2)
201{
202 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
203 radeon_ring_write(rdev, (PA_SC_SCREEN_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_START) >> 2);
204 radeon_ring_write(rdev, (x1 << 0) | (y1 << 16));
205 radeon_ring_write(rdev, (x2 << 0) | (y2 << 16));
206
207 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
208 radeon_ring_write(rdev, (PA_SC_GENERIC_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_START) >> 2);
209 radeon_ring_write(rdev, (x1 << 0) | (y1 << 16) | (1 << 31));
210 radeon_ring_write(rdev, (x2 << 0) | (y2 << 16));
211
212 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
213 radeon_ring_write(rdev, (PA_SC_WINDOW_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_START) >> 2);
214 radeon_ring_write(rdev, (x1 << 0) | (y1 << 16) | (1 << 31));
215 radeon_ring_write(rdev, (x2 << 0) | (y2 << 16));
216}
217
218/* emits 10 */
219static void
220draw_auto(struct radeon_device *rdev)
221{
222 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
223 radeon_ring_write(rdev, (VGT_PRIMITIVE_TYPE - PACKET3_SET_CONFIG_REG_START) >> 2);
224 radeon_ring_write(rdev, DI_PT_RECTLIST);
225
226 radeon_ring_write(rdev, PACKET3(PACKET3_INDEX_TYPE, 0));
0f234f5f
AD		 227 radeon_ring_write(rdev,
228#ifdef __BIG_ENDIAN
229 (2 << 2) |
230#endif
231 DI_INDEX_SIZE_16_BIT);
d7ccd8fc
AD		 232
233 radeon_ring_write(rdev, PACKET3(PACKET3_NUM_INSTANCES, 0));
234 radeon_ring_write(rdev, 1);
235
236 radeon_ring_write(rdev, PACKET3(PACKET3_DRAW_INDEX_AUTO, 1));
237 radeon_ring_write(rdev, 3);
238 radeon_ring_write(rdev, DI_SRC_SEL_AUTO_INDEX);
239
240}
241
12920591 242/* emits 36 */
d7ccd8fc
AD		 243static void
244set_default_state(struct radeon_device *rdev)
245{
246 u32 sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2, sq_gpr_resource_mgmt_3;
247 u32 sq_thread_resource_mgmt, sq_thread_resource_mgmt_2;
248 u32 sq_stack_resource_mgmt_1, sq_stack_resource_mgmt_2, sq_stack_resource_mgmt_3;
249 int num_ps_gprs, num_vs_gprs, num_temp_gprs;
250 int num_gs_gprs, num_es_gprs, num_hs_gprs, num_ls_gprs;
251 int num_ps_threads, num_vs_threads, num_gs_threads, num_es_threads;
252 int num_hs_threads, num_ls_threads;
253 int num_ps_stack_entries, num_vs_stack_entries, num_gs_stack_entries, num_es_stack_entries;
254 int num_hs_stack_entries, num_ls_stack_entries;
1e644d6d
AD		 255 u64 gpu_addr;
256 int dwords;
d7ccd8fc
AD		 257
258 switch (rdev->family) {
259 case CHIP_CEDAR:
260 default:
261 num_ps_gprs = 93;
262 num_vs_gprs = 46;
263 num_temp_gprs = 4;
264 num_gs_gprs = 31;
265 num_es_gprs = 31;
266 num_hs_gprs = 23;
267 num_ls_gprs = 23;
268 num_ps_threads = 96;
269 num_vs_threads = 16;
270 num_gs_threads = 16;
271 num_es_threads = 16;
272 num_hs_threads = 16;
273 num_ls_threads = 16;
274 num_ps_stack_entries = 42;
275 num_vs_stack_entries = 42;
276 num_gs_stack_entries = 42;
277 num_es_stack_entries = 42;
278 num_hs_stack_entries = 42;
279 num_ls_stack_entries = 42;
280 break;
281 case CHIP_REDWOOD:
282 num_ps_gprs = 93;
283 num_vs_gprs = 46;
284 num_temp_gprs = 4;
285 num_gs_gprs = 31;
286 num_es_gprs = 31;
287 num_hs_gprs = 23;
288 num_ls_gprs = 23;
289 num_ps_threads = 128;
290 num_vs_threads = 20;
291 num_gs_threads = 20;
292 num_es_threads = 20;
293 num_hs_threads = 20;
294 num_ls_threads = 20;
295 num_ps_stack_entries = 42;
296 num_vs_stack_entries = 42;
297 num_gs_stack_entries = 42;
298 num_es_stack_entries = 42;
299 num_hs_stack_entries = 42;
300 num_ls_stack_entries = 42;
301 break;
302 case CHIP_JUNIPER:
303 num_ps_gprs = 93;
304 num_vs_gprs = 46;
305 num_temp_gprs = 4;
306 num_gs_gprs = 31;
307 num_es_gprs = 31;
308 num_hs_gprs = 23;
309 num_ls_gprs = 23;
310 num_ps_threads = 128;
311 num_vs_threads = 20;
312 num_gs_threads = 20;
313 num_es_threads = 20;
314 num_hs_threads = 20;
315 num_ls_threads = 20;
316 num_ps_stack_entries = 85;
317 num_vs_stack_entries = 85;
318 num_gs_stack_entries = 85;
319 num_es_stack_entries = 85;
320 num_hs_stack_entries = 85;
321 num_ls_stack_entries = 85;
322 break;
323 case CHIP_CYPRESS:
324 case CHIP_HEMLOCK:
325 num_ps_gprs = 93;
326 num_vs_gprs = 46;
327 num_temp_gprs = 4;
328 num_gs_gprs = 31;
329 num_es_gprs = 31;
330 num_hs_gprs = 23;
331 num_ls_gprs = 23;
332 num_ps_threads = 128;
333 num_vs_threads = 20;
334 num_gs_threads = 20;
335 num_es_threads = 20;
336 num_hs_threads = 20;
337 num_ls_threads = 20;
338 num_ps_stack_entries = 85;
339 num_vs_stack_entries = 85;
340 num_gs_stack_entries = 85;
341 num_es_stack_entries = 85;
342 num_hs_stack_entries = 85;
343 num_ls_stack_entries = 85;
344 break;
e719ebd9
AD		 345 case CHIP_PALM:
346 num_ps_gprs = 93;
347 num_vs_gprs = 46;
348 num_temp_gprs = 4;
349 num_gs_gprs = 31;
350 num_es_gprs = 31;
351 num_hs_gprs = 23;
352 num_ls_gprs = 23;
353 num_ps_threads = 96;
354 num_vs_threads = 16;
355 num_gs_threads = 16;
356 num_es_threads = 16;
357 num_hs_threads = 16;
358 num_ls_threads = 16;
359 num_ps_stack_entries = 42;
360 num_vs_stack_entries = 42;
361 num_gs_stack_entries = 42;
362 num_es_stack_entries = 42;
363 num_hs_stack_entries = 42;
364 num_ls_stack_entries = 42;
365 break;
ff5b8562
AD		 366 case CHIP_BARTS:
367 num_ps_gprs = 93;
368 num_vs_gprs = 46;
369 num_temp_gprs = 4;
370 num_gs_gprs = 31;
371 num_es_gprs = 31;
372 num_hs_gprs = 23;
373 num_ls_gprs = 23;
374 num_ps_threads = 128;
375 num_vs_threads = 20;
376 num_gs_threads = 20;
377 num_es_threads = 20;
378 num_hs_threads = 20;
379 num_ls_threads = 20;
380 num_ps_stack_entries = 85;
381 num_vs_stack_entries = 85;
382 num_gs_stack_entries = 85;
383 num_es_stack_entries = 85;
384 num_hs_stack_entries = 85;
385 num_ls_stack_entries = 85;
386 break;
387 case CHIP_TURKS:
388 num_ps_gprs = 93;
389 num_vs_gprs = 46;
390 num_temp_gprs = 4;
391 num_gs_gprs = 31;
392 num_es_gprs = 31;
393 num_hs_gprs = 23;
394 num_ls_gprs = 23;
395 num_ps_threads = 128;
396 num_vs_threads = 20;
397 num_gs_threads = 20;
398 num_es_threads = 20;
399 num_hs_threads = 20;
400 num_ls_threads = 20;
401 num_ps_stack_entries = 42;
402 num_vs_stack_entries = 42;
403 num_gs_stack_entries = 42;
404 num_es_stack_entries = 42;
405 num_hs_stack_entries = 42;
406 num_ls_stack_entries = 42;
407 break;
408 case CHIP_CAICOS:
409 num_ps_gprs = 93;
410 num_vs_gprs = 46;
411 num_temp_gprs = 4;
412 num_gs_gprs = 31;
413 num_es_gprs = 31;
414 num_hs_gprs = 23;
415 num_ls_gprs = 23;
416 num_ps_threads = 128;
417 num_vs_threads = 10;
418 num_gs_threads = 10;
419 num_es_threads = 10;
420 num_hs_threads = 10;
421 num_ls_threads = 10;
422 num_ps_stack_entries = 42;
423 num_vs_stack_entries = 42;
424 num_gs_stack_entries = 42;
425 num_es_stack_entries = 42;
426 num_hs_stack_entries = 42;
427 num_ls_stack_entries = 42;
428 break;
d7ccd8fc
AD		 429 }
430
e719ebd9 431 if ((rdev->family == CHIP_CEDAR) ||
ff5b8562
AD		 432 (rdev->family == CHIP_PALM) ||
433 (rdev->family == CHIP_CAICOS))
d7ccd8fc
AD		 434 sq_config = 0;
435 else
436 sq_config = VC_ENABLE;
437
438 sq_config |= (EXPORT_SRC_C |
439 CS_PRIO(0) |
440 LS_PRIO(0) |
441 HS_PRIO(0) |
442 PS_PRIO(0) |
443 VS_PRIO(1) |
444 GS_PRIO(2) |
445 ES_PRIO(3));
446
447 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(num_ps_gprs) |
448 NUM_VS_GPRS(num_vs_gprs) |
449 NUM_CLAUSE_TEMP_GPRS(num_temp_gprs));
450 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(num_gs_gprs) |
451 NUM_ES_GPRS(num_es_gprs));
452 sq_gpr_resource_mgmt_3 = (NUM_HS_GPRS(num_hs_gprs) |
453 NUM_LS_GPRS(num_ls_gprs));
454 sq_thread_resource_mgmt = (NUM_PS_THREADS(num_ps_threads) |
455 NUM_VS_THREADS(num_vs_threads) |
456 NUM_GS_THREADS(num_gs_threads) |
457 NUM_ES_THREADS(num_es_threads));
458 sq_thread_resource_mgmt_2 = (NUM_HS_THREADS(num_hs_threads) |
459 NUM_LS_THREADS(num_ls_threads));
460 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(num_ps_stack_entries) |
461 NUM_VS_STACK_ENTRIES(num_vs_stack_entries));
462 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(num_gs_stack_entries) |
463 NUM_ES_STACK_ENTRIES(num_es_stack_entries));
464 sq_stack_resource_mgmt_3 = (NUM_HS_STACK_ENTRIES(num_hs_stack_entries) |
465 NUM_LS_STACK_ENTRIES(num_ls_stack_entries));
466
2281a378
AD		 467 /* set clear context state */
468 radeon_ring_write(rdev, PACKET3(PACKET3_CLEAR_STATE, 0));
469 radeon_ring_write(rdev, 0);
d7ccd8fc
AD		 470
471 /* disable dyn gprs */
472 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
473 radeon_ring_write(rdev, (SQ_DYN_GPR_CNTL_PS_FLUSH_REQ - PACKET3_SET_CONFIG_REG_START) >> 2);
474 radeon_ring_write(rdev, 0);
475
476 /* SQ config */
477 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 11));
478 radeon_ring_write(rdev, (SQ_CONFIG - PACKET3_SET_CONFIG_REG_START) >> 2);
479 radeon_ring_write(rdev, sq_config);
480 radeon_ring_write(rdev, sq_gpr_resource_mgmt_1);
481 radeon_ring_write(rdev, sq_gpr_resource_mgmt_2);
482 radeon_ring_write(rdev, sq_gpr_resource_mgmt_3);
483 radeon_ring_write(rdev, 0);
484 radeon_ring_write(rdev, 0);
485 radeon_ring_write(rdev, sq_thread_resource_mgmt);
486 radeon_ring_write(rdev, sq_thread_resource_mgmt_2);
487 radeon_ring_write(rdev, sq_stack_resource_mgmt_1);
488 radeon_ring_write(rdev, sq_stack_resource_mgmt_2);
489 radeon_ring_write(rdev, sq_stack_resource_mgmt_3);
2281a378
AD		 490
491 /* CONTEXT_CONTROL */
492 radeon_ring_write(rdev, 0xc0012800);
493 radeon_ring_write(rdev, 0x80000000);
494 radeon_ring_write(rdev, 0x80000000);
495
496 /* SQ_VTX_BASE_VTX_LOC */
497 radeon_ring_write(rdev, 0xc0026f00);
498 radeon_ring_write(rdev, 0x00000000);
499 radeon_ring_write(rdev, 0x00000000);
500 radeon_ring_write(rdev, 0x00000000);
501
502 /* SET_SAMPLER */
503 radeon_ring_write(rdev, 0xc0036e00);
504 radeon_ring_write(rdev, 0x00000000);
505 radeon_ring_write(rdev, 0x00000012);
506 radeon_ring_write(rdev, 0x00000000);
507 radeon_ring_write(rdev, 0x00000000);
508
12920591
AD		 509 /* set to DX10/11 mode */
510 radeon_ring_write(rdev, PACKET3(PACKET3_MODE_CONTROL, 0));
511 radeon_ring_write(rdev, 1);
512
1e644d6d
AD		 513 /* emit an IB pointing at default state */
514 dwords = ALIGN(rdev->r600_blit.state_len, 0x10);
515 gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.state_offset;
516 radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
517 radeon_ring_write(rdev, gpu_addr & 0xFFFFFFFC);
518 radeon_ring_write(rdev, upper_32_bits(gpu_addr) & 0xFF);
519 radeon_ring_write(rdev, dwords);
520
d7ccd8fc
AD		 521}
522
523static inline uint32_t i2f(uint32_t input)
524{
525 u32 result, i, exponent, fraction;
526
527 if ((input & 0x3fff) == 0)
528 result = 0; /* 0 is a special case */
529 else {
530 exponent = 140; /* exponent biased by 127; */
531 fraction = (input & 0x3fff) << 10; /* cheat and only
532 handle numbers below 2^^15 */
533 for (i = 0; i < 14; i++) {
534 if (fraction & 0x800000)
535 break;
536 else {
537 fraction = fraction << 1; /* keep
538 shifting left until top bit = 1 */
539 exponent = exponent - 1;
540 }
541 }
542 result = exponent << 23 | (fraction & 0x7fffff); /* mask
543 off top bit; assumed 1 */
544 }
545 return result;
546}
547
548int evergreen_blit_init(struct radeon_device *rdev)
549{
550 u32 obj_size;
0f234f5f 551 int i, r, dwords;
d7ccd8fc 552 void *ptr;
1e644d6d
AD		 553 u32 packet2s[16];
554 int num_packet2s = 0;
d7ccd8fc
AD		 555
556 /* pin copy shader into vram if already initialized */
557 if (rdev->r600_blit.shader_obj)
558 goto done;
559
560 mutex_init(&rdev->r600_blit.mutex);
561 rdev->r600_blit.state_offset = 0;
1e644d6d
AD		 562
563 rdev->r600_blit.state_len = evergreen_default_size;
564
565 dwords = rdev->r600_blit.state_len;
566 while (dwords & 0xf) {
0f234f5f 567 packet2s[num_packet2s++] = cpu_to_le32(PACKET2(0));
1e644d6d
AD		 568 dwords++;
569 }
570
571 obj_size = dwords * 4;
572 obj_size = ALIGN(obj_size, 256);
d7ccd8fc
AD		 573
574 rdev->r600_blit.vs_offset = obj_size;
575 obj_size += evergreen_vs_size * 4;
576 obj_size = ALIGN(obj_size, 256);
577
578 rdev->r600_blit.ps_offset = obj_size;
579 obj_size += evergreen_ps_size * 4;
580 obj_size = ALIGN(obj_size, 256);
581
268b2510 582 r = radeon_bo_create(rdev, NULL, obj_size, PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
d7ccd8fc
AD		 583 &rdev->r600_blit.shader_obj);
584 if (r) {
585 DRM_ERROR("evergreen failed to allocate shader\n");
586 return r;
587 }
588
589 DRM_DEBUG("evergreen blit allocated bo %08x vs %08x ps %08x\n",
590 obj_size,
591 rdev->r600_blit.vs_offset, rdev->r600_blit.ps_offset);
592
593 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
594 if (unlikely(r != 0))
595 return r;
596 r = radeon_bo_kmap(rdev->r600_blit.shader_obj, &ptr);
597 if (r) {
598 DRM_ERROR("failed to map blit object %d\n", r);
599 return r;
600 }
601
1e644d6d
AD		 602 memcpy_toio(ptr + rdev->r600_blit.state_offset,
603 evergreen_default_state, rdev->r600_blit.state_len * 4);
604
605 if (num_packet2s)
606 memcpy_toio(ptr + rdev->r600_blit.state_offset + (rdev->r600_blit.state_len * 4),
607 packet2s, num_packet2s * 4);
0f234f5f
AD		 608 for (i = 0; i < evergreen_vs_size; i++)
609 *(u32 *)((unsigned long)ptr + rdev->r600_blit.vs_offset + i * 4) = cpu_to_le32(evergreen_vs[i]);
610 for (i = 0; i < evergreen_ps_size; i++)
611 *(u32 *)((unsigned long)ptr + rdev->r600_blit.ps_offset + i * 4) = cpu_to_le32(evergreen_ps[i]);
d7ccd8fc
AD		 612 radeon_bo_kunmap(rdev->r600_blit.shader_obj);
613 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
614
615done:
616 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
617 if (unlikely(r != 0))
618 return r;
619 r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
620 &rdev->r600_blit.shader_gpu_addr);
621 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
622 if (r) {
623 dev_err(rdev->dev, "(%d) pin blit object failed\n", r);
624 return r;
625 }
7e942503 626 rdev->mc.active_vram_size = rdev->mc.real_vram_size;
d7ccd8fc
AD		 627 return 0;
628}
629
630void evergreen_blit_fini(struct radeon_device *rdev)
631{
632 int r;
633
7e942503 634 rdev->mc.active_vram_size = rdev->mc.visible_vram_size;
d7ccd8fc
AD		 635 if (rdev->r600_blit.shader_obj == NULL)
636 return;
637 /* If we can't reserve the bo, unref should be enough to destroy
638 * it when it becomes idle.
639 */
640 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
641 if (!r) {
642 radeon_bo_unpin(rdev->r600_blit.shader_obj);
643 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
644 }
645 radeon_bo_unref(&rdev->r600_blit.shader_obj);
646}
647
648static int evergreen_vb_ib_get(struct radeon_device *rdev)
649{
650 int r;
651 r = radeon_ib_get(rdev, &rdev->r600_blit.vb_ib);
652 if (r) {
653 DRM_ERROR("failed to get IB for vertex buffer\n");
654 return r;
655 }
656
657 rdev->r600_blit.vb_total = 64*1024;
658 rdev->r600_blit.vb_used = 0;
659 return 0;
660}
661
662static void evergreen_vb_ib_put(struct radeon_device *rdev)
663{
664 radeon_fence_emit(rdev, rdev->r600_blit.vb_ib->fence);
665 radeon_ib_free(rdev, &rdev->r600_blit.vb_ib);
666}
667
668int evergreen_blit_prepare_copy(struct radeon_device *rdev, int size_bytes)
669{
670 int r;
671 int ring_size, line_size;
672 int max_size;
673 /* loops of emits + fence emit possible */
674 int dwords_per_loop = 74, num_loops;
675
676 r = evergreen_vb_ib_get(rdev);
677 if (r)
678 return r;
679
680 /* 8 bpp vs 32 bpp for xfer unit */
681 if (size_bytes & 3)
682 line_size = 8192;
683 else
684 line_size = 8192 * 4;
685
686 max_size = 8192 * line_size;
687
688 /* major loops cover the max size transfer */
689 num_loops = ((size_bytes + max_size) / max_size);
690 /* minor loops cover the extra non aligned bits */
691 num_loops += ((size_bytes % line_size) ? 1 : 0);
692 /* calculate number of loops correctly */
693 ring_size = num_loops * dwords_per_loop;
694 /* set default + shaders */
12920591 695 ring_size += 52; /* shaders + def state */
d7ccd8fc
AD		 696 ring_size += 10; /* fence emit for VB IB */
697 ring_size += 5; /* done copy */
698 ring_size += 10; /* fence emit for done copy */
699 r = radeon_ring_lock(rdev, ring_size);
700 if (r)
701 return r;
702
12920591 703 set_default_state(rdev); /* 36 */
d7ccd8fc
AD		 704 set_shaders(rdev); /* 16 */
705 return 0;
706}
707
708void evergreen_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence)
709{
710 int r;
711
712 if (rdev->r600_blit.vb_ib)
713 evergreen_vb_ib_put(rdev);
714
715 if (fence)
716 r = radeon_fence_emit(rdev, fence);
717
718 radeon_ring_unlock_commit(rdev);
719}
720
721void evergreen_kms_blit_copy(struct radeon_device *rdev,
722 u64 src_gpu_addr, u64 dst_gpu_addr,
723 int size_bytes)
724{
725 int max_bytes;
726 u64 vb_gpu_addr;
727 u32 *vb;
728
729 DRM_DEBUG("emitting copy %16llx %16llx %d %d\n", src_gpu_addr, dst_gpu_addr,
730 size_bytes, rdev->r600_blit.vb_used);
731 vb = (u32 *)(rdev->r600_blit.vb_ib->ptr + rdev->r600_blit.vb_used);
732 if ((size_bytes & 3) || (src_gpu_addr & 3) || (dst_gpu_addr & 3)) {
733 max_bytes = 8192;
734
735 while (size_bytes) {
736 int cur_size = size_bytes;
737 int src_x = src_gpu_addr & 255;
738 int dst_x = dst_gpu_addr & 255;
739 int h = 1;
2126d0a4
AD		 740 src_gpu_addr = src_gpu_addr & ~255ULL;
741 dst_gpu_addr = dst_gpu_addr & ~255ULL;
d7ccd8fc
AD		 742
743 if (!src_x && !dst_x) {
744 h = (cur_size / max_bytes);
745 if (h > 8192)
746 h = 8192;
747 if (h == 0)
748 h = 1;
749 else
750 cur_size = max_bytes;
751 } else {
752 if (cur_size > max_bytes)
753 cur_size = max_bytes;
754 if (cur_size > (max_bytes - dst_x))
755 cur_size = (max_bytes - dst_x);
756 if (cur_size > (max_bytes - src_x))
757 cur_size = (max_bytes - src_x);
758 }
759
760 if ((rdev->r600_blit.vb_used + 48) > rdev->r600_blit.vb_total) {
761 WARN_ON(1);
762 }
763
764 vb[0] = i2f(dst_x);
765 vb[1] = 0;
766 vb[2] = i2f(src_x);
767 vb[3] = 0;
768
769 vb[4] = i2f(dst_x);
770 vb[5] = i2f(h);
771 vb[6] = i2f(src_x);
772 vb[7] = i2f(h);
773
774 vb[8] = i2f(dst_x + cur_size);
775 vb[9] = i2f(h);
776 vb[10] = i2f(src_x + cur_size);
777 vb[11] = i2f(h);
778
779 /* src 10 */
780 set_tex_resource(rdev, FMT_8,
781 src_x + cur_size, h, src_x + cur_size,
782 src_gpu_addr);
783
784 /* 5 */
785 cp_set_surface_sync(rdev,
786 PACKET3_TC_ACTION_ENA, (src_x + cur_size * h), src_gpu_addr);
787
788
789 /* dst 17 */
790 set_render_target(rdev, COLOR_8,
791 dst_x + cur_size, h,
792 dst_gpu_addr);
793
794 /* scissors 12 */
795 set_scissors(rdev, dst_x, 0, dst_x + cur_size, h);
796
797 /* 15 */
798 vb_gpu_addr = rdev->r600_blit.vb_ib->gpu_addr + rdev->r600_blit.vb_used;
799 set_vtx_resource(rdev, vb_gpu_addr);
800
801 /* draw 10 */
802 draw_auto(rdev);
803
804 /* 5 */
805 cp_set_surface_sync(rdev,
806 PACKET3_CB_ACTION_ENA | PACKET3_CB0_DEST_BASE_ENA,
807 cur_size * h, dst_gpu_addr);
808
809 vb += 12;
810 rdev->r600_blit.vb_used += 12 * 4;
811
812 src_gpu_addr += cur_size * h;
813 dst_gpu_addr += cur_size * h;
814 size_bytes -= cur_size * h;
815 }
816 } else {
817 max_bytes = 8192 * 4;
818
819 while (size_bytes) {
820 int cur_size = size_bytes;
821 int src_x = (src_gpu_addr & 255);
822 int dst_x = (dst_gpu_addr & 255);
823 int h = 1;
2126d0a4
AD		 824 src_gpu_addr = src_gpu_addr & ~255ULL;
825 dst_gpu_addr = dst_gpu_addr & ~255ULL;
d7ccd8fc
AD		 826
827 if (!src_x && !dst_x) {
828 h = (cur_size / max_bytes);
829 if (h > 8192)
830 h = 8192;
831 if (h == 0)
832 h = 1;
833 else
834 cur_size = max_bytes;
835 } else {
836 if (cur_size > max_bytes)
837 cur_size = max_bytes;
838 if (cur_size > (max_bytes - dst_x))
839 cur_size = (max_bytes - dst_x);
840 if (cur_size > (max_bytes - src_x))
841 cur_size = (max_bytes - src_x);
842 }
843
844 if ((rdev->r600_blit.vb_used + 48) > rdev->r600_blit.vb_total) {
845 WARN_ON(1);
846 }
847
848 vb[0] = i2f(dst_x / 4);
849 vb[1] = 0;
850 vb[2] = i2f(src_x / 4);
851 vb[3] = 0;
852
853 vb[4] = i2f(dst_x / 4);
854 vb[5] = i2f(h);
855 vb[6] = i2f(src_x / 4);
856 vb[7] = i2f(h);
857
858 vb[8] = i2f((dst_x + cur_size) / 4);
859 vb[9] = i2f(h);
860 vb[10] = i2f((src_x + cur_size) / 4);
861 vb[11] = i2f(h);
862
863 /* src 10 */
864 set_tex_resource(rdev, FMT_8_8_8_8,
865 (src_x + cur_size) / 4,
866 h, (src_x + cur_size) / 4,
867 src_gpu_addr);
868 /* 5 */
869 cp_set_surface_sync(rdev,
870 PACKET3_TC_ACTION_ENA, (src_x + cur_size * h), src_gpu_addr);
871
872 /* dst 17 */
873 set_render_target(rdev, COLOR_8_8_8_8,
874 (dst_x + cur_size) / 4, h,
875 dst_gpu_addr);
876
877 /* scissors 12 */
878 set_scissors(rdev, (dst_x / 4), 0, (dst_x + cur_size / 4), h);
879
880 /* Vertex buffer setup 15 */
881 vb_gpu_addr = rdev->r600_blit.vb_ib->gpu_addr + rdev->r600_blit.vb_used;
882 set_vtx_resource(rdev, vb_gpu_addr);
883
884 /* draw 10 */
885 draw_auto(rdev);
886
887 /* 5 */
888 cp_set_surface_sync(rdev,
889 PACKET3_CB_ACTION_ENA | PACKET3_CB0_DEST_BASE_ENA,
890 cur_size * h, dst_gpu_addr);
891
892 /* 74 ring dwords per loop */
893 vb += 12;
894 rdev->r600_blit.vb_used += 12 * 4;
895
896 src_gpu_addr += cur_size * h;
897 dst_gpu_addr += cur_size * h;
898 size_bytes -= cur_size * h;
899 }
900 }
901}
902
Linux kernel - Deliverables
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