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cb5fcbd5 AD |
1 | /* |
2 | * Copyright 2010 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
28 | #include "drmP.h" | |
29 | #include "radeon.h" | |
30 | #include "evergreend.h" | |
31 | #include "evergreen_reg_safe.h" | |
c175ca9a | 32 | #include "cayman_reg_safe.h" |
cb5fcbd5 | 33 | |
285484e2 JG |
34 | #define MAX(a,b) (((a)>(b))?(a):(b)) |
35 | #define MIN(a,b) (((a)<(b))?(a):(b)) | |
36 | ||
cb5fcbd5 AD |
37 | static int evergreen_cs_packet_next_reloc(struct radeon_cs_parser *p, |
38 | struct radeon_cs_reloc **cs_reloc); | |
39 | ||
40 | struct evergreen_cs_track { | |
41 | u32 group_size; | |
42 | u32 nbanks; | |
43 | u32 npipes; | |
f3a71df0 | 44 | u32 row_size; |
cb5fcbd5 AD |
45 | /* value we track */ |
46 | u32 nsamples; | |
47 | u32 cb_color_base_last[12]; | |
48 | struct radeon_bo *cb_color_bo[12]; | |
49 | u32 cb_color_bo_offset[12]; | |
50 | struct radeon_bo *cb_color_fmask_bo[8]; | |
51 | struct radeon_bo *cb_color_cmask_bo[8]; | |
52 | u32 cb_color_info[12]; | |
53 | u32 cb_color_view[12]; | |
54 | u32 cb_color_pitch_idx[12]; | |
55 | u32 cb_color_slice_idx[12]; | |
56 | u32 cb_color_dim_idx[12]; | |
57 | u32 cb_color_dim[12]; | |
58 | u32 cb_color_pitch[12]; | |
59 | u32 cb_color_slice[12]; | |
285484e2 | 60 | u32 cb_color_attrib[12]; |
cb5fcbd5 AD |
61 | u32 cb_color_cmask_slice[8]; |
62 | u32 cb_color_fmask_slice[8]; | |
63 | u32 cb_target_mask; | |
64 | u32 cb_shader_mask; | |
65 | u32 vgt_strmout_config; | |
66 | u32 vgt_strmout_buffer_config; | |
dd220a00 MO |
67 | struct radeon_bo *vgt_strmout_bo[4]; |
68 | u64 vgt_strmout_bo_mc[4]; | |
69 | u32 vgt_strmout_bo_offset[4]; | |
70 | u32 vgt_strmout_size[4]; | |
cb5fcbd5 AD |
71 | u32 db_depth_control; |
72 | u32 db_depth_view; | |
285484e2 | 73 | u32 db_depth_slice; |
cb5fcbd5 AD |
74 | u32 db_depth_size; |
75 | u32 db_depth_size_idx; | |
76 | u32 db_z_info; | |
77 | u32 db_z_idx; | |
78 | u32 db_z_read_offset; | |
79 | u32 db_z_write_offset; | |
80 | struct radeon_bo *db_z_read_bo; | |
81 | struct radeon_bo *db_z_write_bo; | |
82 | u32 db_s_info; | |
83 | u32 db_s_idx; | |
84 | u32 db_s_read_offset; | |
85 | u32 db_s_write_offset; | |
86 | struct radeon_bo *db_s_read_bo; | |
87 | struct radeon_bo *db_s_write_bo; | |
779923bc | 88 | bool sx_misc_kill_all_prims; |
cb5fcbd5 AD |
89 | }; |
90 | ||
f3a71df0 AD |
91 | static u32 evergreen_cs_get_aray_mode(u32 tiling_flags) |
92 | { | |
93 | if (tiling_flags & RADEON_TILING_MACRO) | |
94 | return ARRAY_2D_TILED_THIN1; | |
95 | else if (tiling_flags & RADEON_TILING_MICRO) | |
96 | return ARRAY_1D_TILED_THIN1; | |
97 | else | |
98 | return ARRAY_LINEAR_GENERAL; | |
99 | } | |
100 | ||
101 | static u32 evergreen_cs_get_num_banks(u32 nbanks) | |
102 | { | |
103 | switch (nbanks) { | |
104 | case 2: | |
105 | return ADDR_SURF_2_BANK; | |
106 | case 4: | |
107 | return ADDR_SURF_4_BANK; | |
108 | case 8: | |
109 | default: | |
110 | return ADDR_SURF_8_BANK; | |
111 | case 16: | |
112 | return ADDR_SURF_16_BANK; | |
113 | } | |
114 | } | |
115 | ||
cb5fcbd5 AD |
116 | static void evergreen_cs_track_init(struct evergreen_cs_track *track) |
117 | { | |
118 | int i; | |
119 | ||
120 | for (i = 0; i < 8; i++) { | |
121 | track->cb_color_fmask_bo[i] = NULL; | |
122 | track->cb_color_cmask_bo[i] = NULL; | |
123 | track->cb_color_cmask_slice[i] = 0; | |
124 | track->cb_color_fmask_slice[i] = 0; | |
125 | } | |
126 | ||
127 | for (i = 0; i < 12; i++) { | |
128 | track->cb_color_base_last[i] = 0; | |
129 | track->cb_color_bo[i] = NULL; | |
130 | track->cb_color_bo_offset[i] = 0xFFFFFFFF; | |
131 | track->cb_color_info[i] = 0; | |
285484e2 | 132 | track->cb_color_view[i] = 0xFFFFFFFF; |
cb5fcbd5 AD |
133 | track->cb_color_pitch_idx[i] = 0; |
134 | track->cb_color_slice_idx[i] = 0; | |
135 | track->cb_color_dim[i] = 0; | |
136 | track->cb_color_pitch[i] = 0; | |
137 | track->cb_color_slice[i] = 0; | |
138 | track->cb_color_dim[i] = 0; | |
139 | } | |
140 | track->cb_target_mask = 0xFFFFFFFF; | |
141 | track->cb_shader_mask = 0xFFFFFFFF; | |
142 | ||
143 | track->db_depth_view = 0xFFFFC000; | |
144 | track->db_depth_size = 0xFFFFFFFF; | |
145 | track->db_depth_size_idx = 0; | |
146 | track->db_depth_control = 0xFFFFFFFF; | |
147 | track->db_z_info = 0xFFFFFFFF; | |
148 | track->db_z_idx = 0xFFFFFFFF; | |
149 | track->db_z_read_offset = 0xFFFFFFFF; | |
150 | track->db_z_write_offset = 0xFFFFFFFF; | |
151 | track->db_z_read_bo = NULL; | |
152 | track->db_z_write_bo = NULL; | |
153 | track->db_s_info = 0xFFFFFFFF; | |
154 | track->db_s_idx = 0xFFFFFFFF; | |
155 | track->db_s_read_offset = 0xFFFFFFFF; | |
156 | track->db_s_write_offset = 0xFFFFFFFF; | |
157 | track->db_s_read_bo = NULL; | |
158 | track->db_s_write_bo = NULL; | |
dd220a00 MO |
159 | |
160 | for (i = 0; i < 4; i++) { | |
161 | track->vgt_strmout_size[i] = 0; | |
162 | track->vgt_strmout_bo[i] = NULL; | |
163 | track->vgt_strmout_bo_offset[i] = 0xFFFFFFFF; | |
164 | track->vgt_strmout_bo_mc[i] = 0xFFFFFFFF; | |
165 | } | |
779923bc | 166 | track->sx_misc_kill_all_prims = false; |
cb5fcbd5 AD |
167 | } |
168 | ||
285484e2 JG |
169 | struct eg_surface { |
170 | /* value gathered from cs */ | |
171 | unsigned nbx; | |
172 | unsigned nby; | |
173 | unsigned format; | |
174 | unsigned mode; | |
175 | unsigned nbanks; | |
176 | unsigned bankw; | |
177 | unsigned bankh; | |
178 | unsigned tsplit; | |
179 | unsigned mtilea; | |
180 | unsigned nsamples; | |
181 | /* output value */ | |
182 | unsigned bpe; | |
183 | unsigned layer_size; | |
184 | unsigned palign; | |
185 | unsigned halign; | |
186 | unsigned long base_align; | |
187 | }; | |
188 | ||
189 | static int evergreen_surface_check_linear(struct radeon_cs_parser *p, | |
190 | struct eg_surface *surf, | |
191 | const char *prefix) | |
192 | { | |
193 | surf->layer_size = surf->nbx * surf->nby * surf->bpe * surf->nsamples; | |
194 | surf->base_align = surf->bpe; | |
195 | surf->palign = 1; | |
196 | surf->halign = 1; | |
197 | return 0; | |
198 | } | |
199 | ||
200 | static int evergreen_surface_check_linear_aligned(struct radeon_cs_parser *p, | |
201 | struct eg_surface *surf, | |
202 | const char *prefix) | |
203 | { | |
204 | struct evergreen_cs_track *track = p->track; | |
205 | unsigned palign; | |
206 | ||
207 | palign = MAX(64, track->group_size / surf->bpe); | |
208 | surf->layer_size = surf->nbx * surf->nby * surf->bpe * surf->nsamples; | |
209 | surf->base_align = track->group_size; | |
210 | surf->palign = palign; | |
211 | surf->halign = 1; | |
212 | if (surf->nbx & (palign - 1)) { | |
213 | if (prefix) { | |
214 | dev_warn(p->dev, "%s:%d %s pitch %d invalid must be aligned with %d\n", | |
215 | __func__, __LINE__, prefix, surf->nbx, palign); | |
216 | } | |
217 | return -EINVAL; | |
218 | } | |
219 | return 0; | |
220 | } | |
221 | ||
222 | static int evergreen_surface_check_1d(struct radeon_cs_parser *p, | |
223 | struct eg_surface *surf, | |
224 | const char *prefix) | |
225 | { | |
226 | struct evergreen_cs_track *track = p->track; | |
227 | unsigned palign; | |
228 | ||
229 | palign = track->group_size / (8 * surf->bpe * surf->nsamples); | |
230 | palign = MAX(8, palign); | |
231 | surf->layer_size = surf->nbx * surf->nby * surf->bpe; | |
232 | surf->base_align = track->group_size; | |
233 | surf->palign = palign; | |
234 | surf->halign = 8; | |
235 | if ((surf->nbx & (palign - 1))) { | |
236 | if (prefix) { | |
237 | dev_warn(p->dev, "%s:%d %s pitch %d invalid must be aligned with %d (%d %d %d)\n", | |
238 | __func__, __LINE__, prefix, surf->nbx, palign, | |
239 | track->group_size, surf->bpe, surf->nsamples); | |
240 | } | |
241 | return -EINVAL; | |
242 | } | |
243 | if ((surf->nby & (8 - 1))) { | |
244 | if (prefix) { | |
245 | dev_warn(p->dev, "%s:%d %s height %d invalid must be aligned with 8\n", | |
246 | __func__, __LINE__, prefix, surf->nby); | |
247 | } | |
248 | return -EINVAL; | |
249 | } | |
250 | return 0; | |
251 | } | |
252 | ||
253 | static int evergreen_surface_check_2d(struct radeon_cs_parser *p, | |
254 | struct eg_surface *surf, | |
255 | const char *prefix) | |
256 | { | |
257 | struct evergreen_cs_track *track = p->track; | |
258 | unsigned palign, halign, tileb, slice_pt; | |
259 | ||
260 | tileb = 64 * surf->bpe * surf->nsamples; | |
261 | palign = track->group_size / (8 * surf->bpe * surf->nsamples); | |
262 | palign = MAX(8, palign); | |
263 | slice_pt = 1; | |
264 | if (tileb > surf->tsplit) { | |
265 | slice_pt = tileb / surf->tsplit; | |
266 | } | |
267 | tileb = tileb / slice_pt; | |
268 | /* macro tile width & height */ | |
269 | palign = (8 * surf->bankw * track->npipes) * surf->mtilea; | |
270 | halign = (8 * surf->bankh * surf->nbanks) / surf->mtilea; | |
271 | surf->layer_size = surf->nbx * surf->nby * surf->bpe * slice_pt; | |
272 | surf->base_align = (palign / 8) * (halign / 8) * tileb; | |
273 | surf->palign = palign; | |
274 | surf->halign = halign; | |
275 | ||
276 | if ((surf->nbx & (palign - 1))) { | |
277 | if (prefix) { | |
278 | dev_warn(p->dev, "%s:%d %s pitch %d invalid must be aligned with %d\n", | |
279 | __func__, __LINE__, prefix, surf->nbx, palign); | |
280 | } | |
281 | return -EINVAL; | |
282 | } | |
283 | if ((surf->nby & (halign - 1))) { | |
284 | if (prefix) { | |
285 | dev_warn(p->dev, "%s:%d %s height %d invalid must be aligned with %d\n", | |
286 | __func__, __LINE__, prefix, surf->nby, halign); | |
287 | } | |
288 | return -EINVAL; | |
289 | } | |
290 | ||
291 | return 0; | |
292 | } | |
293 | ||
294 | static int evergreen_surface_check(struct radeon_cs_parser *p, | |
295 | struct eg_surface *surf, | |
296 | const char *prefix) | |
297 | { | |
298 | /* some common value computed here */ | |
299 | surf->bpe = r600_fmt_get_blocksize(surf->format); | |
300 | ||
301 | switch (surf->mode) { | |
302 | case ARRAY_LINEAR_GENERAL: | |
303 | return evergreen_surface_check_linear(p, surf, prefix); | |
304 | case ARRAY_LINEAR_ALIGNED: | |
305 | return evergreen_surface_check_linear_aligned(p, surf, prefix); | |
306 | case ARRAY_1D_TILED_THIN1: | |
307 | return evergreen_surface_check_1d(p, surf, prefix); | |
308 | case ARRAY_2D_TILED_THIN1: | |
309 | return evergreen_surface_check_2d(p, surf, prefix); | |
310 | default: | |
311 | dev_warn(p->dev, "%s:%d invalid array mode %d\n", | |
312 | __func__, __LINE__, surf->mode); | |
313 | return -EINVAL; | |
314 | } | |
315 | return -EINVAL; | |
316 | } | |
317 | ||
318 | static int evergreen_surface_value_conv_check(struct radeon_cs_parser *p, | |
319 | struct eg_surface *surf, | |
320 | const char *prefix) | |
321 | { | |
322 | switch (surf->mode) { | |
323 | case ARRAY_2D_TILED_THIN1: | |
324 | break; | |
325 | case ARRAY_LINEAR_GENERAL: | |
326 | case ARRAY_LINEAR_ALIGNED: | |
327 | case ARRAY_1D_TILED_THIN1: | |
328 | return 0; | |
329 | default: | |
330 | dev_warn(p->dev, "%s:%d invalid array mode %d\n", | |
331 | __func__, __LINE__, surf->mode); | |
332 | return -EINVAL; | |
333 | } | |
334 | ||
335 | switch (surf->nbanks) { | |
336 | case 0: surf->nbanks = 2; break; | |
337 | case 1: surf->nbanks = 4; break; | |
338 | case 2: surf->nbanks = 8; break; | |
339 | case 3: surf->nbanks = 16; break; | |
340 | default: | |
341 | dev_warn(p->dev, "%s:%d %s invalid number of banks %d\n", | |
342 | __func__, __LINE__, prefix, surf->nbanks); | |
343 | return -EINVAL; | |
344 | } | |
345 | switch (surf->bankw) { | |
346 | case 0: surf->bankw = 1; break; | |
347 | case 1: surf->bankw = 2; break; | |
348 | case 2: surf->bankw = 4; break; | |
349 | case 3: surf->bankw = 8; break; | |
350 | default: | |
351 | dev_warn(p->dev, "%s:%d %s invalid bankw %d\n", | |
352 | __func__, __LINE__, prefix, surf->bankw); | |
353 | return -EINVAL; | |
354 | } | |
355 | switch (surf->bankh) { | |
356 | case 0: surf->bankh = 1; break; | |
357 | case 1: surf->bankh = 2; break; | |
358 | case 2: surf->bankh = 4; break; | |
359 | case 3: surf->bankh = 8; break; | |
360 | default: | |
361 | dev_warn(p->dev, "%s:%d %s invalid bankh %d\n", | |
362 | __func__, __LINE__, prefix, surf->bankh); | |
363 | return -EINVAL; | |
364 | } | |
365 | switch (surf->mtilea) { | |
366 | case 0: surf->mtilea = 1; break; | |
367 | case 1: surf->mtilea = 2; break; | |
368 | case 2: surf->mtilea = 4; break; | |
369 | case 3: surf->mtilea = 8; break; | |
370 | default: | |
371 | dev_warn(p->dev, "%s:%d %s invalid macro tile aspect %d\n", | |
372 | __func__, __LINE__, prefix, surf->mtilea); | |
373 | return -EINVAL; | |
374 | } | |
375 | switch (surf->tsplit) { | |
376 | case 0: surf->tsplit = 64; break; | |
377 | case 1: surf->tsplit = 128; break; | |
378 | case 2: surf->tsplit = 256; break; | |
379 | case 3: surf->tsplit = 512; break; | |
380 | case 4: surf->tsplit = 1024; break; | |
381 | case 5: surf->tsplit = 2048; break; | |
382 | case 6: surf->tsplit = 4096; break; | |
383 | default: | |
384 | dev_warn(p->dev, "%s:%d %s invalid tile split %d\n", | |
385 | __func__, __LINE__, prefix, surf->tsplit); | |
386 | return -EINVAL; | |
387 | } | |
388 | return 0; | |
389 | } | |
390 | ||
391 | static int evergreen_cs_track_validate_cb(struct radeon_cs_parser *p, unsigned id) | |
392 | { | |
393 | struct evergreen_cs_track *track = p->track; | |
394 | struct eg_surface surf; | |
395 | unsigned pitch, slice, mslice; | |
396 | unsigned long offset; | |
397 | int r; | |
398 | ||
399 | mslice = G_028C6C_SLICE_MAX(track->cb_color_view[id]) + 1; | |
400 | pitch = track->cb_color_pitch[id]; | |
401 | slice = track->cb_color_slice[id]; | |
402 | surf.nbx = (pitch + 1) * 8; | |
403 | surf.nby = ((slice + 1) * 64) / surf.nbx; | |
404 | surf.mode = G_028C70_ARRAY_MODE(track->cb_color_info[id]); | |
405 | surf.format = G_028C70_FORMAT(track->cb_color_info[id]); | |
406 | surf.tsplit = G_028C74_TILE_SPLIT(track->cb_color_attrib[id]); | |
407 | surf.nbanks = G_028C74_NUM_BANKS(track->cb_color_attrib[id]); | |
408 | surf.bankw = G_028C74_BANK_WIDTH(track->cb_color_attrib[id]); | |
409 | surf.bankh = G_028C74_BANK_HEIGHT(track->cb_color_attrib[id]); | |
410 | surf.mtilea = G_028C74_MACRO_TILE_ASPECT(track->cb_color_attrib[id]); | |
411 | surf.nsamples = 1; | |
412 | ||
413 | if (!r600_fmt_is_valid_color(surf.format)) { | |
414 | dev_warn(p->dev, "%s:%d cb invalid format %d for %d (0x%08x)\n", | |
415 | __func__, __LINE__, surf.format, | |
416 | id, track->cb_color_info[id]); | |
417 | return -EINVAL; | |
418 | } | |
419 | ||
420 | r = evergreen_surface_value_conv_check(p, &surf, "cb"); | |
421 | if (r) { | |
422 | return r; | |
423 | } | |
424 | ||
425 | r = evergreen_surface_check(p, &surf, "cb"); | |
426 | if (r) { | |
427 | dev_warn(p->dev, "%s:%d cb[%d] invalid (0x%08x 0x%08x 0x%08x 0x%08x)\n", | |
428 | __func__, __LINE__, id, track->cb_color_pitch[id], | |
429 | track->cb_color_slice[id], track->cb_color_attrib[id], | |
430 | track->cb_color_info[id]); | |
431 | return r; | |
432 | } | |
433 | ||
434 | offset = track->cb_color_bo_offset[id] << 8; | |
435 | if (offset & (surf.base_align - 1)) { | |
436 | dev_warn(p->dev, "%s:%d cb[%d] bo base %ld not aligned with %ld\n", | |
437 | __func__, __LINE__, id, offset, surf.base_align); | |
438 | return -EINVAL; | |
439 | } | |
440 | ||
441 | offset += surf.layer_size * mslice; | |
442 | if (offset > radeon_bo_size(track->cb_color_bo[id])) { | |
443 | dev_warn(p->dev, "%s:%d cb[%d] bo too small (layer size %d, " | |
444 | "offset %d, max layer %d, bo size %ld, slice %d)\n", | |
445 | __func__, __LINE__, id, surf.layer_size, | |
446 | track->cb_color_bo_offset[id] << 8, mslice, | |
447 | radeon_bo_size(track->cb_color_bo[id]), slice); | |
448 | dev_warn(p->dev, "%s:%d problematic surf: (%d %d) (%d %d %d %d %d %d %d)\n", | |
449 | __func__, __LINE__, surf.nbx, surf.nby, | |
450 | surf.mode, surf.bpe, surf.nsamples, | |
451 | surf.bankw, surf.bankh, | |
452 | surf.tsplit, surf.mtilea); | |
453 | return -EINVAL; | |
454 | } | |
455 | ||
456 | return 0; | |
457 | } | |
458 | ||
459 | static int evergreen_cs_track_validate_stencil(struct radeon_cs_parser *p) | |
460 | { | |
461 | struct evergreen_cs_track *track = p->track; | |
462 | struct eg_surface surf; | |
463 | unsigned pitch, slice, mslice; | |
464 | unsigned long offset; | |
465 | int r; | |
466 | ||
467 | mslice = G_028008_SLICE_MAX(track->db_depth_view) + 1; | |
468 | pitch = G_028058_PITCH_TILE_MAX(track->db_depth_size); | |
469 | slice = track->db_depth_slice; | |
470 | surf.nbx = (pitch + 1) * 8; | |
471 | surf.nby = ((slice + 1) * 64) / surf.nbx; | |
472 | surf.mode = G_028040_ARRAY_MODE(track->db_z_info); | |
473 | surf.format = G_028044_FORMAT(track->db_s_info); | |
474 | surf.tsplit = G_028044_TILE_SPLIT(track->db_s_info); | |
475 | surf.nbanks = G_028040_NUM_BANKS(track->db_z_info); | |
476 | surf.bankw = G_028040_BANK_WIDTH(track->db_z_info); | |
477 | surf.bankh = G_028040_BANK_HEIGHT(track->db_z_info); | |
478 | surf.mtilea = G_028040_MACRO_TILE_ASPECT(track->db_z_info); | |
479 | surf.nsamples = 1; | |
480 | ||
481 | if (surf.format != 1) { | |
482 | dev_warn(p->dev, "%s:%d stencil invalid format %d\n", | |
483 | __func__, __LINE__, surf.format); | |
484 | return -EINVAL; | |
485 | } | |
486 | /* replace by color format so we can use same code */ | |
487 | surf.format = V_028C70_COLOR_8; | |
488 | ||
489 | r = evergreen_surface_value_conv_check(p, &surf, "stencil"); | |
490 | if (r) { | |
491 | return r; | |
492 | } | |
493 | ||
494 | r = evergreen_surface_check(p, &surf, NULL); | |
495 | if (r) { | |
496 | /* old userspace doesn't compute proper depth/stencil alignment | |
497 | * check that alignment against a bigger byte per elements and | |
498 | * only report if that alignment is wrong too. | |
499 | */ | |
500 | surf.format = V_028C70_COLOR_8_8_8_8; | |
501 | r = evergreen_surface_check(p, &surf, "stencil"); | |
502 | if (r) { | |
503 | dev_warn(p->dev, "%s:%d stencil invalid (0x%08x 0x%08x 0x%08x 0x%08x)\n", | |
504 | __func__, __LINE__, track->db_depth_size, | |
505 | track->db_depth_slice, track->db_s_info, track->db_z_info); | |
506 | } | |
507 | return r; | |
508 | } | |
509 | ||
510 | offset = track->db_s_read_offset << 8; | |
511 | if (offset & (surf.base_align - 1)) { | |
512 | dev_warn(p->dev, "%s:%d stencil read bo base %ld not aligned with %ld\n", | |
513 | __func__, __LINE__, offset, surf.base_align); | |
514 | return -EINVAL; | |
515 | } | |
516 | offset += surf.layer_size * mslice; | |
517 | if (offset > radeon_bo_size(track->db_s_read_bo)) { | |
518 | dev_warn(p->dev, "%s:%d stencil read bo too small (layer size %d, " | |
519 | "offset %ld, max layer %d, bo size %ld)\n", | |
520 | __func__, __LINE__, surf.layer_size, | |
521 | (unsigned long)track->db_s_read_offset << 8, mslice, | |
522 | radeon_bo_size(track->db_s_read_bo)); | |
523 | dev_warn(p->dev, "%s:%d stencil invalid (0x%08x 0x%08x 0x%08x 0x%08x)\n", | |
524 | __func__, __LINE__, track->db_depth_size, | |
525 | track->db_depth_slice, track->db_s_info, track->db_z_info); | |
526 | return -EINVAL; | |
527 | } | |
528 | ||
529 | offset = track->db_s_write_offset << 8; | |
530 | if (offset & (surf.base_align - 1)) { | |
531 | dev_warn(p->dev, "%s:%d stencil write bo base %ld not aligned with %ld\n", | |
532 | __func__, __LINE__, offset, surf.base_align); | |
533 | return -EINVAL; | |
534 | } | |
535 | offset += surf.layer_size * mslice; | |
536 | if (offset > radeon_bo_size(track->db_s_write_bo)) { | |
537 | dev_warn(p->dev, "%s:%d stencil write bo too small (layer size %d, " | |
538 | "offset %ld, max layer %d, bo size %ld)\n", | |
539 | __func__, __LINE__, surf.layer_size, | |
540 | (unsigned long)track->db_s_write_offset << 8, mslice, | |
541 | radeon_bo_size(track->db_s_write_bo)); | |
542 | return -EINVAL; | |
543 | } | |
544 | ||
545 | return 0; | |
546 | } | |
547 | ||
548 | static int evergreen_cs_track_validate_depth(struct radeon_cs_parser *p) | |
549 | { | |
550 | struct evergreen_cs_track *track = p->track; | |
551 | struct eg_surface surf; | |
552 | unsigned pitch, slice, mslice; | |
553 | unsigned long offset; | |
554 | int r; | |
555 | ||
556 | mslice = G_028008_SLICE_MAX(track->db_depth_view) + 1; | |
557 | pitch = G_028058_PITCH_TILE_MAX(track->db_depth_size); | |
558 | slice = track->db_depth_slice; | |
559 | surf.nbx = (pitch + 1) * 8; | |
560 | surf.nby = ((slice + 1) * 64) / surf.nbx; | |
561 | surf.mode = G_028040_ARRAY_MODE(track->db_z_info); | |
562 | surf.format = G_028040_FORMAT(track->db_z_info); | |
563 | surf.tsplit = G_028040_TILE_SPLIT(track->db_z_info); | |
564 | surf.nbanks = G_028040_NUM_BANKS(track->db_z_info); | |
565 | surf.bankw = G_028040_BANK_WIDTH(track->db_z_info); | |
566 | surf.bankh = G_028040_BANK_HEIGHT(track->db_z_info); | |
567 | surf.mtilea = G_028040_MACRO_TILE_ASPECT(track->db_z_info); | |
568 | surf.nsamples = 1; | |
569 | ||
570 | switch (surf.format) { | |
571 | case V_028040_Z_16: | |
572 | surf.format = V_028C70_COLOR_16; | |
573 | break; | |
574 | case V_028040_Z_24: | |
575 | case V_028040_Z_32_FLOAT: | |
576 | surf.format = V_028C70_COLOR_8_8_8_8; | |
577 | break; | |
578 | default: | |
579 | dev_warn(p->dev, "%s:%d depth invalid format %d\n", | |
580 | __func__, __LINE__, surf.format); | |
581 | return -EINVAL; | |
582 | } | |
583 | ||
584 | r = evergreen_surface_value_conv_check(p, &surf, "depth"); | |
585 | if (r) { | |
586 | dev_warn(p->dev, "%s:%d depth invalid (0x%08x 0x%08x 0x%08x)\n", | |
587 | __func__, __LINE__, track->db_depth_size, | |
588 | track->db_depth_slice, track->db_z_info); | |
589 | return r; | |
590 | } | |
591 | ||
592 | r = evergreen_surface_check(p, &surf, "depth"); | |
593 | if (r) { | |
594 | dev_warn(p->dev, "%s:%d depth invalid (0x%08x 0x%08x 0x%08x)\n", | |
595 | __func__, __LINE__, track->db_depth_size, | |
596 | track->db_depth_slice, track->db_z_info); | |
597 | return r; | |
598 | } | |
599 | ||
600 | offset = track->db_z_read_offset << 8; | |
601 | if (offset & (surf.base_align - 1)) { | |
602 | dev_warn(p->dev, "%s:%d stencil read bo base %ld not aligned with %ld\n", | |
603 | __func__, __LINE__, offset, surf.base_align); | |
604 | return -EINVAL; | |
605 | } | |
606 | offset += surf.layer_size * mslice; | |
607 | if (offset > radeon_bo_size(track->db_z_read_bo)) { | |
608 | dev_warn(p->dev, "%s:%d depth read bo too small (layer size %d, " | |
609 | "offset %ld, max layer %d, bo size %ld)\n", | |
610 | __func__, __LINE__, surf.layer_size, | |
611 | (unsigned long)track->db_z_read_offset << 8, mslice, | |
612 | radeon_bo_size(track->db_z_read_bo)); | |
613 | return -EINVAL; | |
614 | } | |
615 | ||
616 | offset = track->db_z_write_offset << 8; | |
617 | if (offset & (surf.base_align - 1)) { | |
618 | dev_warn(p->dev, "%s:%d stencil write bo base %ld not aligned with %ld\n", | |
619 | __func__, __LINE__, offset, surf.base_align); | |
620 | return -EINVAL; | |
621 | } | |
622 | offset += surf.layer_size * mslice; | |
623 | if (offset > radeon_bo_size(track->db_z_write_bo)) { | |
624 | dev_warn(p->dev, "%s:%d depth write bo too small (layer size %d, " | |
625 | "offset %ld, max layer %d, bo size %ld)\n", | |
626 | __func__, __LINE__, surf.layer_size, | |
627 | (unsigned long)track->db_z_write_offset << 8, mslice, | |
628 | radeon_bo_size(track->db_z_write_bo)); | |
629 | return -EINVAL; | |
630 | } | |
631 | ||
632 | return 0; | |
633 | } | |
634 | ||
635 | static int evergreen_cs_track_validate_texture(struct radeon_cs_parser *p, | |
636 | struct radeon_bo *texture, | |
637 | struct radeon_bo *mipmap, | |
638 | unsigned idx) | |
639 | { | |
640 | struct eg_surface surf; | |
641 | unsigned long toffset, moffset; | |
642 | unsigned dim, llevel, mslice, width, height, depth, i; | |
42b923b5 | 643 | u32 texdw[8]; |
285484e2 JG |
644 | int r; |
645 | ||
646 | texdw[0] = radeon_get_ib_value(p, idx + 0); | |
647 | texdw[1] = radeon_get_ib_value(p, idx + 1); | |
648 | texdw[2] = radeon_get_ib_value(p, idx + 2); | |
649 | texdw[3] = radeon_get_ib_value(p, idx + 3); | |
650 | texdw[4] = radeon_get_ib_value(p, idx + 4); | |
651 | texdw[5] = radeon_get_ib_value(p, idx + 5); | |
652 | texdw[6] = radeon_get_ib_value(p, idx + 6); | |
653 | texdw[7] = radeon_get_ib_value(p, idx + 7); | |
654 | dim = G_030000_DIM(texdw[0]); | |
655 | llevel = G_030014_LAST_LEVEL(texdw[5]); | |
656 | mslice = G_030014_LAST_ARRAY(texdw[5]) + 1; | |
657 | width = G_030000_TEX_WIDTH(texdw[0]) + 1; | |
658 | height = G_030004_TEX_HEIGHT(texdw[1]) + 1; | |
659 | depth = G_030004_TEX_DEPTH(texdw[1]) + 1; | |
660 | surf.format = G_03001C_DATA_FORMAT(texdw[7]); | |
661 | surf.nbx = (G_030000_PITCH(texdw[0]) + 1) * 8; | |
662 | surf.nbx = r600_fmt_get_nblocksx(surf.format, surf.nbx); | |
663 | surf.nby = r600_fmt_get_nblocksy(surf.format, height); | |
664 | surf.mode = G_030004_ARRAY_MODE(texdw[1]); | |
665 | surf.tsplit = G_030018_TILE_SPLIT(texdw[6]); | |
666 | surf.nbanks = G_03001C_NUM_BANKS(texdw[7]); | |
667 | surf.bankw = G_03001C_BANK_WIDTH(texdw[7]); | |
668 | surf.bankh = G_03001C_BANK_HEIGHT(texdw[7]); | |
669 | surf.mtilea = G_03001C_MACRO_TILE_ASPECT(texdw[7]); | |
670 | surf.nsamples = 1; | |
671 | toffset = texdw[2] << 8; | |
672 | moffset = texdw[3] << 8; | |
673 | ||
674 | if (!r600_fmt_is_valid_texture(surf.format, p->family)) { | |
675 | dev_warn(p->dev, "%s:%d texture invalid format %d\n", | |
676 | __func__, __LINE__, surf.format); | |
677 | return -EINVAL; | |
678 | } | |
679 | switch (dim) { | |
680 | case V_030000_SQ_TEX_DIM_1D: | |
681 | case V_030000_SQ_TEX_DIM_2D: | |
682 | case V_030000_SQ_TEX_DIM_CUBEMAP: | |
683 | case V_030000_SQ_TEX_DIM_1D_ARRAY: | |
684 | case V_030000_SQ_TEX_DIM_2D_ARRAY: | |
685 | depth = 1; | |
686 | case V_030000_SQ_TEX_DIM_3D: | |
687 | break; | |
688 | default: | |
689 | dev_warn(p->dev, "%s:%d texture invalid dimension %d\n", | |
690 | __func__, __LINE__, dim); | |
691 | return -EINVAL; | |
692 | } | |
693 | ||
694 | r = evergreen_surface_value_conv_check(p, &surf, "texture"); | |
695 | if (r) { | |
696 | return r; | |
697 | } | |
698 | ||
699 | /* align height */ | |
700 | evergreen_surface_check(p, &surf, NULL); | |
701 | surf.nby = ALIGN(surf.nby, surf.halign); | |
702 | ||
703 | r = evergreen_surface_check(p, &surf, "texture"); | |
704 | if (r) { | |
705 | dev_warn(p->dev, "%s:%d texture invalid 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n", | |
706 | __func__, __LINE__, texdw[0], texdw[1], texdw[4], | |
707 | texdw[5], texdw[6], texdw[7]); | |
708 | return r; | |
709 | } | |
710 | ||
711 | /* check texture size */ | |
712 | if (toffset & (surf.base_align - 1)) { | |
713 | dev_warn(p->dev, "%s:%d texture bo base %ld not aligned with %ld\n", | |
714 | __func__, __LINE__, toffset, surf.base_align); | |
715 | return -EINVAL; | |
716 | } | |
717 | if (moffset & (surf.base_align - 1)) { | |
718 | dev_warn(p->dev, "%s:%d mipmap bo base %ld not aligned with %ld\n", | |
719 | __func__, __LINE__, moffset, surf.base_align); | |
720 | return -EINVAL; | |
721 | } | |
722 | if (dim == SQ_TEX_DIM_3D) { | |
723 | toffset += surf.layer_size * depth; | |
724 | } else { | |
725 | toffset += surf.layer_size * mslice; | |
726 | } | |
727 | if (toffset > radeon_bo_size(texture)) { | |
728 | dev_warn(p->dev, "%s:%d texture bo too small (layer size %d, " | |
729 | "offset %ld, max layer %d, depth %d, bo size %ld) (%d %d)\n", | |
730 | __func__, __LINE__, surf.layer_size, | |
731 | (unsigned long)texdw[2] << 8, mslice, | |
732 | depth, radeon_bo_size(texture), | |
733 | surf.nbx, surf.nby); | |
734 | return -EINVAL; | |
735 | } | |
736 | ||
737 | /* check mipmap size */ | |
738 | for (i = 1; i <= llevel; i++) { | |
739 | unsigned w, h, d; | |
740 | ||
741 | w = r600_mip_minify(width, i); | |
742 | h = r600_mip_minify(height, i); | |
743 | d = r600_mip_minify(depth, i); | |
744 | surf.nbx = r600_fmt_get_nblocksx(surf.format, w); | |
745 | surf.nby = r600_fmt_get_nblocksy(surf.format, h); | |
746 | ||
747 | switch (surf.mode) { | |
748 | case ARRAY_2D_TILED_THIN1: | |
749 | if (surf.nbx < surf.palign || surf.nby < surf.halign) { | |
750 | surf.mode = ARRAY_1D_TILED_THIN1; | |
751 | } | |
752 | /* recompute alignment */ | |
753 | evergreen_surface_check(p, &surf, NULL); | |
754 | break; | |
755 | case ARRAY_LINEAR_GENERAL: | |
756 | case ARRAY_LINEAR_ALIGNED: | |
757 | case ARRAY_1D_TILED_THIN1: | |
758 | break; | |
759 | default: | |
760 | dev_warn(p->dev, "%s:%d invalid array mode %d\n", | |
761 | __func__, __LINE__, surf.mode); | |
762 | return -EINVAL; | |
763 | } | |
764 | surf.nbx = ALIGN(surf.nbx, surf.palign); | |
765 | surf.nby = ALIGN(surf.nby, surf.halign); | |
766 | ||
767 | r = evergreen_surface_check(p, &surf, "mipmap"); | |
768 | if (r) { | |
769 | return r; | |
770 | } | |
771 | ||
772 | if (dim == SQ_TEX_DIM_3D) { | |
773 | moffset += surf.layer_size * d; | |
774 | } else { | |
775 | moffset += surf.layer_size * mslice; | |
776 | } | |
777 | if (moffset > radeon_bo_size(mipmap)) { | |
778 | dev_warn(p->dev, "%s:%d mipmap [%d] bo too small (layer size %d, " | |
779 | "offset %ld, coffset %ld, max layer %d, depth %d, " | |
780 | "bo size %ld) level0 (%d %d %d)\n", | |
781 | __func__, __LINE__, i, surf.layer_size, | |
782 | (unsigned long)texdw[3] << 8, moffset, mslice, | |
783 | d, radeon_bo_size(mipmap), | |
784 | width, height, depth); | |
785 | dev_warn(p->dev, "%s:%d problematic surf: (%d %d) (%d %d %d %d %d %d %d)\n", | |
786 | __func__, __LINE__, surf.nbx, surf.nby, | |
787 | surf.mode, surf.bpe, surf.nsamples, | |
788 | surf.bankw, surf.bankh, | |
789 | surf.tsplit, surf.mtilea); | |
790 | return -EINVAL; | |
791 | } | |
792 | } | |
793 | ||
794 | return 0; | |
795 | } | |
796 | ||
cb5fcbd5 AD |
797 | static int evergreen_cs_track_check(struct radeon_cs_parser *p) |
798 | { | |
799 | struct evergreen_cs_track *track = p->track; | |
285484e2 JG |
800 | unsigned tmp, i, j; |
801 | int r; | |
cb5fcbd5 | 802 | |
dd220a00 MO |
803 | /* check streamout */ |
804 | for (i = 0; i < 4; i++) { | |
805 | if (track->vgt_strmout_config & (1 << i)) { | |
806 | for (j = 0; j < 4; j++) { | |
807 | if ((track->vgt_strmout_buffer_config >> (i * 4)) & (1 << j)) { | |
808 | if (track->vgt_strmout_bo[j]) { | |
809 | u64 offset = (u64)track->vgt_strmout_bo_offset[j] + | |
810 | (u64)track->vgt_strmout_size[j]; | |
811 | if (offset > radeon_bo_size(track->vgt_strmout_bo[i])) { | |
812 | DRM_ERROR("streamout %d bo too small: 0x%llx, 0x%lx\n", | |
813 | j, offset, | |
814 | radeon_bo_size(track->vgt_strmout_bo[j])); | |
815 | return -EINVAL; | |
816 | } | |
817 | } else { | |
818 | dev_warn(p->dev, "No buffer for streamout %d\n", j); | |
819 | return -EINVAL; | |
820 | } | |
821 | } | |
822 | } | |
823 | } | |
cb5fcbd5 AD |
824 | } |
825 | ||
779923bc MO |
826 | if (track->sx_misc_kill_all_prims) |
827 | return 0; | |
828 | ||
285484e2 JG |
829 | /* check that we have a cb for each enabled target |
830 | */ | |
831 | tmp = track->cb_target_mask; | |
832 | for (i = 0; i < 8; i++) { | |
833 | if ((tmp >> (i * 4)) & 0xF) { | |
834 | /* at least one component is enabled */ | |
835 | if (track->cb_color_bo[i] == NULL) { | |
836 | dev_warn(p->dev, "%s:%d mask 0x%08X | 0x%08X no cb for %d\n", | |
837 | __func__, __LINE__, track->cb_target_mask, track->cb_shader_mask, i); | |
838 | return -EINVAL; | |
839 | } | |
840 | /* check cb */ | |
841 | r = evergreen_cs_track_validate_cb(p, i); | |
842 | if (r) { | |
843 | return r; | |
844 | } | |
845 | } | |
846 | } | |
847 | ||
848 | /* Check stencil buffer */ | |
849 | if (G_028800_STENCIL_ENABLE(track->db_depth_control)) { | |
850 | r = evergreen_cs_track_validate_stencil(p); | |
851 | if (r) | |
852 | return r; | |
853 | } | |
854 | /* Check depth buffer */ | |
855 | if (G_028800_Z_WRITE_ENABLE(track->db_depth_control)) { | |
856 | r = evergreen_cs_track_validate_depth(p); | |
857 | if (r) | |
858 | return r; | |
859 | } | |
860 | ||
cb5fcbd5 AD |
861 | return 0; |
862 | } | |
863 | ||
864 | /** | |
865 | * evergreen_cs_packet_parse() - parse cp packet and point ib index to next packet | |
866 | * @parser: parser structure holding parsing context. | |
867 | * @pkt: where to store packet informations | |
868 | * | |
869 | * Assume that chunk_ib_index is properly set. Will return -EINVAL | |
870 | * if packet is bigger than remaining ib size. or if packets is unknown. | |
871 | **/ | |
872 | int evergreen_cs_packet_parse(struct radeon_cs_parser *p, | |
873 | struct radeon_cs_packet *pkt, | |
874 | unsigned idx) | |
875 | { | |
876 | struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx]; | |
877 | uint32_t header; | |
878 | ||
879 | if (idx >= ib_chunk->length_dw) { | |
880 | DRM_ERROR("Can not parse packet at %d after CS end %d !\n", | |
881 | idx, ib_chunk->length_dw); | |
882 | return -EINVAL; | |
883 | } | |
884 | header = radeon_get_ib_value(p, idx); | |
885 | pkt->idx = idx; | |
886 | pkt->type = CP_PACKET_GET_TYPE(header); | |
887 | pkt->count = CP_PACKET_GET_COUNT(header); | |
888 | pkt->one_reg_wr = 0; | |
889 | switch (pkt->type) { | |
890 | case PACKET_TYPE0: | |
891 | pkt->reg = CP_PACKET0_GET_REG(header); | |
892 | break; | |
893 | case PACKET_TYPE3: | |
894 | pkt->opcode = CP_PACKET3_GET_OPCODE(header); | |
895 | break; | |
896 | case PACKET_TYPE2: | |
897 | pkt->count = -1; | |
898 | break; | |
899 | default: | |
900 | DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx); | |
901 | return -EINVAL; | |
902 | } | |
903 | if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) { | |
904 | DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n", | |
905 | pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw); | |
906 | return -EINVAL; | |
907 | } | |
908 | return 0; | |
909 | } | |
910 | ||
911 | /** | |
912 | * evergreen_cs_packet_next_reloc() - parse next packet which should be reloc packet3 | |
913 | * @parser: parser structure holding parsing context. | |
914 | * @data: pointer to relocation data | |
915 | * @offset_start: starting offset | |
916 | * @offset_mask: offset mask (to align start offset on) | |
917 | * @reloc: reloc informations | |
918 | * | |
919 | * Check next packet is relocation packet3, do bo validation and compute | |
920 | * GPU offset using the provided start. | |
921 | **/ | |
922 | static int evergreen_cs_packet_next_reloc(struct radeon_cs_parser *p, | |
923 | struct radeon_cs_reloc **cs_reloc) | |
924 | { | |
925 | struct radeon_cs_chunk *relocs_chunk; | |
926 | struct radeon_cs_packet p3reloc; | |
927 | unsigned idx; | |
928 | int r; | |
929 | ||
930 | if (p->chunk_relocs_idx == -1) { | |
931 | DRM_ERROR("No relocation chunk !\n"); | |
932 | return -EINVAL; | |
933 | } | |
934 | *cs_reloc = NULL; | |
935 | relocs_chunk = &p->chunks[p->chunk_relocs_idx]; | |
936 | r = evergreen_cs_packet_parse(p, &p3reloc, p->idx); | |
937 | if (r) { | |
938 | return r; | |
939 | } | |
940 | p->idx += p3reloc.count + 2; | |
941 | if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) { | |
942 | DRM_ERROR("No packet3 for relocation for packet at %d.\n", | |
943 | p3reloc.idx); | |
944 | return -EINVAL; | |
945 | } | |
946 | idx = radeon_get_ib_value(p, p3reloc.idx + 1); | |
947 | if (idx >= relocs_chunk->length_dw) { | |
948 | DRM_ERROR("Relocs at %d after relocations chunk end %d !\n", | |
949 | idx, relocs_chunk->length_dw); | |
950 | return -EINVAL; | |
951 | } | |
952 | /* FIXME: we assume reloc size is 4 dwords */ | |
953 | *cs_reloc = p->relocs_ptr[(idx / 4)]; | |
954 | return 0; | |
955 | } | |
956 | ||
cb5fcbd5 AD |
957 | /** |
958 | * evergreen_cs_packet_next_vline() - parse userspace VLINE packet | |
959 | * @parser: parser structure holding parsing context. | |
960 | * | |
961 | * Userspace sends a special sequence for VLINE waits. | |
962 | * PACKET0 - VLINE_START_END + value | |
963 | * PACKET3 - WAIT_REG_MEM poll vline status reg | |
964 | * RELOC (P3) - crtc_id in reloc. | |
965 | * | |
966 | * This function parses this and relocates the VLINE START END | |
967 | * and WAIT_REG_MEM packets to the correct crtc. | |
968 | * It also detects a switched off crtc and nulls out the | |
969 | * wait in that case. | |
970 | */ | |
971 | static int evergreen_cs_packet_parse_vline(struct radeon_cs_parser *p) | |
972 | { | |
973 | struct drm_mode_object *obj; | |
974 | struct drm_crtc *crtc; | |
975 | struct radeon_crtc *radeon_crtc; | |
976 | struct radeon_cs_packet p3reloc, wait_reg_mem; | |
977 | int crtc_id; | |
978 | int r; | |
979 | uint32_t header, h_idx, reg, wait_reg_mem_info; | |
980 | volatile uint32_t *ib; | |
981 | ||
982 | ib = p->ib->ptr; | |
983 | ||
984 | /* parse the WAIT_REG_MEM */ | |
985 | r = evergreen_cs_packet_parse(p, &wait_reg_mem, p->idx); | |
986 | if (r) | |
987 | return r; | |
988 | ||
989 | /* check its a WAIT_REG_MEM */ | |
990 | if (wait_reg_mem.type != PACKET_TYPE3 || | |
991 | wait_reg_mem.opcode != PACKET3_WAIT_REG_MEM) { | |
992 | DRM_ERROR("vline wait missing WAIT_REG_MEM segment\n"); | |
a3a88a66 | 993 | return -EINVAL; |
cb5fcbd5 AD |
994 | } |
995 | ||
996 | wait_reg_mem_info = radeon_get_ib_value(p, wait_reg_mem.idx + 1); | |
997 | /* bit 4 is reg (0) or mem (1) */ | |
998 | if (wait_reg_mem_info & 0x10) { | |
999 | DRM_ERROR("vline WAIT_REG_MEM waiting on MEM rather than REG\n"); | |
a3a88a66 | 1000 | return -EINVAL; |
cb5fcbd5 AD |
1001 | } |
1002 | /* waiting for value to be equal */ | |
1003 | if ((wait_reg_mem_info & 0x7) != 0x3) { | |
1004 | DRM_ERROR("vline WAIT_REG_MEM function not equal\n"); | |
a3a88a66 | 1005 | return -EINVAL; |
cb5fcbd5 AD |
1006 | } |
1007 | if ((radeon_get_ib_value(p, wait_reg_mem.idx + 2) << 2) != EVERGREEN_VLINE_STATUS) { | |
1008 | DRM_ERROR("vline WAIT_REG_MEM bad reg\n"); | |
a3a88a66 | 1009 | return -EINVAL; |
cb5fcbd5 AD |
1010 | } |
1011 | ||
1012 | if (radeon_get_ib_value(p, wait_reg_mem.idx + 5) != EVERGREEN_VLINE_STAT) { | |
1013 | DRM_ERROR("vline WAIT_REG_MEM bad bit mask\n"); | |
a3a88a66 | 1014 | return -EINVAL; |
cb5fcbd5 AD |
1015 | } |
1016 | ||
1017 | /* jump over the NOP */ | |
1018 | r = evergreen_cs_packet_parse(p, &p3reloc, p->idx + wait_reg_mem.count + 2); | |
1019 | if (r) | |
1020 | return r; | |
1021 | ||
1022 | h_idx = p->idx - 2; | |
1023 | p->idx += wait_reg_mem.count + 2; | |
1024 | p->idx += p3reloc.count + 2; | |
1025 | ||
1026 | header = radeon_get_ib_value(p, h_idx); | |
1027 | crtc_id = radeon_get_ib_value(p, h_idx + 2 + 7 + 1); | |
1028 | reg = CP_PACKET0_GET_REG(header); | |
cb5fcbd5 AD |
1029 | obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC); |
1030 | if (!obj) { | |
1031 | DRM_ERROR("cannot find crtc %d\n", crtc_id); | |
a3a88a66 | 1032 | return -EINVAL; |
cb5fcbd5 AD |
1033 | } |
1034 | crtc = obj_to_crtc(obj); | |
1035 | radeon_crtc = to_radeon_crtc(crtc); | |
1036 | crtc_id = radeon_crtc->crtc_id; | |
1037 | ||
1038 | if (!crtc->enabled) { | |
1039 | /* if the CRTC isn't enabled - we need to nop out the WAIT_REG_MEM */ | |
1040 | ib[h_idx + 2] = PACKET2(0); | |
1041 | ib[h_idx + 3] = PACKET2(0); | |
1042 | ib[h_idx + 4] = PACKET2(0); | |
1043 | ib[h_idx + 5] = PACKET2(0); | |
1044 | ib[h_idx + 6] = PACKET2(0); | |
1045 | ib[h_idx + 7] = PACKET2(0); | |
1046 | ib[h_idx + 8] = PACKET2(0); | |
1047 | } else { | |
1048 | switch (reg) { | |
1049 | case EVERGREEN_VLINE_START_END: | |
1050 | header &= ~R600_CP_PACKET0_REG_MASK; | |
1051 | header |= (EVERGREEN_VLINE_START_END + radeon_crtc->crtc_offset) >> 2; | |
1052 | ib[h_idx] = header; | |
1053 | ib[h_idx + 4] = (EVERGREEN_VLINE_STATUS + radeon_crtc->crtc_offset) >> 2; | |
1054 | break; | |
1055 | default: | |
1056 | DRM_ERROR("unknown crtc reloc\n"); | |
a3a88a66 | 1057 | return -EINVAL; |
cb5fcbd5 AD |
1058 | } |
1059 | } | |
a3a88a66 | 1060 | return 0; |
cb5fcbd5 AD |
1061 | } |
1062 | ||
1063 | static int evergreen_packet0_check(struct radeon_cs_parser *p, | |
1064 | struct radeon_cs_packet *pkt, | |
1065 | unsigned idx, unsigned reg) | |
1066 | { | |
1067 | int r; | |
1068 | ||
1069 | switch (reg) { | |
1070 | case EVERGREEN_VLINE_START_END: | |
1071 | r = evergreen_cs_packet_parse_vline(p); | |
1072 | if (r) { | |
1073 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", | |
1074 | idx, reg); | |
1075 | return r; | |
1076 | } | |
1077 | break; | |
1078 | default: | |
1079 | printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n", | |
1080 | reg, idx); | |
1081 | return -EINVAL; | |
1082 | } | |
1083 | return 0; | |
1084 | } | |
1085 | ||
1086 | static int evergreen_cs_parse_packet0(struct radeon_cs_parser *p, | |
1087 | struct radeon_cs_packet *pkt) | |
1088 | { | |
1089 | unsigned reg, i; | |
1090 | unsigned idx; | |
1091 | int r; | |
1092 | ||
1093 | idx = pkt->idx + 1; | |
1094 | reg = pkt->reg; | |
1095 | for (i = 0; i <= pkt->count; i++, idx++, reg += 4) { | |
1096 | r = evergreen_packet0_check(p, pkt, idx, reg); | |
1097 | if (r) { | |
1098 | return r; | |
1099 | } | |
1100 | } | |
1101 | return 0; | |
1102 | } | |
1103 | ||
1104 | /** | |
1105 | * evergreen_cs_check_reg() - check if register is authorized or not | |
1106 | * @parser: parser structure holding parsing context | |
1107 | * @reg: register we are testing | |
1108 | * @idx: index into the cs buffer | |
1109 | * | |
1110 | * This function will test against evergreen_reg_safe_bm and return 0 | |
1111 | * if register is safe. If register is not flag as safe this function | |
1112 | * will test it against a list of register needind special handling. | |
1113 | */ | |
488479eb | 1114 | static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) |
cb5fcbd5 AD |
1115 | { |
1116 | struct evergreen_cs_track *track = (struct evergreen_cs_track *)p->track; | |
1117 | struct radeon_cs_reloc *reloc; | |
c175ca9a | 1118 | u32 last_reg; |
cb5fcbd5 AD |
1119 | u32 m, i, tmp, *ib; |
1120 | int r; | |
1121 | ||
c175ca9a AD |
1122 | if (p->rdev->family >= CHIP_CAYMAN) |
1123 | last_reg = ARRAY_SIZE(cayman_reg_safe_bm); | |
1124 | else | |
1125 | last_reg = ARRAY_SIZE(evergreen_reg_safe_bm); | |
1126 | ||
cb5fcbd5 | 1127 | i = (reg >> 7); |
88498839 | 1128 | if (i >= last_reg) { |
cb5fcbd5 AD |
1129 | dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx); |
1130 | return -EINVAL; | |
1131 | } | |
1132 | m = 1 << ((reg >> 2) & 31); | |
c175ca9a AD |
1133 | if (p->rdev->family >= CHIP_CAYMAN) { |
1134 | if (!(cayman_reg_safe_bm[i] & m)) | |
1135 | return 0; | |
1136 | } else { | |
1137 | if (!(evergreen_reg_safe_bm[i] & m)) | |
1138 | return 0; | |
1139 | } | |
cb5fcbd5 AD |
1140 | ib = p->ib->ptr; |
1141 | switch (reg) { | |
25985edc | 1142 | /* force following reg to 0 in an attempt to disable out buffer |
cb5fcbd5 AD |
1143 | * which will need us to better understand how it works to perform |
1144 | * security check on it (Jerome) | |
1145 | */ | |
1146 | case SQ_ESGS_RING_SIZE: | |
1147 | case SQ_GSVS_RING_SIZE: | |
1148 | case SQ_ESTMP_RING_SIZE: | |
1149 | case SQ_GSTMP_RING_SIZE: | |
1150 | case SQ_HSTMP_RING_SIZE: | |
1151 | case SQ_LSTMP_RING_SIZE: | |
1152 | case SQ_PSTMP_RING_SIZE: | |
1153 | case SQ_VSTMP_RING_SIZE: | |
1154 | case SQ_ESGS_RING_ITEMSIZE: | |
1155 | case SQ_ESTMP_RING_ITEMSIZE: | |
1156 | case SQ_GSTMP_RING_ITEMSIZE: | |
1157 | case SQ_GSVS_RING_ITEMSIZE: | |
1158 | case SQ_GS_VERT_ITEMSIZE: | |
1159 | case SQ_GS_VERT_ITEMSIZE_1: | |
1160 | case SQ_GS_VERT_ITEMSIZE_2: | |
1161 | case SQ_GS_VERT_ITEMSIZE_3: | |
1162 | case SQ_GSVS_RING_OFFSET_1: | |
1163 | case SQ_GSVS_RING_OFFSET_2: | |
1164 | case SQ_GSVS_RING_OFFSET_3: | |
1165 | case SQ_HSTMP_RING_ITEMSIZE: | |
1166 | case SQ_LSTMP_RING_ITEMSIZE: | |
1167 | case SQ_PSTMP_RING_ITEMSIZE: | |
1168 | case SQ_VSTMP_RING_ITEMSIZE: | |
1169 | case VGT_TF_RING_SIZE: | |
1170 | /* get value to populate the IB don't remove */ | |
8aa75009 AD |
1171 | /*tmp =radeon_get_ib_value(p, idx); |
1172 | ib[idx] = 0;*/ | |
1173 | break; | |
1174 | case SQ_ESGS_RING_BASE: | |
1175 | case SQ_GSVS_RING_BASE: | |
1176 | case SQ_ESTMP_RING_BASE: | |
1177 | case SQ_GSTMP_RING_BASE: | |
1178 | case SQ_HSTMP_RING_BASE: | |
1179 | case SQ_LSTMP_RING_BASE: | |
1180 | case SQ_PSTMP_RING_BASE: | |
1181 | case SQ_VSTMP_RING_BASE: | |
1182 | r = evergreen_cs_packet_next_reloc(p, &reloc); | |
1183 | if (r) { | |
1184 | dev_warn(p->dev, "bad SET_CONTEXT_REG " | |
1185 | "0x%04X\n", reg); | |
1186 | return -EINVAL; | |
1187 | } | |
1188 | ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); | |
cb5fcbd5 AD |
1189 | break; |
1190 | case DB_DEPTH_CONTROL: | |
1191 | track->db_depth_control = radeon_get_ib_value(p, idx); | |
1192 | break; | |
c175ca9a AD |
1193 | case CAYMAN_DB_EQAA: |
1194 | if (p->rdev->family < CHIP_CAYMAN) { | |
1195 | dev_warn(p->dev, "bad SET_CONTEXT_REG " | |
1196 | "0x%04X\n", reg); | |
1197 | return -EINVAL; | |
1198 | } | |
1199 | break; | |
1200 | case CAYMAN_DB_DEPTH_INFO: | |
1201 | if (p->rdev->family < CHIP_CAYMAN) { | |
1202 | dev_warn(p->dev, "bad SET_CONTEXT_REG " | |
1203 | "0x%04X\n", reg); | |
1204 | return -EINVAL; | |
1205 | } | |
1206 | break; | |
cb5fcbd5 | 1207 | case DB_Z_INFO: |
cb5fcbd5 | 1208 | track->db_z_info = radeon_get_ib_value(p, idx); |
721604a1 | 1209 | if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { |
e70f224c MO |
1210 | r = evergreen_cs_packet_next_reloc(p, &reloc); |
1211 | if (r) { | |
1212 | dev_warn(p->dev, "bad SET_CONTEXT_REG " | |
1213 | "0x%04X\n", reg); | |
1214 | return -EINVAL; | |
1215 | } | |
1216 | ib[idx] &= ~Z_ARRAY_MODE(0xf); | |
1217 | track->db_z_info &= ~Z_ARRAY_MODE(0xf); | |
f3a71df0 AD |
1218 | ib[idx] |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags)); |
1219 | track->db_z_info |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags)); | |
e70f224c | 1220 | if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) { |
285484e2 JG |
1221 | unsigned bankw, bankh, mtaspect, tile_split; |
1222 | ||
1223 | evergreen_tiling_fields(reloc->lobj.tiling_flags, | |
1224 | &bankw, &bankh, &mtaspect, | |
1225 | &tile_split); | |
f3a71df0 | 1226 | ib[idx] |= DB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks)); |
285484e2 JG |
1227 | ib[idx] |= DB_TILE_SPLIT(tile_split) | |
1228 | DB_BANK_WIDTH(bankw) | | |
1229 | DB_BANK_HEIGHT(bankh) | | |
1230 | DB_MACRO_TILE_ASPECT(mtaspect); | |
e70f224c | 1231 | } |
cb5fcbd5 AD |
1232 | } |
1233 | break; | |
1234 | case DB_STENCIL_INFO: | |
1235 | track->db_s_info = radeon_get_ib_value(p, idx); | |
1236 | break; | |
1237 | case DB_DEPTH_VIEW: | |
1238 | track->db_depth_view = radeon_get_ib_value(p, idx); | |
1239 | break; | |
1240 | case DB_DEPTH_SIZE: | |
1241 | track->db_depth_size = radeon_get_ib_value(p, idx); | |
1242 | track->db_depth_size_idx = idx; | |
1243 | break; | |
285484e2 JG |
1244 | case R_02805C_DB_DEPTH_SLICE: |
1245 | track->db_depth_slice = radeon_get_ib_value(p, idx); | |
1246 | break; | |
cb5fcbd5 AD |
1247 | case DB_Z_READ_BASE: |
1248 | r = evergreen_cs_packet_next_reloc(p, &reloc); | |
1249 | if (r) { | |
1250 | dev_warn(p->dev, "bad SET_CONTEXT_REG " | |
1251 | "0x%04X\n", reg); | |
1252 | return -EINVAL; | |
1253 | } | |
1254 | track->db_z_read_offset = radeon_get_ib_value(p, idx); | |
1255 | ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); | |
1256 | track->db_z_read_bo = reloc->robj; | |
1257 | break; | |
1258 | case DB_Z_WRITE_BASE: | |
1259 | r = evergreen_cs_packet_next_reloc(p, &reloc); | |
1260 | if (r) { | |
1261 | dev_warn(p->dev, "bad SET_CONTEXT_REG " | |
1262 | "0x%04X\n", reg); | |
1263 | return -EINVAL; | |
1264 | } | |
1265 | track->db_z_write_offset = radeon_get_ib_value(p, idx); | |
1266 | ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); | |
1267 | track->db_z_write_bo = reloc->robj; | |
1268 | break; | |
1269 | case DB_STENCIL_READ_BASE: | |
1270 | r = evergreen_cs_packet_next_reloc(p, &reloc); | |
1271 | if (r) { | |
1272 | dev_warn(p->dev, "bad SET_CONTEXT_REG " | |
1273 | "0x%04X\n", reg); | |
1274 | return -EINVAL; | |
1275 | } | |
1276 | track->db_s_read_offset = radeon_get_ib_value(p, idx); | |
1277 | ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); | |
1278 | track->db_s_read_bo = reloc->robj; | |
1279 | break; | |
1280 | case DB_STENCIL_WRITE_BASE: | |
1281 | r = evergreen_cs_packet_next_reloc(p, &reloc); | |
1282 | if (r) { | |
1283 | dev_warn(p->dev, "bad SET_CONTEXT_REG " | |
1284 | "0x%04X\n", reg); | |
1285 | return -EINVAL; | |
1286 | } | |
1287 | track->db_s_write_offset = radeon_get_ib_value(p, idx); | |
1288 | ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); | |
1289 | track->db_s_write_bo = reloc->robj; | |
1290 | break; | |
1291 | case VGT_STRMOUT_CONFIG: | |
1292 | track->vgt_strmout_config = radeon_get_ib_value(p, idx); | |
1293 | break; | |
1294 | case VGT_STRMOUT_BUFFER_CONFIG: | |
1295 | track->vgt_strmout_buffer_config = radeon_get_ib_value(p, idx); | |
1296 | break; | |
dd220a00 MO |
1297 | case VGT_STRMOUT_BUFFER_BASE_0: |
1298 | case VGT_STRMOUT_BUFFER_BASE_1: | |
1299 | case VGT_STRMOUT_BUFFER_BASE_2: | |
1300 | case VGT_STRMOUT_BUFFER_BASE_3: | |
1301 | r = evergreen_cs_packet_next_reloc(p, &reloc); | |
1302 | if (r) { | |
1303 | dev_warn(p->dev, "bad SET_CONTEXT_REG " | |
1304 | "0x%04X\n", reg); | |
1305 | return -EINVAL; | |
1306 | } | |
1307 | tmp = (reg - VGT_STRMOUT_BUFFER_BASE_0) / 16; | |
1308 | track->vgt_strmout_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8; | |
1309 | ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); | |
1310 | track->vgt_strmout_bo[tmp] = reloc->robj; | |
1311 | track->vgt_strmout_bo_mc[tmp] = reloc->lobj.gpu_offset; | |
1312 | break; | |
1313 | case VGT_STRMOUT_BUFFER_SIZE_0: | |
1314 | case VGT_STRMOUT_BUFFER_SIZE_1: | |
1315 | case VGT_STRMOUT_BUFFER_SIZE_2: | |
1316 | case VGT_STRMOUT_BUFFER_SIZE_3: | |
1317 | tmp = (reg - VGT_STRMOUT_BUFFER_SIZE_0) / 16; | |
1318 | /* size in register is DWs, convert to bytes */ | |
1319 | track->vgt_strmout_size[tmp] = radeon_get_ib_value(p, idx) * 4; | |
1320 | break; | |
1321 | case CP_COHER_BASE: | |
1322 | r = evergreen_cs_packet_next_reloc(p, &reloc); | |
1323 | if (r) { | |
1324 | dev_warn(p->dev, "missing reloc for CP_COHER_BASE " | |
1325 | "0x%04X\n", reg); | |
1326 | return -EINVAL; | |
1327 | } | |
1328 | ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); | |
cb5fcbd5 AD |
1329 | case CB_TARGET_MASK: |
1330 | track->cb_target_mask = radeon_get_ib_value(p, idx); | |
1331 | break; | |
1332 | case CB_SHADER_MASK: | |
1333 | track->cb_shader_mask = radeon_get_ib_value(p, idx); | |
1334 | break; | |
1335 | case PA_SC_AA_CONFIG: | |
c175ca9a AD |
1336 | if (p->rdev->family >= CHIP_CAYMAN) { |
1337 | dev_warn(p->dev, "bad SET_CONTEXT_REG " | |
1338 | "0x%04X\n", reg); | |
1339 | return -EINVAL; | |
1340 | } | |
cb5fcbd5 AD |
1341 | tmp = radeon_get_ib_value(p, idx) & MSAA_NUM_SAMPLES_MASK; |
1342 | track->nsamples = 1 << tmp; | |
1343 | break; | |
c175ca9a AD |
1344 | case CAYMAN_PA_SC_AA_CONFIG: |
1345 | if (p->rdev->family < CHIP_CAYMAN) { | |
1346 | dev_warn(p->dev, "bad SET_CONTEXT_REG " | |
1347 | "0x%04X\n", reg); | |
1348 | return -EINVAL; | |
1349 | } | |
1350 | tmp = radeon_get_ib_value(p, idx) & CAYMAN_MSAA_NUM_SAMPLES_MASK; | |
1351 | track->nsamples = 1 << tmp; | |
1352 | break; | |
cb5fcbd5 AD |
1353 | case CB_COLOR0_VIEW: |
1354 | case CB_COLOR1_VIEW: | |
1355 | case CB_COLOR2_VIEW: | |
1356 | case CB_COLOR3_VIEW: | |
1357 | case CB_COLOR4_VIEW: | |
1358 | case CB_COLOR5_VIEW: | |
1359 | case CB_COLOR6_VIEW: | |
1360 | case CB_COLOR7_VIEW: | |
1361 | tmp = (reg - CB_COLOR0_VIEW) / 0x3c; | |
1362 | track->cb_color_view[tmp] = radeon_get_ib_value(p, idx); | |
1363 | break; | |
1364 | case CB_COLOR8_VIEW: | |
1365 | case CB_COLOR9_VIEW: | |
1366 | case CB_COLOR10_VIEW: | |
1367 | case CB_COLOR11_VIEW: | |
1368 | tmp = ((reg - CB_COLOR8_VIEW) / 0x1c) + 8; | |
1369 | track->cb_color_view[tmp] = radeon_get_ib_value(p, idx); | |
1370 | break; | |
1371 | case CB_COLOR0_INFO: | |
1372 | case CB_COLOR1_INFO: | |
1373 | case CB_COLOR2_INFO: | |
1374 | case CB_COLOR3_INFO: | |
1375 | case CB_COLOR4_INFO: | |
1376 | case CB_COLOR5_INFO: | |
1377 | case CB_COLOR6_INFO: | |
1378 | case CB_COLOR7_INFO: | |
cb5fcbd5 AD |
1379 | tmp = (reg - CB_COLOR0_INFO) / 0x3c; |
1380 | track->cb_color_info[tmp] = radeon_get_ib_value(p, idx); | |
721604a1 | 1381 | if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { |
e70f224c MO |
1382 | r = evergreen_cs_packet_next_reloc(p, &reloc); |
1383 | if (r) { | |
1384 | dev_warn(p->dev, "bad SET_CONTEXT_REG " | |
1385 | "0x%04X\n", reg); | |
1386 | return -EINVAL; | |
1387 | } | |
f3a71df0 AD |
1388 | ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags)); |
1389 | track->cb_color_info[tmp] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags)); | |
cb5fcbd5 AD |
1390 | } |
1391 | break; | |
1392 | case CB_COLOR8_INFO: | |
1393 | case CB_COLOR9_INFO: | |
1394 | case CB_COLOR10_INFO: | |
1395 | case CB_COLOR11_INFO: | |
cb5fcbd5 AD |
1396 | tmp = ((reg - CB_COLOR8_INFO) / 0x1c) + 8; |
1397 | track->cb_color_info[tmp] = radeon_get_ib_value(p, idx); | |
721604a1 | 1398 | if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { |
e70f224c MO |
1399 | r = evergreen_cs_packet_next_reloc(p, &reloc); |
1400 | if (r) { | |
1401 | dev_warn(p->dev, "bad SET_CONTEXT_REG " | |
1402 | "0x%04X\n", reg); | |
1403 | return -EINVAL; | |
1404 | } | |
f3a71df0 AD |
1405 | ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags)); |
1406 | track->cb_color_info[tmp] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags)); | |
cb5fcbd5 AD |
1407 | } |
1408 | break; | |
1409 | case CB_COLOR0_PITCH: | |
1410 | case CB_COLOR1_PITCH: | |
1411 | case CB_COLOR2_PITCH: | |
1412 | case CB_COLOR3_PITCH: | |
1413 | case CB_COLOR4_PITCH: | |
1414 | case CB_COLOR5_PITCH: | |
1415 | case CB_COLOR6_PITCH: | |
1416 | case CB_COLOR7_PITCH: | |
1417 | tmp = (reg - CB_COLOR0_PITCH) / 0x3c; | |
1418 | track->cb_color_pitch[tmp] = radeon_get_ib_value(p, idx); | |
1419 | track->cb_color_pitch_idx[tmp] = idx; | |
1420 | break; | |
1421 | case CB_COLOR8_PITCH: | |
1422 | case CB_COLOR9_PITCH: | |
1423 | case CB_COLOR10_PITCH: | |
1424 | case CB_COLOR11_PITCH: | |
1425 | tmp = ((reg - CB_COLOR8_PITCH) / 0x1c) + 8; | |
1426 | track->cb_color_pitch[tmp] = radeon_get_ib_value(p, idx); | |
1427 | track->cb_color_pitch_idx[tmp] = idx; | |
1428 | break; | |
1429 | case CB_COLOR0_SLICE: | |
1430 | case CB_COLOR1_SLICE: | |
1431 | case CB_COLOR2_SLICE: | |
1432 | case CB_COLOR3_SLICE: | |
1433 | case CB_COLOR4_SLICE: | |
1434 | case CB_COLOR5_SLICE: | |
1435 | case CB_COLOR6_SLICE: | |
1436 | case CB_COLOR7_SLICE: | |
1437 | tmp = (reg - CB_COLOR0_SLICE) / 0x3c; | |
1438 | track->cb_color_slice[tmp] = radeon_get_ib_value(p, idx); | |
1439 | track->cb_color_slice_idx[tmp] = idx; | |
1440 | break; | |
1441 | case CB_COLOR8_SLICE: | |
1442 | case CB_COLOR9_SLICE: | |
1443 | case CB_COLOR10_SLICE: | |
1444 | case CB_COLOR11_SLICE: | |
1445 | tmp = ((reg - CB_COLOR8_SLICE) / 0x1c) + 8; | |
1446 | track->cb_color_slice[tmp] = radeon_get_ib_value(p, idx); | |
1447 | track->cb_color_slice_idx[tmp] = idx; | |
1448 | break; | |
1449 | case CB_COLOR0_ATTRIB: | |
1450 | case CB_COLOR1_ATTRIB: | |
1451 | case CB_COLOR2_ATTRIB: | |
1452 | case CB_COLOR3_ATTRIB: | |
1453 | case CB_COLOR4_ATTRIB: | |
1454 | case CB_COLOR5_ATTRIB: | |
1455 | case CB_COLOR6_ATTRIB: | |
1456 | case CB_COLOR7_ATTRIB: | |
285484e2 JG |
1457 | r = evergreen_cs_packet_next_reloc(p, &reloc); |
1458 | if (r) { | |
1459 | dev_warn(p->dev, "bad SET_CONTEXT_REG " | |
1460 | "0x%04X\n", reg); | |
1461 | return -EINVAL; | |
1462 | } | |
1463 | if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { | |
1464 | if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) { | |
1465 | unsigned bankw, bankh, mtaspect, tile_split; | |
1466 | ||
1467 | evergreen_tiling_fields(reloc->lobj.tiling_flags, | |
1468 | &bankw, &bankh, &mtaspect, | |
1469 | &tile_split); | |
1470 | ib[idx] |= CB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks)); | |
1471 | ib[idx] |= CB_TILE_SPLIT(tile_split) | | |
1472 | CB_BANK_WIDTH(bankw) | | |
1473 | CB_BANK_HEIGHT(bankh) | | |
1474 | CB_MACRO_TILE_ASPECT(mtaspect); | |
1475 | } | |
1476 | } | |
1477 | tmp = ((reg - CB_COLOR0_ATTRIB) / 0x3c); | |
1478 | track->cb_color_attrib[tmp] = ib[idx]; | |
1479 | break; | |
cb5fcbd5 AD |
1480 | case CB_COLOR8_ATTRIB: |
1481 | case CB_COLOR9_ATTRIB: | |
1482 | case CB_COLOR10_ATTRIB: | |
1483 | case CB_COLOR11_ATTRIB: | |
f3a71df0 AD |
1484 | r = evergreen_cs_packet_next_reloc(p, &reloc); |
1485 | if (r) { | |
1486 | dev_warn(p->dev, "bad SET_CONTEXT_REG " | |
1487 | "0x%04X\n", reg); | |
1488 | return -EINVAL; | |
1489 | } | |
285484e2 JG |
1490 | if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { |
1491 | if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) { | |
1492 | unsigned bankw, bankh, mtaspect, tile_split; | |
1493 | ||
1494 | evergreen_tiling_fields(reloc->lobj.tiling_flags, | |
1495 | &bankw, &bankh, &mtaspect, | |
1496 | &tile_split); | |
1497 | ib[idx] |= CB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks)); | |
1498 | ib[idx] |= CB_TILE_SPLIT(tile_split) | | |
1499 | CB_BANK_WIDTH(bankw) | | |
1500 | CB_BANK_HEIGHT(bankh) | | |
1501 | CB_MACRO_TILE_ASPECT(mtaspect); | |
1502 | } | |
f3a71df0 | 1503 | } |
285484e2 JG |
1504 | tmp = ((reg - CB_COLOR8_ATTRIB) / 0x1c) + 8; |
1505 | track->cb_color_attrib[tmp] = ib[idx]; | |
cb5fcbd5 AD |
1506 | break; |
1507 | case CB_COLOR0_DIM: | |
1508 | case CB_COLOR1_DIM: | |
1509 | case CB_COLOR2_DIM: | |
1510 | case CB_COLOR3_DIM: | |
1511 | case CB_COLOR4_DIM: | |
1512 | case CB_COLOR5_DIM: | |
1513 | case CB_COLOR6_DIM: | |
1514 | case CB_COLOR7_DIM: | |
1515 | tmp = (reg - CB_COLOR0_DIM) / 0x3c; | |
1516 | track->cb_color_dim[tmp] = radeon_get_ib_value(p, idx); | |
1517 | track->cb_color_dim_idx[tmp] = idx; | |
1518 | break; | |
1519 | case CB_COLOR8_DIM: | |
1520 | case CB_COLOR9_DIM: | |
1521 | case CB_COLOR10_DIM: | |
1522 | case CB_COLOR11_DIM: | |
1523 | tmp = ((reg - CB_COLOR8_DIM) / 0x1c) + 8; | |
1524 | track->cb_color_dim[tmp] = radeon_get_ib_value(p, idx); | |
1525 | track->cb_color_dim_idx[tmp] = idx; | |
1526 | break; | |
1527 | case CB_COLOR0_FMASK: | |
1528 | case CB_COLOR1_FMASK: | |
1529 | case CB_COLOR2_FMASK: | |
1530 | case CB_COLOR3_FMASK: | |
1531 | case CB_COLOR4_FMASK: | |
1532 | case CB_COLOR5_FMASK: | |
1533 | case CB_COLOR6_FMASK: | |
1534 | case CB_COLOR7_FMASK: | |
1535 | tmp = (reg - CB_COLOR0_FMASK) / 0x3c; | |
1536 | r = evergreen_cs_packet_next_reloc(p, &reloc); | |
1537 | if (r) { | |
1538 | dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg); | |
1539 | return -EINVAL; | |
1540 | } | |
1541 | ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); | |
1542 | track->cb_color_fmask_bo[tmp] = reloc->robj; | |
1543 | break; | |
1544 | case CB_COLOR0_CMASK: | |
1545 | case CB_COLOR1_CMASK: | |
1546 | case CB_COLOR2_CMASK: | |
1547 | case CB_COLOR3_CMASK: | |
1548 | case CB_COLOR4_CMASK: | |
1549 | case CB_COLOR5_CMASK: | |
1550 | case CB_COLOR6_CMASK: | |
1551 | case CB_COLOR7_CMASK: | |
1552 | tmp = (reg - CB_COLOR0_CMASK) / 0x3c; | |
1553 | r = evergreen_cs_packet_next_reloc(p, &reloc); | |
1554 | if (r) { | |
1555 | dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg); | |
1556 | return -EINVAL; | |
1557 | } | |
1558 | ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); | |
1559 | track->cb_color_cmask_bo[tmp] = reloc->robj; | |
1560 | break; | |
1561 | case CB_COLOR0_FMASK_SLICE: | |
1562 | case CB_COLOR1_FMASK_SLICE: | |
1563 | case CB_COLOR2_FMASK_SLICE: | |
1564 | case CB_COLOR3_FMASK_SLICE: | |
1565 | case CB_COLOR4_FMASK_SLICE: | |
1566 | case CB_COLOR5_FMASK_SLICE: | |
1567 | case CB_COLOR6_FMASK_SLICE: | |
1568 | case CB_COLOR7_FMASK_SLICE: | |
1569 | tmp = (reg - CB_COLOR0_FMASK_SLICE) / 0x3c; | |
1570 | track->cb_color_fmask_slice[tmp] = radeon_get_ib_value(p, idx); | |
1571 | break; | |
1572 | case CB_COLOR0_CMASK_SLICE: | |
1573 | case CB_COLOR1_CMASK_SLICE: | |
1574 | case CB_COLOR2_CMASK_SLICE: | |
1575 | case CB_COLOR3_CMASK_SLICE: | |
1576 | case CB_COLOR4_CMASK_SLICE: | |
1577 | case CB_COLOR5_CMASK_SLICE: | |
1578 | case CB_COLOR6_CMASK_SLICE: | |
1579 | case CB_COLOR7_CMASK_SLICE: | |
1580 | tmp = (reg - CB_COLOR0_CMASK_SLICE) / 0x3c; | |
1581 | track->cb_color_cmask_slice[tmp] = radeon_get_ib_value(p, idx); | |
1582 | break; | |
1583 | case CB_COLOR0_BASE: | |
1584 | case CB_COLOR1_BASE: | |
1585 | case CB_COLOR2_BASE: | |
1586 | case CB_COLOR3_BASE: | |
1587 | case CB_COLOR4_BASE: | |
1588 | case CB_COLOR5_BASE: | |
1589 | case CB_COLOR6_BASE: | |
1590 | case CB_COLOR7_BASE: | |
1591 | r = evergreen_cs_packet_next_reloc(p, &reloc); | |
1592 | if (r) { | |
1593 | dev_warn(p->dev, "bad SET_CONTEXT_REG " | |
1594 | "0x%04X\n", reg); | |
1595 | return -EINVAL; | |
1596 | } | |
1597 | tmp = (reg - CB_COLOR0_BASE) / 0x3c; | |
1598 | track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx); | |
1599 | ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); | |
1600 | track->cb_color_base_last[tmp] = ib[idx]; | |
1601 | track->cb_color_bo[tmp] = reloc->robj; | |
1602 | break; | |
1603 | case CB_COLOR8_BASE: | |
1604 | case CB_COLOR9_BASE: | |
1605 | case CB_COLOR10_BASE: | |
1606 | case CB_COLOR11_BASE: | |
1607 | r = evergreen_cs_packet_next_reloc(p, &reloc); | |
1608 | if (r) { | |
1609 | dev_warn(p->dev, "bad SET_CONTEXT_REG " | |
1610 | "0x%04X\n", reg); | |
1611 | return -EINVAL; | |
1612 | } | |
1613 | tmp = ((reg - CB_COLOR8_BASE) / 0x1c) + 8; | |
1614 | track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx); | |
1615 | ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); | |
1616 | track->cb_color_base_last[tmp] = ib[idx]; | |
1617 | track->cb_color_bo[tmp] = reloc->robj; | |
1618 | break; | |
1619 | case CB_IMMED0_BASE: | |
1620 | case CB_IMMED1_BASE: | |
1621 | case CB_IMMED2_BASE: | |
1622 | case CB_IMMED3_BASE: | |
1623 | case CB_IMMED4_BASE: | |
1624 | case CB_IMMED5_BASE: | |
1625 | case CB_IMMED6_BASE: | |
1626 | case CB_IMMED7_BASE: | |
1627 | case CB_IMMED8_BASE: | |
1628 | case CB_IMMED9_BASE: | |
1629 | case CB_IMMED10_BASE: | |
1630 | case CB_IMMED11_BASE: | |
1631 | case DB_HTILE_DATA_BASE: | |
1632 | case SQ_PGM_START_FS: | |
1633 | case SQ_PGM_START_ES: | |
1634 | case SQ_PGM_START_VS: | |
1635 | case SQ_PGM_START_GS: | |
1636 | case SQ_PGM_START_PS: | |
1637 | case SQ_PGM_START_HS: | |
1638 | case SQ_PGM_START_LS: | |
cb5fcbd5 AD |
1639 | case SQ_CONST_MEM_BASE: |
1640 | case SQ_ALU_CONST_CACHE_GS_0: | |
1641 | case SQ_ALU_CONST_CACHE_GS_1: | |
1642 | case SQ_ALU_CONST_CACHE_GS_2: | |
1643 | case SQ_ALU_CONST_CACHE_GS_3: | |
1644 | case SQ_ALU_CONST_CACHE_GS_4: | |
1645 | case SQ_ALU_CONST_CACHE_GS_5: | |
1646 | case SQ_ALU_CONST_CACHE_GS_6: | |
1647 | case SQ_ALU_CONST_CACHE_GS_7: | |
1648 | case SQ_ALU_CONST_CACHE_GS_8: | |
1649 | case SQ_ALU_CONST_CACHE_GS_9: | |
1650 | case SQ_ALU_CONST_CACHE_GS_10: | |
1651 | case SQ_ALU_CONST_CACHE_GS_11: | |
1652 | case SQ_ALU_CONST_CACHE_GS_12: | |
1653 | case SQ_ALU_CONST_CACHE_GS_13: | |
1654 | case SQ_ALU_CONST_CACHE_GS_14: | |
1655 | case SQ_ALU_CONST_CACHE_GS_15: | |
1656 | case SQ_ALU_CONST_CACHE_PS_0: | |
1657 | case SQ_ALU_CONST_CACHE_PS_1: | |
1658 | case SQ_ALU_CONST_CACHE_PS_2: | |
1659 | case SQ_ALU_CONST_CACHE_PS_3: | |
1660 | case SQ_ALU_CONST_CACHE_PS_4: | |
1661 | case SQ_ALU_CONST_CACHE_PS_5: | |
1662 | case SQ_ALU_CONST_CACHE_PS_6: | |
1663 | case SQ_ALU_CONST_CACHE_PS_7: | |
1664 | case SQ_ALU_CONST_CACHE_PS_8: | |
1665 | case SQ_ALU_CONST_CACHE_PS_9: | |
1666 | case SQ_ALU_CONST_CACHE_PS_10: | |
1667 | case SQ_ALU_CONST_CACHE_PS_11: | |
1668 | case SQ_ALU_CONST_CACHE_PS_12: | |
1669 | case SQ_ALU_CONST_CACHE_PS_13: | |
1670 | case SQ_ALU_CONST_CACHE_PS_14: | |
1671 | case SQ_ALU_CONST_CACHE_PS_15: | |
1672 | case SQ_ALU_CONST_CACHE_VS_0: | |
1673 | case SQ_ALU_CONST_CACHE_VS_1: | |
1674 | case SQ_ALU_CONST_CACHE_VS_2: | |
1675 | case SQ_ALU_CONST_CACHE_VS_3: | |
1676 | case SQ_ALU_CONST_CACHE_VS_4: | |
1677 | case SQ_ALU_CONST_CACHE_VS_5: | |
1678 | case SQ_ALU_CONST_CACHE_VS_6: | |
1679 | case SQ_ALU_CONST_CACHE_VS_7: | |
1680 | case SQ_ALU_CONST_CACHE_VS_8: | |
1681 | case SQ_ALU_CONST_CACHE_VS_9: | |
1682 | case SQ_ALU_CONST_CACHE_VS_10: | |
1683 | case SQ_ALU_CONST_CACHE_VS_11: | |
1684 | case SQ_ALU_CONST_CACHE_VS_12: | |
1685 | case SQ_ALU_CONST_CACHE_VS_13: | |
1686 | case SQ_ALU_CONST_CACHE_VS_14: | |
1687 | case SQ_ALU_CONST_CACHE_VS_15: | |
1688 | case SQ_ALU_CONST_CACHE_HS_0: | |
1689 | case SQ_ALU_CONST_CACHE_HS_1: | |
1690 | case SQ_ALU_CONST_CACHE_HS_2: | |
1691 | case SQ_ALU_CONST_CACHE_HS_3: | |
1692 | case SQ_ALU_CONST_CACHE_HS_4: | |
1693 | case SQ_ALU_CONST_CACHE_HS_5: | |
1694 | case SQ_ALU_CONST_CACHE_HS_6: | |
1695 | case SQ_ALU_CONST_CACHE_HS_7: | |
1696 | case SQ_ALU_CONST_CACHE_HS_8: | |
1697 | case SQ_ALU_CONST_CACHE_HS_9: | |
1698 | case SQ_ALU_CONST_CACHE_HS_10: | |
1699 | case SQ_ALU_CONST_CACHE_HS_11: | |
1700 | case SQ_ALU_CONST_CACHE_HS_12: | |
1701 | case SQ_ALU_CONST_CACHE_HS_13: | |
1702 | case SQ_ALU_CONST_CACHE_HS_14: | |
1703 | case SQ_ALU_CONST_CACHE_HS_15: | |
1704 | case SQ_ALU_CONST_CACHE_LS_0: | |
1705 | case SQ_ALU_CONST_CACHE_LS_1: | |
1706 | case SQ_ALU_CONST_CACHE_LS_2: | |
1707 | case SQ_ALU_CONST_CACHE_LS_3: | |
1708 | case SQ_ALU_CONST_CACHE_LS_4: | |
1709 | case SQ_ALU_CONST_CACHE_LS_5: | |
1710 | case SQ_ALU_CONST_CACHE_LS_6: | |
1711 | case SQ_ALU_CONST_CACHE_LS_7: | |
1712 | case SQ_ALU_CONST_CACHE_LS_8: | |
1713 | case SQ_ALU_CONST_CACHE_LS_9: | |
1714 | case SQ_ALU_CONST_CACHE_LS_10: | |
1715 | case SQ_ALU_CONST_CACHE_LS_11: | |
1716 | case SQ_ALU_CONST_CACHE_LS_12: | |
1717 | case SQ_ALU_CONST_CACHE_LS_13: | |
1718 | case SQ_ALU_CONST_CACHE_LS_14: | |
1719 | case SQ_ALU_CONST_CACHE_LS_15: | |
1720 | r = evergreen_cs_packet_next_reloc(p, &reloc); | |
1721 | if (r) { | |
1722 | dev_warn(p->dev, "bad SET_CONTEXT_REG " | |
1723 | "0x%04X\n", reg); | |
1724 | return -EINVAL; | |
1725 | } | |
1726 | ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); | |
1727 | break; | |
033b5650 AD |
1728 | case SX_MEMORY_EXPORT_BASE: |
1729 | if (p->rdev->family >= CHIP_CAYMAN) { | |
1730 | dev_warn(p->dev, "bad SET_CONFIG_REG " | |
1731 | "0x%04X\n", reg); | |
1732 | return -EINVAL; | |
1733 | } | |
1734 | r = evergreen_cs_packet_next_reloc(p, &reloc); | |
1735 | if (r) { | |
1736 | dev_warn(p->dev, "bad SET_CONFIG_REG " | |
1737 | "0x%04X\n", reg); | |
1738 | return -EINVAL; | |
1739 | } | |
1740 | ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); | |
1741 | break; | |
1742 | case CAYMAN_SX_SCATTER_EXPORT_BASE: | |
1743 | if (p->rdev->family < CHIP_CAYMAN) { | |
1744 | dev_warn(p->dev, "bad SET_CONTEXT_REG " | |
1745 | "0x%04X\n", reg); | |
1746 | return -EINVAL; | |
1747 | } | |
1748 | r = evergreen_cs_packet_next_reloc(p, &reloc); | |
1749 | if (r) { | |
1750 | dev_warn(p->dev, "bad SET_CONTEXT_REG " | |
1751 | "0x%04X\n", reg); | |
1752 | return -EINVAL; | |
1753 | } | |
1754 | ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); | |
1755 | break; | |
779923bc MO |
1756 | case SX_MISC: |
1757 | track->sx_misc_kill_all_prims = (radeon_get_ib_value(p, idx) & 0x1) != 0; | |
1758 | break; | |
cb5fcbd5 AD |
1759 | default: |
1760 | dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx); | |
1761 | return -EINVAL; | |
1762 | } | |
1763 | return 0; | |
1764 | } | |
1765 | ||
dd220a00 MO |
1766 | static bool evergreen_is_safe_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) |
1767 | { | |
1768 | u32 last_reg, m, i; | |
1769 | ||
1770 | if (p->rdev->family >= CHIP_CAYMAN) | |
1771 | last_reg = ARRAY_SIZE(cayman_reg_safe_bm); | |
1772 | else | |
1773 | last_reg = ARRAY_SIZE(evergreen_reg_safe_bm); | |
1774 | ||
1775 | i = (reg >> 7); | |
1776 | if (i >= last_reg) { | |
1777 | dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx); | |
1778 | return false; | |
1779 | } | |
1780 | m = 1 << ((reg >> 2) & 31); | |
1781 | if (p->rdev->family >= CHIP_CAYMAN) { | |
1782 | if (!(cayman_reg_safe_bm[i] & m)) | |
1783 | return true; | |
1784 | } else { | |
1785 | if (!(evergreen_reg_safe_bm[i] & m)) | |
1786 | return true; | |
1787 | } | |
1788 | dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx); | |
1789 | return false; | |
1790 | } | |
1791 | ||
cb5fcbd5 AD |
1792 | static int evergreen_packet3_check(struct radeon_cs_parser *p, |
1793 | struct radeon_cs_packet *pkt) | |
1794 | { | |
1795 | struct radeon_cs_reloc *reloc; | |
1796 | struct evergreen_cs_track *track; | |
1797 | volatile u32 *ib; | |
1798 | unsigned idx; | |
1799 | unsigned i; | |
1800 | unsigned start_reg, end_reg, reg; | |
1801 | int r; | |
1802 | u32 idx_value; | |
1803 | ||
1804 | track = (struct evergreen_cs_track *)p->track; | |
1805 | ib = p->ib->ptr; | |
1806 | idx = pkt->idx + 1; | |
1807 | idx_value = radeon_get_ib_value(p, idx); | |
1808 | ||
1809 | switch (pkt->opcode) { | |
2a19cac8 DA |
1810 | case PACKET3_SET_PREDICATION: |
1811 | { | |
1812 | int pred_op; | |
1813 | int tmp; | |
1814 | if (pkt->count != 1) { | |
1815 | DRM_ERROR("bad SET PREDICATION\n"); | |
1816 | return -EINVAL; | |
1817 | } | |
1818 | ||
1819 | tmp = radeon_get_ib_value(p, idx + 1); | |
1820 | pred_op = (tmp >> 16) & 0x7; | |
1821 | ||
1822 | /* for the clear predicate operation */ | |
1823 | if (pred_op == 0) | |
1824 | return 0; | |
1825 | ||
1826 | if (pred_op > 2) { | |
1827 | DRM_ERROR("bad SET PREDICATION operation %d\n", pred_op); | |
1828 | return -EINVAL; | |
1829 | } | |
1830 | ||
1831 | r = evergreen_cs_packet_next_reloc(p, &reloc); | |
1832 | if (r) { | |
1833 | DRM_ERROR("bad SET PREDICATION\n"); | |
1834 | return -EINVAL; | |
1835 | } | |
1836 | ||
1837 | ib[idx + 0] = idx_value + (u32)(reloc->lobj.gpu_offset & 0xffffffff); | |
1838 | ib[idx + 1] = tmp + (upper_32_bits(reloc->lobj.gpu_offset) & 0xff); | |
1839 | } | |
1840 | break; | |
cb5fcbd5 AD |
1841 | case PACKET3_CONTEXT_CONTROL: |
1842 | if (pkt->count != 1) { | |
1843 | DRM_ERROR("bad CONTEXT_CONTROL\n"); | |
1844 | return -EINVAL; | |
1845 | } | |
1846 | break; | |
1847 | case PACKET3_INDEX_TYPE: | |
1848 | case PACKET3_NUM_INSTANCES: | |
1849 | case PACKET3_CLEAR_STATE: | |
1850 | if (pkt->count) { | |
1851 | DRM_ERROR("bad INDEX_TYPE/NUM_INSTANCES/CLEAR_STATE\n"); | |
1852 | return -EINVAL; | |
1853 | } | |
1854 | break; | |
c175ca9a AD |
1855 | case CAYMAN_PACKET3_DEALLOC_STATE: |
1856 | if (p->rdev->family < CHIP_CAYMAN) { | |
1857 | DRM_ERROR("bad PACKET3_DEALLOC_STATE\n"); | |
1858 | return -EINVAL; | |
1859 | } | |
1860 | if (pkt->count) { | |
1861 | DRM_ERROR("bad INDEX_TYPE/NUM_INSTANCES/CLEAR_STATE\n"); | |
1862 | return -EINVAL; | |
1863 | } | |
1864 | break; | |
cb5fcbd5 AD |
1865 | case PACKET3_INDEX_BASE: |
1866 | if (pkt->count != 1) { | |
1867 | DRM_ERROR("bad INDEX_BASE\n"); | |
1868 | return -EINVAL; | |
1869 | } | |
1870 | r = evergreen_cs_packet_next_reloc(p, &reloc); | |
1871 | if (r) { | |
1872 | DRM_ERROR("bad INDEX_BASE\n"); | |
1873 | return -EINVAL; | |
1874 | } | |
1875 | ib[idx+0] = idx_value + (u32)(reloc->lobj.gpu_offset & 0xffffffff); | |
1876 | ib[idx+1] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff; | |
1877 | r = evergreen_cs_track_check(p); | |
1878 | if (r) { | |
1879 | dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__); | |
1880 | return r; | |
1881 | } | |
1882 | break; | |
1883 | case PACKET3_DRAW_INDEX: | |
1884 | if (pkt->count != 3) { | |
1885 | DRM_ERROR("bad DRAW_INDEX\n"); | |
1886 | return -EINVAL; | |
1887 | } | |
1888 | r = evergreen_cs_packet_next_reloc(p, &reloc); | |
1889 | if (r) { | |
1890 | DRM_ERROR("bad DRAW_INDEX\n"); | |
1891 | return -EINVAL; | |
1892 | } | |
1893 | ib[idx+0] = idx_value + (u32)(reloc->lobj.gpu_offset & 0xffffffff); | |
1894 | ib[idx+1] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff; | |
1895 | r = evergreen_cs_track_check(p); | |
1896 | if (r) { | |
1897 | dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__); | |
1898 | return r; | |
1899 | } | |
1900 | break; | |
1901 | case PACKET3_DRAW_INDEX_2: | |
1902 | if (pkt->count != 4) { | |
1903 | DRM_ERROR("bad DRAW_INDEX_2\n"); | |
1904 | return -EINVAL; | |
1905 | } | |
1906 | r = evergreen_cs_packet_next_reloc(p, &reloc); | |
1907 | if (r) { | |
1908 | DRM_ERROR("bad DRAW_INDEX_2\n"); | |
1909 | return -EINVAL; | |
1910 | } | |
1911 | ib[idx+1] = idx_value + (u32)(reloc->lobj.gpu_offset & 0xffffffff); | |
1912 | ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff; | |
1913 | r = evergreen_cs_track_check(p); | |
1914 | if (r) { | |
1915 | dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__); | |
1916 | return r; | |
1917 | } | |
1918 | break; | |
1919 | case PACKET3_DRAW_INDEX_AUTO: | |
1920 | if (pkt->count != 1) { | |
1921 | DRM_ERROR("bad DRAW_INDEX_AUTO\n"); | |
1922 | return -EINVAL; | |
1923 | } | |
1924 | r = evergreen_cs_track_check(p); | |
1925 | if (r) { | |
1926 | dev_warn(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx); | |
1927 | return r; | |
1928 | } | |
1929 | break; | |
1930 | case PACKET3_DRAW_INDEX_MULTI_AUTO: | |
1931 | if (pkt->count != 2) { | |
1932 | DRM_ERROR("bad DRAW_INDEX_MULTI_AUTO\n"); | |
1933 | return -EINVAL; | |
1934 | } | |
1935 | r = evergreen_cs_track_check(p); | |
1936 | if (r) { | |
1937 | dev_warn(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx); | |
1938 | return r; | |
1939 | } | |
1940 | break; | |
1941 | case PACKET3_DRAW_INDEX_IMMD: | |
1942 | if (pkt->count < 2) { | |
1943 | DRM_ERROR("bad DRAW_INDEX_IMMD\n"); | |
1944 | return -EINVAL; | |
1945 | } | |
1946 | r = evergreen_cs_track_check(p); | |
1947 | if (r) { | |
1948 | dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__); | |
1949 | return r; | |
1950 | } | |
1951 | break; | |
1952 | case PACKET3_DRAW_INDEX_OFFSET: | |
1953 | if (pkt->count != 2) { | |
1954 | DRM_ERROR("bad DRAW_INDEX_OFFSET\n"); | |
1955 | return -EINVAL; | |
1956 | } | |
1957 | r = evergreen_cs_track_check(p); | |
1958 | if (r) { | |
1959 | dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__); | |
1960 | return r; | |
1961 | } | |
1962 | break; | |
1963 | case PACKET3_DRAW_INDEX_OFFSET_2: | |
1964 | if (pkt->count != 3) { | |
1965 | DRM_ERROR("bad DRAW_INDEX_OFFSET_2\n"); | |
1966 | return -EINVAL; | |
1967 | } | |
1968 | r = evergreen_cs_track_check(p); | |
1969 | if (r) { | |
1970 | dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__); | |
1971 | return r; | |
1972 | } | |
1973 | break; | |
033b5650 AD |
1974 | case PACKET3_DISPATCH_DIRECT: |
1975 | if (pkt->count != 3) { | |
1976 | DRM_ERROR("bad DISPATCH_DIRECT\n"); | |
1977 | return -EINVAL; | |
1978 | } | |
1979 | r = evergreen_cs_track_check(p); | |
1980 | if (r) { | |
1981 | dev_warn(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx); | |
1982 | return r; | |
1983 | } | |
1984 | break; | |
1985 | case PACKET3_DISPATCH_INDIRECT: | |
1986 | if (pkt->count != 1) { | |
1987 | DRM_ERROR("bad DISPATCH_INDIRECT\n"); | |
1988 | return -EINVAL; | |
1989 | } | |
1990 | r = evergreen_cs_packet_next_reloc(p, &reloc); | |
1991 | if (r) { | |
1992 | DRM_ERROR("bad DISPATCH_INDIRECT\n"); | |
1993 | return -EINVAL; | |
1994 | } | |
1995 | ib[idx+0] = idx_value + (u32)(reloc->lobj.gpu_offset & 0xffffffff); | |
1996 | r = evergreen_cs_track_check(p); | |
1997 | if (r) { | |
1998 | dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__); | |
1999 | return r; | |
2000 | } | |
2001 | break; | |
cb5fcbd5 AD |
2002 | case PACKET3_WAIT_REG_MEM: |
2003 | if (pkt->count != 5) { | |
2004 | DRM_ERROR("bad WAIT_REG_MEM\n"); | |
2005 | return -EINVAL; | |
2006 | } | |
2007 | /* bit 4 is reg (0) or mem (1) */ | |
2008 | if (idx_value & 0x10) { | |
2009 | r = evergreen_cs_packet_next_reloc(p, &reloc); | |
2010 | if (r) { | |
2011 | DRM_ERROR("bad WAIT_REG_MEM\n"); | |
2012 | return -EINVAL; | |
2013 | } | |
2014 | ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff); | |
2015 | ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff; | |
2016 | } | |
2017 | break; | |
2018 | case PACKET3_SURFACE_SYNC: | |
2019 | if (pkt->count != 3) { | |
2020 | DRM_ERROR("bad SURFACE_SYNC\n"); | |
2021 | return -EINVAL; | |
2022 | } | |
2023 | /* 0xffffffff/0x0 is flush all cache flag */ | |
2024 | if (radeon_get_ib_value(p, idx + 1) != 0xffffffff || | |
2025 | radeon_get_ib_value(p, idx + 2) != 0) { | |
2026 | r = evergreen_cs_packet_next_reloc(p, &reloc); | |
2027 | if (r) { | |
2028 | DRM_ERROR("bad SURFACE_SYNC\n"); | |
2029 | return -EINVAL; | |
2030 | } | |
2031 | ib[idx+2] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); | |
2032 | } | |
2033 | break; | |
2034 | case PACKET3_EVENT_WRITE: | |
2035 | if (pkt->count != 2 && pkt->count != 0) { | |
2036 | DRM_ERROR("bad EVENT_WRITE\n"); | |
2037 | return -EINVAL; | |
2038 | } | |
2039 | if (pkt->count) { | |
2040 | r = evergreen_cs_packet_next_reloc(p, &reloc); | |
2041 | if (r) { | |
2042 | DRM_ERROR("bad EVENT_WRITE\n"); | |
2043 | return -EINVAL; | |
2044 | } | |
2045 | ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff); | |
2046 | ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff; | |
2047 | } | |
2048 | break; | |
2049 | case PACKET3_EVENT_WRITE_EOP: | |
2050 | if (pkt->count != 4) { | |
2051 | DRM_ERROR("bad EVENT_WRITE_EOP\n"); | |
2052 | return -EINVAL; | |
2053 | } | |
2054 | r = evergreen_cs_packet_next_reloc(p, &reloc); | |
2055 | if (r) { | |
2056 | DRM_ERROR("bad EVENT_WRITE_EOP\n"); | |
2057 | return -EINVAL; | |
2058 | } | |
2059 | ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff); | |
2060 | ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff; | |
2061 | break; | |
2062 | case PACKET3_EVENT_WRITE_EOS: | |
2063 | if (pkt->count != 3) { | |
2064 | DRM_ERROR("bad EVENT_WRITE_EOS\n"); | |
2065 | return -EINVAL; | |
2066 | } | |
2067 | r = evergreen_cs_packet_next_reloc(p, &reloc); | |
2068 | if (r) { | |
2069 | DRM_ERROR("bad EVENT_WRITE_EOS\n"); | |
2070 | return -EINVAL; | |
2071 | } | |
2072 | ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff); | |
2073 | ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff; | |
2074 | break; | |
2075 | case PACKET3_SET_CONFIG_REG: | |
2076 | start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_START; | |
2077 | end_reg = 4 * pkt->count + start_reg - 4; | |
2078 | if ((start_reg < PACKET3_SET_CONFIG_REG_START) || | |
2079 | (start_reg >= PACKET3_SET_CONFIG_REG_END) || | |
2080 | (end_reg >= PACKET3_SET_CONFIG_REG_END)) { | |
2081 | DRM_ERROR("bad PACKET3_SET_CONFIG_REG\n"); | |
2082 | return -EINVAL; | |
2083 | } | |
2084 | for (i = 0; i < pkt->count; i++) { | |
2085 | reg = start_reg + (4 * i); | |
2086 | r = evergreen_cs_check_reg(p, reg, idx+1+i); | |
2087 | if (r) | |
2088 | return r; | |
2089 | } | |
2090 | break; | |
2091 | case PACKET3_SET_CONTEXT_REG: | |
2092 | start_reg = (idx_value << 2) + PACKET3_SET_CONTEXT_REG_START; | |
2093 | end_reg = 4 * pkt->count + start_reg - 4; | |
2094 | if ((start_reg < PACKET3_SET_CONTEXT_REG_START) || | |
2095 | (start_reg >= PACKET3_SET_CONTEXT_REG_END) || | |
2096 | (end_reg >= PACKET3_SET_CONTEXT_REG_END)) { | |
2097 | DRM_ERROR("bad PACKET3_SET_CONTEXT_REG\n"); | |
2098 | return -EINVAL; | |
2099 | } | |
2100 | for (i = 0; i < pkt->count; i++) { | |
2101 | reg = start_reg + (4 * i); | |
2102 | r = evergreen_cs_check_reg(p, reg, idx+1+i); | |
2103 | if (r) | |
2104 | return r; | |
2105 | } | |
2106 | break; | |
2107 | case PACKET3_SET_RESOURCE: | |
2108 | if (pkt->count % 8) { | |
2109 | DRM_ERROR("bad SET_RESOURCE\n"); | |
2110 | return -EINVAL; | |
2111 | } | |
2112 | start_reg = (idx_value << 2) + PACKET3_SET_RESOURCE_START; | |
2113 | end_reg = 4 * pkt->count + start_reg - 4; | |
2114 | if ((start_reg < PACKET3_SET_RESOURCE_START) || | |
2115 | (start_reg >= PACKET3_SET_RESOURCE_END) || | |
2116 | (end_reg >= PACKET3_SET_RESOURCE_END)) { | |
2117 | DRM_ERROR("bad SET_RESOURCE\n"); | |
2118 | return -EINVAL; | |
2119 | } | |
2120 | for (i = 0; i < (pkt->count / 8); i++) { | |
2121 | struct radeon_bo *texture, *mipmap; | |
285484e2 | 2122 | u32 toffset, moffset; |
cb5fcbd5 AD |
2123 | u32 size, offset; |
2124 | ||
2125 | switch (G__SQ_CONSTANT_TYPE(radeon_get_ib_value(p, idx+1+(i*8)+7))) { | |
2126 | case SQ_TEX_VTX_VALID_TEXTURE: | |
2127 | /* tex base */ | |
2128 | r = evergreen_cs_packet_next_reloc(p, &reloc); | |
2129 | if (r) { | |
2130 | DRM_ERROR("bad SET_RESOURCE (tex)\n"); | |
2131 | return -EINVAL; | |
2132 | } | |
721604a1 | 2133 | if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { |
f3a71df0 AD |
2134 | ib[idx+1+(i*8)+1] |= |
2135 | TEX_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags)); | |
2136 | if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) { | |
285484e2 JG |
2137 | unsigned bankw, bankh, mtaspect, tile_split; |
2138 | ||
2139 | evergreen_tiling_fields(reloc->lobj.tiling_flags, | |
2140 | &bankw, &bankh, &mtaspect, | |
2141 | &tile_split); | |
2142 | ib[idx+1+(i*8)+6] |= TEX_TILE_SPLIT(tile_split); | |
f3a71df0 | 2143 | ib[idx+1+(i*8)+7] |= |
285484e2 JG |
2144 | TEX_BANK_WIDTH(bankw) | |
2145 | TEX_BANK_HEIGHT(bankh) | | |
2146 | MACRO_TILE_ASPECT(mtaspect) | | |
f3a71df0 AD |
2147 | TEX_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks)); |
2148 | } | |
e70f224c | 2149 | } |
cb5fcbd5 | 2150 | texture = reloc->robj; |
285484e2 | 2151 | toffset = (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); |
cb5fcbd5 AD |
2152 | /* tex mip base */ |
2153 | r = evergreen_cs_packet_next_reloc(p, &reloc); | |
2154 | if (r) { | |
2155 | DRM_ERROR("bad SET_RESOURCE (tex)\n"); | |
2156 | return -EINVAL; | |
2157 | } | |
285484e2 | 2158 | moffset = (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); |
cb5fcbd5 | 2159 | mipmap = reloc->robj; |
285484e2 | 2160 | r = evergreen_cs_track_validate_texture(p, texture, mipmap, idx+1+(i*8)); |
cb5fcbd5 AD |
2161 | if (r) |
2162 | return r; | |
285484e2 JG |
2163 | ib[idx+1+(i*8)+2] += toffset; |
2164 | ib[idx+1+(i*8)+3] += moffset; | |
cb5fcbd5 AD |
2165 | break; |
2166 | case SQ_TEX_VTX_VALID_BUFFER: | |
2167 | /* vtx base */ | |
2168 | r = evergreen_cs_packet_next_reloc(p, &reloc); | |
2169 | if (r) { | |
2170 | DRM_ERROR("bad SET_RESOURCE (vtx)\n"); | |
2171 | return -EINVAL; | |
2172 | } | |
2173 | offset = radeon_get_ib_value(p, idx+1+(i*8)+0); | |
2174 | size = radeon_get_ib_value(p, idx+1+(i*8)+1); | |
2175 | if (p->rdev && (size + offset) > radeon_bo_size(reloc->robj)) { | |
2176 | /* force size to size of the buffer */ | |
2177 | dev_warn(p->dev, "vbo resource seems too big for the bo\n"); | |
2178 | ib[idx+1+(i*8)+1] = radeon_bo_size(reloc->robj); | |
2179 | } | |
2180 | ib[idx+1+(i*8)+0] += (u32)((reloc->lobj.gpu_offset) & 0xffffffff); | |
2181 | ib[idx+1+(i*8)+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff; | |
2182 | break; | |
2183 | case SQ_TEX_VTX_INVALID_TEXTURE: | |
2184 | case SQ_TEX_VTX_INVALID_BUFFER: | |
2185 | default: | |
2186 | DRM_ERROR("bad SET_RESOURCE\n"); | |
2187 | return -EINVAL; | |
2188 | } | |
2189 | } | |
2190 | break; | |
2191 | case PACKET3_SET_ALU_CONST: | |
2192 | /* XXX fix me ALU const buffers only */ | |
2193 | break; | |
2194 | case PACKET3_SET_BOOL_CONST: | |
2195 | start_reg = (idx_value << 2) + PACKET3_SET_BOOL_CONST_START; | |
2196 | end_reg = 4 * pkt->count + start_reg - 4; | |
2197 | if ((start_reg < PACKET3_SET_BOOL_CONST_START) || | |
2198 | (start_reg >= PACKET3_SET_BOOL_CONST_END) || | |
2199 | (end_reg >= PACKET3_SET_BOOL_CONST_END)) { | |
2200 | DRM_ERROR("bad SET_BOOL_CONST\n"); | |
2201 | return -EINVAL; | |
2202 | } | |
2203 | break; | |
2204 | case PACKET3_SET_LOOP_CONST: | |
2205 | start_reg = (idx_value << 2) + PACKET3_SET_LOOP_CONST_START; | |
2206 | end_reg = 4 * pkt->count + start_reg - 4; | |
2207 | if ((start_reg < PACKET3_SET_LOOP_CONST_START) || | |
2208 | (start_reg >= PACKET3_SET_LOOP_CONST_END) || | |
2209 | (end_reg >= PACKET3_SET_LOOP_CONST_END)) { | |
2210 | DRM_ERROR("bad SET_LOOP_CONST\n"); | |
2211 | return -EINVAL; | |
2212 | } | |
2213 | break; | |
2214 | case PACKET3_SET_CTL_CONST: | |
2215 | start_reg = (idx_value << 2) + PACKET3_SET_CTL_CONST_START; | |
2216 | end_reg = 4 * pkt->count + start_reg - 4; | |
2217 | if ((start_reg < PACKET3_SET_CTL_CONST_START) || | |
2218 | (start_reg >= PACKET3_SET_CTL_CONST_END) || | |
2219 | (end_reg >= PACKET3_SET_CTL_CONST_END)) { | |
2220 | DRM_ERROR("bad SET_CTL_CONST\n"); | |
2221 | return -EINVAL; | |
2222 | } | |
2223 | break; | |
2224 | case PACKET3_SET_SAMPLER: | |
2225 | if (pkt->count % 3) { | |
2226 | DRM_ERROR("bad SET_SAMPLER\n"); | |
2227 | return -EINVAL; | |
2228 | } | |
2229 | start_reg = (idx_value << 2) + PACKET3_SET_SAMPLER_START; | |
2230 | end_reg = 4 * pkt->count + start_reg - 4; | |
2231 | if ((start_reg < PACKET3_SET_SAMPLER_START) || | |
2232 | (start_reg >= PACKET3_SET_SAMPLER_END) || | |
2233 | (end_reg >= PACKET3_SET_SAMPLER_END)) { | |
2234 | DRM_ERROR("bad SET_SAMPLER\n"); | |
2235 | return -EINVAL; | |
2236 | } | |
2237 | break; | |
dd220a00 MO |
2238 | case PACKET3_STRMOUT_BUFFER_UPDATE: |
2239 | if (pkt->count != 4) { | |
2240 | DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (invalid count)\n"); | |
2241 | return -EINVAL; | |
2242 | } | |
2243 | /* Updating memory at DST_ADDRESS. */ | |
2244 | if (idx_value & 0x1) { | |
2245 | u64 offset; | |
2246 | r = evergreen_cs_packet_next_reloc(p, &reloc); | |
2247 | if (r) { | |
2248 | DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (missing dst reloc)\n"); | |
2249 | return -EINVAL; | |
2250 | } | |
2251 | offset = radeon_get_ib_value(p, idx+1); | |
2252 | offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32; | |
2253 | if ((offset + 4) > radeon_bo_size(reloc->robj)) { | |
2254 | DRM_ERROR("bad STRMOUT_BUFFER_UPDATE dst bo too small: 0x%llx, 0x%lx\n", | |
2255 | offset + 4, radeon_bo_size(reloc->robj)); | |
2256 | return -EINVAL; | |
2257 | } | |
2258 | ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff); | |
2259 | ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff; | |
2260 | } | |
2261 | /* Reading data from SRC_ADDRESS. */ | |
2262 | if (((idx_value >> 1) & 0x3) == 2) { | |
2263 | u64 offset; | |
2264 | r = evergreen_cs_packet_next_reloc(p, &reloc); | |
2265 | if (r) { | |
2266 | DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (missing src reloc)\n"); | |
2267 | return -EINVAL; | |
2268 | } | |
2269 | offset = radeon_get_ib_value(p, idx+3); | |
2270 | offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32; | |
2271 | if ((offset + 4) > radeon_bo_size(reloc->robj)) { | |
2272 | DRM_ERROR("bad STRMOUT_BUFFER_UPDATE src bo too small: 0x%llx, 0x%lx\n", | |
2273 | offset + 4, radeon_bo_size(reloc->robj)); | |
2274 | return -EINVAL; | |
2275 | } | |
2276 | ib[idx+3] += (u32)(reloc->lobj.gpu_offset & 0xffffffff); | |
2277 | ib[idx+4] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff; | |
2278 | } | |
2279 | break; | |
2280 | case PACKET3_COPY_DW: | |
2281 | if (pkt->count != 4) { | |
2282 | DRM_ERROR("bad COPY_DW (invalid count)\n"); | |
2283 | return -EINVAL; | |
2284 | } | |
2285 | if (idx_value & 0x1) { | |
2286 | u64 offset; | |
2287 | /* SRC is memory. */ | |
2288 | r = evergreen_cs_packet_next_reloc(p, &reloc); | |
2289 | if (r) { | |
2290 | DRM_ERROR("bad COPY_DW (missing src reloc)\n"); | |
2291 | return -EINVAL; | |
2292 | } | |
2293 | offset = radeon_get_ib_value(p, idx+1); | |
2294 | offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32; | |
2295 | if ((offset + 4) > radeon_bo_size(reloc->robj)) { | |
2296 | DRM_ERROR("bad COPY_DW src bo too small: 0x%llx, 0x%lx\n", | |
2297 | offset + 4, radeon_bo_size(reloc->robj)); | |
2298 | return -EINVAL; | |
2299 | } | |
2300 | ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff); | |
2301 | ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff; | |
2302 | } else { | |
2303 | /* SRC is a reg. */ | |
2304 | reg = radeon_get_ib_value(p, idx+1) << 2; | |
2305 | if (!evergreen_is_safe_reg(p, reg, idx+1)) | |
2306 | return -EINVAL; | |
2307 | } | |
2308 | if (idx_value & 0x2) { | |
2309 | u64 offset; | |
2310 | /* DST is memory. */ | |
2311 | r = evergreen_cs_packet_next_reloc(p, &reloc); | |
2312 | if (r) { | |
2313 | DRM_ERROR("bad COPY_DW (missing dst reloc)\n"); | |
2314 | return -EINVAL; | |
2315 | } | |
2316 | offset = radeon_get_ib_value(p, idx+3); | |
2317 | offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32; | |
2318 | if ((offset + 4) > radeon_bo_size(reloc->robj)) { | |
2319 | DRM_ERROR("bad COPY_DW dst bo too small: 0x%llx, 0x%lx\n", | |
2320 | offset + 4, radeon_bo_size(reloc->robj)); | |
2321 | return -EINVAL; | |
2322 | } | |
2323 | ib[idx+3] += (u32)(reloc->lobj.gpu_offset & 0xffffffff); | |
2324 | ib[idx+4] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff; | |
2325 | } else { | |
2326 | /* DST is a reg. */ | |
2327 | reg = radeon_get_ib_value(p, idx+3) << 2; | |
2328 | if (!evergreen_is_safe_reg(p, reg, idx+3)) | |
2329 | return -EINVAL; | |
2330 | } | |
2331 | break; | |
cb5fcbd5 AD |
2332 | case PACKET3_NOP: |
2333 | break; | |
2334 | default: | |
2335 | DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode); | |
2336 | return -EINVAL; | |
2337 | } | |
2338 | return 0; | |
2339 | } | |
2340 | ||
2341 | int evergreen_cs_parse(struct radeon_cs_parser *p) | |
2342 | { | |
2343 | struct radeon_cs_packet pkt; | |
2344 | struct evergreen_cs_track *track; | |
f3a71df0 | 2345 | u32 tmp; |
cb5fcbd5 AD |
2346 | int r; |
2347 | ||
2348 | if (p->track == NULL) { | |
2349 | /* initialize tracker, we are in kms */ | |
2350 | track = kzalloc(sizeof(*track), GFP_KERNEL); | |
2351 | if (track == NULL) | |
2352 | return -ENOMEM; | |
2353 | evergreen_cs_track_init(track); | |
f3a71df0 AD |
2354 | if (p->rdev->family >= CHIP_CAYMAN) |
2355 | tmp = p->rdev->config.cayman.tile_config; | |
2356 | else | |
2357 | tmp = p->rdev->config.evergreen.tile_config; | |
2358 | ||
2359 | switch (tmp & 0xf) { | |
2360 | case 0: | |
2361 | track->npipes = 1; | |
2362 | break; | |
2363 | case 1: | |
2364 | default: | |
2365 | track->npipes = 2; | |
2366 | break; | |
2367 | case 2: | |
2368 | track->npipes = 4; | |
2369 | break; | |
2370 | case 3: | |
2371 | track->npipes = 8; | |
2372 | break; | |
2373 | } | |
2374 | ||
2375 | switch ((tmp & 0xf0) >> 4) { | |
2376 | case 0: | |
2377 | track->nbanks = 4; | |
2378 | break; | |
2379 | case 1: | |
2380 | default: | |
2381 | track->nbanks = 8; | |
2382 | break; | |
2383 | case 2: | |
2384 | track->nbanks = 16; | |
2385 | break; | |
2386 | } | |
2387 | ||
2388 | switch ((tmp & 0xf00) >> 8) { | |
2389 | case 0: | |
2390 | track->group_size = 256; | |
2391 | break; | |
2392 | case 1: | |
2393 | default: | |
2394 | track->group_size = 512; | |
2395 | break; | |
2396 | } | |
2397 | ||
2398 | switch ((tmp & 0xf000) >> 12) { | |
2399 | case 0: | |
2400 | track->row_size = 1; | |
2401 | break; | |
2402 | case 1: | |
2403 | default: | |
2404 | track->row_size = 2; | |
2405 | break; | |
2406 | case 2: | |
2407 | track->row_size = 4; | |
2408 | break; | |
2409 | } | |
2410 | ||
cb5fcbd5 AD |
2411 | p->track = track; |
2412 | } | |
2413 | do { | |
2414 | r = evergreen_cs_packet_parse(p, &pkt, p->idx); | |
2415 | if (r) { | |
2416 | kfree(p->track); | |
2417 | p->track = NULL; | |
2418 | return r; | |
2419 | } | |
2420 | p->idx += pkt.count + 2; | |
2421 | switch (pkt.type) { | |
2422 | case PACKET_TYPE0: | |
2423 | r = evergreen_cs_parse_packet0(p, &pkt); | |
2424 | break; | |
2425 | case PACKET_TYPE2: | |
2426 | break; | |
2427 | case PACKET_TYPE3: | |
2428 | r = evergreen_packet3_check(p, &pkt); | |
2429 | break; | |
2430 | default: | |
2431 | DRM_ERROR("Unknown packet type %d !\n", pkt.type); | |
2432 | kfree(p->track); | |
2433 | p->track = NULL; | |
2434 | return -EINVAL; | |
2435 | } | |
2436 | if (r) { | |
2437 | kfree(p->track); | |
2438 | p->track = NULL; | |
2439 | return r; | |
2440 | } | |
2441 | } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw); | |
2442 | #if 0 | |
2443 | for (r = 0; r < p->ib->length_dw; r++) { | |
2444 | printk(KERN_INFO "%05d 0x%08X\n", r, p->ib->ptr[r]); | |
2445 | mdelay(1); | |
2446 | } | |
2447 | #endif | |
2448 | kfree(p->track); | |
2449 | p->track = NULL; | |
2450 | return 0; | |
2451 | } | |
2452 | ||
721604a1 JG |
2453 | /* vm parser */ |
2454 | static bool evergreen_vm_reg_valid(u32 reg) | |
2455 | { | |
2456 | /* context regs are fine */ | |
2457 | if (reg >= 0x28000) | |
2458 | return true; | |
2459 | ||
2460 | /* check config regs */ | |
2461 | switch (reg) { | |
2462 | case GRBM_GFX_INDEX: | |
2463 | case VGT_VTX_VECT_EJECT_REG: | |
2464 | case VGT_CACHE_INVALIDATION: | |
2465 | case VGT_GS_VERTEX_REUSE: | |
2466 | case VGT_PRIMITIVE_TYPE: | |
2467 | case VGT_INDEX_TYPE: | |
2468 | case VGT_NUM_INDICES: | |
2469 | case VGT_NUM_INSTANCES: | |
2470 | case VGT_COMPUTE_DIM_X: | |
2471 | case VGT_COMPUTE_DIM_Y: | |
2472 | case VGT_COMPUTE_DIM_Z: | |
2473 | case VGT_COMPUTE_START_X: | |
2474 | case VGT_COMPUTE_START_Y: | |
2475 | case VGT_COMPUTE_START_Z: | |
2476 | case VGT_COMPUTE_INDEX: | |
2477 | case VGT_COMPUTE_THREAD_GROUP_SIZE: | |
2478 | case VGT_HS_OFFCHIP_PARAM: | |
2479 | case PA_CL_ENHANCE: | |
2480 | case PA_SU_LINE_STIPPLE_VALUE: | |
2481 | case PA_SC_LINE_STIPPLE_STATE: | |
2482 | case PA_SC_ENHANCE: | |
2483 | case SQ_DYN_GPR_CNTL_PS_FLUSH_REQ: | |
2484 | case SQ_DYN_GPR_SIMD_LOCK_EN: | |
2485 | case SQ_CONFIG: | |
2486 | case SQ_GPR_RESOURCE_MGMT_1: | |
2487 | case SQ_GLOBAL_GPR_RESOURCE_MGMT_1: | |
2488 | case SQ_GLOBAL_GPR_RESOURCE_MGMT_2: | |
2489 | case SQ_CONST_MEM_BASE: | |
2490 | case SQ_STATIC_THREAD_MGMT_1: | |
2491 | case SQ_STATIC_THREAD_MGMT_2: | |
2492 | case SQ_STATIC_THREAD_MGMT_3: | |
2493 | case SPI_CONFIG_CNTL: | |
2494 | case SPI_CONFIG_CNTL_1: | |
2495 | case TA_CNTL_AUX: | |
2496 | case DB_DEBUG: | |
2497 | case DB_DEBUG2: | |
2498 | case DB_DEBUG3: | |
2499 | case DB_DEBUG4: | |
2500 | case DB_WATERMARKS: | |
2501 | case TD_PS_BORDER_COLOR_INDEX: | |
2502 | case TD_PS_BORDER_COLOR_RED: | |
2503 | case TD_PS_BORDER_COLOR_GREEN: | |
2504 | case TD_PS_BORDER_COLOR_BLUE: | |
2505 | case TD_PS_BORDER_COLOR_ALPHA: | |
2506 | case TD_VS_BORDER_COLOR_INDEX: | |
2507 | case TD_VS_BORDER_COLOR_RED: | |
2508 | case TD_VS_BORDER_COLOR_GREEN: | |
2509 | case TD_VS_BORDER_COLOR_BLUE: | |
2510 | case TD_VS_BORDER_COLOR_ALPHA: | |
2511 | case TD_GS_BORDER_COLOR_INDEX: | |
2512 | case TD_GS_BORDER_COLOR_RED: | |
2513 | case TD_GS_BORDER_COLOR_GREEN: | |
2514 | case TD_GS_BORDER_COLOR_BLUE: | |
2515 | case TD_GS_BORDER_COLOR_ALPHA: | |
2516 | case TD_HS_BORDER_COLOR_INDEX: | |
2517 | case TD_HS_BORDER_COLOR_RED: | |
2518 | case TD_HS_BORDER_COLOR_GREEN: | |
2519 | case TD_HS_BORDER_COLOR_BLUE: | |
2520 | case TD_HS_BORDER_COLOR_ALPHA: | |
2521 | case TD_LS_BORDER_COLOR_INDEX: | |
2522 | case TD_LS_BORDER_COLOR_RED: | |
2523 | case TD_LS_BORDER_COLOR_GREEN: | |
2524 | case TD_LS_BORDER_COLOR_BLUE: | |
2525 | case TD_LS_BORDER_COLOR_ALPHA: | |
2526 | case TD_CS_BORDER_COLOR_INDEX: | |
2527 | case TD_CS_BORDER_COLOR_RED: | |
2528 | case TD_CS_BORDER_COLOR_GREEN: | |
2529 | case TD_CS_BORDER_COLOR_BLUE: | |
2530 | case TD_CS_BORDER_COLOR_ALPHA: | |
2531 | case SQ_ESGS_RING_SIZE: | |
2532 | case SQ_GSVS_RING_SIZE: | |
2533 | case SQ_ESTMP_RING_SIZE: | |
2534 | case SQ_GSTMP_RING_SIZE: | |
2535 | case SQ_HSTMP_RING_SIZE: | |
2536 | case SQ_LSTMP_RING_SIZE: | |
2537 | case SQ_PSTMP_RING_SIZE: | |
2538 | case SQ_VSTMP_RING_SIZE: | |
2539 | case SQ_ESGS_RING_ITEMSIZE: | |
2540 | case SQ_ESTMP_RING_ITEMSIZE: | |
2541 | case SQ_GSTMP_RING_ITEMSIZE: | |
2542 | case SQ_GSVS_RING_ITEMSIZE: | |
2543 | case SQ_GS_VERT_ITEMSIZE: | |
2544 | case SQ_GS_VERT_ITEMSIZE_1: | |
2545 | case SQ_GS_VERT_ITEMSIZE_2: | |
2546 | case SQ_GS_VERT_ITEMSIZE_3: | |
2547 | case SQ_GSVS_RING_OFFSET_1: | |
2548 | case SQ_GSVS_RING_OFFSET_2: | |
2549 | case SQ_GSVS_RING_OFFSET_3: | |
2550 | case SQ_HSTMP_RING_ITEMSIZE: | |
2551 | case SQ_LSTMP_RING_ITEMSIZE: | |
2552 | case SQ_PSTMP_RING_ITEMSIZE: | |
2553 | case SQ_VSTMP_RING_ITEMSIZE: | |
2554 | case VGT_TF_RING_SIZE: | |
2555 | case SQ_ESGS_RING_BASE: | |
2556 | case SQ_GSVS_RING_BASE: | |
2557 | case SQ_ESTMP_RING_BASE: | |
2558 | case SQ_GSTMP_RING_BASE: | |
2559 | case SQ_HSTMP_RING_BASE: | |
2560 | case SQ_LSTMP_RING_BASE: | |
2561 | case SQ_PSTMP_RING_BASE: | |
2562 | case SQ_VSTMP_RING_BASE: | |
2563 | case CAYMAN_VGT_OFFCHIP_LDS_BASE: | |
2564 | case CAYMAN_SQ_EX_ALLOC_TABLE_SLOTS: | |
2565 | return true; | |
2566 | default: | |
2567 | return false; | |
2568 | } | |
2569 | } | |
2570 | ||
2571 | static int evergreen_vm_packet3_check(struct radeon_device *rdev, | |
2572 | u32 *ib, struct radeon_cs_packet *pkt) | |
2573 | { | |
2574 | u32 idx = pkt->idx + 1; | |
2575 | u32 idx_value = ib[idx]; | |
2576 | u32 start_reg, end_reg, reg, i; | |
2577 | ||
2578 | switch (pkt->opcode) { | |
2579 | case PACKET3_NOP: | |
2580 | case PACKET3_SET_BASE: | |
2581 | case PACKET3_CLEAR_STATE: | |
2582 | case PACKET3_INDEX_BUFFER_SIZE: | |
2583 | case PACKET3_DISPATCH_DIRECT: | |
2584 | case PACKET3_DISPATCH_INDIRECT: | |
2585 | case PACKET3_MODE_CONTROL: | |
2586 | case PACKET3_SET_PREDICATION: | |
2587 | case PACKET3_COND_EXEC: | |
2588 | case PACKET3_PRED_EXEC: | |
2589 | case PACKET3_DRAW_INDIRECT: | |
2590 | case PACKET3_DRAW_INDEX_INDIRECT: | |
2591 | case PACKET3_INDEX_BASE: | |
2592 | case PACKET3_DRAW_INDEX_2: | |
2593 | case PACKET3_CONTEXT_CONTROL: | |
2594 | case PACKET3_DRAW_INDEX_OFFSET: | |
2595 | case PACKET3_INDEX_TYPE: | |
2596 | case PACKET3_DRAW_INDEX: | |
2597 | case PACKET3_DRAW_INDEX_AUTO: | |
2598 | case PACKET3_DRAW_INDEX_IMMD: | |
2599 | case PACKET3_NUM_INSTANCES: | |
2600 | case PACKET3_DRAW_INDEX_MULTI_AUTO: | |
2601 | case PACKET3_STRMOUT_BUFFER_UPDATE: | |
2602 | case PACKET3_DRAW_INDEX_OFFSET_2: | |
2603 | case PACKET3_DRAW_INDEX_MULTI_ELEMENT: | |
2604 | case PACKET3_MPEG_INDEX: | |
2605 | case PACKET3_WAIT_REG_MEM: | |
2606 | case PACKET3_MEM_WRITE: | |
2607 | case PACKET3_SURFACE_SYNC: | |
2608 | case PACKET3_EVENT_WRITE: | |
2609 | case PACKET3_EVENT_WRITE_EOP: | |
2610 | case PACKET3_EVENT_WRITE_EOS: | |
2611 | case PACKET3_SET_CONTEXT_REG: | |
2612 | case PACKET3_SET_BOOL_CONST: | |
2613 | case PACKET3_SET_LOOP_CONST: | |
2614 | case PACKET3_SET_RESOURCE: | |
2615 | case PACKET3_SET_SAMPLER: | |
2616 | case PACKET3_SET_CTL_CONST: | |
2617 | case PACKET3_SET_RESOURCE_OFFSET: | |
2618 | case PACKET3_SET_CONTEXT_REG_INDIRECT: | |
2619 | case PACKET3_SET_RESOURCE_INDIRECT: | |
2620 | case CAYMAN_PACKET3_DEALLOC_STATE: | |
2621 | break; | |
2622 | case PACKET3_COND_WRITE: | |
2623 | if (idx_value & 0x100) { | |
2624 | reg = ib[idx + 5] * 4; | |
2625 | if (!evergreen_vm_reg_valid(reg)) | |
2626 | return -EINVAL; | |
2627 | } | |
2628 | break; | |
2629 | case PACKET3_COPY_DW: | |
2630 | if (idx_value & 0x2) { | |
2631 | reg = ib[idx + 3] * 4; | |
2632 | if (!evergreen_vm_reg_valid(reg)) | |
2633 | return -EINVAL; | |
2634 | } | |
2635 | break; | |
2636 | case PACKET3_SET_CONFIG_REG: | |
2637 | start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_START; | |
2638 | end_reg = 4 * pkt->count + start_reg - 4; | |
2639 | if ((start_reg < PACKET3_SET_CONFIG_REG_START) || | |
2640 | (start_reg >= PACKET3_SET_CONFIG_REG_END) || | |
2641 | (end_reg >= PACKET3_SET_CONFIG_REG_END)) { | |
2642 | DRM_ERROR("bad PACKET3_SET_CONFIG_REG\n"); | |
2643 | return -EINVAL; | |
2644 | } | |
2645 | for (i = 0; i < pkt->count; i++) { | |
2646 | reg = start_reg + (4 * i); | |
2647 | if (!evergreen_vm_reg_valid(reg)) | |
2648 | return -EINVAL; | |
2649 | } | |
2650 | break; | |
2651 | default: | |
2652 | return -EINVAL; | |
2653 | } | |
2654 | return 0; | |
2655 | } | |
2656 | ||
2657 | int evergreen_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib) | |
2658 | { | |
2659 | int ret = 0; | |
2660 | u32 idx = 0; | |
2661 | struct radeon_cs_packet pkt; | |
2662 | ||
2663 | do { | |
2664 | pkt.idx = idx; | |
2665 | pkt.type = CP_PACKET_GET_TYPE(ib->ptr[idx]); | |
2666 | pkt.count = CP_PACKET_GET_COUNT(ib->ptr[idx]); | |
2667 | pkt.one_reg_wr = 0; | |
2668 | switch (pkt.type) { | |
2669 | case PACKET_TYPE0: | |
2670 | dev_err(rdev->dev, "Packet0 not allowed!\n"); | |
2671 | ret = -EINVAL; | |
2672 | break; | |
2673 | case PACKET_TYPE2: | |
0b41da60 | 2674 | idx += 1; |
721604a1 JG |
2675 | break; |
2676 | case PACKET_TYPE3: | |
2677 | pkt.opcode = CP_PACKET3_GET_OPCODE(ib->ptr[idx]); | |
2678 | ret = evergreen_vm_packet3_check(rdev, ib->ptr, &pkt); | |
0b41da60 | 2679 | idx += pkt.count + 2; |
721604a1 JG |
2680 | break; |
2681 | default: | |
2682 | dev_err(rdev->dev, "Unknown packet type %d !\n", pkt.type); | |
2683 | ret = -EINVAL; | |
2684 | break; | |
2685 | } | |
2686 | if (ret) | |
2687 | break; | |
721604a1 JG |
2688 | } while (idx < ib->length_dw); |
2689 | ||
2690 | return ret; | |
2691 | } |