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drm/radeon: pull out common next_reloc function
[deliverable/linux.git] / drivers / gpu / drm / radeon / evergreen_cs.c
CommitLineData
cb5fcbd5
AD		 1/*
2 * Copyright 2010 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
760285e7 28#include <drm/drmP.h>
cb5fcbd5
AD		 29#include "radeon.h"
30#include "evergreend.h"
31#include "evergreen_reg_safe.h"
c175ca9a 32#include "cayman_reg_safe.h"
cb5fcbd5 33
285484e2
JG		 34#define MAX(a,b) (((a)>(b))?(a):(b))
35#define MIN(a,b) (((a)<(b))?(a):(b))
36
d2ead3ea
AD		 37int r600_dma_cs_next_reloc(struct radeon_cs_parser *p,
38 struct radeon_cs_reloc **cs_reloc);
cb5fcbd5
AD		 39static int evergreen_cs_packet_next_reloc(struct radeon_cs_parser *p,
40 struct radeon_cs_reloc **cs_reloc);
41
42struct evergreen_cs_track {
43 u32 group_size;
44 u32 nbanks;
45 u32 npipes;
f3a71df0 46 u32 row_size;
cb5fcbd5 47 /* value we track */
747e42a1 48 u32 nsamples; /* unused */
cb5fcbd5
AD		 49 struct radeon_bo *cb_color_bo[12];
50 u32 cb_color_bo_offset[12];
747e42a1
MO		 51 struct radeon_bo *cb_color_fmask_bo[8]; /* unused */
52 struct radeon_bo *cb_color_cmask_bo[8]; /* unused */
cb5fcbd5
AD		 53 u32 cb_color_info[12];
54 u32 cb_color_view[12];
cb5fcbd5
AD		 55 u32 cb_color_pitch[12];
56 u32 cb_color_slice[12];
d2609875 57 u32 cb_color_slice_idx[12];
285484e2 58 u32 cb_color_attrib[12];
747e42a1
MO		 59 u32 cb_color_cmask_slice[8];/* unused */
60 u32 cb_color_fmask_slice[8];/* unused */
cb5fcbd5 61 u32 cb_target_mask;
747e42a1 62 u32 cb_shader_mask; /* unused */
cb5fcbd5
AD		 63 u32 vgt_strmout_config;
64 u32 vgt_strmout_buffer_config;
dd220a00 65 struct radeon_bo *vgt_strmout_bo[4];
dd220a00
MO		 66 u32 vgt_strmout_bo_offset[4];
67 u32 vgt_strmout_size[4];
cb5fcbd5
AD		 68 u32 db_depth_control;
69 u32 db_depth_view;
285484e2 70 u32 db_depth_slice;
cb5fcbd5 71 u32 db_depth_size;
cb5fcbd5 72 u32 db_z_info;
cb5fcbd5
AD		 73 u32 db_z_read_offset;
74 u32 db_z_write_offset;
75 struct radeon_bo *db_z_read_bo;
76 struct radeon_bo *db_z_write_bo;
77 u32 db_s_info;
cb5fcbd5
AD		 78 u32 db_s_read_offset;
79 u32 db_s_write_offset;
80 struct radeon_bo *db_s_read_bo;
81 struct radeon_bo *db_s_write_bo;
779923bc 82 bool sx_misc_kill_all_prims;
30838578
MO		 83 bool cb_dirty;
84 bool db_dirty;
85 bool streamout_dirty;
88f50c80
JG		 86 u32 htile_offset;
87 u32 htile_surface;
88 struct radeon_bo *htile_bo;
cb5fcbd5
AD		 89};
90
f3a71df0
AD		 91static u32 evergreen_cs_get_aray_mode(u32 tiling_flags)
92{
93 if (tiling_flags & RADEON_TILING_MACRO)
94 return ARRAY_2D_TILED_THIN1;
95 else if (tiling_flags & RADEON_TILING_MICRO)
96 return ARRAY_1D_TILED_THIN1;
97 else
98 return ARRAY_LINEAR_GENERAL;
99}
100
101static u32 evergreen_cs_get_num_banks(u32 nbanks)
102{
103 switch (nbanks) {
104 case 2:
105 return ADDR_SURF_2_BANK;
106 case 4:
107 return ADDR_SURF_4_BANK;
108 case 8:
109 default:
110 return ADDR_SURF_8_BANK;
111 case 16:
112 return ADDR_SURF_16_BANK;
113 }
114}
115
cb5fcbd5
AD		 116static void evergreen_cs_track_init(struct evergreen_cs_track *track)
117{
118 int i;
119
120 for (i = 0; i < 8; i++) {
121 track->cb_color_fmask_bo[i] = NULL;
122 track->cb_color_cmask_bo[i] = NULL;
123 track->cb_color_cmask_slice[i] = 0;
124 track->cb_color_fmask_slice[i] = 0;
125 }
126
127 for (i = 0; i < 12; i++) {
cb5fcbd5
AD		 128 track->cb_color_bo[i] = NULL;
129 track->cb_color_bo_offset[i] = 0xFFFFFFFF;
130 track->cb_color_info[i] = 0;
285484e2 131 track->cb_color_view[i] = 0xFFFFFFFF;
cb5fcbd5 132 track->cb_color_pitch[i] = 0;
d2609875
JG		 133 track->cb_color_slice[i] = 0xfffffff;
134 track->cb_color_slice_idx[i] = 0;
cb5fcbd5
AD		 135 }
136 track->cb_target_mask = 0xFFFFFFFF;
137 track->cb_shader_mask = 0xFFFFFFFF;
30838578 138 track->cb_dirty = true;
cb5fcbd5 139
d2609875 140 track->db_depth_slice = 0xffffffff;
cb5fcbd5
AD		 141 track->db_depth_view = 0xFFFFC000;
142 track->db_depth_size = 0xFFFFFFFF;
cb5fcbd5
AD		 143 track->db_depth_control = 0xFFFFFFFF;
144 track->db_z_info = 0xFFFFFFFF;
cb5fcbd5
AD		 145 track->db_z_read_offset = 0xFFFFFFFF;
146 track->db_z_write_offset = 0xFFFFFFFF;
147 track->db_z_read_bo = NULL;
148 track->db_z_write_bo = NULL;
149 track->db_s_info = 0xFFFFFFFF;
cb5fcbd5
AD		 150 track->db_s_read_offset = 0xFFFFFFFF;
151 track->db_s_write_offset = 0xFFFFFFFF;
152 track->db_s_read_bo = NULL;
153 track->db_s_write_bo = NULL;
30838578 154 track->db_dirty = true;
88f50c80
JG		 155 track->htile_bo = NULL;
156 track->htile_offset = 0xFFFFFFFF;
157 track->htile_surface = 0;
dd220a00
MO		 158
159 for (i = 0; i < 4; i++) {
160 track->vgt_strmout_size[i] = 0;
161 track->vgt_strmout_bo[i] = NULL;
162 track->vgt_strmout_bo_offset[i] = 0xFFFFFFFF;
dd220a00 163 }
30838578 164 track->streamout_dirty = true;
779923bc 165 track->sx_misc_kill_all_prims = false;
cb5fcbd5
AD		 166}
167
285484e2
JG		 168struct eg_surface {
169 /* value gathered from cs */
170 unsigned nbx;
171 unsigned nby;
172 unsigned format;
173 unsigned mode;
174 unsigned nbanks;
175 unsigned bankw;
176 unsigned bankh;
177 unsigned tsplit;
178 unsigned mtilea;
179 unsigned nsamples;
180 /* output value */
181 unsigned bpe;
182 unsigned layer_size;
183 unsigned palign;
184 unsigned halign;
185 unsigned long base_align;
186};
187
188static int evergreen_surface_check_linear(struct radeon_cs_parser *p,
189 struct eg_surface *surf,
190 const char *prefix)
191{
192 surf->layer_size = surf->nbx * surf->nby * surf->bpe * surf->nsamples;
193 surf->base_align = surf->bpe;
194 surf->palign = 1;
195 surf->halign = 1;
196 return 0;
197}
198
199static int evergreen_surface_check_linear_aligned(struct radeon_cs_parser *p,
200 struct eg_surface *surf,
201 const char *prefix)
202{
203 struct evergreen_cs_track *track = p->track;
204 unsigned palign;
205
206 palign = MAX(64, track->group_size / surf->bpe);
207 surf->layer_size = surf->nbx * surf->nby * surf->bpe * surf->nsamples;
208 surf->base_align = track->group_size;
209 surf->palign = palign;
210 surf->halign = 1;
211 if (surf->nbx & (palign - 1)) {
212 if (prefix) {
213 dev_warn(p->dev, "%s:%d %s pitch %d invalid must be aligned with %d\n",
214 __func__, __LINE__, prefix, surf->nbx, palign);
215 }
216 return -EINVAL;
217 }
218 return 0;
219}
220
221static int evergreen_surface_check_1d(struct radeon_cs_parser *p,
222 struct eg_surface *surf,
223 const char *prefix)
224{
225 struct evergreen_cs_track *track = p->track;
226 unsigned palign;
227
228 palign = track->group_size / (8 * surf->bpe * surf->nsamples);
229 palign = MAX(8, palign);
230 surf->layer_size = surf->nbx * surf->nby * surf->bpe;
231 surf->base_align = track->group_size;
232 surf->palign = palign;
233 surf->halign = 8;
234 if ((surf->nbx & (palign - 1))) {
235 if (prefix) {
236 dev_warn(p->dev, "%s:%d %s pitch %d invalid must be aligned with %d (%d %d %d)\n",
237 __func__, __LINE__, prefix, surf->nbx, palign,
238 track->group_size, surf->bpe, surf->nsamples);
239 }
240 return -EINVAL;
241 }
242 if ((surf->nby & (8 - 1))) {
243 if (prefix) {
244 dev_warn(p->dev, "%s:%d %s height %d invalid must be aligned with 8\n",
245 __func__, __LINE__, prefix, surf->nby);
246 }
247 return -EINVAL;
248 }
249 return 0;
250}
251
252static int evergreen_surface_check_2d(struct radeon_cs_parser *p,
253 struct eg_surface *surf,
254 const char *prefix)
255{
256 struct evergreen_cs_track *track = p->track;
257 unsigned palign, halign, tileb, slice_pt;
d2609875 258 unsigned mtile_pr, mtile_ps, mtileb;
285484e2
JG		 259
260 tileb = 64 * surf->bpe * surf->nsamples;
285484e2
JG		 261 slice_pt = 1;
262 if (tileb > surf->tsplit) {
263 slice_pt = tileb / surf->tsplit;
264 }
265 tileb = tileb / slice_pt;
266 /* macro tile width & height */
267 palign = (8 * surf->bankw * track->npipes) * surf->mtilea;
268 halign = (8 * surf->bankh * surf->nbanks) / surf->mtilea;
74e4ca32 269 mtileb = (palign / 8) * (halign / 8) * tileb;
d2609875
JG		 270 mtile_pr = surf->nbx / palign;
271 mtile_ps = (mtile_pr * surf->nby) / halign;
272 surf->layer_size = mtile_ps * mtileb * slice_pt;
285484e2
JG		 273 surf->base_align = (palign / 8) * (halign / 8) * tileb;
274 surf->palign = palign;
275 surf->halign = halign;
276
277 if ((surf->nbx & (palign - 1))) {
278 if (prefix) {
279 dev_warn(p->dev, "%s:%d %s pitch %d invalid must be aligned with %d\n",
280 __func__, __LINE__, prefix, surf->nbx, palign);
281 }
282 return -EINVAL;
283 }
284 if ((surf->nby & (halign - 1))) {
285 if (prefix) {
286 dev_warn(p->dev, "%s:%d %s height %d invalid must be aligned with %d\n",
287 __func__, __LINE__, prefix, surf->nby, halign);
288 }
289 return -EINVAL;
290 }
291
292 return 0;
293}
294
295static int evergreen_surface_check(struct radeon_cs_parser *p,
296 struct eg_surface *surf,
297 const char *prefix)
298{
299 /* some common value computed here */
300 surf->bpe = r600_fmt_get_blocksize(surf->format);
301
302 switch (surf->mode) {
303 case ARRAY_LINEAR_GENERAL:
304 return evergreen_surface_check_linear(p, surf, prefix);
305 case ARRAY_LINEAR_ALIGNED:
306 return evergreen_surface_check_linear_aligned(p, surf, prefix);
307 case ARRAY_1D_TILED_THIN1:
308 return evergreen_surface_check_1d(p, surf, prefix);
309 case ARRAY_2D_TILED_THIN1:
310 return evergreen_surface_check_2d(p, surf, prefix);
311 default:
7df7c547
MO		 312 dev_warn(p->dev, "%s:%d %s invalid array mode %d\n",
313 __func__, __LINE__, prefix, surf->mode);
285484e2
JG		 314 return -EINVAL;
315 }
316 return -EINVAL;
317}
318
319static int evergreen_surface_value_conv_check(struct radeon_cs_parser *p,
320 struct eg_surface *surf,
321 const char *prefix)
322{
323 switch (surf->mode) {
324 case ARRAY_2D_TILED_THIN1:
325 break;
326 case ARRAY_LINEAR_GENERAL:
327 case ARRAY_LINEAR_ALIGNED:
328 case ARRAY_1D_TILED_THIN1:
329 return 0;
330 default:
7df7c547
MO		 331 dev_warn(p->dev, "%s:%d %s invalid array mode %d\n",
332 __func__, __LINE__, prefix, surf->mode);
285484e2
JG		 333 return -EINVAL;
334 }
335
336 switch (surf->nbanks) {
337 case 0: surf->nbanks = 2; break;
338 case 1: surf->nbanks = 4; break;
339 case 2: surf->nbanks = 8; break;
340 case 3: surf->nbanks = 16; break;
341 default:
342 dev_warn(p->dev, "%s:%d %s invalid number of banks %d\n",
343 __func__, __LINE__, prefix, surf->nbanks);
344 return -EINVAL;
345 }
346 switch (surf->bankw) {
347 case 0: surf->bankw = 1; break;
348 case 1: surf->bankw = 2; break;
349 case 2: surf->bankw = 4; break;
350 case 3: surf->bankw = 8; break;
351 default:
352 dev_warn(p->dev, "%s:%d %s invalid bankw %d\n",
353 __func__, __LINE__, prefix, surf->bankw);
354 return -EINVAL;
355 }
356 switch (surf->bankh) {
357 case 0: surf->bankh = 1; break;
358 case 1: surf->bankh = 2; break;
359 case 2: surf->bankh = 4; break;
360 case 3: surf->bankh = 8; break;
361 default:
362 dev_warn(p->dev, "%s:%d %s invalid bankh %d\n",
363 __func__, __LINE__, prefix, surf->bankh);
364 return -EINVAL;
365 }
366 switch (surf->mtilea) {
367 case 0: surf->mtilea = 1; break;
368 case 1: surf->mtilea = 2; break;
369 case 2: surf->mtilea = 4; break;
370 case 3: surf->mtilea = 8; break;
371 default:
372 dev_warn(p->dev, "%s:%d %s invalid macro tile aspect %d\n",
373 __func__, __LINE__, prefix, surf->mtilea);
374 return -EINVAL;
375 }
376 switch (surf->tsplit) {
377 case 0: surf->tsplit = 64; break;
378 case 1: surf->tsplit = 128; break;
379 case 2: surf->tsplit = 256; break;
380 case 3: surf->tsplit = 512; break;
381 case 4: surf->tsplit = 1024; break;
382 case 5: surf->tsplit = 2048; break;
383 case 6: surf->tsplit = 4096; break;
384 default:
385 dev_warn(p->dev, "%s:%d %s invalid tile split %d\n",
386 __func__, __LINE__, prefix, surf->tsplit);
387 return -EINVAL;
388 }
389 return 0;
390}
391
392static int evergreen_cs_track_validate_cb(struct radeon_cs_parser *p, unsigned id)
393{
394 struct evergreen_cs_track *track = p->track;
395 struct eg_surface surf;
396 unsigned pitch, slice, mslice;
397 unsigned long offset;
398 int r;
399
400 mslice = G_028C6C_SLICE_MAX(track->cb_color_view[id]) + 1;
401 pitch = track->cb_color_pitch[id];
402 slice = track->cb_color_slice[id];
403 surf.nbx = (pitch + 1) * 8;
404 surf.nby = ((slice + 1) * 64) / surf.nbx;
405 surf.mode = G_028C70_ARRAY_MODE(track->cb_color_info[id]);
406 surf.format = G_028C70_FORMAT(track->cb_color_info[id]);
407 surf.tsplit = G_028C74_TILE_SPLIT(track->cb_color_attrib[id]);
408 surf.nbanks = G_028C74_NUM_BANKS(track->cb_color_attrib[id]);
409 surf.bankw = G_028C74_BANK_WIDTH(track->cb_color_attrib[id]);
410 surf.bankh = G_028C74_BANK_HEIGHT(track->cb_color_attrib[id]);
411 surf.mtilea = G_028C74_MACRO_TILE_ASPECT(track->cb_color_attrib[id]);
412 surf.nsamples = 1;
413
414 if (!r600_fmt_is_valid_color(surf.format)) {
415 dev_warn(p->dev, "%s:%d cb invalid format %d for %d (0x%08x)\n",
416 __func__, __LINE__, surf.format,
417 id, track->cb_color_info[id]);
418 return -EINVAL;
419 }
420
421 r = evergreen_surface_value_conv_check(p, &surf, "cb");
422 if (r) {
423 return r;
424 }
425
426 r = evergreen_surface_check(p, &surf, "cb");
427 if (r) {
428 dev_warn(p->dev, "%s:%d cb[%d] invalid (0x%08x 0x%08x 0x%08x 0x%08x)\n",
429 __func__, __LINE__, id, track->cb_color_pitch[id],
430 track->cb_color_slice[id], track->cb_color_attrib[id],
431 track->cb_color_info[id]);
432 return r;
433 }
434
435 offset = track->cb_color_bo_offset[id] << 8;
436 if (offset & (surf.base_align - 1)) {
437 dev_warn(p->dev, "%s:%d cb[%d] bo base %ld not aligned with %ld\n",
438 __func__, __LINE__, id, offset, surf.base_align);
439 return -EINVAL;
440 }
441
442 offset += surf.layer_size * mslice;
443 if (offset > radeon_bo_size(track->cb_color_bo[id])) {
d2609875
JG		 444 /* old ddx are broken they allocate bo with w*h*bpp but
445 * program slice with ALIGN(h, 8), catch this and patch
446 * command stream.
447 */
448 if (!surf.mode) {
449 volatile u32 *ib = p->ib.ptr;
450 unsigned long tmp, nby, bsize, size, min = 0;
451
452 /* find the height the ddx wants */
453 if (surf.nby > 8) {
454 min = surf.nby - 8;
455 }
456 bsize = radeon_bo_size(track->cb_color_bo[id]);
457 tmp = track->cb_color_bo_offset[id] << 8;
458 for (nby = surf.nby; nby > min; nby--) {
459 size = nby * surf.nbx * surf.bpe * surf.nsamples;
460 if ((tmp + size * mslice) <= bsize) {
461 break;
462 }
463 }
464 if (nby > min) {
465 surf.nby = nby;
466 slice = ((nby * surf.nbx) / 64) - 1;
467 if (!evergreen_surface_check(p, &surf, "cb")) {
468 /* check if this one works */
469 tmp += surf.layer_size * mslice;
470 if (tmp <= bsize) {
471 ib[track->cb_color_slice_idx[id]] = slice;
472 goto old_ddx_ok;
473 }
474 }
475 }
476 }
285484e2
JG		 477 dev_warn(p->dev, "%s:%d cb[%d] bo too small (layer size %d, "
478 "offset %d, max layer %d, bo size %ld, slice %d)\n",
479 __func__, __LINE__, id, surf.layer_size,
480 track->cb_color_bo_offset[id] << 8, mslice,
481 radeon_bo_size(track->cb_color_bo[id]), slice);
482 dev_warn(p->dev, "%s:%d problematic surf: (%d %d) (%d %d %d %d %d %d %d)\n",
483 __func__, __LINE__, surf.nbx, surf.nby,
484 surf.mode, surf.bpe, surf.nsamples,
485 surf.bankw, surf.bankh,
486 surf.tsplit, surf.mtilea);
487 return -EINVAL;
488 }
d2609875 489old_ddx_ok:
285484e2
JG		 490
491 return 0;
492}
493
88f50c80
JG		 494static int evergreen_cs_track_validate_htile(struct radeon_cs_parser *p,
495 unsigned nbx, unsigned nby)
496{
497 struct evergreen_cs_track *track = p->track;
498 unsigned long size;
499
500 if (track->htile_bo == NULL) {
501 dev_warn(p->dev, "%s:%d htile enabled without htile surface 0x%08x\n",
502 __func__, __LINE__, track->db_z_info);
503 return -EINVAL;
504 }
505
506 if (G_028ABC_LINEAR(track->htile_surface)) {
507 /* pitch must be 16 htiles aligned == 16 * 8 pixel aligned */
508 nbx = round_up(nbx, 16 * 8);
509 /* height is npipes htiles aligned == npipes * 8 pixel aligned */
510 nby = round_up(nby, track->npipes * 8);
511 } else {
4ac0533a
JG		 512 /* always assume 8x8 htile */
513 /* align is htile align * 8, htile align vary according to
514 * number of pipe and tile width and nby
515 */
88f50c80
JG		 516 switch (track->npipes) {
517 case 8:
4ac0533a 518 /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/
88f50c80
JG		 519 nbx = round_up(nbx, 64 * 8);
520 nby = round_up(nby, 64 * 8);
521 break;
522 case 4:
4ac0533a 523 /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/
88f50c80
JG		 524 nbx = round_up(nbx, 64 * 8);
525 nby = round_up(nby, 32 * 8);
526 break;
527 case 2:
4ac0533a 528 /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/
88f50c80
JG		 529 nbx = round_up(nbx, 32 * 8);
530 nby = round_up(nby, 32 * 8);
531 break;
532 case 1:
4ac0533a 533 /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/
88f50c80
JG		 534 nbx = round_up(nbx, 32 * 8);
535 nby = round_up(nby, 16 * 8);
536 break;
537 default:
538 dev_warn(p->dev, "%s:%d invalid num pipes %d\n",
539 __func__, __LINE__, track->npipes);
540 return -EINVAL;
541 }
542 }
543 /* compute number of htile */
4ac0533a
JG		 544 nbx = nbx >> 3;
545 nby = nby >> 3;
546 /* size must be aligned on npipes * 2K boundary */
547 size = roundup(nbx * nby * 4, track->npipes * (2 << 10));
88f50c80
JG		 548 size += track->htile_offset;
549
550 if (size > radeon_bo_size(track->htile_bo)) {
551 dev_warn(p->dev, "%s:%d htile surface too small %ld for %ld (%d %d)\n",
552 __func__, __LINE__, radeon_bo_size(track->htile_bo),
553 size, nbx, nby);
554 return -EINVAL;
555 }
556 return 0;
557}
558
285484e2
JG		 559static int evergreen_cs_track_validate_stencil(struct radeon_cs_parser *p)
560{
561 struct evergreen_cs_track *track = p->track;
562 struct eg_surface surf;
563 unsigned pitch, slice, mslice;
564 unsigned long offset;
565 int r;
566
567 mslice = G_028008_SLICE_MAX(track->db_depth_view) + 1;
568 pitch = G_028058_PITCH_TILE_MAX(track->db_depth_size);
569 slice = track->db_depth_slice;
570 surf.nbx = (pitch + 1) * 8;
571 surf.nby = ((slice + 1) * 64) / surf.nbx;
572 surf.mode = G_028040_ARRAY_MODE(track->db_z_info);
573 surf.format = G_028044_FORMAT(track->db_s_info);
574 surf.tsplit = G_028044_TILE_SPLIT(track->db_s_info);
575 surf.nbanks = G_028040_NUM_BANKS(track->db_z_info);
576 surf.bankw = G_028040_BANK_WIDTH(track->db_z_info);
577 surf.bankh = G_028040_BANK_HEIGHT(track->db_z_info);
578 surf.mtilea = G_028040_MACRO_TILE_ASPECT(track->db_z_info);
579 surf.nsamples = 1;
580
581 if (surf.format != 1) {
582 dev_warn(p->dev, "%s:%d stencil invalid format %d\n",
583 __func__, __LINE__, surf.format);
584 return -EINVAL;
585 }
586 /* replace by color format so we can use same code */
587 surf.format = V_028C70_COLOR_8;
588
589 r = evergreen_surface_value_conv_check(p, &surf, "stencil");
590 if (r) {
591 return r;
592 }
593
594 r = evergreen_surface_check(p, &surf, NULL);
595 if (r) {
596 /* old userspace doesn't compute proper depth/stencil alignment
597 * check that alignment against a bigger byte per elements and
598 * only report if that alignment is wrong too.
599 */
600 surf.format = V_028C70_COLOR_8_8_8_8;
601 r = evergreen_surface_check(p, &surf, "stencil");
602 if (r) {
603 dev_warn(p->dev, "%s:%d stencil invalid (0x%08x 0x%08x 0x%08x 0x%08x)\n",
604 __func__, __LINE__, track->db_depth_size,
605 track->db_depth_slice, track->db_s_info, track->db_z_info);
606 }
607 return r;
608 }
609
610 offset = track->db_s_read_offset << 8;
611 if (offset & (surf.base_align - 1)) {
612 dev_warn(p->dev, "%s:%d stencil read bo base %ld not aligned with %ld\n",
613 __func__, __LINE__, offset, surf.base_align);
614 return -EINVAL;
615 }
616 offset += surf.layer_size * mslice;
617 if (offset > radeon_bo_size(track->db_s_read_bo)) {
618 dev_warn(p->dev, "%s:%d stencil read bo too small (layer size %d, "
619 "offset %ld, max layer %d, bo size %ld)\n",
620 __func__, __LINE__, surf.layer_size,
621 (unsigned long)track->db_s_read_offset << 8, mslice,
622 radeon_bo_size(track->db_s_read_bo));
623 dev_warn(p->dev, "%s:%d stencil invalid (0x%08x 0x%08x 0x%08x 0x%08x)\n",
624 __func__, __LINE__, track->db_depth_size,
625 track->db_depth_slice, track->db_s_info, track->db_z_info);
626 return -EINVAL;
627 }
628
629 offset = track->db_s_write_offset << 8;
630 if (offset & (surf.base_align - 1)) {
631 dev_warn(p->dev, "%s:%d stencil write bo base %ld not aligned with %ld\n",
632 __func__, __LINE__, offset, surf.base_align);
633 return -EINVAL;
634 }
635 offset += surf.layer_size * mslice;
636 if (offset > radeon_bo_size(track->db_s_write_bo)) {
637 dev_warn(p->dev, "%s:%d stencil write bo too small (layer size %d, "
638 "offset %ld, max layer %d, bo size %ld)\n",
639 __func__, __LINE__, surf.layer_size,
640 (unsigned long)track->db_s_write_offset << 8, mslice,
641 radeon_bo_size(track->db_s_write_bo));
642 return -EINVAL;
643 }
644
88f50c80
JG		 645 /* hyperz */
646 if (G_028040_TILE_SURFACE_ENABLE(track->db_z_info)) {
647 r = evergreen_cs_track_validate_htile(p, surf.nbx, surf.nby);
648 if (r) {
649 return r;
650 }
651 }
652
285484e2
JG		 653 return 0;
654}
655
656static int evergreen_cs_track_validate_depth(struct radeon_cs_parser *p)
657{
658 struct evergreen_cs_track *track = p->track;
659 struct eg_surface surf;
660 unsigned pitch, slice, mslice;
661 unsigned long offset;
662 int r;
663
664 mslice = G_028008_SLICE_MAX(track->db_depth_view) + 1;
665 pitch = G_028058_PITCH_TILE_MAX(track->db_depth_size);
666 slice = track->db_depth_slice;
667 surf.nbx = (pitch + 1) * 8;
668 surf.nby = ((slice + 1) * 64) / surf.nbx;
669 surf.mode = G_028040_ARRAY_MODE(track->db_z_info);
670 surf.format = G_028040_FORMAT(track->db_z_info);
671 surf.tsplit = G_028040_TILE_SPLIT(track->db_z_info);
672 surf.nbanks = G_028040_NUM_BANKS(track->db_z_info);
673 surf.bankw = G_028040_BANK_WIDTH(track->db_z_info);
674 surf.bankh = G_028040_BANK_HEIGHT(track->db_z_info);
675 surf.mtilea = G_028040_MACRO_TILE_ASPECT(track->db_z_info);
676 surf.nsamples = 1;
677
678 switch (surf.format) {
679 case V_028040_Z_16:
680 surf.format = V_028C70_COLOR_16;
681 break;
682 case V_028040_Z_24:
683 case V_028040_Z_32_FLOAT:
684 surf.format = V_028C70_COLOR_8_8_8_8;
685 break;
686 default:
687 dev_warn(p->dev, "%s:%d depth invalid format %d\n",
688 __func__, __LINE__, surf.format);
689 return -EINVAL;
690 }
691
692 r = evergreen_surface_value_conv_check(p, &surf, "depth");
693 if (r) {
694 dev_warn(p->dev, "%s:%d depth invalid (0x%08x 0x%08x 0x%08x)\n",
695 __func__, __LINE__, track->db_depth_size,
696 track->db_depth_slice, track->db_z_info);
697 return r;
698 }
699
700 r = evergreen_surface_check(p, &surf, "depth");
701 if (r) {
702 dev_warn(p->dev, "%s:%d depth invalid (0x%08x 0x%08x 0x%08x)\n",
703 __func__, __LINE__, track->db_depth_size,
704 track->db_depth_slice, track->db_z_info);
705 return r;
706 }
707
708 offset = track->db_z_read_offset << 8;
709 if (offset & (surf.base_align - 1)) {
710 dev_warn(p->dev, "%s:%d stencil read bo base %ld not aligned with %ld\n",
711 __func__, __LINE__, offset, surf.base_align);
712 return -EINVAL;
713 }
714 offset += surf.layer_size * mslice;
715 if (offset > radeon_bo_size(track->db_z_read_bo)) {
716 dev_warn(p->dev, "%s:%d depth read bo too small (layer size %d, "
717 "offset %ld, max layer %d, bo size %ld)\n",
718 __func__, __LINE__, surf.layer_size,
719 (unsigned long)track->db_z_read_offset << 8, mslice,
720 radeon_bo_size(track->db_z_read_bo));
721 return -EINVAL;
722 }
723
724 offset = track->db_z_write_offset << 8;
725 if (offset & (surf.base_align - 1)) {
726 dev_warn(p->dev, "%s:%d stencil write bo base %ld not aligned with %ld\n",
727 __func__, __LINE__, offset, surf.base_align);
728 return -EINVAL;
729 }
730 offset += surf.layer_size * mslice;
731 if (offset > radeon_bo_size(track->db_z_write_bo)) {
732 dev_warn(p->dev, "%s:%d depth write bo too small (layer size %d, "
733 "offset %ld, max layer %d, bo size %ld)\n",
734 __func__, __LINE__, surf.layer_size,
735 (unsigned long)track->db_z_write_offset << 8, mslice,
736 radeon_bo_size(track->db_z_write_bo));
737 return -EINVAL;
738 }
739
88f50c80
JG		 740 /* hyperz */
741 if (G_028040_TILE_SURFACE_ENABLE(track->db_z_info)) {
742 r = evergreen_cs_track_validate_htile(p, surf.nbx, surf.nby);
743 if (r) {
744 return r;
745 }
746 }
747
285484e2
JG		 748 return 0;
749}
750
751static int evergreen_cs_track_validate_texture(struct radeon_cs_parser *p,
752 struct radeon_bo *texture,
753 struct radeon_bo *mipmap,
754 unsigned idx)
755{
756 struct eg_surface surf;
757 unsigned long toffset, moffset;
758 unsigned dim, llevel, mslice, width, height, depth, i;
42b923b5 759 u32 texdw[8];
285484e2
JG		 760 int r;
761
762 texdw[0] = radeon_get_ib_value(p, idx + 0);
763 texdw[1] = radeon_get_ib_value(p, idx + 1);
764 texdw[2] = radeon_get_ib_value(p, idx + 2);
765 texdw[3] = radeon_get_ib_value(p, idx + 3);
766 texdw[4] = radeon_get_ib_value(p, idx + 4);
767 texdw[5] = radeon_get_ib_value(p, idx + 5);
768 texdw[6] = radeon_get_ib_value(p, idx + 6);
769 texdw[7] = radeon_get_ib_value(p, idx + 7);
770 dim = G_030000_DIM(texdw[0]);
771 llevel = G_030014_LAST_LEVEL(texdw[5]);
772 mslice = G_030014_LAST_ARRAY(texdw[5]) + 1;
773 width = G_030000_TEX_WIDTH(texdw[0]) + 1;
774 height = G_030004_TEX_HEIGHT(texdw[1]) + 1;
775 depth = G_030004_TEX_DEPTH(texdw[1]) + 1;
776 surf.format = G_03001C_DATA_FORMAT(texdw[7]);
777 surf.nbx = (G_030000_PITCH(texdw[0]) + 1) * 8;
778 surf.nbx = r600_fmt_get_nblocksx(surf.format, surf.nbx);
779 surf.nby = r600_fmt_get_nblocksy(surf.format, height);
780 surf.mode = G_030004_ARRAY_MODE(texdw[1]);
781 surf.tsplit = G_030018_TILE_SPLIT(texdw[6]);
782 surf.nbanks = G_03001C_NUM_BANKS(texdw[7]);
783 surf.bankw = G_03001C_BANK_WIDTH(texdw[7]);
784 surf.bankh = G_03001C_BANK_HEIGHT(texdw[7]);
785 surf.mtilea = G_03001C_MACRO_TILE_ASPECT(texdw[7]);
786 surf.nsamples = 1;
787 toffset = texdw[2] << 8;
788 moffset = texdw[3] << 8;
789
790 if (!r600_fmt_is_valid_texture(surf.format, p->family)) {
791 dev_warn(p->dev, "%s:%d texture invalid format %d\n",
792 __func__, __LINE__, surf.format);
793 return -EINVAL;
794 }
795 switch (dim) {
796 case V_030000_SQ_TEX_DIM_1D:
797 case V_030000_SQ_TEX_DIM_2D:
798 case V_030000_SQ_TEX_DIM_CUBEMAP:
799 case V_030000_SQ_TEX_DIM_1D_ARRAY:
800 case V_030000_SQ_TEX_DIM_2D_ARRAY:
801 depth = 1;
b51ad12a
MO		 802 break;
803 case V_030000_SQ_TEX_DIM_2D_MSAA:
804 case V_030000_SQ_TEX_DIM_2D_ARRAY_MSAA:
805 surf.nsamples = 1 << llevel;
806 llevel = 0;
807 depth = 1;
808 break;
285484e2
JG		 809 case V_030000_SQ_TEX_DIM_3D:
810 break;
811 default:
812 dev_warn(p->dev, "%s:%d texture invalid dimension %d\n",
813 __func__, __LINE__, dim);
814 return -EINVAL;
815 }
816
817 r = evergreen_surface_value_conv_check(p, &surf, "texture");
818 if (r) {
819 return r;
820 }
821
822 /* align height */
823 evergreen_surface_check(p, &surf, NULL);
824 surf.nby = ALIGN(surf.nby, surf.halign);
825
826 r = evergreen_surface_check(p, &surf, "texture");
827 if (r) {
828 dev_warn(p->dev, "%s:%d texture invalid 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
829 __func__, __LINE__, texdw[0], texdw[1], texdw[4],
830 texdw[5], texdw[6], texdw[7]);
831 return r;
832 }
833
834 /* check texture size */
835 if (toffset & (surf.base_align - 1)) {
836 dev_warn(p->dev, "%s:%d texture bo base %ld not aligned with %ld\n",
837 __func__, __LINE__, toffset, surf.base_align);
838 return -EINVAL;
839 }
840 if (moffset & (surf.base_align - 1)) {
841 dev_warn(p->dev, "%s:%d mipmap bo base %ld not aligned with %ld\n",
842 __func__, __LINE__, moffset, surf.base_align);
843 return -EINVAL;
844 }
845 if (dim == SQ_TEX_DIM_3D) {
846 toffset += surf.layer_size * depth;
847 } else {
848 toffset += surf.layer_size * mslice;
849 }
850 if (toffset > radeon_bo_size(texture)) {
851 dev_warn(p->dev, "%s:%d texture bo too small (layer size %d, "
852 "offset %ld, max layer %d, depth %d, bo size %ld) (%d %d)\n",
853 __func__, __LINE__, surf.layer_size,
854 (unsigned long)texdw[2] << 8, mslice,
855 depth, radeon_bo_size(texture),
856 surf.nbx, surf.nby);
857 return -EINVAL;
858 }
859
61051afd
MO		 860 if (!mipmap) {
861 if (llevel) {
862 dev_warn(p->dev, "%s:%i got NULL MIP_ADDRESS relocation\n",
863 __func__, __LINE__);
864 return -EINVAL;
865 } else {
866 return 0; /* everything's ok */
867 }
868 }
869
285484e2
JG		 870 /* check mipmap size */
871 for (i = 1; i <= llevel; i++) {
872 unsigned w, h, d;
873
874 w = r600_mip_minify(width, i);
875 h = r600_mip_minify(height, i);
876 d = r600_mip_minify(depth, i);
877 surf.nbx = r600_fmt_get_nblocksx(surf.format, w);
878 surf.nby = r600_fmt_get_nblocksy(surf.format, h);
879
880 switch (surf.mode) {
881 case ARRAY_2D_TILED_THIN1:
882 if (surf.nbx < surf.palign || surf.nby < surf.halign) {
883 surf.mode = ARRAY_1D_TILED_THIN1;
884 }
885 /* recompute alignment */
886 evergreen_surface_check(p, &surf, NULL);
887 break;
888 case ARRAY_LINEAR_GENERAL:
889 case ARRAY_LINEAR_ALIGNED:
890 case ARRAY_1D_TILED_THIN1:
891 break;
892 default:
893 dev_warn(p->dev, "%s:%d invalid array mode %d\n",
894 __func__, __LINE__, surf.mode);
895 return -EINVAL;
896 }
897 surf.nbx = ALIGN(surf.nbx, surf.palign);
898 surf.nby = ALIGN(surf.nby, surf.halign);
899
900 r = evergreen_surface_check(p, &surf, "mipmap");
901 if (r) {
902 return r;
903 }
904
905 if (dim == SQ_TEX_DIM_3D) {
906 moffset += surf.layer_size * d;
907 } else {
908 moffset += surf.layer_size * mslice;
909 }
910 if (moffset > radeon_bo_size(mipmap)) {
911 dev_warn(p->dev, "%s:%d mipmap [%d] bo too small (layer size %d, "
912 "offset %ld, coffset %ld, max layer %d, depth %d, "
913 "bo size %ld) level0 (%d %d %d)\n",
914 __func__, __LINE__, i, surf.layer_size,
915 (unsigned long)texdw[3] << 8, moffset, mslice,
916 d, radeon_bo_size(mipmap),
917 width, height, depth);
918 dev_warn(p->dev, "%s:%d problematic surf: (%d %d) (%d %d %d %d %d %d %d)\n",
919 __func__, __LINE__, surf.nbx, surf.nby,
920 surf.mode, surf.bpe, surf.nsamples,
921 surf.bankw, surf.bankh,
922 surf.tsplit, surf.mtilea);
923 return -EINVAL;
924 }
925 }
926
927 return 0;
928}
929
cb5fcbd5
AD		 930static int evergreen_cs_track_check(struct radeon_cs_parser *p)
931{
932 struct evergreen_cs_track *track = p->track;
7e9fa5f6 933 unsigned tmp, i;
285484e2 934 int r;
7e9fa5f6 935 unsigned buffer_mask = 0;
cb5fcbd5 936
dd220a00 937 /* check streamout */
30838578 938 if (track->streamout_dirty && track->vgt_strmout_config) {
7e9fa5f6
MO		 939 for (i = 0; i < 4; i++) {
940 if (track->vgt_strmout_config & (1 << i)) {
941 buffer_mask |= (track->vgt_strmout_buffer_config >> (i * 4)) & 0xf;
942 }
943 }
944
945 for (i = 0; i < 4; i++) {
946 if (buffer_mask & (1 << i)) {
947 if (track->vgt_strmout_bo[i]) {
948 u64 offset = (u64)track->vgt_strmout_bo_offset[i] +
949 (u64)track->vgt_strmout_size[i];
950 if (offset > radeon_bo_size(track->vgt_strmout_bo[i])) {
951 DRM_ERROR("streamout %d bo too small: 0x%llx, 0x%lx\n",
952 i, offset,
953 radeon_bo_size(track->vgt_strmout_bo[i]));
dd220a00
MO		 954 return -EINVAL;
955 }
7e9fa5f6
MO		 956 } else {
957 dev_warn(p->dev, "No buffer for streamout %d\n", i);
958 return -EINVAL;
dd220a00
MO		 959 }
960 }
961 }
30838578 962 track->streamout_dirty = false;
cb5fcbd5
AD		 963 }
964
779923bc
MO		 965 if (track->sx_misc_kill_all_prims)
966 return 0;
967
285484e2
JG		 968 /* check that we have a cb for each enabled target
969 */
30838578
MO		 970 if (track->cb_dirty) {
971 tmp = track->cb_target_mask;
972 for (i = 0; i < 8; i++) {
973 if ((tmp >> (i * 4)) & 0xF) {
974 /* at least one component is enabled */
975 if (track->cb_color_bo[i] == NULL) {
976 dev_warn(p->dev, "%s:%d mask 0x%08X | 0x%08X no cb for %d\n",
977 __func__, __LINE__, track->cb_target_mask, track->cb_shader_mask, i);
978 return -EINVAL;
979 }
980 /* check cb */
981 r = evergreen_cs_track_validate_cb(p, i);
982 if (r) {
983 return r;
984 }
285484e2
JG		 985 }
986 }
30838578 987 track->cb_dirty = false;
285484e2
JG		 988 }
989
30838578
MO		 990 if (track->db_dirty) {
991 /* Check stencil buffer */
0f457e48
MO		 992 if (G_028044_FORMAT(track->db_s_info) != V_028044_STENCIL_INVALID &&
993 G_028800_STENCIL_ENABLE(track->db_depth_control)) {
30838578
MO		 994 r = evergreen_cs_track_validate_stencil(p);
995 if (r)
996 return r;
997 }
998 /* Check depth buffer */
0f457e48
MO		 999 if (G_028040_FORMAT(track->db_z_info) != V_028040_Z_INVALID &&
1000 G_028800_Z_ENABLE(track->db_depth_control)) {
30838578
MO		 1001 r = evergreen_cs_track_validate_depth(p);
1002 if (r)
1003 return r;
1004 }
1005 track->db_dirty = false;
285484e2
JG		 1006 }
1007
cb5fcbd5
AD		 1008 return 0;
1009}
1010
cb5fcbd5
AD		 1011/**
1012 * evergreen_cs_packet_next_reloc() - parse next packet which should be reloc packet3
1013 * @parser: parser structure holding parsing context.
1014 * @data: pointer to relocation data
1015 * @offset_start: starting offset
1016 * @offset_mask: offset mask (to align start offset on)
1017 * @reloc: reloc informations
1018 *
1019 * Check next packet is relocation packet3, do bo validation and compute
1020 * GPU offset using the provided start.
1021 **/
1022static int evergreen_cs_packet_next_reloc(struct radeon_cs_parser *p,
1023 struct radeon_cs_reloc **cs_reloc)
1024{
1025 struct radeon_cs_chunk *relocs_chunk;
1026 struct radeon_cs_packet p3reloc;
1027 unsigned idx;
1028 int r;
1029
1030 if (p->chunk_relocs_idx == -1) {
1031 DRM_ERROR("No relocation chunk !\n");
1032 return -EINVAL;
1033 }
1034 *cs_reloc = NULL;
1035 relocs_chunk = &p->chunks[p->chunk_relocs_idx];
c38f34b5 1036 r = radeon_cs_packet_parse(p, &p3reloc, p->idx);
cb5fcbd5
AD		 1037 if (r) {
1038 return r;
1039 }
1040 p->idx += p3reloc.count + 2;
1041 if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
1042 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
1043 p3reloc.idx);
1044 return -EINVAL;
1045 }
1046 idx = radeon_get_ib_value(p, p3reloc.idx + 1);
1047 if (idx >= relocs_chunk->length_dw) {
1048 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
1049 idx, relocs_chunk->length_dw);
1050 return -EINVAL;
1051 }
1052 /* FIXME: we assume reloc size is 4 dwords */
1053 *cs_reloc = p->relocs_ptr[(idx / 4)];
1054 return 0;
1055}
1056
cb5fcbd5 1057/**
40592a17 1058 * evergreen_cs_packet_parse_vline() - parse userspace VLINE packet
cb5fcbd5
AD		 1059 * @parser: parser structure holding parsing context.
1060 *
40592a17
IH		 1061 * This is an Evergreen(+)-specific function for parsing VLINE packets.
1062 * Real work is done by r600_cs_common_vline_parse function.
1063 * Here we just set up ASIC-specific register table and call
1064 * the common implementation function.
cb5fcbd5
AD		 1065 */
1066static int evergreen_cs_packet_parse_vline(struct radeon_cs_parser *p)
1067{
cb5fcbd5 1068
40592a17
IH		 1069 static uint32_t vline_start_end[6] = {
1070 EVERGREEN_VLINE_START_END + EVERGREEN_CRTC0_REGISTER_OFFSET,
1071 EVERGREEN_VLINE_START_END + EVERGREEN_CRTC1_REGISTER_OFFSET,
1072 EVERGREEN_VLINE_START_END + EVERGREEN_CRTC2_REGISTER_OFFSET,
1073 EVERGREEN_VLINE_START_END + EVERGREEN_CRTC3_REGISTER_OFFSET,
1074 EVERGREEN_VLINE_START_END + EVERGREEN_CRTC4_REGISTER_OFFSET,
1075 EVERGREEN_VLINE_START_END + EVERGREEN_CRTC5_REGISTER_OFFSET
1076 };
1077 static uint32_t vline_status[6] = {
1078 EVERGREEN_VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET,
1079 EVERGREEN_VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET,
1080 EVERGREEN_VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET,
1081 EVERGREEN_VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET,
1082 EVERGREEN_VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET,
1083 EVERGREEN_VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET
1084 };
1085
1086 return r600_cs_common_vline_parse(p, vline_start_end, vline_status);
cb5fcbd5
AD		 1087}
1088
1089static int evergreen_packet0_check(struct radeon_cs_parser *p,
1090 struct radeon_cs_packet *pkt,
1091 unsigned idx, unsigned reg)
1092{
1093 int r;
1094
1095 switch (reg) {
1096 case EVERGREEN_VLINE_START_END:
1097 r = evergreen_cs_packet_parse_vline(p);
1098 if (r) {
1099 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1100 idx, reg);
1101 return r;
1102 }
1103 break;
1104 default:
1105 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1106 reg, idx);
1107 return -EINVAL;
1108 }
1109 return 0;
1110}
1111
1112static int evergreen_cs_parse_packet0(struct radeon_cs_parser *p,
1113 struct radeon_cs_packet *pkt)
1114{
1115 unsigned reg, i;
1116 unsigned idx;
1117 int r;
1118
1119 idx = pkt->idx + 1;
1120 reg = pkt->reg;
1121 for (i = 0; i <= pkt->count; i++, idx++, reg += 4) {
1122 r = evergreen_packet0_check(p, pkt, idx, reg);
1123 if (r) {
1124 return r;
1125 }
1126 }
1127 return 0;
1128}
1129
1130/**
1131 * evergreen_cs_check_reg() - check if register is authorized or not
1132 * @parser: parser structure holding parsing context
1133 * @reg: register we are testing
1134 * @idx: index into the cs buffer
1135 *
1136 * This function will test against evergreen_reg_safe_bm and return 0
1137 * if register is safe. If register is not flag as safe this function
1138 * will test it against a list of register needind special handling.
1139 */
488479eb 1140static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
cb5fcbd5
AD		 1141{
1142 struct evergreen_cs_track *track = (struct evergreen_cs_track *)p->track;
1143 struct radeon_cs_reloc *reloc;
c175ca9a 1144 u32 last_reg;
cb5fcbd5
AD		 1145 u32 m, i, tmp, *ib;
1146 int r;
1147
c175ca9a
AD		 1148 if (p->rdev->family >= CHIP_CAYMAN)
1149 last_reg = ARRAY_SIZE(cayman_reg_safe_bm);
1150 else
1151 last_reg = ARRAY_SIZE(evergreen_reg_safe_bm);
1152
cb5fcbd5 1153 i = (reg >> 7);
88498839 1154 if (i >= last_reg) {
cb5fcbd5
AD		 1155 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
1156 return -EINVAL;
1157 }
1158 m = 1 << ((reg >> 2) & 31);
c175ca9a
AD		 1159 if (p->rdev->family >= CHIP_CAYMAN) {
1160 if (!(cayman_reg_safe_bm[i] & m))
1161 return 0;
1162 } else {
1163 if (!(evergreen_reg_safe_bm[i] & m))
1164 return 0;
1165 }
f2e39221 1166 ib = p->ib.ptr;
cb5fcbd5 1167 switch (reg) {
25985edc 1168 /* force following reg to 0 in an attempt to disable out buffer
cb5fcbd5
AD		 1169 * which will need us to better understand how it works to perform
1170 * security check on it (Jerome)
1171 */
1172 case SQ_ESGS_RING_SIZE:
1173 case SQ_GSVS_RING_SIZE:
1174 case SQ_ESTMP_RING_SIZE:
1175 case SQ_GSTMP_RING_SIZE:
1176 case SQ_HSTMP_RING_SIZE:
1177 case SQ_LSTMP_RING_SIZE:
1178 case SQ_PSTMP_RING_SIZE:
1179 case SQ_VSTMP_RING_SIZE:
1180 case SQ_ESGS_RING_ITEMSIZE:
1181 case SQ_ESTMP_RING_ITEMSIZE:
1182 case SQ_GSTMP_RING_ITEMSIZE:
1183 case SQ_GSVS_RING_ITEMSIZE:
1184 case SQ_GS_VERT_ITEMSIZE:
1185 case SQ_GS_VERT_ITEMSIZE_1:
1186 case SQ_GS_VERT_ITEMSIZE_2:
1187 case SQ_GS_VERT_ITEMSIZE_3:
1188 case SQ_GSVS_RING_OFFSET_1:
1189 case SQ_GSVS_RING_OFFSET_2:
1190 case SQ_GSVS_RING_OFFSET_3:
1191 case SQ_HSTMP_RING_ITEMSIZE:
1192 case SQ_LSTMP_RING_ITEMSIZE:
1193 case SQ_PSTMP_RING_ITEMSIZE:
1194 case SQ_VSTMP_RING_ITEMSIZE:
1195 case VGT_TF_RING_SIZE:
1196 /* get value to populate the IB don't remove */
8aa75009
AD		 1197 /*tmp =radeon_get_ib_value(p, idx);
1198 ib[idx] = 0;*/
1199 break;
1200 case SQ_ESGS_RING_BASE:
1201 case SQ_GSVS_RING_BASE:
1202 case SQ_ESTMP_RING_BASE:
1203 case SQ_GSTMP_RING_BASE:
1204 case SQ_HSTMP_RING_BASE:
1205 case SQ_LSTMP_RING_BASE:
1206 case SQ_PSTMP_RING_BASE:
1207 case SQ_VSTMP_RING_BASE:
1208 r = evergreen_cs_packet_next_reloc(p, &reloc);
1209 if (r) {
1210 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1211 "0x%04X\n", reg);
1212 return -EINVAL;
1213 }
1214 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
cb5fcbd5
AD		 1215 break;
1216 case DB_DEPTH_CONTROL:
1217 track->db_depth_control = radeon_get_ib_value(p, idx);
30838578 1218 track->db_dirty = true;
cb5fcbd5 1219 break;
c175ca9a
AD		 1220 case CAYMAN_DB_EQAA:
1221 if (p->rdev->family < CHIP_CAYMAN) {
1222 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1223 "0x%04X\n", reg);
1224 return -EINVAL;
1225 }
1226 break;
1227 case CAYMAN_DB_DEPTH_INFO:
1228 if (p->rdev->family < CHIP_CAYMAN) {
1229 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1230 "0x%04X\n", reg);
1231 return -EINVAL;
1232 }
1233 break;
cb5fcbd5 1234 case DB_Z_INFO:
cb5fcbd5 1235 track->db_z_info = radeon_get_ib_value(p, idx);
721604a1 1236 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
e70f224c
MO		 1237 r = evergreen_cs_packet_next_reloc(p, &reloc);
1238 if (r) {
1239 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1240 "0x%04X\n", reg);
1241 return -EINVAL;
1242 }
1243 ib[idx] &= ~Z_ARRAY_MODE(0xf);
1244 track->db_z_info &= ~Z_ARRAY_MODE(0xf);
f3a71df0
AD		 1245 ib[idx] |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
1246 track->db_z_info |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
e70f224c 1247 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
285484e2
JG		 1248 unsigned bankw, bankh, mtaspect, tile_split;
1249
1250 evergreen_tiling_fields(reloc->lobj.tiling_flags,
1251 &bankw, &bankh, &mtaspect,
1252 &tile_split);
f3a71df0 1253 ib[idx] |= DB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks));
285484e2
JG		 1254 ib[idx] |= DB_TILE_SPLIT(tile_split) |
1255 DB_BANK_WIDTH(bankw) |
1256 DB_BANK_HEIGHT(bankh) |
1257 DB_MACRO_TILE_ASPECT(mtaspect);
e70f224c 1258 }
cb5fcbd5 1259 }
30838578 1260 track->db_dirty = true;
cb5fcbd5
AD		 1261 break;
1262 case DB_STENCIL_INFO:
1263 track->db_s_info = radeon_get_ib_value(p, idx);
30838578 1264 track->db_dirty = true;
cb5fcbd5
AD		 1265 break;
1266 case DB_DEPTH_VIEW:
1267 track->db_depth_view = radeon_get_ib_value(p, idx);
30838578 1268 track->db_dirty = true;
cb5fcbd5
AD		 1269 break;
1270 case DB_DEPTH_SIZE:
1271 track->db_depth_size = radeon_get_ib_value(p, idx);
30838578 1272 track->db_dirty = true;
cb5fcbd5 1273 break;
285484e2
JG		 1274 case R_02805C_DB_DEPTH_SLICE:
1275 track->db_depth_slice = radeon_get_ib_value(p, idx);
30838578 1276 track->db_dirty = true;
285484e2 1277 break;
cb5fcbd5
AD		 1278 case DB_Z_READ_BASE:
1279 r = evergreen_cs_packet_next_reloc(p, &reloc);
1280 if (r) {
1281 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1282 "0x%04X\n", reg);
1283 return -EINVAL;
1284 }
1285 track->db_z_read_offset = radeon_get_ib_value(p, idx);
1286 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1287 track->db_z_read_bo = reloc->robj;
30838578 1288 track->db_dirty = true;
cb5fcbd5
AD		 1289 break;
1290 case DB_Z_WRITE_BASE:
1291 r = evergreen_cs_packet_next_reloc(p, &reloc);
1292 if (r) {
1293 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1294 "0x%04X\n", reg);
1295 return -EINVAL;
1296 }
1297 track->db_z_write_offset = radeon_get_ib_value(p, idx);
1298 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1299 track->db_z_write_bo = reloc->robj;
30838578 1300 track->db_dirty = true;
cb5fcbd5
AD		 1301 break;
1302 case DB_STENCIL_READ_BASE:
1303 r = evergreen_cs_packet_next_reloc(p, &reloc);
1304 if (r) {
1305 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1306 "0x%04X\n", reg);
1307 return -EINVAL;
1308 }
1309 track->db_s_read_offset = radeon_get_ib_value(p, idx);
1310 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1311 track->db_s_read_bo = reloc->robj;
30838578 1312 track->db_dirty = true;
cb5fcbd5
AD		 1313 break;
1314 case DB_STENCIL_WRITE_BASE:
1315 r = evergreen_cs_packet_next_reloc(p, &reloc);
1316 if (r) {
1317 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1318 "0x%04X\n", reg);
1319 return -EINVAL;
1320 }
1321 track->db_s_write_offset = radeon_get_ib_value(p, idx);
1322 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1323 track->db_s_write_bo = reloc->robj;
30838578 1324 track->db_dirty = true;
cb5fcbd5
AD		 1325 break;
1326 case VGT_STRMOUT_CONFIG:
1327 track->vgt_strmout_config = radeon_get_ib_value(p, idx);
30838578 1328 track->streamout_dirty = true;
cb5fcbd5
AD		 1329 break;
1330 case VGT_STRMOUT_BUFFER_CONFIG:
1331 track->vgt_strmout_buffer_config = radeon_get_ib_value(p, idx);
30838578 1332 track->streamout_dirty = true;
cb5fcbd5 1333 break;
dd220a00
MO		 1334 case VGT_STRMOUT_BUFFER_BASE_0:
1335 case VGT_STRMOUT_BUFFER_BASE_1:
1336 case VGT_STRMOUT_BUFFER_BASE_2:
1337 case VGT_STRMOUT_BUFFER_BASE_3:
1338 r = evergreen_cs_packet_next_reloc(p, &reloc);
1339 if (r) {
1340 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1341 "0x%04X\n", reg);
1342 return -EINVAL;
1343 }
1344 tmp = (reg - VGT_STRMOUT_BUFFER_BASE_0) / 16;
1345 track->vgt_strmout_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8;
1346 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1347 track->vgt_strmout_bo[tmp] = reloc->robj;
30838578 1348 track->streamout_dirty = true;
dd220a00
MO		 1349 break;
1350 case VGT_STRMOUT_BUFFER_SIZE_0:
1351 case VGT_STRMOUT_BUFFER_SIZE_1:
1352 case VGT_STRMOUT_BUFFER_SIZE_2:
1353 case VGT_STRMOUT_BUFFER_SIZE_3:
1354 tmp = (reg - VGT_STRMOUT_BUFFER_SIZE_0) / 16;
1355 /* size in register is DWs, convert to bytes */
1356 track->vgt_strmout_size[tmp] = radeon_get_ib_value(p, idx) * 4;
30838578 1357 track->streamout_dirty = true;
dd220a00
MO		 1358 break;
1359 case CP_COHER_BASE:
1360 r = evergreen_cs_packet_next_reloc(p, &reloc);
1361 if (r) {
1362 dev_warn(p->dev, "missing reloc for CP_COHER_BASE "
1363 "0x%04X\n", reg);
1364 return -EINVAL;
1365 }
1366 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
cb5fcbd5
AD		 1367 case CB_TARGET_MASK:
1368 track->cb_target_mask = radeon_get_ib_value(p, idx);
30838578 1369 track->cb_dirty = true;
cb5fcbd5
AD		 1370 break;
1371 case CB_SHADER_MASK:
1372 track->cb_shader_mask = radeon_get_ib_value(p, idx);
30838578 1373 track->cb_dirty = true;
cb5fcbd5
AD		 1374 break;
1375 case PA_SC_AA_CONFIG:
c175ca9a
AD		 1376 if (p->rdev->family >= CHIP_CAYMAN) {
1377 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1378 "0x%04X\n", reg);
1379 return -EINVAL;
1380 }
cb5fcbd5
AD		 1381 tmp = radeon_get_ib_value(p, idx) & MSAA_NUM_SAMPLES_MASK;
1382 track->nsamples = 1 << tmp;
1383 break;
c175ca9a
AD		 1384 case CAYMAN_PA_SC_AA_CONFIG:
1385 if (p->rdev->family < CHIP_CAYMAN) {
1386 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1387 "0x%04X\n", reg);
1388 return -EINVAL;
1389 }
1390 tmp = radeon_get_ib_value(p, idx) & CAYMAN_MSAA_NUM_SAMPLES_MASK;
1391 track->nsamples = 1 << tmp;
1392 break;
cb5fcbd5
AD		 1393 case CB_COLOR0_VIEW:
1394 case CB_COLOR1_VIEW:
1395 case CB_COLOR2_VIEW:
1396 case CB_COLOR3_VIEW:
1397 case CB_COLOR4_VIEW:
1398 case CB_COLOR5_VIEW:
1399 case CB_COLOR6_VIEW:
1400 case CB_COLOR7_VIEW:
1401 tmp = (reg - CB_COLOR0_VIEW) / 0x3c;
1402 track->cb_color_view[tmp] = radeon_get_ib_value(p, idx);
30838578 1403 track->cb_dirty = true;
cb5fcbd5
AD		 1404 break;
1405 case CB_COLOR8_VIEW:
1406 case CB_COLOR9_VIEW:
1407 case CB_COLOR10_VIEW:
1408 case CB_COLOR11_VIEW:
1409 tmp = ((reg - CB_COLOR8_VIEW) / 0x1c) + 8;
1410 track->cb_color_view[tmp] = radeon_get_ib_value(p, idx);
30838578 1411 track->cb_dirty = true;
cb5fcbd5
AD		 1412 break;
1413 case CB_COLOR0_INFO:
1414 case CB_COLOR1_INFO:
1415 case CB_COLOR2_INFO:
1416 case CB_COLOR3_INFO:
1417 case CB_COLOR4_INFO:
1418 case CB_COLOR5_INFO:
1419 case CB_COLOR6_INFO:
1420 case CB_COLOR7_INFO:
cb5fcbd5
AD		 1421 tmp = (reg - CB_COLOR0_INFO) / 0x3c;
1422 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
721604a1 1423 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
e70f224c
MO		 1424 r = evergreen_cs_packet_next_reloc(p, &reloc);
1425 if (r) {
1426 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1427 "0x%04X\n", reg);
1428 return -EINVAL;
1429 }
f3a71df0
AD		 1430 ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
1431 track->cb_color_info[tmp] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
cb5fcbd5 1432 }
30838578 1433 track->cb_dirty = true;
cb5fcbd5
AD		 1434 break;
1435 case CB_COLOR8_INFO:
1436 case CB_COLOR9_INFO:
1437 case CB_COLOR10_INFO:
1438 case CB_COLOR11_INFO:
cb5fcbd5
AD		 1439 tmp = ((reg - CB_COLOR8_INFO) / 0x1c) + 8;
1440 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
721604a1 1441 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
e70f224c
MO		 1442 r = evergreen_cs_packet_next_reloc(p, &reloc);
1443 if (r) {
1444 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1445 "0x%04X\n", reg);
1446 return -EINVAL;
1447 }
f3a71df0
AD		 1448 ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
1449 track->cb_color_info[tmp] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
cb5fcbd5 1450 }
30838578 1451 track->cb_dirty = true;
cb5fcbd5
AD		 1452 break;
1453 case CB_COLOR0_PITCH:
1454 case CB_COLOR1_PITCH:
1455 case CB_COLOR2_PITCH:
1456 case CB_COLOR3_PITCH:
1457 case CB_COLOR4_PITCH:
1458 case CB_COLOR5_PITCH:
1459 case CB_COLOR6_PITCH:
1460 case CB_COLOR7_PITCH:
1461 tmp = (reg - CB_COLOR0_PITCH) / 0x3c;
1462 track->cb_color_pitch[tmp] = radeon_get_ib_value(p, idx);
30838578 1463 track->cb_dirty = true;
cb5fcbd5
AD		 1464 break;
1465 case CB_COLOR8_PITCH:
1466 case CB_COLOR9_PITCH:
1467 case CB_COLOR10_PITCH:
1468 case CB_COLOR11_PITCH:
1469 tmp = ((reg - CB_COLOR8_PITCH) / 0x1c) + 8;
1470 track->cb_color_pitch[tmp] = radeon_get_ib_value(p, idx);
30838578 1471 track->cb_dirty = true;
cb5fcbd5
AD		 1472 break;
1473 case CB_COLOR0_SLICE:
1474 case CB_COLOR1_SLICE:
1475 case CB_COLOR2_SLICE:
1476 case CB_COLOR3_SLICE:
1477 case CB_COLOR4_SLICE:
1478 case CB_COLOR5_SLICE:
1479 case CB_COLOR6_SLICE:
1480 case CB_COLOR7_SLICE:
1481 tmp = (reg - CB_COLOR0_SLICE) / 0x3c;
1482 track->cb_color_slice[tmp] = radeon_get_ib_value(p, idx);
d2609875 1483 track->cb_color_slice_idx[tmp] = idx;
30838578 1484 track->cb_dirty = true;
cb5fcbd5
AD		 1485 break;
1486 case CB_COLOR8_SLICE:
1487 case CB_COLOR9_SLICE:
1488 case CB_COLOR10_SLICE:
1489 case CB_COLOR11_SLICE:
1490 tmp = ((reg - CB_COLOR8_SLICE) / 0x1c) + 8;
1491 track->cb_color_slice[tmp] = radeon_get_ib_value(p, idx);
d2609875 1492 track->cb_color_slice_idx[tmp] = idx;
30838578 1493 track->cb_dirty = true;
cb5fcbd5
AD		 1494 break;
1495 case CB_COLOR0_ATTRIB:
1496 case CB_COLOR1_ATTRIB:
1497 case CB_COLOR2_ATTRIB:
1498 case CB_COLOR3_ATTRIB:
1499 case CB_COLOR4_ATTRIB:
1500 case CB_COLOR5_ATTRIB:
1501 case CB_COLOR6_ATTRIB:
1502 case CB_COLOR7_ATTRIB:
285484e2
JG		 1503 r = evergreen_cs_packet_next_reloc(p, &reloc);
1504 if (r) {
1505 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1506 "0x%04X\n", reg);
1507 return -EINVAL;
1508 }
1509 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1510 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
1511 unsigned bankw, bankh, mtaspect, tile_split;
1512
1513 evergreen_tiling_fields(reloc->lobj.tiling_flags,
1514 &bankw, &bankh, &mtaspect,
1515 &tile_split);
1516 ib[idx] |= CB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks));
1517 ib[idx] |= CB_TILE_SPLIT(tile_split) |
1518 CB_BANK_WIDTH(bankw) |
1519 CB_BANK_HEIGHT(bankh) |
1520 CB_MACRO_TILE_ASPECT(mtaspect);
1521 }
1522 }
1523 tmp = ((reg - CB_COLOR0_ATTRIB) / 0x3c);
1524 track->cb_color_attrib[tmp] = ib[idx];
30838578 1525 track->cb_dirty = true;
285484e2 1526 break;
cb5fcbd5
AD		 1527 case CB_COLOR8_ATTRIB:
1528 case CB_COLOR9_ATTRIB:
1529 case CB_COLOR10_ATTRIB:
1530 case CB_COLOR11_ATTRIB:
f3a71df0
AD		 1531 r = evergreen_cs_packet_next_reloc(p, &reloc);
1532 if (r) {
1533 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1534 "0x%04X\n", reg);
1535 return -EINVAL;
1536 }
285484e2
JG		 1537 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1538 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
1539 unsigned bankw, bankh, mtaspect, tile_split;
1540
1541 evergreen_tiling_fields(reloc->lobj.tiling_flags,
1542 &bankw, &bankh, &mtaspect,
1543 &tile_split);
1544 ib[idx] |= CB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks));
1545 ib[idx] |= CB_TILE_SPLIT(tile_split) |
1546 CB_BANK_WIDTH(bankw) |
1547 CB_BANK_HEIGHT(bankh) |
1548 CB_MACRO_TILE_ASPECT(mtaspect);
1549 }
f3a71df0 1550 }
285484e2
JG		 1551 tmp = ((reg - CB_COLOR8_ATTRIB) / 0x1c) + 8;
1552 track->cb_color_attrib[tmp] = ib[idx];
30838578 1553 track->cb_dirty = true;
cb5fcbd5 1554 break;
cb5fcbd5
AD		 1555 case CB_COLOR0_FMASK:
1556 case CB_COLOR1_FMASK:
1557 case CB_COLOR2_FMASK:
1558 case CB_COLOR3_FMASK:
1559 case CB_COLOR4_FMASK:
1560 case CB_COLOR5_FMASK:
1561 case CB_COLOR6_FMASK:
1562 case CB_COLOR7_FMASK:
1563 tmp = (reg - CB_COLOR0_FMASK) / 0x3c;
1564 r = evergreen_cs_packet_next_reloc(p, &reloc);
1565 if (r) {
1566 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
1567 return -EINVAL;
1568 }
1569 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1570 track->cb_color_fmask_bo[tmp] = reloc->robj;
1571 break;
1572 case CB_COLOR0_CMASK:
1573 case CB_COLOR1_CMASK:
1574 case CB_COLOR2_CMASK:
1575 case CB_COLOR3_CMASK:
1576 case CB_COLOR4_CMASK:
1577 case CB_COLOR5_CMASK:
1578 case CB_COLOR6_CMASK:
1579 case CB_COLOR7_CMASK:
1580 tmp = (reg - CB_COLOR0_CMASK) / 0x3c;
1581 r = evergreen_cs_packet_next_reloc(p, &reloc);
1582 if (r) {
1583 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
1584 return -EINVAL;
1585 }
1586 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1587 track->cb_color_cmask_bo[tmp] = reloc->robj;
1588 break;
1589 case CB_COLOR0_FMASK_SLICE:
1590 case CB_COLOR1_FMASK_SLICE:
1591 case CB_COLOR2_FMASK_SLICE:
1592 case CB_COLOR3_FMASK_SLICE:
1593 case CB_COLOR4_FMASK_SLICE:
1594 case CB_COLOR5_FMASK_SLICE:
1595 case CB_COLOR6_FMASK_SLICE:
1596 case CB_COLOR7_FMASK_SLICE:
1597 tmp = (reg - CB_COLOR0_FMASK_SLICE) / 0x3c;
1598 track->cb_color_fmask_slice[tmp] = radeon_get_ib_value(p, idx);
1599 break;
1600 case CB_COLOR0_CMASK_SLICE:
1601 case CB_COLOR1_CMASK_SLICE:
1602 case CB_COLOR2_CMASK_SLICE:
1603 case CB_COLOR3_CMASK_SLICE:
1604 case CB_COLOR4_CMASK_SLICE:
1605 case CB_COLOR5_CMASK_SLICE:
1606 case CB_COLOR6_CMASK_SLICE:
1607 case CB_COLOR7_CMASK_SLICE:
1608 tmp = (reg - CB_COLOR0_CMASK_SLICE) / 0x3c;
1609 track->cb_color_cmask_slice[tmp] = radeon_get_ib_value(p, idx);
1610 break;
1611 case CB_COLOR0_BASE:
1612 case CB_COLOR1_BASE:
1613 case CB_COLOR2_BASE:
1614 case CB_COLOR3_BASE:
1615 case CB_COLOR4_BASE:
1616 case CB_COLOR5_BASE:
1617 case CB_COLOR6_BASE:
1618 case CB_COLOR7_BASE:
1619 r = evergreen_cs_packet_next_reloc(p, &reloc);
1620 if (r) {
1621 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1622 "0x%04X\n", reg);
1623 return -EINVAL;
1624 }
1625 tmp = (reg - CB_COLOR0_BASE) / 0x3c;
1626 track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx);
1627 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
cb5fcbd5 1628 track->cb_color_bo[tmp] = reloc->robj;
30838578 1629 track->cb_dirty = true;
cb5fcbd5
AD		 1630 break;
1631 case CB_COLOR8_BASE:
1632 case CB_COLOR9_BASE:
1633 case CB_COLOR10_BASE:
1634 case CB_COLOR11_BASE:
1635 r = evergreen_cs_packet_next_reloc(p, &reloc);
1636 if (r) {
1637 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1638 "0x%04X\n", reg);
1639 return -EINVAL;
1640 }
1641 tmp = ((reg - CB_COLOR8_BASE) / 0x1c) + 8;
1642 track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx);
1643 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
cb5fcbd5 1644 track->cb_color_bo[tmp] = reloc->robj;
30838578 1645 track->cb_dirty = true;
cb5fcbd5 1646 break;
88f50c80
JG		 1647 case DB_HTILE_DATA_BASE:
1648 r = evergreen_cs_packet_next_reloc(p, &reloc);
1649 if (r) {
1650 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1651 "0x%04X\n", reg);
1652 return -EINVAL;
1653 }
1654 track->htile_offset = radeon_get_ib_value(p, idx);
1655 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1656 track->htile_bo = reloc->robj;
1657 track->db_dirty = true;
1658 break;
1659 case DB_HTILE_SURFACE:
1660 /* 8x8 only */
1661 track->htile_surface = radeon_get_ib_value(p, idx);
4ac0533a
JG		 1662 /* force 8x8 htile width and height */
1663 ib[idx] |= 3;
88f50c80
JG		 1664 track->db_dirty = true;
1665 break;
cb5fcbd5
AD		 1666 case CB_IMMED0_BASE:
1667 case CB_IMMED1_BASE:
1668 case CB_IMMED2_BASE:
1669 case CB_IMMED3_BASE:
1670 case CB_IMMED4_BASE:
1671 case CB_IMMED5_BASE:
1672 case CB_IMMED6_BASE:
1673 case CB_IMMED7_BASE:
1674 case CB_IMMED8_BASE:
1675 case CB_IMMED9_BASE:
1676 case CB_IMMED10_BASE:
1677 case CB_IMMED11_BASE:
cb5fcbd5
AD		 1678 case SQ_PGM_START_FS:
1679 case SQ_PGM_START_ES:
1680 case SQ_PGM_START_VS:
1681 case SQ_PGM_START_GS:
1682 case SQ_PGM_START_PS:
1683 case SQ_PGM_START_HS:
1684 case SQ_PGM_START_LS:
cb5fcbd5
AD		 1685 case SQ_CONST_MEM_BASE:
1686 case SQ_ALU_CONST_CACHE_GS_0:
1687 case SQ_ALU_CONST_CACHE_GS_1:
1688 case SQ_ALU_CONST_CACHE_GS_2:
1689 case SQ_ALU_CONST_CACHE_GS_3:
1690 case SQ_ALU_CONST_CACHE_GS_4:
1691 case SQ_ALU_CONST_CACHE_GS_5:
1692 case SQ_ALU_CONST_CACHE_GS_6:
1693 case SQ_ALU_CONST_CACHE_GS_7:
1694 case SQ_ALU_CONST_CACHE_GS_8:
1695 case SQ_ALU_CONST_CACHE_GS_9:
1696 case SQ_ALU_CONST_CACHE_GS_10:
1697 case SQ_ALU_CONST_CACHE_GS_11:
1698 case SQ_ALU_CONST_CACHE_GS_12:
1699 case SQ_ALU_CONST_CACHE_GS_13:
1700 case SQ_ALU_CONST_CACHE_GS_14:
1701 case SQ_ALU_CONST_CACHE_GS_15:
1702 case SQ_ALU_CONST_CACHE_PS_0:
1703 case SQ_ALU_CONST_CACHE_PS_1:
1704 case SQ_ALU_CONST_CACHE_PS_2:
1705 case SQ_ALU_CONST_CACHE_PS_3:
1706 case SQ_ALU_CONST_CACHE_PS_4:
1707 case SQ_ALU_CONST_CACHE_PS_5:
1708 case SQ_ALU_CONST_CACHE_PS_6:
1709 case SQ_ALU_CONST_CACHE_PS_7:
1710 case SQ_ALU_CONST_CACHE_PS_8:
1711 case SQ_ALU_CONST_CACHE_PS_9:
1712 case SQ_ALU_CONST_CACHE_PS_10:
1713 case SQ_ALU_CONST_CACHE_PS_11:
1714 case SQ_ALU_CONST_CACHE_PS_12:
1715 case SQ_ALU_CONST_CACHE_PS_13:
1716 case SQ_ALU_CONST_CACHE_PS_14:
1717 case SQ_ALU_CONST_CACHE_PS_15:
1718 case SQ_ALU_CONST_CACHE_VS_0:
1719 case SQ_ALU_CONST_CACHE_VS_1:
1720 case SQ_ALU_CONST_CACHE_VS_2:
1721 case SQ_ALU_CONST_CACHE_VS_3:
1722 case SQ_ALU_CONST_CACHE_VS_4:
1723 case SQ_ALU_CONST_CACHE_VS_5:
1724 case SQ_ALU_CONST_CACHE_VS_6:
1725 case SQ_ALU_CONST_CACHE_VS_7:
1726 case SQ_ALU_CONST_CACHE_VS_8:
1727 case SQ_ALU_CONST_CACHE_VS_9:
1728 case SQ_ALU_CONST_CACHE_VS_10:
1729 case SQ_ALU_CONST_CACHE_VS_11:
1730 case SQ_ALU_CONST_CACHE_VS_12:
1731 case SQ_ALU_CONST_CACHE_VS_13:
1732 case SQ_ALU_CONST_CACHE_VS_14:
1733 case SQ_ALU_CONST_CACHE_VS_15:
1734 case SQ_ALU_CONST_CACHE_HS_0:
1735 case SQ_ALU_CONST_CACHE_HS_1:
1736 case SQ_ALU_CONST_CACHE_HS_2:
1737 case SQ_ALU_CONST_CACHE_HS_3:
1738 case SQ_ALU_CONST_CACHE_HS_4:
1739 case SQ_ALU_CONST_CACHE_HS_5:
1740 case SQ_ALU_CONST_CACHE_HS_6:
1741 case SQ_ALU_CONST_CACHE_HS_7:
1742 case SQ_ALU_CONST_CACHE_HS_8:
1743 case SQ_ALU_CONST_CACHE_HS_9:
1744 case SQ_ALU_CONST_CACHE_HS_10:
1745 case SQ_ALU_CONST_CACHE_HS_11:
1746 case SQ_ALU_CONST_CACHE_HS_12:
1747 case SQ_ALU_CONST_CACHE_HS_13:
1748 case SQ_ALU_CONST_CACHE_HS_14:
1749 case SQ_ALU_CONST_CACHE_HS_15:
1750 case SQ_ALU_CONST_CACHE_LS_0:
1751 case SQ_ALU_CONST_CACHE_LS_1:
1752 case SQ_ALU_CONST_CACHE_LS_2:
1753 case SQ_ALU_CONST_CACHE_LS_3:
1754 case SQ_ALU_CONST_CACHE_LS_4:
1755 case SQ_ALU_CONST_CACHE_LS_5:
1756 case SQ_ALU_CONST_CACHE_LS_6:
1757 case SQ_ALU_CONST_CACHE_LS_7:
1758 case SQ_ALU_CONST_CACHE_LS_8:
1759 case SQ_ALU_CONST_CACHE_LS_9:
1760 case SQ_ALU_CONST_CACHE_LS_10:
1761 case SQ_ALU_CONST_CACHE_LS_11:
1762 case SQ_ALU_CONST_CACHE_LS_12:
1763 case SQ_ALU_CONST_CACHE_LS_13:
1764 case SQ_ALU_CONST_CACHE_LS_14:
1765 case SQ_ALU_CONST_CACHE_LS_15:
1766 r = evergreen_cs_packet_next_reloc(p, &reloc);
1767 if (r) {
1768 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1769 "0x%04X\n", reg);
1770 return -EINVAL;
1771 }
1772 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1773 break;
033b5650
AD		 1774 case SX_MEMORY_EXPORT_BASE:
1775 if (p->rdev->family >= CHIP_CAYMAN) {
1776 dev_warn(p->dev, "bad SET_CONFIG_REG "
1777 "0x%04X\n", reg);
1778 return -EINVAL;
1779 }
1780 r = evergreen_cs_packet_next_reloc(p, &reloc);
1781 if (r) {
1782 dev_warn(p->dev, "bad SET_CONFIG_REG "
1783 "0x%04X\n", reg);
1784 return -EINVAL;
1785 }
1786 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1787 break;
1788 case CAYMAN_SX_SCATTER_EXPORT_BASE:
1789 if (p->rdev->family < CHIP_CAYMAN) {
1790 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1791 "0x%04X\n", reg);
1792 return -EINVAL;
1793 }
1794 r = evergreen_cs_packet_next_reloc(p, &reloc);
1795 if (r) {
1796 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1797 "0x%04X\n", reg);
1798 return -EINVAL;
1799 }
1800 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1801 break;
779923bc
MO		 1802 case SX_MISC:
1803 track->sx_misc_kill_all_prims = (radeon_get_ib_value(p, idx) & 0x1) != 0;
1804 break;
cb5fcbd5
AD		 1805 default:
1806 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
1807 return -EINVAL;
1808 }
1809 return 0;
1810}
1811
dd220a00
MO		 1812static bool evergreen_is_safe_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
1813{
1814 u32 last_reg, m, i;
1815
1816 if (p->rdev->family >= CHIP_CAYMAN)
1817 last_reg = ARRAY_SIZE(cayman_reg_safe_bm);
1818 else
1819 last_reg = ARRAY_SIZE(evergreen_reg_safe_bm);
1820
1821 i = (reg >> 7);
1822 if (i >= last_reg) {
1823 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
1824 return false;
1825 }
1826 m = 1 << ((reg >> 2) & 31);
1827 if (p->rdev->family >= CHIP_CAYMAN) {
1828 if (!(cayman_reg_safe_bm[i] & m))
1829 return true;
1830 } else {
1831 if (!(evergreen_reg_safe_bm[i] & m))
1832 return true;
1833 }
1834 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
1835 return false;
1836}
1837
cb5fcbd5
AD		 1838static int evergreen_packet3_check(struct radeon_cs_parser *p,
1839 struct radeon_cs_packet *pkt)
1840{
1841 struct radeon_cs_reloc *reloc;
1842 struct evergreen_cs_track *track;
1843 volatile u32 *ib;
1844 unsigned idx;
1845 unsigned i;
1846 unsigned start_reg, end_reg, reg;
1847 int r;
1848 u32 idx_value;
1849
1850 track = (struct evergreen_cs_track *)p->track;
f2e39221 1851 ib = p->ib.ptr;
cb5fcbd5
AD		 1852 idx = pkt->idx + 1;
1853 idx_value = radeon_get_ib_value(p, idx);
1854
1855 switch (pkt->opcode) {
2a19cac8
DA		 1856 case PACKET3_SET_PREDICATION:
1857 {
1858 int pred_op;
1859 int tmp;
78857131
MO		 1860 uint64_t offset;
1861
2a19cac8
DA		 1862 if (pkt->count != 1) {
1863 DRM_ERROR("bad SET PREDICATION\n");
1864 return -EINVAL;
1865 }
1866
1867 tmp = radeon_get_ib_value(p, idx + 1);
1868 pred_op = (tmp >> 16) & 0x7;
1869
1870 /* for the clear predicate operation */
1871 if (pred_op == 0)
1872 return 0;
1873
1874 if (pred_op > 2) {
1875 DRM_ERROR("bad SET PREDICATION operation %d\n", pred_op);
1876 return -EINVAL;
1877 }
1878
1879 r = evergreen_cs_packet_next_reloc(p, &reloc);
1880 if (r) {
1881 DRM_ERROR("bad SET PREDICATION\n");
1882 return -EINVAL;
1883 }
1884
78857131
MO		 1885 offset = reloc->lobj.gpu_offset +
1886 (idx_value & 0xfffffff0) +
1887 ((u64)(tmp & 0xff) << 32);
1888
1889 ib[idx + 0] = offset;
1890 ib[idx + 1] = (tmp & 0xffffff00) | (upper_32_bits(offset) & 0xff);
2a19cac8
DA		 1891 }
1892 break;
cb5fcbd5
AD		 1893 case PACKET3_CONTEXT_CONTROL:
1894 if (pkt->count != 1) {
1895 DRM_ERROR("bad CONTEXT_CONTROL\n");
1896 return -EINVAL;
1897 }
1898 break;
1899 case PACKET3_INDEX_TYPE:
1900 case PACKET3_NUM_INSTANCES:
1901 case PACKET3_CLEAR_STATE:
1902 if (pkt->count) {
1903 DRM_ERROR("bad INDEX_TYPE/NUM_INSTANCES/CLEAR_STATE\n");
1904 return -EINVAL;
1905 }
1906 break;
c175ca9a
AD		 1907 case CAYMAN_PACKET3_DEALLOC_STATE:
1908 if (p->rdev->family < CHIP_CAYMAN) {
1909 DRM_ERROR("bad PACKET3_DEALLOC_STATE\n");
1910 return -EINVAL;
1911 }
1912 if (pkt->count) {
1913 DRM_ERROR("bad INDEX_TYPE/NUM_INSTANCES/CLEAR_STATE\n");
1914 return -EINVAL;
1915 }
1916 break;
cb5fcbd5 1917 case PACKET3_INDEX_BASE:
78857131
MO		 1918 {
1919 uint64_t offset;
1920
cb5fcbd5
AD		 1921 if (pkt->count != 1) {
1922 DRM_ERROR("bad INDEX_BASE\n");
1923 return -EINVAL;
1924 }
1925 r = evergreen_cs_packet_next_reloc(p, &reloc);
1926 if (r) {
1927 DRM_ERROR("bad INDEX_BASE\n");
1928 return -EINVAL;
1929 }
78857131
MO		 1930
1931 offset = reloc->lobj.gpu_offset +
1932 idx_value +
1933 ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32);
1934
1935 ib[idx+0] = offset;
1936 ib[idx+1] = upper_32_bits(offset) & 0xff;
1937
cb5fcbd5
AD		 1938 r = evergreen_cs_track_check(p);
1939 if (r) {
1940 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
1941 return r;
1942 }
1943 break;
78857131 1944 }
cb5fcbd5 1945 case PACKET3_DRAW_INDEX:
78857131
MO		 1946 {
1947 uint64_t offset;
cb5fcbd5
AD		 1948 if (pkt->count != 3) {
1949 DRM_ERROR("bad DRAW_INDEX\n");
1950 return -EINVAL;
1951 }
1952 r = evergreen_cs_packet_next_reloc(p, &reloc);
1953 if (r) {
1954 DRM_ERROR("bad DRAW_INDEX\n");
1955 return -EINVAL;
1956 }
78857131
MO		 1957
1958 offset = reloc->lobj.gpu_offset +
1959 idx_value +
1960 ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32);
1961
1962 ib[idx+0] = offset;
1963 ib[idx+1] = upper_32_bits(offset) & 0xff;
1964
cb5fcbd5
AD		 1965 r = evergreen_cs_track_check(p);
1966 if (r) {
1967 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
1968 return r;
1969 }
1970 break;
78857131 1971 }
cb5fcbd5 1972 case PACKET3_DRAW_INDEX_2:
78857131
MO		 1973 {
1974 uint64_t offset;
1975
cb5fcbd5
AD		 1976 if (pkt->count != 4) {
1977 DRM_ERROR("bad DRAW_INDEX_2\n");
1978 return -EINVAL;
1979 }
1980 r = evergreen_cs_packet_next_reloc(p, &reloc);
1981 if (r) {
1982 DRM_ERROR("bad DRAW_INDEX_2\n");
1983 return -EINVAL;
1984 }
78857131
MO		 1985
1986 offset = reloc->lobj.gpu_offset +
1987 radeon_get_ib_value(p, idx+1) +
1988 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);
1989
1990 ib[idx+1] = offset;
1991 ib[idx+2] = upper_32_bits(offset) & 0xff;
1992
cb5fcbd5
AD		 1993 r = evergreen_cs_track_check(p);
1994 if (r) {
1995 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
1996 return r;
1997 }
1998 break;
78857131 1999 }
cb5fcbd5
AD		 2000 case PACKET3_DRAW_INDEX_AUTO:
2001 if (pkt->count != 1) {
2002 DRM_ERROR("bad DRAW_INDEX_AUTO\n");
2003 return -EINVAL;
2004 }
2005 r = evergreen_cs_track_check(p);
2006 if (r) {
2007 dev_warn(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx);
2008 return r;
2009 }
2010 break;
2011 case PACKET3_DRAW_INDEX_MULTI_AUTO:
2012 if (pkt->count != 2) {
2013 DRM_ERROR("bad DRAW_INDEX_MULTI_AUTO\n");
2014 return -EINVAL;
2015 }
2016 r = evergreen_cs_track_check(p);
2017 if (r) {
2018 dev_warn(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx);
2019 return r;
2020 }
2021 break;
2022 case PACKET3_DRAW_INDEX_IMMD:
2023 if (pkt->count < 2) {
2024 DRM_ERROR("bad DRAW_INDEX_IMMD\n");
2025 return -EINVAL;
2026 }
2027 r = evergreen_cs_track_check(p);
2028 if (r) {
2029 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
2030 return r;
2031 }
2032 break;
2033 case PACKET3_DRAW_INDEX_OFFSET:
2034 if (pkt->count != 2) {
2035 DRM_ERROR("bad DRAW_INDEX_OFFSET\n");
2036 return -EINVAL;
2037 }
2038 r = evergreen_cs_track_check(p);
2039 if (r) {
2040 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
2041 return r;
2042 }
2043 break;
2044 case PACKET3_DRAW_INDEX_OFFSET_2:
2045 if (pkt->count != 3) {
2046 DRM_ERROR("bad DRAW_INDEX_OFFSET_2\n");
2047 return -EINVAL;
2048 }
2049 r = evergreen_cs_track_check(p);
2050 if (r) {
2051 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
2052 return r;
2053 }
2054 break;
033b5650
AD		 2055 case PACKET3_DISPATCH_DIRECT:
2056 if (pkt->count != 3) {
2057 DRM_ERROR("bad DISPATCH_DIRECT\n");
2058 return -EINVAL;
2059 }
2060 r = evergreen_cs_track_check(p);
2061 if (r) {
2062 dev_warn(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx);
2063 return r;
2064 }
2065 break;
2066 case PACKET3_DISPATCH_INDIRECT:
2067 if (pkt->count != 1) {
2068 DRM_ERROR("bad DISPATCH_INDIRECT\n");
2069 return -EINVAL;
2070 }
2071 r = evergreen_cs_packet_next_reloc(p, &reloc);
2072 if (r) {
2073 DRM_ERROR("bad DISPATCH_INDIRECT\n");
2074 return -EINVAL;
2075 }
2076 ib[idx+0] = idx_value + (u32)(reloc->lobj.gpu_offset & 0xffffffff);
2077 r = evergreen_cs_track_check(p);
2078 if (r) {
2079 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
2080 return r;
2081 }
2082 break;
cb5fcbd5
AD		 2083 case PACKET3_WAIT_REG_MEM:
2084 if (pkt->count != 5) {
2085 DRM_ERROR("bad WAIT_REG_MEM\n");
2086 return -EINVAL;
2087 }
2088 /* bit 4 is reg (0) or mem (1) */
2089 if (idx_value & 0x10) {
78857131
MO		 2090 uint64_t offset;
2091
cb5fcbd5
AD		 2092 r = evergreen_cs_packet_next_reloc(p, &reloc);
2093 if (r) {
2094 DRM_ERROR("bad WAIT_REG_MEM\n");
2095 return -EINVAL;
2096 }
78857131
MO		 2097
2098 offset = reloc->lobj.gpu_offset +
2099 (radeon_get_ib_value(p, idx+1) & 0xfffffffc) +
2100 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);
2101
2102 ib[idx+1] = (ib[idx+1] & 0x3) | (offset & 0xfffffffc);
2103 ib[idx+2] = upper_32_bits(offset) & 0xff;
d6e18a34
IH		 2104 } else if (idx_value & 0x100) {
2105 DRM_ERROR("cannot use PFP on REG wait\n");
2106 return -EINVAL;
cb5fcbd5
AD		 2107 }
2108 break;
8770b86b
AD		 2109 case PACKET3_CP_DMA:
2110 {
2111 u32 command, size, info;
2112 u64 offset, tmp;
2113 if (pkt->count != 4) {
2114 DRM_ERROR("bad CP DMA\n");
2115 return -EINVAL;
2116 }
2117 command = radeon_get_ib_value(p, idx+4);
2118 size = command & 0x1fffff;
2119 info = radeon_get_ib_value(p, idx+1);
9d89d78e
AD		 2120 if ((((info & 0x60000000) >> 29) != 0) || /* src = GDS or DATA */
2121 (((info & 0x00300000) >> 20) != 0) || /* dst = GDS */
2122 ((((info & 0x00300000) >> 20) == 0) &&
2123 (command & PACKET3_CP_DMA_CMD_DAS)) || /* dst = register */
2124 ((((info & 0x60000000) >> 29) == 0) &&
2125 (command & PACKET3_CP_DMA_CMD_SAS))) { /* src = register */
2126 /* non mem to mem copies requires dw aligned count */
2127 if (size % 4) {
2128 DRM_ERROR("CP DMA command requires dw count alignment\n");
2129 return -EINVAL;
2130 }
2131 }
8770b86b
AD		 2132 if (command & PACKET3_CP_DMA_CMD_SAS) {
2133 /* src address space is register */
2134 /* GDS is ok */
2135 if (((info & 0x60000000) >> 29) != 1) {
2136 DRM_ERROR("CP DMA SAS not supported\n");
2137 return -EINVAL;
2138 }
2139 } else {
2140 if (command & PACKET3_CP_DMA_CMD_SAIC) {
2141 DRM_ERROR("CP DMA SAIC only supported for registers\n");
2142 return -EINVAL;
2143 }
2144 /* src address space is memory */
2145 if (((info & 0x60000000) >> 29) == 0) {
2146 r = evergreen_cs_packet_next_reloc(p, &reloc);
2147 if (r) {
2148 DRM_ERROR("bad CP DMA SRC\n");
2149 return -EINVAL;
2150 }
2151
2152 tmp = radeon_get_ib_value(p, idx) +
2153 ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32);
2154
2155 offset = reloc->lobj.gpu_offset + tmp;
2156
2157 if ((tmp + size) > radeon_bo_size(reloc->robj)) {
2158 dev_warn(p->dev, "CP DMA src buffer too small (%llu %lu)\n",
2159 tmp + size, radeon_bo_size(reloc->robj));
2160 return -EINVAL;
2161 }
2162
2163 ib[idx] = offset;
2164 ib[idx+1] = (ib[idx+1] & 0xffffff00) | (upper_32_bits(offset) & 0xff);
2165 } else if (((info & 0x60000000) >> 29) != 2) {
2166 DRM_ERROR("bad CP DMA SRC_SEL\n");
2167 return -EINVAL;
2168 }
2169 }
2170 if (command & PACKET3_CP_DMA_CMD_DAS) {
2171 /* dst address space is register */
2172 /* GDS is ok */
2173 if (((info & 0x00300000) >> 20) != 1) {
2174 DRM_ERROR("CP DMA DAS not supported\n");
2175 return -EINVAL;
2176 }
2177 } else {
2178 /* dst address space is memory */
2179 if (command & PACKET3_CP_DMA_CMD_DAIC) {
2180 DRM_ERROR("CP DMA DAIC only supported for registers\n");
2181 return -EINVAL;
2182 }
2183 if (((info & 0x00300000) >> 20) == 0) {
2184 r = evergreen_cs_packet_next_reloc(p, &reloc);
2185 if (r) {
2186 DRM_ERROR("bad CP DMA DST\n");
2187 return -EINVAL;
2188 }
2189
2190 tmp = radeon_get_ib_value(p, idx+2) +
2191 ((u64)(radeon_get_ib_value(p, idx+3) & 0xff) << 32);
2192
2193 offset = reloc->lobj.gpu_offset + tmp;
2194
2195 if ((tmp + size) > radeon_bo_size(reloc->robj)) {
2196 dev_warn(p->dev, "CP DMA dst buffer too small (%llu %lu)\n",
2197 tmp + size, radeon_bo_size(reloc->robj));
2198 return -EINVAL;
2199 }
2200
2201 ib[idx+2] = offset;
2202 ib[idx+3] = upper_32_bits(offset) & 0xff;
2203 } else {
2204 DRM_ERROR("bad CP DMA DST_SEL\n");
2205 return -EINVAL;
2206 }
2207 }
2208 break;
2209 }
cb5fcbd5
AD		 2210 case PACKET3_SURFACE_SYNC:
2211 if (pkt->count != 3) {
2212 DRM_ERROR("bad SURFACE_SYNC\n");
2213 return -EINVAL;
2214 }
2215 /* 0xffffffff/0x0 is flush all cache flag */
2216 if (radeon_get_ib_value(p, idx + 1) != 0xffffffff ||
2217 radeon_get_ib_value(p, idx + 2) != 0) {
2218 r = evergreen_cs_packet_next_reloc(p, &reloc);
2219 if (r) {
2220 DRM_ERROR("bad SURFACE_SYNC\n");
2221 return -EINVAL;
2222 }
2223 ib[idx+2] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
2224 }
2225 break;
2226 case PACKET3_EVENT_WRITE:
2227 if (pkt->count != 2 && pkt->count != 0) {
2228 DRM_ERROR("bad EVENT_WRITE\n");
2229 return -EINVAL;
2230 }
2231 if (pkt->count) {
78857131
MO		 2232 uint64_t offset;
2233
cb5fcbd5
AD		 2234 r = evergreen_cs_packet_next_reloc(p, &reloc);
2235 if (r) {
2236 DRM_ERROR("bad EVENT_WRITE\n");
2237 return -EINVAL;
2238 }
78857131
MO		 2239 offset = reloc->lobj.gpu_offset +
2240 (radeon_get_ib_value(p, idx+1) & 0xfffffff8) +
2241 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);
2242
2243 ib[idx+1] = offset & 0xfffffff8;
2244 ib[idx+2] = upper_32_bits(offset) & 0xff;
cb5fcbd5
AD		 2245 }
2246 break;
2247 case PACKET3_EVENT_WRITE_EOP:
78857131
MO		 2248 {
2249 uint64_t offset;
2250
cb5fcbd5
AD		 2251 if (pkt->count != 4) {
2252 DRM_ERROR("bad EVENT_WRITE_EOP\n");
2253 return -EINVAL;
2254 }
2255 r = evergreen_cs_packet_next_reloc(p, &reloc);
2256 if (r) {
2257 DRM_ERROR("bad EVENT_WRITE_EOP\n");
2258 return -EINVAL;
2259 }
78857131
MO		 2260
2261 offset = reloc->lobj.gpu_offset +
2262 (radeon_get_ib_value(p, idx+1) & 0xfffffffc) +
2263 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);
2264
2265 ib[idx+1] = offset & 0xfffffffc;
2266 ib[idx+2] = (ib[idx+2] & 0xffffff00) | (upper_32_bits(offset) & 0xff);
cb5fcbd5 2267 break;
78857131 2268 }
cb5fcbd5 2269 case PACKET3_EVENT_WRITE_EOS:
78857131
MO		 2270 {
2271 uint64_t offset;
2272
cb5fcbd5
AD		 2273 if (pkt->count != 3) {
2274 DRM_ERROR("bad EVENT_WRITE_EOS\n");
2275 return -EINVAL;
2276 }
2277 r = evergreen_cs_packet_next_reloc(p, &reloc);
2278 if (r) {
2279 DRM_ERROR("bad EVENT_WRITE_EOS\n");
2280 return -EINVAL;
2281 }
78857131
MO		 2282
2283 offset = reloc->lobj.gpu_offset +
2284 (radeon_get_ib_value(p, idx+1) & 0xfffffffc) +
2285 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);
2286
2287 ib[idx+1] = offset & 0xfffffffc;
2288 ib[idx+2] = (ib[idx+2] & 0xffffff00) | (upper_32_bits(offset) & 0xff);
cb5fcbd5 2289 break;
78857131 2290 }
cb5fcbd5
AD		 2291 case PACKET3_SET_CONFIG_REG:
2292 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_START;
2293 end_reg = 4 * pkt->count + start_reg - 4;
2294 if ((start_reg < PACKET3_SET_CONFIG_REG_START) ||
2295 (start_reg >= PACKET3_SET_CONFIG_REG_END) ||
2296 (end_reg >= PACKET3_SET_CONFIG_REG_END)) {
2297 DRM_ERROR("bad PACKET3_SET_CONFIG_REG\n");
2298 return -EINVAL;
2299 }
2300 for (i = 0; i < pkt->count; i++) {
2301 reg = start_reg + (4 * i);
2302 r = evergreen_cs_check_reg(p, reg, idx+1+i);
2303 if (r)
2304 return r;
2305 }
2306 break;
2307 case PACKET3_SET_CONTEXT_REG:
2308 start_reg = (idx_value << 2) + PACKET3_SET_CONTEXT_REG_START;
2309 end_reg = 4 * pkt->count + start_reg - 4;
2310 if ((start_reg < PACKET3_SET_CONTEXT_REG_START) ||
2311 (start_reg >= PACKET3_SET_CONTEXT_REG_END) ||
2312 (end_reg >= PACKET3_SET_CONTEXT_REG_END)) {
2313 DRM_ERROR("bad PACKET3_SET_CONTEXT_REG\n");
2314 return -EINVAL;
2315 }
2316 for (i = 0; i < pkt->count; i++) {
2317 reg = start_reg + (4 * i);
2318 r = evergreen_cs_check_reg(p, reg, idx+1+i);
2319 if (r)
2320 return r;
2321 }
2322 break;
2323 case PACKET3_SET_RESOURCE:
2324 if (pkt->count % 8) {
2325 DRM_ERROR("bad SET_RESOURCE\n");
2326 return -EINVAL;
2327 }
2328 start_reg = (idx_value << 2) + PACKET3_SET_RESOURCE_START;
2329 end_reg = 4 * pkt->count + start_reg - 4;
2330 if ((start_reg < PACKET3_SET_RESOURCE_START) ||
2331 (start_reg >= PACKET3_SET_RESOURCE_END) ||
2332 (end_reg >= PACKET3_SET_RESOURCE_END)) {
2333 DRM_ERROR("bad SET_RESOURCE\n");
2334 return -EINVAL;
2335 }
2336 for (i = 0; i < (pkt->count / 8); i++) {
2337 struct radeon_bo *texture, *mipmap;
285484e2 2338 u32 toffset, moffset;
61051afd 2339 u32 size, offset, mip_address, tex_dim;
cb5fcbd5
AD		 2340
2341 switch (G__SQ_CONSTANT_TYPE(radeon_get_ib_value(p, idx+1+(i*8)+7))) {
2342 case SQ_TEX_VTX_VALID_TEXTURE:
2343 /* tex base */
2344 r = evergreen_cs_packet_next_reloc(p, &reloc);
2345 if (r) {
2346 DRM_ERROR("bad SET_RESOURCE (tex)\n");
2347 return -EINVAL;
2348 }
721604a1 2349 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
f3a71df0
AD		 2350 ib[idx+1+(i*8)+1] |=
2351 TEX_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
2352 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
285484e2
JG		 2353 unsigned bankw, bankh, mtaspect, tile_split;
2354
2355 evergreen_tiling_fields(reloc->lobj.tiling_flags,
2356 &bankw, &bankh, &mtaspect,
2357 &tile_split);
2358 ib[idx+1+(i*8)+6] |= TEX_TILE_SPLIT(tile_split);
f3a71df0 2359 ib[idx+1+(i*8)+7] |=
285484e2
JG		 2360 TEX_BANK_WIDTH(bankw) |
2361 TEX_BANK_HEIGHT(bankh) |
2362 MACRO_TILE_ASPECT(mtaspect) |
f3a71df0
AD		 2363 TEX_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks));
2364 }
e70f224c 2365 }
cb5fcbd5 2366 texture = reloc->robj;
285484e2 2367 toffset = (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
61051afd 2368
cb5fcbd5 2369 /* tex mip base */
61051afd
MO		 2370 tex_dim = ib[idx+1+(i*8)+0] & 0x7;
2371 mip_address = ib[idx+1+(i*8)+3];
2372
2373 if ((tex_dim == SQ_TEX_DIM_2D_MSAA || tex_dim == SQ_TEX_DIM_2D_ARRAY_MSAA) &&
2374 !mip_address &&
9ffb7a6d 2375 !radeon_cs_packet_next_is_pkt3_nop(p)) {
61051afd
MO		 2376 /* MIP_ADDRESS should point to FMASK for an MSAA texture.
2377 * It should be 0 if FMASK is disabled. */
2378 moffset = 0;
2379 mipmap = NULL;
2380 } else {
2381 r = evergreen_cs_packet_next_reloc(p, &reloc);
2382 if (r) {
2383 DRM_ERROR("bad SET_RESOURCE (tex)\n");
2384 return -EINVAL;
2385 }
2386 moffset = (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
2387 mipmap = reloc->robj;
cb5fcbd5 2388 }
61051afd 2389
285484e2 2390 r = evergreen_cs_track_validate_texture(p, texture, mipmap, idx+1+(i*8));
cb5fcbd5
AD		 2391 if (r)
2392 return r;
285484e2
JG		 2393 ib[idx+1+(i*8)+2] += toffset;
2394 ib[idx+1+(i*8)+3] += moffset;
cb5fcbd5
AD		 2395 break;
2396 case SQ_TEX_VTX_VALID_BUFFER:
78857131
MO		 2397 {
2398 uint64_t offset64;
cb5fcbd5
AD		 2399 /* vtx base */
2400 r = evergreen_cs_packet_next_reloc(p, &reloc);
2401 if (r) {
2402 DRM_ERROR("bad SET_RESOURCE (vtx)\n");
2403 return -EINVAL;
2404 }
2405 offset = radeon_get_ib_value(p, idx+1+(i*8)+0);
2406 size = radeon_get_ib_value(p, idx+1+(i*8)+1);
2407 if (p->rdev && (size + offset) > radeon_bo_size(reloc->robj)) {
2408 /* force size to size of the buffer */
2409 dev_warn(p->dev, "vbo resource seems too big for the bo\n");
78857131 2410 ib[idx+1+(i*8)+1] = radeon_bo_size(reloc->robj) - offset;
cb5fcbd5 2411 }
78857131
MO		 2412
2413 offset64 = reloc->lobj.gpu_offset + offset;
2414 ib[idx+1+(i*8)+0] = offset64;
2415 ib[idx+1+(i*8)+2] = (ib[idx+1+(i*8)+2] & 0xffffff00) |
2416 (upper_32_bits(offset64) & 0xff);
cb5fcbd5 2417 break;
78857131 2418 }
cb5fcbd5
AD		 2419 case SQ_TEX_VTX_INVALID_TEXTURE:
2420 case SQ_TEX_VTX_INVALID_BUFFER:
2421 default:
2422 DRM_ERROR("bad SET_RESOURCE\n");
2423 return -EINVAL;
2424 }
2425 }
2426 break;
2427 case PACKET3_SET_ALU_CONST:
2428 /* XXX fix me ALU const buffers only */
2429 break;
2430 case PACKET3_SET_BOOL_CONST:
2431 start_reg = (idx_value << 2) + PACKET3_SET_BOOL_CONST_START;
2432 end_reg = 4 * pkt->count + start_reg - 4;
2433 if ((start_reg < PACKET3_SET_BOOL_CONST_START) ||
2434 (start_reg >= PACKET3_SET_BOOL_CONST_END) ||
2435 (end_reg >= PACKET3_SET_BOOL_CONST_END)) {
2436 DRM_ERROR("bad SET_BOOL_CONST\n");
2437 return -EINVAL;
2438 }
2439 break;
2440 case PACKET3_SET_LOOP_CONST:
2441 start_reg = (idx_value << 2) + PACKET3_SET_LOOP_CONST_START;
2442 end_reg = 4 * pkt->count + start_reg - 4;
2443 if ((start_reg < PACKET3_SET_LOOP_CONST_START) ||
2444 (start_reg >= PACKET3_SET_LOOP_CONST_END) ||
2445 (end_reg >= PACKET3_SET_LOOP_CONST_END)) {
2446 DRM_ERROR("bad SET_LOOP_CONST\n");
2447 return -EINVAL;
2448 }
2449 break;
2450 case PACKET3_SET_CTL_CONST:
2451 start_reg = (idx_value << 2) + PACKET3_SET_CTL_CONST_START;
2452 end_reg = 4 * pkt->count + start_reg - 4;
2453 if ((start_reg < PACKET3_SET_CTL_CONST_START) ||
2454 (start_reg >= PACKET3_SET_CTL_CONST_END) ||
2455 (end_reg >= PACKET3_SET_CTL_CONST_END)) {
2456 DRM_ERROR("bad SET_CTL_CONST\n");
2457 return -EINVAL;
2458 }
2459 break;
2460 case PACKET3_SET_SAMPLER:
2461 if (pkt->count % 3) {
2462 DRM_ERROR("bad SET_SAMPLER\n");
2463 return -EINVAL;
2464 }
2465 start_reg = (idx_value << 2) + PACKET3_SET_SAMPLER_START;
2466 end_reg = 4 * pkt->count + start_reg - 4;
2467 if ((start_reg < PACKET3_SET_SAMPLER_START) ||
2468 (start_reg >= PACKET3_SET_SAMPLER_END) ||
2469 (end_reg >= PACKET3_SET_SAMPLER_END)) {
2470 DRM_ERROR("bad SET_SAMPLER\n");
2471 return -EINVAL;
2472 }
2473 break;
dd220a00
MO		 2474 case PACKET3_STRMOUT_BUFFER_UPDATE:
2475 if (pkt->count != 4) {
2476 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (invalid count)\n");
2477 return -EINVAL;
2478 }
2479 /* Updating memory at DST_ADDRESS. */
2480 if (idx_value & 0x1) {
2481 u64 offset;
2482 r = evergreen_cs_packet_next_reloc(p, &reloc);
2483 if (r) {
2484 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (missing dst reloc)\n");
2485 return -EINVAL;
2486 }
2487 offset = radeon_get_ib_value(p, idx+1);
2488 offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32;
2489 if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2490 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE dst bo too small: 0x%llx, 0x%lx\n",
2491 offset + 4, radeon_bo_size(reloc->robj));
2492 return -EINVAL;
2493 }
78857131
MO		 2494 offset += reloc->lobj.gpu_offset;
2495 ib[idx+1] = offset;
2496 ib[idx+2] = upper_32_bits(offset) & 0xff;
dd220a00
MO		 2497 }
2498 /* Reading data from SRC_ADDRESS. */
2499 if (((idx_value >> 1) & 0x3) == 2) {
2500 u64 offset;
2501 r = evergreen_cs_packet_next_reloc(p, &reloc);
2502 if (r) {
2503 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (missing src reloc)\n");
2504 return -EINVAL;
2505 }
2506 offset = radeon_get_ib_value(p, idx+3);
2507 offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;
2508 if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2509 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE src bo too small: 0x%llx, 0x%lx\n",
2510 offset + 4, radeon_bo_size(reloc->robj));
2511 return -EINVAL;
2512 }
78857131
MO		 2513 offset += reloc->lobj.gpu_offset;
2514 ib[idx+3] = offset;
2515 ib[idx+4] = upper_32_bits(offset) & 0xff;
dd220a00
MO		 2516 }
2517 break;
4613ca14
JG		 2518 case PACKET3_MEM_WRITE:
2519 {
2520 u64 offset;
2521
2522 if (pkt->count != 3) {
2523 DRM_ERROR("bad MEM_WRITE (invalid count)\n");
2524 return -EINVAL;
2525 }
2526 r = evergreen_cs_packet_next_reloc(p, &reloc);
2527 if (r) {
2528 DRM_ERROR("bad MEM_WRITE (missing reloc)\n");
2529 return -EINVAL;
2530 }
2531 offset = radeon_get_ib_value(p, idx+0);
2532 offset += ((u64)(radeon_get_ib_value(p, idx+1) & 0xff)) << 32UL;
2533 if (offset & 0x7) {
2534 DRM_ERROR("bad MEM_WRITE (address not qwords aligned)\n");
2535 return -EINVAL;
2536 }
2537 if ((offset + 8) > radeon_bo_size(reloc->robj)) {
2538 DRM_ERROR("bad MEM_WRITE bo too small: 0x%llx, 0x%lx\n",
2539 offset + 8, radeon_bo_size(reloc->robj));
2540 return -EINVAL;
2541 }
2542 offset += reloc->lobj.gpu_offset;
2543 ib[idx+0] = offset;
2544 ib[idx+1] = upper_32_bits(offset) & 0xff;
2545 break;
2546 }
dd220a00
MO		 2547 case PACKET3_COPY_DW:
2548 if (pkt->count != 4) {
2549 DRM_ERROR("bad COPY_DW (invalid count)\n");
2550 return -EINVAL;
2551 }
2552 if (idx_value & 0x1) {
2553 u64 offset;
2554 /* SRC is memory. */
2555 r = evergreen_cs_packet_next_reloc(p, &reloc);
2556 if (r) {
2557 DRM_ERROR("bad COPY_DW (missing src reloc)\n");
2558 return -EINVAL;
2559 }
2560 offset = radeon_get_ib_value(p, idx+1);
2561 offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32;
2562 if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2563 DRM_ERROR("bad COPY_DW src bo too small: 0x%llx, 0x%lx\n",
2564 offset + 4, radeon_bo_size(reloc->robj));
2565 return -EINVAL;
2566 }
78857131
MO		 2567 offset += reloc->lobj.gpu_offset;
2568 ib[idx+1] = offset;
2569 ib[idx+2] = upper_32_bits(offset) & 0xff;
dd220a00
MO		 2570 } else {
2571 /* SRC is a reg. */
2572 reg = radeon_get_ib_value(p, idx+1) << 2;
2573 if (!evergreen_is_safe_reg(p, reg, idx+1))
2574 return -EINVAL;
2575 }
2576 if (idx_value & 0x2) {
2577 u64 offset;
2578 /* DST is memory. */
2579 r = evergreen_cs_packet_next_reloc(p, &reloc);
2580 if (r) {
2581 DRM_ERROR("bad COPY_DW (missing dst reloc)\n");
2582 return -EINVAL;
2583 }
2584 offset = radeon_get_ib_value(p, idx+3);
2585 offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;
2586 if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2587 DRM_ERROR("bad COPY_DW dst bo too small: 0x%llx, 0x%lx\n",
2588 offset + 4, radeon_bo_size(reloc->robj));
2589 return -EINVAL;
2590 }
78857131
MO		 2591 offset += reloc->lobj.gpu_offset;
2592 ib[idx+3] = offset;
2593 ib[idx+4] = upper_32_bits(offset) & 0xff;
dd220a00
MO		 2594 } else {
2595 /* DST is a reg. */
2596 reg = radeon_get_ib_value(p, idx+3) << 2;
2597 if (!evergreen_is_safe_reg(p, reg, idx+3))
2598 return -EINVAL;
2599 }
2600 break;
cb5fcbd5
AD		 2601 case PACKET3_NOP:
2602 break;
2603 default:
2604 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
2605 return -EINVAL;
2606 }
2607 return 0;
2608}
2609
2610int evergreen_cs_parse(struct radeon_cs_parser *p)
2611{
2612 struct radeon_cs_packet pkt;
2613 struct evergreen_cs_track *track;
f3a71df0 2614 u32 tmp;
cb5fcbd5
AD		 2615 int r;
2616
2617 if (p->track == NULL) {
2618 /* initialize tracker, we are in kms */
2619 track = kzalloc(sizeof(*track), GFP_KERNEL);
2620 if (track == NULL)
2621 return -ENOMEM;
2622 evergreen_cs_track_init(track);
f3a71df0
AD		 2623 if (p->rdev->family >= CHIP_CAYMAN)
2624 tmp = p->rdev->config.cayman.tile_config;
2625 else
2626 tmp = p->rdev->config.evergreen.tile_config;
2627
2628 switch (tmp & 0xf) {
2629 case 0:
2630 track->npipes = 1;
2631 break;
2632 case 1:
2633 default:
2634 track->npipes = 2;
2635 break;
2636 case 2:
2637 track->npipes = 4;
2638 break;
2639 case 3:
2640 track->npipes = 8;
2641 break;
2642 }
2643
2644 switch ((tmp & 0xf0) >> 4) {
2645 case 0:
2646 track->nbanks = 4;
2647 break;
2648 case 1:
2649 default:
2650 track->nbanks = 8;
2651 break;
2652 case 2:
2653 track->nbanks = 16;
2654 break;
2655 }
2656
2657 switch ((tmp & 0xf00) >> 8) {
2658 case 0:
2659 track->group_size = 256;
2660 break;
2661 case 1:
2662 default:
2663 track->group_size = 512;
2664 break;
2665 }
2666
2667 switch ((tmp & 0xf000) >> 12) {
2668 case 0:
2669 track->row_size = 1;
2670 break;
2671 case 1:
2672 default:
2673 track->row_size = 2;
2674 break;
2675 case 2:
2676 track->row_size = 4;
2677 break;
2678 }
2679
cb5fcbd5
AD		 2680 p->track = track;
2681 }
2682 do {
c38f34b5 2683 r = radeon_cs_packet_parse(p, &pkt, p->idx);
cb5fcbd5
AD		 2684 if (r) {
2685 kfree(p->track);
2686 p->track = NULL;
2687 return r;
2688 }
2689 p->idx += pkt.count + 2;
2690 switch (pkt.type) {
2691 case PACKET_TYPE0:
2692 r = evergreen_cs_parse_packet0(p, &pkt);
2693 break;
2694 case PACKET_TYPE2:
2695 break;
2696 case PACKET_TYPE3:
2697 r = evergreen_packet3_check(p, &pkt);
2698 break;
2699 default:
2700 DRM_ERROR("Unknown packet type %d !\n", pkt.type);
2701 kfree(p->track);
2702 p->track = NULL;
2703 return -EINVAL;
2704 }
2705 if (r) {
2706 kfree(p->track);
2707 p->track = NULL;
2708 return r;
2709 }
2710 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
2711#if 0
f2e39221
JG		 2712 for (r = 0; r < p->ib.length_dw; r++) {
2713 printk(KERN_INFO "%05d 0x%08X\n", r, p->ib.ptr[r]);
cb5fcbd5
AD		 2714 mdelay(1);
2715 }
2716#endif
2717 kfree(p->track);
2718 p->track = NULL;
2719 return 0;
2720}
2721
d2ead3ea
AD		 2722/*
2723 * DMA
2724 */
2725
2726#define GET_DMA_CMD(h) (((h) & 0xf0000000) >> 28)
2727#define GET_DMA_COUNT(h) ((h) & 0x000fffff)
2728#define GET_DMA_T(h) (((h) & 0x00800000) >> 23)
2729#define GET_DMA_NEW(h) (((h) & 0x04000000) >> 26)
2730#define GET_DMA_MISC(h) (((h) & 0x0700000) >> 20)
2731
2732/**
2733 * evergreen_dma_cs_parse() - parse the DMA IB
2734 * @p: parser structure holding parsing context.
2735 *
2736 * Parses the DMA IB from the CS ioctl and updates
2737 * the GPU addresses based on the reloc information and
2738 * checks for errors. (Evergreen-Cayman)
2739 * Returns 0 for success and an error on failure.
2740 **/
2741int evergreen_dma_cs_parse(struct radeon_cs_parser *p)
2742{
2743 struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
2744 struct radeon_cs_reloc *src_reloc, *dst_reloc, *dst2_reloc;
2745 u32 header, cmd, count, tiled, new_cmd, misc;
2746 volatile u32 *ib = p->ib.ptr;
2747 u32 idx, idx_value;
2748 u64 src_offset, dst_offset, dst2_offset;
2749 int r;
2750
2751 do {
2752 if (p->idx >= ib_chunk->length_dw) {
2753 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
2754 p->idx, ib_chunk->length_dw);
2755 return -EINVAL;
2756 }
2757 idx = p->idx;
2758 header = radeon_get_ib_value(p, idx);
2759 cmd = GET_DMA_CMD(header);
2760 count = GET_DMA_COUNT(header);
2761 tiled = GET_DMA_T(header);
2762 new_cmd = GET_DMA_NEW(header);
2763 misc = GET_DMA_MISC(header);
2764
2765 switch (cmd) {
2766 case DMA_PACKET_WRITE:
2767 r = r600_dma_cs_next_reloc(p, &dst_reloc);
2768 if (r) {
2769 DRM_ERROR("bad DMA_PACKET_WRITE\n");
2770 return -EINVAL;
2771 }
2772 if (tiled) {
2773 dst_offset = ib[idx+1];
2774 dst_offset <<= 8;
2775
2776 ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8);
2777 p->idx += count + 7;
2778 } else {
2779 dst_offset = ib[idx+1];
2780 dst_offset |= ((u64)(ib[idx+2] & 0xff)) << 32;
2781
2782 ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
2783 ib[idx+2] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
2784 p->idx += count + 3;
2785 }
2786 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
2787 dev_warn(p->dev, "DMA write buffer too small (%llu %lu)\n",
2788 dst_offset, radeon_bo_size(dst_reloc->robj));
2789 return -EINVAL;
2790 }
2791 break;
2792 case DMA_PACKET_COPY:
2793 r = r600_dma_cs_next_reloc(p, &src_reloc);
2794 if (r) {
2795 DRM_ERROR("bad DMA_PACKET_COPY\n");
2796 return -EINVAL;
2797 }
2798 r = r600_dma_cs_next_reloc(p, &dst_reloc);
2799 if (r) {
2800 DRM_ERROR("bad DMA_PACKET_COPY\n");
2801 return -EINVAL;
2802 }
2803 if (tiled) {
2804 idx_value = radeon_get_ib_value(p, idx + 2);
2805 if (new_cmd) {
2806 switch (misc) {
2807 case 0:
2808 /* L2T, frame to fields */
2809 if (idx_value & (1 << 31)) {
2810 DRM_ERROR("bad L2T, frame to fields DMA_PACKET_COPY\n");
2811 return -EINVAL;
2812 }
2813 r = r600_dma_cs_next_reloc(p, &dst2_reloc);
2814 if (r) {
2815 DRM_ERROR("bad L2T, frame to fields DMA_PACKET_COPY\n");
2816 return -EINVAL;
2817 }
2818 dst_offset = ib[idx+1];
2819 dst_offset <<= 8;
2820 dst2_offset = ib[idx+2];
2821 dst2_offset <<= 8;
2822 src_offset = ib[idx+8];
2823 src_offset |= ((u64)(ib[idx+9] & 0xff)) << 32;
2824 if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {
2825 dev_warn(p->dev, "DMA L2T, frame to fields src buffer too small (%llu %lu)\n",
2826 src_offset + (count * 4), radeon_bo_size(src_reloc->robj));
2827 return -EINVAL;
2828 }
2829 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
2830 dev_warn(p->dev, "DMA L2T, frame to fields buffer too small (%llu %lu)\n",
2831 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
2832 return -EINVAL;
2833 }
2834 if ((dst2_offset + (count * 4)) > radeon_bo_size(dst2_reloc->robj)) {
2835 dev_warn(p->dev, "DMA L2T, frame to fields buffer too small (%llu %lu)\n",
2836 dst2_offset + (count * 4), radeon_bo_size(dst2_reloc->robj));
2837 return -EINVAL;
2838 }
2839 ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8);
2840 ib[idx+2] += (u32)(dst2_reloc->lobj.gpu_offset >> 8);
2841 ib[idx+8] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
2842 ib[idx+9] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
2843 p->idx += 10;
2844 break;
2845 case 1:
2846 /* L2T, T2L partial */
2847 if (p->family < CHIP_CAYMAN) {
2848 DRM_ERROR("L2T, T2L Partial is cayman only !\n");
2849 return -EINVAL;
2850 }
2851 /* detile bit */
2852 if (idx_value & (1 << 31)) {
2853 /* tiled src, linear dst */
2854 ib[idx+1] += (u32)(src_reloc->lobj.gpu_offset >> 8);
2855
2856 ib[idx+7] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
2857 ib[idx+8] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
2858 } else {
2859 /* linear src, tiled dst */
2860 ib[idx+7] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
2861 ib[idx+8] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
2862
2863 ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8);
2864 }
2865 p->idx += 12;
2866 break;
2867 case 3:
2868 /* L2T, broadcast */
2869 if (idx_value & (1 << 31)) {
2870 DRM_ERROR("bad L2T, broadcast DMA_PACKET_COPY\n");
2871 return -EINVAL;
2872 }
2873 r = r600_dma_cs_next_reloc(p, &dst2_reloc);
2874 if (r) {
2875 DRM_ERROR("bad L2T, broadcast DMA_PACKET_COPY\n");
2876 return -EINVAL;
2877 }
2878 dst_offset = ib[idx+1];
2879 dst_offset <<= 8;
2880 dst2_offset = ib[idx+2];
2881 dst2_offset <<= 8;
2882 src_offset = ib[idx+8];
2883 src_offset |= ((u64)(ib[idx+9] & 0xff)) << 32;
2884 if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {
2885 dev_warn(p->dev, "DMA L2T, broadcast src buffer too small (%llu %lu)\n",
2886 src_offset + (count * 4), radeon_bo_size(src_reloc->robj));
2887 return -EINVAL;
2888 }
2889 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
2890 dev_warn(p->dev, "DMA L2T, broadcast dst buffer too small (%llu %lu)\n",
2891 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
2892 return -EINVAL;
2893 }
2894 if ((dst2_offset + (count * 4)) > radeon_bo_size(dst2_reloc->robj)) {
2895 dev_warn(p->dev, "DMA L2T, broadcast dst2 buffer too small (%llu %lu)\n",
2896 dst2_offset + (count * 4), radeon_bo_size(dst2_reloc->robj));
2897 return -EINVAL;
2898 }
2899 ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8);
2900 ib[idx+2] += (u32)(dst2_reloc->lobj.gpu_offset >> 8);
2901 ib[idx+8] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
2902 ib[idx+9] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
2903 p->idx += 10;
2904 break;
2905 case 4:
2906 /* L2T, T2L */
2907 /* detile bit */
2908 if (idx_value & (1 << 31)) {
2909 /* tiled src, linear dst */
2910 src_offset = ib[idx+1];
2911 src_offset <<= 8;
2912 ib[idx+1] += (u32)(src_reloc->lobj.gpu_offset >> 8);
2913
2914 dst_offset = ib[idx+7];
2915 dst_offset |= ((u64)(ib[idx+8] & 0xff)) << 32;
2916 ib[idx+7] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
2917 ib[idx+8] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
2918 } else {
2919 /* linear src, tiled dst */
2920 src_offset = ib[idx+7];
2921 src_offset |= ((u64)(ib[idx+8] & 0xff)) << 32;
2922 ib[idx+7] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
2923 ib[idx+8] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
2924
2925 dst_offset = ib[idx+1];
2926 dst_offset <<= 8;
2927 ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8);
2928 }
2929 if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {
2930 dev_warn(p->dev, "DMA L2T, T2L src buffer too small (%llu %lu)\n",
2931 src_offset + (count * 4), radeon_bo_size(src_reloc->robj));
2932 return -EINVAL;
2933 }
2934 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
2935 dev_warn(p->dev, "DMA L2T, T2L dst buffer too small (%llu %lu)\n",
2936 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
2937 return -EINVAL;
2938 }
2939 p->idx += 9;
2940 break;
2941 case 5:
2942 /* T2T partial */
2943 if (p->family < CHIP_CAYMAN) {
2944 DRM_ERROR("L2T, T2L Partial is cayman only !\n");
2945 return -EINVAL;
2946 }
2947 ib[idx+1] += (u32)(src_reloc->lobj.gpu_offset >> 8);
2948 ib[idx+4] += (u32)(dst_reloc->lobj.gpu_offset >> 8);
2949 p->idx += 13;
2950 break;
2951 case 7:
2952 /* L2T, broadcast */
2953 if (idx_value & (1 << 31)) {
2954 DRM_ERROR("bad L2T, broadcast DMA_PACKET_COPY\n");
2955 return -EINVAL;
2956 }
2957 r = r600_dma_cs_next_reloc(p, &dst2_reloc);
2958 if (r) {
2959 DRM_ERROR("bad L2T, broadcast DMA_PACKET_COPY\n");
2960 return -EINVAL;
2961 }
2962 dst_offset = ib[idx+1];
2963 dst_offset <<= 8;
2964 dst2_offset = ib[idx+2];
2965 dst2_offset <<= 8;
2966 src_offset = ib[idx+8];
2967 src_offset |= ((u64)(ib[idx+9] & 0xff)) << 32;
2968 if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {
2969 dev_warn(p->dev, "DMA L2T, broadcast src buffer too small (%llu %lu)\n",
2970 src_offset + (count * 4), radeon_bo_size(src_reloc->robj));
2971 return -EINVAL;
2972 }
2973 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
2974 dev_warn(p->dev, "DMA L2T, broadcast dst buffer too small (%llu %lu)\n",
2975 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
2976 return -EINVAL;
2977 }
2978 if ((dst2_offset + (count * 4)) > radeon_bo_size(dst2_reloc->robj)) {
2979 dev_warn(p->dev, "DMA L2T, broadcast dst2 buffer too small (%llu %lu)\n",
2980 dst2_offset + (count * 4), radeon_bo_size(dst2_reloc->robj));
2981 return -EINVAL;
2982 }
2983 ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8);
2984 ib[idx+2] += (u32)(dst2_reloc->lobj.gpu_offset >> 8);
2985 ib[idx+8] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
2986 ib[idx+9] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
2987 p->idx += 10;
2988 break;
2989 default:
2990 DRM_ERROR("bad DMA_PACKET_COPY misc %u\n", misc);
2991 return -EINVAL;
2992 }
2993 } else {
2994 switch (misc) {
2995 case 0:
2996 /* detile bit */
2997 if (idx_value & (1 << 31)) {
2998 /* tiled src, linear dst */
2999 src_offset = ib[idx+1];
3000 src_offset <<= 8;
3001 ib[idx+1] += (u32)(src_reloc->lobj.gpu_offset >> 8);
3002
3003 dst_offset = ib[idx+7];
3004 dst_offset |= ((u64)(ib[idx+8] & 0xff)) << 32;
3005 ib[idx+7] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
3006 ib[idx+8] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
3007 } else {
3008 /* linear src, tiled dst */
3009 src_offset = ib[idx+7];
3010 src_offset |= ((u64)(ib[idx+8] & 0xff)) << 32;
3011 ib[idx+7] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
3012 ib[idx+8] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
3013
3014 dst_offset = ib[idx+1];
3015 dst_offset <<= 8;
3016 ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8);
3017 }
3018 if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {
3019 dev_warn(p->dev, "DMA L2T, broadcast src buffer too small (%llu %lu)\n",
3020 src_offset + (count * 4), radeon_bo_size(src_reloc->robj));
3021 return -EINVAL;
3022 }
3023 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
3024 dev_warn(p->dev, "DMA L2T, broadcast dst buffer too small (%llu %lu)\n",
3025 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
3026 return -EINVAL;
3027 }
3028 p->idx += 9;
3029 break;
3030 default:
3031 DRM_ERROR("bad DMA_PACKET_COPY misc %u\n", misc);
3032 return -EINVAL;
3033 }
3034 }
3035 } else {
3036 if (new_cmd) {
3037 switch (misc) {
3038 case 0:
3039 /* L2L, byte */
3040 src_offset = ib[idx+2];
3041 src_offset |= ((u64)(ib[idx+4] & 0xff)) << 32;
3042 dst_offset = ib[idx+1];
3043 dst_offset |= ((u64)(ib[idx+3] & 0xff)) << 32;
3044 if ((src_offset + count) > radeon_bo_size(src_reloc->robj)) {
3045 dev_warn(p->dev, "DMA L2L, byte src buffer too small (%llu %lu)\n",
3046 src_offset + count, radeon_bo_size(src_reloc->robj));
3047 return -EINVAL;
3048 }
3049 if ((dst_offset + count) > radeon_bo_size(dst_reloc->robj)) {
3050 dev_warn(p->dev, "DMA L2L, byte dst buffer too small (%llu %lu)\n",
3051 dst_offset + count, radeon_bo_size(dst_reloc->robj));
3052 return -EINVAL;
3053 }
3054 ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xffffffff);
3055 ib[idx+2] += (u32)(src_reloc->lobj.gpu_offset & 0xffffffff);
3056 ib[idx+3] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
3057 ib[idx+4] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
3058 p->idx += 5;
3059 break;
3060 case 1:
3061 /* L2L, partial */
3062 if (p->family < CHIP_CAYMAN) {
3063 DRM_ERROR("L2L Partial is cayman only !\n");
3064 return -EINVAL;
3065 }
3066 ib[idx+1] += (u32)(src_reloc->lobj.gpu_offset & 0xffffffff);
3067 ib[idx+2] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
3068 ib[idx+4] += (u32)(dst_reloc->lobj.gpu_offset & 0xffffffff);
3069 ib[idx+5] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
3070
3071 p->idx += 9;
3072 break;
3073 case 4:
3074 /* L2L, dw, broadcast */
3075 r = r600_dma_cs_next_reloc(p, &dst2_reloc);
3076 if (r) {
3077 DRM_ERROR("bad L2L, dw, broadcast DMA_PACKET_COPY\n");
3078 return -EINVAL;
3079 }
3080 dst_offset = ib[idx+1];
3081 dst_offset |= ((u64)(ib[idx+4] & 0xff)) << 32;
3082 dst2_offset = ib[idx+2];
3083 dst2_offset |= ((u64)(ib[idx+5] & 0xff)) << 32;
3084 src_offset = ib[idx+3];
3085 src_offset |= ((u64)(ib[idx+6] & 0xff)) << 32;
3086 if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {
3087 dev_warn(p->dev, "DMA L2L, dw, broadcast src buffer too small (%llu %lu)\n",
3088 src_offset + (count * 4), radeon_bo_size(src_reloc->robj));
3089 return -EINVAL;
3090 }
3091 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
3092 dev_warn(p->dev, "DMA L2L, dw, broadcast dst buffer too small (%llu %lu)\n",
3093 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
3094 return -EINVAL;
3095 }
3096 if ((dst2_offset + (count * 4)) > radeon_bo_size(dst2_reloc->robj)) {
3097 dev_warn(p->dev, "DMA L2L, dw, broadcast dst2 buffer too small (%llu %lu)\n",
3098 dst2_offset + (count * 4), radeon_bo_size(dst2_reloc->robj));
3099 return -EINVAL;
3100 }
3101 ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
3102 ib[idx+2] += (u32)(dst2_reloc->lobj.gpu_offset & 0xfffffffc);
3103 ib[idx+3] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
3104 ib[idx+4] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
3105 ib[idx+5] += upper_32_bits(dst2_reloc->lobj.gpu_offset) & 0xff;
3106 ib[idx+6] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
3107 p->idx += 7;
3108 break;
3109 default:
3110 DRM_ERROR("bad DMA_PACKET_COPY misc %u\n", misc);
3111 return -EINVAL;
3112 }
3113 } else {
3114 /* L2L, dw */
3115 src_offset = ib[idx+2];
3116 src_offset |= ((u64)(ib[idx+4] & 0xff)) << 32;
3117 dst_offset = ib[idx+1];
3118 dst_offset |= ((u64)(ib[idx+3] & 0xff)) << 32;
3119 if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {
3120 dev_warn(p->dev, "DMA L2L, dw src buffer too small (%llu %lu)\n",
3121 src_offset + (count * 4), radeon_bo_size(src_reloc->robj));
3122 return -EINVAL;
3123 }
3124 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
3125 dev_warn(p->dev, "DMA L2L, dw dst buffer too small (%llu %lu)\n",
3126 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
3127 return -EINVAL;
3128 }
3129 ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
3130 ib[idx+2] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
3131 ib[idx+3] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
3132 ib[idx+4] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
3133 p->idx += 5;
3134 }
3135 }
3136 break;
3137 case DMA_PACKET_CONSTANT_FILL:
3138 r = r600_dma_cs_next_reloc(p, &dst_reloc);
3139 if (r) {
3140 DRM_ERROR("bad DMA_PACKET_CONSTANT_FILL\n");
3141 return -EINVAL;
3142 }
3143 dst_offset = ib[idx+1];
3144 dst_offset |= ((u64)(ib[idx+3] & 0x00ff0000)) << 16;
3145 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
3146 dev_warn(p->dev, "DMA constant fill buffer too small (%llu %lu)\n",
3147 dst_offset, radeon_bo_size(dst_reloc->robj));
3148 return -EINVAL;
3149 }
3150 ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
3151 ib[idx+3] += (upper_32_bits(dst_reloc->lobj.gpu_offset) << 16) & 0x00ff0000;
3152 p->idx += 4;
3153 break;
3154 case DMA_PACKET_NOP:
3155 p->idx += 1;
3156 break;
3157 default:
3158 DRM_ERROR("Unknown packet type %d at %d !\n", cmd, idx);
3159 return -EINVAL;
3160 }
3161 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
3162#if 0
3163 for (r = 0; r < p->ib->length_dw; r++) {
3164 printk(KERN_INFO "%05d 0x%08X\n", r, p->ib.ptr[r]);
3165 mdelay(1);
3166 }
3167#endif
3168 return 0;
3169}
3170
721604a1
JG		 3171/* vm parser */
3172static bool evergreen_vm_reg_valid(u32 reg)
3173{
3174 /* context regs are fine */
3175 if (reg >= 0x28000)
3176 return true;
3177
3178 /* check config regs */
3179 switch (reg) {
668bbc81 3180 case WAIT_UNTIL:
721604a1 3181 case GRBM_GFX_INDEX:
860fe2f0
AD		 3182 case CP_STRMOUT_CNTL:
3183 case CP_COHER_CNTL:
3184 case CP_COHER_SIZE:
721604a1
JG		 3185 case VGT_VTX_VECT_EJECT_REG:
3186 case VGT_CACHE_INVALIDATION:
3187 case VGT_GS_VERTEX_REUSE:
3188 case VGT_PRIMITIVE_TYPE:
3189 case VGT_INDEX_TYPE:
3190 case VGT_NUM_INDICES:
3191 case VGT_NUM_INSTANCES:
3192 case VGT_COMPUTE_DIM_X:
3193 case VGT_COMPUTE_DIM_Y:
3194 case VGT_COMPUTE_DIM_Z:
3195 case VGT_COMPUTE_START_X:
3196 case VGT_COMPUTE_START_Y:
3197 case VGT_COMPUTE_START_Z:
3198 case VGT_COMPUTE_INDEX:
3199 case VGT_COMPUTE_THREAD_GROUP_SIZE:
3200 case VGT_HS_OFFCHIP_PARAM:
3201 case PA_CL_ENHANCE:
3202 case PA_SU_LINE_STIPPLE_VALUE:
3203 case PA_SC_LINE_STIPPLE_STATE:
3204 case PA_SC_ENHANCE:
3205 case SQ_DYN_GPR_CNTL_PS_FLUSH_REQ:
3206 case SQ_DYN_GPR_SIMD_LOCK_EN:
3207 case SQ_CONFIG:
3208 case SQ_GPR_RESOURCE_MGMT_1:
3209 case SQ_GLOBAL_GPR_RESOURCE_MGMT_1:
3210 case SQ_GLOBAL_GPR_RESOURCE_MGMT_2:
3211 case SQ_CONST_MEM_BASE:
3212 case SQ_STATIC_THREAD_MGMT_1:
3213 case SQ_STATIC_THREAD_MGMT_2:
3214 case SQ_STATIC_THREAD_MGMT_3:
3215 case SPI_CONFIG_CNTL:
3216 case SPI_CONFIG_CNTL_1:
3217 case TA_CNTL_AUX:
3218 case DB_DEBUG:
3219 case DB_DEBUG2:
3220 case DB_DEBUG3:
3221 case DB_DEBUG4:
3222 case DB_WATERMARKS:
3223 case TD_PS_BORDER_COLOR_INDEX:
3224 case TD_PS_BORDER_COLOR_RED:
3225 case TD_PS_BORDER_COLOR_GREEN:
3226 case TD_PS_BORDER_COLOR_BLUE:
3227 case TD_PS_BORDER_COLOR_ALPHA:
3228 case TD_VS_BORDER_COLOR_INDEX:
3229 case TD_VS_BORDER_COLOR_RED:
3230 case TD_VS_BORDER_COLOR_GREEN:
3231 case TD_VS_BORDER_COLOR_BLUE:
3232 case TD_VS_BORDER_COLOR_ALPHA:
3233 case TD_GS_BORDER_COLOR_INDEX:
3234 case TD_GS_BORDER_COLOR_RED:
3235 case TD_GS_BORDER_COLOR_GREEN:
3236 case TD_GS_BORDER_COLOR_BLUE:
3237 case TD_GS_BORDER_COLOR_ALPHA:
3238 case TD_HS_BORDER_COLOR_INDEX:
3239 case TD_HS_BORDER_COLOR_RED:
3240 case TD_HS_BORDER_COLOR_GREEN:
3241 case TD_HS_BORDER_COLOR_BLUE:
3242 case TD_HS_BORDER_COLOR_ALPHA:
3243 case TD_LS_BORDER_COLOR_INDEX:
3244 case TD_LS_BORDER_COLOR_RED:
3245 case TD_LS_BORDER_COLOR_GREEN:
3246 case TD_LS_BORDER_COLOR_BLUE:
3247 case TD_LS_BORDER_COLOR_ALPHA:
3248 case TD_CS_BORDER_COLOR_INDEX:
3249 case TD_CS_BORDER_COLOR_RED:
3250 case TD_CS_BORDER_COLOR_GREEN:
3251 case TD_CS_BORDER_COLOR_BLUE:
3252 case TD_CS_BORDER_COLOR_ALPHA:
3253 case SQ_ESGS_RING_SIZE:
3254 case SQ_GSVS_RING_SIZE:
3255 case SQ_ESTMP_RING_SIZE:
3256 case SQ_GSTMP_RING_SIZE:
3257 case SQ_HSTMP_RING_SIZE:
3258 case SQ_LSTMP_RING_SIZE:
3259 case SQ_PSTMP_RING_SIZE:
3260 case SQ_VSTMP_RING_SIZE:
3261 case SQ_ESGS_RING_ITEMSIZE:
3262 case SQ_ESTMP_RING_ITEMSIZE:
3263 case SQ_GSTMP_RING_ITEMSIZE:
3264 case SQ_GSVS_RING_ITEMSIZE:
3265 case SQ_GS_VERT_ITEMSIZE:
3266 case SQ_GS_VERT_ITEMSIZE_1:
3267 case SQ_GS_VERT_ITEMSIZE_2:
3268 case SQ_GS_VERT_ITEMSIZE_3:
3269 case SQ_GSVS_RING_OFFSET_1:
3270 case SQ_GSVS_RING_OFFSET_2:
3271 case SQ_GSVS_RING_OFFSET_3:
3272 case SQ_HSTMP_RING_ITEMSIZE:
3273 case SQ_LSTMP_RING_ITEMSIZE:
3274 case SQ_PSTMP_RING_ITEMSIZE:
3275 case SQ_VSTMP_RING_ITEMSIZE:
3276 case VGT_TF_RING_SIZE:
3277 case SQ_ESGS_RING_BASE:
3278 case SQ_GSVS_RING_BASE:
3279 case SQ_ESTMP_RING_BASE:
3280 case SQ_GSTMP_RING_BASE:
3281 case SQ_HSTMP_RING_BASE:
3282 case SQ_LSTMP_RING_BASE:
3283 case SQ_PSTMP_RING_BASE:
3284 case SQ_VSTMP_RING_BASE:
3285 case CAYMAN_VGT_OFFCHIP_LDS_BASE:
3286 case CAYMAN_SQ_EX_ALLOC_TABLE_SLOTS:
3287 return true;
3288 default:
c7172132 3289 DRM_ERROR("Invalid register 0x%x in CS\n", reg);
721604a1
JG		 3290 return false;
3291 }
3292}
3293
3294static int evergreen_vm_packet3_check(struct radeon_device *rdev,
3295 u32 *ib, struct radeon_cs_packet *pkt)
3296{
3297 u32 idx = pkt->idx + 1;
3298 u32 idx_value = ib[idx];
3299 u32 start_reg, end_reg, reg, i;
94e014ee 3300 u32 command, info;
721604a1
JG		 3301
3302 switch (pkt->opcode) {
3303 case PACKET3_NOP:
3304 case PACKET3_SET_BASE:
3305 case PACKET3_CLEAR_STATE:
3306 case PACKET3_INDEX_BUFFER_SIZE:
3307 case PACKET3_DISPATCH_DIRECT:
3308 case PACKET3_DISPATCH_INDIRECT:
3309 case PACKET3_MODE_CONTROL:
3310 case PACKET3_SET_PREDICATION:
3311 case PACKET3_COND_EXEC:
3312 case PACKET3_PRED_EXEC:
3313 case PACKET3_DRAW_INDIRECT:
3314 case PACKET3_DRAW_INDEX_INDIRECT:
3315 case PACKET3_INDEX_BASE:
3316 case PACKET3_DRAW_INDEX_2:
3317 case PACKET3_CONTEXT_CONTROL:
3318 case PACKET3_DRAW_INDEX_OFFSET:
3319 case PACKET3_INDEX_TYPE:
3320 case PACKET3_DRAW_INDEX:
3321 case PACKET3_DRAW_INDEX_AUTO:
3322 case PACKET3_DRAW_INDEX_IMMD:
3323 case PACKET3_NUM_INSTANCES:
3324 case PACKET3_DRAW_INDEX_MULTI_AUTO:
3325 case PACKET3_STRMOUT_BUFFER_UPDATE:
3326 case PACKET3_DRAW_INDEX_OFFSET_2:
3327 case PACKET3_DRAW_INDEX_MULTI_ELEMENT:
3328 case PACKET3_MPEG_INDEX:
3329 case PACKET3_WAIT_REG_MEM:
3330 case PACKET3_MEM_WRITE:
3331 case PACKET3_SURFACE_SYNC:
3332 case PACKET3_EVENT_WRITE:
3333 case PACKET3_EVENT_WRITE_EOP:
3334 case PACKET3_EVENT_WRITE_EOS:
3335 case PACKET3_SET_CONTEXT_REG:
3336 case PACKET3_SET_BOOL_CONST:
3337 case PACKET3_SET_LOOP_CONST:
3338 case PACKET3_SET_RESOURCE:
3339 case PACKET3_SET_SAMPLER:
3340 case PACKET3_SET_CTL_CONST:
3341 case PACKET3_SET_RESOURCE_OFFSET:
3342 case PACKET3_SET_CONTEXT_REG_INDIRECT:
3343 case PACKET3_SET_RESOURCE_INDIRECT:
3344 case CAYMAN_PACKET3_DEALLOC_STATE:
3345 break;
3346 case PACKET3_COND_WRITE:
3347 if (idx_value & 0x100) {
3348 reg = ib[idx + 5] * 4;
3349 if (!evergreen_vm_reg_valid(reg))
3350 return -EINVAL;
3351 }
3352 break;
3353 case PACKET3_COPY_DW:
3354 if (idx_value & 0x2) {
3355 reg = ib[idx + 3] * 4;
3356 if (!evergreen_vm_reg_valid(reg))
3357 return -EINVAL;
3358 }
3359 break;
3360 case PACKET3_SET_CONFIG_REG:
3361 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_START;
3362 end_reg = 4 * pkt->count + start_reg - 4;
3363 if ((start_reg < PACKET3_SET_CONFIG_REG_START) ||
3364 (start_reg >= PACKET3_SET_CONFIG_REG_END) ||
3365 (end_reg >= PACKET3_SET_CONFIG_REG_END)) {
3366 DRM_ERROR("bad PACKET3_SET_CONFIG_REG\n");
3367 return -EINVAL;
3368 }
3369 for (i = 0; i < pkt->count; i++) {
3370 reg = start_reg + (4 * i);
3371 if (!evergreen_vm_reg_valid(reg))
3372 return -EINVAL;
3373 }
3374 break;
94e014ee
AD		 3375 case PACKET3_CP_DMA:
3376 command = ib[idx + 4];
3377 info = ib[idx + 1];
9d89d78e
AD		 3378 if ((((info & 0x60000000) >> 29) != 0) || /* src = GDS or DATA */
3379 (((info & 0x00300000) >> 20) != 0) || /* dst = GDS */
3380 ((((info & 0x00300000) >> 20) == 0) &&
3381 (command & PACKET3_CP_DMA_CMD_DAS)) || /* dst = register */
3382 ((((info & 0x60000000) >> 29) == 0) &&
3383 (command & PACKET3_CP_DMA_CMD_SAS))) { /* src = register */
3384 /* non mem to mem copies requires dw aligned count */
3385 if ((command & 0x1fffff) % 4) {
3386 DRM_ERROR("CP DMA command requires dw count alignment\n");
3387 return -EINVAL;
3388 }
3389 }
94e014ee
AD		 3390 if (command & PACKET3_CP_DMA_CMD_SAS) {
3391 /* src address space is register */
3392 if (((info & 0x60000000) >> 29) == 0) {
3393 start_reg = idx_value << 2;
3394 if (command & PACKET3_CP_DMA_CMD_SAIC) {
3395 reg = start_reg;
3396 if (!evergreen_vm_reg_valid(reg)) {
3397 DRM_ERROR("CP DMA Bad SRC register\n");
3398 return -EINVAL;
3399 }
3400 } else {
3401 for (i = 0; i < (command & 0x1fffff); i++) {
3402 reg = start_reg + (4 * i);
3403 if (!evergreen_vm_reg_valid(reg)) {
3404 DRM_ERROR("CP DMA Bad SRC register\n");
3405 return -EINVAL;
3406 }
3407 }
3408 }
3409 }
3410 }
3411 if (command & PACKET3_CP_DMA_CMD_DAS) {
3412 /* dst address space is register */
3413 if (((info & 0x00300000) >> 20) == 0) {
3414 start_reg = ib[idx + 2];
3415 if (command & PACKET3_CP_DMA_CMD_DAIC) {
3416 reg = start_reg;
3417 if (!evergreen_vm_reg_valid(reg)) {
3418 DRM_ERROR("CP DMA Bad DST register\n");
3419 return -EINVAL;
3420 }
3421 } else {
3422 for (i = 0; i < (command & 0x1fffff); i++) {
3423 reg = start_reg + (4 * i);
3424 if (!evergreen_vm_reg_valid(reg)) {
3425 DRM_ERROR("CP DMA Bad DST register\n");
3426 return -EINVAL;
3427 }
3428 }
3429 }
3430 }
3431 }
3432 break;
721604a1
JG		 3433 default:
3434 return -EINVAL;
3435 }
3436 return 0;
3437}
3438
3439int evergreen_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib)
3440{
3441 int ret = 0;
3442 u32 idx = 0;
3443 struct radeon_cs_packet pkt;
3444
3445 do {
3446 pkt.idx = idx;
3447 pkt.type = CP_PACKET_GET_TYPE(ib->ptr[idx]);
3448 pkt.count = CP_PACKET_GET_COUNT(ib->ptr[idx]);
3449 pkt.one_reg_wr = 0;
3450 switch (pkt.type) {
3451 case PACKET_TYPE0:
3452 dev_err(rdev->dev, "Packet0 not allowed!\n");
3453 ret = -EINVAL;
3454 break;
3455 case PACKET_TYPE2:
0b41da60 3456 idx += 1;
721604a1
JG		 3457 break;
3458 case PACKET_TYPE3:
3459 pkt.opcode = CP_PACKET3_GET_OPCODE(ib->ptr[idx]);
3460 ret = evergreen_vm_packet3_check(rdev, ib->ptr, &pkt);
0b41da60 3461 idx += pkt.count + 2;
721604a1
JG		 3462 break;
3463 default:
3464 dev_err(rdev->dev, "Unknown packet type %d !\n", pkt.type);
3465 ret = -EINVAL;
3466 break;
3467 }
3468 if (ret)
3469 break;
721604a1
JG		 3470 } while (idx < ib->length_dw);
3471
3472 return ret;
3473}
cd459e52
AD		 3474
3475/**
3476 * evergreen_dma_ib_parse() - parse the DMA IB for VM
3477 * @rdev: radeon_device pointer
3478 * @ib: radeon_ib pointer
3479 *
3480 * Parses the DMA IB from the VM CS ioctl
3481 * checks for errors. (Cayman-SI)
3482 * Returns 0 for success and an error on failure.
3483 **/
3484int evergreen_dma_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib)
3485{
3486 u32 idx = 0;
3487 u32 header, cmd, count, tiled, new_cmd, misc;
3488
3489 do {
3490 header = ib->ptr[idx];
3491 cmd = GET_DMA_CMD(header);
3492 count = GET_DMA_COUNT(header);
3493 tiled = GET_DMA_T(header);
3494 new_cmd = GET_DMA_NEW(header);
3495 misc = GET_DMA_MISC(header);
3496
3497 switch (cmd) {
3498 case DMA_PACKET_WRITE:
3499 if (tiled)
3500 idx += count + 7;
3501 else
3502 idx += count + 3;
3503 break;
3504 case DMA_PACKET_COPY:
3505 if (tiled) {
3506 if (new_cmd) {
3507 switch (misc) {
3508 case 0:
3509 /* L2T, frame to fields */
3510 idx += 10;
3511 break;
3512 case 1:
3513 /* L2T, T2L partial */
3514 idx += 12;
3515 break;
3516 case 3:
3517 /* L2T, broadcast */
3518 idx += 10;
3519 break;
3520 case 4:
3521 /* L2T, T2L */
3522 idx += 9;
3523 break;
3524 case 5:
3525 /* T2T partial */
3526 idx += 13;
3527 break;
3528 case 7:
3529 /* L2T, broadcast */
3530 idx += 10;
3531 break;
3532 default:
3533 DRM_ERROR("bad DMA_PACKET_COPY misc %u\n", misc);
3534 return -EINVAL;
3535 }
3536 } else {
3537 switch (misc) {
3538 case 0:
3539 idx += 9;
3540 break;
3541 default:
3542 DRM_ERROR("bad DMA_PACKET_COPY misc %u\n", misc);
3543 return -EINVAL;
3544 }
3545 }
3546 } else {
3547 if (new_cmd) {
3548 switch (misc) {
3549 case 0:
3550 /* L2L, byte */
3551 idx += 5;
3552 break;
3553 case 1:
3554 /* L2L, partial */
3555 idx += 9;
3556 break;
3557 case 4:
3558 /* L2L, dw, broadcast */
3559 idx += 7;
3560 break;
3561 default:
3562 DRM_ERROR("bad DMA_PACKET_COPY misc %u\n", misc);
3563 return -EINVAL;
3564 }
3565 } else {
3566 /* L2L, dw */
3567 idx += 5;
3568 }
3569 }
3570 break;
3571 case DMA_PACKET_CONSTANT_FILL:
3572 idx += 4;
3573 break;
3574 case DMA_PACKET_NOP:
3575 idx += 1;
3576 break;
3577 default:
3578 DRM_ERROR("Unknown packet type %d at %d !\n", cmd, idx);
3579 return -EINVAL;
3580 }
3581 } while (idx < ib->length_dw);
3582
3583 return 0;
3584}
Linux kernel - Deliverables
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