Commit | Line | Data |
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e55d3e6c RM |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Christian König. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Christian König | |
25 | * Rafał Miłecki | |
26 | */ | |
e3b2e034 | 27 | #include <linux/hdmi.h> |
760285e7 DH |
28 | #include <drm/drmP.h> |
29 | #include <drm/radeon_drm.h> | |
e55d3e6c RM |
30 | #include "radeon.h" |
31 | #include "radeon_asic.h" | |
070a2e63 | 32 | #include "radeon_audio.h" |
e55d3e6c RM |
33 | #include "evergreend.h" |
34 | #include "atom.h" | |
35 | ||
d3d8c141 | 36 | /* enable the audio stream */ |
8bf59820 | 37 | void dce4_audio_enable(struct radeon_device *rdev, |
d3d8c141 AD |
38 | struct r600_audio_pin *pin, |
39 | u8 enable_mask) | |
40 | { | |
41 | u32 tmp = RREG32(AZ_HOT_PLUG_CONTROL); | |
42 | ||
43 | if (!pin) | |
44 | return; | |
45 | ||
46 | if (enable_mask) { | |
47 | tmp |= AUDIO_ENABLED; | |
48 | if (enable_mask & 1) | |
49 | tmp |= PIN0_AUDIO_ENABLED; | |
50 | if (enable_mask & 2) | |
51 | tmp |= PIN1_AUDIO_ENABLED; | |
52 | if (enable_mask & 4) | |
53 | tmp |= PIN2_AUDIO_ENABLED; | |
54 | if (enable_mask & 8) | |
55 | tmp |= PIN3_AUDIO_ENABLED; | |
56 | } else { | |
57 | tmp &= ~(AUDIO_ENABLED | | |
58 | PIN0_AUDIO_ENABLED | | |
59 | PIN1_AUDIO_ENABLED | | |
60 | PIN2_AUDIO_ENABLED | | |
61 | PIN3_AUDIO_ENABLED); | |
62 | } | |
63 | ||
64 | WREG32(AZ_HOT_PLUG_CONTROL, tmp); | |
65 | } | |
66 | ||
e55d3e6c RM |
67 | /* |
68 | * update the N and CTS parameters for a given pixel clock rate | |
69 | */ | |
70 | static void evergreen_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock) | |
71 | { | |
72 | struct drm_device *dev = encoder->dev; | |
73 | struct radeon_device *rdev = dev->dev_private; | |
74 | struct radeon_hdmi_acr acr = r600_hdmi_acr(clock); | |
cfcbd6d3 RM |
75 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
76 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; | |
77 | uint32_t offset = dig->afmt->offset; | |
e55d3e6c RM |
78 | |
79 | WREG32(HDMI_ACR_32_0 + offset, HDMI_ACR_CTS_32(acr.cts_32khz)); | |
80 | WREG32(HDMI_ACR_32_1 + offset, acr.n_32khz); | |
81 | ||
82 | WREG32(HDMI_ACR_44_0 + offset, HDMI_ACR_CTS_44(acr.cts_44_1khz)); | |
83 | WREG32(HDMI_ACR_44_1 + offset, acr.n_44_1khz); | |
84 | ||
85 | WREG32(HDMI_ACR_48_0 + offset, HDMI_ACR_CTS_48(acr.cts_48khz)); | |
86 | WREG32(HDMI_ACR_48_1 + offset, acr.n_48khz); | |
87 | } | |
88 | ||
87654f87 SG |
89 | void dce4_afmt_write_latency_fields(struct drm_encoder *encoder, |
90 | struct drm_connector *connector, struct drm_display_mode *mode) | |
712fd8a2 AD |
91 | { |
92 | struct radeon_device *rdev = encoder->dev->dev_private; | |
712fd8a2 AD |
93 | u32 tmp = 0; |
94 | ||
712fd8a2 AD |
95 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) { |
96 | if (connector->latency_present[1]) | |
97 | tmp = VIDEO_LIPSYNC(connector->video_latency[1]) | | |
98 | AUDIO_LIPSYNC(connector->audio_latency[1]); | |
99 | else | |
100 | tmp = VIDEO_LIPSYNC(255) | AUDIO_LIPSYNC(255); | |
101 | } else { | |
102 | if (connector->latency_present[0]) | |
103 | tmp = VIDEO_LIPSYNC(connector->video_latency[0]) | | |
104 | AUDIO_LIPSYNC(connector->audio_latency[0]); | |
105 | else | |
106 | tmp = VIDEO_LIPSYNC(255) | AUDIO_LIPSYNC(255); | |
107 | } | |
87654f87 | 108 | WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_LIPSYNC, tmp); |
712fd8a2 AD |
109 | } |
110 | ||
00a9d4bc SG |
111 | void dce4_afmt_hdmi_write_speaker_allocation(struct drm_encoder *encoder, |
112 | u8 *sadb, int sad_count) | |
ba7def4f AD |
113 | { |
114 | struct radeon_device *rdev = encoder->dev->dev_private; | |
ba7def4f | 115 | u32 tmp; |
ba7def4f AD |
116 | |
117 | /* program the speaker allocation */ | |
00a9d4bc | 118 | tmp = RREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER); |
ba7def4f AD |
119 | tmp &= ~(DP_CONNECTION | SPEAKER_ALLOCATION_MASK); |
120 | /* set HDMI mode */ | |
121 | tmp |= HDMI_CONNECTION; | |
122 | if (sad_count) | |
123 | tmp |= SPEAKER_ALLOCATION(sadb[0]); | |
124 | else | |
125 | tmp |= SPEAKER_ALLOCATION(5); /* stereo */ | |
00a9d4bc SG |
126 | WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp); |
127 | } | |
ba7def4f | 128 | |
00a9d4bc SG |
129 | void dce4_afmt_dp_write_speaker_allocation(struct drm_encoder *encoder, |
130 | u8 *sadb, int sad_count) | |
131 | { | |
132 | struct radeon_device *rdev = encoder->dev->dev_private; | |
133 | u32 tmp; | |
134 | ||
135 | /* program the speaker allocation */ | |
136 | tmp = RREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER); | |
137 | tmp &= ~(HDMI_CONNECTION | SPEAKER_ALLOCATION_MASK); | |
138 | /* set DP mode */ | |
139 | tmp |= DP_CONNECTION; | |
140 | if (sad_count) | |
141 | tmp |= SPEAKER_ALLOCATION(sadb[0]); | |
142 | else | |
143 | tmp |= SPEAKER_ALLOCATION(5); /* stereo */ | |
144 | WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp); | |
ba7def4f AD |
145 | } |
146 | ||
070a2e63 AD |
147 | void evergreen_hdmi_write_sad_regs(struct drm_encoder *encoder, |
148 | struct cea_sad *sads, int sad_count) | |
46892caa | 149 | { |
070a2e63 | 150 | int i; |
46892caa | 151 | struct radeon_device *rdev = encoder->dev->dev_private; |
46892caa RM |
152 | static const u16 eld_reg_to_type[][2] = { |
153 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM }, | |
154 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 }, | |
155 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 }, | |
156 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 }, | |
157 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 }, | |
158 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC }, | |
159 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS }, | |
160 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC }, | |
161 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 }, | |
162 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD }, | |
163 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP }, | |
164 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO }, | |
165 | }; | |
166 | ||
46892caa RM |
167 | for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) { |
168 | u32 value = 0; | |
0f57bca9 AH |
169 | u8 stereo_freqs = 0; |
170 | int max_channels = -1; | |
46892caa RM |
171 | int j; |
172 | ||
173 | for (j = 0; j < sad_count; j++) { | |
174 | struct cea_sad *sad = &sads[j]; | |
175 | ||
176 | if (sad->format == eld_reg_to_type[i][1]) { | |
0f57bca9 AH |
177 | if (sad->channels > max_channels) { |
178 | value = MAX_CHANNELS(sad->channels) | | |
179 | DESCRIPTOR_BYTE_2(sad->byte2) | | |
180 | SUPPORTED_FREQUENCIES(sad->freq); | |
181 | max_channels = sad->channels; | |
182 | } | |
183 | ||
46892caa | 184 | if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM) |
0f57bca9 AH |
185 | stereo_freqs |= sad->freq; |
186 | else | |
187 | break; | |
46892caa RM |
188 | } |
189 | } | |
0f57bca9 AH |
190 | |
191 | value |= SUPPORTED_FREQUENCIES_STEREO(stereo_freqs); | |
192 | ||
070a2e63 | 193 | WREG32_ENDPOINT(0, eld_reg_to_type[i][0], value); |
46892caa | 194 | } |
46892caa RM |
195 | } |
196 | ||
e55d3e6c RM |
197 | /* |
198 | * build a HDMI Video Info Frame | |
199 | */ | |
e3b2e034 TR |
200 | static void evergreen_hdmi_update_avi_infoframe(struct drm_encoder *encoder, |
201 | void *buffer, size_t size) | |
e55d3e6c RM |
202 | { |
203 | struct drm_device *dev = encoder->dev; | |
204 | struct radeon_device *rdev = dev->dev_private; | |
cfcbd6d3 RM |
205 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
206 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; | |
207 | uint32_t offset = dig->afmt->offset; | |
e3b2e034 | 208 | uint8_t *frame = buffer + 3; |
f100380e | 209 | uint8_t *header = buffer; |
e55d3e6c RM |
210 | |
211 | WREG32(AFMT_AVI_INFO0 + offset, | |
212 | frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24)); | |
213 | WREG32(AFMT_AVI_INFO1 + offset, | |
214 | frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24)); | |
215 | WREG32(AFMT_AVI_INFO2 + offset, | |
216 | frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24)); | |
217 | WREG32(AFMT_AVI_INFO3 + offset, | |
f100380e | 218 | frame[0xC] | (frame[0xD] << 8) | (header[1] << 24)); |
e55d3e6c RM |
219 | } |
220 | ||
b1f6f47e AD |
221 | static void evergreen_audio_set_dto(struct drm_encoder *encoder, u32 clock) |
222 | { | |
223 | struct drm_device *dev = encoder->dev; | |
224 | struct radeon_device *rdev = dev->dev_private; | |
225 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
226 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; | |
227 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); | |
731da21b | 228 | u32 base_rate = 24000; |
1518dd8e AD |
229 | u32 max_ratio = clock / base_rate; |
230 | u32 dto_phase; | |
231 | u32 dto_modulo = clock; | |
232 | u32 wallclock_ratio; | |
233 | u32 dto_cntl; | |
b1f6f47e AD |
234 | |
235 | if (!dig || !dig->afmt) | |
236 | return; | |
237 | ||
b530602f | 238 | if (ASIC_IS_DCE6(rdev)) { |
1518dd8e | 239 | dto_phase = 24 * 1000; |
b530602f AD |
240 | } else { |
241 | if (max_ratio >= 8) { | |
242 | dto_phase = 192 * 1000; | |
243 | wallclock_ratio = 3; | |
244 | } else if (max_ratio >= 4) { | |
245 | dto_phase = 96 * 1000; | |
246 | wallclock_ratio = 2; | |
247 | } else if (max_ratio >= 2) { | |
248 | dto_phase = 48 * 1000; | |
249 | wallclock_ratio = 1; | |
250 | } else { | |
251 | dto_phase = 24 * 1000; | |
252 | wallclock_ratio = 0; | |
253 | } | |
254 | dto_cntl = RREG32(DCCG_AUDIO_DTO0_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK; | |
255 | dto_cntl |= DCCG_AUDIO_DTO_WALLCLOCK_RATIO(wallclock_ratio); | |
256 | WREG32(DCCG_AUDIO_DTO0_CNTL, dto_cntl); | |
1518dd8e | 257 | } |
1518dd8e | 258 | |
b1f6f47e AD |
259 | /* XXX two dtos; generally use dto0 for hdmi */ |
260 | /* Express [24MHz / target pixel clock] as an exact rational | |
261 | * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE | |
262 | * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator | |
263 | */ | |
7d61d835 | 264 | WREG32(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL(radeon_crtc->crtc_id)); |
1518dd8e AD |
265 | WREG32(DCCG_AUDIO_DTO0_PHASE, dto_phase); |
266 | WREG32(DCCG_AUDIO_DTO0_MODULE, dto_modulo); | |
b1f6f47e AD |
267 | } |
268 | ||
269 | ||
e55d3e6c RM |
270 | /* |
271 | * update the info frames with the data from the current display mode | |
272 | */ | |
273 | void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode) | |
274 | { | |
275 | struct drm_device *dev = encoder->dev; | |
276 | struct radeon_device *rdev = dev->dev_private; | |
cfcbd6d3 RM |
277 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
278 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; | |
79766915 | 279 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); |
e3b2e034 TR |
280 | u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE]; |
281 | struct hdmi_avi_infoframe frame; | |
cfcbd6d3 | 282 | uint32_t offset; |
e3b2e034 | 283 | ssize_t err; |
7b555e06 | 284 | uint32_t val; |
79766915 | 285 | int bpc = 8; |
e55d3e6c | 286 | |
c2b4cacf AD |
287 | if (!dig || !dig->afmt) |
288 | return; | |
289 | ||
cfcbd6d3 RM |
290 | /* Silent, r600_hdmi_enable will raise WARN for us */ |
291 | if (!dig->afmt->enabled) | |
e55d3e6c | 292 | return; |
cfcbd6d3 | 293 | offset = dig->afmt->offset; |
e55d3e6c | 294 | |
79766915 AD |
295 | /* hdmi deep color mode general control packets setup, if bpc > 8 */ |
296 | if (encoder->crtc) { | |
297 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); | |
298 | bpc = radeon_crtc->bpc; | |
299 | } | |
300 | ||
832eafaf | 301 | /* disable audio prior to setting up hw */ |
3cdde027 | 302 | dig->afmt->pin = radeon_audio_get_pin(encoder); |
8bf59820 | 303 | radeon_audio_enable(rdev, dig->afmt->pin, 0); |
832eafaf | 304 | |
b1f6f47e | 305 | evergreen_audio_set_dto(encoder, mode->clock); |
e55d3e6c | 306 | |
1c3439f2 RM |
307 | WREG32(HDMI_VBI_PACKET_CONTROL + offset, |
308 | HDMI_NULL_SEND); /* send null packets when required */ | |
309 | ||
e55d3e6c | 310 | WREG32(AFMT_AUDIO_CRC_CONTROL + offset, 0x1000); |
e55d3e6c | 311 | |
7b555e06 AD |
312 | val = RREG32(HDMI_CONTROL + offset); |
313 | val &= ~HDMI_DEEP_COLOR_ENABLE; | |
314 | val &= ~HDMI_DEEP_COLOR_DEPTH_MASK; | |
315 | ||
316 | switch (bpc) { | |
317 | case 0: | |
318 | case 6: | |
319 | case 8: | |
320 | case 16: | |
321 | default: | |
322 | DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n", | |
72082093 | 323 | connector->name, bpc); |
7b555e06 AD |
324 | break; |
325 | case 10: | |
326 | val |= HDMI_DEEP_COLOR_ENABLE; | |
327 | val |= HDMI_DEEP_COLOR_DEPTH(HDMI_30BIT_DEEP_COLOR); | |
328 | DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n", | |
72082093 | 329 | connector->name); |
7b555e06 AD |
330 | break; |
331 | case 12: | |
332 | val |= HDMI_DEEP_COLOR_ENABLE; | |
333 | val |= HDMI_DEEP_COLOR_DEPTH(HDMI_36BIT_DEEP_COLOR); | |
334 | DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n", | |
72082093 | 335 | connector->name); |
7b555e06 AD |
336 | break; |
337 | } | |
338 | ||
339 | WREG32(HDMI_CONTROL + offset, val); | |
340 | ||
1c3439f2 RM |
341 | WREG32(HDMI_VBI_PACKET_CONTROL + offset, |
342 | HDMI_NULL_SEND | /* send null packets when required */ | |
343 | HDMI_GC_SEND | /* send general control packets */ | |
344 | HDMI_GC_CONT); /* send general control packets every frame */ | |
345 | ||
346 | WREG32(HDMI_INFOFRAME_CONTROL0 + offset, | |
1c3439f2 RM |
347 | HDMI_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */ |
348 | HDMI_AUDIO_INFO_CONT); /* required for audio info values to be updated */ | |
e55d3e6c | 349 | |
1c3439f2 RM |
350 | WREG32(AFMT_INFOFRAME_CONTROL0 + offset, |
351 | AFMT_AUDIO_INFO_UPDATE); /* required for audio info values to be updated */ | |
e55d3e6c | 352 | |
1c3439f2 | 353 | WREG32(HDMI_INFOFRAME_CONTROL1 + offset, |
1c3439f2 RM |
354 | HDMI_AUDIO_INFO_LINE(2)); /* anything other than 0 */ |
355 | ||
356 | WREG32(HDMI_GC + offset, 0); /* unset HDMI_GC_AVMUTE */ | |
e55d3e6c | 357 | |
91a44019 RM |
358 | WREG32(HDMI_AUDIO_PACKET_CONTROL + offset, |
359 | HDMI_AUDIO_DELAY_EN(1) | /* set the default audio delay */ | |
360 | HDMI_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */ | |
361 | ||
362 | WREG32(AFMT_AUDIO_PACKET_CONTROL + offset, | |
363 | AFMT_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */ | |
364 | ||
365 | /* fglrx clears sth in AFMT_AUDIO_PACKET_CONTROL2 here */ | |
366 | ||
79766915 AD |
367 | if (bpc > 8) |
368 | WREG32(HDMI_ACR_PACKET_CONTROL + offset, | |
369 | HDMI_ACR_AUTO_SEND); /* allow hw to sent ACR packets when required */ | |
370 | else | |
371 | WREG32(HDMI_ACR_PACKET_CONTROL + offset, | |
372 | HDMI_ACR_SOURCE | /* select SW CTS value */ | |
373 | HDMI_ACR_AUTO_SEND); /* allow hw to sent ACR packets when required */ | |
91a44019 RM |
374 | |
375 | evergreen_hdmi_update_ACR(encoder, mode->clock); | |
376 | ||
f93e3fc3 RM |
377 | WREG32(AFMT_60958_0 + offset, |
378 | AFMT_60958_CS_CHANNEL_NUMBER_L(1)); | |
379 | ||
380 | WREG32(AFMT_60958_1 + offset, | |
381 | AFMT_60958_CS_CHANNEL_NUMBER_R(2)); | |
382 | ||
383 | WREG32(AFMT_60958_2 + offset, | |
384 | AFMT_60958_CS_CHANNEL_NUMBER_2(3) | | |
385 | AFMT_60958_CS_CHANNEL_NUMBER_3(4) | | |
386 | AFMT_60958_CS_CHANNEL_NUMBER_4(5) | | |
387 | AFMT_60958_CS_CHANNEL_NUMBER_5(6) | | |
388 | AFMT_60958_CS_CHANNEL_NUMBER_6(7) | | |
389 | AFMT_60958_CS_CHANNEL_NUMBER_7(8)); | |
390 | ||
00a9d4bc | 391 | radeon_audio_write_speaker_allocation(encoder); |
f93e3fc3 RM |
392 | |
393 | WREG32(AFMT_AUDIO_PACKET_CONTROL2 + offset, | |
394 | AFMT_AUDIO_CHANNEL_ENABLE(0xff)); | |
395 | ||
396 | /* fglrx sets 0x40 in 0x5f80 here */ | |
b530602f | 397 | |
88252d77 | 398 | radeon_audio_select_pin(encoder); |
070a2e63 | 399 | radeon_audio_write_sad_regs(encoder); |
87654f87 | 400 | radeon_audio_write_latency_fields(encoder, mode); |
070a2e63 | 401 | |
e3b2e034 TR |
402 | err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode); |
403 | if (err < 0) { | |
404 | DRM_ERROR("failed to setup AVI infoframe: %zd\n", err); | |
405 | return; | |
406 | } | |
407 | ||
408 | err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer)); | |
409 | if (err < 0) { | |
410 | DRM_ERROR("failed to pack AVI infoframe: %zd\n", err); | |
411 | return; | |
412 | } | |
e55d3e6c | 413 | |
e3b2e034 | 414 | evergreen_hdmi_update_avi_infoframe(encoder, buffer, sizeof(buffer)); |
1c3439f2 | 415 | |
d3418eac RM |
416 | WREG32_OR(HDMI_INFOFRAME_CONTROL0 + offset, |
417 | HDMI_AVI_INFO_SEND | /* enable AVI info frames */ | |
418 | HDMI_AVI_INFO_CONT); /* required for audio info values to be updated */ | |
419 | ||
420 | WREG32_P(HDMI_INFOFRAME_CONTROL1 + offset, | |
421 | HDMI_AVI_INFO_LINE(2), /* anything other than 0 */ | |
422 | ~HDMI_AVI_INFO_LINE_MASK); | |
423 | ||
424 | WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + offset, | |
425 | AFMT_AUDIO_SAMPLE_SEND); /* send audio packets */ | |
426 | ||
e55d3e6c RM |
427 | /* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */ |
428 | WREG32(AFMT_RAMP_CONTROL0 + offset, 0x00FFFFFF); | |
429 | WREG32(AFMT_RAMP_CONTROL1 + offset, 0x007FFFFF); | |
430 | WREG32(AFMT_RAMP_CONTROL2 + offset, 0x00000001); | |
431 | WREG32(AFMT_RAMP_CONTROL3 + offset, 0x00000001); | |
832eafaf AD |
432 | |
433 | /* enable audio after to setting up hw */ | |
8bf59820 | 434 | radeon_audio_enable(rdev, dig->afmt->pin, 0xf); |
e55d3e6c | 435 | } |
a973bea1 AD |
436 | |
437 | void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable) | |
438 | { | |
4adb34ef AD |
439 | struct drm_device *dev = encoder->dev; |
440 | struct radeon_device *rdev = dev->dev_private; | |
a973bea1 AD |
441 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
442 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; | |
443 | ||
c2b4cacf AD |
444 | if (!dig || !dig->afmt) |
445 | return; | |
446 | ||
a973bea1 AD |
447 | /* Silent, r600_hdmi_enable will raise WARN for us */ |
448 | if (enable && dig->afmt->enabled) | |
449 | return; | |
450 | if (!enable && !dig->afmt->enabled) | |
451 | return; | |
452 | ||
4adb34ef | 453 | if (!enable && dig->afmt->pin) { |
8bf59820 | 454 | radeon_audio_enable(rdev, dig->afmt->pin, 0); |
4adb34ef AD |
455 | dig->afmt->pin = NULL; |
456 | } | |
457 | ||
a973bea1 AD |
458 | dig->afmt->enabled = enable; |
459 | ||
460 | DRM_DEBUG("%sabling HDMI interface @ 0x%04X for encoder 0x%x\n", | |
461 | enable ? "En" : "Dis", dig->afmt->offset, radeon_encoder->encoder_id); | |
462 | } |