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drm/radeon: clean up r600_free_extended_power_table()
[deliverable/linux.git] / drivers / gpu / drm / radeon / kv_dpm.c
CommitLineData
41a524ab
AD		 1/*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include "drmP.h"
25#include "radeon.h"
26#include "cikd.h"
27#include "r600_dpm.h"
28#include "kv_dpm.h"
e409b128 29#include "radeon_asic.h"
ae3e40e8 30#include <linux/seq_file.h>
41a524ab
AD		 31
32#define KV_MAX_DEEPSLEEP_DIVIDER_ID 5
33#define KV_MINIMUM_ENGINE_CLOCK 800
34#define SMC_RAM_END 0x40000
35
36static void kv_init_graphics_levels(struct radeon_device *rdev);
37static int kv_calculate_ds_divider(struct radeon_device *rdev);
38static int kv_calculate_nbps_level_settings(struct radeon_device *rdev);
39static int kv_calculate_dpm_settings(struct radeon_device *rdev);
40static void kv_enable_new_levels(struct radeon_device *rdev);
41static void kv_program_nbps_index_settings(struct radeon_device *rdev,
42 struct radeon_ps *new_rps);
43static int kv_set_enabled_levels(struct radeon_device *rdev);
2b4c8022 44static int kv_force_dpm_highest(struct radeon_device *rdev);
41a524ab
AD		 45static int kv_force_dpm_lowest(struct radeon_device *rdev);
46static void kv_apply_state_adjust_rules(struct radeon_device *rdev,
47 struct radeon_ps *new_rps,
48 struct radeon_ps *old_rps);
49static int kv_set_thermal_temperature_range(struct radeon_device *rdev,
50 int min_temp, int max_temp);
51static int kv_init_fps_limits(struct radeon_device *rdev);
52
77df508a 53void kv_dpm_powergate_uvd(struct radeon_device *rdev, bool gate);
41a524ab
AD		 54static void kv_dpm_powergate_vce(struct radeon_device *rdev, bool gate);
55static void kv_dpm_powergate_samu(struct radeon_device *rdev, bool gate);
56static void kv_dpm_powergate_acp(struct radeon_device *rdev, bool gate);
57
58extern void cik_enter_rlc_safe_mode(struct radeon_device *rdev);
59extern void cik_exit_rlc_safe_mode(struct radeon_device *rdev);
60extern void cik_update_cg(struct radeon_device *rdev,
61 u32 block, bool enable);
62
63static const struct kv_lcac_config_values sx_local_cac_cfg_kv[] =
64{
65 { 0, 4, 1 },
66 { 1, 4, 1 },
67 { 2, 5, 1 },
68 { 3, 4, 2 },
69 { 4, 1, 1 },
70 { 5, 5, 2 },
71 { 6, 6, 1 },
72 { 7, 9, 2 },
73 { 0xffffffff }
74};
75
76static const struct kv_lcac_config_values mc0_local_cac_cfg_kv[] =
77{
78 { 0, 4, 1 },
79 { 0xffffffff }
80};
81
82static const struct kv_lcac_config_values mc1_local_cac_cfg_kv[] =
83{
84 { 0, 4, 1 },
85 { 0xffffffff }
86};
87
88static const struct kv_lcac_config_values mc2_local_cac_cfg_kv[] =
89{
90 { 0, 4, 1 },
91 { 0xffffffff }
92};
93
94static const struct kv_lcac_config_values mc3_local_cac_cfg_kv[] =
95{
96 { 0, 4, 1 },
97 { 0xffffffff }
98};
99
100static const struct kv_lcac_config_values cpl_local_cac_cfg_kv[] =
101{
102 { 0, 4, 1 },
103 { 1, 4, 1 },
104 { 2, 5, 1 },
105 { 3, 4, 1 },
106 { 4, 1, 1 },
107 { 5, 5, 1 },
108 { 6, 6, 1 },
109 { 7, 9, 1 },
110 { 8, 4, 1 },
111 { 9, 2, 1 },
112 { 10, 3, 1 },
113 { 11, 6, 1 },
114 { 12, 8, 2 },
115 { 13, 1, 1 },
116 { 14, 2, 1 },
117 { 15, 3, 1 },
118 { 16, 1, 1 },
119 { 17, 4, 1 },
120 { 18, 3, 1 },
121 { 19, 1, 1 },
122 { 20, 8, 1 },
123 { 21, 5, 1 },
124 { 22, 1, 1 },
125 { 23, 1, 1 },
126 { 24, 4, 1 },
127 { 27, 6, 1 },
128 { 28, 1, 1 },
129 { 0xffffffff }
130};
131
132static const struct kv_lcac_config_reg sx0_cac_config_reg[] =
133{
134 { 0xc0400d00, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 }
135};
136
137static const struct kv_lcac_config_reg mc0_cac_config_reg[] =
138{
139 { 0xc0400d30, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 }
140};
141
142static const struct kv_lcac_config_reg mc1_cac_config_reg[] =
143{
144 { 0xc0400d3c, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 }
145};
146
147static const struct kv_lcac_config_reg mc2_cac_config_reg[] =
148{
149 { 0xc0400d48, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 }
150};
151
152static const struct kv_lcac_config_reg mc3_cac_config_reg[] =
153{
154 { 0xc0400d54, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 }
155};
156
157static const struct kv_lcac_config_reg cpl_cac_config_reg[] =
158{
159 { 0xc0400d80, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 }
160};
161
162static const struct kv_pt_config_reg didt_config_kv[] =
163{
164 { 0x10, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
165 { 0x10, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
166 { 0x10, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
167 { 0x10, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
168 { 0x11, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
169 { 0x11, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
170 { 0x11, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
171 { 0x11, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
172 { 0x12, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
173 { 0x12, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
174 { 0x12, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
175 { 0x12, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
176 { 0x2, 0x00003fff, 0, 0x4, KV_CONFIGREG_DIDT_IND },
177 { 0x2, 0x03ff0000, 16, 0x80, KV_CONFIGREG_DIDT_IND },
178 { 0x2, 0x78000000, 27, 0x3, KV_CONFIGREG_DIDT_IND },
179 { 0x1, 0x0000ffff, 0, 0x3FFF, KV_CONFIGREG_DIDT_IND },
180 { 0x1, 0xffff0000, 16, 0x3FFF, KV_CONFIGREG_DIDT_IND },
181 { 0x0, 0x00000001, 0, 0x0, KV_CONFIGREG_DIDT_IND },
182 { 0x30, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
183 { 0x30, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
184 { 0x30, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
185 { 0x30, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
186 { 0x31, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
187 { 0x31, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
188 { 0x31, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
189 { 0x31, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
190 { 0x32, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
191 { 0x32, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
192 { 0x32, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
193 { 0x32, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
194 { 0x22, 0x00003fff, 0, 0x4, KV_CONFIGREG_DIDT_IND },
195 { 0x22, 0x03ff0000, 16, 0x80, KV_CONFIGREG_DIDT_IND },
196 { 0x22, 0x78000000, 27, 0x3, KV_CONFIGREG_DIDT_IND },
197 { 0x21, 0x0000ffff, 0, 0x3FFF, KV_CONFIGREG_DIDT_IND },
198 { 0x21, 0xffff0000, 16, 0x3FFF, KV_CONFIGREG_DIDT_IND },
199 { 0x20, 0x00000001, 0, 0x0, KV_CONFIGREG_DIDT_IND },
200 { 0x50, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
201 { 0x50, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
202 { 0x50, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
203 { 0x50, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
204 { 0x51, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
205 { 0x51, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
206 { 0x51, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
207 { 0x51, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
208 { 0x52, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
209 { 0x52, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
210 { 0x52, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
211 { 0x52, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
212 { 0x42, 0x00003fff, 0, 0x4, KV_CONFIGREG_DIDT_IND },
213 { 0x42, 0x03ff0000, 16, 0x80, KV_CONFIGREG_DIDT_IND },
214 { 0x42, 0x78000000, 27, 0x3, KV_CONFIGREG_DIDT_IND },
215 { 0x41, 0x0000ffff, 0, 0x3FFF, KV_CONFIGREG_DIDT_IND },
216 { 0x41, 0xffff0000, 16, 0x3FFF, KV_CONFIGREG_DIDT_IND },
217 { 0x40, 0x00000001, 0, 0x0, KV_CONFIGREG_DIDT_IND },
218 { 0x70, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
219 { 0x70, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
220 { 0x70, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
221 { 0x70, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
222 { 0x71, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
223 { 0x71, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
224 { 0x71, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
225 { 0x71, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
226 { 0x72, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
227 { 0x72, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
228 { 0x72, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
229 { 0x72, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
230 { 0x62, 0x00003fff, 0, 0x4, KV_CONFIGREG_DIDT_IND },
231 { 0x62, 0x03ff0000, 16, 0x80, KV_CONFIGREG_DIDT_IND },
232 { 0x62, 0x78000000, 27, 0x3, KV_CONFIGREG_DIDT_IND },
233 { 0x61, 0x0000ffff, 0, 0x3FFF, KV_CONFIGREG_DIDT_IND },
234 { 0x61, 0xffff0000, 16, 0x3FFF, KV_CONFIGREG_DIDT_IND },
235 { 0x60, 0x00000001, 0, 0x0, KV_CONFIGREG_DIDT_IND },
236 { 0xFFFFFFFF }
237};
238
239static struct kv_ps *kv_get_ps(struct radeon_ps *rps)
240{
241 struct kv_ps *ps = rps->ps_priv;
242
243 return ps;
244}
245
246static struct kv_power_info *kv_get_pi(struct radeon_device *rdev)
247{
248 struct kv_power_info *pi = rdev->pm.dpm.priv;
249
250 return pi;
251}
252
253#if 0
254static void kv_program_local_cac_table(struct radeon_device *rdev,
255 const struct kv_lcac_config_values *local_cac_table,
256 const struct kv_lcac_config_reg *local_cac_reg)
257{
258 u32 i, count, data;
259 const struct kv_lcac_config_values *values = local_cac_table;
260
261 while (values->block_id != 0xffffffff) {
262 count = values->signal_id;
263 for (i = 0; i < count; i++) {
264 data = ((values->block_id << local_cac_reg->block_shift) &
265 local_cac_reg->block_mask);
266 data |= ((i << local_cac_reg->signal_shift) &
267 local_cac_reg->signal_mask);
268 data |= ((values->t << local_cac_reg->t_shift) &
269 local_cac_reg->t_mask);
270 data |= ((1 << local_cac_reg->enable_shift) &
271 local_cac_reg->enable_mask);
272 WREG32_SMC(local_cac_reg->cntl, data);
273 }
274 values++;
275 }
276}
277#endif
278
279static int kv_program_pt_config_registers(struct radeon_device *rdev,
280 const struct kv_pt_config_reg *cac_config_regs)
281{
282 const struct kv_pt_config_reg *config_regs = cac_config_regs;
283 u32 data;
284 u32 cache = 0;
285
286 if (config_regs == NULL)
287 return -EINVAL;
288
289 while (config_regs->offset != 0xFFFFFFFF) {
290 if (config_regs->type == KV_CONFIGREG_CACHE) {
291 cache |= ((config_regs->value << config_regs->shift) & config_regs->mask);
292 } else {
293 switch (config_regs->type) {
294 case KV_CONFIGREG_SMC_IND:
295 data = RREG32_SMC(config_regs->offset);
296 break;
297 case KV_CONFIGREG_DIDT_IND:
298 data = RREG32_DIDT(config_regs->offset);
299 break;
300 default:
301 data = RREG32(config_regs->offset << 2);
302 break;
303 }
304
305 data &= ~config_regs->mask;
306 data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
307 data |= cache;
308 cache = 0;
309
310 switch (config_regs->type) {
311 case KV_CONFIGREG_SMC_IND:
312 WREG32_SMC(config_regs->offset, data);
313 break;
314 case KV_CONFIGREG_DIDT_IND:
315 WREG32_DIDT(config_regs->offset, data);
316 break;
317 default:
318 WREG32(config_regs->offset << 2, data);
319 break;
320 }
321 }
322 config_regs++;
323 }
324
325 return 0;
326}
327
328static void kv_do_enable_didt(struct radeon_device *rdev, bool enable)
329{
330 struct kv_power_info *pi = kv_get_pi(rdev);
331 u32 data;
332
333 if (pi->caps_sq_ramping) {
334 data = RREG32_DIDT(DIDT_SQ_CTRL0);
335 if (enable)
336 data |= DIDT_CTRL_EN;
337 else
338 data &= ~DIDT_CTRL_EN;
339 WREG32_DIDT(DIDT_SQ_CTRL0, data);
340 }
341
342 if (pi->caps_db_ramping) {
343 data = RREG32_DIDT(DIDT_DB_CTRL0);
344 if (enable)
345 data |= DIDT_CTRL_EN;
346 else
347 data &= ~DIDT_CTRL_EN;
348 WREG32_DIDT(DIDT_DB_CTRL0, data);
349 }
350
351 if (pi->caps_td_ramping) {
352 data = RREG32_DIDT(DIDT_TD_CTRL0);
353 if (enable)
354 data |= DIDT_CTRL_EN;
355 else
356 data &= ~DIDT_CTRL_EN;
357 WREG32_DIDT(DIDT_TD_CTRL0, data);
358 }
359
360 if (pi->caps_tcp_ramping) {
361 data = RREG32_DIDT(DIDT_TCP_CTRL0);
362 if (enable)
363 data |= DIDT_CTRL_EN;
364 else
365 data &= ~DIDT_CTRL_EN;
366 WREG32_DIDT(DIDT_TCP_CTRL0, data);
367 }
368}
369
370static int kv_enable_didt(struct radeon_device *rdev, bool enable)
371{
372 struct kv_power_info *pi = kv_get_pi(rdev);
373 int ret;
374
375 if (pi->caps_sq_ramping ||
376 pi->caps_db_ramping ||
377 pi->caps_td_ramping ||
378 pi->caps_tcp_ramping) {
379 cik_enter_rlc_safe_mode(rdev);
380
381 if (enable) {
382 ret = kv_program_pt_config_registers(rdev, didt_config_kv);
383 if (ret) {
384 cik_exit_rlc_safe_mode(rdev);
385 return ret;
386 }
387 }
388
389 kv_do_enable_didt(rdev, enable);
390
391 cik_exit_rlc_safe_mode(rdev);
392 }
393
394 return 0;
395}
396
397#if 0
398static void kv_initialize_hardware_cac_manager(struct radeon_device *rdev)
399{
400 struct kv_power_info *pi = kv_get_pi(rdev);
401
402 if (pi->caps_cac) {
403 WREG32_SMC(LCAC_SX0_OVR_SEL, 0);
404 WREG32_SMC(LCAC_SX0_OVR_VAL, 0);
405 kv_program_local_cac_table(rdev, sx_local_cac_cfg_kv, sx0_cac_config_reg);
406
407 WREG32_SMC(LCAC_MC0_OVR_SEL, 0);
408 WREG32_SMC(LCAC_MC0_OVR_VAL, 0);
409 kv_program_local_cac_table(rdev, mc0_local_cac_cfg_kv, mc0_cac_config_reg);
410
411 WREG32_SMC(LCAC_MC1_OVR_SEL, 0);
412 WREG32_SMC(LCAC_MC1_OVR_VAL, 0);
413 kv_program_local_cac_table(rdev, mc1_local_cac_cfg_kv, mc1_cac_config_reg);
414
415 WREG32_SMC(LCAC_MC2_OVR_SEL, 0);
416 WREG32_SMC(LCAC_MC2_OVR_VAL, 0);
417 kv_program_local_cac_table(rdev, mc2_local_cac_cfg_kv, mc2_cac_config_reg);
418
419 WREG32_SMC(LCAC_MC3_OVR_SEL, 0);
420 WREG32_SMC(LCAC_MC3_OVR_VAL, 0);
421 kv_program_local_cac_table(rdev, mc3_local_cac_cfg_kv, mc3_cac_config_reg);
422
423 WREG32_SMC(LCAC_CPL_OVR_SEL, 0);
424 WREG32_SMC(LCAC_CPL_OVR_VAL, 0);
425 kv_program_local_cac_table(rdev, cpl_local_cac_cfg_kv, cpl_cac_config_reg);
426 }
427}
428#endif
429
430static int kv_enable_smc_cac(struct radeon_device *rdev, bool enable)
431{
432 struct kv_power_info *pi = kv_get_pi(rdev);
433 int ret = 0;
434
435 if (pi->caps_cac) {
436 if (enable) {
437 ret = kv_notify_message_to_smu(rdev, PPSMC_MSG_EnableCac);
438 if (ret)
439 pi->cac_enabled = false;
440 else
441 pi->cac_enabled = true;
442 } else if (pi->cac_enabled) {
443 kv_notify_message_to_smu(rdev, PPSMC_MSG_DisableCac);
444 pi->cac_enabled = false;
445 }
446 }
447
448 return ret;
449}
450
451static int kv_process_firmware_header(struct radeon_device *rdev)
452{
453 struct kv_power_info *pi = kv_get_pi(rdev);
454 u32 tmp;
455 int ret;
456
457 ret = kv_read_smc_sram_dword(rdev, SMU7_FIRMWARE_HEADER_LOCATION +
458 offsetof(SMU7_Firmware_Header, DpmTable),
459 &tmp, pi->sram_end);
460
461 if (ret == 0)
462 pi->dpm_table_start = tmp;
463
464 ret = kv_read_smc_sram_dword(rdev, SMU7_FIRMWARE_HEADER_LOCATION +
465 offsetof(SMU7_Firmware_Header, SoftRegisters),
466 &tmp, pi->sram_end);
467
468 if (ret == 0)
469 pi->soft_regs_start = tmp;
470
471 return ret;
472}
473
474static int kv_enable_dpm_voltage_scaling(struct radeon_device *rdev)
475{
476 struct kv_power_info *pi = kv_get_pi(rdev);
477 int ret;
478
479 pi->graphics_voltage_change_enable = 1;
480
481 ret = kv_copy_bytes_to_smc(rdev,
482 pi->dpm_table_start +
483 offsetof(SMU7_Fusion_DpmTable, GraphicsVoltageChangeEnable),
484 &pi->graphics_voltage_change_enable,
485 sizeof(u8), pi->sram_end);
486
487 return ret;
488}
489
490static int kv_set_dpm_interval(struct radeon_device *rdev)
491{
492 struct kv_power_info *pi = kv_get_pi(rdev);
493 int ret;
494
495 pi->graphics_interval = 1;
496
497 ret = kv_copy_bytes_to_smc(rdev,
498 pi->dpm_table_start +
499 offsetof(SMU7_Fusion_DpmTable, GraphicsInterval),
500 &pi->graphics_interval,
501 sizeof(u8), pi->sram_end);
502
503 return ret;
504}
505
506static int kv_set_dpm_boot_state(struct radeon_device *rdev)
507{
508 struct kv_power_info *pi = kv_get_pi(rdev);
509 int ret;
510
511 ret = kv_copy_bytes_to_smc(rdev,
512 pi->dpm_table_start +
513 offsetof(SMU7_Fusion_DpmTable, GraphicsBootLevel),
514 &pi->graphics_boot_level,
515 sizeof(u8), pi->sram_end);
516
517 return ret;
518}
519
520static void kv_program_vc(struct radeon_device *rdev)
521{
522 WREG32_SMC(CG_FTV_0, 0x3FFFC000);
523}
524
525static void kv_clear_vc(struct radeon_device *rdev)
526{
527 WREG32_SMC(CG_FTV_0, 0);
528}
529
530static int kv_set_divider_value(struct radeon_device *rdev,
531 u32 index, u32 sclk)
532{
533 struct kv_power_info *pi = kv_get_pi(rdev);
534 struct atom_clock_dividers dividers;
535 int ret;
536
537 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
538 sclk, false, &dividers);
539 if (ret)
540 return ret;
541
542 pi->graphics_level[index].SclkDid = (u8)dividers.post_div;
543 pi->graphics_level[index].SclkFrequency = cpu_to_be32(sclk);
544
545 return 0;
546}
547
548static u16 kv_convert_8bit_index_to_voltage(struct radeon_device *rdev,
549 u16 voltage)
550{
551 return 6200 - (voltage * 25);
552}
553
554static u16 kv_convert_2bit_index_to_voltage(struct radeon_device *rdev,
555 u32 vid_2bit)
556{
557 struct kv_power_info *pi = kv_get_pi(rdev);
558 u32 vid_8bit = sumo_convert_vid2_to_vid7(rdev,
559 &pi->sys_info.vid_mapping_table,
560 vid_2bit);
561
562 return kv_convert_8bit_index_to_voltage(rdev, (u16)vid_8bit);
563}
564
565
566static int kv_set_vid(struct radeon_device *rdev, u32 index, u32 vid)
567{
568 struct kv_power_info *pi = kv_get_pi(rdev);
569
570 pi->graphics_level[index].VoltageDownH = (u8)pi->voltage_drop_t;
571 pi->graphics_level[index].MinVddNb =
572 cpu_to_be32(kv_convert_2bit_index_to_voltage(rdev, vid));
573
574 return 0;
575}
576
577static int kv_set_at(struct radeon_device *rdev, u32 index, u32 at)
578{
579 struct kv_power_info *pi = kv_get_pi(rdev);
580
581 pi->graphics_level[index].AT = cpu_to_be16((u16)at);
582
583 return 0;
584}
585
586static void kv_dpm_power_level_enable(struct radeon_device *rdev,
587 u32 index, bool enable)
588{
589 struct kv_power_info *pi = kv_get_pi(rdev);
590
591 pi->graphics_level[index].EnabledForActivity = enable ? 1 : 0;
592}
593
594static void kv_start_dpm(struct radeon_device *rdev)
595{
596 u32 tmp = RREG32_SMC(GENERAL_PWRMGT);
597
598 tmp |= GLOBAL_PWRMGT_EN;
599 WREG32_SMC(GENERAL_PWRMGT, tmp);
600
601 kv_smc_dpm_enable(rdev, true);
602}
603
604static void kv_stop_dpm(struct radeon_device *rdev)
605{
606 kv_smc_dpm_enable(rdev, false);
607}
608
609static void kv_start_am(struct radeon_device *rdev)
610{
611 u32 sclk_pwrmgt_cntl = RREG32_SMC(SCLK_PWRMGT_CNTL);
612
613 sclk_pwrmgt_cntl &= ~(RESET_SCLK_CNT | RESET_BUSY_CNT);
614 sclk_pwrmgt_cntl |= DYNAMIC_PM_EN;
615
616 WREG32_SMC(SCLK_PWRMGT_CNTL, sclk_pwrmgt_cntl);
617}
618
619static void kv_reset_am(struct radeon_device *rdev)
620{
621 u32 sclk_pwrmgt_cntl = RREG32_SMC(SCLK_PWRMGT_CNTL);
622
623 sclk_pwrmgt_cntl |= (RESET_SCLK_CNT | RESET_BUSY_CNT);
624
625 WREG32_SMC(SCLK_PWRMGT_CNTL, sclk_pwrmgt_cntl);
626}
627
628static int kv_freeze_sclk_dpm(struct radeon_device *rdev, bool freeze)
629{
630 return kv_notify_message_to_smu(rdev, freeze ?
631 PPSMC_MSG_SCLKDPM_FreezeLevel : PPSMC_MSG_SCLKDPM_UnfreezeLevel);
632}
633
634static int kv_force_lowest_valid(struct radeon_device *rdev)
635{
636 return kv_force_dpm_lowest(rdev);
637}
638
639static int kv_unforce_levels(struct radeon_device *rdev)
640{
641 return kv_notify_message_to_smu(rdev, PPSMC_MSG_NoForcedLevel);
642}
643
644static int kv_update_sclk_t(struct radeon_device *rdev)
645{
646 struct kv_power_info *pi = kv_get_pi(rdev);
647 u32 low_sclk_interrupt_t = 0;
648 int ret = 0;
649
650 if (pi->caps_sclk_throttle_low_notification) {
651 low_sclk_interrupt_t = cpu_to_be32(pi->low_sclk_interrupt_t);
652
653 ret = kv_copy_bytes_to_smc(rdev,
654 pi->dpm_table_start +
655 offsetof(SMU7_Fusion_DpmTable, LowSclkInterruptT),
656 (u8 *)&low_sclk_interrupt_t,
657 sizeof(u32), pi->sram_end);
658 }
659 return ret;
660}
661
662static int kv_program_bootup_state(struct radeon_device *rdev)
663{
664 struct kv_power_info *pi = kv_get_pi(rdev);
665 u32 i;
666 struct radeon_clock_voltage_dependency_table *table =
667 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
668
669 if (table && table->count) {
670 for (i = pi->graphics_dpm_level_count - 1; i >= 0; i--) {
671 if ((table->entries[i].clk == pi->boot_pl.sclk) ||
672 (i == 0))
673 break;
674 }
675
676 pi->graphics_boot_level = (u8)i;
677 kv_dpm_power_level_enable(rdev, i, true);
678 } else {
679 struct sumo_sclk_voltage_mapping_table *table =
680 &pi->sys_info.sclk_voltage_mapping_table;
681
682 if (table->num_max_dpm_entries == 0)
683 return -EINVAL;
684
685 for (i = pi->graphics_dpm_level_count - 1; i >= 0; i--) {
686 if ((table->entries[i].sclk_frequency == pi->boot_pl.sclk) ||
687 (i == 0))
688 break;
689 }
690
691 pi->graphics_boot_level = (u8)i;
692 kv_dpm_power_level_enable(rdev, i, true);
693 }
694 return 0;
695}
696
697static int kv_enable_auto_thermal_throttling(struct radeon_device *rdev)
698{
699 struct kv_power_info *pi = kv_get_pi(rdev);
700 int ret;
701
702 pi->graphics_therm_throttle_enable = 1;
703
704 ret = kv_copy_bytes_to_smc(rdev,
705 pi->dpm_table_start +
706 offsetof(SMU7_Fusion_DpmTable, GraphicsThermThrottleEnable),
707 &pi->graphics_therm_throttle_enable,
708 sizeof(u8), pi->sram_end);
709
710 return ret;
711}
712
713static int kv_upload_dpm_settings(struct radeon_device *rdev)
714{
715 struct kv_power_info *pi = kv_get_pi(rdev);
716 int ret;
717
718 ret = kv_copy_bytes_to_smc(rdev,
719 pi->dpm_table_start +
720 offsetof(SMU7_Fusion_DpmTable, GraphicsLevel),
721 (u8 *)&pi->graphics_level,
722 sizeof(SMU7_Fusion_GraphicsLevel) * SMU7_MAX_LEVELS_GRAPHICS,
723 pi->sram_end);
724
725 if (ret)
726 return ret;
727
728 ret = kv_copy_bytes_to_smc(rdev,
729 pi->dpm_table_start +
730 offsetof(SMU7_Fusion_DpmTable, GraphicsDpmLevelCount),
731 &pi->graphics_dpm_level_count,
732 sizeof(u8), pi->sram_end);
733
734 return ret;
735}
736
737static u32 kv_get_clock_difference(u32 a, u32 b)
738{
739 return (a >= b) ? a - b : b - a;
740}
741
742static u32 kv_get_clk_bypass(struct radeon_device *rdev, u32 clk)
743{
744 struct kv_power_info *pi = kv_get_pi(rdev);
745 u32 value;
746
747 if (pi->caps_enable_dfs_bypass) {
748 if (kv_get_clock_difference(clk, 40000) < 200)
749 value = 3;
750 else if (kv_get_clock_difference(clk, 30000) < 200)
751 value = 2;
752 else if (kv_get_clock_difference(clk, 20000) < 200)
753 value = 7;
754 else if (kv_get_clock_difference(clk, 15000) < 200)
755 value = 6;
756 else if (kv_get_clock_difference(clk, 10000) < 200)
757 value = 8;
758 else
759 value = 0;
760 } else {
761 value = 0;
762 }
763
764 return value;
765}
766
767static int kv_populate_uvd_table(struct radeon_device *rdev)
768{
769 struct kv_power_info *pi = kv_get_pi(rdev);
770 struct radeon_uvd_clock_voltage_dependency_table *table =
771 &rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;
772 struct atom_clock_dividers dividers;
773 int ret;
774 u32 i;
775
776 if (table == NULL || table->count == 0)
777 return 0;
778
779 pi->uvd_level_count = 0;
780 for (i = 0; i < table->count; i++) {
781 if (pi->high_voltage_t &&
782 (pi->high_voltage_t < table->entries[i].v))
783 break;
784
785 pi->uvd_level[i].VclkFrequency = cpu_to_be32(table->entries[i].vclk);
786 pi->uvd_level[i].DclkFrequency = cpu_to_be32(table->entries[i].dclk);
787 pi->uvd_level[i].MinVddNb = cpu_to_be16(table->entries[i].v);
788
789 pi->uvd_level[i].VClkBypassCntl =
790 (u8)kv_get_clk_bypass(rdev, table->entries[i].vclk);
791 pi->uvd_level[i].DClkBypassCntl =
792 (u8)kv_get_clk_bypass(rdev, table->entries[i].dclk);
793
794 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
795 table->entries[i].vclk, false, &dividers);
796 if (ret)
797 return ret;
798 pi->uvd_level[i].VclkDivider = (u8)dividers.post_div;
799
800 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
801 table->entries[i].dclk, false, &dividers);
802 if (ret)
803 return ret;
804 pi->uvd_level[i].DclkDivider = (u8)dividers.post_div;
805
806 pi->uvd_level_count++;
807 }
808
809 ret = kv_copy_bytes_to_smc(rdev,
810 pi->dpm_table_start +
811 offsetof(SMU7_Fusion_DpmTable, UvdLevelCount),
812 (u8 *)&pi->uvd_level_count,
813 sizeof(u8), pi->sram_end);
814 if (ret)
815 return ret;
816
817 pi->uvd_interval = 1;
818
819 ret = kv_copy_bytes_to_smc(rdev,
820 pi->dpm_table_start +
821 offsetof(SMU7_Fusion_DpmTable, UVDInterval),
822 &pi->uvd_interval,
823 sizeof(u8), pi->sram_end);
824 if (ret)
825 return ret;
826
827 ret = kv_copy_bytes_to_smc(rdev,
828 pi->dpm_table_start +
829 offsetof(SMU7_Fusion_DpmTable, UvdLevel),
830 (u8 *)&pi->uvd_level,
831 sizeof(SMU7_Fusion_UvdLevel) * SMU7_MAX_LEVELS_UVD,
832 pi->sram_end);
833
834 return ret;
835
836}
837
838static int kv_populate_vce_table(struct radeon_device *rdev)
839{
840 struct kv_power_info *pi = kv_get_pi(rdev);
841 int ret;
842 u32 i;
843 struct radeon_vce_clock_voltage_dependency_table *table =
844 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
845 struct atom_clock_dividers dividers;
846
847 if (table == NULL || table->count == 0)
848 return 0;
849
850 pi->vce_level_count = 0;
851 for (i = 0; i < table->count; i++) {
852 if (pi->high_voltage_t &&
853 pi->high_voltage_t < table->entries[i].v)
854 break;
855
856 pi->vce_level[i].Frequency = cpu_to_be32(table->entries[i].evclk);
857 pi->vce_level[i].MinVoltage = cpu_to_be16(table->entries[i].v);
858
859 pi->vce_level[i].ClkBypassCntl =
860 (u8)kv_get_clk_bypass(rdev, table->entries[i].evclk);
861
862 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
863 table->entries[i].evclk, false, &dividers);
864 if (ret)
865 return ret;
866 pi->vce_level[i].Divider = (u8)dividers.post_div;
867
868 pi->vce_level_count++;
869 }
870
871 ret = kv_copy_bytes_to_smc(rdev,
872 pi->dpm_table_start +
873 offsetof(SMU7_Fusion_DpmTable, VceLevelCount),
874 (u8 *)&pi->vce_level_count,
875 sizeof(u8),
876 pi->sram_end);
877 if (ret)
878 return ret;
879
880 pi->vce_interval = 1;
881
882 ret = kv_copy_bytes_to_smc(rdev,
883 pi->dpm_table_start +
884 offsetof(SMU7_Fusion_DpmTable, VCEInterval),
885 (u8 *)&pi->vce_interval,
886 sizeof(u8),
887 pi->sram_end);
888 if (ret)
889 return ret;
890
891 ret = kv_copy_bytes_to_smc(rdev,
892 pi->dpm_table_start +
893 offsetof(SMU7_Fusion_DpmTable, VceLevel),
894 (u8 *)&pi->vce_level,
895 sizeof(SMU7_Fusion_ExtClkLevel) * SMU7_MAX_LEVELS_VCE,
896 pi->sram_end);
897
898 return ret;
899}
900
901static int kv_populate_samu_table(struct radeon_device *rdev)
902{
903 struct kv_power_info *pi = kv_get_pi(rdev);
904 struct radeon_clock_voltage_dependency_table *table =
905 &rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table;
906 struct atom_clock_dividers dividers;
907 int ret;
908 u32 i;
909
910 if (table == NULL || table->count == 0)
911 return 0;
912
913 pi->samu_level_count = 0;
914 for (i = 0; i < table->count; i++) {
915 if (pi->high_voltage_t &&
916 pi->high_voltage_t < table->entries[i].v)
917 break;
918
919 pi->samu_level[i].Frequency = cpu_to_be32(table->entries[i].clk);
920 pi->samu_level[i].MinVoltage = cpu_to_be16(table->entries[i].v);
921
922 pi->samu_level[i].ClkBypassCntl =
923 (u8)kv_get_clk_bypass(rdev, table->entries[i].clk);
924
925 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
926 table->entries[i].clk, false, &dividers);
927 if (ret)
928 return ret;
929 pi->samu_level[i].Divider = (u8)dividers.post_div;
930
931 pi->samu_level_count++;
932 }
933
934 ret = kv_copy_bytes_to_smc(rdev,
935 pi->dpm_table_start +
936 offsetof(SMU7_Fusion_DpmTable, SamuLevelCount),
937 (u8 *)&pi->samu_level_count,
938 sizeof(u8),
939 pi->sram_end);
940 if (ret)
941 return ret;
942
943 pi->samu_interval = 1;
944
945 ret = kv_copy_bytes_to_smc(rdev,
946 pi->dpm_table_start +
947 offsetof(SMU7_Fusion_DpmTable, SAMUInterval),
948 (u8 *)&pi->samu_interval,
949 sizeof(u8),
950 pi->sram_end);
951 if (ret)
952 return ret;
953
954 ret = kv_copy_bytes_to_smc(rdev,
955 pi->dpm_table_start +
956 offsetof(SMU7_Fusion_DpmTable, SamuLevel),
957 (u8 *)&pi->samu_level,
958 sizeof(SMU7_Fusion_ExtClkLevel) * SMU7_MAX_LEVELS_SAMU,
959 pi->sram_end);
960 if (ret)
961 return ret;
962
963 return ret;
964}
965
966
967static int kv_populate_acp_table(struct radeon_device *rdev)
968{
969 struct kv_power_info *pi = kv_get_pi(rdev);
970 struct radeon_clock_voltage_dependency_table *table =
971 &rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table;
972 struct atom_clock_dividers dividers;
973 int ret;
974 u32 i;
975
976 if (table == NULL || table->count == 0)
977 return 0;
978
979 pi->acp_level_count = 0;
980 for (i = 0; i < table->count; i++) {
981 pi->acp_level[i].Frequency = cpu_to_be32(table->entries[i].clk);
982 pi->acp_level[i].MinVoltage = cpu_to_be16(table->entries[i].v);
983
984 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
985 table->entries[i].clk, false, &dividers);
986 if (ret)
987 return ret;
988 pi->acp_level[i].Divider = (u8)dividers.post_div;
989
990 pi->acp_level_count++;
991 }
992
993 ret = kv_copy_bytes_to_smc(rdev,
994 pi->dpm_table_start +
995 offsetof(SMU7_Fusion_DpmTable, AcpLevelCount),
996 (u8 *)&pi->acp_level_count,
997 sizeof(u8),
998 pi->sram_end);
999 if (ret)
1000 return ret;
1001
1002 pi->acp_interval = 1;
1003
1004 ret = kv_copy_bytes_to_smc(rdev,
1005 pi->dpm_table_start +
1006 offsetof(SMU7_Fusion_DpmTable, ACPInterval),
1007 (u8 *)&pi->acp_interval,
1008 sizeof(u8),
1009 pi->sram_end);
1010 if (ret)
1011 return ret;
1012
1013 ret = kv_copy_bytes_to_smc(rdev,
1014 pi->dpm_table_start +
1015 offsetof(SMU7_Fusion_DpmTable, AcpLevel),
1016 (u8 *)&pi->acp_level,
1017 sizeof(SMU7_Fusion_ExtClkLevel) * SMU7_MAX_LEVELS_ACP,
1018 pi->sram_end);
1019 if (ret)
1020 return ret;
1021
1022 return ret;
1023}
1024
1025static void kv_calculate_dfs_bypass_settings(struct radeon_device *rdev)
1026{
1027 struct kv_power_info *pi = kv_get_pi(rdev);
1028 u32 i;
1029 struct radeon_clock_voltage_dependency_table *table =
1030 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
1031
1032 if (table && table->count) {
1033 for (i = 0; i < pi->graphics_dpm_level_count; i++) {
1034 if (pi->caps_enable_dfs_bypass) {
1035 if (kv_get_clock_difference(table->entries[i].clk, 40000) < 200)
1036 pi->graphics_level[i].ClkBypassCntl = 3;
1037 else if (kv_get_clock_difference(table->entries[i].clk, 30000) < 200)
1038 pi->graphics_level[i].ClkBypassCntl = 2;
1039 else if (kv_get_clock_difference(table->entries[i].clk, 26600) < 200)
1040 pi->graphics_level[i].ClkBypassCntl = 7;
1041 else if (kv_get_clock_difference(table->entries[i].clk , 20000) < 200)
1042 pi->graphics_level[i].ClkBypassCntl = 6;
1043 else if (kv_get_clock_difference(table->entries[i].clk , 10000) < 200)
1044 pi->graphics_level[i].ClkBypassCntl = 8;
1045 else
1046 pi->graphics_level[i].ClkBypassCntl = 0;
1047 } else {
1048 pi->graphics_level[i].ClkBypassCntl = 0;
1049 }
1050 }
1051 } else {
1052 struct sumo_sclk_voltage_mapping_table *table =
1053 &pi->sys_info.sclk_voltage_mapping_table;
1054 for (i = 0; i < pi->graphics_dpm_level_count; i++) {
1055 if (pi->caps_enable_dfs_bypass) {
1056 if (kv_get_clock_difference(table->entries[i].sclk_frequency, 40000) < 200)
1057 pi->graphics_level[i].ClkBypassCntl = 3;
1058 else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 30000) < 200)
1059 pi->graphics_level[i].ClkBypassCntl = 2;
1060 else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 26600) < 200)
1061 pi->graphics_level[i].ClkBypassCntl = 7;
1062 else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 20000) < 200)
1063 pi->graphics_level[i].ClkBypassCntl = 6;
1064 else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 10000) < 200)
1065 pi->graphics_level[i].ClkBypassCntl = 8;
1066 else
1067 pi->graphics_level[i].ClkBypassCntl = 0;
1068 } else {
1069 pi->graphics_level[i].ClkBypassCntl = 0;
1070 }
1071 }
1072 }
1073}
1074
1075static int kv_enable_ulv(struct radeon_device *rdev, bool enable)
1076{
1077 return kv_notify_message_to_smu(rdev, enable ?
1078 PPSMC_MSG_EnableULV : PPSMC_MSG_DisableULV);
1079}
1080
1081static void kv_update_current_ps(struct radeon_device *rdev,
1082 struct radeon_ps *rps)
1083{
1084 struct kv_ps *new_ps = kv_get_ps(rps);
1085 struct kv_power_info *pi = kv_get_pi(rdev);
1086
1087 pi->current_rps = *rps;
1088 pi->current_ps = *new_ps;
1089 pi->current_rps.ps_priv = &pi->current_ps;
1090}
1091
1092static void kv_update_requested_ps(struct radeon_device *rdev,
1093 struct radeon_ps *rps)
1094{
1095 struct kv_ps *new_ps = kv_get_ps(rps);
1096 struct kv_power_info *pi = kv_get_pi(rdev);
1097
1098 pi->requested_rps = *rps;
1099 pi->requested_ps = *new_ps;
1100 pi->requested_rps.ps_priv = &pi->requested_ps;
1101}
1102
1103int kv_dpm_enable(struct radeon_device *rdev)
1104{
1105 struct kv_power_info *pi = kv_get_pi(rdev);
1106 int ret;
1107
6500fc0c
AD		 1108 cik_update_cg(rdev, (RADEON_CG_BLOCK_GFX |
1109 RADEON_CG_BLOCK_SDMA |
1110 RADEON_CG_BLOCK_BIF |
1111 RADEON_CG_BLOCK_HDP), false);
1112
41a524ab
AD		 1113 ret = kv_process_firmware_header(rdev);
1114 if (ret) {
1115 DRM_ERROR("kv_process_firmware_header failed\n");
1116 return ret;
1117 }
1118 kv_init_fps_limits(rdev);
1119 kv_init_graphics_levels(rdev);
1120 ret = kv_program_bootup_state(rdev);
1121 if (ret) {
1122 DRM_ERROR("kv_program_bootup_state failed\n");
1123 return ret;
1124 }
1125 kv_calculate_dfs_bypass_settings(rdev);
1126 ret = kv_upload_dpm_settings(rdev);
1127 if (ret) {
1128 DRM_ERROR("kv_upload_dpm_settings failed\n");
1129 return ret;
1130 }
1131 ret = kv_populate_uvd_table(rdev);
1132 if (ret) {
1133 DRM_ERROR("kv_populate_uvd_table failed\n");
1134 return ret;
1135 }
1136 ret = kv_populate_vce_table(rdev);
1137 if (ret) {
1138 DRM_ERROR("kv_populate_vce_table failed\n");
1139 return ret;
1140 }
1141 ret = kv_populate_samu_table(rdev);
1142 if (ret) {
1143 DRM_ERROR("kv_populate_samu_table failed\n");
1144 return ret;
1145 }
1146 ret = kv_populate_acp_table(rdev);
1147 if (ret) {
1148 DRM_ERROR("kv_populate_acp_table failed\n");
1149 return ret;
1150 }
1151 kv_program_vc(rdev);
1152#if 0
1153 kv_initialize_hardware_cac_manager(rdev);
1154#endif
1155 kv_start_am(rdev);
1156 if (pi->enable_auto_thermal_throttling) {
1157 ret = kv_enable_auto_thermal_throttling(rdev);
1158 if (ret) {
1159 DRM_ERROR("kv_enable_auto_thermal_throttling failed\n");
1160 return ret;
1161 }
1162 }
1163 ret = kv_enable_dpm_voltage_scaling(rdev);
1164 if (ret) {
1165 DRM_ERROR("kv_enable_dpm_voltage_scaling failed\n");
1166 return ret;
1167 }
1168 ret = kv_set_dpm_interval(rdev);
1169 if (ret) {
1170 DRM_ERROR("kv_set_dpm_interval failed\n");
1171 return ret;
1172 }
1173 ret = kv_set_dpm_boot_state(rdev);
1174 if (ret) {
1175 DRM_ERROR("kv_set_dpm_boot_state failed\n");
1176 return ret;
1177 }
1178 ret = kv_enable_ulv(rdev, true);
1179 if (ret) {
1180 DRM_ERROR("kv_enable_ulv failed\n");
1181 return ret;
1182 }
1183 kv_start_dpm(rdev);
1184 ret = kv_enable_didt(rdev, true);
1185 if (ret) {
1186 DRM_ERROR("kv_enable_didt failed\n");
1187 return ret;
1188 }
1189 ret = kv_enable_smc_cac(rdev, true);
1190 if (ret) {
1191 DRM_ERROR("kv_enable_smc_cac failed\n");
1192 return ret;
1193 }
1194
1195 if (rdev->irq.installed &&
1196 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
1197 ret = kv_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
1198 if (ret) {
1199 DRM_ERROR("kv_set_thermal_temperature_range failed\n");
1200 return ret;
1201 }
1202 rdev->irq.dpm_thermal = true;
1203 radeon_irq_set(rdev);
1204 }
1205
1206 /* powerdown unused blocks for now */
1207 kv_dpm_powergate_acp(rdev, true);
1208 kv_dpm_powergate_samu(rdev, true);
1209 kv_dpm_powergate_vce(rdev, true);
77df508a 1210 kv_dpm_powergate_uvd(rdev, true);
41a524ab 1211
6500fc0c
AD		 1212 cik_update_cg(rdev, (RADEON_CG_BLOCK_GFX |
1213 RADEON_CG_BLOCK_SDMA |
1214 RADEON_CG_BLOCK_BIF |
1215 RADEON_CG_BLOCK_HDP), true);
1216
41a524ab
AD		 1217 kv_update_current_ps(rdev, rdev->pm.dpm.boot_ps);
1218
1219 return ret;
1220}
1221
1222void kv_dpm_disable(struct radeon_device *rdev)
1223{
6500fc0c
AD		 1224 cik_update_cg(rdev, (RADEON_CG_BLOCK_GFX |
1225 RADEON_CG_BLOCK_SDMA |
1226 RADEON_CG_BLOCK_BIF |
1227 RADEON_CG_BLOCK_HDP), false);
1228
39c88ae3
AD		 1229 /* powerup blocks */
1230 kv_dpm_powergate_acp(rdev, false);
1231 kv_dpm_powergate_samu(rdev, false);
1232 kv_dpm_powergate_vce(rdev, false);
1233 kv_dpm_powergate_uvd(rdev, false);
1234
41a524ab
AD		 1235 kv_enable_smc_cac(rdev, false);
1236 kv_enable_didt(rdev, false);
1237 kv_clear_vc(rdev);
1238 kv_stop_dpm(rdev);
1239 kv_enable_ulv(rdev, false);
1240 kv_reset_am(rdev);
1241
1242 kv_update_current_ps(rdev, rdev->pm.dpm.boot_ps);
1243}
1244
1245#if 0
1246static int kv_write_smc_soft_register(struct radeon_device *rdev,
1247 u16 reg_offset, u32 value)
1248{
1249 struct kv_power_info *pi = kv_get_pi(rdev);
1250
1251 return kv_copy_bytes_to_smc(rdev, pi->soft_regs_start + reg_offset,
1252 (u8 *)&value, sizeof(u16), pi->sram_end);
1253}
1254
1255static int kv_read_smc_soft_register(struct radeon_device *rdev,
1256 u16 reg_offset, u32 *value)
1257{
1258 struct kv_power_info *pi = kv_get_pi(rdev);
1259
1260 return kv_read_smc_sram_dword(rdev, pi->soft_regs_start + reg_offset,
1261 value, pi->sram_end);
1262}
1263#endif
1264
1265static void kv_init_sclk_t(struct radeon_device *rdev)
1266{
1267 struct kv_power_info *pi = kv_get_pi(rdev);
1268
1269 pi->low_sclk_interrupt_t = 0;
1270}
1271
1272static int kv_init_fps_limits(struct radeon_device *rdev)
1273{
1274 struct kv_power_info *pi = kv_get_pi(rdev);
1275 int ret = 0;
1276
1277 if (pi->caps_fps) {
1278 u16 tmp;
1279
1280 tmp = 45;
1281 pi->fps_high_t = cpu_to_be16(tmp);
1282 ret = kv_copy_bytes_to_smc(rdev,
1283 pi->dpm_table_start +
1284 offsetof(SMU7_Fusion_DpmTable, FpsHighT),
1285 (u8 *)&pi->fps_high_t,
1286 sizeof(u16), pi->sram_end);
1287
1288 tmp = 30;
1289 pi->fps_low_t = cpu_to_be16(tmp);
1290
1291 ret = kv_copy_bytes_to_smc(rdev,
1292 pi->dpm_table_start +
1293 offsetof(SMU7_Fusion_DpmTable, FpsLowT),
1294 (u8 *)&pi->fps_low_t,
1295 sizeof(u16), pi->sram_end);
1296
1297 }
1298 return ret;
1299}
1300
1301static void kv_init_powergate_state(struct radeon_device *rdev)
1302{
1303 struct kv_power_info *pi = kv_get_pi(rdev);
1304
1305 pi->uvd_power_gated = false;
1306 pi->vce_power_gated = false;
1307 pi->samu_power_gated = false;
1308 pi->acp_power_gated = false;
1309
1310}
1311
1312static int kv_enable_uvd_dpm(struct radeon_device *rdev, bool enable)
1313{
1314 return kv_notify_message_to_smu(rdev, enable ?
1315 PPSMC_MSG_UVDDPM_Enable : PPSMC_MSG_UVDDPM_Disable);
1316}
1317
1318#if 0
1319static int kv_enable_vce_dpm(struct radeon_device *rdev, bool enable)
1320{
1321 return kv_notify_message_to_smu(rdev, enable ?
1322 PPSMC_MSG_VCEDPM_Enable : PPSMC_MSG_VCEDPM_Disable);
1323}
1324#endif
1325
1326static int kv_enable_samu_dpm(struct radeon_device *rdev, bool enable)
1327{
1328 return kv_notify_message_to_smu(rdev, enable ?
1329 PPSMC_MSG_SAMUDPM_Enable : PPSMC_MSG_SAMUDPM_Disable);
1330}
1331
1332static int kv_enable_acp_dpm(struct radeon_device *rdev, bool enable)
1333{
1334 return kv_notify_message_to_smu(rdev, enable ?
1335 PPSMC_MSG_ACPDPM_Enable : PPSMC_MSG_ACPDPM_Disable);
1336}
1337
1338static int kv_update_uvd_dpm(struct radeon_device *rdev, bool gate)
1339{
1340 struct kv_power_info *pi = kv_get_pi(rdev);
1341 struct radeon_uvd_clock_voltage_dependency_table *table =
1342 &rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;
1343 int ret;
1344
1345 if (!gate) {
1346 if (!pi->caps_uvd_dpm || table->count || pi->caps_stable_p_state)
1347 pi->uvd_boot_level = table->count - 1;
1348 else
1349 pi->uvd_boot_level = 0;
1350
1351 ret = kv_copy_bytes_to_smc(rdev,
1352 pi->dpm_table_start +
1353 offsetof(SMU7_Fusion_DpmTable, UvdBootLevel),
1354 (uint8_t *)&pi->uvd_boot_level,
1355 sizeof(u8), pi->sram_end);
1356 if (ret)
1357 return ret;
1358
1359 if (!pi->caps_uvd_dpm ||
1360 pi->caps_stable_p_state)
1361 kv_send_msg_to_smc_with_parameter(rdev,
1362 PPSMC_MSG_UVDDPM_SetEnabledMask,
1363 (1 << pi->uvd_boot_level));
1364 }
1365
1366 return kv_enable_uvd_dpm(rdev, !gate);
1367}
1368
1369#if 0
1370static u8 kv_get_vce_boot_level(struct radeon_device *rdev)
1371{
1372 u8 i;
1373 struct radeon_vce_clock_voltage_dependency_table *table =
1374 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
1375
1376 for (i = 0; i < table->count; i++) {
1377 if (table->entries[i].evclk >= 0) /* XXX */
1378 break;
1379 }
1380
1381 return i;
1382}
1383
1384static int kv_update_vce_dpm(struct radeon_device *rdev,
1385 struct radeon_ps *radeon_new_state,
1386 struct radeon_ps *radeon_current_state)
1387{
1388 struct kv_power_info *pi = kv_get_pi(rdev);
1389 struct radeon_vce_clock_voltage_dependency_table *table =
1390 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
1391 int ret;
1392
1393 if (radeon_new_state->evclk > 0 && radeon_current_state->evclk == 0) {
1394 if (pi->caps_stable_p_state)
1395 pi->vce_boot_level = table->count - 1;
1396 else
1397 pi->vce_boot_level = kv_get_vce_boot_level(rdev);
1398
1399 ret = kv_copy_bytes_to_smc(rdev,
1400 pi->dpm_table_start +
1401 offsetof(SMU7_Fusion_DpmTable, VceBootLevel),
1402 (u8 *)&pi->vce_boot_level,
1403 sizeof(u8),
1404 pi->sram_end);
1405 if (ret)
1406 return ret;
1407
1408 if (pi->caps_stable_p_state)
1409 kv_send_msg_to_smc_with_parameter(rdev,
1410 PPSMC_MSG_VCEDPM_SetEnabledMask,
1411 (1 << pi->vce_boot_level));
1412
1413 kv_enable_vce_dpm(rdev, true);
1414 } else if (radeon_new_state->evclk == 0 && radeon_current_state->evclk > 0) {
1415 kv_enable_vce_dpm(rdev, false);
1416 }
1417
1418 return 0;
1419}
1420#endif
1421
1422static int kv_update_samu_dpm(struct radeon_device *rdev, bool gate)
1423{
1424 struct kv_power_info *pi = kv_get_pi(rdev);
1425 struct radeon_clock_voltage_dependency_table *table =
1426 &rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table;
1427 int ret;
1428
1429 if (!gate) {
1430 if (pi->caps_stable_p_state)
1431 pi->samu_boot_level = table->count - 1;
1432 else
1433 pi->samu_boot_level = 0;
1434
1435 ret = kv_copy_bytes_to_smc(rdev,
1436 pi->dpm_table_start +
1437 offsetof(SMU7_Fusion_DpmTable, SamuBootLevel),
1438 (u8 *)&pi->samu_boot_level,
1439 sizeof(u8),
1440 pi->sram_end);
1441 if (ret)
1442 return ret;
1443
1444 if (pi->caps_stable_p_state)
1445 kv_send_msg_to_smc_with_parameter(rdev,
1446 PPSMC_MSG_SAMUDPM_SetEnabledMask,
1447 (1 << pi->samu_boot_level));
1448 }
1449
1450 return kv_enable_samu_dpm(rdev, !gate);
1451}
1452
1453static int kv_update_acp_dpm(struct radeon_device *rdev, bool gate)
1454{
1455 struct kv_power_info *pi = kv_get_pi(rdev);
1456 struct radeon_clock_voltage_dependency_table *table =
1457 &rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table;
1458 int ret;
1459
1460 if (!gate) {
1461 if (pi->caps_stable_p_state)
1462 pi->acp_boot_level = table->count - 1;
1463 else
1464 pi->acp_boot_level = 0;
1465
1466 ret = kv_copy_bytes_to_smc(rdev,
1467 pi->dpm_table_start +
1468 offsetof(SMU7_Fusion_DpmTable, AcpBootLevel),
1469 (u8 *)&pi->acp_boot_level,
1470 sizeof(u8),
1471 pi->sram_end);
1472 if (ret)
1473 return ret;
1474
1475 if (pi->caps_stable_p_state)
1476 kv_send_msg_to_smc_with_parameter(rdev,
1477 PPSMC_MSG_ACPDPM_SetEnabledMask,
1478 (1 << pi->acp_boot_level));
1479 }
1480
1481 return kv_enable_acp_dpm(rdev, !gate);
1482}
1483
77df508a 1484void kv_dpm_powergate_uvd(struct radeon_device *rdev, bool gate)
41a524ab
AD		 1485{
1486 struct kv_power_info *pi = kv_get_pi(rdev);
1487
1488 if (pi->uvd_power_gated == gate)
1489 return;
1490
1491 pi->uvd_power_gated = gate;
1492
1493 if (gate) {
f30df435
AD		 1494 if (pi->caps_uvd_pg) {
1495 uvd_v1_0_stop(rdev);
1496 cik_update_cg(rdev, RADEON_CG_BLOCK_UVD, false);
1497 }
77df508a 1498 kv_update_uvd_dpm(rdev, gate);
41a524ab
AD		 1499 if (pi->caps_uvd_pg)
1500 kv_notify_message_to_smu(rdev, PPSMC_MSG_UVDPowerOFF);
1501 } else {
f30df435 1502 if (pi->caps_uvd_pg) {
41a524ab 1503 kv_notify_message_to_smu(rdev, PPSMC_MSG_UVDPowerON);
f30df435
AD		 1504 uvd_v4_2_resume(rdev);
1505 uvd_v1_0_start(rdev);
1506 cik_update_cg(rdev, RADEON_CG_BLOCK_UVD, true);
1507 }
77df508a 1508 kv_update_uvd_dpm(rdev, gate);
41a524ab
AD		 1509 }
1510}
1511
1512static void kv_dpm_powergate_vce(struct radeon_device *rdev, bool gate)
1513{
1514 struct kv_power_info *pi = kv_get_pi(rdev);
1515
1516 if (pi->vce_power_gated == gate)
1517 return;
1518
1519 pi->vce_power_gated = gate;
1520
1521 if (gate) {
1522 if (pi->caps_vce_pg)
1523 kv_notify_message_to_smu(rdev, PPSMC_MSG_VCEPowerOFF);
1524 } else {
1525 if (pi->caps_vce_pg)
1526 kv_notify_message_to_smu(rdev, PPSMC_MSG_VCEPowerON);
1527 }
1528}
1529
1530static void kv_dpm_powergate_samu(struct radeon_device *rdev, bool gate)
1531{
1532 struct kv_power_info *pi = kv_get_pi(rdev);
1533
1534 if (pi->samu_power_gated == gate)
1535 return;
1536
1537 pi->samu_power_gated = gate;
1538
1539 if (gate) {
1540 kv_update_samu_dpm(rdev, true);
1541 if (pi->caps_samu_pg)
1542 kv_notify_message_to_smu(rdev, PPSMC_MSG_SAMPowerOFF);
1543 } else {
1544 if (pi->caps_samu_pg)
1545 kv_notify_message_to_smu(rdev, PPSMC_MSG_SAMPowerON);
1546 kv_update_samu_dpm(rdev, false);
1547 }
1548}
1549
1550static void kv_dpm_powergate_acp(struct radeon_device *rdev, bool gate)
1551{
1552 struct kv_power_info *pi = kv_get_pi(rdev);
1553
1554 if (pi->acp_power_gated == gate)
1555 return;
1556
1557 if (rdev->family == CHIP_KABINI)
1558 return;
1559
1560 pi->acp_power_gated = gate;
1561
1562 if (gate) {
1563 kv_update_acp_dpm(rdev, true);
1564 if (pi->caps_acp_pg)
1565 kv_notify_message_to_smu(rdev, PPSMC_MSG_ACPPowerOFF);
1566 } else {
1567 if (pi->caps_acp_pg)
1568 kv_notify_message_to_smu(rdev, PPSMC_MSG_ACPPowerON);
1569 kv_update_acp_dpm(rdev, false);
1570 }
1571}
1572
1573static void kv_set_valid_clock_range(struct radeon_device *rdev,
1574 struct radeon_ps *new_rps)
1575{
1576 struct kv_ps *new_ps = kv_get_ps(new_rps);
1577 struct kv_power_info *pi = kv_get_pi(rdev);
1578 u32 i;
1579 struct radeon_clock_voltage_dependency_table *table =
1580 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
1581
1582 if (table && table->count) {
1583 for (i = 0; i < pi->graphics_dpm_level_count; i++) {
1584 if ((table->entries[i].clk >= new_ps->levels[0].sclk) ||
1585 (i == (pi->graphics_dpm_level_count - 1))) {
1586 pi->lowest_valid = i;
1587 break;
1588 }
1589 }
1590
1591 for (i = pi->graphics_dpm_level_count - 1; i >= 0; i--) {
1592 if ((table->entries[i].clk <= new_ps->levels[new_ps->num_levels -1].sclk) ||
1593 (i == 0)) {
1594 pi->highest_valid = i;
1595 break;
1596 }
1597 }
1598
1599 if (pi->lowest_valid > pi->highest_valid) {
1600 if ((new_ps->levels[0].sclk - table->entries[pi->highest_valid].clk) >
1601 (table->entries[pi->lowest_valid].clk - new_ps->levels[new_ps->num_levels - 1].sclk))
1602 pi->highest_valid = pi->lowest_valid;
1603 else
1604 pi->lowest_valid = pi->highest_valid;
1605 }
1606 } else {
1607 struct sumo_sclk_voltage_mapping_table *table =
1608 &pi->sys_info.sclk_voltage_mapping_table;
1609
1610 for (i = 0; i < (int)pi->graphics_dpm_level_count; i++) {
1611 if (table->entries[i].sclk_frequency >= new_ps->levels[0].sclk ||
1612 i == (int)(pi->graphics_dpm_level_count - 1)) {
1613 pi->lowest_valid = i;
1614 break;
1615 }
1616 }
1617
1618 for (i = pi->graphics_dpm_level_count - 1; i >= 0; i--) {
1619 if (table->entries[i].sclk_frequency <=
1620 new_ps->levels[new_ps->num_levels - 1].sclk ||
1621 i == 0) {
1622 pi->highest_valid = i;
1623 break;
1624 }
1625 }
1626
1627 if (pi->lowest_valid > pi->highest_valid) {
1628 if ((new_ps->levels[0].sclk -
1629 table->entries[pi->highest_valid].sclk_frequency) >
1630 (table->entries[pi->lowest_valid].sclk_frequency -
1631 new_ps->levels[new_ps->num_levels -1].sclk))
1632 pi->highest_valid = pi->lowest_valid;
1633 else
1634 pi->lowest_valid = pi->highest_valid;
1635 }
1636 }
1637}
1638
1639static int kv_update_dfs_bypass_settings(struct radeon_device *rdev,
1640 struct radeon_ps *new_rps)
1641{
1642 struct kv_ps *new_ps = kv_get_ps(new_rps);
1643 struct kv_power_info *pi = kv_get_pi(rdev);
1644 int ret = 0;
1645 u8 clk_bypass_cntl;
1646
1647 if (pi->caps_enable_dfs_bypass) {
1648 clk_bypass_cntl = new_ps->need_dfs_bypass ?
1649 pi->graphics_level[pi->graphics_boot_level].ClkBypassCntl : 0;
1650 ret = kv_copy_bytes_to_smc(rdev,
1651 (pi->dpm_table_start +
1652 offsetof(SMU7_Fusion_DpmTable, GraphicsLevel) +
1653 (pi->graphics_boot_level * sizeof(SMU7_Fusion_GraphicsLevel)) +
1654 offsetof(SMU7_Fusion_GraphicsLevel, ClkBypassCntl)),
1655 &clk_bypass_cntl,
1656 sizeof(u8), pi->sram_end);
1657 }
1658
1659 return ret;
1660}
1661
1662static int kv_enable_nb_dpm(struct radeon_device *rdev)
1663{
1664 struct kv_power_info *pi = kv_get_pi(rdev);
1665 int ret = 0;
1666
1667 if (pi->enable_nb_dpm && !pi->nb_dpm_enabled) {
1668 ret = kv_notify_message_to_smu(rdev, PPSMC_MSG_NBDPM_Enable);
1669 if (ret == 0)
1670 pi->nb_dpm_enabled = true;
1671 }
1672
1673 return ret;
1674}
1675
2b4c8022
AD		 1676int kv_dpm_force_performance_level(struct radeon_device *rdev,
1677 enum radeon_dpm_forced_level level)
1678{
1679 int ret;
1680
1681 if (level == RADEON_DPM_FORCED_LEVEL_HIGH) {
1682 ret = kv_force_dpm_highest(rdev);
1683 if (ret)
1684 return ret;
1685 } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) {
1686 ret = kv_force_dpm_lowest(rdev);
1687 if (ret)
1688 return ret;
1689 } else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) {
1690 ret = kv_unforce_levels(rdev);
1691 if (ret)
1692 return ret;
1693 }
1694
1695 rdev->pm.dpm.forced_level = level;
1696
1697 return 0;
1698}
1699
41a524ab
AD		 1700int kv_dpm_pre_set_power_state(struct radeon_device *rdev)
1701{
1702 struct kv_power_info *pi = kv_get_pi(rdev);
1703 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps;
1704 struct radeon_ps *new_ps = &requested_ps;
1705
1706 kv_update_requested_ps(rdev, new_ps);
1707
1708 kv_apply_state_adjust_rules(rdev,
1709 &pi->requested_rps,
1710 &pi->current_rps);
1711
1712 return 0;
1713}
1714
1715int kv_dpm_set_power_state(struct radeon_device *rdev)
1716{
1717 struct kv_power_info *pi = kv_get_pi(rdev);
1718 struct radeon_ps *new_ps = &pi->requested_rps;
1719 /*struct radeon_ps *old_ps = &pi->current_rps;*/
1720 int ret;
1721
6500fc0c
AD		 1722 cik_update_cg(rdev, (RADEON_CG_BLOCK_GFX |
1723 RADEON_CG_BLOCK_SDMA |
1724 RADEON_CG_BLOCK_BIF |
1725 RADEON_CG_BLOCK_HDP), false);
1726
41a524ab
AD		 1727 if (rdev->family == CHIP_KABINI) {
1728 if (pi->enable_dpm) {
1729 kv_set_valid_clock_range(rdev, new_ps);
1730 kv_update_dfs_bypass_settings(rdev, new_ps);
1731 ret = kv_calculate_ds_divider(rdev);
1732 if (ret) {
1733 DRM_ERROR("kv_calculate_ds_divider failed\n");
1734 return ret;
1735 }
1736 kv_calculate_nbps_level_settings(rdev);
1737 kv_calculate_dpm_settings(rdev);
1738 kv_force_lowest_valid(rdev);
1739 kv_enable_new_levels(rdev);
1740 kv_upload_dpm_settings(rdev);
1741 kv_program_nbps_index_settings(rdev, new_ps);
1742 kv_unforce_levels(rdev);
1743 kv_set_enabled_levels(rdev);
1744 kv_force_lowest_valid(rdev);
1745 kv_unforce_levels(rdev);
1746#if 0
1747 ret = kv_update_vce_dpm(rdev, new_ps, old_ps);
1748 if (ret) {
1749 DRM_ERROR("kv_update_vce_dpm failed\n");
1750 return ret;
1751 }
1752#endif
41a524ab
AD		 1753 kv_update_sclk_t(rdev);
1754 }
1755 } else {
1756 if (pi->enable_dpm) {
1757 kv_set_valid_clock_range(rdev, new_ps);
1758 kv_update_dfs_bypass_settings(rdev, new_ps);
1759 ret = kv_calculate_ds_divider(rdev);
1760 if (ret) {
1761 DRM_ERROR("kv_calculate_ds_divider failed\n");
1762 return ret;
1763 }
1764 kv_calculate_nbps_level_settings(rdev);
1765 kv_calculate_dpm_settings(rdev);
1766 kv_freeze_sclk_dpm(rdev, true);
1767 kv_upload_dpm_settings(rdev);
1768 kv_program_nbps_index_settings(rdev, new_ps);
1769 kv_freeze_sclk_dpm(rdev, false);
1770 kv_set_enabled_levels(rdev);
1771#if 0
1772 ret = kv_update_vce_dpm(rdev, new_ps, old_ps);
1773 if (ret) {
1774 DRM_ERROR("kv_update_vce_dpm failed\n");
1775 return ret;
1776 }
1777#endif
41a524ab
AD		 1778 kv_update_sclk_t(rdev);
1779 kv_enable_nb_dpm(rdev);
1780 }
1781 }
6500fc0c
AD		 1782
1783 cik_update_cg(rdev, (RADEON_CG_BLOCK_GFX |
1784 RADEON_CG_BLOCK_SDMA |
1785 RADEON_CG_BLOCK_BIF |
1786 RADEON_CG_BLOCK_HDP), true);
1787
2b4c8022 1788 rdev->pm.dpm.forced_level = RADEON_DPM_FORCED_LEVEL_AUTO;
41a524ab
AD		 1789 return 0;
1790}
1791
1792void kv_dpm_post_set_power_state(struct radeon_device *rdev)
1793{
1794 struct kv_power_info *pi = kv_get_pi(rdev);
1795 struct radeon_ps *new_ps = &pi->requested_rps;
1796
1797 kv_update_current_ps(rdev, new_ps);
1798}
1799
1800void kv_dpm_setup_asic(struct radeon_device *rdev)
1801{
1802 sumo_take_smu_control(rdev, true);
1803 kv_init_powergate_state(rdev);
1804 kv_init_sclk_t(rdev);
1805}
1806
1807void kv_dpm_reset_asic(struct radeon_device *rdev)
1808{
1809 kv_force_lowest_valid(rdev);
1810 kv_init_graphics_levels(rdev);
1811 kv_program_bootup_state(rdev);
1812 kv_upload_dpm_settings(rdev);
1813 kv_force_lowest_valid(rdev);
1814 kv_unforce_levels(rdev);
1815}
1816
1817//XXX use sumo_dpm_display_configuration_changed
1818
1819static void kv_construct_max_power_limits_table(struct radeon_device *rdev,
1820 struct radeon_clock_and_voltage_limits *table)
1821{
1822 struct kv_power_info *pi = kv_get_pi(rdev);
1823
1824 if (pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries > 0) {
1825 int idx = pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries - 1;
1826 table->sclk =
1827 pi->sys_info.sclk_voltage_mapping_table.entries[idx].sclk_frequency;
1828 table->vddc =
1829 kv_convert_2bit_index_to_voltage(rdev,
1830 pi->sys_info.sclk_voltage_mapping_table.entries[idx].vid_2bit);
1831 }
1832
1833 table->mclk = pi->sys_info.nbp_memory_clock[0];
1834}
1835
1836static void kv_patch_voltage_values(struct radeon_device *rdev)
1837{
1838 int i;
1839 struct radeon_uvd_clock_voltage_dependency_table *table =
1840 &rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;
1841
1842 if (table->count) {
1843 for (i = 0; i < table->count; i++)
1844 table->entries[i].v =
1845 kv_convert_8bit_index_to_voltage(rdev,
1846 table->entries[i].v);
1847 }
1848
1849}
1850
1851static void kv_construct_boot_state(struct radeon_device *rdev)
1852{
1853 struct kv_power_info *pi = kv_get_pi(rdev);
1854
1855 pi->boot_pl.sclk = pi->sys_info.bootup_sclk;
1856 pi->boot_pl.vddc_index = pi->sys_info.bootup_nb_voltage_index;
1857 pi->boot_pl.ds_divider_index = 0;
1858 pi->boot_pl.ss_divider_index = 0;
1859 pi->boot_pl.allow_gnb_slow = 1;
1860 pi->boot_pl.force_nbp_state = 0;
1861 pi->boot_pl.display_wm = 0;
1862 pi->boot_pl.vce_wm = 0;
1863}
1864
2b4c8022
AD		 1865static int kv_force_dpm_highest(struct radeon_device *rdev)
1866{
1867 int ret;
1868 u32 enable_mask, i;
1869
1870 ret = kv_dpm_get_enable_mask(rdev, &enable_mask);
1871 if (ret)
1872 return ret;
1873
1874 for (i = SMU7_MAX_LEVELS_GRAPHICS - 1; i >= 0; i--) {
1875 if (enable_mask & (1 << i))
1876 break;
1877 }
1878
1879 return kv_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_DPM_ForceState, i);
1880}
1881
41a524ab
AD		 1882static int kv_force_dpm_lowest(struct radeon_device *rdev)
1883{
1884 int ret;
1885 u32 enable_mask, i;
1886
1887 ret = kv_dpm_get_enable_mask(rdev, &enable_mask);
1888 if (ret)
1889 return ret;
1890
1891 for (i = 0; i < SMU7_MAX_LEVELS_GRAPHICS; i++) {
1892 if (enable_mask & (1 << i))
1893 break;
1894 }
1895
1896 return kv_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_DPM_ForceState, i);
1897}
1898
1899static u8 kv_get_sleep_divider_id_from_clock(struct radeon_device *rdev,
1900 u32 sclk, u32 min_sclk_in_sr)
1901{
1902 struct kv_power_info *pi = kv_get_pi(rdev);
1903 u32 i;
1904 u32 temp;
1905 u32 min = (min_sclk_in_sr > KV_MINIMUM_ENGINE_CLOCK) ?
1906 min_sclk_in_sr : KV_MINIMUM_ENGINE_CLOCK;
1907
1908 if (sclk < min)
1909 return 0;
1910
1911 if (!pi->caps_sclk_ds)
1912 return 0;
1913
1914 for (i = KV_MAX_DEEPSLEEP_DIVIDER_ID; i <= 0; i--) {
1915 temp = sclk / sumo_get_sleep_divider_from_id(i);
1916 if ((temp >= min) || (i == 0))
1917 break;
1918 }
1919
1920 return (u8)i;
1921}
1922
1923static int kv_get_high_voltage_limit(struct radeon_device *rdev, int *limit)
1924{
1925 struct kv_power_info *pi = kv_get_pi(rdev);
1926 struct radeon_clock_voltage_dependency_table *table =
1927 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
1928 int i;
1929
1930 if (table && table->count) {
1931 for (i = table->count - 1; i >= 0; i--) {
1932 if (pi->high_voltage_t &&
1933 (kv_convert_8bit_index_to_voltage(rdev, table->entries[i].v) <=
1934 pi->high_voltage_t)) {
1935 *limit = i;
1936 return 0;
1937 }
1938 }
1939 } else {
1940 struct sumo_sclk_voltage_mapping_table *table =
1941 &pi->sys_info.sclk_voltage_mapping_table;
1942
1943 for (i = table->num_max_dpm_entries - 1; i >= 0; i--) {
1944 if (pi->high_voltage_t &&
1945 (kv_convert_2bit_index_to_voltage(rdev, table->entries[i].vid_2bit) <=
1946 pi->high_voltage_t)) {
1947 *limit = i;
1948 return 0;
1949 }
1950 }
1951 }
1952
1953 *limit = 0;
1954 return 0;
1955}
1956
1957static void kv_apply_state_adjust_rules(struct radeon_device *rdev,
1958 struct radeon_ps *new_rps,
1959 struct radeon_ps *old_rps)
1960{
1961 struct kv_ps *ps = kv_get_ps(new_rps);
1962 struct kv_power_info *pi = kv_get_pi(rdev);
1963 u32 min_sclk = 10000; /* ??? */
1964 u32 sclk, mclk = 0;
1965 int i, limit;
1966 bool force_high;
1967 struct radeon_clock_voltage_dependency_table *table =
1968 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
1969 u32 stable_p_state_sclk = 0;
1970 struct radeon_clock_and_voltage_limits *max_limits =
1971 &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
1972
1973 mclk = max_limits->mclk;
1974 sclk = min_sclk;
1975
1976 if (pi->caps_stable_p_state) {
1977 stable_p_state_sclk = (max_limits->sclk * 75) / 100;
1978
1979 for (i = table->count - 1; i >= 0; i++) {
1980 if (stable_p_state_sclk >= table->entries[i].clk) {
1981 stable_p_state_sclk = table->entries[i].clk;
1982 break;
1983 }
1984 }
1985
1986 if (i > 0)
1987 stable_p_state_sclk = table->entries[0].clk;
1988
1989 sclk = stable_p_state_sclk;
1990 }
1991
1992 ps->need_dfs_bypass = true;
1993
1994 for (i = 0; i < ps->num_levels; i++) {
1995 if (ps->levels[i].sclk < sclk)
1996 ps->levels[i].sclk = sclk;
1997 }
1998
1999 if (table && table->count) {
2000 for (i = 0; i < ps->num_levels; i++) {
2001 if (pi->high_voltage_t &&
2002 (pi->high_voltage_t <
2003 kv_convert_8bit_index_to_voltage(rdev, ps->levels[i].vddc_index))) {
2004 kv_get_high_voltage_limit(rdev, &limit);
2005 ps->levels[i].sclk = table->entries[limit].clk;
2006 }
2007 }
2008 } else {
2009 struct sumo_sclk_voltage_mapping_table *table =
2010 &pi->sys_info.sclk_voltage_mapping_table;
2011
2012 for (i = 0; i < ps->num_levels; i++) {
2013 if (pi->high_voltage_t &&
2014 (pi->high_voltage_t <
2015 kv_convert_8bit_index_to_voltage(rdev, ps->levels[i].vddc_index))) {
2016 kv_get_high_voltage_limit(rdev, &limit);
2017 ps->levels[i].sclk = table->entries[limit].sclk_frequency;
2018 }
2019 }
2020 }
2021
2022 if (pi->caps_stable_p_state) {
2023 for (i = 0; i < ps->num_levels; i++) {
2024 ps->levels[i].sclk = stable_p_state_sclk;
2025 }
2026 }
2027
2028 pi->video_start = new_rps->dclk || new_rps->vclk;
2029
2030 if ((new_rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) ==
2031 ATOM_PPLIB_CLASSIFICATION_UI_BATTERY)
2032 pi->battery_state = true;
2033 else
2034 pi->battery_state = false;
2035
2036 if (rdev->family == CHIP_KABINI) {
2037 ps->dpm0_pg_nb_ps_lo = 0x1;
2038 ps->dpm0_pg_nb_ps_hi = 0x0;
2039 ps->dpmx_nb_ps_lo = 0x1;
2040 ps->dpmx_nb_ps_hi = 0x0;
2041 } else {
2042 ps->dpm0_pg_nb_ps_lo = 0x1;
2043 ps->dpm0_pg_nb_ps_hi = 0x0;
2044 ps->dpmx_nb_ps_lo = 0x2;
2045 ps->dpmx_nb_ps_hi = 0x1;
2046
2047 if (pi->sys_info.nb_dpm_enable && pi->battery_state) {
2048 force_high = (mclk >= pi->sys_info.nbp_memory_clock[3]) ||
2049 pi->video_start || (rdev->pm.dpm.new_active_crtc_count >= 3) ||
2050 pi->disable_nb_ps3_in_battery;
2051 ps->dpm0_pg_nb_ps_lo = force_high ? 0x2 : 0x3;
2052 ps->dpm0_pg_nb_ps_hi = 0x2;
2053 ps->dpmx_nb_ps_lo = force_high ? 0x2 : 0x3;
2054 ps->dpmx_nb_ps_hi = 0x2;
2055 }
2056 }
2057}
2058
2059static void kv_dpm_power_level_enabled_for_throttle(struct radeon_device *rdev,
2060 u32 index, bool enable)
2061{
2062 struct kv_power_info *pi = kv_get_pi(rdev);
2063
2064 pi->graphics_level[index].EnabledForThrottle = enable ? 1 : 0;
2065}
2066
2067static int kv_calculate_ds_divider(struct radeon_device *rdev)
2068{
2069 struct kv_power_info *pi = kv_get_pi(rdev);
2070 u32 sclk_in_sr = 10000; /* ??? */
2071 u32 i;
2072
2073 if (pi->lowest_valid > pi->highest_valid)
2074 return -EINVAL;
2075
2076 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) {
2077 pi->graphics_level[i].DeepSleepDivId =
2078 kv_get_sleep_divider_id_from_clock(rdev,
2079 be32_to_cpu(pi->graphics_level[i].SclkFrequency),
2080 sclk_in_sr);
2081 }
2082 return 0;
2083}
2084
2085static int kv_calculate_nbps_level_settings(struct radeon_device *rdev)
2086{
2087 struct kv_power_info *pi = kv_get_pi(rdev);
2088 u32 i;
2089 bool force_high;
2090 struct radeon_clock_and_voltage_limits *max_limits =
2091 &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
2092 u32 mclk = max_limits->mclk;
2093
2094 if (pi->lowest_valid > pi->highest_valid)
2095 return -EINVAL;
2096
2097 if (rdev->family == CHIP_KABINI) {
2098 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) {
2099 pi->graphics_level[i].GnbSlow = 1;
2100 pi->graphics_level[i].ForceNbPs1 = 0;
2101 pi->graphics_level[i].UpH = 0;
2102 }
2103
2104 if (!pi->sys_info.nb_dpm_enable)
2105 return 0;
2106
2107 force_high = ((mclk >= pi->sys_info.nbp_memory_clock[3]) ||
2108 (rdev->pm.dpm.new_active_crtc_count >= 3) || pi->video_start);
2109
2110 if (force_high) {
2111 for (i = pi->lowest_valid; i <= pi->highest_valid; i++)
2112 pi->graphics_level[i].GnbSlow = 0;
2113 } else {
2114 if (pi->battery_state)
2115 pi->graphics_level[0].ForceNbPs1 = 1;
2116
2117 pi->graphics_level[1].GnbSlow = 0;
2118 pi->graphics_level[2].GnbSlow = 0;
2119 pi->graphics_level[3].GnbSlow = 0;
2120 pi->graphics_level[4].GnbSlow = 0;
2121 }
2122 } else {
2123 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) {
2124 pi->graphics_level[i].GnbSlow = 1;
2125 pi->graphics_level[i].ForceNbPs1 = 0;
2126 pi->graphics_level[i].UpH = 0;
2127 }
2128
2129 if (pi->sys_info.nb_dpm_enable && pi->battery_state) {
2130 pi->graphics_level[pi->lowest_valid].UpH = 0x28;
2131 pi->graphics_level[pi->lowest_valid].GnbSlow = 0;
2132 if (pi->lowest_valid != pi->highest_valid)
2133 pi->graphics_level[pi->lowest_valid].ForceNbPs1 = 1;
2134 }
2135 }
2136 return 0;
2137}
2138
2139static int kv_calculate_dpm_settings(struct radeon_device *rdev)
2140{
2141 struct kv_power_info *pi = kv_get_pi(rdev);
2142 u32 i;
2143
2144 if (pi->lowest_valid > pi->highest_valid)
2145 return -EINVAL;
2146
2147 for (i = pi->lowest_valid; i <= pi->highest_valid; i++)
2148 pi->graphics_level[i].DisplayWatermark = (i == pi->highest_valid) ? 1 : 0;
2149
2150 return 0;
2151}
2152
2153static void kv_init_graphics_levels(struct radeon_device *rdev)
2154{
2155 struct kv_power_info *pi = kv_get_pi(rdev);
2156 u32 i;
2157 struct radeon_clock_voltage_dependency_table *table =
2158 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
2159
2160 if (table && table->count) {
2161 u32 vid_2bit;
2162
2163 pi->graphics_dpm_level_count = 0;
2164 for (i = 0; i < table->count; i++) {
2165 if (pi->high_voltage_t &&
2166 (pi->high_voltage_t <
2167 kv_convert_8bit_index_to_voltage(rdev, table->entries[i].v)))
2168 break;
2169
2170 kv_set_divider_value(rdev, i, table->entries[i].clk);
2171 vid_2bit = sumo_convert_vid7_to_vid2(rdev,
2172 &pi->sys_info.vid_mapping_table,
2173 table->entries[i].v);
2174 kv_set_vid(rdev, i, vid_2bit);
2175 kv_set_at(rdev, i, pi->at[i]);
2176 kv_dpm_power_level_enabled_for_throttle(rdev, i, true);
2177 pi->graphics_dpm_level_count++;
2178 }
2179 } else {
2180 struct sumo_sclk_voltage_mapping_table *table =
2181 &pi->sys_info.sclk_voltage_mapping_table;
2182
2183 pi->graphics_dpm_level_count = 0;
2184 for (i = 0; i < table->num_max_dpm_entries; i++) {
2185 if (pi->high_voltage_t &&
2186 pi->high_voltage_t <
2187 kv_convert_2bit_index_to_voltage(rdev, table->entries[i].vid_2bit))
2188 break;
2189
2190 kv_set_divider_value(rdev, i, table->entries[i].sclk_frequency);
2191 kv_set_vid(rdev, i, table->entries[i].vid_2bit);
2192 kv_set_at(rdev, i, pi->at[i]);
2193 kv_dpm_power_level_enabled_for_throttle(rdev, i, true);
2194 pi->graphics_dpm_level_count++;
2195 }
2196 }
2197
2198 for (i = 0; i < SMU7_MAX_LEVELS_GRAPHICS; i++)
2199 kv_dpm_power_level_enable(rdev, i, false);
2200}
2201
2202static void kv_enable_new_levels(struct radeon_device *rdev)
2203{
2204 struct kv_power_info *pi = kv_get_pi(rdev);
2205 u32 i;
2206
2207 for (i = 0; i < SMU7_MAX_LEVELS_GRAPHICS; i++) {
2208 if (i >= pi->lowest_valid && i <= pi->highest_valid)
2209 kv_dpm_power_level_enable(rdev, i, true);
2210 }
2211}
2212
2213static int kv_set_enabled_levels(struct radeon_device *rdev)
2214{
2215 struct kv_power_info *pi = kv_get_pi(rdev);
2216 u32 i, new_mask = 0;
2217
2218 for (i = pi->lowest_valid; i <= pi->highest_valid; i++)
2219 new_mask |= (1 << i);
2220
2221 return kv_send_msg_to_smc_with_parameter(rdev,
2222 PPSMC_MSG_SCLKDPM_SetEnabledMask,
2223 new_mask);
2224}
2225
2226static void kv_program_nbps_index_settings(struct radeon_device *rdev,
2227 struct radeon_ps *new_rps)
2228{
2229 struct kv_ps *new_ps = kv_get_ps(new_rps);
2230 struct kv_power_info *pi = kv_get_pi(rdev);
2231 u32 nbdpmconfig1;
2232
2233 if (rdev->family == CHIP_KABINI)
2234 return;
2235
2236 if (pi->sys_info.nb_dpm_enable) {
2237 nbdpmconfig1 = RREG32_SMC(NB_DPM_CONFIG_1);
2238 nbdpmconfig1 &= ~(Dpm0PgNbPsLo_MASK | Dpm0PgNbPsHi_MASK |
2239 DpmXNbPsLo_MASK | DpmXNbPsHi_MASK);
2240 nbdpmconfig1 |= (Dpm0PgNbPsLo(new_ps->dpm0_pg_nb_ps_lo) |
2241 Dpm0PgNbPsHi(new_ps->dpm0_pg_nb_ps_hi) |
2242 DpmXNbPsLo(new_ps->dpmx_nb_ps_lo) |
2243 DpmXNbPsHi(new_ps->dpmx_nb_ps_hi));
2244 WREG32_SMC(NB_DPM_CONFIG_1, nbdpmconfig1);
2245 }
2246}
2247
2248static int kv_set_thermal_temperature_range(struct radeon_device *rdev,
2249 int min_temp, int max_temp)
2250{
2251 int low_temp = 0 * 1000;
2252 int high_temp = 255 * 1000;
2253 u32 tmp;
2254
2255 if (low_temp < min_temp)
2256 low_temp = min_temp;
2257 if (high_temp > max_temp)
2258 high_temp = max_temp;
2259 if (high_temp < low_temp) {
2260 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
2261 return -EINVAL;
2262 }
2263
2264 tmp = RREG32_SMC(CG_THERMAL_INT_CTRL);
2265 tmp &= ~(DIG_THERM_INTH_MASK | DIG_THERM_INTL_MASK);
2266 tmp |= (DIG_THERM_INTH(49 + (high_temp / 1000)) |
2267 DIG_THERM_INTL(49 + (low_temp / 1000)));
2268 WREG32_SMC(CG_THERMAL_INT_CTRL, tmp);
2269
2270 rdev->pm.dpm.thermal.min_temp = low_temp;
2271 rdev->pm.dpm.thermal.max_temp = high_temp;
2272
2273 return 0;
2274}
2275
2276union igp_info {
2277 struct _ATOM_INTEGRATED_SYSTEM_INFO info;
2278 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
2279 struct _ATOM_INTEGRATED_SYSTEM_INFO_V5 info_5;
2280 struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6;
2281 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7;
2282 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 info_8;
2283};
2284
2285static int kv_parse_sys_info_table(struct radeon_device *rdev)
2286{
2287 struct kv_power_info *pi = kv_get_pi(rdev);
2288 struct radeon_mode_info *mode_info = &rdev->mode_info;
2289 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
2290 union igp_info *igp_info;
2291 u8 frev, crev;
2292 u16 data_offset;
2293 int i;
2294
2295 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2296 &frev, &crev, &data_offset)) {
2297 igp_info = (union igp_info *)(mode_info->atom_context->bios +
2298 data_offset);
2299
2300 if (crev != 8) {
2301 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
2302 return -EINVAL;
2303 }
2304 pi->sys_info.bootup_sclk = le32_to_cpu(igp_info->info_8.ulBootUpEngineClock);
2305 pi->sys_info.bootup_uma_clk = le32_to_cpu(igp_info->info_8.ulBootUpUMAClock);
2306 pi->sys_info.bootup_nb_voltage_index =
2307 le16_to_cpu(igp_info->info_8.usBootUpNBVoltage);
2308 if (igp_info->info_8.ucHtcTmpLmt == 0)
2309 pi->sys_info.htc_tmp_lmt = 203;
2310 else
2311 pi->sys_info.htc_tmp_lmt = igp_info->info_8.ucHtcTmpLmt;
2312 if (igp_info->info_8.ucHtcHystLmt == 0)
2313 pi->sys_info.htc_hyst_lmt = 5;
2314 else
2315 pi->sys_info.htc_hyst_lmt = igp_info->info_8.ucHtcHystLmt;
2316 if (pi->sys_info.htc_tmp_lmt <= pi->sys_info.htc_hyst_lmt) {
2317 DRM_ERROR("The htcTmpLmt should be larger than htcHystLmt.\n");
2318 }
2319
2320 if (le32_to_cpu(igp_info->info_8.ulSystemConfig) & (1 << 3))
2321 pi->sys_info.nb_dpm_enable = true;
2322 else
2323 pi->sys_info.nb_dpm_enable = false;
2324
2325 for (i = 0; i < KV_NUM_NBPSTATES; i++) {
2326 pi->sys_info.nbp_memory_clock[i] =
2327 le32_to_cpu(igp_info->info_8.ulNbpStateMemclkFreq[i]);
2328 pi->sys_info.nbp_n_clock[i] =
2329 le32_to_cpu(igp_info->info_8.ulNbpStateNClkFreq[i]);
2330 }
2331 if (le32_to_cpu(igp_info->info_8.ulGPUCapInfo) &
2332 SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS)
2333 pi->caps_enable_dfs_bypass = true;
2334
2335 sumo_construct_sclk_voltage_mapping_table(rdev,
2336 &pi->sys_info.sclk_voltage_mapping_table,
2337 igp_info->info_8.sAvail_SCLK);
2338
2339 sumo_construct_vid_mapping_table(rdev,
2340 &pi->sys_info.vid_mapping_table,
2341 igp_info->info_8.sAvail_SCLK);
2342
2343 kv_construct_max_power_limits_table(rdev,
2344 &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac);
2345 }
2346 return 0;
2347}
2348
2349union power_info {
2350 struct _ATOM_POWERPLAY_INFO info;
2351 struct _ATOM_POWERPLAY_INFO_V2 info_2;
2352 struct _ATOM_POWERPLAY_INFO_V3 info_3;
2353 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
2354 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
2355 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
2356};
2357
2358union pplib_clock_info {
2359 struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
2360 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
2361 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
2362 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
2363};
2364
2365union pplib_power_state {
2366 struct _ATOM_PPLIB_STATE v1;
2367 struct _ATOM_PPLIB_STATE_V2 v2;
2368};
2369
2370static void kv_patch_boot_state(struct radeon_device *rdev,
2371 struct kv_ps *ps)
2372{
2373 struct kv_power_info *pi = kv_get_pi(rdev);
2374
2375 ps->num_levels = 1;
2376 ps->levels[0] = pi->boot_pl;
2377}
2378
2379static void kv_parse_pplib_non_clock_info(struct radeon_device *rdev,
2380 struct radeon_ps *rps,
2381 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
2382 u8 table_rev)
2383{
2384 struct kv_ps *ps = kv_get_ps(rps);
2385
2386 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
2387 rps->class = le16_to_cpu(non_clock_info->usClassification);
2388 rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
2389
2390 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
2391 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
2392 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
2393 } else {
2394 rps->vclk = 0;
2395 rps->dclk = 0;
2396 }
2397
2398 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
2399 rdev->pm.dpm.boot_ps = rps;
2400 kv_patch_boot_state(rdev, ps);
2401 }
2402 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
2403 rdev->pm.dpm.uvd_ps = rps;
2404}
2405
2406static void kv_parse_pplib_clock_info(struct radeon_device *rdev,
2407 struct radeon_ps *rps, int index,
2408 union pplib_clock_info *clock_info)
2409{
2410 struct kv_power_info *pi = kv_get_pi(rdev);
2411 struct kv_ps *ps = kv_get_ps(rps);
2412 struct kv_pl *pl = &ps->levels[index];
2413 u32 sclk;
2414
2415 sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow);
2416 sclk |= clock_info->sumo.ucEngineClockHigh << 16;
2417 pl->sclk = sclk;
2418 pl->vddc_index = clock_info->sumo.vddcIndex;
2419
2420 ps->num_levels = index + 1;
2421
2422 if (pi->caps_sclk_ds) {
2423 pl->ds_divider_index = 5;
2424 pl->ss_divider_index = 5;
2425 }
2426}
2427
2428static int kv_parse_power_table(struct radeon_device *rdev)
2429{
2430 struct radeon_mode_info *mode_info = &rdev->mode_info;
2431 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2432 union pplib_power_state *power_state;
2433 int i, j, k, non_clock_array_index, clock_array_index;
2434 union pplib_clock_info *clock_info;
2435 struct _StateArray *state_array;
2436 struct _ClockInfoArray *clock_info_array;
2437 struct _NonClockInfoArray *non_clock_info_array;
2438 union power_info *power_info;
2439 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2440 u16 data_offset;
2441 u8 frev, crev;
2442 u8 *power_state_offset;
2443 struct kv_ps *ps;
2444
2445 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2446 &frev, &crev, &data_offset))
2447 return -EINVAL;
2448 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2449
2450 state_array = (struct _StateArray *)
2451 (mode_info->atom_context->bios + data_offset +
2452 le16_to_cpu(power_info->pplib.usStateArrayOffset));
2453 clock_info_array = (struct _ClockInfoArray *)
2454 (mode_info->atom_context->bios + data_offset +
2455 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
2456 non_clock_info_array = (struct _NonClockInfoArray *)
2457 (mode_info->atom_context->bios + data_offset +
2458 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
2459
2460 rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) *
2461 state_array->ucNumEntries, GFP_KERNEL);
2462 if (!rdev->pm.dpm.ps)
2463 return -ENOMEM;
2464 power_state_offset = (u8 *)state_array->states;
2465 rdev->pm.dpm.platform_caps = le32_to_cpu(power_info->pplib.ulPlatformCaps);
2466 rdev->pm.dpm.backbias_response_time = le16_to_cpu(power_info->pplib.usBackbiasTime);
2467 rdev->pm.dpm.voltage_response_time = le16_to_cpu(power_info->pplib.usVoltageTime);
2468 for (i = 0; i < state_array->ucNumEntries; i++) {
9af37a7d 2469 u8 *idx;
41a524ab
AD		 2470 power_state = (union pplib_power_state *)power_state_offset;
2471 non_clock_array_index = power_state->v2.nonClockInfoIndex;
2472 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2473 &non_clock_info_array->nonClockInfo[non_clock_array_index];
2474 if (!rdev->pm.power_state[i].clock_info)
2475 return -EINVAL;
2476 ps = kzalloc(sizeof(struct kv_ps), GFP_KERNEL);
2477 if (ps == NULL) {
2478 kfree(rdev->pm.dpm.ps);
2479 return -ENOMEM;
2480 }
2481 rdev->pm.dpm.ps[i].ps_priv = ps;
2482 k = 0;
9af37a7d 2483 idx = (u8 *)&power_state->v2.clockInfoIndex[0];
41a524ab 2484 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
9af37a7d 2485 clock_array_index = idx[j];
41a524ab
AD		 2486 if (clock_array_index >= clock_info_array->ucNumEntries)
2487 continue;
2488 if (k >= SUMO_MAX_HARDWARE_POWERLEVELS)
2489 break;
2490 clock_info = (union pplib_clock_info *)
9af37a7d
AD		 2491 ((u8 *)&clock_info_array->clockInfo[0] +
2492 (clock_array_index * clock_info_array->ucEntrySize));
41a524ab
AD		 2493 kv_parse_pplib_clock_info(rdev,
2494 &rdev->pm.dpm.ps[i], k,
2495 clock_info);
2496 k++;
2497 }
2498 kv_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],
2499 non_clock_info,
2500 non_clock_info_array->ucEntrySize);
2501 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
2502 }
2503 rdev->pm.dpm.num_ps = state_array->ucNumEntries;
2504 return 0;
2505}
2506
2507int kv_dpm_init(struct radeon_device *rdev)
2508{
2509 struct kv_power_info *pi;
2510 int ret, i;
2511
2512 pi = kzalloc(sizeof(struct kv_power_info), GFP_KERNEL);
2513 if (pi == NULL)
2514 return -ENOMEM;
2515 rdev->pm.dpm.priv = pi;
2516
2517 ret = r600_parse_extended_power_table(rdev);
2518 if (ret)
2519 return ret;
2520
2521 for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++)
2522 pi->at[i] = TRINITY_AT_DFLT;
2523
2524 pi->sram_end = SMC_RAM_END;
2525
2526 if (rdev->family == CHIP_KABINI)
2527 pi->high_voltage_t = 4001;
2528
2529 pi->enable_nb_dpm = true;
2530
2531 pi->caps_power_containment = true;
2532 pi->caps_cac = true;
2533 pi->enable_didt = false;
2534 if (pi->enable_didt) {
2535 pi->caps_sq_ramping = true;
2536 pi->caps_db_ramping = true;
2537 pi->caps_td_ramping = true;
2538 pi->caps_tcp_ramping = true;
2539 }
2540
2541 pi->caps_sclk_ds = true;
2542 pi->enable_auto_thermal_throttling = true;
2543 pi->disable_nb_ps3_in_battery = false;
2544 pi->bapm_enable = true;
2545 pi->voltage_drop_t = 0;
2546 pi->caps_sclk_throttle_low_notification = false;
2547 pi->caps_fps = false; /* true? */
77df508a 2548 pi->caps_uvd_pg = true;
41a524ab
AD		 2549 pi->caps_uvd_dpm = true;
2550 pi->caps_vce_pg = false;
2551 pi->caps_samu_pg = false;
2552 pi->caps_acp_pg = false;
2553 pi->caps_stable_p_state = false;
2554
2555 ret = kv_parse_sys_info_table(rdev);
2556 if (ret)
2557 return ret;
2558
2559 kv_patch_voltage_values(rdev);
2560 kv_construct_boot_state(rdev);
2561
2562 ret = kv_parse_power_table(rdev);
2563 if (ret)
2564 return ret;
2565
2566 pi->enable_dpm = true;
2567
2568 return 0;
2569}
2570
ae3e40e8
AD		 2571void kv_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
2572 struct seq_file *m)
2573{
2574 struct kv_power_info *pi = kv_get_pi(rdev);
2575 u32 current_index =
2576 (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) & CURR_SCLK_INDEX_MASK) >>
2577 CURR_SCLK_INDEX_SHIFT;
2578 u32 sclk, tmp;
2579 u16 vddc;
2580
2581 if (current_index >= SMU__NUM_SCLK_DPM_STATE) {
2582 seq_printf(m, "invalid dpm profile %d\n", current_index);
2583 } else {
2584 sclk = be32_to_cpu(pi->graphics_level[current_index].SclkFrequency);
2585 tmp = (RREG32_SMC(SMU_VOLTAGE_STATUS) & SMU_VOLTAGE_CURRENT_LEVEL_MASK) >>
2586 SMU_VOLTAGE_CURRENT_LEVEL_SHIFT;
2587 vddc = kv_convert_8bit_index_to_voltage(rdev, (u16)tmp);
2588 seq_printf(m, "power level %d sclk: %u vddc: %u\n",
2589 current_index, sclk, vddc);
2590 }
2591}
2592
41a524ab
AD		 2593void kv_dpm_print_power_state(struct radeon_device *rdev,
2594 struct radeon_ps *rps)
2595{
2596 int i;
2597 struct kv_ps *ps = kv_get_ps(rps);
2598
2599 r600_dpm_print_class_info(rps->class, rps->class2);
2600 r600_dpm_print_cap_info(rps->caps);
2601 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
2602 for (i = 0; i < ps->num_levels; i++) {
2603 struct kv_pl *pl = &ps->levels[i];
2604 printk("\t\tpower level %d sclk: %u vddc: %u\n",
2605 i, pl->sclk,
2606 kv_convert_8bit_index_to_voltage(rdev, pl->vddc_index));
2607 }
2608 r600_dpm_print_ps_status(rdev, rps);
2609}
2610
2611void kv_dpm_fini(struct radeon_device *rdev)
2612{
2613 int i;
2614
2615 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
2616 kfree(rdev->pm.dpm.ps[i].ps_priv);
2617 }
2618 kfree(rdev->pm.dpm.ps);
2619 kfree(rdev->pm.dpm.priv);
2620 r600_free_extended_power_table(rdev);
2621}
2622
2623void kv_dpm_display_configuration_changed(struct radeon_device *rdev)
2624{
2625
2626}
2627
2628u32 kv_dpm_get_sclk(struct radeon_device *rdev, bool low)
2629{
2630 struct kv_power_info *pi = kv_get_pi(rdev);
2631 struct kv_ps *requested_state = kv_get_ps(&pi->requested_rps);
2632
2633 if (low)
2634 return requested_state->levels[0].sclk;
2635 else
2636 return requested_state->levels[requested_state->num_levels - 1].sclk;
2637}
2638
2639u32 kv_dpm_get_mclk(struct radeon_device *rdev, bool low)
2640{
2641 struct kv_power_info *pi = kv_get_pi(rdev);
2642
2643 return pi->sys_info.bootup_uma_clk;
2644}
2645
Linux kernel - Deliverables
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