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drm/radeon: cleanup properly if mmio mapping fails
[deliverable/linux.git] / drivers / gpu / drm / radeon / ni.c
CommitLineData
0af62b01
AD		 1/*
2 * Copyright 2010 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24#include <linux/firmware.h>
25#include <linux/platform_device.h>
26#include <linux/slab.h>
e0cd3608 27#include <linux/module.h>
760285e7 28#include <drm/drmP.h>
0af62b01
AD		 29#include "radeon.h"
30#include "radeon_asic.h"
760285e7 31#include <drm/radeon_drm.h>
0af62b01
AD		 32#include "nid.h"
33#include "atom.h"
34#include "ni_reg.h"
0c88a02e 35#include "cayman_blit_shaders.h"
0af62b01 36
168757ea 37extern bool evergreen_is_display_hung(struct radeon_device *rdev);
187e3593 38extern void evergreen_print_gpu_status_regs(struct radeon_device *rdev);
b9952a8a
AD		 39extern void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save);
40extern void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save);
41extern int evergreen_mc_wait_for_idle(struct radeon_device *rdev);
755d819e
AD		 42extern void evergreen_mc_program(struct radeon_device *rdev);
43extern void evergreen_irq_suspend(struct radeon_device *rdev);
44extern int evergreen_mc_init(struct radeon_device *rdev);
d054ac16 45extern void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev);
b07759bf 46extern void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
c420c745
AD		 47extern void si_rlc_fini(struct radeon_device *rdev);
48extern int si_rlc_init(struct radeon_device *rdev);
b9952a8a 49
0af62b01
AD		 50#define EVERGREEN_PFP_UCODE_SIZE 1120
51#define EVERGREEN_PM4_UCODE_SIZE 1376
52#define EVERGREEN_RLC_UCODE_SIZE 768
53#define BTC_MC_UCODE_SIZE 6024
54
9b8253ce
AD		 55#define CAYMAN_PFP_UCODE_SIZE 2176
56#define CAYMAN_PM4_UCODE_SIZE 2176
57#define CAYMAN_RLC_UCODE_SIZE 1024
58#define CAYMAN_MC_UCODE_SIZE 6037
59
c420c745
AD		 60#define ARUBA_RLC_UCODE_SIZE 1536
61
0af62b01
AD		 62/* Firmware Names */
63MODULE_FIRMWARE("radeon/BARTS_pfp.bin");
64MODULE_FIRMWARE("radeon/BARTS_me.bin");
65MODULE_FIRMWARE("radeon/BARTS_mc.bin");
66MODULE_FIRMWARE("radeon/BTC_rlc.bin");
67MODULE_FIRMWARE("radeon/TURKS_pfp.bin");
68MODULE_FIRMWARE("radeon/TURKS_me.bin");
69MODULE_FIRMWARE("radeon/TURKS_mc.bin");
70MODULE_FIRMWARE("radeon/CAICOS_pfp.bin");
71MODULE_FIRMWARE("radeon/CAICOS_me.bin");
72MODULE_FIRMWARE("radeon/CAICOS_mc.bin");
9b8253ce
AD		 73MODULE_FIRMWARE("radeon/CAYMAN_pfp.bin");
74MODULE_FIRMWARE("radeon/CAYMAN_me.bin");
75MODULE_FIRMWARE("radeon/CAYMAN_mc.bin");
76MODULE_FIRMWARE("radeon/CAYMAN_rlc.bin");
c420c745
AD		 77MODULE_FIRMWARE("radeon/ARUBA_pfp.bin");
78MODULE_FIRMWARE("radeon/ARUBA_me.bin");
79MODULE_FIRMWARE("radeon/ARUBA_rlc.bin");
0af62b01
AD		 80
81#define BTC_IO_MC_REGS_SIZE 29
82
83static const u32 barts_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
84 {0x00000077, 0xff010100},
85 {0x00000078, 0x00000000},
86 {0x00000079, 0x00001434},
87 {0x0000007a, 0xcc08ec08},
88 {0x0000007b, 0x00040000},
89 {0x0000007c, 0x000080c0},
90 {0x0000007d, 0x09000000},
91 {0x0000007e, 0x00210404},
92 {0x00000081, 0x08a8e800},
93 {0x00000082, 0x00030444},
94 {0x00000083, 0x00000000},
95 {0x00000085, 0x00000001},
96 {0x00000086, 0x00000002},
97 {0x00000087, 0x48490000},
98 {0x00000088, 0x20244647},
99 {0x00000089, 0x00000005},
100 {0x0000008b, 0x66030000},
101 {0x0000008c, 0x00006603},
102 {0x0000008d, 0x00000100},
103 {0x0000008f, 0x00001c0a},
104 {0x00000090, 0xff000001},
105 {0x00000094, 0x00101101},
106 {0x00000095, 0x00000fff},
107 {0x00000096, 0x00116fff},
108 {0x00000097, 0x60010000},
109 {0x00000098, 0x10010000},
110 {0x00000099, 0x00006000},
111 {0x0000009a, 0x00001000},
112 {0x0000009f, 0x00946a00}
113};
114
115static const u32 turks_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
116 {0x00000077, 0xff010100},
117 {0x00000078, 0x00000000},
118 {0x00000079, 0x00001434},
119 {0x0000007a, 0xcc08ec08},
120 {0x0000007b, 0x00040000},
121 {0x0000007c, 0x000080c0},
122 {0x0000007d, 0x09000000},
123 {0x0000007e, 0x00210404},
124 {0x00000081, 0x08a8e800},
125 {0x00000082, 0x00030444},
126 {0x00000083, 0x00000000},
127 {0x00000085, 0x00000001},
128 {0x00000086, 0x00000002},
129 {0x00000087, 0x48490000},
130 {0x00000088, 0x20244647},
131 {0x00000089, 0x00000005},
132 {0x0000008b, 0x66030000},
133 {0x0000008c, 0x00006603},
134 {0x0000008d, 0x00000100},
135 {0x0000008f, 0x00001c0a},
136 {0x00000090, 0xff000001},
137 {0x00000094, 0x00101101},
138 {0x00000095, 0x00000fff},
139 {0x00000096, 0x00116fff},
140 {0x00000097, 0x60010000},
141 {0x00000098, 0x10010000},
142 {0x00000099, 0x00006000},
143 {0x0000009a, 0x00001000},
144 {0x0000009f, 0x00936a00}
145};
146
147static const u32 caicos_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
148 {0x00000077, 0xff010100},
149 {0x00000078, 0x00000000},
150 {0x00000079, 0x00001434},
151 {0x0000007a, 0xcc08ec08},
152 {0x0000007b, 0x00040000},
153 {0x0000007c, 0x000080c0},
154 {0x0000007d, 0x09000000},
155 {0x0000007e, 0x00210404},
156 {0x00000081, 0x08a8e800},
157 {0x00000082, 0x00030444},
158 {0x00000083, 0x00000000},
159 {0x00000085, 0x00000001},
160 {0x00000086, 0x00000002},
161 {0x00000087, 0x48490000},
162 {0x00000088, 0x20244647},
163 {0x00000089, 0x00000005},
164 {0x0000008b, 0x66030000},
165 {0x0000008c, 0x00006603},
166 {0x0000008d, 0x00000100},
167 {0x0000008f, 0x00001c0a},
168 {0x00000090, 0xff000001},
169 {0x00000094, 0x00101101},
170 {0x00000095, 0x00000fff},
171 {0x00000096, 0x00116fff},
172 {0x00000097, 0x60010000},
173 {0x00000098, 0x10010000},
174 {0x00000099, 0x00006000},
175 {0x0000009a, 0x00001000},
176 {0x0000009f, 0x00916a00}
177};
178
9b8253ce
AD		 179static const u32 cayman_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
180 {0x00000077, 0xff010100},
181 {0x00000078, 0x00000000},
182 {0x00000079, 0x00001434},
183 {0x0000007a, 0xcc08ec08},
184 {0x0000007b, 0x00040000},
185 {0x0000007c, 0x000080c0},
186 {0x0000007d, 0x09000000},
187 {0x0000007e, 0x00210404},
188 {0x00000081, 0x08a8e800},
189 {0x00000082, 0x00030444},
190 {0x00000083, 0x00000000},
191 {0x00000085, 0x00000001},
192 {0x00000086, 0x00000002},
193 {0x00000087, 0x48490000},
194 {0x00000088, 0x20244647},
195 {0x00000089, 0x00000005},
196 {0x0000008b, 0x66030000},
197 {0x0000008c, 0x00006603},
198 {0x0000008d, 0x00000100},
199 {0x0000008f, 0x00001c0a},
200 {0x00000090, 0xff000001},
201 {0x00000094, 0x00101101},
202 {0x00000095, 0x00000fff},
203 {0x00000096, 0x00116fff},
204 {0x00000097, 0x60010000},
205 {0x00000098, 0x10010000},
206 {0x00000099, 0x00006000},
207 {0x0000009a, 0x00001000},
208 {0x0000009f, 0x00976b00}
209};
210
755d819e 211int ni_mc_load_microcode(struct radeon_device *rdev)
0af62b01
AD		 212{
213 const __be32 *fw_data;
214 u32 mem_type, running, blackout = 0;
215 u32 *io_mc_regs;
9b8253ce 216 int i, ucode_size, regs_size;
0af62b01
AD		 217
218 if (!rdev->mc_fw)
219 return -EINVAL;
220
221 switch (rdev->family) {
222 case CHIP_BARTS:
223 io_mc_regs = (u32 *)&barts_io_mc_regs;
9b8253ce
AD		 224 ucode_size = BTC_MC_UCODE_SIZE;
225 regs_size = BTC_IO_MC_REGS_SIZE;
0af62b01
AD		 226 break;
227 case CHIP_TURKS:
228 io_mc_regs = (u32 *)&turks_io_mc_regs;
9b8253ce
AD		 229 ucode_size = BTC_MC_UCODE_SIZE;
230 regs_size = BTC_IO_MC_REGS_SIZE;
0af62b01
AD		 231 break;
232 case CHIP_CAICOS:
233 default:
234 io_mc_regs = (u32 *)&caicos_io_mc_regs;
9b8253ce
AD		 235 ucode_size = BTC_MC_UCODE_SIZE;
236 regs_size = BTC_IO_MC_REGS_SIZE;
237 break;
238 case CHIP_CAYMAN:
239 io_mc_regs = (u32 *)&cayman_io_mc_regs;
240 ucode_size = CAYMAN_MC_UCODE_SIZE;
241 regs_size = BTC_IO_MC_REGS_SIZE;
0af62b01
AD		 242 break;
243 }
244
245 mem_type = (RREG32(MC_SEQ_MISC0) & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT;
246 running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK;
247
248 if ((mem_type == MC_SEQ_MISC0_GDDR5_VALUE) && (running == 0)) {
249 if (running) {
250 blackout = RREG32(MC_SHARED_BLACKOUT_CNTL);
251 WREG32(MC_SHARED_BLACKOUT_CNTL, 1);
252 }
253
254 /* reset the engine and set to writable */
255 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
256 WREG32(MC_SEQ_SUP_CNTL, 0x00000010);
257
258 /* load mc io regs */
9b8253ce 259 for (i = 0; i < regs_size; i++) {
0af62b01
AD		 260 WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]);
261 WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]);
262 }
263 /* load the MC ucode */
264 fw_data = (const __be32 *)rdev->mc_fw->data;
9b8253ce 265 for (i = 0; i < ucode_size; i++)
0af62b01
AD		 266 WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++));
267
268 /* put the engine back into the active state */
269 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
270 WREG32(MC_SEQ_SUP_CNTL, 0x00000004);
271 WREG32(MC_SEQ_SUP_CNTL, 0x00000001);
272
273 /* wait for training to complete */
0e2c978e
AD		 274 for (i = 0; i < rdev->usec_timeout; i++) {
275 if (RREG32(MC_IO_PAD_CNTL_D0) & MEM_FALL_OUT_CMD)
276 break;
277 udelay(1);
278 }
0af62b01
AD		 279
280 if (running)
281 WREG32(MC_SHARED_BLACKOUT_CNTL, blackout);
282 }
283
284 return 0;
285}
286
287int ni_init_microcode(struct radeon_device *rdev)
288{
289 struct platform_device *pdev;
290 const char *chip_name;
291 const char *rlc_chip_name;
292 size_t pfp_req_size, me_req_size, rlc_req_size, mc_req_size;
293 char fw_name[30];
294 int err;
295
296 DRM_DEBUG("\n");
297
298 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
299 err = IS_ERR(pdev);
300 if (err) {
301 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
302 return -EINVAL;
303 }
304
305 switch (rdev->family) {
306 case CHIP_BARTS:
307 chip_name = "BARTS";
308 rlc_chip_name = "BTC";
9b8253ce
AD		 309 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
310 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
311 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
312 mc_req_size = BTC_MC_UCODE_SIZE * 4;
0af62b01
AD		 313 break;
314 case CHIP_TURKS:
315 chip_name = "TURKS";
316 rlc_chip_name = "BTC";
9b8253ce
AD		 317 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
318 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
319 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
320 mc_req_size = BTC_MC_UCODE_SIZE * 4;
0af62b01
AD		 321 break;
322 case CHIP_CAICOS:
323 chip_name = "CAICOS";
324 rlc_chip_name = "BTC";
9b8253ce
AD		 325 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
326 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
327 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
328 mc_req_size = BTC_MC_UCODE_SIZE * 4;
329 break;
330 case CHIP_CAYMAN:
331 chip_name = "CAYMAN";
332 rlc_chip_name = "CAYMAN";
333 pfp_req_size = CAYMAN_PFP_UCODE_SIZE * 4;
334 me_req_size = CAYMAN_PM4_UCODE_SIZE * 4;
335 rlc_req_size = CAYMAN_RLC_UCODE_SIZE * 4;
336 mc_req_size = CAYMAN_MC_UCODE_SIZE * 4;
0af62b01 337 break;
c420c745
AD		 338 case CHIP_ARUBA:
339 chip_name = "ARUBA";
340 rlc_chip_name = "ARUBA";
341 /* pfp/me same size as CAYMAN */
342 pfp_req_size = CAYMAN_PFP_UCODE_SIZE * 4;
343 me_req_size = CAYMAN_PM4_UCODE_SIZE * 4;
344 rlc_req_size = ARUBA_RLC_UCODE_SIZE * 4;
345 mc_req_size = 0;
346 break;
0af62b01
AD		 347 default: BUG();
348 }
349
0af62b01
AD		 350 DRM_INFO("Loading %s Microcode\n", chip_name);
351
352 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
353 err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
354 if (err)
355 goto out;
356 if (rdev->pfp_fw->size != pfp_req_size) {
357 printk(KERN_ERR
358 "ni_cp: Bogus length %zu in firmware \"%s\"\n",
359 rdev->pfp_fw->size, fw_name);
360 err = -EINVAL;
361 goto out;
362 }
363
364 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
365 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
366 if (err)
367 goto out;
368 if (rdev->me_fw->size != me_req_size) {
369 printk(KERN_ERR
370 "ni_cp: Bogus length %zu in firmware \"%s\"\n",
371 rdev->me_fw->size, fw_name);
372 err = -EINVAL;
373 }
374
375 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
376 err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev);
377 if (err)
378 goto out;
379 if (rdev->rlc_fw->size != rlc_req_size) {
380 printk(KERN_ERR
381 "ni_rlc: Bogus length %zu in firmware \"%s\"\n",
382 rdev->rlc_fw->size, fw_name);
383 err = -EINVAL;
384 }
385
c420c745
AD		 386 /* no MC ucode on TN */
387 if (!(rdev->flags & RADEON_IS_IGP)) {
388 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
389 err = request_firmware(&rdev->mc_fw, fw_name, &pdev->dev);
390 if (err)
391 goto out;
392 if (rdev->mc_fw->size != mc_req_size) {
393 printk(KERN_ERR
394 "ni_mc: Bogus length %zu in firmware \"%s\"\n",
395 rdev->mc_fw->size, fw_name);
396 err = -EINVAL;
397 }
0af62b01
AD		 398 }
399out:
400 platform_device_unregister(pdev);
401
402 if (err) {
403 if (err != -EINVAL)
404 printk(KERN_ERR
405 "ni_cp: Failed to load firmware \"%s\"\n",
406 fw_name);
407 release_firmware(rdev->pfp_fw);
408 rdev->pfp_fw = NULL;
409 release_firmware(rdev->me_fw);
410 rdev->me_fw = NULL;
411 release_firmware(rdev->rlc_fw);
412 rdev->rlc_fw = NULL;
413 release_firmware(rdev->mc_fw);
414 rdev->mc_fw = NULL;
415 }
416 return err;
417}
418
fecf1d07
AD		 419/*
420 * Core functions
421 */
fecf1d07
AD		 422static void cayman_gpu_init(struct radeon_device *rdev)
423{
fecf1d07
AD		 424 u32 gb_addr_config = 0;
425 u32 mc_shared_chmap, mc_arb_ramcfg;
fecf1d07
AD		 426 u32 cgts_tcc_disable;
427 u32 sx_debug_1;
428 u32 smx_dc_ctl0;
fecf1d07
AD		 429 u32 cgts_sm_ctrl_reg;
430 u32 hdp_host_path_cntl;
431 u32 tmp;
416a2bd2 432 u32 disabled_rb_mask;
fecf1d07
AD		 433 int i, j;
434
435 switch (rdev->family) {
436 case CHIP_CAYMAN:
fecf1d07
AD		 437 rdev->config.cayman.max_shader_engines = 2;
438 rdev->config.cayman.max_pipes_per_simd = 4;
439 rdev->config.cayman.max_tile_pipes = 8;
440 rdev->config.cayman.max_simds_per_se = 12;
441 rdev->config.cayman.max_backends_per_se = 4;
442 rdev->config.cayman.max_texture_channel_caches = 8;
443 rdev->config.cayman.max_gprs = 256;
444 rdev->config.cayman.max_threads = 256;
445 rdev->config.cayman.max_gs_threads = 32;
446 rdev->config.cayman.max_stack_entries = 512;
447 rdev->config.cayman.sx_num_of_sets = 8;
448 rdev->config.cayman.sx_max_export_size = 256;
449 rdev->config.cayman.sx_max_export_pos_size = 64;
450 rdev->config.cayman.sx_max_export_smx_size = 192;
451 rdev->config.cayman.max_hw_contexts = 8;
452 rdev->config.cayman.sq_num_cf_insts = 2;
453
454 rdev->config.cayman.sc_prim_fifo_size = 0x100;
455 rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30;
456 rdev->config.cayman.sc_earlyz_tile_fifo_size = 0x130;
416a2bd2 457 gb_addr_config = CAYMAN_GB_ADDR_CONFIG_GOLDEN;
fecf1d07 458 break;
7b76e479
AD		 459 case CHIP_ARUBA:
460 default:
461 rdev->config.cayman.max_shader_engines = 1;
462 rdev->config.cayman.max_pipes_per_simd = 4;
463 rdev->config.cayman.max_tile_pipes = 2;
464 if ((rdev->pdev->device == 0x9900) ||
d430f7db
AD		 465 (rdev->pdev->device == 0x9901) ||
466 (rdev->pdev->device == 0x9905) ||
467 (rdev->pdev->device == 0x9906) ||
468 (rdev->pdev->device == 0x9907) ||
469 (rdev->pdev->device == 0x9908) ||
470 (rdev->pdev->device == 0x9909) ||
e4d17063
AD		 471 (rdev->pdev->device == 0x990B) ||
472 (rdev->pdev->device == 0x990C) ||
473 (rdev->pdev->device == 0x990F) ||
d430f7db 474 (rdev->pdev->device == 0x9910) ||
e4d17063
AD		 475 (rdev->pdev->device == 0x9917) ||
476 (rdev->pdev->device == 0x9999)) {
7b76e479
AD		 477 rdev->config.cayman.max_simds_per_se = 6;
478 rdev->config.cayman.max_backends_per_se = 2;
479 } else if ((rdev->pdev->device == 0x9903) ||
d430f7db
AD		 480 (rdev->pdev->device == 0x9904) ||
481 (rdev->pdev->device == 0x990A) ||
e4d17063
AD		 482 (rdev->pdev->device == 0x990D) ||
483 (rdev->pdev->device == 0x990E) ||
d430f7db
AD		 484 (rdev->pdev->device == 0x9913) ||
485 (rdev->pdev->device == 0x9918)) {
7b76e479
AD		 486 rdev->config.cayman.max_simds_per_se = 4;
487 rdev->config.cayman.max_backends_per_se = 2;
d430f7db
AD		 488 } else if ((rdev->pdev->device == 0x9919) ||
489 (rdev->pdev->device == 0x9990) ||
490 (rdev->pdev->device == 0x9991) ||
491 (rdev->pdev->device == 0x9994) ||
e4d17063
AD		 492 (rdev->pdev->device == 0x9995) ||
493 (rdev->pdev->device == 0x9996) ||
494 (rdev->pdev->device == 0x999A) ||
d430f7db 495 (rdev->pdev->device == 0x99A0)) {
7b76e479
AD		 496 rdev->config.cayman.max_simds_per_se = 3;
497 rdev->config.cayman.max_backends_per_se = 1;
498 } else {
499 rdev->config.cayman.max_simds_per_se = 2;
500 rdev->config.cayman.max_backends_per_se = 1;
501 }
502 rdev->config.cayman.max_texture_channel_caches = 2;
503 rdev->config.cayman.max_gprs = 256;
504 rdev->config.cayman.max_threads = 256;
505 rdev->config.cayman.max_gs_threads = 32;
506 rdev->config.cayman.max_stack_entries = 512;
507 rdev->config.cayman.sx_num_of_sets = 8;
508 rdev->config.cayman.sx_max_export_size = 256;
509 rdev->config.cayman.sx_max_export_pos_size = 64;
510 rdev->config.cayman.sx_max_export_smx_size = 192;
511 rdev->config.cayman.max_hw_contexts = 8;
512 rdev->config.cayman.sq_num_cf_insts = 2;
513
514 rdev->config.cayman.sc_prim_fifo_size = 0x40;
515 rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30;
516 rdev->config.cayman.sc_earlyz_tile_fifo_size = 0x130;
416a2bd2 517 gb_addr_config = ARUBA_GB_ADDR_CONFIG_GOLDEN;
7b76e479 518 break;
fecf1d07
AD		 519 }
520
521 /* Initialize HDP */
522 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
523 WREG32((0x2c14 + j), 0x00000000);
524 WREG32((0x2c18 + j), 0x00000000);
525 WREG32((0x2c1c + j), 0x00000000);
526 WREG32((0x2c20 + j), 0x00000000);
527 WREG32((0x2c24 + j), 0x00000000);
528 }
529
530 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
531
d054ac16
AD		 532 evergreen_fix_pci_max_read_req_size(rdev);
533
fecf1d07
AD		 534 mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
535 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
536
fecf1d07
AD		 537 tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT;
538 rdev->config.cayman.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
539 if (rdev->config.cayman.mem_row_size_in_kb > 4)
540 rdev->config.cayman.mem_row_size_in_kb = 4;
541 /* XXX use MC settings? */
542 rdev->config.cayman.shader_engine_tile_size = 32;
543 rdev->config.cayman.num_gpus = 1;
544 rdev->config.cayman.multi_gpu_tile_size = 64;
545
fecf1d07
AD		 546 tmp = (gb_addr_config & NUM_PIPES_MASK) >> NUM_PIPES_SHIFT;
547 rdev->config.cayman.num_tile_pipes = (1 << tmp);
548 tmp = (gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT;
549 rdev->config.cayman.mem_max_burst_length_bytes = (tmp + 1) * 256;
550 tmp = (gb_addr_config & NUM_SHADER_ENGINES_MASK) >> NUM_SHADER_ENGINES_SHIFT;
551 rdev->config.cayman.num_shader_engines = tmp + 1;
552 tmp = (gb_addr_config & NUM_GPUS_MASK) >> NUM_GPUS_SHIFT;
553 rdev->config.cayman.num_gpus = tmp + 1;
554 tmp = (gb_addr_config & MULTI_GPU_TILE_SIZE_MASK) >> MULTI_GPU_TILE_SIZE_SHIFT;
555 rdev->config.cayman.multi_gpu_tile_size = 1 << tmp;
556 tmp = (gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT;
557 rdev->config.cayman.mem_row_size_in_kb = 1 << tmp;
558
416a2bd2 559
fecf1d07
AD		 560 /* setup tiling info dword. gb_addr_config is not adequate since it does
561 * not have bank info, so create a custom tiling dword.
562 * bits 3:0 num_pipes
563 * bits 7:4 num_banks
564 * bits 11:8 group_size
565 * bits 15:12 row_size
566 */
567 rdev->config.cayman.tile_config = 0;
568 switch (rdev->config.cayman.num_tile_pipes) {
569 case 1:
570 default:
571 rdev->config.cayman.tile_config |= (0 << 0);
572 break;
573 case 2:
574 rdev->config.cayman.tile_config |= (1 << 0);
575 break;
576 case 4:
577 rdev->config.cayman.tile_config |= (2 << 0);
578 break;
579 case 8:
580 rdev->config.cayman.tile_config |= (3 << 0);
581 break;
582 }
7b76e479
AD		 583
584 /* num banks is 8 on all fusion asics. 0 = 4, 1 = 8, 2 = 16 */
585 if (rdev->flags & RADEON_IS_IGP)
1f73cca7 586 rdev->config.cayman.tile_config |= 1 << 4;
29d65406 587 else {
5b23c904
AD		 588 switch ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) {
589 case 0: /* four banks */
29d65406 590 rdev->config.cayman.tile_config |= 0 << 4;
5b23c904
AD		 591 break;
592 case 1: /* eight banks */
593 rdev->config.cayman.tile_config |= 1 << 4;
594 break;
595 case 2: /* sixteen banks */
596 default:
597 rdev->config.cayman.tile_config |= 2 << 4;
598 break;
599 }
29d65406 600 }
fecf1d07 601 rdev->config.cayman.tile_config |=
cde5083b 602 ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8;
fecf1d07
AD		 603 rdev->config.cayman.tile_config |=
604 ((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12;
605
416a2bd2
AD		 606 tmp = 0;
607 for (i = (rdev->config.cayman.max_shader_engines - 1); i >= 0; i--) {
608 u32 rb_disable_bitmap;
609
610 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
611 WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
612 rb_disable_bitmap = (RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000) >> 16;
613 tmp <<= 4;
614 tmp |= rb_disable_bitmap;
615 }
616 /* enabled rb are just the one not disabled :) */
617 disabled_rb_mask = tmp;
cedb655a
AD		 618 tmp = 0;
619 for (i = 0; i < (rdev->config.cayman.max_backends_per_se * rdev->config.cayman.max_shader_engines); i++)
620 tmp |= (1 << i);
621 /* if all the backends are disabled, fix it up here */
622 if ((disabled_rb_mask & tmp) == tmp) {
623 for (i = 0; i < (rdev->config.cayman.max_backends_per_se * rdev->config.cayman.max_shader_engines); i++)
624 disabled_rb_mask &= ~(1 << i);
625 }
416a2bd2
AD		 626
627 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
628 WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
629
fecf1d07
AD		 630 WREG32(GB_ADDR_CONFIG, gb_addr_config);
631 WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
7c1c7c18
AD		 632 if (ASIC_IS_DCE6(rdev))
633 WREG32(DMIF_ADDR_CALC, gb_addr_config);
fecf1d07 634 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
f60cbd11
AD		 635 WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
636 WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);
9a21059d
CK		 637 WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config);
638 WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
639 WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
fecf1d07 640
8f612b23
AD		 641 if ((rdev->config.cayman.max_backends_per_se == 1) &&
642 (rdev->flags & RADEON_IS_IGP)) {
643 if ((disabled_rb_mask & 3) == 1) {
644 /* RB0 disabled, RB1 enabled */
645 tmp = 0x11111111;
646 } else {
647 /* RB1 disabled, RB0 enabled */
648 tmp = 0x00000000;
649 }
650 } else {
651 tmp = gb_addr_config & NUM_PIPES_MASK;
652 tmp = r6xx_remap_render_backend(rdev, tmp,
653 rdev->config.cayman.max_backends_per_se *
654 rdev->config.cayman.max_shader_engines,
655 CAYMAN_MAX_BACKENDS, disabled_rb_mask);
656 }
416a2bd2 657 WREG32(GB_BACKEND_MAP, tmp);
fecf1d07 658
416a2bd2
AD		 659 cgts_tcc_disable = 0xffff0000;
660 for (i = 0; i < rdev->config.cayman.max_texture_channel_caches; i++)
661 cgts_tcc_disable &= ~(1 << (16 + i));
fecf1d07
AD		 662 WREG32(CGTS_TCC_DISABLE, cgts_tcc_disable);
663 WREG32(CGTS_SYS_TCC_DISABLE, cgts_tcc_disable);
fecf1d07
AD		 664 WREG32(CGTS_USER_SYS_TCC_DISABLE, cgts_tcc_disable);
665 WREG32(CGTS_USER_TCC_DISABLE, cgts_tcc_disable);
666
667 /* reprogram the shader complex */
668 cgts_sm_ctrl_reg = RREG32(CGTS_SM_CTRL_REG);
669 for (i = 0; i < 16; i++)
670 WREG32(CGTS_SM_CTRL_REG, OVERRIDE);
671 WREG32(CGTS_SM_CTRL_REG, cgts_sm_ctrl_reg);
672
673 /* set HW defaults for 3D engine */
674 WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60));
675
676 sx_debug_1 = RREG32(SX_DEBUG_1);
677 sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
678 WREG32(SX_DEBUG_1, sx_debug_1);
679
680 smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
681 smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff);
285e042d 682 smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.cayman.sx_num_of_sets);
fecf1d07
AD		 683 WREG32(SMX_DC_CTL0, smx_dc_ctl0);
684
685 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4) | CRC_SIMD_ID_WADDR_DISABLE);
686
687 /* need to be explicitly zero-ed */
688 WREG32(VGT_OFFCHIP_LDS_BASE, 0);
689 WREG32(SQ_LSTMP_RING_BASE, 0);
690 WREG32(SQ_HSTMP_RING_BASE, 0);
691 WREG32(SQ_ESTMP_RING_BASE, 0);
692 WREG32(SQ_GSTMP_RING_BASE, 0);
693 WREG32(SQ_VSTMP_RING_BASE, 0);
694 WREG32(SQ_PSTMP_RING_BASE, 0);
695
696 WREG32(TA_CNTL_AUX, DISABLE_CUBE_ANISO);
697
285e042d
DA		 698 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.cayman.sx_max_export_size / 4) - 1) |
699 POSITION_BUFFER_SIZE((rdev->config.cayman.sx_max_export_pos_size / 4) - 1) |
700 SMX_BUFFER_SIZE((rdev->config.cayman.sx_max_export_smx_size / 4) - 1)));
fecf1d07 701
285e042d
DA		 702 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.cayman.sc_prim_fifo_size) |
703 SC_HIZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_hiz_tile_fifo_size) |
704 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_earlyz_tile_fifo_size)));
fecf1d07
AD		 705
706
707 WREG32(VGT_NUM_INSTANCES, 1);
708
709 WREG32(CP_PERFMON_CNTL, 0);
710
285e042d 711 WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.cayman.sq_num_cf_insts) |
fecf1d07
AD		 712 FETCH_FIFO_HIWATER(0x4) |
713 DONE_FIFO_HIWATER(0xe0) |
714 ALU_UPDATE_FIFO_HIWATER(0x8)));
715
716 WREG32(SQ_GPR_RESOURCE_MGMT_1, NUM_CLAUSE_TEMP_GPRS(4));
717 WREG32(SQ_CONFIG, (VC_ENABLE |
718 EXPORT_SRC_C |
719 GFX_PRIO(0) |
720 CS1_PRIO(0) |
721 CS2_PRIO(1)));
722 WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, DYN_GPR_ENABLE);
723
724 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
725 FORCE_EOV_MAX_REZ_CNT(255)));
726
727 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) |
728 AUTO_INVLD_EN(ES_AND_GS_AUTO));
729
730 WREG32(VGT_GS_VERTEX_REUSE, 16);
731 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
732
733 WREG32(CB_PERF_CTR0_SEL_0, 0);
734 WREG32(CB_PERF_CTR0_SEL_1, 0);
735 WREG32(CB_PERF_CTR1_SEL_0, 0);
736 WREG32(CB_PERF_CTR1_SEL_1, 0);
737 WREG32(CB_PERF_CTR2_SEL_0, 0);
738 WREG32(CB_PERF_CTR2_SEL_1, 0);
739 WREG32(CB_PERF_CTR3_SEL_0, 0);
740 WREG32(CB_PERF_CTR3_SEL_1, 0);
741
0b65f83f
DA		 742 tmp = RREG32(HDP_MISC_CNTL);
743 tmp |= HDP_FLUSH_INVALIDATE_CACHE;
744 WREG32(HDP_MISC_CNTL, tmp);
745
fecf1d07
AD		 746 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
747 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
748
749 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
750
751 udelay(50);
752}
753
fa8198ea
AD		 754/*
755 * GART
756 */
757void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev)
758{
759 /* flush hdp cache */
760 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
761
762 /* bits 0-7 are the VM contexts0-7 */
763 WREG32(VM_INVALIDATE_REQUEST, 1);
764}
765
1109ca09 766static int cayman_pcie_gart_enable(struct radeon_device *rdev)
fa8198ea 767{
721604a1 768 int i, r;
fa8198ea 769
c9a1be96 770 if (rdev->gart.robj == NULL) {
fa8198ea
AD		 771 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
772 return -EINVAL;
773 }
774 r = radeon_gart_table_vram_pin(rdev);
775 if (r)
776 return r;
777 radeon_gart_restore(rdev);
778 /* Setup TLB control */
721604a1
JG		 779 WREG32(MC_VM_MX_L1_TLB_CNTL,
780 (0xA << 7) |
781 ENABLE_L1_TLB |
fa8198ea
AD		 782 ENABLE_L1_FRAGMENT_PROCESSING |
783 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
721604a1 784 ENABLE_ADVANCED_DRIVER_MODEL |
fa8198ea
AD		 785 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
786 /* Setup L2 cache */
787 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE |
788 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
789 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
790 EFFECTIVE_L2_QUEUE_SIZE(7) |
791 CONTEXT1_IDENTITY_ACCESS_MODE(1));
792 WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE);
793 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
794 L2_CACHE_BIGK_FRAGMENT_SIZE(6));
795 /* setup context0 */
796 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
797 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
798 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
799 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
800 (u32)(rdev->dummy_page.addr >> 12));
801 WREG32(VM_CONTEXT0_CNTL2, 0);
802 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
803 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
721604a1
JG		 804
805 WREG32(0x15D4, 0);
806 WREG32(0x15D8, 0);
807 WREG32(0x15DC, 0);
808
809 /* empty context1-7 */
23d4f1f2
AD		 810 /* Assign the pt base to something valid for now; the pts used for
811 * the VMs are determined by the application and setup and assigned
812 * on the fly in the vm part of radeon_gart.c
813 */
721604a1
JG		 814 for (i = 1; i < 8; i++) {
815 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR + (i << 2), 0);
c1a7ca0d 816 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR + (i << 2), rdev->vm_manager.max_pfn);
721604a1
JG		 817 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2),
818 rdev->gart.table_addr >> 12);
819 }
820
821 /* enable context1-7 */
822 WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
823 (u32)(rdev->dummy_page.addr >> 12));
ae133a11 824 WREG32(VM_CONTEXT1_CNTL2, 4);
fa87e62d 825 WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) |
ae133a11
CK		 826 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT |
827 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT |
828 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT |
829 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT |
830 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT |
831 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT |
832 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT |
833 VALID_PROTECTION_FAULT_ENABLE_DEFAULT |
834 READ_PROTECTION_FAULT_ENABLE_INTERRUPT |
835 READ_PROTECTION_FAULT_ENABLE_DEFAULT |
836 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT |
837 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT);
fa8198ea
AD		 838
839 cayman_pcie_gart_tlb_flush(rdev);
fcf4de5a
TV		 840 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
841 (unsigned)(rdev->mc.gtt_size >> 20),
842 (unsigned long long)rdev->gart.table_addr);
fa8198ea
AD		 843 rdev->gart.ready = true;
844 return 0;
845}
846
1109ca09 847static void cayman_pcie_gart_disable(struct radeon_device *rdev)
fa8198ea 848{
fa8198ea
AD		 849 /* Disable all tables */
850 WREG32(VM_CONTEXT0_CNTL, 0);
851 WREG32(VM_CONTEXT1_CNTL, 0);
852 /* Setup TLB control */
853 WREG32(MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING |
854 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
855 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
856 /* Setup L2 cache */
857 WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
858 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
859 EFFECTIVE_L2_QUEUE_SIZE(7) |
860 CONTEXT1_IDENTITY_ACCESS_MODE(1));
861 WREG32(VM_L2_CNTL2, 0);
862 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
863 L2_CACHE_BIGK_FRAGMENT_SIZE(6));
c9a1be96 864 radeon_gart_table_vram_unpin(rdev);
fa8198ea
AD		 865}
866
1109ca09 867static void cayman_pcie_gart_fini(struct radeon_device *rdev)
fa8198ea
AD		 868{
869 cayman_pcie_gart_disable(rdev);
870 radeon_gart_table_vram_free(rdev);
871 radeon_gart_fini(rdev);
872}
873
1b37078b
AD		 874void cayman_cp_int_cntl_setup(struct radeon_device *rdev,
875 int ring, u32 cp_int_cntl)
876{
877 u32 srbm_gfx_cntl = RREG32(SRBM_GFX_CNTL) & ~3;
878
879 WREG32(SRBM_GFX_CNTL, srbm_gfx_cntl | (ring & 3));
880 WREG32(CP_INT_CNTL, cp_int_cntl);
881}
882
0c88a02e
AD		 883/*
884 * CP.
885 */
b40e7e16
AD		 886void cayman_fence_ring_emit(struct radeon_device *rdev,
887 struct radeon_fence *fence)
888{
889 struct radeon_ring *ring = &rdev->ring[fence->ring];
890 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
891
721604a1
JG		 892 /* flush read cache over gart for this vmid */
893 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
894 radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
895 radeon_ring_write(ring, 0);
b40e7e16
AD		 896 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
897 radeon_ring_write(ring, PACKET3_TC_ACTION_ENA | PACKET3_SH_ACTION_ENA);
898 radeon_ring_write(ring, 0xFFFFFFFF);
899 radeon_ring_write(ring, 0);
900 radeon_ring_write(ring, 10); /* poll interval */
901 /* EVENT_WRITE_EOP - flush caches, send int */
902 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
903 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5));
904 radeon_ring_write(ring, addr & 0xffffffff);
905 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
906 radeon_ring_write(ring, fence->seq);
907 radeon_ring_write(ring, 0);
908}
909
721604a1
JG		 910void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
911{
876dc9f3 912 struct radeon_ring *ring = &rdev->ring[ib->ring];
721604a1
JG		 913
914 /* set to DX10/11 mode */
915 radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0));
916 radeon_ring_write(ring, 1);
45df6803
CK		 917
918 if (ring->rptr_save_reg) {
919 uint32_t next_rptr = ring->wptr + 3 + 4 + 8;
920 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
921 radeon_ring_write(ring, ((ring->rptr_save_reg -
922 PACKET3_SET_CONFIG_REG_START) >> 2));
923 radeon_ring_write(ring, next_rptr);
924 }
925
721604a1
JG		 926 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
927 radeon_ring_write(ring,
928#ifdef __BIG_ENDIAN
929 (2 << 0) |
930#endif
931 (ib->gpu_addr & 0xFFFFFFFC));
932 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF);
4bf3dd92
CK		 933 radeon_ring_write(ring, ib->length_dw |
934 (ib->vm ? (ib->vm->id << 24) : 0));
721604a1
JG		 935
936 /* flush read cache over gart for this vmid */
937 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
938 radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
4bf3dd92 939 radeon_ring_write(ring, ib->vm ? ib->vm->id : 0);
721604a1
JG		 940 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
941 radeon_ring_write(ring, PACKET3_TC_ACTION_ENA | PACKET3_SH_ACTION_ENA);
942 radeon_ring_write(ring, 0xFFFFFFFF);
943 radeon_ring_write(ring, 0);
944 radeon_ring_write(ring, 10); /* poll interval */
945}
946
f2ba57b5
CK		 947void cayman_uvd_semaphore_emit(struct radeon_device *rdev,
948 struct radeon_ring *ring,
949 struct radeon_semaphore *semaphore,
950 bool emit_wait)
951{
952 uint64_t addr = semaphore->gpu_addr;
953
954 radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_LOW, 0));
955 radeon_ring_write(ring, (addr >> 3) & 0x000FFFFF);
956
957 radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_HIGH, 0));
958 radeon_ring_write(ring, (addr >> 23) & 0x000FFFFF);
959
960 radeon_ring_write(ring, PACKET0(UVD_SEMA_CMD, 0));
961 radeon_ring_write(ring, 0x80 | (emit_wait ? 1 : 0));
962}
963
0c88a02e
AD		 964static void cayman_cp_enable(struct radeon_device *rdev, bool enable)
965{
966 if (enable)
967 WREG32(CP_ME_CNTL, 0);
968 else {
38f1cff0 969 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
0c88a02e
AD		 970 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
971 WREG32(SCRATCH_UMSK, 0);
f60cbd11 972 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
0c88a02e
AD		 973 }
974}
975
976static int cayman_cp_load_microcode(struct radeon_device *rdev)
977{
978 const __be32 *fw_data;
979 int i;
980
981 if (!rdev->me_fw || !rdev->pfp_fw)
982 return -EINVAL;
983
984 cayman_cp_enable(rdev, false);
985
986 fw_data = (const __be32 *)rdev->pfp_fw->data;
987 WREG32(CP_PFP_UCODE_ADDR, 0);
988 for (i = 0; i < CAYMAN_PFP_UCODE_SIZE; i++)
989 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
990 WREG32(CP_PFP_UCODE_ADDR, 0);
991
992 fw_data = (const __be32 *)rdev->me_fw->data;
993 WREG32(CP_ME_RAM_WADDR, 0);
994 for (i = 0; i < CAYMAN_PM4_UCODE_SIZE; i++)
995 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
996
997 WREG32(CP_PFP_UCODE_ADDR, 0);
998 WREG32(CP_ME_RAM_WADDR, 0);
999 WREG32(CP_ME_RAM_RADDR, 0);
1000 return 0;
1001}
1002
1003static int cayman_cp_start(struct radeon_device *rdev)
1004{
e32eb50d 1005 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
0c88a02e
AD		 1006 int r, i;
1007
e32eb50d 1008 r = radeon_ring_lock(rdev, ring, 7);
0c88a02e
AD		 1009 if (r) {
1010 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1011 return r;
1012 }
e32eb50d
CK		 1013 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
1014 radeon_ring_write(ring, 0x1);
1015 radeon_ring_write(ring, 0x0);
1016 radeon_ring_write(ring, rdev->config.cayman.max_hw_contexts - 1);
1017 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1018 radeon_ring_write(ring, 0);
1019 radeon_ring_write(ring, 0);
1020 radeon_ring_unlock_commit(rdev, ring);
0c88a02e
AD		 1021
1022 cayman_cp_enable(rdev, true);
1023
e32eb50d 1024 r = radeon_ring_lock(rdev, ring, cayman_default_size + 19);
0c88a02e
AD		 1025 if (r) {
1026 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1027 return r;
1028 }
1029
1030 /* setup clear context state */
e32eb50d
CK		 1031 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1032 radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
0c88a02e
AD		 1033
1034 for (i = 0; i < cayman_default_size; i++)
e32eb50d 1035 radeon_ring_write(ring, cayman_default_state[i]);
0c88a02e 1036
e32eb50d
CK		 1037 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1038 radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
0c88a02e
AD		 1039
1040 /* set clear context state */
e32eb50d
CK		 1041 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
1042 radeon_ring_write(ring, 0);
0c88a02e
AD		 1043
1044 /* SQ_VTX_BASE_VTX_LOC */
e32eb50d
CK		 1045 radeon_ring_write(ring, 0xc0026f00);
1046 radeon_ring_write(ring, 0x00000000);
1047 radeon_ring_write(ring, 0x00000000);
1048 radeon_ring_write(ring, 0x00000000);
0c88a02e
AD		 1049
1050 /* Clear consts */
e32eb50d
CK		 1051 radeon_ring_write(ring, 0xc0036f00);
1052 radeon_ring_write(ring, 0x00000bc4);
1053 radeon_ring_write(ring, 0xffffffff);
1054 radeon_ring_write(ring, 0xffffffff);
1055 radeon_ring_write(ring, 0xffffffff);
0c88a02e 1056
e32eb50d
CK		 1057 radeon_ring_write(ring, 0xc0026900);
1058 radeon_ring_write(ring, 0x00000316);
1059 radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
1060 radeon_ring_write(ring, 0x00000010); /* */
9b91d18d 1061
e32eb50d 1062 radeon_ring_unlock_commit(rdev, ring);
0c88a02e
AD		 1063
1064 /* XXX init other rings */
1065
1066 return 0;
1067}
1068
755d819e
AD		 1069static void cayman_cp_fini(struct radeon_device *rdev)
1070{
45df6803 1071 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
755d819e 1072 cayman_cp_enable(rdev, false);
45df6803
CK		 1073 radeon_ring_fini(rdev, ring);
1074 radeon_scratch_free(rdev, ring->rptr_save_reg);
755d819e
AD		 1075}
1076
1109ca09 1077static int cayman_cp_resume(struct radeon_device *rdev)
0c88a02e 1078{
b90ca986
CK		 1079 static const int ridx[] = {
1080 RADEON_RING_TYPE_GFX_INDEX,
1081 CAYMAN_RING_TYPE_CP1_INDEX,
1082 CAYMAN_RING_TYPE_CP2_INDEX
1083 };
1084 static const unsigned cp_rb_cntl[] = {
1085 CP_RB0_CNTL,
1086 CP_RB1_CNTL,
1087 CP_RB2_CNTL,
1088 };
1089 static const unsigned cp_rb_rptr_addr[] = {
1090 CP_RB0_RPTR_ADDR,
1091 CP_RB1_RPTR_ADDR,
1092 CP_RB2_RPTR_ADDR
1093 };
1094 static const unsigned cp_rb_rptr_addr_hi[] = {
1095 CP_RB0_RPTR_ADDR_HI,
1096 CP_RB1_RPTR_ADDR_HI,
1097 CP_RB2_RPTR_ADDR_HI
1098 };
1099 static const unsigned cp_rb_base[] = {
1100 CP_RB0_BASE,
1101 CP_RB1_BASE,
1102 CP_RB2_BASE
1103 };
e32eb50d 1104 struct radeon_ring *ring;
b90ca986 1105 int i, r;
0c88a02e
AD		 1106
1107 /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
1108 WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
1109 SOFT_RESET_PA |
1110 SOFT_RESET_SH |
1111 SOFT_RESET_VGT |
a49a50da 1112 SOFT_RESET_SPI |
0c88a02e
AD		 1113 SOFT_RESET_SX));
1114 RREG32(GRBM_SOFT_RESET);
1115 mdelay(15);
1116 WREG32(GRBM_SOFT_RESET, 0);
1117 RREG32(GRBM_SOFT_RESET);
1118
15d3332f 1119 WREG32(CP_SEM_WAIT_TIMER, 0x0);
11ef3f1f 1120 WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
0c88a02e
AD		 1121
1122 /* Set the write pointer delay */
1123 WREG32(CP_RB_WPTR_DELAY, 0);
1124
1125 WREG32(CP_DEBUG, (1 << 27));
1126
48fc7f7e 1127 /* set the wb address whether it's enabled or not */
0c88a02e 1128 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
b90ca986 1129 WREG32(SCRATCH_UMSK, 0xff);
0c88a02e 1130
b90ca986
CK		 1131 for (i = 0; i < 3; ++i) {
1132 uint32_t rb_cntl;
1133 uint64_t addr;
0c88a02e 1134
b90ca986
CK		 1135 /* Set ring buffer size */
1136 ring = &rdev->ring[ridx[i]];
1137 rb_cntl = drm_order(ring->ring_size / 8);
1138 rb_cntl |= drm_order(RADEON_GPU_PAGE_SIZE/8) << 8;
0c88a02e 1139#ifdef __BIG_ENDIAN
b90ca986 1140 rb_cntl |= BUF_SWAP_32BIT;
0c88a02e 1141#endif
b90ca986 1142 WREG32(cp_rb_cntl[i], rb_cntl);
0c88a02e 1143
48fc7f7e 1144 /* set the wb address whether it's enabled or not */
b90ca986
CK		 1145 addr = rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET;
1146 WREG32(cp_rb_rptr_addr[i], addr & 0xFFFFFFFC);
1147 WREG32(cp_rb_rptr_addr_hi[i], upper_32_bits(addr) & 0xFF);
1148 }
0c88a02e 1149
b90ca986
CK		 1150 /* set the rb base addr, this causes an internal reset of ALL rings */
1151 for (i = 0; i < 3; ++i) {
1152 ring = &rdev->ring[ridx[i]];
1153 WREG32(cp_rb_base[i], ring->gpu_addr >> 8);
1154 }
0c88a02e 1155
b90ca986
CK		 1156 for (i = 0; i < 3; ++i) {
1157 /* Initialize the ring buffer's read and write pointers */
1158 ring = &rdev->ring[ridx[i]];
1159 WREG32_P(cp_rb_cntl[i], RB_RPTR_WR_ENA, ~RB_RPTR_WR_ENA);
0c88a02e 1160
b90ca986
CK		 1161 ring->rptr = ring->wptr = 0;
1162 WREG32(ring->rptr_reg, ring->rptr);
1163 WREG32(ring->wptr_reg, ring->wptr);
0c88a02e 1164
b90ca986
CK		 1165 mdelay(1);
1166 WREG32_P(cp_rb_cntl[i], 0, ~RB_RPTR_WR_ENA);
1167 }
0c88a02e
AD		 1168
1169 /* start the rings */
1170 cayman_cp_start(rdev);
e32eb50d
CK		 1171 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = true;
1172 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
1173 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
0c88a02e 1174 /* this only test cp0 */
f712812e 1175 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
0c88a02e 1176 if (r) {
e32eb50d
CK		 1177 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1178 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
1179 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
0c88a02e
AD		 1180 return r;
1181 }
1182
1183 return 0;
1184}
1185
f60cbd11
AD		 1186/*
1187 * DMA
1188 * Starting with R600, the GPU has an asynchronous
1189 * DMA engine. The programming model is very similar
1190 * to the 3D engine (ring buffer, IBs, etc.), but the
1191 * DMA controller has it's own packet format that is
1192 * different form the PM4 format used by the 3D engine.
1193 * It supports copying data, writing embedded data,
1194 * solid fills, and a number of other things. It also
1195 * has support for tiling/detiling of buffers.
1196 * Cayman and newer support two asynchronous DMA engines.
1197 */
1198/**
1199 * cayman_dma_ring_ib_execute - Schedule an IB on the DMA engine
1200 *
1201 * @rdev: radeon_device pointer
1202 * @ib: IB object to schedule
1203 *
1204 * Schedule an IB in the DMA ring (cayman-SI).
1205 */
1206void cayman_dma_ring_ib_execute(struct radeon_device *rdev,
1207 struct radeon_ib *ib)
1208{
1209 struct radeon_ring *ring = &rdev->ring[ib->ring];
1210
1211 if (rdev->wb.enabled) {
1212 u32 next_rptr = ring->wptr + 4;
1213 while ((next_rptr & 7) != 5)
1214 next_rptr++;
1215 next_rptr += 3;
1216 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1));
1217 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
1218 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff);
1219 radeon_ring_write(ring, next_rptr);
1220 }
1221
1222 /* The indirect buffer packet must end on an 8 DW boundary in the DMA ring.
1223 * Pad as necessary with NOPs.
1224 */
1225 while ((ring->wptr & 7) != 5)
1226 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
1227 radeon_ring_write(ring, DMA_IB_PACKET(DMA_PACKET_INDIRECT_BUFFER, ib->vm ? ib->vm->id : 0, 0));
1228 radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0));
1229 radeon_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF));
1230
1231}
1232
1233/**
1234 * cayman_dma_stop - stop the async dma engines
1235 *
1236 * @rdev: radeon_device pointer
1237 *
1238 * Stop the async dma engines (cayman-SI).
1239 */
1240void cayman_dma_stop(struct radeon_device *rdev)
1241{
1242 u32 rb_cntl;
1243
1244 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1245
1246 /* dma0 */
1247 rb_cntl = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);
1248 rb_cntl &= ~DMA_RB_ENABLE;
1249 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, rb_cntl);
1250
1251 /* dma1 */
1252 rb_cntl = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);
1253 rb_cntl &= ~DMA_RB_ENABLE;
1254 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, rb_cntl);
1255
1256 rdev->ring[R600_RING_TYPE_DMA_INDEX].ready = false;
1257 rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX].ready = false;
1258}
1259
1260/**
1261 * cayman_dma_resume - setup and start the async dma engines
1262 *
1263 * @rdev: radeon_device pointer
1264 *
1265 * Set up the DMA ring buffers and enable them. (cayman-SI).
1266 * Returns 0 for success, error for failure.
1267 */
1268int cayman_dma_resume(struct radeon_device *rdev)
1269{
1270 struct radeon_ring *ring;
b3dfcb20 1271 u32 rb_cntl, dma_cntl, ib_cntl;
f60cbd11
AD		 1272 u32 rb_bufsz;
1273 u32 reg_offset, wb_offset;
1274 int i, r;
1275
1276 /* Reset dma */
1277 WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA | SOFT_RESET_DMA1);
1278 RREG32(SRBM_SOFT_RESET);
1279 udelay(50);
1280 WREG32(SRBM_SOFT_RESET, 0);
1281
1282 for (i = 0; i < 2; i++) {
1283 if (i == 0) {
1284 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
1285 reg_offset = DMA0_REGISTER_OFFSET;
1286 wb_offset = R600_WB_DMA_RPTR_OFFSET;
1287 } else {
1288 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
1289 reg_offset = DMA1_REGISTER_OFFSET;
1290 wb_offset = CAYMAN_WB_DMA1_RPTR_OFFSET;
1291 }
1292
1293 WREG32(DMA_SEM_INCOMPLETE_TIMER_CNTL + reg_offset, 0);
1294 WREG32(DMA_SEM_WAIT_FAIL_TIMER_CNTL + reg_offset, 0);
1295
1296 /* Set ring buffer size in dwords */
1297 rb_bufsz = drm_order(ring->ring_size / 4);
1298 rb_cntl = rb_bufsz << 1;
1299#ifdef __BIG_ENDIAN
1300 rb_cntl |= DMA_RB_SWAP_ENABLE | DMA_RPTR_WRITEBACK_SWAP_ENABLE;
1301#endif
1302 WREG32(DMA_RB_CNTL + reg_offset, rb_cntl);
1303
1304 /* Initialize the ring buffer's read and write pointers */
1305 WREG32(DMA_RB_RPTR + reg_offset, 0);
1306 WREG32(DMA_RB_WPTR + reg_offset, 0);
1307
1308 /* set the wb address whether it's enabled or not */
1309 WREG32(DMA_RB_RPTR_ADDR_HI + reg_offset,
1310 upper_32_bits(rdev->wb.gpu_addr + wb_offset) & 0xFF);
1311 WREG32(DMA_RB_RPTR_ADDR_LO + reg_offset,
1312 ((rdev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC));
1313
1314 if (rdev->wb.enabled)
1315 rb_cntl |= DMA_RPTR_WRITEBACK_ENABLE;
1316
1317 WREG32(DMA_RB_BASE + reg_offset, ring->gpu_addr >> 8);
1318
1319 /* enable DMA IBs */
b3dfcb20
MD		 1320 ib_cntl = DMA_IB_ENABLE | CMD_VMID_FORCE;
1321#ifdef __BIG_ENDIAN
1322 ib_cntl |= DMA_IB_SWAP_ENABLE;
1323#endif
1324 WREG32(DMA_IB_CNTL + reg_offset, ib_cntl);
f60cbd11
AD		 1325
1326 dma_cntl = RREG32(DMA_CNTL + reg_offset);
1327 dma_cntl &= ~CTXEMPTY_INT_ENABLE;
1328 WREG32(DMA_CNTL + reg_offset, dma_cntl);
1329
1330 ring->wptr = 0;
1331 WREG32(DMA_RB_WPTR + reg_offset, ring->wptr << 2);
1332
1333 ring->rptr = RREG32(DMA_RB_RPTR + reg_offset) >> 2;
1334
1335 WREG32(DMA_RB_CNTL + reg_offset, rb_cntl | DMA_RB_ENABLE);
1336
1337 ring->ready = true;
1338
1339 r = radeon_ring_test(rdev, ring->idx, ring);
1340 if (r) {
1341 ring->ready = false;
1342 return r;
1343 }
1344 }
1345
1346 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
1347
1348 return 0;
1349}
1350
1351/**
1352 * cayman_dma_fini - tear down the async dma engines
1353 *
1354 * @rdev: radeon_device pointer
1355 *
1356 * Stop the async dma engines and free the rings (cayman-SI).
1357 */
1358void cayman_dma_fini(struct radeon_device *rdev)
1359{
1360 cayman_dma_stop(rdev);
1361 radeon_ring_fini(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX]);
1362 radeon_ring_fini(rdev, &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]);
1363}
1364
168757ea 1365static u32 cayman_gpu_check_soft_reset(struct radeon_device *rdev)
271d6fed 1366{
168757ea 1367 u32 reset_mask = 0;
187e3593 1368 u32 tmp;
271d6fed 1369
168757ea
AD		 1370 /* GRBM_STATUS */
1371 tmp = RREG32(GRBM_STATUS);
1372 if (tmp & (PA_BUSY | SC_BUSY |
1373 SH_BUSY | SX_BUSY |
1374 TA_BUSY | VGT_BUSY |
1375 DB_BUSY | CB_BUSY |
1376 GDS_BUSY | SPI_BUSY |
1377 IA_BUSY | IA_BUSY_NO_DMA))
1378 reset_mask |= RADEON_RESET_GFX;
1379
1380 if (tmp & (CF_RQ_PENDING | PF_RQ_PENDING |
1381 CP_BUSY | CP_COHERENCY_BUSY))
1382 reset_mask |= RADEON_RESET_CP;
1383
1384 if (tmp & GRBM_EE_BUSY)
1385 reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP;
1386
1387 /* DMA_STATUS_REG 0 */
1388 tmp = RREG32(DMA_STATUS_REG + DMA0_REGISTER_OFFSET);
1389 if (!(tmp & DMA_IDLE))
1390 reset_mask |= RADEON_RESET_DMA;
1391
1392 /* DMA_STATUS_REG 1 */
1393 tmp = RREG32(DMA_STATUS_REG + DMA1_REGISTER_OFFSET);
1394 if (!(tmp & DMA_IDLE))
1395 reset_mask |= RADEON_RESET_DMA1;
1396
1397 /* SRBM_STATUS2 */
1398 tmp = RREG32(SRBM_STATUS2);
1399 if (tmp & DMA_BUSY)
1400 reset_mask |= RADEON_RESET_DMA;
1401
1402 if (tmp & DMA1_BUSY)
1403 reset_mask |= RADEON_RESET_DMA1;
1404
1405 /* SRBM_STATUS */
1406 tmp = RREG32(SRBM_STATUS);
1407 if (tmp & (RLC_RQ_PENDING | RLC_BUSY))
1408 reset_mask |= RADEON_RESET_RLC;
1409
1410 if (tmp & IH_BUSY)
1411 reset_mask |= RADEON_RESET_IH;
1412
1413 if (tmp & SEM_BUSY)
1414 reset_mask |= RADEON_RESET_SEM;
1415
1416 if (tmp & GRBM_RQ_PENDING)
1417 reset_mask |= RADEON_RESET_GRBM;
1418
1419 if (tmp & VMC_BUSY)
1420 reset_mask |= RADEON_RESET_VMC;
19fc42ed 1421
168757ea
AD		 1422 if (tmp & (MCB_BUSY | MCB_NON_DISPLAY_BUSY |
1423 MCC_BUSY | MCD_BUSY))
1424 reset_mask |= RADEON_RESET_MC;
1425
1426 if (evergreen_is_display_hung(rdev))
1427 reset_mask |= RADEON_RESET_DISPLAY;
1428
1429 /* VM_L2_STATUS */
1430 tmp = RREG32(VM_L2_STATUS);
1431 if (tmp & L2_BUSY)
1432 reset_mask |= RADEON_RESET_VMC;
1433
d808fc88
AD		 1434 /* Skip MC reset as it's mostly likely not hung, just busy */
1435 if (reset_mask & RADEON_RESET_MC) {
1436 DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask);
1437 reset_mask &= ~RADEON_RESET_MC;
1438 }
1439
168757ea
AD		 1440 return reset_mask;
1441}
1442
1443static void cayman_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
1444{
1445 struct evergreen_mc_save save;
1446 u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
1447 u32 tmp;
19fc42ed 1448
271d6fed 1449 if (reset_mask == 0)
168757ea 1450 return;
271d6fed
AD		 1451
1452 dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);
1453
187e3593 1454 evergreen_print_gpu_status_regs(rdev);
271d6fed
AD		 1455 dev_info(rdev->dev, " VM_CONTEXT0_PROTECTION_FAULT_ADDR 0x%08X\n",
1456 RREG32(0x14F8));
1457 dev_info(rdev->dev, " VM_CONTEXT0_PROTECTION_FAULT_STATUS 0x%08X\n",
1458 RREG32(0x14D8));
1459 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
1460 RREG32(0x14FC));
1461 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1462 RREG32(0x14DC));
1463
187e3593
AD		 1464 /* Disable CP parsing/prefetching */
1465 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
1466
1467 if (reset_mask & RADEON_RESET_DMA) {
1468 /* dma0 */
1469 tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);
1470 tmp &= ~DMA_RB_ENABLE;
1471 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp);
168757ea 1472 }
187e3593 1473
168757ea 1474 if (reset_mask & RADEON_RESET_DMA1) {
187e3593
AD		 1475 /* dma1 */
1476 tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);
1477 tmp &= ~DMA_RB_ENABLE;
1478 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp);
1479 }
1480
90fb8779
AD		 1481 udelay(50);
1482
1483 evergreen_mc_stop(rdev, &save);
1484 if (evergreen_mc_wait_for_idle(rdev)) {
1485 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1486 }
1487
187e3593
AD		 1488 if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE)) {
1489 grbm_soft_reset = SOFT_RESET_CB |
1490 SOFT_RESET_DB |
1491 SOFT_RESET_GDS |
1492 SOFT_RESET_PA |
1493 SOFT_RESET_SC |
1494 SOFT_RESET_SPI |
1495 SOFT_RESET_SH |
1496 SOFT_RESET_SX |
1497 SOFT_RESET_TC |
1498 SOFT_RESET_TA |
1499 SOFT_RESET_VGT |
1500 SOFT_RESET_IA;
1501 }
1502
1503 if (reset_mask & RADEON_RESET_CP) {
1504 grbm_soft_reset |= SOFT_RESET_CP | SOFT_RESET_VGT;
1505
1506 srbm_soft_reset |= SOFT_RESET_GRBM;
1507 }
271d6fed
AD		 1508
1509 if (reset_mask & RADEON_RESET_DMA)
168757ea
AD		 1510 srbm_soft_reset |= SOFT_RESET_DMA;
1511
1512 if (reset_mask & RADEON_RESET_DMA1)
1513 srbm_soft_reset |= SOFT_RESET_DMA1;
1514
1515 if (reset_mask & RADEON_RESET_DISPLAY)
1516 srbm_soft_reset |= SOFT_RESET_DC;
1517
1518 if (reset_mask & RADEON_RESET_RLC)
1519 srbm_soft_reset |= SOFT_RESET_RLC;
1520
1521 if (reset_mask & RADEON_RESET_SEM)
1522 srbm_soft_reset |= SOFT_RESET_SEM;
1523
1524 if (reset_mask & RADEON_RESET_IH)
1525 srbm_soft_reset |= SOFT_RESET_IH;
1526
1527 if (reset_mask & RADEON_RESET_GRBM)
1528 srbm_soft_reset |= SOFT_RESET_GRBM;
1529
1530 if (reset_mask & RADEON_RESET_VMC)
1531 srbm_soft_reset |= SOFT_RESET_VMC;
1532
24178ec4
AD		 1533 if (!(rdev->flags & RADEON_IS_IGP)) {
1534 if (reset_mask & RADEON_RESET_MC)
1535 srbm_soft_reset |= SOFT_RESET_MC;
1536 }
187e3593
AD		 1537
1538 if (grbm_soft_reset) {
1539 tmp = RREG32(GRBM_SOFT_RESET);
1540 tmp |= grbm_soft_reset;
1541 dev_info(rdev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
1542 WREG32(GRBM_SOFT_RESET, tmp);
1543 tmp = RREG32(GRBM_SOFT_RESET);
1544
1545 udelay(50);
1546
1547 tmp &= ~grbm_soft_reset;
1548 WREG32(GRBM_SOFT_RESET, tmp);
1549 tmp = RREG32(GRBM_SOFT_RESET);
1550 }
1551
1552 if (srbm_soft_reset) {
1553 tmp = RREG32(SRBM_SOFT_RESET);
1554 tmp |= srbm_soft_reset;
1555 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1556 WREG32(SRBM_SOFT_RESET, tmp);
1557 tmp = RREG32(SRBM_SOFT_RESET);
1558
1559 udelay(50);
1560
1561 tmp &= ~srbm_soft_reset;
1562 WREG32(SRBM_SOFT_RESET, tmp);
1563 tmp = RREG32(SRBM_SOFT_RESET);
1564 }
271d6fed
AD		 1565
1566 /* Wait a little for things to settle down */
1567 udelay(50);
1568
b9952a8a 1569 evergreen_mc_resume(rdev, &save);
187e3593
AD		 1570 udelay(50);
1571
187e3593 1572 evergreen_print_gpu_status_regs(rdev);
b9952a8a
AD		 1573}
1574
1575int cayman_asic_reset(struct radeon_device *rdev)
1576{
168757ea
AD		 1577 u32 reset_mask;
1578
1579 reset_mask = cayman_gpu_check_soft_reset(rdev);
1580
1581 if (reset_mask)
1582 r600_set_bios_scratch_engine_hung(rdev, true);
1583
1584 cayman_gpu_soft_reset(rdev, reset_mask);
1585
1586 reset_mask = cayman_gpu_check_soft_reset(rdev);
1587
1588 if (!reset_mask)
1589 r600_set_bios_scratch_engine_hung(rdev, false);
1590
1591 return 0;
b9952a8a
AD		 1592}
1593
123bc183
AD		 1594/**
1595 * cayman_gfx_is_lockup - Check if the GFX engine is locked up
1596 *
1597 * @rdev: radeon_device pointer
1598 * @ring: radeon_ring structure holding ring information
1599 *
1600 * Check if the GFX engine is locked up.
1601 * Returns true if the engine appears to be locked up, false if not.
1602 */
1603bool cayman_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
1604{
1605 u32 reset_mask = cayman_gpu_check_soft_reset(rdev);
1606
1607 if (!(reset_mask & (RADEON_RESET_GFX |
1608 RADEON_RESET_COMPUTE |
1609 RADEON_RESET_CP))) {
1610 radeon_ring_lockup_update(ring);
1611 return false;
1612 }
1613 /* force CP activities */
1614 radeon_ring_force_activity(rdev, ring);
1615 return radeon_ring_test_lockup(rdev, ring);
1616}
1617
f60cbd11
AD		 1618/**
1619 * cayman_dma_is_lockup - Check if the DMA engine is locked up
1620 *
1621 * @rdev: radeon_device pointer
1622 * @ring: radeon_ring structure holding ring information
1623 *
123bc183 1624 * Check if the async DMA engine is locked up.
f60cbd11
AD		 1625 * Returns true if the engine appears to be locked up, false if not.
1626 */
1627bool cayman_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
1628{
123bc183
AD		 1629 u32 reset_mask = cayman_gpu_check_soft_reset(rdev);
1630 u32 mask;
f60cbd11
AD		 1631
1632 if (ring->idx == R600_RING_TYPE_DMA_INDEX)
123bc183 1633 mask = RADEON_RESET_DMA;
f60cbd11 1634 else
123bc183
AD		 1635 mask = RADEON_RESET_DMA1;
1636
1637 if (!(reset_mask & mask)) {
f60cbd11
AD		 1638 radeon_ring_lockup_update(ring);
1639 return false;
1640 }
1641 /* force ring activities */
1642 radeon_ring_force_activity(rdev, ring);
1643 return radeon_ring_test_lockup(rdev, ring);
1644}
1645
755d819e
AD		 1646static int cayman_startup(struct radeon_device *rdev)
1647{
e32eb50d 1648 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
755d819e
AD		 1649 int r;
1650
b07759bf
IH		 1651 /* enable pcie gen2 link */
1652 evergreen_pcie_gen2_enable(rdev);
1653
c420c745
AD		 1654 if (rdev->flags & RADEON_IS_IGP) {
1655 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
1656 r = ni_init_microcode(rdev);
1657 if (r) {
1658 DRM_ERROR("Failed to load firmware!\n");
1659 return r;
1660 }
1661 }
1662 } else {
1663 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) {
1664 r = ni_init_microcode(rdev);
1665 if (r) {
1666 DRM_ERROR("Failed to load firmware!\n");
1667 return r;
1668 }
1669 }
1670
1671 r = ni_mc_load_microcode(rdev);
755d819e 1672 if (r) {
c420c745 1673 DRM_ERROR("Failed to load MC firmware!\n");
755d819e
AD		 1674 return r;
1675 }
1676 }
755d819e 1677
16cdf04d
AD		 1678 r = r600_vram_scratch_init(rdev);
1679 if (r)
1680 return r;
1681
755d819e
AD		 1682 evergreen_mc_program(rdev);
1683 r = cayman_pcie_gart_enable(rdev);
1684 if (r)
1685 return r;
1686 cayman_gpu_init(rdev);
1687
cb92d452 1688 r = evergreen_blit_init(rdev);
755d819e 1689 if (r) {
fb3d9e97 1690 r600_blit_fini(rdev);
27cd7769 1691 rdev->asic->copy.copy = NULL;
755d819e
AD		 1692 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
1693 }
755d819e 1694
c420c745
AD		 1695 /* allocate rlc buffers */
1696 if (rdev->flags & RADEON_IS_IGP) {
1697 r = si_rlc_init(rdev);
1698 if (r) {
1699 DRM_ERROR("Failed to init rlc BOs!\n");
1700 return r;
1701 }
1702 }
1703
755d819e
AD		 1704 /* allocate wb buffer */
1705 r = radeon_wb_init(rdev);
1706 if (r)
1707 return r;
1708
30eb77f4
JG		 1709 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
1710 if (r) {
1711 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
1712 return r;
1713 }
1714
f2ba57b5
CK		 1715 r = rv770_uvd_resume(rdev);
1716 if (!r) {
1717 r = radeon_fence_driver_start_ring(rdev,
1718 R600_RING_TYPE_UVD_INDEX);
1719 if (r)
1720 dev_err(rdev->dev, "UVD fences init error (%d).\n", r);
1721 }
1722 if (r)
1723 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0;
1724
30eb77f4
JG		 1725 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
1726 if (r) {
1727 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
1728 return r;
1729 }
1730
1731 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
1732 if (r) {
1733 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
1734 return r;
1735 }
1736
f60cbd11
AD		 1737 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX);
1738 if (r) {
1739 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
1740 return r;
1741 }
1742
1743 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_DMA1_INDEX);
1744 if (r) {
1745 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
1746 return r;
1747 }
1748
755d819e
AD		 1749 /* Enable IRQ */
1750 r = r600_irq_init(rdev);
1751 if (r) {
1752 DRM_ERROR("radeon: IH init failed (%d).\n", r);
1753 radeon_irq_kms_fini(rdev);
1754 return r;
1755 }
1756 evergreen_irq_set(rdev);
1757
e32eb50d 1758 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
78c5560a
AD		 1759 CP_RB0_RPTR, CP_RB0_WPTR,
1760 0, 0xfffff, RADEON_CP_PACKET2);
755d819e
AD		 1761 if (r)
1762 return r;
f60cbd11
AD		 1763
1764 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
1765 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
1766 DMA_RB_RPTR + DMA0_REGISTER_OFFSET,
1767 DMA_RB_WPTR + DMA0_REGISTER_OFFSET,
1768 2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
1769 if (r)
1770 return r;
1771
1772 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
1773 r = radeon_ring_init(rdev, ring, ring->ring_size, CAYMAN_WB_DMA1_RPTR_OFFSET,
1774 DMA_RB_RPTR + DMA1_REGISTER_OFFSET,
1775 DMA_RB_WPTR + DMA1_REGISTER_OFFSET,
1776 2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
1777 if (r)
1778 return r;
1779
755d819e
AD		 1780 r = cayman_cp_load_microcode(rdev);
1781 if (r)
1782 return r;
1783 r = cayman_cp_resume(rdev);
1784 if (r)
1785 return r;
1786
f60cbd11
AD		 1787 r = cayman_dma_resume(rdev);
1788 if (r)
1789 return r;
1790
f2ba57b5
CK		 1791 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
1792 if (ring->ring_size) {
1793 r = radeon_ring_init(rdev, ring, ring->ring_size,
1794 R600_WB_UVD_RPTR_OFFSET,
1795 UVD_RBC_RB_RPTR, UVD_RBC_RB_WPTR,
1796 0, 0xfffff, RADEON_CP_PACKET2);
1797 if (!r)
1798 r = r600_uvd_init(rdev);
1799 if (r)
1800 DRM_ERROR("radeon: failed initializing UVD (%d).\n", r);
1801 }
1802
2898c348
CK		 1803 r = radeon_ib_pool_init(rdev);
1804 if (r) {
1805 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
b15ba512 1806 return r;
2898c348 1807 }
b15ba512 1808
c6105f24
CK		 1809 r = radeon_vm_manager_init(rdev);
1810 if (r) {
1811 dev_err(rdev->dev, "vm manager initialization failed (%d).\n", r);
721604a1 1812 return r;
c6105f24 1813 }
721604a1 1814
6b53a050
RM		 1815 r = r600_audio_init(rdev);
1816 if (r)
1817 return r;
1818
755d819e
AD		 1819 return 0;
1820}
1821
1822int cayman_resume(struct radeon_device *rdev)
1823{
1824 int r;
1825
1826 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
1827 * posting will perform necessary task to bring back GPU into good
1828 * shape.
1829 */
1830 /* post card */
1831 atom_asic_init(rdev->mode_info.atom_context);
1832
b15ba512 1833 rdev->accel_working = true;
755d819e
AD		 1834 r = cayman_startup(rdev);
1835 if (r) {
1836 DRM_ERROR("cayman startup failed on resume\n");
6b7746e8 1837 rdev->accel_working = false;
755d819e
AD		 1838 return r;
1839 }
755d819e 1840 return r;
755d819e
AD		 1841}
1842
1843int cayman_suspend(struct radeon_device *rdev)
1844{
6b53a050 1845 r600_audio_fini(rdev);
fa3daf9a 1846 radeon_vm_manager_fini(rdev);
755d819e 1847 cayman_cp_enable(rdev, false);
f60cbd11 1848 cayman_dma_stop(rdev);
f2ba57b5
CK		 1849 r600_uvd_rbc_stop(rdev);
1850 radeon_uvd_suspend(rdev);
755d819e
AD		 1851 evergreen_irq_suspend(rdev);
1852 radeon_wb_disable(rdev);
1853 cayman_pcie_gart_disable(rdev);
755d819e
AD		 1854 return 0;
1855}
1856
1857/* Plan is to move initialization in that function and use
1858 * helper function so that radeon_device_init pretty much
1859 * do nothing more than calling asic specific function. This
1860 * should also allow to remove a bunch of callback function
1861 * like vram_info.
1862 */
1863int cayman_init(struct radeon_device *rdev)
1864{
e32eb50d 1865 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
755d819e
AD		 1866 int r;
1867
755d819e
AD		 1868 /* Read BIOS */
1869 if (!radeon_get_bios(rdev)) {
1870 if (ASIC_IS_AVIVO(rdev))
1871 return -EINVAL;
1872 }
1873 /* Must be an ATOMBIOS */
1874 if (!rdev->is_atom_bios) {
1875 dev_err(rdev->dev, "Expecting atombios for cayman GPU\n");
1876 return -EINVAL;
1877 }
1878 r = radeon_atombios_init(rdev);
1879 if (r)
1880 return r;
1881
1882 /* Post card if necessary */
1883 if (!radeon_card_posted(rdev)) {
1884 if (!rdev->bios) {
1885 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
1886 return -EINVAL;
1887 }
1888 DRM_INFO("GPU not posted. posting now...\n");
1889 atom_asic_init(rdev->mode_info.atom_context);
1890 }
1891 /* Initialize scratch registers */
1892 r600_scratch_init(rdev);
1893 /* Initialize surface registers */
1894 radeon_surface_init(rdev);
1895 /* Initialize clocks */
1896 radeon_get_clock_info(rdev->ddev);
1897 /* Fence driver */
30eb77f4 1898 r = radeon_fence_driver_init(rdev);
755d819e
AD		 1899 if (r)
1900 return r;
1901 /* initialize memory controller */
1902 r = evergreen_mc_init(rdev);
1903 if (r)
1904 return r;
1905 /* Memory manager */
1906 r = radeon_bo_init(rdev);
1907 if (r)
1908 return r;
1909
1910 r = radeon_irq_kms_init(rdev);
1911 if (r)
1912 return r;
1913
e32eb50d
CK		 1914 ring->ring_obj = NULL;
1915 r600_ring_init(rdev, ring, 1024 * 1024);
755d819e 1916
f60cbd11
AD		 1917 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
1918 ring->ring_obj = NULL;
1919 r600_ring_init(rdev, ring, 64 * 1024);
1920
1921 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
1922 ring->ring_obj = NULL;
1923 r600_ring_init(rdev, ring, 64 * 1024);
1924
f2ba57b5
CK		 1925 r = radeon_uvd_init(rdev);
1926 if (!r) {
1927 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
1928 ring->ring_obj = NULL;
1929 r600_ring_init(rdev, ring, 4096);
1930 }
1931
755d819e
AD		 1932 rdev->ih.ring_obj = NULL;
1933 r600_ih_ring_init(rdev, 64 * 1024);
1934
1935 r = r600_pcie_gart_init(rdev);
1936 if (r)
1937 return r;
1938
1939 rdev->accel_working = true;
1940 r = cayman_startup(rdev);
1941 if (r) {
1942 dev_err(rdev->dev, "disabling GPU acceleration\n");
1943 cayman_cp_fini(rdev);
f60cbd11 1944 cayman_dma_fini(rdev);
755d819e 1945 r600_irq_fini(rdev);
c420c745
AD		 1946 if (rdev->flags & RADEON_IS_IGP)
1947 si_rlc_fini(rdev);
755d819e 1948 radeon_wb_fini(rdev);
2898c348 1949 radeon_ib_pool_fini(rdev);
721604a1 1950 radeon_vm_manager_fini(rdev);
755d819e
AD		 1951 radeon_irq_kms_fini(rdev);
1952 cayman_pcie_gart_fini(rdev);
1953 rdev->accel_working = false;
1954 }
755d819e
AD		 1955
1956 /* Don't start up if the MC ucode is missing.
1957 * The default clocks and voltages before the MC ucode
1958 * is loaded are not suffient for advanced operations.
c420c745
AD		 1959 *
1960 * We can skip this check for TN, because there is no MC
1961 * ucode.
755d819e 1962 */
c420c745 1963 if (!rdev->mc_fw && !(rdev->flags & RADEON_IS_IGP)) {
755d819e
AD		 1964 DRM_ERROR("radeon: MC ucode required for NI+.\n");
1965 return -EINVAL;
1966 }
1967
1968 return 0;
1969}
1970
1971void cayman_fini(struct radeon_device *rdev)
1972{
fb3d9e97 1973 r600_blit_fini(rdev);
755d819e 1974 cayman_cp_fini(rdev);
f60cbd11 1975 cayman_dma_fini(rdev);
755d819e 1976 r600_irq_fini(rdev);
c420c745
AD		 1977 if (rdev->flags & RADEON_IS_IGP)
1978 si_rlc_fini(rdev);
755d819e 1979 radeon_wb_fini(rdev);
721604a1 1980 radeon_vm_manager_fini(rdev);
2898c348 1981 radeon_ib_pool_fini(rdev);
755d819e 1982 radeon_irq_kms_fini(rdev);
f2ba57b5 1983 radeon_uvd_fini(rdev);
755d819e 1984 cayman_pcie_gart_fini(rdev);
16cdf04d 1985 r600_vram_scratch_fini(rdev);
755d819e
AD		 1986 radeon_gem_fini(rdev);
1987 radeon_fence_driver_fini(rdev);
1988 radeon_bo_fini(rdev);
1989 radeon_atombios_fini(rdev);
1990 kfree(rdev->bios);
1991 rdev->bios = NULL;
1992}
1993
721604a1
JG		 1994/*
1995 * vm
1996 */
1997int cayman_vm_init(struct radeon_device *rdev)
1998{
1999 /* number of VMs */
2000 rdev->vm_manager.nvm = 8;
2001 /* base offset of vram pages */
e71270fd
AD		 2002 if (rdev->flags & RADEON_IS_IGP) {
2003 u64 tmp = RREG32(FUS_MC_VM_FB_OFFSET);
2004 tmp <<= 22;
2005 rdev->vm_manager.vram_base_offset = tmp;
2006 } else
2007 rdev->vm_manager.vram_base_offset = 0;
721604a1
JG		 2008 return 0;
2009}
2010
2011void cayman_vm_fini(struct radeon_device *rdev)
2012{
2013}
2014
dce34bfd 2015#define R600_ENTRY_VALID (1 << 0)
721604a1
JG		 2016#define R600_PTE_SYSTEM (1 << 1)
2017#define R600_PTE_SNOOPED (1 << 2)
2018#define R600_PTE_READABLE (1 << 5)
2019#define R600_PTE_WRITEABLE (1 << 6)
2020
089a786e 2021uint32_t cayman_vm_page_flags(struct radeon_device *rdev, uint32_t flags)
721604a1
JG		 2022{
2023 uint32_t r600_flags = 0;
dce34bfd 2024 r600_flags |= (flags & RADEON_VM_PAGE_VALID) ? R600_ENTRY_VALID : 0;
721604a1
JG		 2025 r600_flags |= (flags & RADEON_VM_PAGE_READABLE) ? R600_PTE_READABLE : 0;
2026 r600_flags |= (flags & RADEON_VM_PAGE_WRITEABLE) ? R600_PTE_WRITEABLE : 0;
2027 if (flags & RADEON_VM_PAGE_SYSTEM) {
2028 r600_flags |= R600_PTE_SYSTEM;
2029 r600_flags |= (flags & RADEON_VM_PAGE_SNOOPED) ? R600_PTE_SNOOPED : 0;
2030 }
2031 return r600_flags;
2032}
2033
7a083293
AD		 2034/**
2035 * cayman_vm_set_page - update the page tables using the CP
2036 *
2037 * @rdev: radeon_device pointer
43f1214a 2038 * @ib: indirect buffer to fill with commands
dce34bfd
CK		 2039 * @pe: addr of the page entry
2040 * @addr: dst addr to write into pe
2041 * @count: number of page entries to update
2042 * @incr: increase next addr by incr bytes
2043 * @flags: access flags
7a083293 2044 *
43f1214a 2045 * Update the page tables using the CP (cayman/TN).
7a083293 2046 */
43f1214a
AD		 2047void cayman_vm_set_page(struct radeon_device *rdev,
2048 struct radeon_ib *ib,
2049 uint64_t pe,
dce34bfd
CK		 2050 uint64_t addr, unsigned count,
2051 uint32_t incr, uint32_t flags)
721604a1 2052{
dce34bfd 2053 uint32_t r600_flags = cayman_vm_page_flags(rdev, flags);
3b6b59b6
AD		 2054 uint64_t value;
2055 unsigned ndw;
2056
2057 if (rdev->asic->vm.pt_ring_index == RADEON_RING_TYPE_GFX_INDEX) {
2058 while (count) {
2059 ndw = 1 + count * 2;
2060 if (ndw > 0x3FFF)
2061 ndw = 0x3FFF;
2062
43f1214a
AD		 2063 ib->ptr[ib->length_dw++] = PACKET3(PACKET3_ME_WRITE, ndw);
2064 ib->ptr[ib->length_dw++] = pe;
2065 ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff;
3b6b59b6
AD		 2066 for (; ndw > 1; ndw -= 2, --count, pe += 8) {
2067 if (flags & RADEON_VM_PAGE_SYSTEM) {
2068 value = radeon_vm_map_gart(rdev, addr);
2069 value &= 0xFFFFFFFFFFFFF000ULL;
2070 } else if (flags & RADEON_VM_PAGE_VALID) {
2071 value = addr;
2072 } else {
2073 value = 0;
2074 }
f9fdffa5 2075 addr += incr;
3b6b59b6 2076 value |= r600_flags;
43f1214a
AD		 2077 ib->ptr[ib->length_dw++] = value;
2078 ib->ptr[ib->length_dw++] = upper_32_bits(value);
3b6b59b6
AD		 2079 }
2080 }
2081 } else {
2082 while (count) {
2083 ndw = count * 2;
2084 if (ndw > 0xFFFFE)
2085 ndw = 0xFFFFE;
2086
2087 /* for non-physically contiguous pages (system) */
43f1214a
AD		 2088 ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_WRITE, 0, 0, ndw);
2089 ib->ptr[ib->length_dw++] = pe;
2090 ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff;
3b6b59b6
AD		 2091 for (; ndw > 0; ndw -= 2, --count, pe += 8) {
2092 if (flags & RADEON_VM_PAGE_SYSTEM) {
2093 value = radeon_vm_map_gart(rdev, addr);
2094 value &= 0xFFFFFFFFFFFFF000ULL;
2095 } else if (flags & RADEON_VM_PAGE_VALID) {
2096 value = addr;
2097 } else {
2098 value = 0;
2099 }
f9fdffa5 2100 addr += incr;
3b6b59b6 2101 value |= r600_flags;
43f1214a
AD		 2102 ib->ptr[ib->length_dw++] = value;
2103 ib->ptr[ib->length_dw++] = upper_32_bits(value);
f9fdffa5 2104 }
f9fdffa5 2105 }
43f1214a
AD		 2106 while (ib->length_dw & 0x7)
2107 ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0);
2a6f1abb 2108 }
721604a1 2109}
9b40e5d8 2110
7a083293
AD		 2111/**
2112 * cayman_vm_flush - vm flush using the CP
2113 *
2114 * @rdev: radeon_device pointer
2115 *
2116 * Update the page table base and flush the VM TLB
2117 * using the CP (cayman-si).
2118 */
498522b4 2119void cayman_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm)
721604a1 2120{
498522b4 2121 struct radeon_ring *ring = &rdev->ring[ridx];
9b40e5d8 2122
ee60e29f 2123 if (vm == NULL)
9b40e5d8
CK		 2124 return;
2125
ee60e29f 2126 radeon_ring_write(ring, PACKET0(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2), 0));
fa87e62d 2127 radeon_ring_write(ring, vm->pd_gpu_addr >> 12);
ee60e29f 2128
9b40e5d8
CK		 2129 /* flush hdp cache */
2130 radeon_ring_write(ring, PACKET0(HDP_MEM_COHERENCY_FLUSH_CNTL, 0));
2131 radeon_ring_write(ring, 0x1);
2132
2133 /* bits 0-7 are the VM contexts0-7 */
2134 radeon_ring_write(ring, PACKET0(VM_INVALIDATE_REQUEST, 0));
498522b4 2135 radeon_ring_write(ring, 1 << vm->id);
58f8cf56
CK		 2136
2137 /* sync PFP to ME, otherwise we might get invalid PFP reads */
2138 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
2139 radeon_ring_write(ring, 0x0);
721604a1 2140}
f60cbd11
AD		 2141
2142void cayman_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm)
2143{
2144 struct radeon_ring *ring = &rdev->ring[ridx];
2145
2146 if (vm == NULL)
2147 return;
2148
2149 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0));
2150 radeon_ring_write(ring, (0xf << 16) | ((VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2)) >> 2));
2151 radeon_ring_write(ring, vm->pd_gpu_addr >> 12);
2152
2153 /* flush hdp cache */
2154 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0));
2155 radeon_ring_write(ring, (0xf << 16) | (HDP_MEM_COHERENCY_FLUSH_CNTL >> 2));
2156 radeon_ring_write(ring, 1);
2157
2158 /* bits 0-7 are the VM contexts0-7 */
2159 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0));
2160 radeon_ring_write(ring, (0xf << 16) | (VM_INVALIDATE_REQUEST >> 2));
2161 radeon_ring_write(ring, 1 << vm->id);
2162}
2163
Linux kernel - Deliverables
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