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drm/radeon: rework fallback handling v2
[deliverable/linux.git] / drivers / gpu / drm / radeon / ni.c
CommitLineData
0af62b01
AD		 1/*
2 * Copyright 2010 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24#include <linux/firmware.h>
25#include <linux/platform_device.h>
26#include <linux/slab.h>
e0cd3608 27#include <linux/module.h>
760285e7 28#include <drm/drmP.h>
0af62b01
AD		 29#include "radeon.h"
30#include "radeon_asic.h"
760285e7 31#include <drm/radeon_drm.h>
0af62b01
AD		 32#include "nid.h"
33#include "atom.h"
34#include "ni_reg.h"
0c88a02e 35#include "cayman_blit_shaders.h"
0af62b01 36
168757ea 37extern bool evergreen_is_display_hung(struct radeon_device *rdev);
187e3593 38extern void evergreen_print_gpu_status_regs(struct radeon_device *rdev);
b9952a8a
AD		 39extern void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save);
40extern void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save);
41extern int evergreen_mc_wait_for_idle(struct radeon_device *rdev);
755d819e
AD		 42extern void evergreen_mc_program(struct radeon_device *rdev);
43extern void evergreen_irq_suspend(struct radeon_device *rdev);
44extern int evergreen_mc_init(struct radeon_device *rdev);
d054ac16 45extern void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev);
b07759bf 46extern void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
c420c745
AD		 47extern void si_rlc_fini(struct radeon_device *rdev);
48extern int si_rlc_init(struct radeon_device *rdev);
b9952a8a 49
0af62b01
AD		 50#define EVERGREEN_PFP_UCODE_SIZE 1120
51#define EVERGREEN_PM4_UCODE_SIZE 1376
52#define EVERGREEN_RLC_UCODE_SIZE 768
53#define BTC_MC_UCODE_SIZE 6024
54
9b8253ce
AD		 55#define CAYMAN_PFP_UCODE_SIZE 2176
56#define CAYMAN_PM4_UCODE_SIZE 2176
57#define CAYMAN_RLC_UCODE_SIZE 1024
58#define CAYMAN_MC_UCODE_SIZE 6037
59
c420c745
AD		 60#define ARUBA_RLC_UCODE_SIZE 1536
61
0af62b01
AD		 62/* Firmware Names */
63MODULE_FIRMWARE("radeon/BARTS_pfp.bin");
64MODULE_FIRMWARE("radeon/BARTS_me.bin");
65MODULE_FIRMWARE("radeon/BARTS_mc.bin");
66MODULE_FIRMWARE("radeon/BTC_rlc.bin");
67MODULE_FIRMWARE("radeon/TURKS_pfp.bin");
68MODULE_FIRMWARE("radeon/TURKS_me.bin");
69MODULE_FIRMWARE("radeon/TURKS_mc.bin");
70MODULE_FIRMWARE("radeon/CAICOS_pfp.bin");
71MODULE_FIRMWARE("radeon/CAICOS_me.bin");
72MODULE_FIRMWARE("radeon/CAICOS_mc.bin");
9b8253ce
AD		 73MODULE_FIRMWARE("radeon/CAYMAN_pfp.bin");
74MODULE_FIRMWARE("radeon/CAYMAN_me.bin");
75MODULE_FIRMWARE("radeon/CAYMAN_mc.bin");
76MODULE_FIRMWARE("radeon/CAYMAN_rlc.bin");
c420c745
AD		 77MODULE_FIRMWARE("radeon/ARUBA_pfp.bin");
78MODULE_FIRMWARE("radeon/ARUBA_me.bin");
79MODULE_FIRMWARE("radeon/ARUBA_rlc.bin");
0af62b01
AD		 80
81#define BTC_IO_MC_REGS_SIZE 29
82
83static const u32 barts_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
84 {0x00000077, 0xff010100},
85 {0x00000078, 0x00000000},
86 {0x00000079, 0x00001434},
87 {0x0000007a, 0xcc08ec08},
88 {0x0000007b, 0x00040000},
89 {0x0000007c, 0x000080c0},
90 {0x0000007d, 0x09000000},
91 {0x0000007e, 0x00210404},
92 {0x00000081, 0x08a8e800},
93 {0x00000082, 0x00030444},
94 {0x00000083, 0x00000000},
95 {0x00000085, 0x00000001},
96 {0x00000086, 0x00000002},
97 {0x00000087, 0x48490000},
98 {0x00000088, 0x20244647},
99 {0x00000089, 0x00000005},
100 {0x0000008b, 0x66030000},
101 {0x0000008c, 0x00006603},
102 {0x0000008d, 0x00000100},
103 {0x0000008f, 0x00001c0a},
104 {0x00000090, 0xff000001},
105 {0x00000094, 0x00101101},
106 {0x00000095, 0x00000fff},
107 {0x00000096, 0x00116fff},
108 {0x00000097, 0x60010000},
109 {0x00000098, 0x10010000},
110 {0x00000099, 0x00006000},
111 {0x0000009a, 0x00001000},
112 {0x0000009f, 0x00946a00}
113};
114
115static const u32 turks_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
116 {0x00000077, 0xff010100},
117 {0x00000078, 0x00000000},
118 {0x00000079, 0x00001434},
119 {0x0000007a, 0xcc08ec08},
120 {0x0000007b, 0x00040000},
121 {0x0000007c, 0x000080c0},
122 {0x0000007d, 0x09000000},
123 {0x0000007e, 0x00210404},
124 {0x00000081, 0x08a8e800},
125 {0x00000082, 0x00030444},
126 {0x00000083, 0x00000000},
127 {0x00000085, 0x00000001},
128 {0x00000086, 0x00000002},
129 {0x00000087, 0x48490000},
130 {0x00000088, 0x20244647},
131 {0x00000089, 0x00000005},
132 {0x0000008b, 0x66030000},
133 {0x0000008c, 0x00006603},
134 {0x0000008d, 0x00000100},
135 {0x0000008f, 0x00001c0a},
136 {0x00000090, 0xff000001},
137 {0x00000094, 0x00101101},
138 {0x00000095, 0x00000fff},
139 {0x00000096, 0x00116fff},
140 {0x00000097, 0x60010000},
141 {0x00000098, 0x10010000},
142 {0x00000099, 0x00006000},
143 {0x0000009a, 0x00001000},
144 {0x0000009f, 0x00936a00}
145};
146
147static const u32 caicos_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
148 {0x00000077, 0xff010100},
149 {0x00000078, 0x00000000},
150 {0x00000079, 0x00001434},
151 {0x0000007a, 0xcc08ec08},
152 {0x0000007b, 0x00040000},
153 {0x0000007c, 0x000080c0},
154 {0x0000007d, 0x09000000},
155 {0x0000007e, 0x00210404},
156 {0x00000081, 0x08a8e800},
157 {0x00000082, 0x00030444},
158 {0x00000083, 0x00000000},
159 {0x00000085, 0x00000001},
160 {0x00000086, 0x00000002},
161 {0x00000087, 0x48490000},
162 {0x00000088, 0x20244647},
163 {0x00000089, 0x00000005},
164 {0x0000008b, 0x66030000},
165 {0x0000008c, 0x00006603},
166 {0x0000008d, 0x00000100},
167 {0x0000008f, 0x00001c0a},
168 {0x00000090, 0xff000001},
169 {0x00000094, 0x00101101},
170 {0x00000095, 0x00000fff},
171 {0x00000096, 0x00116fff},
172 {0x00000097, 0x60010000},
173 {0x00000098, 0x10010000},
174 {0x00000099, 0x00006000},
175 {0x0000009a, 0x00001000},
176 {0x0000009f, 0x00916a00}
177};
178
9b8253ce
AD		 179static const u32 cayman_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
180 {0x00000077, 0xff010100},
181 {0x00000078, 0x00000000},
182 {0x00000079, 0x00001434},
183 {0x0000007a, 0xcc08ec08},
184 {0x0000007b, 0x00040000},
185 {0x0000007c, 0x000080c0},
186 {0x0000007d, 0x09000000},
187 {0x0000007e, 0x00210404},
188 {0x00000081, 0x08a8e800},
189 {0x00000082, 0x00030444},
190 {0x00000083, 0x00000000},
191 {0x00000085, 0x00000001},
192 {0x00000086, 0x00000002},
193 {0x00000087, 0x48490000},
194 {0x00000088, 0x20244647},
195 {0x00000089, 0x00000005},
196 {0x0000008b, 0x66030000},
197 {0x0000008c, 0x00006603},
198 {0x0000008d, 0x00000100},
199 {0x0000008f, 0x00001c0a},
200 {0x00000090, 0xff000001},
201 {0x00000094, 0x00101101},
202 {0x00000095, 0x00000fff},
203 {0x00000096, 0x00116fff},
204 {0x00000097, 0x60010000},
205 {0x00000098, 0x10010000},
206 {0x00000099, 0x00006000},
207 {0x0000009a, 0x00001000},
208 {0x0000009f, 0x00976b00}
209};
210
755d819e 211int ni_mc_load_microcode(struct radeon_device *rdev)
0af62b01
AD		 212{
213 const __be32 *fw_data;
214 u32 mem_type, running, blackout = 0;
215 u32 *io_mc_regs;
9b8253ce 216 int i, ucode_size, regs_size;
0af62b01
AD		 217
218 if (!rdev->mc_fw)
219 return -EINVAL;
220
221 switch (rdev->family) {
222 case CHIP_BARTS:
223 io_mc_regs = (u32 *)&barts_io_mc_regs;
9b8253ce
AD		 224 ucode_size = BTC_MC_UCODE_SIZE;
225 regs_size = BTC_IO_MC_REGS_SIZE;
0af62b01
AD		 226 break;
227 case CHIP_TURKS:
228 io_mc_regs = (u32 *)&turks_io_mc_regs;
9b8253ce
AD		 229 ucode_size = BTC_MC_UCODE_SIZE;
230 regs_size = BTC_IO_MC_REGS_SIZE;
0af62b01
AD		 231 break;
232 case CHIP_CAICOS:
233 default:
234 io_mc_regs = (u32 *)&caicos_io_mc_regs;
9b8253ce
AD		 235 ucode_size = BTC_MC_UCODE_SIZE;
236 regs_size = BTC_IO_MC_REGS_SIZE;
237 break;
238 case CHIP_CAYMAN:
239 io_mc_regs = (u32 *)&cayman_io_mc_regs;
240 ucode_size = CAYMAN_MC_UCODE_SIZE;
241 regs_size = BTC_IO_MC_REGS_SIZE;
0af62b01
AD		 242 break;
243 }
244
245 mem_type = (RREG32(MC_SEQ_MISC0) & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT;
246 running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK;
247
248 if ((mem_type == MC_SEQ_MISC0_GDDR5_VALUE) && (running == 0)) {
249 if (running) {
250 blackout = RREG32(MC_SHARED_BLACKOUT_CNTL);
251 WREG32(MC_SHARED_BLACKOUT_CNTL, 1);
252 }
253
254 /* reset the engine and set to writable */
255 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
256 WREG32(MC_SEQ_SUP_CNTL, 0x00000010);
257
258 /* load mc io regs */
9b8253ce 259 for (i = 0; i < regs_size; i++) {
0af62b01
AD		 260 WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]);
261 WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]);
262 }
263 /* load the MC ucode */
264 fw_data = (const __be32 *)rdev->mc_fw->data;
9b8253ce 265 for (i = 0; i < ucode_size; i++)
0af62b01
AD		 266 WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++));
267
268 /* put the engine back into the active state */
269 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
270 WREG32(MC_SEQ_SUP_CNTL, 0x00000004);
271 WREG32(MC_SEQ_SUP_CNTL, 0x00000001);
272
273 /* wait for training to complete */
0e2c978e
AD		 274 for (i = 0; i < rdev->usec_timeout; i++) {
275 if (RREG32(MC_IO_PAD_CNTL_D0) & MEM_FALL_OUT_CMD)
276 break;
277 udelay(1);
278 }
0af62b01
AD		 279
280 if (running)
281 WREG32(MC_SHARED_BLACKOUT_CNTL, blackout);
282 }
283
284 return 0;
285}
286
287int ni_init_microcode(struct radeon_device *rdev)
288{
289 struct platform_device *pdev;
290 const char *chip_name;
291 const char *rlc_chip_name;
292 size_t pfp_req_size, me_req_size, rlc_req_size, mc_req_size;
293 char fw_name[30];
294 int err;
295
296 DRM_DEBUG("\n");
297
298 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
299 err = IS_ERR(pdev);
300 if (err) {
301 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
302 return -EINVAL;
303 }
304
305 switch (rdev->family) {
306 case CHIP_BARTS:
307 chip_name = "BARTS";
308 rlc_chip_name = "BTC";
9b8253ce
AD		 309 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
310 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
311 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
312 mc_req_size = BTC_MC_UCODE_SIZE * 4;
0af62b01
AD		 313 break;
314 case CHIP_TURKS:
315 chip_name = "TURKS";
316 rlc_chip_name = "BTC";
9b8253ce
AD		 317 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
318 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
319 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
320 mc_req_size = BTC_MC_UCODE_SIZE * 4;
0af62b01
AD		 321 break;
322 case CHIP_CAICOS:
323 chip_name = "CAICOS";
324 rlc_chip_name = "BTC";
9b8253ce
AD		 325 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
326 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
327 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
328 mc_req_size = BTC_MC_UCODE_SIZE * 4;
329 break;
330 case CHIP_CAYMAN:
331 chip_name = "CAYMAN";
332 rlc_chip_name = "CAYMAN";
333 pfp_req_size = CAYMAN_PFP_UCODE_SIZE * 4;
334 me_req_size = CAYMAN_PM4_UCODE_SIZE * 4;
335 rlc_req_size = CAYMAN_RLC_UCODE_SIZE * 4;
336 mc_req_size = CAYMAN_MC_UCODE_SIZE * 4;
0af62b01 337 break;
c420c745
AD		 338 case CHIP_ARUBA:
339 chip_name = "ARUBA";
340 rlc_chip_name = "ARUBA";
341 /* pfp/me same size as CAYMAN */
342 pfp_req_size = CAYMAN_PFP_UCODE_SIZE * 4;
343 me_req_size = CAYMAN_PM4_UCODE_SIZE * 4;
344 rlc_req_size = ARUBA_RLC_UCODE_SIZE * 4;
345 mc_req_size = 0;
346 break;
0af62b01
AD		 347 default: BUG();
348 }
349
0af62b01
AD		 350 DRM_INFO("Loading %s Microcode\n", chip_name);
351
352 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
353 err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
354 if (err)
355 goto out;
356 if (rdev->pfp_fw->size != pfp_req_size) {
357 printk(KERN_ERR
358 "ni_cp: Bogus length %zu in firmware \"%s\"\n",
359 rdev->pfp_fw->size, fw_name);
360 err = -EINVAL;
361 goto out;
362 }
363
364 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
365 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
366 if (err)
367 goto out;
368 if (rdev->me_fw->size != me_req_size) {
369 printk(KERN_ERR
370 "ni_cp: Bogus length %zu in firmware \"%s\"\n",
371 rdev->me_fw->size, fw_name);
372 err = -EINVAL;
373 }
374
375 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
376 err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev);
377 if (err)
378 goto out;
379 if (rdev->rlc_fw->size != rlc_req_size) {
380 printk(KERN_ERR
381 "ni_rlc: Bogus length %zu in firmware \"%s\"\n",
382 rdev->rlc_fw->size, fw_name);
383 err = -EINVAL;
384 }
385
c420c745
AD		 386 /* no MC ucode on TN */
387 if (!(rdev->flags & RADEON_IS_IGP)) {
388 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
389 err = request_firmware(&rdev->mc_fw, fw_name, &pdev->dev);
390 if (err)
391 goto out;
392 if (rdev->mc_fw->size != mc_req_size) {
393 printk(KERN_ERR
394 "ni_mc: Bogus length %zu in firmware \"%s\"\n",
395 rdev->mc_fw->size, fw_name);
396 err = -EINVAL;
397 }
0af62b01
AD		 398 }
399out:
400 platform_device_unregister(pdev);
401
402 if (err) {
403 if (err != -EINVAL)
404 printk(KERN_ERR
405 "ni_cp: Failed to load firmware \"%s\"\n",
406 fw_name);
407 release_firmware(rdev->pfp_fw);
408 rdev->pfp_fw = NULL;
409 release_firmware(rdev->me_fw);
410 rdev->me_fw = NULL;
411 release_firmware(rdev->rlc_fw);
412 rdev->rlc_fw = NULL;
413 release_firmware(rdev->mc_fw);
414 rdev->mc_fw = NULL;
415 }
416 return err;
417}
418
fecf1d07
AD		 419/*
420 * Core functions
421 */
fecf1d07
AD		 422static void cayman_gpu_init(struct radeon_device *rdev)
423{
fecf1d07
AD		 424 u32 gb_addr_config = 0;
425 u32 mc_shared_chmap, mc_arb_ramcfg;
fecf1d07
AD		 426 u32 cgts_tcc_disable;
427 u32 sx_debug_1;
428 u32 smx_dc_ctl0;
fecf1d07
AD		 429 u32 cgts_sm_ctrl_reg;
430 u32 hdp_host_path_cntl;
431 u32 tmp;
416a2bd2 432 u32 disabled_rb_mask;
fecf1d07
AD		 433 int i, j;
434
435 switch (rdev->family) {
436 case CHIP_CAYMAN:
fecf1d07
AD		 437 rdev->config.cayman.max_shader_engines = 2;
438 rdev->config.cayman.max_pipes_per_simd = 4;
439 rdev->config.cayman.max_tile_pipes = 8;
440 rdev->config.cayman.max_simds_per_se = 12;
441 rdev->config.cayman.max_backends_per_se = 4;
442 rdev->config.cayman.max_texture_channel_caches = 8;
443 rdev->config.cayman.max_gprs = 256;
444 rdev->config.cayman.max_threads = 256;
445 rdev->config.cayman.max_gs_threads = 32;
446 rdev->config.cayman.max_stack_entries = 512;
447 rdev->config.cayman.sx_num_of_sets = 8;
448 rdev->config.cayman.sx_max_export_size = 256;
449 rdev->config.cayman.sx_max_export_pos_size = 64;
450 rdev->config.cayman.sx_max_export_smx_size = 192;
451 rdev->config.cayman.max_hw_contexts = 8;
452 rdev->config.cayman.sq_num_cf_insts = 2;
453
454 rdev->config.cayman.sc_prim_fifo_size = 0x100;
455 rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30;
456 rdev->config.cayman.sc_earlyz_tile_fifo_size = 0x130;
416a2bd2 457 gb_addr_config = CAYMAN_GB_ADDR_CONFIG_GOLDEN;
fecf1d07 458 break;
7b76e479
AD		 459 case CHIP_ARUBA:
460 default:
461 rdev->config.cayman.max_shader_engines = 1;
462 rdev->config.cayman.max_pipes_per_simd = 4;
463 rdev->config.cayman.max_tile_pipes = 2;
464 if ((rdev->pdev->device == 0x9900) ||
d430f7db
AD		 465 (rdev->pdev->device == 0x9901) ||
466 (rdev->pdev->device == 0x9905) ||
467 (rdev->pdev->device == 0x9906) ||
468 (rdev->pdev->device == 0x9907) ||
469 (rdev->pdev->device == 0x9908) ||
470 (rdev->pdev->device == 0x9909) ||
e4d17063
AD		 471 (rdev->pdev->device == 0x990B) ||
472 (rdev->pdev->device == 0x990C) ||
473 (rdev->pdev->device == 0x990F) ||
d430f7db 474 (rdev->pdev->device == 0x9910) ||
e4d17063
AD		 475 (rdev->pdev->device == 0x9917) ||
476 (rdev->pdev->device == 0x9999)) {
7b76e479
AD		 477 rdev->config.cayman.max_simds_per_se = 6;
478 rdev->config.cayman.max_backends_per_se = 2;
479 } else if ((rdev->pdev->device == 0x9903) ||
d430f7db
AD		 480 (rdev->pdev->device == 0x9904) ||
481 (rdev->pdev->device == 0x990A) ||
e4d17063
AD		 482 (rdev->pdev->device == 0x990D) ||
483 (rdev->pdev->device == 0x990E) ||
d430f7db
AD		 484 (rdev->pdev->device == 0x9913) ||
485 (rdev->pdev->device == 0x9918)) {
7b76e479
AD		 486 rdev->config.cayman.max_simds_per_se = 4;
487 rdev->config.cayman.max_backends_per_se = 2;
d430f7db
AD		 488 } else if ((rdev->pdev->device == 0x9919) ||
489 (rdev->pdev->device == 0x9990) ||
490 (rdev->pdev->device == 0x9991) ||
491 (rdev->pdev->device == 0x9994) ||
e4d17063
AD		 492 (rdev->pdev->device == 0x9995) ||
493 (rdev->pdev->device == 0x9996) ||
494 (rdev->pdev->device == 0x999A) ||
d430f7db 495 (rdev->pdev->device == 0x99A0)) {
7b76e479
AD		 496 rdev->config.cayman.max_simds_per_se = 3;
497 rdev->config.cayman.max_backends_per_se = 1;
498 } else {
499 rdev->config.cayman.max_simds_per_se = 2;
500 rdev->config.cayman.max_backends_per_se = 1;
501 }
502 rdev->config.cayman.max_texture_channel_caches = 2;
503 rdev->config.cayman.max_gprs = 256;
504 rdev->config.cayman.max_threads = 256;
505 rdev->config.cayman.max_gs_threads = 32;
506 rdev->config.cayman.max_stack_entries = 512;
507 rdev->config.cayman.sx_num_of_sets = 8;
508 rdev->config.cayman.sx_max_export_size = 256;
509 rdev->config.cayman.sx_max_export_pos_size = 64;
510 rdev->config.cayman.sx_max_export_smx_size = 192;
511 rdev->config.cayman.max_hw_contexts = 8;
512 rdev->config.cayman.sq_num_cf_insts = 2;
513
514 rdev->config.cayman.sc_prim_fifo_size = 0x40;
515 rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30;
516 rdev->config.cayman.sc_earlyz_tile_fifo_size = 0x130;
416a2bd2 517 gb_addr_config = ARUBA_GB_ADDR_CONFIG_GOLDEN;
7b76e479 518 break;
fecf1d07
AD		 519 }
520
521 /* Initialize HDP */
522 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
523 WREG32((0x2c14 + j), 0x00000000);
524 WREG32((0x2c18 + j), 0x00000000);
525 WREG32((0x2c1c + j), 0x00000000);
526 WREG32((0x2c20 + j), 0x00000000);
527 WREG32((0x2c24 + j), 0x00000000);
528 }
529
530 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
531
d054ac16
AD		 532 evergreen_fix_pci_max_read_req_size(rdev);
533
fecf1d07
AD		 534 mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
535 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
536
fecf1d07
AD		 537 tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT;
538 rdev->config.cayman.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
539 if (rdev->config.cayman.mem_row_size_in_kb > 4)
540 rdev->config.cayman.mem_row_size_in_kb = 4;
541 /* XXX use MC settings? */
542 rdev->config.cayman.shader_engine_tile_size = 32;
543 rdev->config.cayman.num_gpus = 1;
544 rdev->config.cayman.multi_gpu_tile_size = 64;
545
fecf1d07
AD		 546 tmp = (gb_addr_config & NUM_PIPES_MASK) >> NUM_PIPES_SHIFT;
547 rdev->config.cayman.num_tile_pipes = (1 << tmp);
548 tmp = (gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT;
549 rdev->config.cayman.mem_max_burst_length_bytes = (tmp + 1) * 256;
550 tmp = (gb_addr_config & NUM_SHADER_ENGINES_MASK) >> NUM_SHADER_ENGINES_SHIFT;
551 rdev->config.cayman.num_shader_engines = tmp + 1;
552 tmp = (gb_addr_config & NUM_GPUS_MASK) >> NUM_GPUS_SHIFT;
553 rdev->config.cayman.num_gpus = tmp + 1;
554 tmp = (gb_addr_config & MULTI_GPU_TILE_SIZE_MASK) >> MULTI_GPU_TILE_SIZE_SHIFT;
555 rdev->config.cayman.multi_gpu_tile_size = 1 << tmp;
556 tmp = (gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT;
557 rdev->config.cayman.mem_row_size_in_kb = 1 << tmp;
558
416a2bd2 559
fecf1d07
AD		 560 /* setup tiling info dword. gb_addr_config is not adequate since it does
561 * not have bank info, so create a custom tiling dword.
562 * bits 3:0 num_pipes
563 * bits 7:4 num_banks
564 * bits 11:8 group_size
565 * bits 15:12 row_size
566 */
567 rdev->config.cayman.tile_config = 0;
568 switch (rdev->config.cayman.num_tile_pipes) {
569 case 1:
570 default:
571 rdev->config.cayman.tile_config |= (0 << 0);
572 break;
573 case 2:
574 rdev->config.cayman.tile_config |= (1 << 0);
575 break;
576 case 4:
577 rdev->config.cayman.tile_config |= (2 << 0);
578 break;
579 case 8:
580 rdev->config.cayman.tile_config |= (3 << 0);
581 break;
582 }
7b76e479
AD		 583
584 /* num banks is 8 on all fusion asics. 0 = 4, 1 = 8, 2 = 16 */
585 if (rdev->flags & RADEON_IS_IGP)
1f73cca7 586 rdev->config.cayman.tile_config |= 1 << 4;
29d65406 587 else {
5b23c904
AD		 588 switch ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) {
589 case 0: /* four banks */
29d65406 590 rdev->config.cayman.tile_config |= 0 << 4;
5b23c904
AD		 591 break;
592 case 1: /* eight banks */
593 rdev->config.cayman.tile_config |= 1 << 4;
594 break;
595 case 2: /* sixteen banks */
596 default:
597 rdev->config.cayman.tile_config |= 2 << 4;
598 break;
599 }
29d65406 600 }
fecf1d07 601 rdev->config.cayman.tile_config |=
cde5083b 602 ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8;
fecf1d07
AD		 603 rdev->config.cayman.tile_config |=
604 ((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12;
605
416a2bd2
AD		 606 tmp = 0;
607 for (i = (rdev->config.cayman.max_shader_engines - 1); i >= 0; i--) {
608 u32 rb_disable_bitmap;
609
610 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
611 WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
612 rb_disable_bitmap = (RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000) >> 16;
613 tmp <<= 4;
614 tmp |= rb_disable_bitmap;
615 }
616 /* enabled rb are just the one not disabled :) */
617 disabled_rb_mask = tmp;
618
619 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
620 WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
621
fecf1d07
AD		 622 WREG32(GB_ADDR_CONFIG, gb_addr_config);
623 WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
7c1c7c18
AD		 624 if (ASIC_IS_DCE6(rdev))
625 WREG32(DMIF_ADDR_CALC, gb_addr_config);
fecf1d07 626 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
f60cbd11
AD		 627 WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
628 WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);
fecf1d07 629
8f612b23
AD		 630 if ((rdev->config.cayman.max_backends_per_se == 1) &&
631 (rdev->flags & RADEON_IS_IGP)) {
632 if ((disabled_rb_mask & 3) == 1) {
633 /* RB0 disabled, RB1 enabled */
634 tmp = 0x11111111;
635 } else {
636 /* RB1 disabled, RB0 enabled */
637 tmp = 0x00000000;
638 }
639 } else {
640 tmp = gb_addr_config & NUM_PIPES_MASK;
641 tmp = r6xx_remap_render_backend(rdev, tmp,
642 rdev->config.cayman.max_backends_per_se *
643 rdev->config.cayman.max_shader_engines,
644 CAYMAN_MAX_BACKENDS, disabled_rb_mask);
645 }
416a2bd2 646 WREG32(GB_BACKEND_MAP, tmp);
fecf1d07 647
416a2bd2
AD		 648 cgts_tcc_disable = 0xffff0000;
649 for (i = 0; i < rdev->config.cayman.max_texture_channel_caches; i++)
650 cgts_tcc_disable &= ~(1 << (16 + i));
fecf1d07
AD		 651 WREG32(CGTS_TCC_DISABLE, cgts_tcc_disable);
652 WREG32(CGTS_SYS_TCC_DISABLE, cgts_tcc_disable);
fecf1d07
AD		 653 WREG32(CGTS_USER_SYS_TCC_DISABLE, cgts_tcc_disable);
654 WREG32(CGTS_USER_TCC_DISABLE, cgts_tcc_disable);
655
656 /* reprogram the shader complex */
657 cgts_sm_ctrl_reg = RREG32(CGTS_SM_CTRL_REG);
658 for (i = 0; i < 16; i++)
659 WREG32(CGTS_SM_CTRL_REG, OVERRIDE);
660 WREG32(CGTS_SM_CTRL_REG, cgts_sm_ctrl_reg);
661
662 /* set HW defaults for 3D engine */
663 WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60));
664
665 sx_debug_1 = RREG32(SX_DEBUG_1);
666 sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
667 WREG32(SX_DEBUG_1, sx_debug_1);
668
669 smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
670 smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff);
285e042d 671 smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.cayman.sx_num_of_sets);
fecf1d07
AD		 672 WREG32(SMX_DC_CTL0, smx_dc_ctl0);
673
674 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4) | CRC_SIMD_ID_WADDR_DISABLE);
675
676 /* need to be explicitly zero-ed */
677 WREG32(VGT_OFFCHIP_LDS_BASE, 0);
678 WREG32(SQ_LSTMP_RING_BASE, 0);
679 WREG32(SQ_HSTMP_RING_BASE, 0);
680 WREG32(SQ_ESTMP_RING_BASE, 0);
681 WREG32(SQ_GSTMP_RING_BASE, 0);
682 WREG32(SQ_VSTMP_RING_BASE, 0);
683 WREG32(SQ_PSTMP_RING_BASE, 0);
684
685 WREG32(TA_CNTL_AUX, DISABLE_CUBE_ANISO);
686
285e042d
DA		 687 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.cayman.sx_max_export_size / 4) - 1) |
688 POSITION_BUFFER_SIZE((rdev->config.cayman.sx_max_export_pos_size / 4) - 1) |
689 SMX_BUFFER_SIZE((rdev->config.cayman.sx_max_export_smx_size / 4) - 1)));
fecf1d07 690
285e042d
DA		 691 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.cayman.sc_prim_fifo_size) |
692 SC_HIZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_hiz_tile_fifo_size) |
693 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_earlyz_tile_fifo_size)));
fecf1d07
AD		 694
695
696 WREG32(VGT_NUM_INSTANCES, 1);
697
698 WREG32(CP_PERFMON_CNTL, 0);
699
285e042d 700 WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.cayman.sq_num_cf_insts) |
fecf1d07
AD		 701 FETCH_FIFO_HIWATER(0x4) |
702 DONE_FIFO_HIWATER(0xe0) |
703 ALU_UPDATE_FIFO_HIWATER(0x8)));
704
705 WREG32(SQ_GPR_RESOURCE_MGMT_1, NUM_CLAUSE_TEMP_GPRS(4));
706 WREG32(SQ_CONFIG, (VC_ENABLE |
707 EXPORT_SRC_C |
708 GFX_PRIO(0) |
709 CS1_PRIO(0) |
710 CS2_PRIO(1)));
711 WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, DYN_GPR_ENABLE);
712
713 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
714 FORCE_EOV_MAX_REZ_CNT(255)));
715
716 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) |
717 AUTO_INVLD_EN(ES_AND_GS_AUTO));
718
719 WREG32(VGT_GS_VERTEX_REUSE, 16);
720 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
721
722 WREG32(CB_PERF_CTR0_SEL_0, 0);
723 WREG32(CB_PERF_CTR0_SEL_1, 0);
724 WREG32(CB_PERF_CTR1_SEL_0, 0);
725 WREG32(CB_PERF_CTR1_SEL_1, 0);
726 WREG32(CB_PERF_CTR2_SEL_0, 0);
727 WREG32(CB_PERF_CTR2_SEL_1, 0);
728 WREG32(CB_PERF_CTR3_SEL_0, 0);
729 WREG32(CB_PERF_CTR3_SEL_1, 0);
730
0b65f83f
DA		 731 tmp = RREG32(HDP_MISC_CNTL);
732 tmp |= HDP_FLUSH_INVALIDATE_CACHE;
733 WREG32(HDP_MISC_CNTL, tmp);
734
fecf1d07
AD		 735 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
736 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
737
738 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
739
740 udelay(50);
741}
742
fa8198ea
AD		 743/*
744 * GART
745 */
746void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev)
747{
748 /* flush hdp cache */
749 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
750
751 /* bits 0-7 are the VM contexts0-7 */
752 WREG32(VM_INVALIDATE_REQUEST, 1);
753}
754
1109ca09 755static int cayman_pcie_gart_enable(struct radeon_device *rdev)
fa8198ea 756{
721604a1 757 int i, r;
fa8198ea 758
c9a1be96 759 if (rdev->gart.robj == NULL) {
fa8198ea
AD		 760 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
761 return -EINVAL;
762 }
763 r = radeon_gart_table_vram_pin(rdev);
764 if (r)
765 return r;
766 radeon_gart_restore(rdev);
767 /* Setup TLB control */
721604a1
JG		 768 WREG32(MC_VM_MX_L1_TLB_CNTL,
769 (0xA << 7) |
770 ENABLE_L1_TLB |
fa8198ea
AD		 771 ENABLE_L1_FRAGMENT_PROCESSING |
772 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
721604a1 773 ENABLE_ADVANCED_DRIVER_MODEL |
fa8198ea
AD		 774 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
775 /* Setup L2 cache */
776 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE |
777 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
778 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
779 EFFECTIVE_L2_QUEUE_SIZE(7) |
780 CONTEXT1_IDENTITY_ACCESS_MODE(1));
781 WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE);
782 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
783 L2_CACHE_BIGK_FRAGMENT_SIZE(6));
784 /* setup context0 */
785 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
786 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
787 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
788 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
789 (u32)(rdev->dummy_page.addr >> 12));
790 WREG32(VM_CONTEXT0_CNTL2, 0);
791 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
792 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
721604a1
JG		 793
794 WREG32(0x15D4, 0);
795 WREG32(0x15D8, 0);
796 WREG32(0x15DC, 0);
797
798 /* empty context1-7 */
23d4f1f2
AD		 799 /* Assign the pt base to something valid for now; the pts used for
800 * the VMs are determined by the application and setup and assigned
801 * on the fly in the vm part of radeon_gart.c
802 */
721604a1
JG		 803 for (i = 1; i < 8; i++) {
804 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR + (i << 2), 0);
c1a7ca0d 805 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR + (i << 2), rdev->vm_manager.max_pfn);
721604a1
JG		 806 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2),
807 rdev->gart.table_addr >> 12);
808 }
809
810 /* enable context1-7 */
811 WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
812 (u32)(rdev->dummy_page.addr >> 12));
ae133a11 813 WREG32(VM_CONTEXT1_CNTL2, 4);
fa87e62d 814 WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) |
ae133a11
CK		 815 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT |
816 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT |
817 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT |
818 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT |
819 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT |
820 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT |
821 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT |
822 VALID_PROTECTION_FAULT_ENABLE_DEFAULT |
823 READ_PROTECTION_FAULT_ENABLE_INTERRUPT |
824 READ_PROTECTION_FAULT_ENABLE_DEFAULT |
825 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT |
826 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT);
fa8198ea
AD		 827
828 cayman_pcie_gart_tlb_flush(rdev);
fcf4de5a
TV		 829 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
830 (unsigned)(rdev->mc.gtt_size >> 20),
831 (unsigned long long)rdev->gart.table_addr);
fa8198ea
AD		 832 rdev->gart.ready = true;
833 return 0;
834}
835
1109ca09 836static void cayman_pcie_gart_disable(struct radeon_device *rdev)
fa8198ea 837{
fa8198ea
AD		 838 /* Disable all tables */
839 WREG32(VM_CONTEXT0_CNTL, 0);
840 WREG32(VM_CONTEXT1_CNTL, 0);
841 /* Setup TLB control */
842 WREG32(MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING |
843 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
844 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
845 /* Setup L2 cache */
846 WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
847 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
848 EFFECTIVE_L2_QUEUE_SIZE(7) |
849 CONTEXT1_IDENTITY_ACCESS_MODE(1));
850 WREG32(VM_L2_CNTL2, 0);
851 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
852 L2_CACHE_BIGK_FRAGMENT_SIZE(6));
c9a1be96 853 radeon_gart_table_vram_unpin(rdev);
fa8198ea
AD		 854}
855
1109ca09 856static void cayman_pcie_gart_fini(struct radeon_device *rdev)
fa8198ea
AD		 857{
858 cayman_pcie_gart_disable(rdev);
859 radeon_gart_table_vram_free(rdev);
860 radeon_gart_fini(rdev);
861}
862
1b37078b
AD		 863void cayman_cp_int_cntl_setup(struct radeon_device *rdev,
864 int ring, u32 cp_int_cntl)
865{
866 u32 srbm_gfx_cntl = RREG32(SRBM_GFX_CNTL) & ~3;
867
868 WREG32(SRBM_GFX_CNTL, srbm_gfx_cntl | (ring & 3));
869 WREG32(CP_INT_CNTL, cp_int_cntl);
870}
871
0c88a02e
AD		 872/*
873 * CP.
874 */
b40e7e16
AD		 875void cayman_fence_ring_emit(struct radeon_device *rdev,
876 struct radeon_fence *fence)
877{
878 struct radeon_ring *ring = &rdev->ring[fence->ring];
879 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
880
721604a1
JG		 881 /* flush read cache over gart for this vmid */
882 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
883 radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
884 radeon_ring_write(ring, 0);
b40e7e16
AD		 885 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
886 radeon_ring_write(ring, PACKET3_TC_ACTION_ENA | PACKET3_SH_ACTION_ENA);
887 radeon_ring_write(ring, 0xFFFFFFFF);
888 radeon_ring_write(ring, 0);
889 radeon_ring_write(ring, 10); /* poll interval */
890 /* EVENT_WRITE_EOP - flush caches, send int */
891 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
892 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5));
893 radeon_ring_write(ring, addr & 0xffffffff);
894 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
895 radeon_ring_write(ring, fence->seq);
896 radeon_ring_write(ring, 0);
897}
898
721604a1
JG		 899void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
900{
876dc9f3 901 struct radeon_ring *ring = &rdev->ring[ib->ring];
721604a1
JG		 902
903 /* set to DX10/11 mode */
904 radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0));
905 radeon_ring_write(ring, 1);
45df6803
CK		 906
907 if (ring->rptr_save_reg) {
908 uint32_t next_rptr = ring->wptr + 3 + 4 + 8;
909 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
910 radeon_ring_write(ring, ((ring->rptr_save_reg -
911 PACKET3_SET_CONFIG_REG_START) >> 2));
912 radeon_ring_write(ring, next_rptr);
913 }
914
721604a1
JG		 915 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
916 radeon_ring_write(ring,
917#ifdef __BIG_ENDIAN
918 (2 << 0) |
919#endif
920 (ib->gpu_addr & 0xFFFFFFFC));
921 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF);
4bf3dd92
CK		 922 radeon_ring_write(ring, ib->length_dw |
923 (ib->vm ? (ib->vm->id << 24) : 0));
721604a1
JG		 924
925 /* flush read cache over gart for this vmid */
926 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
927 radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
4bf3dd92 928 radeon_ring_write(ring, ib->vm ? ib->vm->id : 0);
721604a1
JG		 929 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
930 radeon_ring_write(ring, PACKET3_TC_ACTION_ENA | PACKET3_SH_ACTION_ENA);
931 radeon_ring_write(ring, 0xFFFFFFFF);
932 radeon_ring_write(ring, 0);
933 radeon_ring_write(ring, 10); /* poll interval */
934}
935
0c88a02e
AD		 936static void cayman_cp_enable(struct radeon_device *rdev, bool enable)
937{
938 if (enable)
939 WREG32(CP_ME_CNTL, 0);
940 else {
38f1cff0 941 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
0c88a02e
AD		 942 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
943 WREG32(SCRATCH_UMSK, 0);
f60cbd11 944 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
0c88a02e
AD		 945 }
946}
947
948static int cayman_cp_load_microcode(struct radeon_device *rdev)
949{
950 const __be32 *fw_data;
951 int i;
952
953 if (!rdev->me_fw || !rdev->pfp_fw)
954 return -EINVAL;
955
956 cayman_cp_enable(rdev, false);
957
958 fw_data = (const __be32 *)rdev->pfp_fw->data;
959 WREG32(CP_PFP_UCODE_ADDR, 0);
960 for (i = 0; i < CAYMAN_PFP_UCODE_SIZE; i++)
961 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
962 WREG32(CP_PFP_UCODE_ADDR, 0);
963
964 fw_data = (const __be32 *)rdev->me_fw->data;
965 WREG32(CP_ME_RAM_WADDR, 0);
966 for (i = 0; i < CAYMAN_PM4_UCODE_SIZE; i++)
967 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
968
969 WREG32(CP_PFP_UCODE_ADDR, 0);
970 WREG32(CP_ME_RAM_WADDR, 0);
971 WREG32(CP_ME_RAM_RADDR, 0);
972 return 0;
973}
974
975static int cayman_cp_start(struct radeon_device *rdev)
976{
e32eb50d 977 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
0c88a02e
AD		 978 int r, i;
979
e32eb50d 980 r = radeon_ring_lock(rdev, ring, 7);
0c88a02e
AD		 981 if (r) {
982 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
983 return r;
984 }
e32eb50d
CK		 985 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
986 radeon_ring_write(ring, 0x1);
987 radeon_ring_write(ring, 0x0);
988 radeon_ring_write(ring, rdev->config.cayman.max_hw_contexts - 1);
989 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
990 radeon_ring_write(ring, 0);
991 radeon_ring_write(ring, 0);
992 radeon_ring_unlock_commit(rdev, ring);
0c88a02e
AD		 993
994 cayman_cp_enable(rdev, true);
995
e32eb50d 996 r = radeon_ring_lock(rdev, ring, cayman_default_size + 19);
0c88a02e
AD		 997 if (r) {
998 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
999 return r;
1000 }
1001
1002 /* setup clear context state */
e32eb50d
CK		 1003 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1004 radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
0c88a02e
AD		 1005
1006 for (i = 0; i < cayman_default_size; i++)
e32eb50d 1007 radeon_ring_write(ring, cayman_default_state[i]);
0c88a02e 1008
e32eb50d
CK		 1009 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1010 radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
0c88a02e
AD		 1011
1012 /* set clear context state */
e32eb50d
CK		 1013 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
1014 radeon_ring_write(ring, 0);
0c88a02e
AD		 1015
1016 /* SQ_VTX_BASE_VTX_LOC */
e32eb50d
CK		 1017 radeon_ring_write(ring, 0xc0026f00);
1018 radeon_ring_write(ring, 0x00000000);
1019 radeon_ring_write(ring, 0x00000000);
1020 radeon_ring_write(ring, 0x00000000);
0c88a02e
AD		 1021
1022 /* Clear consts */
e32eb50d
CK		 1023 radeon_ring_write(ring, 0xc0036f00);
1024 radeon_ring_write(ring, 0x00000bc4);
1025 radeon_ring_write(ring, 0xffffffff);
1026 radeon_ring_write(ring, 0xffffffff);
1027 radeon_ring_write(ring, 0xffffffff);
0c88a02e 1028
e32eb50d
CK		 1029 radeon_ring_write(ring, 0xc0026900);
1030 radeon_ring_write(ring, 0x00000316);
1031 radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
1032 radeon_ring_write(ring, 0x00000010); /* */
9b91d18d 1033
e32eb50d 1034 radeon_ring_unlock_commit(rdev, ring);
0c88a02e
AD		 1035
1036 /* XXX init other rings */
1037
1038 return 0;
1039}
1040
755d819e
AD		 1041static void cayman_cp_fini(struct radeon_device *rdev)
1042{
45df6803 1043 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
755d819e 1044 cayman_cp_enable(rdev, false);
45df6803
CK		 1045 radeon_ring_fini(rdev, ring);
1046 radeon_scratch_free(rdev, ring->rptr_save_reg);
755d819e
AD		 1047}
1048
1109ca09 1049static int cayman_cp_resume(struct radeon_device *rdev)
0c88a02e 1050{
b90ca986
CK		 1051 static const int ridx[] = {
1052 RADEON_RING_TYPE_GFX_INDEX,
1053 CAYMAN_RING_TYPE_CP1_INDEX,
1054 CAYMAN_RING_TYPE_CP2_INDEX
1055 };
1056 static const unsigned cp_rb_cntl[] = {
1057 CP_RB0_CNTL,
1058 CP_RB1_CNTL,
1059 CP_RB2_CNTL,
1060 };
1061 static const unsigned cp_rb_rptr_addr[] = {
1062 CP_RB0_RPTR_ADDR,
1063 CP_RB1_RPTR_ADDR,
1064 CP_RB2_RPTR_ADDR
1065 };
1066 static const unsigned cp_rb_rptr_addr_hi[] = {
1067 CP_RB0_RPTR_ADDR_HI,
1068 CP_RB1_RPTR_ADDR_HI,
1069 CP_RB2_RPTR_ADDR_HI
1070 };
1071 static const unsigned cp_rb_base[] = {
1072 CP_RB0_BASE,
1073 CP_RB1_BASE,
1074 CP_RB2_BASE
1075 };
e32eb50d 1076 struct radeon_ring *ring;
b90ca986 1077 int i, r;
0c88a02e
AD		 1078
1079 /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
1080 WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
1081 SOFT_RESET_PA |
1082 SOFT_RESET_SH |
1083 SOFT_RESET_VGT |
a49a50da 1084 SOFT_RESET_SPI |
0c88a02e
AD		 1085 SOFT_RESET_SX));
1086 RREG32(GRBM_SOFT_RESET);
1087 mdelay(15);
1088 WREG32(GRBM_SOFT_RESET, 0);
1089 RREG32(GRBM_SOFT_RESET);
1090
15d3332f 1091 WREG32(CP_SEM_WAIT_TIMER, 0x0);
11ef3f1f 1092 WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
0c88a02e
AD		 1093
1094 /* Set the write pointer delay */
1095 WREG32(CP_RB_WPTR_DELAY, 0);
1096
1097 WREG32(CP_DEBUG, (1 << 27));
1098
48fc7f7e 1099 /* set the wb address whether it's enabled or not */
0c88a02e 1100 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
b90ca986 1101 WREG32(SCRATCH_UMSK, 0xff);
0c88a02e 1102
b90ca986
CK		 1103 for (i = 0; i < 3; ++i) {
1104 uint32_t rb_cntl;
1105 uint64_t addr;
0c88a02e 1106
b90ca986
CK		 1107 /* Set ring buffer size */
1108 ring = &rdev->ring[ridx[i]];
1109 rb_cntl = drm_order(ring->ring_size / 8);
1110 rb_cntl |= drm_order(RADEON_GPU_PAGE_SIZE/8) << 8;
0c88a02e 1111#ifdef __BIG_ENDIAN
b90ca986 1112 rb_cntl |= BUF_SWAP_32BIT;
0c88a02e 1113#endif
b90ca986 1114 WREG32(cp_rb_cntl[i], rb_cntl);
0c88a02e 1115
48fc7f7e 1116 /* set the wb address whether it's enabled or not */
b90ca986
CK		 1117 addr = rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET;
1118 WREG32(cp_rb_rptr_addr[i], addr & 0xFFFFFFFC);
1119 WREG32(cp_rb_rptr_addr_hi[i], upper_32_bits(addr) & 0xFF);
1120 }
0c88a02e 1121
b90ca986
CK		 1122 /* set the rb base addr, this causes an internal reset of ALL rings */
1123 for (i = 0; i < 3; ++i) {
1124 ring = &rdev->ring[ridx[i]];
1125 WREG32(cp_rb_base[i], ring->gpu_addr >> 8);
1126 }
0c88a02e 1127
b90ca986
CK		 1128 for (i = 0; i < 3; ++i) {
1129 /* Initialize the ring buffer's read and write pointers */
1130 ring = &rdev->ring[ridx[i]];
1131 WREG32_P(cp_rb_cntl[i], RB_RPTR_WR_ENA, ~RB_RPTR_WR_ENA);
0c88a02e 1132
b90ca986
CK		 1133 ring->rptr = ring->wptr = 0;
1134 WREG32(ring->rptr_reg, ring->rptr);
1135 WREG32(ring->wptr_reg, ring->wptr);
0c88a02e 1136
b90ca986
CK		 1137 mdelay(1);
1138 WREG32_P(cp_rb_cntl[i], 0, ~RB_RPTR_WR_ENA);
1139 }
0c88a02e
AD		 1140
1141 /* start the rings */
1142 cayman_cp_start(rdev);
e32eb50d
CK		 1143 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = true;
1144 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
1145 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
0c88a02e 1146 /* this only test cp0 */
f712812e 1147 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
0c88a02e 1148 if (r) {
e32eb50d
CK		 1149 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1150 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
1151 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
0c88a02e
AD		 1152 return r;
1153 }
1154
1155 return 0;
1156}
1157
f60cbd11
AD		 1158/*
1159 * DMA
1160 * Starting with R600, the GPU has an asynchronous
1161 * DMA engine. The programming model is very similar
1162 * to the 3D engine (ring buffer, IBs, etc.), but the
1163 * DMA controller has it's own packet format that is
1164 * different form the PM4 format used by the 3D engine.
1165 * It supports copying data, writing embedded data,
1166 * solid fills, and a number of other things. It also
1167 * has support for tiling/detiling of buffers.
1168 * Cayman and newer support two asynchronous DMA engines.
1169 */
1170/**
1171 * cayman_dma_ring_ib_execute - Schedule an IB on the DMA engine
1172 *
1173 * @rdev: radeon_device pointer
1174 * @ib: IB object to schedule
1175 *
1176 * Schedule an IB in the DMA ring (cayman-SI).
1177 */
1178void cayman_dma_ring_ib_execute(struct radeon_device *rdev,
1179 struct radeon_ib *ib)
1180{
1181 struct radeon_ring *ring = &rdev->ring[ib->ring];
1182
1183 if (rdev->wb.enabled) {
1184 u32 next_rptr = ring->wptr + 4;
1185 while ((next_rptr & 7) != 5)
1186 next_rptr++;
1187 next_rptr += 3;
1188 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1));
1189 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
1190 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff);
1191 radeon_ring_write(ring, next_rptr);
1192 }
1193
1194 /* The indirect buffer packet must end on an 8 DW boundary in the DMA ring.
1195 * Pad as necessary with NOPs.
1196 */
1197 while ((ring->wptr & 7) != 5)
1198 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
1199 radeon_ring_write(ring, DMA_IB_PACKET(DMA_PACKET_INDIRECT_BUFFER, ib->vm ? ib->vm->id : 0, 0));
1200 radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0));
1201 radeon_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF));
1202
1203}
1204
1205/**
1206 * cayman_dma_stop - stop the async dma engines
1207 *
1208 * @rdev: radeon_device pointer
1209 *
1210 * Stop the async dma engines (cayman-SI).
1211 */
1212void cayman_dma_stop(struct radeon_device *rdev)
1213{
1214 u32 rb_cntl;
1215
1216 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1217
1218 /* dma0 */
1219 rb_cntl = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);
1220 rb_cntl &= ~DMA_RB_ENABLE;
1221 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, rb_cntl);
1222
1223 /* dma1 */
1224 rb_cntl = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);
1225 rb_cntl &= ~DMA_RB_ENABLE;
1226 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, rb_cntl);
1227
1228 rdev->ring[R600_RING_TYPE_DMA_INDEX].ready = false;
1229 rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX].ready = false;
1230}
1231
1232/**
1233 * cayman_dma_resume - setup and start the async dma engines
1234 *
1235 * @rdev: radeon_device pointer
1236 *
1237 * Set up the DMA ring buffers and enable them. (cayman-SI).
1238 * Returns 0 for success, error for failure.
1239 */
1240int cayman_dma_resume(struct radeon_device *rdev)
1241{
1242 struct radeon_ring *ring;
b3dfcb20 1243 u32 rb_cntl, dma_cntl, ib_cntl;
f60cbd11
AD		 1244 u32 rb_bufsz;
1245 u32 reg_offset, wb_offset;
1246 int i, r;
1247
1248 /* Reset dma */
1249 WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA | SOFT_RESET_DMA1);
1250 RREG32(SRBM_SOFT_RESET);
1251 udelay(50);
1252 WREG32(SRBM_SOFT_RESET, 0);
1253
1254 for (i = 0; i < 2; i++) {
1255 if (i == 0) {
1256 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
1257 reg_offset = DMA0_REGISTER_OFFSET;
1258 wb_offset = R600_WB_DMA_RPTR_OFFSET;
1259 } else {
1260 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
1261 reg_offset = DMA1_REGISTER_OFFSET;
1262 wb_offset = CAYMAN_WB_DMA1_RPTR_OFFSET;
1263 }
1264
1265 WREG32(DMA_SEM_INCOMPLETE_TIMER_CNTL + reg_offset, 0);
1266 WREG32(DMA_SEM_WAIT_FAIL_TIMER_CNTL + reg_offset, 0);
1267
1268 /* Set ring buffer size in dwords */
1269 rb_bufsz = drm_order(ring->ring_size / 4);
1270 rb_cntl = rb_bufsz << 1;
1271#ifdef __BIG_ENDIAN
1272 rb_cntl |= DMA_RB_SWAP_ENABLE | DMA_RPTR_WRITEBACK_SWAP_ENABLE;
1273#endif
1274 WREG32(DMA_RB_CNTL + reg_offset, rb_cntl);
1275
1276 /* Initialize the ring buffer's read and write pointers */
1277 WREG32(DMA_RB_RPTR + reg_offset, 0);
1278 WREG32(DMA_RB_WPTR + reg_offset, 0);
1279
1280 /* set the wb address whether it's enabled or not */
1281 WREG32(DMA_RB_RPTR_ADDR_HI + reg_offset,
1282 upper_32_bits(rdev->wb.gpu_addr + wb_offset) & 0xFF);
1283 WREG32(DMA_RB_RPTR_ADDR_LO + reg_offset,
1284 ((rdev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC));
1285
1286 if (rdev->wb.enabled)
1287 rb_cntl |= DMA_RPTR_WRITEBACK_ENABLE;
1288
1289 WREG32(DMA_RB_BASE + reg_offset, ring->gpu_addr >> 8);
1290
1291 /* enable DMA IBs */
b3dfcb20
MD		 1292 ib_cntl = DMA_IB_ENABLE | CMD_VMID_FORCE;
1293#ifdef __BIG_ENDIAN
1294 ib_cntl |= DMA_IB_SWAP_ENABLE;
1295#endif
1296 WREG32(DMA_IB_CNTL + reg_offset, ib_cntl);
f60cbd11
AD		 1297
1298 dma_cntl = RREG32(DMA_CNTL + reg_offset);
1299 dma_cntl &= ~CTXEMPTY_INT_ENABLE;
1300 WREG32(DMA_CNTL + reg_offset, dma_cntl);
1301
1302 ring->wptr = 0;
1303 WREG32(DMA_RB_WPTR + reg_offset, ring->wptr << 2);
1304
1305 ring->rptr = RREG32(DMA_RB_RPTR + reg_offset) >> 2;
1306
1307 WREG32(DMA_RB_CNTL + reg_offset, rb_cntl | DMA_RB_ENABLE);
1308
1309 ring->ready = true;
1310
1311 r = radeon_ring_test(rdev, ring->idx, ring);
1312 if (r) {
1313 ring->ready = false;
1314 return r;
1315 }
1316 }
1317
1318 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
1319
1320 return 0;
1321}
1322
1323/**
1324 * cayman_dma_fini - tear down the async dma engines
1325 *
1326 * @rdev: radeon_device pointer
1327 *
1328 * Stop the async dma engines and free the rings (cayman-SI).
1329 */
1330void cayman_dma_fini(struct radeon_device *rdev)
1331{
1332 cayman_dma_stop(rdev);
1333 radeon_ring_fini(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX]);
1334 radeon_ring_fini(rdev, &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]);
1335}
1336
168757ea 1337static u32 cayman_gpu_check_soft_reset(struct radeon_device *rdev)
271d6fed 1338{
168757ea 1339 u32 reset_mask = 0;
187e3593 1340 u32 tmp;
271d6fed 1341
168757ea
AD		 1342 /* GRBM_STATUS */
1343 tmp = RREG32(GRBM_STATUS);
1344 if (tmp & (PA_BUSY | SC_BUSY |
1345 SH_BUSY | SX_BUSY |
1346 TA_BUSY | VGT_BUSY |
1347 DB_BUSY | CB_BUSY |
1348 GDS_BUSY | SPI_BUSY |
1349 IA_BUSY | IA_BUSY_NO_DMA))
1350 reset_mask |= RADEON_RESET_GFX;
1351
1352 if (tmp & (CF_RQ_PENDING | PF_RQ_PENDING |
1353 CP_BUSY | CP_COHERENCY_BUSY))
1354 reset_mask |= RADEON_RESET_CP;
1355
1356 if (tmp & GRBM_EE_BUSY)
1357 reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP;
1358
1359 /* DMA_STATUS_REG 0 */
1360 tmp = RREG32(DMA_STATUS_REG + DMA0_REGISTER_OFFSET);
1361 if (!(tmp & DMA_IDLE))
1362 reset_mask |= RADEON_RESET_DMA;
1363
1364 /* DMA_STATUS_REG 1 */
1365 tmp = RREG32(DMA_STATUS_REG + DMA1_REGISTER_OFFSET);
1366 if (!(tmp & DMA_IDLE))
1367 reset_mask |= RADEON_RESET_DMA1;
1368
1369 /* SRBM_STATUS2 */
1370 tmp = RREG32(SRBM_STATUS2);
1371 if (tmp & DMA_BUSY)
1372 reset_mask |= RADEON_RESET_DMA;
1373
1374 if (tmp & DMA1_BUSY)
1375 reset_mask |= RADEON_RESET_DMA1;
1376
1377 /* SRBM_STATUS */
1378 tmp = RREG32(SRBM_STATUS);
1379 if (tmp & (RLC_RQ_PENDING | RLC_BUSY))
1380 reset_mask |= RADEON_RESET_RLC;
1381
1382 if (tmp & IH_BUSY)
1383 reset_mask |= RADEON_RESET_IH;
1384
1385 if (tmp & SEM_BUSY)
1386 reset_mask |= RADEON_RESET_SEM;
1387
1388 if (tmp & GRBM_RQ_PENDING)
1389 reset_mask |= RADEON_RESET_GRBM;
1390
1391 if (tmp & VMC_BUSY)
1392 reset_mask |= RADEON_RESET_VMC;
19fc42ed 1393
168757ea
AD		 1394 if (tmp & (MCB_BUSY | MCB_NON_DISPLAY_BUSY |
1395 MCC_BUSY | MCD_BUSY))
1396 reset_mask |= RADEON_RESET_MC;
1397
1398 if (evergreen_is_display_hung(rdev))
1399 reset_mask |= RADEON_RESET_DISPLAY;
1400
1401 /* VM_L2_STATUS */
1402 tmp = RREG32(VM_L2_STATUS);
1403 if (tmp & L2_BUSY)
1404 reset_mask |= RADEON_RESET_VMC;
1405
d808fc88
AD		 1406 /* Skip MC reset as it's mostly likely not hung, just busy */
1407 if (reset_mask & RADEON_RESET_MC) {
1408 DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask);
1409 reset_mask &= ~RADEON_RESET_MC;
1410 }
1411
168757ea
AD		 1412 return reset_mask;
1413}
1414
1415static void cayman_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
1416{
1417 struct evergreen_mc_save save;
1418 u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
1419 u32 tmp;
19fc42ed 1420
271d6fed 1421 if (reset_mask == 0)
168757ea 1422 return;
271d6fed
AD		 1423
1424 dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);
1425
187e3593 1426 evergreen_print_gpu_status_regs(rdev);
271d6fed
AD		 1427 dev_info(rdev->dev, " VM_CONTEXT0_PROTECTION_FAULT_ADDR 0x%08X\n",
1428 RREG32(0x14F8));
1429 dev_info(rdev->dev, " VM_CONTEXT0_PROTECTION_FAULT_STATUS 0x%08X\n",
1430 RREG32(0x14D8));
1431 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
1432 RREG32(0x14FC));
1433 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1434 RREG32(0x14DC));
1435
187e3593
AD		 1436 /* Disable CP parsing/prefetching */
1437 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
1438
1439 if (reset_mask & RADEON_RESET_DMA) {
1440 /* dma0 */
1441 tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);
1442 tmp &= ~DMA_RB_ENABLE;
1443 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp);
168757ea 1444 }
187e3593 1445
168757ea 1446 if (reset_mask & RADEON_RESET_DMA1) {
187e3593
AD		 1447 /* dma1 */
1448 tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);
1449 tmp &= ~DMA_RB_ENABLE;
1450 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp);
1451 }
1452
90fb8779
AD		 1453 udelay(50);
1454
1455 evergreen_mc_stop(rdev, &save);
1456 if (evergreen_mc_wait_for_idle(rdev)) {
1457 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1458 }
1459
187e3593
AD		 1460 if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE)) {
1461 grbm_soft_reset = SOFT_RESET_CB |
1462 SOFT_RESET_DB |
1463 SOFT_RESET_GDS |
1464 SOFT_RESET_PA |
1465 SOFT_RESET_SC |
1466 SOFT_RESET_SPI |
1467 SOFT_RESET_SH |
1468 SOFT_RESET_SX |
1469 SOFT_RESET_TC |
1470 SOFT_RESET_TA |
1471 SOFT_RESET_VGT |
1472 SOFT_RESET_IA;
1473 }
1474
1475 if (reset_mask & RADEON_RESET_CP) {
1476 grbm_soft_reset |= SOFT_RESET_CP | SOFT_RESET_VGT;
1477
1478 srbm_soft_reset |= SOFT_RESET_GRBM;
1479 }
271d6fed
AD		 1480
1481 if (reset_mask & RADEON_RESET_DMA)
168757ea
AD		 1482 srbm_soft_reset |= SOFT_RESET_DMA;
1483
1484 if (reset_mask & RADEON_RESET_DMA1)
1485 srbm_soft_reset |= SOFT_RESET_DMA1;
1486
1487 if (reset_mask & RADEON_RESET_DISPLAY)
1488 srbm_soft_reset |= SOFT_RESET_DC;
1489
1490 if (reset_mask & RADEON_RESET_RLC)
1491 srbm_soft_reset |= SOFT_RESET_RLC;
1492
1493 if (reset_mask & RADEON_RESET_SEM)
1494 srbm_soft_reset |= SOFT_RESET_SEM;
1495
1496 if (reset_mask & RADEON_RESET_IH)
1497 srbm_soft_reset |= SOFT_RESET_IH;
1498
1499 if (reset_mask & RADEON_RESET_GRBM)
1500 srbm_soft_reset |= SOFT_RESET_GRBM;
1501
1502 if (reset_mask & RADEON_RESET_VMC)
1503 srbm_soft_reset |= SOFT_RESET_VMC;
1504
24178ec4
AD		 1505 if (!(rdev->flags & RADEON_IS_IGP)) {
1506 if (reset_mask & RADEON_RESET_MC)
1507 srbm_soft_reset |= SOFT_RESET_MC;
1508 }
187e3593
AD		 1509
1510 if (grbm_soft_reset) {
1511 tmp = RREG32(GRBM_SOFT_RESET);
1512 tmp |= grbm_soft_reset;
1513 dev_info(rdev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
1514 WREG32(GRBM_SOFT_RESET, tmp);
1515 tmp = RREG32(GRBM_SOFT_RESET);
1516
1517 udelay(50);
1518
1519 tmp &= ~grbm_soft_reset;
1520 WREG32(GRBM_SOFT_RESET, tmp);
1521 tmp = RREG32(GRBM_SOFT_RESET);
1522 }
1523
1524 if (srbm_soft_reset) {
1525 tmp = RREG32(SRBM_SOFT_RESET);
1526 tmp |= srbm_soft_reset;
1527 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1528 WREG32(SRBM_SOFT_RESET, tmp);
1529 tmp = RREG32(SRBM_SOFT_RESET);
1530
1531 udelay(50);
1532
1533 tmp &= ~srbm_soft_reset;
1534 WREG32(SRBM_SOFT_RESET, tmp);
1535 tmp = RREG32(SRBM_SOFT_RESET);
1536 }
271d6fed
AD		 1537
1538 /* Wait a little for things to settle down */
1539 udelay(50);
1540
b9952a8a 1541 evergreen_mc_resume(rdev, &save);
187e3593
AD		 1542 udelay(50);
1543
187e3593 1544 evergreen_print_gpu_status_regs(rdev);
b9952a8a
AD		 1545}
1546
1547int cayman_asic_reset(struct radeon_device *rdev)
1548{
168757ea
AD		 1549 u32 reset_mask;
1550
1551 reset_mask = cayman_gpu_check_soft_reset(rdev);
1552
1553 if (reset_mask)
1554 r600_set_bios_scratch_engine_hung(rdev, true);
1555
1556 cayman_gpu_soft_reset(rdev, reset_mask);
1557
1558 reset_mask = cayman_gpu_check_soft_reset(rdev);
1559
1560 if (!reset_mask)
1561 r600_set_bios_scratch_engine_hung(rdev, false);
1562
1563 return 0;
b9952a8a
AD		 1564}
1565
123bc183
AD		 1566/**
1567 * cayman_gfx_is_lockup - Check if the GFX engine is locked up
1568 *
1569 * @rdev: radeon_device pointer
1570 * @ring: radeon_ring structure holding ring information
1571 *
1572 * Check if the GFX engine is locked up.
1573 * Returns true if the engine appears to be locked up, false if not.
1574 */
1575bool cayman_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
1576{
1577 u32 reset_mask = cayman_gpu_check_soft_reset(rdev);
1578
1579 if (!(reset_mask & (RADEON_RESET_GFX |
1580 RADEON_RESET_COMPUTE |
1581 RADEON_RESET_CP))) {
1582 radeon_ring_lockup_update(ring);
1583 return false;
1584 }
1585 /* force CP activities */
1586 radeon_ring_force_activity(rdev, ring);
1587 return radeon_ring_test_lockup(rdev, ring);
1588}
1589
f60cbd11
AD		 1590/**
1591 * cayman_dma_is_lockup - Check if the DMA engine is locked up
1592 *
1593 * @rdev: radeon_device pointer
1594 * @ring: radeon_ring structure holding ring information
1595 *
123bc183 1596 * Check if the async DMA engine is locked up.
f60cbd11
AD		 1597 * Returns true if the engine appears to be locked up, false if not.
1598 */
1599bool cayman_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
1600{
123bc183
AD		 1601 u32 reset_mask = cayman_gpu_check_soft_reset(rdev);
1602 u32 mask;
f60cbd11
AD		 1603
1604 if (ring->idx == R600_RING_TYPE_DMA_INDEX)
123bc183 1605 mask = RADEON_RESET_DMA;
f60cbd11 1606 else
123bc183
AD		 1607 mask = RADEON_RESET_DMA1;
1608
1609 if (!(reset_mask & mask)) {
f60cbd11
AD		 1610 radeon_ring_lockup_update(ring);
1611 return false;
1612 }
1613 /* force ring activities */
1614 radeon_ring_force_activity(rdev, ring);
1615 return radeon_ring_test_lockup(rdev, ring);
1616}
1617
755d819e
AD		 1618static int cayman_startup(struct radeon_device *rdev)
1619{
e32eb50d 1620 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
755d819e
AD		 1621 int r;
1622
b07759bf
IH		 1623 /* enable pcie gen2 link */
1624 evergreen_pcie_gen2_enable(rdev);
1625
c420c745
AD		 1626 if (rdev->flags & RADEON_IS_IGP) {
1627 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
1628 r = ni_init_microcode(rdev);
1629 if (r) {
1630 DRM_ERROR("Failed to load firmware!\n");
1631 return r;
1632 }
1633 }
1634 } else {
1635 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) {
1636 r = ni_init_microcode(rdev);
1637 if (r) {
1638 DRM_ERROR("Failed to load firmware!\n");
1639 return r;
1640 }
1641 }
1642
1643 r = ni_mc_load_microcode(rdev);
755d819e 1644 if (r) {
c420c745 1645 DRM_ERROR("Failed to load MC firmware!\n");
755d819e
AD		 1646 return r;
1647 }
1648 }
755d819e 1649
16cdf04d
AD		 1650 r = r600_vram_scratch_init(rdev);
1651 if (r)
1652 return r;
1653
755d819e
AD		 1654 evergreen_mc_program(rdev);
1655 r = cayman_pcie_gart_enable(rdev);
1656 if (r)
1657 return r;
1658 cayman_gpu_init(rdev);
1659
cb92d452 1660 r = evergreen_blit_init(rdev);
755d819e 1661 if (r) {
fb3d9e97 1662 r600_blit_fini(rdev);
27cd7769 1663 rdev->asic->copy.copy = NULL;
755d819e
AD		 1664 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
1665 }
755d819e 1666
c420c745
AD		 1667 /* allocate rlc buffers */
1668 if (rdev->flags & RADEON_IS_IGP) {
1669 r = si_rlc_init(rdev);
1670 if (r) {
1671 DRM_ERROR("Failed to init rlc BOs!\n");
1672 return r;
1673 }
1674 }
1675
755d819e
AD		 1676 /* allocate wb buffer */
1677 r = radeon_wb_init(rdev);
1678 if (r)
1679 return r;
1680
30eb77f4
JG		 1681 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
1682 if (r) {
1683 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
1684 return r;
1685 }
1686
1687 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
1688 if (r) {
1689 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
1690 return r;
1691 }
1692
1693 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
1694 if (r) {
1695 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
1696 return r;
1697 }
1698
f60cbd11
AD		 1699 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX);
1700 if (r) {
1701 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
1702 return r;
1703 }
1704
1705 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_DMA1_INDEX);
1706 if (r) {
1707 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
1708 return r;
1709 }
1710
755d819e
AD		 1711 /* Enable IRQ */
1712 r = r600_irq_init(rdev);
1713 if (r) {
1714 DRM_ERROR("radeon: IH init failed (%d).\n", r);
1715 radeon_irq_kms_fini(rdev);
1716 return r;
1717 }
1718 evergreen_irq_set(rdev);
1719
e32eb50d 1720 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
78c5560a
AD		 1721 CP_RB0_RPTR, CP_RB0_WPTR,
1722 0, 0xfffff, RADEON_CP_PACKET2);
755d819e
AD		 1723 if (r)
1724 return r;
f60cbd11
AD		 1725
1726 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
1727 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
1728 DMA_RB_RPTR + DMA0_REGISTER_OFFSET,
1729 DMA_RB_WPTR + DMA0_REGISTER_OFFSET,
1730 2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
1731 if (r)
1732 return r;
1733
1734 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
1735 r = radeon_ring_init(rdev, ring, ring->ring_size, CAYMAN_WB_DMA1_RPTR_OFFSET,
1736 DMA_RB_RPTR + DMA1_REGISTER_OFFSET,
1737 DMA_RB_WPTR + DMA1_REGISTER_OFFSET,
1738 2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
1739 if (r)
1740 return r;
1741
755d819e
AD		 1742 r = cayman_cp_load_microcode(rdev);
1743 if (r)
1744 return r;
1745 r = cayman_cp_resume(rdev);
1746 if (r)
1747 return r;
1748
f60cbd11
AD		 1749 r = cayman_dma_resume(rdev);
1750 if (r)
1751 return r;
1752
2898c348
CK		 1753 r = radeon_ib_pool_init(rdev);
1754 if (r) {
1755 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
b15ba512 1756 return r;
2898c348 1757 }
b15ba512 1758
c6105f24
CK		 1759 r = radeon_vm_manager_init(rdev);
1760 if (r) {
1761 dev_err(rdev->dev, "vm manager initialization failed (%d).\n", r);
721604a1 1762 return r;
c6105f24 1763 }
721604a1 1764
6b53a050
RM		 1765 r = r600_audio_init(rdev);
1766 if (r)
1767 return r;
1768
755d819e
AD		 1769 return 0;
1770}
1771
1772int cayman_resume(struct radeon_device *rdev)
1773{
1774 int r;
1775
1776 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
1777 * posting will perform necessary task to bring back GPU into good
1778 * shape.
1779 */
1780 /* post card */
1781 atom_asic_init(rdev->mode_info.atom_context);
1782
b15ba512 1783 rdev->accel_working = true;
755d819e
AD		 1784 r = cayman_startup(rdev);
1785 if (r) {
1786 DRM_ERROR("cayman startup failed on resume\n");
6b7746e8 1787 rdev->accel_working = false;
755d819e
AD		 1788 return r;
1789 }
755d819e 1790 return r;
755d819e
AD		 1791}
1792
1793int cayman_suspend(struct radeon_device *rdev)
1794{
6b53a050 1795 r600_audio_fini(rdev);
fa3daf9a 1796 radeon_vm_manager_fini(rdev);
755d819e 1797 cayman_cp_enable(rdev, false);
f60cbd11 1798 cayman_dma_stop(rdev);
755d819e
AD		 1799 evergreen_irq_suspend(rdev);
1800 radeon_wb_disable(rdev);
1801 cayman_pcie_gart_disable(rdev);
755d819e
AD		 1802 return 0;
1803}
1804
1805/* Plan is to move initialization in that function and use
1806 * helper function so that radeon_device_init pretty much
1807 * do nothing more than calling asic specific function. This
1808 * should also allow to remove a bunch of callback function
1809 * like vram_info.
1810 */
1811int cayman_init(struct radeon_device *rdev)
1812{
e32eb50d 1813 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
755d819e
AD		 1814 int r;
1815
755d819e
AD		 1816 /* Read BIOS */
1817 if (!radeon_get_bios(rdev)) {
1818 if (ASIC_IS_AVIVO(rdev))
1819 return -EINVAL;
1820 }
1821 /* Must be an ATOMBIOS */
1822 if (!rdev->is_atom_bios) {
1823 dev_err(rdev->dev, "Expecting atombios for cayman GPU\n");
1824 return -EINVAL;
1825 }
1826 r = radeon_atombios_init(rdev);
1827 if (r)
1828 return r;
1829
1830 /* Post card if necessary */
1831 if (!radeon_card_posted(rdev)) {
1832 if (!rdev->bios) {
1833 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
1834 return -EINVAL;
1835 }
1836 DRM_INFO("GPU not posted. posting now...\n");
1837 atom_asic_init(rdev->mode_info.atom_context);
1838 }
1839 /* Initialize scratch registers */
1840 r600_scratch_init(rdev);
1841 /* Initialize surface registers */
1842 radeon_surface_init(rdev);
1843 /* Initialize clocks */
1844 radeon_get_clock_info(rdev->ddev);
1845 /* Fence driver */
30eb77f4 1846 r = radeon_fence_driver_init(rdev);
755d819e
AD		 1847 if (r)
1848 return r;
1849 /* initialize memory controller */
1850 r = evergreen_mc_init(rdev);
1851 if (r)
1852 return r;
1853 /* Memory manager */
1854 r = radeon_bo_init(rdev);
1855 if (r)
1856 return r;
1857
1858 r = radeon_irq_kms_init(rdev);
1859 if (r)
1860 return r;
1861
e32eb50d
CK		 1862 ring->ring_obj = NULL;
1863 r600_ring_init(rdev, ring, 1024 * 1024);
755d819e 1864
f60cbd11
AD		 1865 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
1866 ring->ring_obj = NULL;
1867 r600_ring_init(rdev, ring, 64 * 1024);
1868
1869 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
1870 ring->ring_obj = NULL;
1871 r600_ring_init(rdev, ring, 64 * 1024);
1872
755d819e
AD		 1873 rdev->ih.ring_obj = NULL;
1874 r600_ih_ring_init(rdev, 64 * 1024);
1875
1876 r = r600_pcie_gart_init(rdev);
1877 if (r)
1878 return r;
1879
1880 rdev->accel_working = true;
1881 r = cayman_startup(rdev);
1882 if (r) {
1883 dev_err(rdev->dev, "disabling GPU acceleration\n");
1884 cayman_cp_fini(rdev);
f60cbd11 1885 cayman_dma_fini(rdev);
755d819e 1886 r600_irq_fini(rdev);
c420c745
AD		 1887 if (rdev->flags & RADEON_IS_IGP)
1888 si_rlc_fini(rdev);
755d819e 1889 radeon_wb_fini(rdev);
2898c348 1890 radeon_ib_pool_fini(rdev);
721604a1 1891 radeon_vm_manager_fini(rdev);
755d819e
AD		 1892 radeon_irq_kms_fini(rdev);
1893 cayman_pcie_gart_fini(rdev);
1894 rdev->accel_working = false;
1895 }
755d819e
AD		 1896
1897 /* Don't start up if the MC ucode is missing.
1898 * The default clocks and voltages before the MC ucode
1899 * is loaded are not suffient for advanced operations.
c420c745
AD		 1900 *
1901 * We can skip this check for TN, because there is no MC
1902 * ucode.
755d819e 1903 */
c420c745 1904 if (!rdev->mc_fw && !(rdev->flags & RADEON_IS_IGP)) {
755d819e
AD		 1905 DRM_ERROR("radeon: MC ucode required for NI+.\n");
1906 return -EINVAL;
1907 }
1908
1909 return 0;
1910}
1911
1912void cayman_fini(struct radeon_device *rdev)
1913{
fb3d9e97 1914 r600_blit_fini(rdev);
755d819e 1915 cayman_cp_fini(rdev);
f60cbd11 1916 cayman_dma_fini(rdev);
755d819e 1917 r600_irq_fini(rdev);
c420c745
AD		 1918 if (rdev->flags & RADEON_IS_IGP)
1919 si_rlc_fini(rdev);
755d819e 1920 radeon_wb_fini(rdev);
721604a1 1921 radeon_vm_manager_fini(rdev);
2898c348 1922 radeon_ib_pool_fini(rdev);
755d819e
AD		 1923 radeon_irq_kms_fini(rdev);
1924 cayman_pcie_gart_fini(rdev);
16cdf04d 1925 r600_vram_scratch_fini(rdev);
755d819e
AD		 1926 radeon_gem_fini(rdev);
1927 radeon_fence_driver_fini(rdev);
1928 radeon_bo_fini(rdev);
1929 radeon_atombios_fini(rdev);
1930 kfree(rdev->bios);
1931 rdev->bios = NULL;
1932}
1933
721604a1
JG		 1934/*
1935 * vm
1936 */
1937int cayman_vm_init(struct radeon_device *rdev)
1938{
1939 /* number of VMs */
1940 rdev->vm_manager.nvm = 8;
1941 /* base offset of vram pages */
e71270fd
AD		 1942 if (rdev->flags & RADEON_IS_IGP) {
1943 u64 tmp = RREG32(FUS_MC_VM_FB_OFFSET);
1944 tmp <<= 22;
1945 rdev->vm_manager.vram_base_offset = tmp;
1946 } else
1947 rdev->vm_manager.vram_base_offset = 0;
721604a1
JG		 1948 return 0;
1949}
1950
1951void cayman_vm_fini(struct radeon_device *rdev)
1952{
1953}
1954
dce34bfd 1955#define R600_ENTRY_VALID (1 << 0)
721604a1
JG		 1956#define R600_PTE_SYSTEM (1 << 1)
1957#define R600_PTE_SNOOPED (1 << 2)
1958#define R600_PTE_READABLE (1 << 5)
1959#define R600_PTE_WRITEABLE (1 << 6)
1960
089a786e 1961uint32_t cayman_vm_page_flags(struct radeon_device *rdev, uint32_t flags)
721604a1
JG		 1962{
1963 uint32_t r600_flags = 0;
dce34bfd 1964 r600_flags |= (flags & RADEON_VM_PAGE_VALID) ? R600_ENTRY_VALID : 0;
721604a1
JG		 1965 r600_flags |= (flags & RADEON_VM_PAGE_READABLE) ? R600_PTE_READABLE : 0;
1966 r600_flags |= (flags & RADEON_VM_PAGE_WRITEABLE) ? R600_PTE_WRITEABLE : 0;
1967 if (flags & RADEON_VM_PAGE_SYSTEM) {
1968 r600_flags |= R600_PTE_SYSTEM;
1969 r600_flags |= (flags & RADEON_VM_PAGE_SNOOPED) ? R600_PTE_SNOOPED : 0;
1970 }
1971 return r600_flags;
1972}
1973
7a083293
AD		 1974/**
1975 * cayman_vm_set_page - update the page tables using the CP
1976 *
1977 * @rdev: radeon_device pointer
43f1214a 1978 * @ib: indirect buffer to fill with commands
dce34bfd
CK		 1979 * @pe: addr of the page entry
1980 * @addr: dst addr to write into pe
1981 * @count: number of page entries to update
1982 * @incr: increase next addr by incr bytes
1983 * @flags: access flags
7a083293 1984 *
43f1214a 1985 * Update the page tables using the CP (cayman/TN).
7a083293 1986 */
43f1214a
AD		 1987void cayman_vm_set_page(struct radeon_device *rdev,
1988 struct radeon_ib *ib,
1989 uint64_t pe,
dce34bfd
CK		 1990 uint64_t addr, unsigned count,
1991 uint32_t incr, uint32_t flags)
721604a1 1992{
dce34bfd 1993 uint32_t r600_flags = cayman_vm_page_flags(rdev, flags);
3b6b59b6
AD		 1994 uint64_t value;
1995 unsigned ndw;
1996
1997 if (rdev->asic->vm.pt_ring_index == RADEON_RING_TYPE_GFX_INDEX) {
1998 while (count) {
1999 ndw = 1 + count * 2;
2000 if (ndw > 0x3FFF)
2001 ndw = 0x3FFF;
2002
43f1214a
AD		 2003 ib->ptr[ib->length_dw++] = PACKET3(PACKET3_ME_WRITE, ndw);
2004 ib->ptr[ib->length_dw++] = pe;
2005 ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff;
3b6b59b6
AD		 2006 for (; ndw > 1; ndw -= 2, --count, pe += 8) {
2007 if (flags & RADEON_VM_PAGE_SYSTEM) {
2008 value = radeon_vm_map_gart(rdev, addr);
2009 value &= 0xFFFFFFFFFFFFF000ULL;
2010 } else if (flags & RADEON_VM_PAGE_VALID) {
2011 value = addr;
2012 } else {
2013 value = 0;
2014 }
f9fdffa5 2015 addr += incr;
3b6b59b6 2016 value |= r600_flags;
43f1214a
AD		 2017 ib->ptr[ib->length_dw++] = value;
2018 ib->ptr[ib->length_dw++] = upper_32_bits(value);
3b6b59b6
AD		 2019 }
2020 }
2021 } else {
2022 while (count) {
2023 ndw = count * 2;
2024 if (ndw > 0xFFFFE)
2025 ndw = 0xFFFFE;
2026
2027 /* for non-physically contiguous pages (system) */
43f1214a
AD		 2028 ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_WRITE, 0, 0, ndw);
2029 ib->ptr[ib->length_dw++] = pe;
2030 ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff;
3b6b59b6
AD		 2031 for (; ndw > 0; ndw -= 2, --count, pe += 8) {
2032 if (flags & RADEON_VM_PAGE_SYSTEM) {
2033 value = radeon_vm_map_gart(rdev, addr);
2034 value &= 0xFFFFFFFFFFFFF000ULL;
2035 } else if (flags & RADEON_VM_PAGE_VALID) {
2036 value = addr;
2037 } else {
2038 value = 0;
2039 }
f9fdffa5 2040 addr += incr;
3b6b59b6 2041 value |= r600_flags;
43f1214a
AD		 2042 ib->ptr[ib->length_dw++] = value;
2043 ib->ptr[ib->length_dw++] = upper_32_bits(value);
f9fdffa5 2044 }
f9fdffa5 2045 }
43f1214a
AD		 2046 while (ib->length_dw & 0x7)
2047 ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0);
2a6f1abb 2048 }
721604a1 2049}
9b40e5d8 2050
7a083293
AD		 2051/**
2052 * cayman_vm_flush - vm flush using the CP
2053 *
2054 * @rdev: radeon_device pointer
2055 *
2056 * Update the page table base and flush the VM TLB
2057 * using the CP (cayman-si).
2058 */
498522b4 2059void cayman_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm)
721604a1 2060{
498522b4 2061 struct radeon_ring *ring = &rdev->ring[ridx];
9b40e5d8 2062
ee60e29f 2063 if (vm == NULL)
9b40e5d8
CK		 2064 return;
2065
ee60e29f 2066 radeon_ring_write(ring, PACKET0(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2), 0));
fa87e62d 2067 radeon_ring_write(ring, vm->pd_gpu_addr >> 12);
ee60e29f 2068
9b40e5d8
CK		 2069 /* flush hdp cache */
2070 radeon_ring_write(ring, PACKET0(HDP_MEM_COHERENCY_FLUSH_CNTL, 0));
2071 radeon_ring_write(ring, 0x1);
2072
2073 /* bits 0-7 are the VM contexts0-7 */
2074 radeon_ring_write(ring, PACKET0(VM_INVALIDATE_REQUEST, 0));
498522b4 2075 radeon_ring_write(ring, 1 << vm->id);
58f8cf56
CK		 2076
2077 /* sync PFP to ME, otherwise we might get invalid PFP reads */
2078 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
2079 radeon_ring_write(ring, 0x0);
721604a1 2080}
f60cbd11
AD		 2081
2082void cayman_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm)
2083{
2084 struct radeon_ring *ring = &rdev->ring[ridx];
2085
2086 if (vm == NULL)
2087 return;
2088
2089 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0));
2090 radeon_ring_write(ring, (0xf << 16) | ((VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2)) >> 2));
2091 radeon_ring_write(ring, vm->pd_gpu_addr >> 12);
2092
2093 /* flush hdp cache */
2094 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0));
2095 radeon_ring_write(ring, (0xf << 16) | (HDP_MEM_COHERENCY_FLUSH_CNTL >> 2));
2096 radeon_ring_write(ring, 1);
2097
2098 /* bits 0-7 are the VM contexts0-7 */
2099 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0));
2100 radeon_ring_write(ring, (0xf << 16) | (VM_INVALIDATE_REQUEST >> 2));
2101 radeon_ring_write(ring, 1 << vm->id);
2102}
2103
Linux kernel - Deliverables
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