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drm/radeon/kms: add dpm support for cayman (v5)
[deliverable/linux.git] / drivers / gpu / drm / radeon / ni_dpm.c
CommitLineData
69e0b57a
AD		 1/*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include "drmP.h"
25#include "radeon.h"
26#include "nid.h"
27#include "r600_dpm.h"
28#include "ni_dpm.h"
29#include "atom.h"
30
31#define MC_CG_ARB_FREQ_F0 0x0a
32#define MC_CG_ARB_FREQ_F1 0x0b
33#define MC_CG_ARB_FREQ_F2 0x0c
34#define MC_CG_ARB_FREQ_F3 0x0d
35
36#define SMC_RAM_END 0xC000
37
38static const struct ni_cac_weights cac_weights_cayman_xt =
39{
40 0x15,
41 0x2,
42 0x19,
43 0x2,
44 0x8,
45 0x14,
46 0x2,
47 0x16,
48 0xE,
49 0x17,
50 0x13,
51 0x2B,
52 0x10,
53 0x7,
54 0x5,
55 0x5,
56 0x5,
57 0x2,
58 0x3,
59 0x9,
60 0x10,
61 0x10,
62 0x2B,
63 0xA,
64 0x9,
65 0x4,
66 0xD,
67 0xD,
68 0x3E,
69 0x18,
70 0x14,
71 0,
72 0x3,
73 0x3,
74 0x5,
75 0,
76 0x2,
77 0,
78 0,
79 0,
80 0,
81 0,
82 0,
83 0,
84 0,
85 0,
86 0x1CC,
87 0,
88 0x164,
89 1,
90 1,
91 1,
92 1,
93 12,
94 12,
95 12,
96 0x12,
97 0x1F,
98 132,
99 5,
100 7,
101 0,
102 { 0, 0, 0, 0, 0, 0, 0, 0 },
103 { 0, 0, 0, 0 },
104 true
105};
106
107static const struct ni_cac_weights cac_weights_cayman_pro =
108{
109 0x16,
110 0x4,
111 0x10,
112 0x2,
113 0xA,
114 0x16,
115 0x2,
116 0x18,
117 0x10,
118 0x1A,
119 0x16,
120 0x2D,
121 0x12,
122 0xA,
123 0x6,
124 0x6,
125 0x6,
126 0x2,
127 0x4,
128 0xB,
129 0x11,
130 0x11,
131 0x2D,
132 0xC,
133 0xC,
134 0x7,
135 0x10,
136 0x10,
137 0x3F,
138 0x1A,
139 0x16,
140 0,
141 0x7,
142 0x4,
143 0x6,
144 1,
145 0x2,
146 0x1,
147 0,
148 0,
149 0,
150 0,
151 0,
152 0,
153 0x30,
154 0,
155 0x1CF,
156 0,
157 0x166,
158 1,
159 1,
160 1,
161 1,
162 12,
163 12,
164 12,
165 0x15,
166 0x1F,
167 132,
168 6,
169 6,
170 0,
171 { 0, 0, 0, 0, 0, 0, 0, 0 },
172 { 0, 0, 0, 0 },
173 true
174};
175
176static const struct ni_cac_weights cac_weights_cayman_le =
177{
178 0x7,
179 0xE,
180 0x1,
181 0xA,
182 0x1,
183 0x3F,
184 0x2,
185 0x18,
186 0x10,
187 0x1A,
188 0x1,
189 0x3F,
190 0x1,
191 0xE,
192 0x6,
193 0x6,
194 0x6,
195 0x2,
196 0x4,
197 0x9,
198 0x1A,
199 0x1A,
200 0x2C,
201 0xA,
202 0x11,
203 0x8,
204 0x19,
205 0x19,
206 0x1,
207 0x1,
208 0x1A,
209 0,
210 0x8,
211 0x5,
212 0x8,
213 0x1,
214 0x3,
215 0x1,
216 0,
217 0,
218 0,
219 0,
220 0,
221 0,
222 0x38,
223 0x38,
224 0x239,
225 0x3,
226 0x18A,
227 1,
228 1,
229 1,
230 1,
231 12,
232 12,
233 12,
234 0x15,
235 0x22,
236 132,
237 6,
238 6,
239 0,
240 { 0, 0, 0, 0, 0, 0, 0, 0 },
241 { 0, 0, 0, 0 },
242 true
243};
244
245#define NISLANDS_MGCG_SEQUENCE 300
246
247static const u32 cayman_cgcg_cgls_default[] =
248{
249 0x000008f8, 0x00000010, 0xffffffff,
250 0x000008fc, 0x00000000, 0xffffffff,
251 0x000008f8, 0x00000011, 0xffffffff,
252 0x000008fc, 0x00000000, 0xffffffff,
253 0x000008f8, 0x00000012, 0xffffffff,
254 0x000008fc, 0x00000000, 0xffffffff,
255 0x000008f8, 0x00000013, 0xffffffff,
256 0x000008fc, 0x00000000, 0xffffffff,
257 0x000008f8, 0x00000014, 0xffffffff,
258 0x000008fc, 0x00000000, 0xffffffff,
259 0x000008f8, 0x00000015, 0xffffffff,
260 0x000008fc, 0x00000000, 0xffffffff,
261 0x000008f8, 0x00000016, 0xffffffff,
262 0x000008fc, 0x00000000, 0xffffffff,
263 0x000008f8, 0x00000017, 0xffffffff,
264 0x000008fc, 0x00000000, 0xffffffff,
265 0x000008f8, 0x00000018, 0xffffffff,
266 0x000008fc, 0x00000000, 0xffffffff,
267 0x000008f8, 0x00000019, 0xffffffff,
268 0x000008fc, 0x00000000, 0xffffffff,
269 0x000008f8, 0x0000001a, 0xffffffff,
270 0x000008fc, 0x00000000, 0xffffffff,
271 0x000008f8, 0x0000001b, 0xffffffff,
272 0x000008fc, 0x00000000, 0xffffffff,
273 0x000008f8, 0x00000020, 0xffffffff,
274 0x000008fc, 0x00000000, 0xffffffff,
275 0x000008f8, 0x00000021, 0xffffffff,
276 0x000008fc, 0x00000000, 0xffffffff,
277 0x000008f8, 0x00000022, 0xffffffff,
278 0x000008fc, 0x00000000, 0xffffffff,
279 0x000008f8, 0x00000023, 0xffffffff,
280 0x000008fc, 0x00000000, 0xffffffff,
281 0x000008f8, 0x00000024, 0xffffffff,
282 0x000008fc, 0x00000000, 0xffffffff,
283 0x000008f8, 0x00000025, 0xffffffff,
284 0x000008fc, 0x00000000, 0xffffffff,
285 0x000008f8, 0x00000026, 0xffffffff,
286 0x000008fc, 0x00000000, 0xffffffff,
287 0x000008f8, 0x00000027, 0xffffffff,
288 0x000008fc, 0x00000000, 0xffffffff,
289 0x000008f8, 0x00000028, 0xffffffff,
290 0x000008fc, 0x00000000, 0xffffffff,
291 0x000008f8, 0x00000029, 0xffffffff,
292 0x000008fc, 0x00000000, 0xffffffff,
293 0x000008f8, 0x0000002a, 0xffffffff,
294 0x000008fc, 0x00000000, 0xffffffff,
295 0x000008f8, 0x0000002b, 0xffffffff,
296 0x000008fc, 0x00000000, 0xffffffff
297};
298#define CAYMAN_CGCG_CGLS_DEFAULT_LENGTH sizeof(cayman_cgcg_cgls_default) / (3 * sizeof(u32))
299
300static const u32 cayman_cgcg_cgls_disable[] =
301{
302 0x000008f8, 0x00000010, 0xffffffff,
303 0x000008fc, 0xffffffff, 0xffffffff,
304 0x000008f8, 0x00000011, 0xffffffff,
305 0x000008fc, 0xffffffff, 0xffffffff,
306 0x000008f8, 0x00000012, 0xffffffff,
307 0x000008fc, 0xffffffff, 0xffffffff,
308 0x000008f8, 0x00000013, 0xffffffff,
309 0x000008fc, 0xffffffff, 0xffffffff,
310 0x000008f8, 0x00000014, 0xffffffff,
311 0x000008fc, 0xffffffff, 0xffffffff,
312 0x000008f8, 0x00000015, 0xffffffff,
313 0x000008fc, 0xffffffff, 0xffffffff,
314 0x000008f8, 0x00000016, 0xffffffff,
315 0x000008fc, 0xffffffff, 0xffffffff,
316 0x000008f8, 0x00000017, 0xffffffff,
317 0x000008fc, 0xffffffff, 0xffffffff,
318 0x000008f8, 0x00000018, 0xffffffff,
319 0x000008fc, 0xffffffff, 0xffffffff,
320 0x000008f8, 0x00000019, 0xffffffff,
321 0x000008fc, 0xffffffff, 0xffffffff,
322 0x000008f8, 0x0000001a, 0xffffffff,
323 0x000008fc, 0xffffffff, 0xffffffff,
324 0x000008f8, 0x0000001b, 0xffffffff,
325 0x000008fc, 0xffffffff, 0xffffffff,
326 0x000008f8, 0x00000020, 0xffffffff,
327 0x000008fc, 0x00000000, 0xffffffff,
328 0x000008f8, 0x00000021, 0xffffffff,
329 0x000008fc, 0x00000000, 0xffffffff,
330 0x000008f8, 0x00000022, 0xffffffff,
331 0x000008fc, 0x00000000, 0xffffffff,
332 0x000008f8, 0x00000023, 0xffffffff,
333 0x000008fc, 0x00000000, 0xffffffff,
334 0x000008f8, 0x00000024, 0xffffffff,
335 0x000008fc, 0x00000000, 0xffffffff,
336 0x000008f8, 0x00000025, 0xffffffff,
337 0x000008fc, 0x00000000, 0xffffffff,
338 0x000008f8, 0x00000026, 0xffffffff,
339 0x000008fc, 0x00000000, 0xffffffff,
340 0x000008f8, 0x00000027, 0xffffffff,
341 0x000008fc, 0x00000000, 0xffffffff,
342 0x000008f8, 0x00000028, 0xffffffff,
343 0x000008fc, 0x00000000, 0xffffffff,
344 0x000008f8, 0x00000029, 0xffffffff,
345 0x000008fc, 0x00000000, 0xffffffff,
346 0x000008f8, 0x0000002a, 0xffffffff,
347 0x000008fc, 0x00000000, 0xffffffff,
348 0x000008f8, 0x0000002b, 0xffffffff,
349 0x000008fc, 0x00000000, 0xffffffff,
350 0x00000644, 0x000f7902, 0x001f4180,
351 0x00000644, 0x000f3802, 0x001f4180
352};
353#define CAYMAN_CGCG_CGLS_DISABLE_LENGTH sizeof(cayman_cgcg_cgls_disable) / (3 * sizeof(u32))
354
355static const u32 cayman_cgcg_cgls_enable[] =
356{
357 0x00000644, 0x000f7882, 0x001f4080,
358 0x000008f8, 0x00000010, 0xffffffff,
359 0x000008fc, 0x00000000, 0xffffffff,
360 0x000008f8, 0x00000011, 0xffffffff,
361 0x000008fc, 0x00000000, 0xffffffff,
362 0x000008f8, 0x00000012, 0xffffffff,
363 0x000008fc, 0x00000000, 0xffffffff,
364 0x000008f8, 0x00000013, 0xffffffff,
365 0x000008fc, 0x00000000, 0xffffffff,
366 0x000008f8, 0x00000014, 0xffffffff,
367 0x000008fc, 0x00000000, 0xffffffff,
368 0x000008f8, 0x00000015, 0xffffffff,
369 0x000008fc, 0x00000000, 0xffffffff,
370 0x000008f8, 0x00000016, 0xffffffff,
371 0x000008fc, 0x00000000, 0xffffffff,
372 0x000008f8, 0x00000017, 0xffffffff,
373 0x000008fc, 0x00000000, 0xffffffff,
374 0x000008f8, 0x00000018, 0xffffffff,
375 0x000008fc, 0x00000000, 0xffffffff,
376 0x000008f8, 0x00000019, 0xffffffff,
377 0x000008fc, 0x00000000, 0xffffffff,
378 0x000008f8, 0x0000001a, 0xffffffff,
379 0x000008fc, 0x00000000, 0xffffffff,
380 0x000008f8, 0x0000001b, 0xffffffff,
381 0x000008fc, 0x00000000, 0xffffffff,
382 0x000008f8, 0x00000020, 0xffffffff,
383 0x000008fc, 0xffffffff, 0xffffffff,
384 0x000008f8, 0x00000021, 0xffffffff,
385 0x000008fc, 0xffffffff, 0xffffffff,
386 0x000008f8, 0x00000022, 0xffffffff,
387 0x000008fc, 0xffffffff, 0xffffffff,
388 0x000008f8, 0x00000023, 0xffffffff,
389 0x000008fc, 0xffffffff, 0xffffffff,
390 0x000008f8, 0x00000024, 0xffffffff,
391 0x000008fc, 0xffffffff, 0xffffffff,
392 0x000008f8, 0x00000025, 0xffffffff,
393 0x000008fc, 0xffffffff, 0xffffffff,
394 0x000008f8, 0x00000026, 0xffffffff,
395 0x000008fc, 0xffffffff, 0xffffffff,
396 0x000008f8, 0x00000027, 0xffffffff,
397 0x000008fc, 0xffffffff, 0xffffffff,
398 0x000008f8, 0x00000028, 0xffffffff,
399 0x000008fc, 0xffffffff, 0xffffffff,
400 0x000008f8, 0x00000029, 0xffffffff,
401 0x000008fc, 0xffffffff, 0xffffffff,
402 0x000008f8, 0x0000002a, 0xffffffff,
403 0x000008fc, 0xffffffff, 0xffffffff,
404 0x000008f8, 0x0000002b, 0xffffffff,
405 0x000008fc, 0xffffffff, 0xffffffff
406};
407#define CAYMAN_CGCG_CGLS_ENABLE_LENGTH sizeof(cayman_cgcg_cgls_enable) / (3 * sizeof(u32))
408
409static const u32 cayman_mgcg_default[] =
410{
411 0x0000802c, 0xc0000000, 0xffffffff,
412 0x00003fc4, 0xc0000000, 0xffffffff,
413 0x00005448, 0x00000100, 0xffffffff,
414 0x000055e4, 0x00000100, 0xffffffff,
415 0x0000160c, 0x00000100, 0xffffffff,
416 0x00008984, 0x06000100, 0xffffffff,
417 0x0000c164, 0x00000100, 0xffffffff,
418 0x00008a18, 0x00000100, 0xffffffff,
419 0x0000897c, 0x06000100, 0xffffffff,
420 0x00008b28, 0x00000100, 0xffffffff,
421 0x00009144, 0x00800200, 0xffffffff,
422 0x00009a60, 0x00000100, 0xffffffff,
423 0x00009868, 0x00000100, 0xffffffff,
424 0x00008d58, 0x00000100, 0xffffffff,
425 0x00009510, 0x00000100, 0xffffffff,
426 0x0000949c, 0x00000100, 0xffffffff,
427 0x00009654, 0x00000100, 0xffffffff,
428 0x00009030, 0x00000100, 0xffffffff,
429 0x00009034, 0x00000100, 0xffffffff,
430 0x00009038, 0x00000100, 0xffffffff,
431 0x0000903c, 0x00000100, 0xffffffff,
432 0x00009040, 0x00000100, 0xffffffff,
433 0x0000a200, 0x00000100, 0xffffffff,
434 0x0000a204, 0x00000100, 0xffffffff,
435 0x0000a208, 0x00000100, 0xffffffff,
436 0x0000a20c, 0x00000100, 0xffffffff,
437 0x00009744, 0x00000100, 0xffffffff,
438 0x00003f80, 0x00000100, 0xffffffff,
439 0x0000a210, 0x00000100, 0xffffffff,
440 0x0000a214, 0x00000100, 0xffffffff,
441 0x000004d8, 0x00000100, 0xffffffff,
442 0x00009664, 0x00000100, 0xffffffff,
443 0x00009698, 0x00000100, 0xffffffff,
444 0x000004d4, 0x00000200, 0xffffffff,
445 0x000004d0, 0x00000000, 0xffffffff,
446 0x000030cc, 0x00000104, 0xffffffff,
447 0x0000d0c0, 0x00000100, 0xffffffff,
448 0x0000d8c0, 0x00000100, 0xffffffff,
449 0x0000802c, 0x40000000, 0xffffffff,
450 0x00003fc4, 0x40000000, 0xffffffff,
451 0x0000915c, 0x00010000, 0xffffffff,
452 0x00009160, 0x00030002, 0xffffffff,
453 0x00009164, 0x00050004, 0xffffffff,
454 0x00009168, 0x00070006, 0xffffffff,
455 0x00009178, 0x00070000, 0xffffffff,
456 0x0000917c, 0x00030002, 0xffffffff,
457 0x00009180, 0x00050004, 0xffffffff,
458 0x0000918c, 0x00010006, 0xffffffff,
459 0x00009190, 0x00090008, 0xffffffff,
460 0x00009194, 0x00070000, 0xffffffff,
461 0x00009198, 0x00030002, 0xffffffff,
462 0x0000919c, 0x00050004, 0xffffffff,
463 0x000091a8, 0x00010006, 0xffffffff,
464 0x000091ac, 0x00090008, 0xffffffff,
465 0x000091b0, 0x00070000, 0xffffffff,
466 0x000091b4, 0x00030002, 0xffffffff,
467 0x000091b8, 0x00050004, 0xffffffff,
468 0x000091c4, 0x00010006, 0xffffffff,
469 0x000091c8, 0x00090008, 0xffffffff,
470 0x000091cc, 0x00070000, 0xffffffff,
471 0x000091d0, 0x00030002, 0xffffffff,
472 0x000091d4, 0x00050004, 0xffffffff,
473 0x000091e0, 0x00010006, 0xffffffff,
474 0x000091e4, 0x00090008, 0xffffffff,
475 0x000091e8, 0x00000000, 0xffffffff,
476 0x000091ec, 0x00070000, 0xffffffff,
477 0x000091f0, 0x00030002, 0xffffffff,
478 0x000091f4, 0x00050004, 0xffffffff,
479 0x00009200, 0x00010006, 0xffffffff,
480 0x00009204, 0x00090008, 0xffffffff,
481 0x00009208, 0x00070000, 0xffffffff,
482 0x0000920c, 0x00030002, 0xffffffff,
483 0x00009210, 0x00050004, 0xffffffff,
484 0x0000921c, 0x00010006, 0xffffffff,
485 0x00009220, 0x00090008, 0xffffffff,
486 0x00009224, 0x00070000, 0xffffffff,
487 0x00009228, 0x00030002, 0xffffffff,
488 0x0000922c, 0x00050004, 0xffffffff,
489 0x00009238, 0x00010006, 0xffffffff,
490 0x0000923c, 0x00090008, 0xffffffff,
491 0x00009240, 0x00070000, 0xffffffff,
492 0x00009244, 0x00030002, 0xffffffff,
493 0x00009248, 0x00050004, 0xffffffff,
494 0x00009254, 0x00010006, 0xffffffff,
495 0x00009258, 0x00090008, 0xffffffff,
496 0x0000925c, 0x00070000, 0xffffffff,
497 0x00009260, 0x00030002, 0xffffffff,
498 0x00009264, 0x00050004, 0xffffffff,
499 0x00009270, 0x00010006, 0xffffffff,
500 0x00009274, 0x00090008, 0xffffffff,
501 0x00009278, 0x00070000, 0xffffffff,
502 0x0000927c, 0x00030002, 0xffffffff,
503 0x00009280, 0x00050004, 0xffffffff,
504 0x0000928c, 0x00010006, 0xffffffff,
505 0x00009290, 0x00090008, 0xffffffff,
506 0x000092a8, 0x00070000, 0xffffffff,
507 0x000092ac, 0x00030002, 0xffffffff,
508 0x000092b0, 0x00050004, 0xffffffff,
509 0x000092bc, 0x00010006, 0xffffffff,
510 0x000092c0, 0x00090008, 0xffffffff,
511 0x000092c4, 0x00070000, 0xffffffff,
512 0x000092c8, 0x00030002, 0xffffffff,
513 0x000092cc, 0x00050004, 0xffffffff,
514 0x000092d8, 0x00010006, 0xffffffff,
515 0x000092dc, 0x00090008, 0xffffffff,
516 0x00009294, 0x00000000, 0xffffffff,
517 0x0000802c, 0x40010000, 0xffffffff,
518 0x00003fc4, 0x40010000, 0xffffffff,
519 0x0000915c, 0x00010000, 0xffffffff,
520 0x00009160, 0x00030002, 0xffffffff,
521 0x00009164, 0x00050004, 0xffffffff,
522 0x00009168, 0x00070006, 0xffffffff,
523 0x00009178, 0x00070000, 0xffffffff,
524 0x0000917c, 0x00030002, 0xffffffff,
525 0x00009180, 0x00050004, 0xffffffff,
526 0x0000918c, 0x00010006, 0xffffffff,
527 0x00009190, 0x00090008, 0xffffffff,
528 0x00009194, 0x00070000, 0xffffffff,
529 0x00009198, 0x00030002, 0xffffffff,
530 0x0000919c, 0x00050004, 0xffffffff,
531 0x000091a8, 0x00010006, 0xffffffff,
532 0x000091ac, 0x00090008, 0xffffffff,
533 0x000091b0, 0x00070000, 0xffffffff,
534 0x000091b4, 0x00030002, 0xffffffff,
535 0x000091b8, 0x00050004, 0xffffffff,
536 0x000091c4, 0x00010006, 0xffffffff,
537 0x000091c8, 0x00090008, 0xffffffff,
538 0x000091cc, 0x00070000, 0xffffffff,
539 0x000091d0, 0x00030002, 0xffffffff,
540 0x000091d4, 0x00050004, 0xffffffff,
541 0x000091e0, 0x00010006, 0xffffffff,
542 0x000091e4, 0x00090008, 0xffffffff,
543 0x000091e8, 0x00000000, 0xffffffff,
544 0x000091ec, 0x00070000, 0xffffffff,
545 0x000091f0, 0x00030002, 0xffffffff,
546 0x000091f4, 0x00050004, 0xffffffff,
547 0x00009200, 0x00010006, 0xffffffff,
548 0x00009204, 0x00090008, 0xffffffff,
549 0x00009208, 0x00070000, 0xffffffff,
550 0x0000920c, 0x00030002, 0xffffffff,
551 0x00009210, 0x00050004, 0xffffffff,
552 0x0000921c, 0x00010006, 0xffffffff,
553 0x00009220, 0x00090008, 0xffffffff,
554 0x00009224, 0x00070000, 0xffffffff,
555 0x00009228, 0x00030002, 0xffffffff,
556 0x0000922c, 0x00050004, 0xffffffff,
557 0x00009238, 0x00010006, 0xffffffff,
558 0x0000923c, 0x00090008, 0xffffffff,
559 0x00009240, 0x00070000, 0xffffffff,
560 0x00009244, 0x00030002, 0xffffffff,
561 0x00009248, 0x00050004, 0xffffffff,
562 0x00009254, 0x00010006, 0xffffffff,
563 0x00009258, 0x00090008, 0xffffffff,
564 0x0000925c, 0x00070000, 0xffffffff,
565 0x00009260, 0x00030002, 0xffffffff,
566 0x00009264, 0x00050004, 0xffffffff,
567 0x00009270, 0x00010006, 0xffffffff,
568 0x00009274, 0x00090008, 0xffffffff,
569 0x00009278, 0x00070000, 0xffffffff,
570 0x0000927c, 0x00030002, 0xffffffff,
571 0x00009280, 0x00050004, 0xffffffff,
572 0x0000928c, 0x00010006, 0xffffffff,
573 0x00009290, 0x00090008, 0xffffffff,
574 0x000092a8, 0x00070000, 0xffffffff,
575 0x000092ac, 0x00030002, 0xffffffff,
576 0x000092b0, 0x00050004, 0xffffffff,
577 0x000092bc, 0x00010006, 0xffffffff,
578 0x000092c0, 0x00090008, 0xffffffff,
579 0x000092c4, 0x00070000, 0xffffffff,
580 0x000092c8, 0x00030002, 0xffffffff,
581 0x000092cc, 0x00050004, 0xffffffff,
582 0x000092d8, 0x00010006, 0xffffffff,
583 0x000092dc, 0x00090008, 0xffffffff,
584 0x00009294, 0x00000000, 0xffffffff,
585 0x0000802c, 0xc0000000, 0xffffffff,
586 0x00003fc4, 0xc0000000, 0xffffffff,
587 0x000008f8, 0x00000010, 0xffffffff,
588 0x000008fc, 0x00000000, 0xffffffff,
589 0x000008f8, 0x00000011, 0xffffffff,
590 0x000008fc, 0x00000000, 0xffffffff,
591 0x000008f8, 0x00000012, 0xffffffff,
592 0x000008fc, 0x00000000, 0xffffffff,
593 0x000008f8, 0x00000013, 0xffffffff,
594 0x000008fc, 0x00000000, 0xffffffff,
595 0x000008f8, 0x00000014, 0xffffffff,
596 0x000008fc, 0x00000000, 0xffffffff,
597 0x000008f8, 0x00000015, 0xffffffff,
598 0x000008fc, 0x00000000, 0xffffffff,
599 0x000008f8, 0x00000016, 0xffffffff,
600 0x000008fc, 0x00000000, 0xffffffff,
601 0x000008f8, 0x00000017, 0xffffffff,
602 0x000008fc, 0x00000000, 0xffffffff,
603 0x000008f8, 0x00000018, 0xffffffff,
604 0x000008fc, 0x00000000, 0xffffffff,
605 0x000008f8, 0x00000019, 0xffffffff,
606 0x000008fc, 0x00000000, 0xffffffff,
607 0x000008f8, 0x0000001a, 0xffffffff,
608 0x000008fc, 0x00000000, 0xffffffff,
609 0x000008f8, 0x0000001b, 0xffffffff,
610 0x000008fc, 0x00000000, 0xffffffff
611};
612#define CAYMAN_MGCG_DEFAULT_LENGTH sizeof(cayman_mgcg_default) / (3 * sizeof(u32))
613
614static const u32 cayman_mgcg_disable[] =
615{
616 0x0000802c, 0xc0000000, 0xffffffff,
617 0x000008f8, 0x00000000, 0xffffffff,
618 0x000008fc, 0xffffffff, 0xffffffff,
619 0x000008f8, 0x00000001, 0xffffffff,
620 0x000008fc, 0xffffffff, 0xffffffff,
621 0x000008f8, 0x00000002, 0xffffffff,
622 0x000008fc, 0xffffffff, 0xffffffff,
623 0x000008f8, 0x00000003, 0xffffffff,
624 0x000008fc, 0xffffffff, 0xffffffff,
625 0x00009150, 0x00600000, 0xffffffff
626};
627#define CAYMAN_MGCG_DISABLE_LENGTH sizeof(cayman_mgcg_disable) / (3 * sizeof(u32))
628
629static const u32 cayman_mgcg_enable[] =
630{
631 0x0000802c, 0xc0000000, 0xffffffff,
632 0x000008f8, 0x00000000, 0xffffffff,
633 0x000008fc, 0x00000000, 0xffffffff,
634 0x000008f8, 0x00000001, 0xffffffff,
635 0x000008fc, 0x00000000, 0xffffffff,
636 0x000008f8, 0x00000002, 0xffffffff,
637 0x000008fc, 0x00600000, 0xffffffff,
638 0x000008f8, 0x00000003, 0xffffffff,
639 0x000008fc, 0x00000000, 0xffffffff,
640 0x00009150, 0x96944200, 0xffffffff
641};
642
643#define CAYMAN_MGCG_ENABLE_LENGTH sizeof(cayman_mgcg_enable) / (3 * sizeof(u32))
644
645#define NISLANDS_SYSLS_SEQUENCE 100
646
647static const u32 cayman_sysls_default[] =
648{
649 /* Register, Value, Mask bits */
650 0x000055e8, 0x00000000, 0xffffffff,
651 0x0000d0bc, 0x00000000, 0xffffffff,
652 0x0000d8bc, 0x00000000, 0xffffffff,
653 0x000015c0, 0x000c1401, 0xffffffff,
654 0x0000264c, 0x000c0400, 0xffffffff,
655 0x00002648, 0x000c0400, 0xffffffff,
656 0x00002650, 0x000c0400, 0xffffffff,
657 0x000020b8, 0x000c0400, 0xffffffff,
658 0x000020bc, 0x000c0400, 0xffffffff,
659 0x000020c0, 0x000c0c80, 0xffffffff,
660 0x0000f4a0, 0x000000c0, 0xffffffff,
661 0x0000f4a4, 0x00680fff, 0xffffffff,
662 0x00002f50, 0x00000404, 0xffffffff,
663 0x000004c8, 0x00000001, 0xffffffff,
664 0x000064ec, 0x00000000, 0xffffffff,
665 0x00000c7c, 0x00000000, 0xffffffff,
666 0x00008dfc, 0x00000000, 0xffffffff
667};
668#define CAYMAN_SYSLS_DEFAULT_LENGTH sizeof(cayman_sysls_default) / (3 * sizeof(u32))
669
670static const u32 cayman_sysls_disable[] =
671{
672 /* Register, Value, Mask bits */
673 0x0000d0c0, 0x00000000, 0xffffffff,
674 0x0000d8c0, 0x00000000, 0xffffffff,
675 0x000055e8, 0x00000000, 0xffffffff,
676 0x0000d0bc, 0x00000000, 0xffffffff,
677 0x0000d8bc, 0x00000000, 0xffffffff,
678 0x000015c0, 0x00041401, 0xffffffff,
679 0x0000264c, 0x00040400, 0xffffffff,
680 0x00002648, 0x00040400, 0xffffffff,
681 0x00002650, 0x00040400, 0xffffffff,
682 0x000020b8, 0x00040400, 0xffffffff,
683 0x000020bc, 0x00040400, 0xffffffff,
684 0x000020c0, 0x00040c80, 0xffffffff,
685 0x0000f4a0, 0x000000c0, 0xffffffff,
686 0x0000f4a4, 0x00680000, 0xffffffff,
687 0x00002f50, 0x00000404, 0xffffffff,
688 0x000004c8, 0x00000001, 0xffffffff,
689 0x000064ec, 0x00007ffd, 0xffffffff,
690 0x00000c7c, 0x0000ff00, 0xffffffff,
691 0x00008dfc, 0x0000007f, 0xffffffff
692};
693#define CAYMAN_SYSLS_DISABLE_LENGTH sizeof(cayman_sysls_disable) / (3 * sizeof(u32))
694
695static const u32 cayman_sysls_enable[] =
696{
697 /* Register, Value, Mask bits */
698 0x000055e8, 0x00000001, 0xffffffff,
699 0x0000d0bc, 0x00000100, 0xffffffff,
700 0x0000d8bc, 0x00000100, 0xffffffff,
701 0x000015c0, 0x000c1401, 0xffffffff,
702 0x0000264c, 0x000c0400, 0xffffffff,
703 0x00002648, 0x000c0400, 0xffffffff,
704 0x00002650, 0x000c0400, 0xffffffff,
705 0x000020b8, 0x000c0400, 0xffffffff,
706 0x000020bc, 0x000c0400, 0xffffffff,
707 0x000020c0, 0x000c0c80, 0xffffffff,
708 0x0000f4a0, 0x000000c0, 0xffffffff,
709 0x0000f4a4, 0x00680fff, 0xffffffff,
710 0x00002f50, 0x00000903, 0xffffffff,
711 0x000004c8, 0x00000000, 0xffffffff,
712 0x000064ec, 0x00000000, 0xffffffff,
713 0x00000c7c, 0x00000000, 0xffffffff,
714 0x00008dfc, 0x00000000, 0xffffffff
715};
716#define CAYMAN_SYSLS_ENABLE_LENGTH sizeof(cayman_sysls_enable) / (3 * sizeof(u32))
717
718struct rv7xx_power_info *rv770_get_pi(struct radeon_device *rdev);
719struct evergreen_power_info *evergreen_get_pi(struct radeon_device *rdev);
720
721static struct ni_power_info *ni_get_pi(struct radeon_device *rdev)
722{
723 struct ni_power_info *pi = rdev->pm.dpm.priv;
724
725 return pi;
726}
727
728struct ni_ps *ni_get_ps(struct radeon_ps *rps)
729{
730 struct ni_ps *ps = rps->ps_priv;
731
732 return ps;
733}
734
735/* XXX: fix for kernel use */
736#if 0
737static double ni_exp(double x)
738{
739 int count = 1;
740 double sum = 1.0, term, tolerance = 0.000000001, y = x;
741
742 if (x < 0)
743 y = -1 * x;
744 term = y;
745
746 while (term >= tolerance) {
747 sum = sum + term;
748 count = count + 1;
749 term = term * (y / count);
750 }
751
752 if (x < 0)
753 sum = 1.0 / sum;
754
755 return sum;
756}
757#endif
758
759static void ni_calculate_leakage_for_v_and_t_formula(const struct ni_leakage_coeffients *coeff,
760 u16 v, s32 t,
761 u32 ileakage,
762 u32 *leakage)
763{
764/* XXX: fix for kernel use */
765#if 0
766 double kt, kv, leakage_w, i_leakage, vddc, temperature;
767
768 i_leakage = ((double)ileakage) / 1000;
769 vddc = ((double)v) / 1000;
770 temperature = ((double)t) / 1000;
771
772 kt = (((double)(coeff->at)) / 1000) * ni_exp((((double)(coeff->bt)) / 1000) * temperature);
773 kv = (((double)(coeff->av)) / 1000) * ni_exp((((double)(coeff->bv)) / 1000) * vddc);
774
775 leakage_w = i_leakage * kt * kv * vddc;
776
777 *leakage = (u32)(leakage_w * 1000);
778#endif
779}
780
781static void ni_calculate_leakage_for_v_and_t(struct radeon_device *rdev,
782 const struct ni_leakage_coeffients *coeff,
783 u16 v,
784 s32 t,
785 u32 i_leakage,
786 u32 *leakage)
787{
788 ni_calculate_leakage_for_v_and_t_formula(coeff, v, t, i_leakage, leakage);
789}
790
791static void ni_apply_state_adjust_rules(struct radeon_device *rdev)
792{
793 struct ni_power_info *ni_pi = ni_get_pi(rdev);
794 struct radeon_ps *rps = rdev->pm.dpm.requested_ps;
795 struct ni_ps *ps = ni_get_ps(rps);
796 struct radeon_clock_and_voltage_limits *max_limits;
797 bool disable_mclk_switching;
798 u32 mclk, sclk;
799 u16 vddc, vddci;
800 int i;
801
802 /* point to the hw copy since this function will modify the ps */
803 ni_pi->hw_ps = *ps;
804 rdev->pm.dpm.hw_ps.ps_priv = &ni_pi->hw_ps;
805 ps = &ni_pi->hw_ps;
806
807 if (rdev->pm.dpm.new_active_crtc_count > 1)
808 disable_mclk_switching = true;
809 else
810 disable_mclk_switching = false;
811
812 if (rdev->pm.dpm.ac_power)
813 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
814 else
815 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
816
817 if (rdev->pm.dpm.ac_power == false) {
818 for (i = 0; i < ps->performance_level_count; i++) {
819 if (ps->performance_levels[i].mclk > max_limits->mclk)
820 ps->performance_levels[i].mclk = max_limits->mclk;
821 if (ps->performance_levels[i].sclk > max_limits->sclk)
822 ps->performance_levels[i].sclk = max_limits->sclk;
823 if (ps->performance_levels[i].vddc > max_limits->vddc)
824 ps->performance_levels[i].vddc = max_limits->vddc;
825 if (ps->performance_levels[i].vddci > max_limits->vddci)
826 ps->performance_levels[i].vddci = max_limits->vddci;
827 }
828 }
829
830 /* XXX validate the min clocks required for display */
831
832 if (disable_mclk_switching) {
833 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk;
834 sclk = ps->performance_levels[0].sclk;
835 vddc = ps->performance_levels[0].vddc;
836 vddci = ps->performance_levels[ps->performance_level_count - 1].vddci;
837 } else {
838 sclk = ps->performance_levels[0].sclk;
839 mclk = ps->performance_levels[0].mclk;
840 vddc = ps->performance_levels[0].vddc;
841 vddci = ps->performance_levels[0].vddci;
842 }
843
844 /* adjusted low state */
845 ps->performance_levels[0].sclk = sclk;
846 ps->performance_levels[0].mclk = mclk;
847 ps->performance_levels[0].vddc = vddc;
848 ps->performance_levels[0].vddci = vddci;
849
850 btc_skip_blacklist_clocks(rdev, max_limits->sclk, max_limits->mclk,
851 &ps->performance_levels[0].sclk,
852 &ps->performance_levels[0].mclk);
853
854 for (i = 1; i < ps->performance_level_count; i++) {
855 if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk)
856 ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk;
857 if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc)
858 ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc;
859 }
860
861 if (disable_mclk_switching) {
862 mclk = ps->performance_levels[0].mclk;
863 for (i = 1; i < ps->performance_level_count; i++) {
864 if (mclk < ps->performance_levels[i].mclk)
865 mclk = ps->performance_levels[i].mclk;
866 }
867 for (i = 0; i < ps->performance_level_count; i++) {
868 ps->performance_levels[i].mclk = mclk;
869 ps->performance_levels[i].vddci = vddci;
870 }
871 } else {
872 for (i = 1; i < ps->performance_level_count; i++) {
873 if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk)
874 ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk;
875 if (ps->performance_levels[i].vddci < ps->performance_levels[i - 1].vddci)
876 ps->performance_levels[i].vddci = ps->performance_levels[i - 1].vddci;
877 }
878 }
879
880 for (i = 1; i < ps->performance_level_count; i++)
881 btc_skip_blacklist_clocks(rdev, max_limits->sclk, max_limits->mclk,
882 &ps->performance_levels[i].sclk,
883 &ps->performance_levels[i].mclk);
884
885 for (i = 0; i < ps->performance_level_count; i++)
886 btc_adjust_clock_combinations(rdev, max_limits,
887 &ps->performance_levels[i]);
888
889 for (i = 0; i < ps->performance_level_count; i++) {
890 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
891 ps->performance_levels[i].sclk,
892 max_limits->vddc, &ps->performance_levels[i].vddc);
893 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
894 ps->performance_levels[i].mclk,
895 max_limits->vddci, &ps->performance_levels[i].vddci);
896 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
897 ps->performance_levels[i].mclk,
898 max_limits->vddc, &ps->performance_levels[i].vddc);
899 /* XXX validate the voltage required for display */
900 }
901
902 for (i = 0; i < ps->performance_level_count; i++) {
903 btc_apply_voltage_delta_rules(rdev,
904 max_limits->vddc, max_limits->vddci,
905 &ps->performance_levels[i].vddc,
906 &ps->performance_levels[i].vddci);
907 }
908
909 ps->dc_compatible = true;
910 for (i = 0; i < ps->performance_level_count; i++) {
911 if (ps->performance_levels[i].vddc > rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc)
912 ps->dc_compatible = false;
913
914 if (ps->performance_levels[i].vddc < rdev->pm.dpm.dyn_state.min_vddc_for_pcie_gen2)
915 ps->performance_levels[i].flags &= ~ATOM_PPLIB_R600_FLAGS_PCIEGEN2;
916 }
917}
918
919static void ni_cg_clockgating_default(struct radeon_device *rdev)
920{
921 u32 count;
922 const u32 *ps = NULL;
923
924 ps = (const u32 *)&cayman_cgcg_cgls_default;
925 count = CAYMAN_CGCG_CGLS_DEFAULT_LENGTH;
926
927 btc_program_mgcg_hw_sequence(rdev, ps, count);
928}
929
930static void ni_gfx_clockgating_enable(struct radeon_device *rdev,
931 bool enable)
932{
933 u32 count;
934 const u32 *ps = NULL;
935
936 if (enable) {
937 ps = (const u32 *)&cayman_cgcg_cgls_enable;
938 count = CAYMAN_CGCG_CGLS_ENABLE_LENGTH;
939 } else {
940 ps = (const u32 *)&cayman_cgcg_cgls_disable;
941 count = CAYMAN_CGCG_CGLS_DISABLE_LENGTH;
942 }
943
944 btc_program_mgcg_hw_sequence(rdev, ps, count);
945}
946
947static void ni_mg_clockgating_default(struct radeon_device *rdev)
948{
949 u32 count;
950 const u32 *ps = NULL;
951
952 ps = (const u32 *)&cayman_mgcg_default;
953 count = CAYMAN_MGCG_DEFAULT_LENGTH;
954
955 btc_program_mgcg_hw_sequence(rdev, ps, count);
956}
957
958static void ni_mg_clockgating_enable(struct radeon_device *rdev,
959 bool enable)
960{
961 u32 count;
962 const u32 *ps = NULL;
963
964 if (enable) {
965 ps = (const u32 *)&cayman_mgcg_enable;
966 count = CAYMAN_MGCG_ENABLE_LENGTH;
967 } else {
968 ps = (const u32 *)&cayman_mgcg_disable;
969 count = CAYMAN_MGCG_DISABLE_LENGTH;
970 }
971
972 btc_program_mgcg_hw_sequence(rdev, ps, count);
973}
974
975static void ni_ls_clockgating_default(struct radeon_device *rdev)
976{
977 u32 count;
978 const u32 *ps = NULL;
979
980 ps = (const u32 *)&cayman_sysls_default;
981 count = CAYMAN_SYSLS_DEFAULT_LENGTH;
982
983 btc_program_mgcg_hw_sequence(rdev, ps, count);
984}
985
986static void ni_ls_clockgating_enable(struct radeon_device *rdev,
987 bool enable)
988{
989 u32 count;
990 const u32 *ps = NULL;
991
992 if (enable) {
993 ps = (const u32 *)&cayman_sysls_enable;
994 count = CAYMAN_SYSLS_ENABLE_LENGTH;
995 } else {
996 ps = (const u32 *)&cayman_sysls_disable;
997 count = CAYMAN_SYSLS_DISABLE_LENGTH;
998 }
999
1000 btc_program_mgcg_hw_sequence(rdev, ps, count);
1001
1002}
1003
1004static int ni_patch_single_dependency_table_based_on_leakage(struct radeon_device *rdev,
1005 struct radeon_clock_voltage_dependency_table *table)
1006{
1007 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1008 u32 i;
1009
1010 if (table) {
1011 for (i = 0; i < table->count; i++) {
1012 if (0xff01 == table->entries[i].v) {
1013 if (pi->max_vddc == 0)
1014 return -EINVAL;
1015 table->entries[i].v = pi->max_vddc;
1016 }
1017 }
1018 }
1019 return 0;
1020}
1021
1022static int ni_patch_dependency_tables_based_on_leakage(struct radeon_device *rdev)
1023{
1024 int ret = 0;
1025
1026 ret = ni_patch_single_dependency_table_based_on_leakage(rdev,
1027 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk);
1028
1029 ret = ni_patch_single_dependency_table_based_on_leakage(rdev,
1030 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk);
1031 return ret;
1032}
1033
1034static void ni_stop_dpm(struct radeon_device *rdev)
1035{
1036 WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN);
1037}
1038
1039#if 0
1040static int ni_notify_hw_of_power_source(struct radeon_device *rdev,
1041 bool ac_power)
1042{
1043 if (ac_power)
1044 return (rv770_send_msg_to_smc(rdev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ?
1045 0 : -EINVAL;
1046
1047 return 0;
1048}
1049#endif
1050
1051static PPSMC_Result ni_send_msg_to_smc_with_parameter(struct radeon_device *rdev,
1052 PPSMC_Msg msg, u32 parameter)
1053{
1054 WREG32(SMC_SCRATCH0, parameter);
1055 return rv770_send_msg_to_smc(rdev, msg);
1056}
1057
1058static int ni_restrict_performance_levels_before_switch(struct radeon_device *rdev)
1059{
1060 if (rv770_send_msg_to_smc(rdev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK)
1061 return -EINVAL;
1062
1063 return (ni_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) == PPSMC_Result_OK) ?
1064 0 : -EINVAL;
1065}
1066
1067#if 0
1068static int ni_unrestrict_performance_levels_after_switch(struct radeon_device *rdev)
1069{
1070 if (ni_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
1071 return -EINVAL;
1072
1073 return (ni_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 0) == PPSMC_Result_OK) ?
1074 0 : -EINVAL;
1075}
1076#endif
1077
1078static void ni_stop_smc(struct radeon_device *rdev)
1079{
1080 u32 tmp;
1081 int i;
1082
1083 for (i = 0; i < rdev->usec_timeout; i++) {
1084 tmp = RREG32(LB_SYNC_RESET_SEL) & LB_SYNC_RESET_SEL_MASK;
1085 if (tmp != 1)
1086 break;
1087 udelay(1);
1088 }
1089
1090 udelay(100);
1091
1092 r7xx_stop_smc(rdev);
1093}
1094
1095static int ni_process_firmware_header(struct radeon_device *rdev)
1096{
1097 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1098 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1099 struct ni_power_info *ni_pi = ni_get_pi(rdev);
1100 u32 tmp;
1101 int ret;
1102
1103 ret = rv770_read_smc_sram_dword(rdev,
1104 NISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
1105 NISLANDS_SMC_FIRMWARE_HEADER_stateTable,
1106 &tmp, pi->sram_end);
1107
1108 if (ret)
1109 return ret;
1110
1111 pi->state_table_start = (u16)tmp;
1112
1113 ret = rv770_read_smc_sram_dword(rdev,
1114 NISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
1115 NISLANDS_SMC_FIRMWARE_HEADER_softRegisters,
1116 &tmp, pi->sram_end);
1117
1118 if (ret)
1119 return ret;
1120
1121 pi->soft_regs_start = (u16)tmp;
1122
1123 ret = rv770_read_smc_sram_dword(rdev,
1124 NISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
1125 NISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable,
1126 &tmp, pi->sram_end);
1127
1128 if (ret)
1129 return ret;
1130
1131 eg_pi->mc_reg_table_start = (u16)tmp;
1132
1133 ret = rv770_read_smc_sram_dword(rdev,
1134 NISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
1135 NISLANDS_SMC_FIRMWARE_HEADER_fanTable,
1136 &tmp, pi->sram_end);
1137
1138 if (ret)
1139 return ret;
1140
1141 ni_pi->fan_table_start = (u16)tmp;
1142
1143 ret = rv770_read_smc_sram_dword(rdev,
1144 NISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
1145 NISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable,
1146 &tmp, pi->sram_end);
1147
1148 if (ret)
1149 return ret;
1150
1151 ni_pi->arb_table_start = (u16)tmp;
1152
1153 ret = rv770_read_smc_sram_dword(rdev,
1154 NISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
1155 NISLANDS_SMC_FIRMWARE_HEADER_cacTable,
1156 &tmp, pi->sram_end);
1157
1158 if (ret)
1159 return ret;
1160
1161 ni_pi->cac_table_start = (u16)tmp;
1162
1163 ret = rv770_read_smc_sram_dword(rdev,
1164 NISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
1165 NISLANDS_SMC_FIRMWARE_HEADER_spllTable,
1166 &tmp, pi->sram_end);
1167
1168 if (ret)
1169 return ret;
1170
1171 ni_pi->spll_table_start = (u16)tmp;
1172
1173
1174 return ret;
1175}
1176
1177static void ni_read_clock_registers(struct radeon_device *rdev)
1178{
1179 struct ni_power_info *ni_pi = ni_get_pi(rdev);
1180
1181 ni_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL);
1182 ni_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2);
1183 ni_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3);
1184 ni_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4);
1185 ni_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM);
1186 ni_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2);
1187 ni_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL);
1188 ni_pi->clock_registers.mpll_ad_func_cntl_2 = RREG32(MPLL_AD_FUNC_CNTL_2);
1189 ni_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL);
1190 ni_pi->clock_registers.mpll_dq_func_cntl_2 = RREG32(MPLL_DQ_FUNC_CNTL_2);
1191 ni_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL);
1192 ni_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL);
1193 ni_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);
1194 ni_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2);
1195}
1196
1197#if 0
1198static int ni_enter_ulp_state(struct radeon_device *rdev)
1199{
1200 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1201
1202 if (pi->gfx_clock_gating) {
1203 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN);
1204 WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON);
1205 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON);
1206 RREG32(GB_ADDR_CONFIG);
1207 }
1208
1209 WREG32_P(SMC_MSG, HOST_SMC_MSG(PPSMC_MSG_SwitchToMinimumPower),
1210 ~HOST_SMC_MSG_MASK);
1211
1212 udelay(25000);
1213
1214 return 0;
1215}
1216#endif
1217
1218static void ni_program_response_times(struct radeon_device *rdev)
1219{
1220 u32 voltage_response_time, backbias_response_time, acpi_delay_time, vbi_time_out;
1221 u32 vddc_dly, bb_dly, acpi_dly, vbi_dly, mclk_switch_limit;
1222 u32 reference_clock;
1223
1224 rv770_write_smc_soft_register(rdev, NI_SMC_SOFT_REGISTER_mvdd_chg_time, 1);
1225
1226 voltage_response_time = (u32)rdev->pm.dpm.voltage_response_time;
1227 backbias_response_time = (u32)rdev->pm.dpm.backbias_response_time;
1228
1229 if (voltage_response_time == 0)
1230 voltage_response_time = 1000;
1231
1232 if (backbias_response_time == 0)
1233 backbias_response_time = 1000;
1234
1235 acpi_delay_time = 15000;
1236 vbi_time_out = 100000;
1237
1238 reference_clock = radeon_get_xclk(rdev);
1239
1240 vddc_dly = (voltage_response_time * reference_clock) / 1600;
1241 bb_dly = (backbias_response_time * reference_clock) / 1600;
1242 acpi_dly = (acpi_delay_time * reference_clock) / 1600;
1243 vbi_dly = (vbi_time_out * reference_clock) / 1600;
1244
1245 mclk_switch_limit = (460 * reference_clock) / 100;
1246
1247 rv770_write_smc_soft_register(rdev, NI_SMC_SOFT_REGISTER_delay_vreg, vddc_dly);
1248 rv770_write_smc_soft_register(rdev, NI_SMC_SOFT_REGISTER_delay_bbias, bb_dly);
1249 rv770_write_smc_soft_register(rdev, NI_SMC_SOFT_REGISTER_delay_acpi, acpi_dly);
1250 rv770_write_smc_soft_register(rdev, NI_SMC_SOFT_REGISTER_mclk_chg_timeout, vbi_dly);
1251 rv770_write_smc_soft_register(rdev, NI_SMC_SOFT_REGISTER_mc_block_delay, 0xAA);
1252 rv770_write_smc_soft_register(rdev, NI_SMC_SOFT_REGISTER_mclk_switch_lim, mclk_switch_limit);
1253}
1254
1255static void ni_populate_smc_voltage_table(struct radeon_device *rdev,
1256 struct atom_voltage_table *voltage_table,
1257 NISLANDS_SMC_STATETABLE *table)
1258{
1259 unsigned int i;
1260
1261 for (i = 0; i < voltage_table->count; i++) {
1262 table->highSMIO[i] = 0;
1263 table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low);
1264 }
1265}
1266
1267static void ni_populate_smc_voltage_tables(struct radeon_device *rdev,
1268 NISLANDS_SMC_STATETABLE *table)
1269{
1270 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1271 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1272 unsigned char i;
1273
1274 if (eg_pi->vddc_voltage_table.count) {
1275 ni_populate_smc_voltage_table(rdev, &eg_pi->vddc_voltage_table, table);
1276 table->voltageMaskTable.highMask[NISLANDS_SMC_VOLTAGEMASK_VDDC] = 0;
1277 table->voltageMaskTable.lowMask[NISLANDS_SMC_VOLTAGEMASK_VDDC] =
1278 cpu_to_be32(eg_pi->vddc_voltage_table.mask_low);
1279
1280 for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) {
1281 if (pi->max_vddc_in_table <= eg_pi->vddc_voltage_table.entries[i].value) {
1282 table->maxVDDCIndexInPPTable = i;
1283 break;
1284 }
1285 }
1286 }
1287
1288 if (eg_pi->vddci_voltage_table.count) {
1289 ni_populate_smc_voltage_table(rdev, &eg_pi->vddci_voltage_table, table);
1290
1291 table->voltageMaskTable.highMask[NISLANDS_SMC_VOLTAGEMASK_VDDCI] = 0;
1292 table->voltageMaskTable.lowMask[NISLANDS_SMC_VOLTAGEMASK_VDDCI] =
1293 cpu_to_be32(eg_pi->vddc_voltage_table.mask_low);
1294 }
1295}
1296
1297static int ni_populate_voltage_value(struct radeon_device *rdev,
1298 struct atom_voltage_table *table,
1299 u16 value,
1300 NISLANDS_SMC_VOLTAGE_VALUE *voltage)
1301{
1302 unsigned int i;
1303
1304 for (i = 0; i < table->count; i++) {
1305 if (value <= table->entries[i].value) {
1306 voltage->index = (u8)i;
1307 voltage->value = cpu_to_be16(table->entries[i].value);
1308 break;
1309 }
1310 }
1311
1312 if (i >= table->count)
1313 return -EINVAL;
1314
1315 return 0;
1316}
1317
1318static void ni_populate_mvdd_value(struct radeon_device *rdev,
1319 u32 mclk,
1320 NISLANDS_SMC_VOLTAGE_VALUE *voltage)
1321{
1322 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1323 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1324
1325 if (!pi->mvdd_control) {
1326 voltage->index = eg_pi->mvdd_high_index;
1327 voltage->value = cpu_to_be16(MVDD_HIGH_VALUE);
1328 return;
1329 }
1330
1331 if (mclk <= pi->mvdd_split_frequency) {
1332 voltage->index = eg_pi->mvdd_low_index;
1333 voltage->value = cpu_to_be16(MVDD_LOW_VALUE);
1334 } else {
1335 voltage->index = eg_pi->mvdd_high_index;
1336 voltage->value = cpu_to_be16(MVDD_HIGH_VALUE);
1337 }
1338}
1339
1340static int ni_get_std_voltage_value(struct radeon_device *rdev,
1341 NISLANDS_SMC_VOLTAGE_VALUE *voltage,
1342 u16 *std_voltage)
1343{
1344 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries &&
1345 ((u32)voltage->index < rdev->pm.dpm.dyn_state.cac_leakage_table.count))
1346 *std_voltage = rdev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc;
1347 else
1348 *std_voltage = be16_to_cpu(voltage->value);
1349
1350 return 0;
1351}
1352
1353static void ni_populate_std_voltage_value(struct radeon_device *rdev,
1354 u16 value, u8 index,
1355 NISLANDS_SMC_VOLTAGE_VALUE *voltage)
1356{
1357 voltage->index = index;
1358 voltage->value = cpu_to_be16(value);
1359}
1360
1361static u32 ni_get_smc_power_scaling_factor(struct radeon_device *rdev)
1362{
1363 u32 xclk_period;
1364 u32 xclk = radeon_get_xclk(rdev);
1365 u32 tmp = RREG32(CG_CAC_CTRL) & TID_CNT_MASK;
1366
1367 xclk_period = (1000000000UL / xclk);
1368 xclk_period /= 10000UL;
1369
1370 return tmp * xclk_period;
1371}
1372
1373static u32 ni_scale_power_for_smc(u32 power_in_watts, u32 scaling_factor)
1374{
1375 return (power_in_watts * scaling_factor) << 2;
1376}
1377
1378static u32 ni_calculate_power_boost_limit(struct radeon_device *rdev,
1379 struct radeon_ps *radeon_state,
1380 u32 near_tdp_limit)
1381{
1382 struct ni_ps *state = ni_get_ps(radeon_state);
1383 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1384 struct ni_power_info *ni_pi = ni_get_pi(rdev);
1385 u32 power_boost_limit = 0;
1386 int ret;
1387
1388 if (ni_pi->enable_power_containment &&
1389 ni_pi->use_power_boost_limit) {
1390 NISLANDS_SMC_VOLTAGE_VALUE vddc;
1391 u16 std_vddc_med;
1392 u16 std_vddc_high;
1393 u64 tmp, n, d;
1394
1395 if (state->performance_level_count < 3)
1396 return 0;
1397
1398 ret = ni_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
1399 state->performance_levels[state->performance_level_count - 2].vddc,
1400 &vddc);
1401 if (ret)
1402 return 0;
1403
1404 ret = ni_get_std_voltage_value(rdev, &vddc, &std_vddc_med);
1405 if (ret)
1406 return 0;
1407
1408 ret = ni_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
1409 state->performance_levels[state->performance_level_count - 1].vddc,
1410 &vddc);
1411 if (ret)
1412 return 0;
1413
1414 ret = ni_get_std_voltage_value(rdev, &vddc, &std_vddc_high);
1415 if (ret)
1416 return 0;
1417
1418 n = ((u64)near_tdp_limit * ((u64)std_vddc_med * (u64)std_vddc_med) * 90);
1419 d = ((u64)std_vddc_high * (u64)std_vddc_high * 100);
1420 tmp = div64_u64(n, d);
1421
1422 if (tmp >> 32)
1423 return 0;
1424 power_boost_limit = (u32)tmp;
1425 }
1426
1427 return power_boost_limit;
1428}
1429
1430static int ni_calculate_adjusted_tdp_limits(struct radeon_device *rdev,
1431 bool adjust_polarity,
1432 u32 tdp_adjustment,
1433 u32 *tdp_limit,
1434 u32 *near_tdp_limit)
1435{
1436 if (tdp_adjustment > (u32)rdev->pm.dpm.tdp_od_limit)
1437 return -EINVAL;
1438
1439 if (adjust_polarity) {
1440 *tdp_limit = ((100 + tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100;
1441 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit + (*tdp_limit - rdev->pm.dpm.tdp_limit);
1442 } else {
1443 *tdp_limit = ((100 - tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100;
1444 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit - (rdev->pm.dpm.tdp_limit - *tdp_limit);
1445 }
1446
1447 return 0;
1448}
1449
1450static int ni_populate_smc_tdp_limits(struct radeon_device *rdev)
1451{
1452 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1453 struct ni_power_info *ni_pi = ni_get_pi(rdev);
1454
1455 if (ni_pi->enable_power_containment) {
1456 struct radeon_ps *radeon_state = rdev->pm.dpm.requested_ps;
1457 NISLANDS_SMC_STATETABLE *smc_table = &ni_pi->smc_statetable;
1458 u32 scaling_factor = ni_get_smc_power_scaling_factor(rdev);
1459 u32 tdp_limit;
1460 u32 near_tdp_limit;
1461 u32 power_boost_limit;
1462 int ret;
1463
1464 if (scaling_factor == 0)
1465 return -EINVAL;
1466
1467 memset(smc_table, 0, sizeof(NISLANDS_SMC_STATETABLE));
1468
1469 ret = ni_calculate_adjusted_tdp_limits(rdev,
1470 false, /* ??? */
1471 rdev->pm.dpm.tdp_adjustment,
1472 &tdp_limit,
1473 &near_tdp_limit);
1474 if (ret)
1475 return ret;
1476
1477 power_boost_limit = ni_calculate_power_boost_limit(rdev, radeon_state,
1478 near_tdp_limit);
1479
1480 smc_table->dpm2Params.TDPLimit =
1481 cpu_to_be32(ni_scale_power_for_smc(tdp_limit, scaling_factor));
1482 smc_table->dpm2Params.NearTDPLimit =
1483 cpu_to_be32(ni_scale_power_for_smc(near_tdp_limit, scaling_factor));
1484 smc_table->dpm2Params.SafePowerLimit =
1485 cpu_to_be32(ni_scale_power_for_smc((near_tdp_limit * NISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100,
1486 scaling_factor));
1487 smc_table->dpm2Params.PowerBoostLimit =
1488 cpu_to_be32(ni_scale_power_for_smc(power_boost_limit, scaling_factor));
1489
1490 ret = rv770_copy_bytes_to_smc(rdev,
1491 (u16)(pi->state_table_start + offsetof(NISLANDS_SMC_STATETABLE, dpm2Params) +
1492 offsetof(PP_NIslands_DPM2Parameters, TDPLimit)),
1493 (u8 *)(&smc_table->dpm2Params.TDPLimit),
1494 sizeof(u32) * 4, pi->sram_end);
1495 if (ret)
1496 return ret;
1497 }
1498
1499 return 0;
1500}
1501
1502static int ni_copy_and_switch_arb_sets(struct radeon_device *rdev,
1503 u32 arb_freq_src, u32 arb_freq_dest)
1504{
1505 u32 mc_arb_dram_timing;
1506 u32 mc_arb_dram_timing2;
1507 u32 burst_time;
1508 u32 mc_cg_config;
1509
1510 switch (arb_freq_src) {
1511 case MC_CG_ARB_FREQ_F0:
1512 mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING);
1513 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
1514 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE0_MASK) >> STATE0_SHIFT;
1515 break;
1516 case MC_CG_ARB_FREQ_F1:
1517 mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING_1);
1518 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_1);
1519 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE1_MASK) >> STATE1_SHIFT;
1520 break;
1521 case MC_CG_ARB_FREQ_F2:
1522 mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING_2);
1523 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_2);
1524 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE2_MASK) >> STATE2_SHIFT;
1525 break;
1526 case MC_CG_ARB_FREQ_F3:
1527 mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING_3);
1528 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_3);
1529 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE3_MASK) >> STATE3_SHIFT;
1530 break;
1531 default:
1532 return -EINVAL;
1533 }
1534
1535 switch (arb_freq_dest) {
1536 case MC_CG_ARB_FREQ_F0:
1537 WREG32(MC_ARB_DRAM_TIMING, mc_arb_dram_timing);
1538 WREG32(MC_ARB_DRAM_TIMING2, mc_arb_dram_timing2);
1539 WREG32_P(MC_ARB_BURST_TIME, STATE0(burst_time), ~STATE0_MASK);
1540 break;
1541 case MC_CG_ARB_FREQ_F1:
1542 WREG32(MC_ARB_DRAM_TIMING_1, mc_arb_dram_timing);
1543 WREG32(MC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2);
1544 WREG32_P(MC_ARB_BURST_TIME, STATE1(burst_time), ~STATE1_MASK);
1545 break;
1546 case MC_CG_ARB_FREQ_F2:
1547 WREG32(MC_ARB_DRAM_TIMING_2, mc_arb_dram_timing);
1548 WREG32(MC_ARB_DRAM_TIMING2_2, mc_arb_dram_timing2);
1549 WREG32_P(MC_ARB_BURST_TIME, STATE2(burst_time), ~STATE2_MASK);
1550 break;
1551 case MC_CG_ARB_FREQ_F3:
1552 WREG32(MC_ARB_DRAM_TIMING_3, mc_arb_dram_timing);
1553 WREG32(MC_ARB_DRAM_TIMING2_3, mc_arb_dram_timing2);
1554 WREG32_P(MC_ARB_BURST_TIME, STATE3(burst_time), ~STATE3_MASK);
1555 break;
1556 default:
1557 return -EINVAL;
1558 }
1559
1560 mc_cg_config = RREG32(MC_CG_CONFIG) | 0x0000000F;
1561 WREG32(MC_CG_CONFIG, mc_cg_config);
1562 WREG32_P(MC_ARB_CG, CG_ARB_REQ(arb_freq_dest), ~CG_ARB_REQ_MASK);
1563
1564 return 0;
1565}
1566
1567static int ni_init_arb_table_index(struct radeon_device *rdev)
1568{
1569 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1570 struct ni_power_info *ni_pi = ni_get_pi(rdev);
1571 u32 tmp;
1572 int ret;
1573
1574 ret = rv770_read_smc_sram_dword(rdev, ni_pi->arb_table_start,
1575 &tmp, pi->sram_end);
1576 if (ret)
1577 return ret;
1578
1579 tmp &= 0x00FFFFFF;
1580 tmp |= ((u32)MC_CG_ARB_FREQ_F1) << 24;
1581
1582 return rv770_write_smc_sram_dword(rdev, ni_pi->arb_table_start,
1583 tmp, pi->sram_end);
1584}
1585
1586static int ni_initial_switch_from_arb_f0_to_f1(struct radeon_device *rdev)
1587{
1588 return ni_copy_and_switch_arb_sets(rdev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
1589}
1590
1591static int ni_force_switch_to_arb_f0(struct radeon_device *rdev)
1592{
1593 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1594 struct ni_power_info *ni_pi = ni_get_pi(rdev);
1595 u32 tmp;
1596 int ret;
1597
1598 ret = rv770_read_smc_sram_dword(rdev, ni_pi->arb_table_start,
1599 &tmp, pi->sram_end);
1600 if (ret)
1601 return ret;
1602
1603 tmp = (tmp >> 24) & 0xff;
1604
1605 if (tmp == MC_CG_ARB_FREQ_F0)
1606 return 0;
1607
1608 return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0);
1609}
1610
1611static int ni_populate_memory_timing_parameters(struct radeon_device *rdev,
1612 struct rv7xx_pl *pl,
1613 SMC_NIslands_MCArbDramTimingRegisterSet *arb_regs)
1614{
1615 u32 dram_timing;
1616 u32 dram_timing2;
1617
1618 arb_regs->mc_arb_rfsh_rate =
1619 (u8)rv770_calculate_memory_refresh_rate(rdev, pl->sclk);
1620
1621
1622 radeon_atom_set_engine_dram_timings(rdev,
1623 pl->sclk,
1624 pl->mclk);
1625
1626 dram_timing = RREG32(MC_ARB_DRAM_TIMING);
1627 dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
1628
1629 arb_regs->mc_arb_dram_timing = cpu_to_be32(dram_timing);
1630 arb_regs->mc_arb_dram_timing2 = cpu_to_be32(dram_timing2);
1631
1632 return 0;
1633}
1634
1635static int ni_do_program_memory_timing_parameters(struct radeon_device *rdev,
1636 struct radeon_ps *radeon_state,
1637 unsigned int first_arb_set)
1638{
1639 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1640 struct ni_power_info *ni_pi = ni_get_pi(rdev);
1641 struct ni_ps *state = ni_get_ps(radeon_state);
1642 SMC_NIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
1643 int i, ret = 0;
1644
1645 for (i = 0; i < state->performance_level_count; i++) {
1646 ret = ni_populate_memory_timing_parameters(rdev, &state->performance_levels[i], &arb_regs);
1647 if (ret)
1648 break;
1649
1650 ret = rv770_copy_bytes_to_smc(rdev,
1651 (u16)(ni_pi->arb_table_start +
1652 offsetof(SMC_NIslands_MCArbDramTimingRegisters, data) +
1653 sizeof(SMC_NIslands_MCArbDramTimingRegisterSet) * (first_arb_set + i)),
1654 (u8 *)&arb_regs,
1655 (u16)sizeof(SMC_NIslands_MCArbDramTimingRegisterSet),
1656 pi->sram_end);
1657 if (ret)
1658 break;
1659 }
1660 return ret;
1661}
1662
1663static int ni_program_memory_timing_parameters(struct radeon_device *rdev)
1664{
1665 struct radeon_ps *radeon_new_state = rdev->pm.dpm.requested_ps;
1666
1667 return ni_do_program_memory_timing_parameters(rdev, radeon_new_state,
1668 NISLANDS_DRIVER_STATE_ARB_INDEX);
1669}
1670
1671static void ni_populate_initial_mvdd_value(struct radeon_device *rdev,
1672 struct NISLANDS_SMC_VOLTAGE_VALUE *voltage)
1673{
1674 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1675
1676 voltage->index = eg_pi->mvdd_high_index;
1677 voltage->value = cpu_to_be16(MVDD_HIGH_VALUE);
1678}
1679
1680static int ni_populate_smc_initial_state(struct radeon_device *rdev,
1681 struct radeon_ps *radeon_initial_state,
1682 NISLANDS_SMC_STATETABLE *table)
1683{
1684 struct ni_ps *initial_state = ni_get_ps(radeon_initial_state);
1685 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1686 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1687 struct ni_power_info *ni_pi = ni_get_pi(rdev);
1688 u32 reg;
1689 int ret;
1690
1691 table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
1692 cpu_to_be32(ni_pi->clock_registers.mpll_ad_func_cntl);
1693 table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL_2 =
1694 cpu_to_be32(ni_pi->clock_registers.mpll_ad_func_cntl_2);
1695 table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
1696 cpu_to_be32(ni_pi->clock_registers.mpll_dq_func_cntl);
1697 table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL_2 =
1698 cpu_to_be32(ni_pi->clock_registers.mpll_dq_func_cntl_2);
1699 table->initialState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
1700 cpu_to_be32(ni_pi->clock_registers.mclk_pwrmgt_cntl);
1701 table->initialState.levels[0].mclk.vDLL_CNTL =
1702 cpu_to_be32(ni_pi->clock_registers.dll_cntl);
1703 table->initialState.levels[0].mclk.vMPLL_SS =
1704 cpu_to_be32(ni_pi->clock_registers.mpll_ss1);
1705 table->initialState.levels[0].mclk.vMPLL_SS2 =
1706 cpu_to_be32(ni_pi->clock_registers.mpll_ss2);
1707 table->initialState.levels[0].mclk.mclk_value =
1708 cpu_to_be32(initial_state->performance_levels[0].mclk);
1709
1710 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
1711 cpu_to_be32(ni_pi->clock_registers.cg_spll_func_cntl);
1712 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
1713 cpu_to_be32(ni_pi->clock_registers.cg_spll_func_cntl_2);
1714 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
1715 cpu_to_be32(ni_pi->clock_registers.cg_spll_func_cntl_3);
1716 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
1717 cpu_to_be32(ni_pi->clock_registers.cg_spll_func_cntl_4);
1718 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM =
1719 cpu_to_be32(ni_pi->clock_registers.cg_spll_spread_spectrum);
1720 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2 =
1721 cpu_to_be32(ni_pi->clock_registers.cg_spll_spread_spectrum_2);
1722 table->initialState.levels[0].sclk.sclk_value =
1723 cpu_to_be32(initial_state->performance_levels[0].sclk);
1724 table->initialState.levels[0].arbRefreshState =
1725 NISLANDS_INITIAL_STATE_ARB_INDEX;
1726
1727 table->initialState.levels[0].ACIndex = 0;
1728
1729 ret = ni_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
1730 initial_state->performance_levels[0].vddc,
1731 &table->initialState.levels[0].vddc);
1732 if (!ret) {
1733 u16 std_vddc;
1734
1735 ret = ni_get_std_voltage_value(rdev,
1736 &table->initialState.levels[0].vddc,
1737 &std_vddc);
1738 if (!ret)
1739 ni_populate_std_voltage_value(rdev, std_vddc,
1740 table->initialState.levels[0].vddc.index,
1741 &table->initialState.levels[0].std_vddc);
1742 }
1743
1744 if (eg_pi->vddci_control)
1745 ni_populate_voltage_value(rdev,
1746 &eg_pi->vddci_voltage_table,
1747 initial_state->performance_levels[0].vddci,
1748 &table->initialState.levels[0].vddci);
1749
1750 ni_populate_initial_mvdd_value(rdev, &table->initialState.levels[0].mvdd);
1751
1752 reg = CG_R(0xffff) | CG_L(0);
1753 table->initialState.levels[0].aT = cpu_to_be32(reg);
1754
1755 table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp);
1756
1757 if (pi->boot_in_gen2)
1758 table->initialState.levels[0].gen2PCIE = 1;
1759 else
1760 table->initialState.levels[0].gen2PCIE = 0;
1761
1762 if (pi->mem_gddr5) {
1763 table->initialState.levels[0].strobeMode =
1764 cypress_get_strobe_mode_settings(rdev,
1765 initial_state->performance_levels[0].mclk);
1766
1767 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold)
1768 table->initialState.levels[0].mcFlags = NISLANDS_SMC_MC_EDC_RD_FLAG | NISLANDS_SMC_MC_EDC_WR_FLAG;
1769 else
1770 table->initialState.levels[0].mcFlags = 0;
1771 }
1772
1773 table->initialState.levelCount = 1;
1774
1775 table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC;
1776
1777 table->initialState.levels[0].dpm2.MaxPS = 0;
1778 table->initialState.levels[0].dpm2.NearTDPDec = 0;
1779 table->initialState.levels[0].dpm2.AboveSafeInc = 0;
1780 table->initialState.levels[0].dpm2.BelowSafeInc = 0;
1781
1782 reg = MIN_POWER_MASK | MAX_POWER_MASK;
1783 table->initialState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
1784
1785 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
1786 table->initialState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
1787
1788 return 0;
1789}
1790
1791static int ni_populate_smc_acpi_state(struct radeon_device *rdev,
1792 NISLANDS_SMC_STATETABLE *table)
1793{
1794 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1795 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1796 struct ni_power_info *ni_pi = ni_get_pi(rdev);
1797 u32 mpll_ad_func_cntl = ni_pi->clock_registers.mpll_ad_func_cntl;
1798 u32 mpll_ad_func_cntl_2 = ni_pi->clock_registers.mpll_ad_func_cntl_2;
1799 u32 mpll_dq_func_cntl = ni_pi->clock_registers.mpll_dq_func_cntl;
1800 u32 mpll_dq_func_cntl_2 = ni_pi->clock_registers.mpll_dq_func_cntl_2;
1801 u32 spll_func_cntl = ni_pi->clock_registers.cg_spll_func_cntl;
1802 u32 spll_func_cntl_2 = ni_pi->clock_registers.cg_spll_func_cntl_2;
1803 u32 spll_func_cntl_3 = ni_pi->clock_registers.cg_spll_func_cntl_3;
1804 u32 spll_func_cntl_4 = ni_pi->clock_registers.cg_spll_func_cntl_4;
1805 u32 mclk_pwrmgt_cntl = ni_pi->clock_registers.mclk_pwrmgt_cntl;
1806 u32 dll_cntl = ni_pi->clock_registers.dll_cntl;
1807 u32 reg;
1808 int ret;
1809
1810 table->ACPIState = table->initialState;
1811
1812 table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC;
1813
1814 if (pi->acpi_vddc) {
1815 ret = ni_populate_voltage_value(rdev,
1816 &eg_pi->vddc_voltage_table,
1817 pi->acpi_vddc, &table->ACPIState.levels[0].vddc);
1818 if (!ret) {
1819 u16 std_vddc;
1820
1821 ret = ni_get_std_voltage_value(rdev,
1822 &table->ACPIState.levels[0].vddc, &std_vddc);
1823 if (!ret)
1824 ni_populate_std_voltage_value(rdev, std_vddc,
1825 table->ACPIState.levels[0].vddc.index,
1826 &table->ACPIState.levels[0].std_vddc);
1827 }
1828
1829 if (pi->pcie_gen2) {
1830 if (pi->acpi_pcie_gen2)
1831 table->ACPIState.levels[0].gen2PCIE = 1;
1832 else
1833 table->ACPIState.levels[0].gen2PCIE = 0;
1834 } else {
1835 table->ACPIState.levels[0].gen2PCIE = 0;
1836 }
1837 } else {
1838 ret = ni_populate_voltage_value(rdev,
1839 &eg_pi->vddc_voltage_table,
1840 pi->min_vddc_in_table,
1841 &table->ACPIState.levels[0].vddc);
1842 if (!ret) {
1843 u16 std_vddc;
1844
1845 ret = ni_get_std_voltage_value(rdev,
1846 &table->ACPIState.levels[0].vddc,
1847 &std_vddc);
1848 if (!ret)
1849 ni_populate_std_voltage_value(rdev, std_vddc,
1850 table->ACPIState.levels[0].vddc.index,
1851 &table->ACPIState.levels[0].std_vddc);
1852 }
1853 table->ACPIState.levels[0].gen2PCIE = 0;
1854 }
1855
1856 if (eg_pi->acpi_vddci) {
1857 if (eg_pi->vddci_control)
1858 ni_populate_voltage_value(rdev,
1859 &eg_pi->vddci_voltage_table,
1860 eg_pi->acpi_vddci,
1861 &table->ACPIState.levels[0].vddci);
1862 }
1863
1864
1865 mpll_ad_func_cntl &= ~PDNB;
1866
1867 mpll_ad_func_cntl_2 |= BIAS_GEN_PDNB | RESET_EN;
1868
1869 if (pi->mem_gddr5)
1870 mpll_dq_func_cntl &= ~PDNB;
1871 mpll_dq_func_cntl_2 |= BIAS_GEN_PDNB | RESET_EN | BYPASS;
1872
1873
1874 mclk_pwrmgt_cntl |= (MRDCKA0_RESET |
1875 MRDCKA1_RESET |
1876 MRDCKB0_RESET |
1877 MRDCKB1_RESET |
1878 MRDCKC0_RESET |
1879 MRDCKC1_RESET |
1880 MRDCKD0_RESET |
1881 MRDCKD1_RESET);
1882
1883 mclk_pwrmgt_cntl &= ~(MRDCKA0_PDNB |
1884 MRDCKA1_PDNB |
1885 MRDCKB0_PDNB |
1886 MRDCKB1_PDNB |
1887 MRDCKC0_PDNB |
1888 MRDCKC1_PDNB |
1889 MRDCKD0_PDNB |
1890 MRDCKD1_PDNB);
1891
1892 dll_cntl |= (MRDCKA0_BYPASS |
1893 MRDCKA1_BYPASS |
1894 MRDCKB0_BYPASS |
1895 MRDCKB1_BYPASS |
1896 MRDCKC0_BYPASS |
1897 MRDCKC1_BYPASS |
1898 MRDCKD0_BYPASS |
1899 MRDCKD1_BYPASS);
1900
1901 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
1902 spll_func_cntl_2 |= SCLK_MUX_SEL(4);
1903
1904 table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl);
1905 table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL_2 = cpu_to_be32(mpll_ad_func_cntl_2);
1906 table->ACPIState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl);
1907 table->ACPIState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL_2 = cpu_to_be32(mpll_dq_func_cntl_2);
1908 table->ACPIState.levels[0].mclk.vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl);
1909 table->ACPIState.levels[0].mclk.vDLL_CNTL = cpu_to_be32(dll_cntl);
1910
1911 table->ACPIState.levels[0].mclk.mclk_value = 0;
1912
1913 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl);
1914 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2);
1915 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3);
1916 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(spll_func_cntl_4);
1917
1918 table->ACPIState.levels[0].sclk.sclk_value = 0;
1919
1920 ni_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd);
1921
1922 if (eg_pi->dynamic_ac_timing)
1923 table->ACPIState.levels[0].ACIndex = 1;
1924
1925 table->ACPIState.levels[0].dpm2.MaxPS = 0;
1926 table->ACPIState.levels[0].dpm2.NearTDPDec = 0;
1927 table->ACPIState.levels[0].dpm2.AboveSafeInc = 0;
1928 table->ACPIState.levels[0].dpm2.BelowSafeInc = 0;
1929
1930 reg = MIN_POWER_MASK | MAX_POWER_MASK;
1931 table->ACPIState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
1932
1933 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
1934 table->ACPIState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
1935
1936 return 0;
1937}
1938
1939static int ni_init_smc_table(struct radeon_device *rdev)
1940{
1941 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1942 struct ni_power_info *ni_pi = ni_get_pi(rdev);
1943 int ret;
1944 struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps;
1945 NISLANDS_SMC_STATETABLE *table = &ni_pi->smc_statetable;
1946
1947 memset(table, 0, sizeof(NISLANDS_SMC_STATETABLE));
1948
1949 ni_populate_smc_voltage_tables(rdev, table);
1950
1951 switch (rdev->pm.int_thermal_type) {
1952 case THERMAL_TYPE_NI:
1953 case THERMAL_TYPE_EMC2103_WITH_INTERNAL:
1954 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL;
1955 break;
1956 case THERMAL_TYPE_NONE:
1957 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE;
1958 break;
1959 default:
1960 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL;
1961 break;
1962 }
1963
1964 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)
1965 table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
1966
1967 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT)
1968 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT;
1969
1970 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
1971 table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
1972
1973 if (pi->mem_gddr5)
1974 table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
1975
1976 ret = ni_populate_smc_initial_state(rdev, radeon_boot_state, table);
1977 if (ret)
1978 return ret;
1979
1980 ret = ni_populate_smc_acpi_state(rdev, table);
1981 if (ret)
1982 return ret;
1983
1984 table->driverState = table->initialState;
1985
1986 table->ULVState = table->initialState;
1987
1988 ret = ni_do_program_memory_timing_parameters(rdev, radeon_boot_state,
1989 NISLANDS_INITIAL_STATE_ARB_INDEX);
1990 if (ret)
1991 return ret;
1992
1993 return rv770_copy_bytes_to_smc(rdev, pi->state_table_start, (u8 *)table,
1994 sizeof(NISLANDS_SMC_STATETABLE), pi->sram_end);
1995}
1996
1997static int ni_calculate_sclk_params(struct radeon_device *rdev,
1998 u32 engine_clock,
1999 NISLANDS_SMC_SCLK_VALUE *sclk)
2000{
2001 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
2002 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2003 struct atom_clock_dividers dividers;
2004 u32 spll_func_cntl = ni_pi->clock_registers.cg_spll_func_cntl;
2005 u32 spll_func_cntl_2 = ni_pi->clock_registers.cg_spll_func_cntl_2;
2006 u32 spll_func_cntl_3 = ni_pi->clock_registers.cg_spll_func_cntl_3;
2007 u32 spll_func_cntl_4 = ni_pi->clock_registers.cg_spll_func_cntl_4;
2008 u32 cg_spll_spread_spectrum = ni_pi->clock_registers.cg_spll_spread_spectrum;
2009 u32 cg_spll_spread_spectrum_2 = ni_pi->clock_registers.cg_spll_spread_spectrum_2;
2010 u64 tmp;
2011 u32 reference_clock = rdev->clock.spll.reference_freq;
2012 u32 reference_divider;
2013 u32 fbdiv;
2014 int ret;
2015
2016 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
2017 engine_clock, false, &dividers);
2018 if (ret)
2019 return ret;
2020
2021 reference_divider = 1 + dividers.ref_div;
2022
2023
2024 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16834;
2025 do_div(tmp, reference_clock);
2026 fbdiv = (u32) tmp;
2027
2028 spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK);
2029 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);
2030 spll_func_cntl |= SPLL_PDIV_A(dividers.post_div);
2031
2032 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
2033 spll_func_cntl_2 |= SCLK_MUX_SEL(2);
2034
2035 spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK;
2036 spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv);
2037 spll_func_cntl_3 |= SPLL_DITHEN;
2038
2039 if (pi->sclk_ss) {
2040 struct radeon_atom_ss ss;
2041 u32 vco_freq = engine_clock * dividers.post_div;
2042
2043 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
2044 ASIC_INTERNAL_ENGINE_SS, vco_freq)) {
2045 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);
2046 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);
2047
2048 cg_spll_spread_spectrum &= ~CLK_S_MASK;
2049 cg_spll_spread_spectrum |= CLK_S(clk_s);
2050 cg_spll_spread_spectrum |= SSEN;
2051
2052 cg_spll_spread_spectrum_2 &= ~CLK_V_MASK;
2053 cg_spll_spread_spectrum_2 |= CLK_V(clk_v);
2054 }
2055 }
2056
2057 sclk->sclk_value = engine_clock;
2058 sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl;
2059 sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2;
2060 sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3;
2061 sclk->vCG_SPLL_FUNC_CNTL_4 = spll_func_cntl_4;
2062 sclk->vCG_SPLL_SPREAD_SPECTRUM = cg_spll_spread_spectrum;
2063 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cg_spll_spread_spectrum_2;
2064
2065 return 0;
2066}
2067
2068static int ni_populate_sclk_value(struct radeon_device *rdev,
2069 u32 engine_clock,
2070 NISLANDS_SMC_SCLK_VALUE *sclk)
2071{
2072 NISLANDS_SMC_SCLK_VALUE sclk_tmp;
2073 int ret;
2074
2075 ret = ni_calculate_sclk_params(rdev, engine_clock, &sclk_tmp);
2076 if (!ret) {
2077 sclk->sclk_value = cpu_to_be32(sclk_tmp.sclk_value);
2078 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL);
2079 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_2);
2080 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3);
2081 sclk->vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_4);
2082 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM);
2083 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM_2);
2084 }
2085
2086 return ret;
2087}
2088
2089static int ni_init_smc_spll_table(struct radeon_device *rdev)
2090{
2091 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
2092 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2093 SMC_NISLANDS_SPLL_DIV_TABLE *spll_table;
2094 NISLANDS_SMC_SCLK_VALUE sclk_params;
2095 u32 fb_div;
2096 u32 p_div;
2097 u32 clk_s;
2098 u32 clk_v;
2099 u32 sclk = 0;
2100 int i, ret;
2101 u32 tmp;
2102
2103 if (ni_pi->spll_table_start == 0)
2104 return -EINVAL;
2105
2106 spll_table = kzalloc(sizeof(SMC_NISLANDS_SPLL_DIV_TABLE), GFP_KERNEL);
2107 if (spll_table == NULL)
2108 return -ENOMEM;
2109
2110 for (i = 0; i < 256; i++) {
2111 ret = ni_calculate_sclk_params(rdev, sclk, &sclk_params);
2112 if (ret)
2113 break;
2114
2115 p_div = (sclk_params.vCG_SPLL_FUNC_CNTL & SPLL_PDIV_A_MASK) >> SPLL_PDIV_A_SHIFT;
2116 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT;
2117 clk_s = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM & CLK_S_MASK) >> CLK_S_SHIFT;
2118 clk_v = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM_2 & CLK_V_MASK) >> CLK_V_SHIFT;
2119
2120 fb_div &= ~0x00001FFF;
2121 fb_div >>= 1;
2122 clk_v >>= 6;
2123
2124 if (p_div & ~(SMC_NISLANDS_SPLL_DIV_TABLE_PDIV_MASK >> SMC_NISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT))
2125 ret = -EINVAL;
2126
2127 if (clk_s & ~(SMC_NISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_NISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT))
2128 ret = -EINVAL;
2129
2130 if (clk_s & ~(SMC_NISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_NISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT))
2131 ret = -EINVAL;
2132
2133 if (clk_v & ~(SMC_NISLANDS_SPLL_DIV_TABLE_CLKV_MASK >> SMC_NISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT))
2134 ret = -EINVAL;
2135
2136 if (ret)
2137 break;
2138
2139 tmp = ((fb_div << SMC_NISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_NISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) |
2140 ((p_div << SMC_NISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT) & SMC_NISLANDS_SPLL_DIV_TABLE_PDIV_MASK);
2141 spll_table->freq[i] = cpu_to_be32(tmp);
2142
2143 tmp = ((clk_v << SMC_NISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT) & SMC_NISLANDS_SPLL_DIV_TABLE_CLKV_MASK) |
2144 ((clk_s << SMC_NISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT) & SMC_NISLANDS_SPLL_DIV_TABLE_CLKS_MASK);
2145 spll_table->ss[i] = cpu_to_be32(tmp);
2146
2147 sclk += 512;
2148 }
2149
2150 if (!ret)
2151 ret = rv770_copy_bytes_to_smc(rdev, ni_pi->spll_table_start, (u8 *)spll_table,
2152 sizeof(SMC_NISLANDS_SPLL_DIV_TABLE), pi->sram_end);
2153
2154 kfree(spll_table);
2155
2156 return ret;
2157}
2158
2159static int ni_populate_mclk_value(struct radeon_device *rdev,
2160 u32 engine_clock,
2161 u32 memory_clock,
2162 NISLANDS_SMC_MCLK_VALUE *mclk,
2163 bool strobe_mode,
2164 bool dll_state_on)
2165{
2166 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
2167 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2168 u32 mpll_ad_func_cntl = ni_pi->clock_registers.mpll_ad_func_cntl;
2169 u32 mpll_ad_func_cntl_2 = ni_pi->clock_registers.mpll_ad_func_cntl_2;
2170 u32 mpll_dq_func_cntl = ni_pi->clock_registers.mpll_dq_func_cntl;
2171 u32 mpll_dq_func_cntl_2 = ni_pi->clock_registers.mpll_dq_func_cntl_2;
2172 u32 mclk_pwrmgt_cntl = ni_pi->clock_registers.mclk_pwrmgt_cntl;
2173 u32 dll_cntl = ni_pi->clock_registers.dll_cntl;
2174 u32 mpll_ss1 = ni_pi->clock_registers.mpll_ss1;
2175 u32 mpll_ss2 = ni_pi->clock_registers.mpll_ss2;
2176 struct atom_clock_dividers dividers;
2177 u32 ibias;
2178 u32 dll_speed;
2179 int ret;
2180 u32 mc_seq_misc7;
2181
2182 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_MEMORY_PLL_PARAM,
2183 memory_clock, strobe_mode, &dividers);
2184 if (ret)
2185 return ret;
2186
2187 if (!strobe_mode) {
2188 mc_seq_misc7 = RREG32(MC_SEQ_MISC7);
2189
2190 if (mc_seq_misc7 & 0x8000000)
2191 dividers.post_div = 1;
2192 }
2193
2194 ibias = cypress_map_clkf_to_ibias(rdev, dividers.whole_fb_div);
2195
2196 mpll_ad_func_cntl &= ~(CLKR_MASK |
2197 YCLK_POST_DIV_MASK |
2198 CLKF_MASK |
2199 CLKFRAC_MASK |
2200 IBIAS_MASK);
2201 mpll_ad_func_cntl |= CLKR(dividers.ref_div);
2202 mpll_ad_func_cntl |= YCLK_POST_DIV(dividers.post_div);
2203 mpll_ad_func_cntl |= CLKF(dividers.whole_fb_div);
2204 mpll_ad_func_cntl |= CLKFRAC(dividers.frac_fb_div);
2205 mpll_ad_func_cntl |= IBIAS(ibias);
2206
2207 if (dividers.vco_mode)
2208 mpll_ad_func_cntl_2 |= VCO_MODE;
2209 else
2210 mpll_ad_func_cntl_2 &= ~VCO_MODE;
2211
2212 if (pi->mem_gddr5) {
2213 mpll_dq_func_cntl &= ~(CLKR_MASK |
2214 YCLK_POST_DIV_MASK |
2215 CLKF_MASK |
2216 CLKFRAC_MASK |
2217 IBIAS_MASK);
2218 mpll_dq_func_cntl |= CLKR(dividers.ref_div);
2219 mpll_dq_func_cntl |= YCLK_POST_DIV(dividers.post_div);
2220 mpll_dq_func_cntl |= CLKF(dividers.whole_fb_div);
2221 mpll_dq_func_cntl |= CLKFRAC(dividers.frac_fb_div);
2222 mpll_dq_func_cntl |= IBIAS(ibias);
2223
2224 if (strobe_mode)
2225 mpll_dq_func_cntl &= ~PDNB;
2226 else
2227 mpll_dq_func_cntl |= PDNB;
2228
2229 if (dividers.vco_mode)
2230 mpll_dq_func_cntl_2 |= VCO_MODE;
2231 else
2232 mpll_dq_func_cntl_2 &= ~VCO_MODE;
2233 }
2234
2235 if (pi->mclk_ss) {
2236 struct radeon_atom_ss ss;
2237 u32 vco_freq = memory_clock * dividers.post_div;
2238
2239 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
2240 ASIC_INTERNAL_MEMORY_SS, vco_freq)) {
2241 u32 reference_clock = rdev->clock.mpll.reference_freq;
2242 u32 decoded_ref = rv740_get_decoded_reference_divider(dividers.ref_div);
2243 u32 clk_s = reference_clock * 5 / (decoded_ref * ss.rate);
2244 u32 clk_v = ss.percentage *
2245 (0x4000 * dividers.whole_fb_div + 0x800 * dividers.frac_fb_div) / (clk_s * 625);
2246
2247 mpll_ss1 &= ~CLKV_MASK;
2248 mpll_ss1 |= CLKV(clk_v);
2249
2250 mpll_ss2 &= ~CLKS_MASK;
2251 mpll_ss2 |= CLKS(clk_s);
2252 }
2253 }
2254
2255 dll_speed = rv740_get_dll_speed(pi->mem_gddr5,
2256 memory_clock);
2257
2258 mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK;
2259 mclk_pwrmgt_cntl |= DLL_SPEED(dll_speed);
2260 if (dll_state_on)
2261 mclk_pwrmgt_cntl |= (MRDCKA0_PDNB |
2262 MRDCKA1_PDNB |
2263 MRDCKB0_PDNB |
2264 MRDCKB1_PDNB |
2265 MRDCKC0_PDNB |
2266 MRDCKC1_PDNB |
2267 MRDCKD0_PDNB |
2268 MRDCKD1_PDNB);
2269 else
2270 mclk_pwrmgt_cntl &= ~(MRDCKA0_PDNB |
2271 MRDCKA1_PDNB |
2272 MRDCKB0_PDNB |
2273 MRDCKB1_PDNB |
2274 MRDCKC0_PDNB |
2275 MRDCKC1_PDNB |
2276 MRDCKD0_PDNB |
2277 MRDCKD1_PDNB);
2278
2279
2280 mclk->mclk_value = cpu_to_be32(memory_clock);
2281 mclk->vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl);
2282 mclk->vMPLL_AD_FUNC_CNTL_2 = cpu_to_be32(mpll_ad_func_cntl_2);
2283 mclk->vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl);
2284 mclk->vMPLL_DQ_FUNC_CNTL_2 = cpu_to_be32(mpll_dq_func_cntl_2);
2285 mclk->vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl);
2286 mclk->vDLL_CNTL = cpu_to_be32(dll_cntl);
2287 mclk->vMPLL_SS = cpu_to_be32(mpll_ss1);
2288 mclk->vMPLL_SS2 = cpu_to_be32(mpll_ss2);
2289
2290 return 0;
2291}
2292
2293static void ni_populate_smc_sp(struct radeon_device *rdev,
2294 struct radeon_ps *radeon_state,
2295 NISLANDS_SMC_SWSTATE *smc_state)
2296{
2297 struct ni_ps *ps = ni_get_ps(radeon_state);
2298 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
2299 int i;
2300
2301 for (i = 0; i < ps->performance_level_count - 1; i++)
2302 smc_state->levels[i].bSP = cpu_to_be32(pi->dsp);
2303
2304 smc_state->levels[ps->performance_level_count - 1].bSP =
2305 cpu_to_be32(pi->psp);
2306}
2307
2308static int ni_convert_power_level_to_smc(struct radeon_device *rdev,
2309 struct rv7xx_pl *pl,
2310 NISLANDS_SMC_HW_PERFORMANCE_LEVEL *level)
2311{
2312 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
2313 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
2314 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2315 int ret;
2316 bool dll_state_on;
2317 u16 std_vddc;
2318 u32 tmp = RREG32(DC_STUTTER_CNTL);
2319
2320 level->gen2PCIE = pi->pcie_gen2 ?
2321 ((pl->flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2) ? 1 : 0) : 0;
2322
2323 ret = ni_populate_sclk_value(rdev, pl->sclk, &level->sclk);
2324 if (ret)
2325 return ret;
2326
2327 level->mcFlags = 0;
2328 if (pi->mclk_stutter_mode_threshold &&
2329 (pl->mclk <= pi->mclk_stutter_mode_threshold) &&
2330 !eg_pi->uvd_enabled &&
2331 (tmp & DC_STUTTER_ENABLE_A) &&
2332 (tmp & DC_STUTTER_ENABLE_B))
2333 level->mcFlags |= NISLANDS_SMC_MC_STUTTER_EN;
2334
2335 if (pi->mem_gddr5) {
2336 if (pl->mclk > pi->mclk_edc_enable_threshold)
2337 level->mcFlags |= NISLANDS_SMC_MC_EDC_RD_FLAG;
2338 if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold)
2339 level->mcFlags |= NISLANDS_SMC_MC_EDC_WR_FLAG;
2340
2341 level->strobeMode = cypress_get_strobe_mode_settings(rdev, pl->mclk);
2342
2343 if (level->strobeMode & NISLANDS_SMC_STROBE_ENABLE) {
2344 if (cypress_get_mclk_frequency_ratio(rdev, pl->mclk, true) >=
2345 ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf))
2346 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
2347 else
2348 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
2349 } else {
2350 dll_state_on = false;
2351 if (pl->mclk > ni_pi->mclk_rtt_mode_threshold)
2352 level->mcFlags |= NISLANDS_SMC_MC_RTT_ENABLE;
2353 }
2354
2355 ret = ni_populate_mclk_value(rdev, pl->sclk, pl->mclk,
2356 &level->mclk,
2357 (level->strobeMode & NISLANDS_SMC_STROBE_ENABLE) != 0,
2358 dll_state_on);
2359 } else
2360 ret = ni_populate_mclk_value(rdev, pl->sclk, pl->mclk, &level->mclk, 1, 1);
2361
2362 if (ret)
2363 return ret;
2364
2365 ret = ni_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
2366 pl->vddc, &level->vddc);
2367 if (ret)
2368 return ret;
2369
2370 ret = ni_get_std_voltage_value(rdev, &level->vddc, &std_vddc);
2371 if (ret)
2372 return ret;
2373
2374 ni_populate_std_voltage_value(rdev, std_vddc,
2375 level->vddc.index, &level->std_vddc);
2376
2377 if (eg_pi->vddci_control) {
2378 ret = ni_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table,
2379 pl->vddci, &level->vddci);
2380 if (ret)
2381 return ret;
2382 }
2383
2384 ni_populate_mvdd_value(rdev, pl->mclk, &level->mvdd);
2385
2386 return ret;
2387}
2388
2389static int ni_populate_smc_t(struct radeon_device *rdev,
2390 struct radeon_ps *radeon_state,
2391 NISLANDS_SMC_SWSTATE *smc_state)
2392{
2393 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
2394 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
2395 struct ni_ps *state = ni_get_ps(radeon_state);
2396 u32 a_t;
2397 u32 t_l, t_h;
2398 u32 high_bsp;
2399 int i, ret;
2400
2401 if (state->performance_level_count >= 9)
2402 return -EINVAL;
2403
2404 if (state->performance_level_count < 2) {
2405 a_t = CG_R(0xffff) | CG_L(0);
2406 smc_state->levels[0].aT = cpu_to_be32(a_t);
2407 return 0;
2408 }
2409
2410 smc_state->levels[0].aT = cpu_to_be32(0);
2411
2412 for (i = 0; i <= state->performance_level_count - 2; i++) {
2413 if (eg_pi->uvd_enabled)
2414 ret = r600_calculate_at(
2415 1000 * (i * (eg_pi->smu_uvd_hs ? 2 : 8) + 2),
2416 100 * R600_AH_DFLT,
2417 state->performance_levels[i + 1].sclk,
2418 state->performance_levels[i].sclk,
2419 &t_l,
2420 &t_h);
2421 else
2422 ret = r600_calculate_at(
2423 1000 * (i + 1),
2424 100 * R600_AH_DFLT,
2425 state->performance_levels[i + 1].sclk,
2426 state->performance_levels[i].sclk,
2427 &t_l,
2428 &t_h);
2429
2430 if (ret) {
2431 t_h = (i + 1) * 1000 - 50 * R600_AH_DFLT;
2432 t_l = (i + 1) * 1000 + 50 * R600_AH_DFLT;
2433 }
2434
2435 a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_R_MASK;
2436 a_t |= CG_R(t_l * pi->bsp / 20000);
2437 smc_state->levels[i].aT = cpu_to_be32(a_t);
2438
2439 high_bsp = (i == state->performance_level_count - 2) ?
2440 pi->pbsp : pi->bsp;
2441
2442 a_t = CG_R(0xffff) | CG_L(t_h * high_bsp / 20000);
2443 smc_state->levels[i + 1].aT = cpu_to_be32(a_t);
2444 }
2445
2446 return 0;
2447}
2448
2449static int ni_populate_power_containment_values(struct radeon_device *rdev,
2450 struct radeon_ps *radeon_state,
2451 NISLANDS_SMC_SWSTATE *smc_state)
2452{
2453 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
2454 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
2455 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2456 struct ni_ps *state = ni_get_ps(radeon_state);
2457 u32 prev_sclk;
2458 u32 max_sclk;
2459 u32 min_sclk;
2460 int i, ret;
2461 u32 tdp_limit;
2462 u32 near_tdp_limit;
2463 u32 power_boost_limit;
2464 u8 max_ps_percent;
2465
2466 if (ni_pi->enable_power_containment == false)
2467 return 0;
2468
2469 if (state->performance_level_count == 0)
2470 return -EINVAL;
2471
2472 if (smc_state->levelCount != state->performance_level_count)
2473 return -EINVAL;
2474
2475 ret = ni_calculate_adjusted_tdp_limits(rdev,
2476 false, /* ??? */
2477 rdev->pm.dpm.tdp_adjustment,
2478 &tdp_limit,
2479 &near_tdp_limit);
2480 if (ret)
2481 return ret;
2482
2483 power_boost_limit = ni_calculate_power_boost_limit(rdev, radeon_state, near_tdp_limit);
2484
2485 ret = rv770_write_smc_sram_dword(rdev,
2486 pi->state_table_start +
2487 offsetof(NISLANDS_SMC_STATETABLE, dpm2Params) +
2488 offsetof(PP_NIslands_DPM2Parameters, PowerBoostLimit),
2489 ni_scale_power_for_smc(power_boost_limit, ni_get_smc_power_scaling_factor(rdev)),
2490 pi->sram_end);
2491 if (ret)
2492 power_boost_limit = 0;
2493
2494 smc_state->levels[0].dpm2.MaxPS = 0;
2495 smc_state->levels[0].dpm2.NearTDPDec = 0;
2496 smc_state->levels[0].dpm2.AboveSafeInc = 0;
2497 smc_state->levels[0].dpm2.BelowSafeInc = 0;
2498 smc_state->levels[0].stateFlags |= power_boost_limit ? PPSMC_STATEFLAG_POWERBOOST : 0;
2499
2500 for (i = 1; i < state->performance_level_count; i++) {
2501 prev_sclk = state->performance_levels[i-1].sclk;
2502 max_sclk = state->performance_levels[i].sclk;
2503 max_ps_percent = (i != (state->performance_level_count - 1)) ?
2504 NISLANDS_DPM2_MAXPS_PERCENT_M : NISLANDS_DPM2_MAXPS_PERCENT_H;
2505
2506 if (max_sclk < prev_sclk)
2507 return -EINVAL;
2508
2509 if ((max_ps_percent == 0) || (prev_sclk == max_sclk) || eg_pi->uvd_enabled)
2510 min_sclk = max_sclk;
2511 else if (1 == i)
2512 min_sclk = prev_sclk;
2513 else
2514 min_sclk = (prev_sclk * (u32)max_ps_percent) / 100;
2515
2516 if (min_sclk < state->performance_levels[0].sclk)
2517 min_sclk = state->performance_levels[0].sclk;
2518
2519 if (min_sclk == 0)
2520 return -EINVAL;
2521
2522 smc_state->levels[i].dpm2.MaxPS =
2523 (u8)((NISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk);
2524 smc_state->levels[i].dpm2.NearTDPDec = NISLANDS_DPM2_NEAR_TDP_DEC;
2525 smc_state->levels[i].dpm2.AboveSafeInc = NISLANDS_DPM2_ABOVE_SAFE_INC;
2526 smc_state->levels[i].dpm2.BelowSafeInc = NISLANDS_DPM2_BELOW_SAFE_INC;
2527 smc_state->levels[i].stateFlags |=
2528 ((i != (state->performance_level_count - 1)) && power_boost_limit) ?
2529 PPSMC_STATEFLAG_POWERBOOST : 0;
2530 }
2531
2532 return 0;
2533}
2534
2535static int ni_populate_sq_ramping_values(struct radeon_device *rdev,
2536 struct radeon_ps *radeon_state,
2537 NISLANDS_SMC_SWSTATE *smc_state)
2538{
2539 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2540 struct ni_ps *state = ni_get_ps(radeon_state);
2541 u32 sq_power_throttle;
2542 u32 sq_power_throttle2;
2543 bool enable_sq_ramping = ni_pi->enable_sq_ramping;
2544 int i;
2545
2546 if (state->performance_level_count == 0)
2547 return -EINVAL;
2548
2549 if (smc_state->levelCount != state->performance_level_count)
2550 return -EINVAL;
2551
2552 if (rdev->pm.dpm.sq_ramping_threshold == 0)
2553 return -EINVAL;
2554
2555 if (NISLANDS_DPM2_SQ_RAMP_MAX_POWER > (MAX_POWER_MASK >> MAX_POWER_SHIFT))
2556 enable_sq_ramping = false;
2557
2558 if (NISLANDS_DPM2_SQ_RAMP_MIN_POWER > (MIN_POWER_MASK >> MIN_POWER_SHIFT))
2559 enable_sq_ramping = false;
2560
2561 if (NISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA > (MAX_POWER_DELTA_MASK >> MAX_POWER_DELTA_SHIFT))
2562 enable_sq_ramping = false;
2563
2564 if (NISLANDS_DPM2_SQ_RAMP_STI_SIZE > (STI_SIZE_MASK >> STI_SIZE_SHIFT))
2565 enable_sq_ramping = false;
2566
2567 if (NISLANDS_DPM2_SQ_RAMP_LTI_RATIO <= (LTI_RATIO_MASK >> LTI_RATIO_SHIFT))
2568 enable_sq_ramping = false;
2569
2570 for (i = 0; i < state->performance_level_count; i++) {
2571 sq_power_throttle = 0;
2572 sq_power_throttle2 = 0;
2573
2574 if ((state->performance_levels[i].sclk >= rdev->pm.dpm.sq_ramping_threshold) &&
2575 enable_sq_ramping) {
2576 sq_power_throttle |= MAX_POWER(NISLANDS_DPM2_SQ_RAMP_MAX_POWER);
2577 sq_power_throttle |= MIN_POWER(NISLANDS_DPM2_SQ_RAMP_MIN_POWER);
2578 sq_power_throttle2 |= MAX_POWER_DELTA(NISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA);
2579 sq_power_throttle2 |= STI_SIZE(NISLANDS_DPM2_SQ_RAMP_STI_SIZE);
2580 sq_power_throttle2 |= LTI_RATIO(NISLANDS_DPM2_SQ_RAMP_LTI_RATIO);
2581 } else {
2582 sq_power_throttle |= MAX_POWER_MASK | MIN_POWER_MASK;
2583 sq_power_throttle2 |= MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
2584 }
2585
2586 smc_state->levels[i].SQPowerThrottle = cpu_to_be32(sq_power_throttle);
2587 smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2);
2588 }
2589
2590 return 0;
2591}
2592
2593static int ni_enable_power_containment(struct radeon_device *rdev, bool enable)
2594{
2595 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2596 PPSMC_Result smc_result;
2597 int ret = 0;
2598
2599 if (ni_pi->enable_power_containment) {
2600 if (enable) {
2601 struct radeon_ps *radeon_new_state = rdev->pm.dpm.requested_ps;
2602
2603 if (!r600_is_uvd_state(radeon_new_state->class, radeon_new_state->class2)) {
2604 smc_result = rv770_send_msg_to_smc(rdev, PPSMC_TDPClampingActive);
2605 if (smc_result != PPSMC_Result_OK) {
2606 ret = -EINVAL;
2607 ni_pi->pc_enabled = false;
2608 } else {
2609 ni_pi->pc_enabled = true;
2610 }
2611 }
2612 } else {
2613 smc_result = rv770_send_msg_to_smc(rdev, PPSMC_TDPClampingInactive);
2614 if (smc_result != PPSMC_Result_OK)
2615 ret = -EINVAL;
2616 ni_pi->pc_enabled = false;
2617 }
2618 }
2619
2620 return ret;
2621}
2622
2623static int ni_convert_power_state_to_smc(struct radeon_device *rdev,
2624 struct radeon_ps *radeon_state,
2625 NISLANDS_SMC_SWSTATE *smc_state)
2626{
2627 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
2628 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2629 struct ni_ps *state = ni_get_ps(radeon_state);
2630 int i, ret;
2631 u32 threshold = state->performance_levels[state->performance_level_count - 1].sclk * 100 / 100;
2632
2633 if (!(radeon_state->caps & ATOM_PPLIB_DISALLOW_ON_DC))
2634 smc_state->flags |= PPSMC_SWSTATE_FLAG_DC;
2635
2636 smc_state->levelCount = 0;
2637
2638 if (state->performance_level_count > NISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE)
2639 return -EINVAL;
2640
2641 for (i = 0; i < state->performance_level_count; i++) {
2642 ret = ni_convert_power_level_to_smc(rdev, &state->performance_levels[i],
2643 &smc_state->levels[i]);
2644 smc_state->levels[i].arbRefreshState =
2645 (u8)(NISLANDS_DRIVER_STATE_ARB_INDEX + i);
2646
2647 if (ret)
2648 return ret;
2649
2650 if (ni_pi->enable_power_containment)
2651 smc_state->levels[i].displayWatermark =
2652 (state->performance_levels[i].sclk < threshold) ?
2653 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
2654 else
2655 smc_state->levels[i].displayWatermark = (i < 2) ?
2656 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
2657
2658 if (eg_pi->dynamic_ac_timing)
2659 smc_state->levels[i].ACIndex = NISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i;
2660 else
2661 smc_state->levels[i].ACIndex = 0;
2662
2663 smc_state->levelCount++;
2664 }
2665
2666 rv770_write_smc_soft_register(rdev, NI_SMC_SOFT_REGISTER_watermark_threshold,
2667 cpu_to_be32(threshold / 512));
2668
2669 ni_populate_smc_sp(rdev, radeon_state, smc_state);
2670
2671 ret = ni_populate_power_containment_values(rdev, radeon_state, smc_state);
2672 if (ret)
2673 ni_pi->enable_power_containment = false;
2674
2675 ret = ni_populate_sq_ramping_values(rdev, radeon_state, smc_state);
2676 if (ret)
2677 ni_pi->enable_sq_ramping = false;
2678
2679 return ni_populate_smc_t(rdev, radeon_state, smc_state);
2680}
2681
2682static int ni_upload_sw_state(struct radeon_device *rdev)
2683{
2684 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
2685 struct radeon_ps *radeon_new_state = rdev->pm.dpm.requested_ps;
2686 u16 address = pi->state_table_start +
2687 offsetof(NISLANDS_SMC_STATETABLE, driverState);
2688 u16 state_size = sizeof(NISLANDS_SMC_SWSTATE) +
2689 ((NISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE - 1) * sizeof(NISLANDS_SMC_HW_PERFORMANCE_LEVEL));
2690 int ret;
2691 NISLANDS_SMC_SWSTATE *smc_state = kzalloc(state_size, GFP_KERNEL);
2692
2693 if (smc_state == NULL)
2694 return -ENOMEM;
2695
2696 ret = ni_convert_power_state_to_smc(rdev, radeon_new_state, smc_state);
2697 if (ret)
2698 goto done;
2699
2700 ret = rv770_copy_bytes_to_smc(rdev, address, (u8 *)smc_state, state_size, pi->sram_end);
2701
2702done:
2703 kfree(smc_state);
2704
2705 return ret;
2706}
2707
2708static int ni_set_mc_special_registers(struct radeon_device *rdev,
2709 struct ni_mc_reg_table *table)
2710{
2711 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
2712 u8 i, j, k;
2713 u32 temp_reg;
2714
2715 for (i = 0, j = table->last; i < table->last; i++) {
2716 switch (table->mc_reg_address[i].s1) {
2717 case MC_SEQ_MISC1 >> 2:
2718 if (j >= SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE)
2719 return -EINVAL;
2720 temp_reg = RREG32(MC_PMG_CMD_EMRS);
2721 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2;
2722 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
2723 for (k = 0; k < table->num_entries; k++)
2724 table->mc_reg_table_entry[k].mc_data[j] =
2725 ((temp_reg & 0xffff0000)) |
2726 ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
2727 j++;
2728 if (j >= SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE)
2729 return -EINVAL;
2730
2731 temp_reg = RREG32(MC_PMG_CMD_MRS);
2732 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2;
2733 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2;
2734 for(k = 0; k < table->num_entries; k++) {
2735 table->mc_reg_table_entry[k].mc_data[j] =
2736 (temp_reg & 0xffff0000) |
2737 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
2738 if (!pi->mem_gddr5)
2739 table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
2740 }
2741 j++;
2742 if (j > SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE)
2743 return -EINVAL;
2744 break;
2745 case MC_SEQ_RESERVE_M >> 2:
2746 temp_reg = RREG32(MC_PMG_CMD_MRS1);
2747 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2;
2748 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
2749 for (k = 0; k < table->num_entries; k++)
2750 table->mc_reg_table_entry[k].mc_data[j] =
2751 (temp_reg & 0xffff0000) |
2752 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
2753 j++;
2754 if (j > SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE)
2755 return -EINVAL;
2756 break;
2757 default:
2758 break;
2759 }
2760 }
2761
2762 table->last = j;
2763
2764 return 0;
2765}
2766
2767static bool ni_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg)
2768{
2769 bool result = true;
2770
2771 switch (in_reg) {
2772 case MC_SEQ_RAS_TIMING >> 2:
2773 *out_reg = MC_SEQ_RAS_TIMING_LP >> 2;
2774 break;
2775 case MC_SEQ_CAS_TIMING >> 2:
2776 *out_reg = MC_SEQ_CAS_TIMING_LP >> 2;
2777 break;
2778 case MC_SEQ_MISC_TIMING >> 2:
2779 *out_reg = MC_SEQ_MISC_TIMING_LP >> 2;
2780 break;
2781 case MC_SEQ_MISC_TIMING2 >> 2:
2782 *out_reg = MC_SEQ_MISC_TIMING2_LP >> 2;
2783 break;
2784 case MC_SEQ_RD_CTL_D0 >> 2:
2785 *out_reg = MC_SEQ_RD_CTL_D0_LP >> 2;
2786 break;
2787 case MC_SEQ_RD_CTL_D1 >> 2:
2788 *out_reg = MC_SEQ_RD_CTL_D1_LP >> 2;
2789 break;
2790 case MC_SEQ_WR_CTL_D0 >> 2:
2791 *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2;
2792 break;
2793 case MC_SEQ_WR_CTL_D1 >> 2:
2794 *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2;
2795 break;
2796 case MC_PMG_CMD_EMRS >> 2:
2797 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
2798 break;
2799 case MC_PMG_CMD_MRS >> 2:
2800 *out_reg = MC_SEQ_PMG_CMD_MRS_LP >> 2;
2801 break;
2802 case MC_PMG_CMD_MRS1 >> 2:
2803 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
2804 break;
2805 case MC_SEQ_PMG_TIMING >> 2:
2806 *out_reg = MC_SEQ_PMG_TIMING_LP >> 2;
2807 break;
2808 case MC_PMG_CMD_MRS2 >> 2:
2809 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP >> 2;
2810 break;
2811 default:
2812 result = false;
2813 break;
2814 }
2815
2816 return result;
2817}
2818
2819static void ni_set_valid_flag(struct ni_mc_reg_table *table)
2820{
2821 u8 i, j;
2822
2823 for (i = 0; i < table->last; i++) {
2824 for (j = 1; j < table->num_entries; j++) {
2825 if (table->mc_reg_table_entry[j-1].mc_data[i] != table->mc_reg_table_entry[j].mc_data[i]) {
2826 table->valid_flag |= 1 << i;
2827 break;
2828 }
2829 }
2830 }
2831}
2832
2833static void ni_set_s0_mc_reg_index(struct ni_mc_reg_table *table)
2834{
2835 u32 i;
2836 u16 address;
2837
2838 for (i = 0; i < table->last; i++)
2839 table->mc_reg_address[i].s0 =
2840 ni_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ?
2841 address : table->mc_reg_address[i].s1;
2842}
2843
2844static int ni_copy_vbios_mc_reg_table(struct atom_mc_reg_table *table,
2845 struct ni_mc_reg_table *ni_table)
2846{
2847 u8 i, j;
2848
2849 if (table->last > SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE)
2850 return -EINVAL;
2851 if (table->num_entries > MAX_AC_TIMING_ENTRIES)
2852 return -EINVAL;
2853
2854 for (i = 0; i < table->last; i++)
2855 ni_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
2856 ni_table->last = table->last;
2857
2858 for (i = 0; i < table->num_entries; i++) {
2859 ni_table->mc_reg_table_entry[i].mclk_max =
2860 table->mc_reg_table_entry[i].mclk_max;
2861 for (j = 0; j < table->last; j++)
2862 ni_table->mc_reg_table_entry[i].mc_data[j] =
2863 table->mc_reg_table_entry[i].mc_data[j];
2864 }
2865 ni_table->num_entries = table->num_entries;
2866
2867 return 0;
2868}
2869
2870static int ni_initialize_mc_reg_table(struct radeon_device *rdev)
2871{
2872 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2873 int ret;
2874 struct atom_mc_reg_table *table;
2875 struct ni_mc_reg_table *ni_table = &ni_pi->mc_reg_table;
2876 u8 module_index = rv770_get_memory_module_index(rdev);
2877
2878 table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL);
2879 if (!table)
2880 return -ENOMEM;
2881
2882 WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));
2883 WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));
2884 WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));
2885 WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));
2886 WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS));
2887 WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS));
2888 WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));
2889 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));
2890 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
2891 WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));
2892 WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));
2893 WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING));
2894 WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2));
2895
2896 ret = radeon_atom_init_mc_reg_table(rdev, module_index, table);
2897
2898 if (ret)
2899 goto init_mc_done;
2900
2901 ret = ni_copy_vbios_mc_reg_table(table, ni_table);
2902
2903 if (ret)
2904 goto init_mc_done;
2905
2906 ni_set_s0_mc_reg_index(ni_table);
2907
2908 ret = ni_set_mc_special_registers(rdev, ni_table);
2909
2910 if (ret)
2911 goto init_mc_done;
2912
2913 ni_set_valid_flag(ni_table);
2914
2915init_mc_done:
2916 kfree(table);
2917
2918 return ret;
2919}
2920
2921static void ni_populate_mc_reg_addresses(struct radeon_device *rdev,
2922 SMC_NIslands_MCRegisters *mc_reg_table)
2923{
2924 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2925 u32 i, j;
2926
2927 for (i = 0, j = 0; j < ni_pi->mc_reg_table.last; j++) {
2928 if (ni_pi->mc_reg_table.valid_flag & (1 << j)) {
2929 if (i >= SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE)
2930 break;
2931 mc_reg_table->address[i].s0 =
2932 cpu_to_be16(ni_pi->mc_reg_table.mc_reg_address[j].s0);
2933 mc_reg_table->address[i].s1 =
2934 cpu_to_be16(ni_pi->mc_reg_table.mc_reg_address[j].s1);
2935 i++;
2936 }
2937 }
2938 mc_reg_table->last = (u8)i;
2939}
2940
2941
2942static void ni_convert_mc_registers(struct ni_mc_reg_entry *entry,
2943 SMC_NIslands_MCRegisterSet *data,
2944 u32 num_entries, u32 valid_flag)
2945{
2946 u32 i, j;
2947
2948 for (i = 0, j = 0; j < num_entries; j++) {
2949 if (valid_flag & (1 << j)) {
2950 data->value[i] = cpu_to_be32(entry->mc_data[j]);
2951 i++;
2952 }
2953 }
2954}
2955
2956static void ni_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev,
2957 struct rv7xx_pl *pl,
2958 SMC_NIslands_MCRegisterSet *mc_reg_table_data)
2959{
2960 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2961 u32 i = 0;
2962
2963 for (i = 0; i < ni_pi->mc_reg_table.num_entries; i++) {
2964 if (pl->mclk <= ni_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max)
2965 break;
2966 }
2967
2968 if ((i == ni_pi->mc_reg_table.num_entries) && (i > 0))
2969 --i;
2970
2971 ni_convert_mc_registers(&ni_pi->mc_reg_table.mc_reg_table_entry[i],
2972 mc_reg_table_data,
2973 ni_pi->mc_reg_table.last,
2974 ni_pi->mc_reg_table.valid_flag);
2975}
2976
2977static void ni_convert_mc_reg_table_to_smc(struct radeon_device *rdev,
2978 struct radeon_ps *radeon_state,
2979 SMC_NIslands_MCRegisters *mc_reg_table)
2980{
2981 struct ni_ps *state = ni_get_ps(radeon_state);
2982 int i;
2983
2984 for (i = 0; i < state->performance_level_count; i++) {
2985 ni_convert_mc_reg_table_entry_to_smc(rdev,
2986 &state->performance_levels[i],
2987 &mc_reg_table->data[NISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i]);
2988 }
2989}
2990
2991static int ni_populate_mc_reg_table(struct radeon_device *rdev)
2992{
2993 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
2994 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
2995 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2996 struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps;
2997 struct ni_ps *boot_state = ni_get_ps(radeon_boot_state);
2998 SMC_NIslands_MCRegisters *mc_reg_table = &ni_pi->smc_mc_reg_table;
2999
3000 memset(mc_reg_table, 0, sizeof(SMC_NIslands_MCRegisters));
3001
3002 rv770_write_smc_soft_register(rdev, NI_SMC_SOFT_REGISTER_seq_index, 1);
3003
3004 ni_populate_mc_reg_addresses(rdev, mc_reg_table);
3005
3006 ni_convert_mc_reg_table_entry_to_smc(rdev, &boot_state->performance_levels[0],
3007 &mc_reg_table->data[0]);
3008
3009 ni_convert_mc_registers(&ni_pi->mc_reg_table.mc_reg_table_entry[0],
3010 &mc_reg_table->data[1],
3011 ni_pi->mc_reg_table.last,
3012 ni_pi->mc_reg_table.valid_flag);
3013
3014 ni_convert_mc_reg_table_to_smc(rdev, radeon_boot_state, mc_reg_table);
3015
3016 return rv770_copy_bytes_to_smc(rdev, eg_pi->mc_reg_table_start,
3017 (u8 *)mc_reg_table,
3018 sizeof(SMC_NIslands_MCRegisters),
3019 pi->sram_end);
3020}
3021
3022static int ni_upload_mc_reg_table(struct radeon_device *rdev)
3023{
3024 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3025 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3026 struct ni_power_info *ni_pi = ni_get_pi(rdev);
3027 struct radeon_ps *radeon_new_state = rdev->pm.dpm.requested_ps;
3028 struct ni_ps *ni_new_state = ni_get_ps(radeon_new_state);
3029 SMC_NIslands_MCRegisters *mc_reg_table = &ni_pi->smc_mc_reg_table;
3030 u16 address;
3031
3032 memset(mc_reg_table, 0, sizeof(SMC_NIslands_MCRegisters));
3033
3034 ni_convert_mc_reg_table_to_smc(rdev, radeon_new_state, mc_reg_table);
3035
3036 address = eg_pi->mc_reg_table_start +
3037 (u16)offsetof(SMC_NIslands_MCRegisters, data[NISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT]);
3038
3039 return rv770_copy_bytes_to_smc(rdev, address,
3040 (u8 *)&mc_reg_table->data[NISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT],
3041 sizeof(SMC_NIslands_MCRegisterSet) * ni_new_state->performance_level_count,
3042 pi->sram_end);
3043}
3044
3045static int ni_init_driver_calculated_leakage_table(struct radeon_device *rdev,
3046 PP_NIslands_CACTABLES *cac_tables)
3047{
3048 struct ni_power_info *ni_pi = ni_get_pi(rdev);
3049 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3050 u32 leakage = 0;
3051 unsigned int i, j, table_size;
3052 s32 t;
3053 u32 smc_leakage, max_leakage = 0;
3054 u32 scaling_factor;
3055
3056 table_size = eg_pi->vddc_voltage_table.count;
3057
3058 if (SMC_NISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES < table_size)
3059 table_size = SMC_NISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES;
3060
3061 scaling_factor = ni_get_smc_power_scaling_factor(rdev);
3062
3063 for (i = 0; i < SMC_NISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES; i++) {
3064 for (j = 0; j < table_size; j++) {
3065 t = (1000 * ((i + 1) * 8));
3066
3067 if (t < ni_pi->cac_data.leakage_minimum_temperature)
3068 t = ni_pi->cac_data.leakage_minimum_temperature;
3069
3070 ni_calculate_leakage_for_v_and_t(rdev,
3071 &ni_pi->cac_data.leakage_coefficients,
3072 eg_pi->vddc_voltage_table.entries[j].value,
3073 t,
3074 ni_pi->cac_data.i_leakage,
3075 &leakage);
3076
3077 smc_leakage = ni_scale_power_for_smc(leakage, scaling_factor) / 1000;
3078 if (smc_leakage > max_leakage)
3079 max_leakage = smc_leakage;
3080
3081 cac_tables->cac_lkge_lut[i][j] = cpu_to_be32(smc_leakage);
3082 }
3083 }
3084
3085 for (j = table_size; j < SMC_NISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
3086 for (i = 0; i < SMC_NISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES; i++)
3087 cac_tables->cac_lkge_lut[i][j] = cpu_to_be32(max_leakage);
3088 }
3089 return 0;
3090}
3091
3092static int ni_init_simplified_leakage_table(struct radeon_device *rdev,
3093 PP_NIslands_CACTABLES *cac_tables)
3094{
3095 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3096 struct radeon_cac_leakage_table *leakage_table =
3097 &rdev->pm.dpm.dyn_state.cac_leakage_table;
3098 u32 i, j, table_size;
3099 u32 smc_leakage, max_leakage = 0;
3100 u32 scaling_factor;
3101
3102 if (!leakage_table)
3103 return -EINVAL;
3104
3105 table_size = leakage_table->count;
3106
3107 if (eg_pi->vddc_voltage_table.count != table_size)
3108 table_size = (eg_pi->vddc_voltage_table.count < leakage_table->count) ?
3109 eg_pi->vddc_voltage_table.count : leakage_table->count;
3110
3111 if (SMC_NISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES < table_size)
3112 table_size = SMC_NISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES;
3113
3114 if (table_size == 0)
3115 return -EINVAL;
3116
3117 scaling_factor = ni_get_smc_power_scaling_factor(rdev);
3118
3119 for (j = 0; j < table_size; j++) {
3120 smc_leakage = leakage_table->entries[j].leakage;
3121
3122 if (smc_leakage > max_leakage)
3123 max_leakage = smc_leakage;
3124
3125 for (i = 0; i < SMC_NISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES; i++)
3126 cac_tables->cac_lkge_lut[i][j] =
3127 cpu_to_be32(ni_scale_power_for_smc(smc_leakage, scaling_factor));
3128 }
3129
3130 for (j = table_size; j < SMC_NISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
3131 for (i = 0; i < SMC_NISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES; i++)
3132 cac_tables->cac_lkge_lut[i][j] =
3133 cpu_to_be32(ni_scale_power_for_smc(max_leakage, scaling_factor));
3134 }
3135 return 0;
3136}
3137
3138static int ni_initialize_smc_cac_tables(struct radeon_device *rdev)
3139{
3140 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3141 struct ni_power_info *ni_pi = ni_get_pi(rdev);
3142 PP_NIslands_CACTABLES *cac_tables = NULL;
3143 int i, ret;
3144 u32 reg;
3145
3146 if (ni_pi->enable_cac == false)
3147 return 0;
3148
3149 cac_tables = kzalloc(sizeof(PP_NIslands_CACTABLES), GFP_KERNEL);
3150 if (!cac_tables)
3151 return -ENOMEM;
3152
3153 reg = RREG32(CG_CAC_CTRL) & ~(TID_CNT_MASK | TID_UNIT_MASK);
3154 reg |= (TID_CNT(ni_pi->cac_weights->tid_cnt) |
3155 TID_UNIT(ni_pi->cac_weights->tid_unit));
3156 WREG32(CG_CAC_CTRL, reg);
3157
3158 for (i = 0; i < NISLANDS_DCCAC_MAX_LEVELS; i++)
3159 ni_pi->dc_cac_table[i] = ni_pi->cac_weights->dc_cac[i];
3160
3161 for (i = 0; i < SMC_NISLANDS_BIF_LUT_NUM_OF_ENTRIES; i++)
3162 cac_tables->cac_bif_lut[i] = ni_pi->cac_weights->pcie_cac[i];
3163
3164 ni_pi->cac_data.i_leakage = rdev->pm.dpm.cac_leakage;
3165 ni_pi->cac_data.pwr_const = 0;
3166 ni_pi->cac_data.dc_cac_value = ni_pi->dc_cac_table[NISLANDS_DCCAC_LEVEL_0];
3167 ni_pi->cac_data.bif_cac_value = 0;
3168 ni_pi->cac_data.mc_wr_weight = ni_pi->cac_weights->mc_write_weight;
3169 ni_pi->cac_data.mc_rd_weight = ni_pi->cac_weights->mc_read_weight;
3170 ni_pi->cac_data.allow_ovrflw = 0;
3171 ni_pi->cac_data.l2num_win_tdp = ni_pi->lta_window_size;
3172 ni_pi->cac_data.num_win_tdp = 0;
3173 ni_pi->cac_data.lts_truncate_n = ni_pi->lts_truncate;
3174
3175 if (ni_pi->driver_calculate_cac_leakage)
3176 ret = ni_init_driver_calculated_leakage_table(rdev, cac_tables);
3177 else
3178 ret = ni_init_simplified_leakage_table(rdev, cac_tables);
3179
3180 if (ret)
3181 goto done_free;
3182
3183 cac_tables->pwr_const = cpu_to_be32(ni_pi->cac_data.pwr_const);
3184 cac_tables->dc_cacValue = cpu_to_be32(ni_pi->cac_data.dc_cac_value);
3185 cac_tables->bif_cacValue = cpu_to_be32(ni_pi->cac_data.bif_cac_value);
3186 cac_tables->AllowOvrflw = ni_pi->cac_data.allow_ovrflw;
3187 cac_tables->MCWrWeight = ni_pi->cac_data.mc_wr_weight;
3188 cac_tables->MCRdWeight = ni_pi->cac_data.mc_rd_weight;
3189 cac_tables->numWin_TDP = ni_pi->cac_data.num_win_tdp;
3190 cac_tables->l2numWin_TDP = ni_pi->cac_data.l2num_win_tdp;
3191 cac_tables->lts_truncate_n = ni_pi->cac_data.lts_truncate_n;
3192
3193 ret = rv770_copy_bytes_to_smc(rdev, ni_pi->cac_table_start, (u8 *)cac_tables,
3194 sizeof(PP_NIslands_CACTABLES), pi->sram_end);
3195
3196done_free:
3197 if (ret) {
3198 ni_pi->enable_cac = false;
3199 ni_pi->enable_power_containment = false;
3200 }
3201
3202 kfree(cac_tables);
3203
3204 return 0;
3205}
3206
3207static int ni_initialize_hardware_cac_manager(struct radeon_device *rdev)
3208{
3209 struct ni_power_info *ni_pi = ni_get_pi(rdev);
3210 u32 reg;
3211
3212 if (!ni_pi->enable_cac ||
3213 !ni_pi->cac_configuration_required)
3214 return 0;
3215
3216 if (ni_pi->cac_weights == NULL)
3217 return -EINVAL;
3218
3219 reg = RREG32_CG(CG_CAC_REGION_1_WEIGHT_0) & ~(WEIGHT_TCP_SIG0_MASK |
3220 WEIGHT_TCP_SIG1_MASK |
3221 WEIGHT_TA_SIG_MASK);
3222 reg |= (WEIGHT_TCP_SIG0(ni_pi->cac_weights->weight_tcp_sig0) |
3223 WEIGHT_TCP_SIG1(ni_pi->cac_weights->weight_tcp_sig1) |
3224 WEIGHT_TA_SIG(ni_pi->cac_weights->weight_ta_sig));
3225 WREG32_CG(CG_CAC_REGION_1_WEIGHT_0, reg);
3226
3227 reg = RREG32_CG(CG_CAC_REGION_1_WEIGHT_1) & ~(WEIGHT_TCC_EN0_MASK |
3228 WEIGHT_TCC_EN1_MASK |
3229 WEIGHT_TCC_EN2_MASK);
3230 reg |= (WEIGHT_TCC_EN0(ni_pi->cac_weights->weight_tcc_en0) |
3231 WEIGHT_TCC_EN1(ni_pi->cac_weights->weight_tcc_en1) |
3232 WEIGHT_TCC_EN2(ni_pi->cac_weights->weight_tcc_en2));
3233 WREG32_CG(CG_CAC_REGION_1_WEIGHT_1, reg);
3234
3235 reg = RREG32_CG(CG_CAC_REGION_2_WEIGHT_0) & ~(WEIGHT_CB_EN0_MASK |
3236 WEIGHT_CB_EN1_MASK |
3237 WEIGHT_CB_EN2_MASK |
3238 WEIGHT_CB_EN3_MASK);
3239 reg |= (WEIGHT_CB_EN0(ni_pi->cac_weights->weight_cb_en0) |
3240 WEIGHT_CB_EN1(ni_pi->cac_weights->weight_cb_en1) |
3241 WEIGHT_CB_EN2(ni_pi->cac_weights->weight_cb_en2) |
3242 WEIGHT_CB_EN3(ni_pi->cac_weights->weight_cb_en3));
3243 WREG32_CG(CG_CAC_REGION_2_WEIGHT_0, reg);
3244
3245 reg = RREG32_CG(CG_CAC_REGION_2_WEIGHT_1) & ~(WEIGHT_DB_SIG0_MASK |
3246 WEIGHT_DB_SIG1_MASK |
3247 WEIGHT_DB_SIG2_MASK |
3248 WEIGHT_DB_SIG3_MASK);
3249 reg |= (WEIGHT_DB_SIG0(ni_pi->cac_weights->weight_db_sig0) |
3250 WEIGHT_DB_SIG1(ni_pi->cac_weights->weight_db_sig1) |
3251 WEIGHT_DB_SIG2(ni_pi->cac_weights->weight_db_sig2) |
3252 WEIGHT_DB_SIG3(ni_pi->cac_weights->weight_db_sig3));
3253 WREG32_CG(CG_CAC_REGION_2_WEIGHT_1, reg);
3254
3255 reg = RREG32_CG(CG_CAC_REGION_2_WEIGHT_2) & ~(WEIGHT_SXM_SIG0_MASK |
3256 WEIGHT_SXM_SIG1_MASK |
3257 WEIGHT_SXM_SIG2_MASK |
3258 WEIGHT_SXS_SIG0_MASK |
3259 WEIGHT_SXS_SIG1_MASK);
3260 reg |= (WEIGHT_SXM_SIG0(ni_pi->cac_weights->weight_sxm_sig0) |
3261 WEIGHT_SXM_SIG1(ni_pi->cac_weights->weight_sxm_sig1) |
3262 WEIGHT_SXM_SIG2(ni_pi->cac_weights->weight_sxm_sig2) |
3263 WEIGHT_SXS_SIG0(ni_pi->cac_weights->weight_sxs_sig0) |
3264 WEIGHT_SXS_SIG1(ni_pi->cac_weights->weight_sxs_sig1));
3265 WREG32_CG(CG_CAC_REGION_2_WEIGHT_2, reg);
3266
3267 reg = RREG32_CG(CG_CAC_REGION_3_WEIGHT_0) & ~(WEIGHT_XBR_0_MASK |
3268 WEIGHT_XBR_1_MASK |
3269 WEIGHT_XBR_2_MASK |
3270 WEIGHT_SPI_SIG0_MASK);
3271 reg |= (WEIGHT_XBR_0(ni_pi->cac_weights->weight_xbr_0) |
3272 WEIGHT_XBR_1(ni_pi->cac_weights->weight_xbr_1) |
3273 WEIGHT_XBR_2(ni_pi->cac_weights->weight_xbr_2) |
3274 WEIGHT_SPI_SIG0(ni_pi->cac_weights->weight_spi_sig0));
3275 WREG32_CG(CG_CAC_REGION_3_WEIGHT_0, reg);
3276
3277 reg = RREG32_CG(CG_CAC_REGION_3_WEIGHT_1) & ~(WEIGHT_SPI_SIG1_MASK |
3278 WEIGHT_SPI_SIG2_MASK |
3279 WEIGHT_SPI_SIG3_MASK |
3280 WEIGHT_SPI_SIG4_MASK |
3281 WEIGHT_SPI_SIG5_MASK);
3282 reg |= (WEIGHT_SPI_SIG1(ni_pi->cac_weights->weight_spi_sig1) |
3283 WEIGHT_SPI_SIG2(ni_pi->cac_weights->weight_spi_sig2) |
3284 WEIGHT_SPI_SIG3(ni_pi->cac_weights->weight_spi_sig3) |
3285 WEIGHT_SPI_SIG4(ni_pi->cac_weights->weight_spi_sig4) |
3286 WEIGHT_SPI_SIG5(ni_pi->cac_weights->weight_spi_sig5));
3287 WREG32_CG(CG_CAC_REGION_3_WEIGHT_1, reg);
3288
3289 reg = RREG32_CG(CG_CAC_REGION_4_WEIGHT_0) & ~(WEIGHT_LDS_SIG0_MASK |
3290 WEIGHT_LDS_SIG1_MASK |
3291 WEIGHT_SC_MASK);
3292 reg |= (WEIGHT_LDS_SIG0(ni_pi->cac_weights->weight_lds_sig0) |
3293 WEIGHT_LDS_SIG1(ni_pi->cac_weights->weight_lds_sig1) |
3294 WEIGHT_SC(ni_pi->cac_weights->weight_sc));
3295 WREG32_CG(CG_CAC_REGION_4_WEIGHT_0, reg);
3296
3297 reg = RREG32_CG(CG_CAC_REGION_4_WEIGHT_1) & ~(WEIGHT_BIF_MASK |
3298 WEIGHT_CP_MASK |
3299 WEIGHT_PA_SIG0_MASK |
3300 WEIGHT_PA_SIG1_MASK |
3301 WEIGHT_VGT_SIG0_MASK);
3302 reg |= (WEIGHT_BIF(ni_pi->cac_weights->weight_bif) |
3303 WEIGHT_CP(ni_pi->cac_weights->weight_cp) |
3304 WEIGHT_PA_SIG0(ni_pi->cac_weights->weight_pa_sig0) |
3305 WEIGHT_PA_SIG1(ni_pi->cac_weights->weight_pa_sig1) |
3306 WEIGHT_VGT_SIG0(ni_pi->cac_weights->weight_vgt_sig0));
3307 WREG32_CG(CG_CAC_REGION_4_WEIGHT_1, reg);
3308
3309 reg = RREG32_CG(CG_CAC_REGION_4_WEIGHT_2) & ~(WEIGHT_VGT_SIG1_MASK |
3310 WEIGHT_VGT_SIG2_MASK |
3311 WEIGHT_DC_SIG0_MASK |
3312 WEIGHT_DC_SIG1_MASK |
3313 WEIGHT_DC_SIG2_MASK);
3314 reg |= (WEIGHT_VGT_SIG1(ni_pi->cac_weights->weight_vgt_sig1) |
3315 WEIGHT_VGT_SIG2(ni_pi->cac_weights->weight_vgt_sig2) |
3316 WEIGHT_DC_SIG0(ni_pi->cac_weights->weight_dc_sig0) |
3317 WEIGHT_DC_SIG1(ni_pi->cac_weights->weight_dc_sig1) |
3318 WEIGHT_DC_SIG2(ni_pi->cac_weights->weight_dc_sig2));
3319 WREG32_CG(CG_CAC_REGION_4_WEIGHT_2, reg);
3320
3321 reg = RREG32_CG(CG_CAC_REGION_4_WEIGHT_3) & ~(WEIGHT_DC_SIG3_MASK |
3322 WEIGHT_UVD_SIG0_MASK |
3323 WEIGHT_UVD_SIG1_MASK |
3324 WEIGHT_SPARE0_MASK |
3325 WEIGHT_SPARE1_MASK);
3326 reg |= (WEIGHT_DC_SIG3(ni_pi->cac_weights->weight_dc_sig3) |
3327 WEIGHT_UVD_SIG0(ni_pi->cac_weights->weight_uvd_sig0) |
3328 WEIGHT_UVD_SIG1(ni_pi->cac_weights->weight_uvd_sig1) |
3329 WEIGHT_SPARE0(ni_pi->cac_weights->weight_spare0) |
3330 WEIGHT_SPARE1(ni_pi->cac_weights->weight_spare1));
3331 WREG32_CG(CG_CAC_REGION_4_WEIGHT_3, reg);
3332
3333 reg = RREG32_CG(CG_CAC_REGION_5_WEIGHT_0) & ~(WEIGHT_SQ_VSP_MASK |
3334 WEIGHT_SQ_VSP0_MASK);
3335 reg |= (WEIGHT_SQ_VSP(ni_pi->cac_weights->weight_sq_vsp) |
3336 WEIGHT_SQ_VSP0(ni_pi->cac_weights->weight_sq_vsp0));
3337 WREG32_CG(CG_CAC_REGION_5_WEIGHT_0, reg);
3338
3339 reg = RREG32_CG(CG_CAC_REGION_5_WEIGHT_1) & ~(WEIGHT_SQ_GPR_MASK);
3340 reg |= WEIGHT_SQ_GPR(ni_pi->cac_weights->weight_sq_gpr);
3341 WREG32_CG(CG_CAC_REGION_5_WEIGHT_1, reg);
3342
3343 reg = RREG32_CG(CG_CAC_REGION_4_OVERRIDE_4) & ~(OVR_MODE_SPARE_0_MASK |
3344 OVR_VAL_SPARE_0_MASK |
3345 OVR_MODE_SPARE_1_MASK |
3346 OVR_VAL_SPARE_1_MASK);
3347 reg |= (OVR_MODE_SPARE_0(ni_pi->cac_weights->ovr_mode_spare_0) |
3348 OVR_VAL_SPARE_0(ni_pi->cac_weights->ovr_val_spare_0) |
3349 OVR_MODE_SPARE_1(ni_pi->cac_weights->ovr_mode_spare_1) |
3350 OVR_VAL_SPARE_1(ni_pi->cac_weights->ovr_val_spare_1));
3351 WREG32_CG(CG_CAC_REGION_4_OVERRIDE_4, reg);
3352
3353 reg = RREG32(SQ_CAC_THRESHOLD) & ~(VSP_MASK |
3354 VSP0_MASK |
3355 GPR_MASK);
3356 reg |= (VSP(ni_pi->cac_weights->vsp) |
3357 VSP0(ni_pi->cac_weights->vsp0) |
3358 GPR(ni_pi->cac_weights->gpr));
3359 WREG32(SQ_CAC_THRESHOLD, reg);
3360
3361 reg = (MCDW_WR_ENABLE |
3362 MCDX_WR_ENABLE |
3363 MCDY_WR_ENABLE |
3364 MCDZ_WR_ENABLE |
3365 INDEX(0x09D4));
3366 WREG32(MC_CG_CONFIG, reg);
3367
3368 reg = (READ_WEIGHT(ni_pi->cac_weights->mc_read_weight) |
3369 WRITE_WEIGHT(ni_pi->cac_weights->mc_write_weight) |
3370 ALLOW_OVERFLOW);
3371 WREG32(MC_CG_DATAPORT, reg);
3372
3373 return 0;
3374}
3375
3376static int ni_enable_smc_cac(struct radeon_device *rdev, bool enable)
3377{
3378 struct ni_power_info *ni_pi = ni_get_pi(rdev);
3379 int ret = 0;
3380 PPSMC_Result smc_result;
3381
3382 if (ni_pi->enable_cac) {
3383 if (enable) {
3384 struct radeon_ps *radeon_new_state = rdev->pm.dpm.requested_ps;
3385
3386 if (!r600_is_uvd_state(radeon_new_state->class, radeon_new_state->class2)) {
3387 smc_result = rv770_send_msg_to_smc(rdev, PPSMC_MSG_CollectCAC_PowerCorreln);
3388
3389 if (ni_pi->support_cac_long_term_average) {
3390 smc_result = rv770_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgEnable);
3391 if (PPSMC_Result_OK != smc_result)
3392 ni_pi->support_cac_long_term_average = false;
3393 }
3394
3395 smc_result = rv770_send_msg_to_smc(rdev, PPSMC_MSG_EnableCac);
3396 if (PPSMC_Result_OK != smc_result)
3397 ret = -EINVAL;
3398
3399 ni_pi->cac_enabled = (PPSMC_Result_OK == smc_result) ? true : false;
3400 }
3401 } else if (ni_pi->cac_enabled) {
3402 smc_result = rv770_send_msg_to_smc(rdev, PPSMC_MSG_DisableCac);
3403
3404 ni_pi->cac_enabled = false;
3405
3406 if (ni_pi->support_cac_long_term_average) {
3407 smc_result = rv770_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgDisable);
3408 if (PPSMC_Result_OK != smc_result)
3409 ni_pi->support_cac_long_term_average = false;
3410 }
3411 }
3412 }
3413
3414 return ret;
3415}
3416
3417static int ni_pcie_performance_request(struct radeon_device *rdev,
3418 u8 perf_req, bool advertise)
3419{
3420 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3421
3422#if defined(CONFIG_ACPI)
3423 if ((perf_req == PCIE_PERF_REQ_PECI_GEN1) ||
3424 (perf_req == PCIE_PERF_REQ_PECI_GEN2)) {
3425 if (eg_pi->pcie_performance_request_registered == false)
3426 radeon_acpi_pcie_notify_device_ready(rdev);
3427 eg_pi->pcie_performance_request_registered = true;
3428 return radeon_acpi_pcie_performance_request(rdev, perf_req, advertise);
3429 } else if ((perf_req == PCIE_PERF_REQ_REMOVE_REGISTRY) &&
3430 eg_pi->pcie_performance_request_registered) {
3431 eg_pi->pcie_performance_request_registered = false;
3432 return radeon_acpi_pcie_performance_request(rdev, perf_req, advertise);
3433 }
3434#endif
3435 return 0;
3436}
3437
3438static int ni_advertise_gen2_capability(struct radeon_device *rdev)
3439{
3440 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3441 u32 tmp;
3442
3443 tmp = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
3444
3445 if ((tmp & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
3446 (tmp & LC_OTHER_SIDE_SUPPORTS_GEN2))
3447 pi->pcie_gen2 = true;
3448 else
3449 pi->pcie_gen2 = false;
3450
3451 if (!pi->pcie_gen2)
3452 ni_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, true);
3453
3454 return 0;
3455}
3456
3457static void ni_enable_bif_dynamic_pcie_gen2(struct radeon_device *rdev,
3458 bool enable)
3459{
3460 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3461 u32 tmp, bif;
3462
3463 tmp = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
3464
3465 if ((tmp & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
3466 (tmp & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
3467 if (enable) {
3468 if (!pi->boot_in_gen2) {
3469 bif = RREG32(CG_BIF_REQ_AND_RSP) & ~CG_CLIENT_REQ_MASK;
3470 bif |= CG_CLIENT_REQ(0xd);
3471 WREG32(CG_BIF_REQ_AND_RSP, bif);
3472 }
3473 tmp &= ~LC_HW_VOLTAGE_IF_CONTROL_MASK;
3474 tmp |= LC_HW_VOLTAGE_IF_CONTROL(1);
3475 tmp |= LC_GEN2_EN_STRAP;
3476
3477 tmp |= LC_CLR_FAILED_SPD_CHANGE_CNT;
3478 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp);
3479 udelay(10);
3480 tmp &= ~LC_CLR_FAILED_SPD_CHANGE_CNT;
3481 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp);
3482 } else {
3483 if (!pi->boot_in_gen2) {
3484 bif = RREG32(CG_BIF_REQ_AND_RSP) & ~CG_CLIENT_REQ_MASK;
3485 bif |= CG_CLIENT_REQ(0xd);
3486 WREG32(CG_BIF_REQ_AND_RSP, bif);
3487
3488 tmp &= ~LC_HW_VOLTAGE_IF_CONTROL_MASK;
3489 tmp &= ~LC_GEN2_EN_STRAP;
3490 }
3491 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp);
3492 }
3493 }
3494}
3495
3496static void ni_enable_dynamic_pcie_gen2(struct radeon_device *rdev,
3497 bool enable)
3498{
3499 ni_enable_bif_dynamic_pcie_gen2(rdev, enable);
3500
3501 if (enable)
3502 WREG32_P(GENERAL_PWRMGT, ENABLE_GEN2PCIE, ~ENABLE_GEN2PCIE);
3503 else
3504 WREG32_P(GENERAL_PWRMGT, 0, ~ENABLE_GEN2PCIE);
3505}
3506
3507void ni_dpm_setup_asic(struct radeon_device *rdev)
3508{
3509 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3510
3511 ni_read_clock_registers(rdev);
3512 btc_read_arb_registers(rdev);
3513 rv770_get_memory_type(rdev);
3514 if (eg_pi->pcie_performance_request)
3515 ni_advertise_gen2_capability(rdev);
3516 rv770_get_pcie_gen2_status(rdev);
3517 rv770_enable_acpi_pm(rdev);
3518}
3519
3520int ni_dpm_enable(struct radeon_device *rdev)
3521{
3522 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3523 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3524
3525 if (pi->gfx_clock_gating)
3526 ni_cg_clockgating_default(rdev);
3527 if (btc_dpm_enabled(rdev))
3528 return -EINVAL;
3529 if (pi->mg_clock_gating)
3530 ni_mg_clockgating_default(rdev);
3531 if (eg_pi->ls_clock_gating)
3532 ni_ls_clockgating_default(rdev);
3533 if (pi->voltage_control) {
3534 rv770_enable_voltage_control(rdev, true);
3535 cypress_construct_voltage_tables(rdev);
3536 }
3537 if (eg_pi->dynamic_ac_timing)
3538 ni_initialize_mc_reg_table(rdev);
3539 if (pi->dynamic_ss)
3540 cypress_enable_spread_spectrum(rdev, true);
3541 if (pi->thermal_protection)
3542 rv770_enable_thermal_protection(rdev, true);
3543 rv770_setup_bsp(rdev);
3544 rv770_program_git(rdev);
3545 rv770_program_tp(rdev);
3546 rv770_program_tpp(rdev);
3547 rv770_program_sstp(rdev);
3548 cypress_enable_display_gap(rdev);
3549 rv770_program_vc(rdev);
3550 if (pi->dynamic_pcie_gen2)
3551 ni_enable_dynamic_pcie_gen2(rdev, true);
3552 if (rv770_upload_firmware(rdev))
3553 return -EINVAL;
3554 ni_process_firmware_header(rdev);
3555 ni_initial_switch_from_arb_f0_to_f1(rdev);
3556 ni_init_smc_table(rdev);
3557 ni_init_smc_spll_table(rdev);
3558 ni_init_arb_table_index(rdev);
3559 if (eg_pi->dynamic_ac_timing)
3560 ni_populate_mc_reg_table(rdev);
3561 ni_initialize_smc_cac_tables(rdev);
3562 ni_initialize_hardware_cac_manager(rdev);
3563 ni_populate_smc_tdp_limits(rdev);
3564 ni_program_response_times(rdev);
3565 r7xx_start_smc(rdev);
3566 cypress_notify_smc_display_change(rdev, false);
3567 cypress_enable_sclk_control(rdev, true);
3568 if (eg_pi->memory_transition)
3569 cypress_enable_mclk_control(rdev, true);
3570 cypress_start_dpm(rdev);
3571 if (pi->gfx_clock_gating)
3572 ni_gfx_clockgating_enable(rdev, true);
3573 if (pi->mg_clock_gating)
3574 ni_mg_clockgating_enable(rdev, true);
3575 if (eg_pi->ls_clock_gating)
3576 ni_ls_clockgating_enable(rdev, true);
3577
3578 if (rdev->irq.installed &&
3579 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
3580 PPSMC_Result result;
3581
3582 rv770_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, 0xff * 1000);
3583 rdev->irq.dpm_thermal = true;
3584 radeon_irq_set(rdev);
3585 result = rv770_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt);
3586
3587 if (result != PPSMC_Result_OK)
3588 DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
3589 }
3590
3591 rv770_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
3592
3593 return 0;
3594}
3595
3596void ni_dpm_disable(struct radeon_device *rdev)
3597{
3598 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3599 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3600
3601 if (!btc_dpm_enabled(rdev))
3602 return;
3603 rv770_clear_vc(rdev);
3604 if (pi->thermal_protection)
3605 rv770_enable_thermal_protection(rdev, false);
3606 ni_enable_power_containment(rdev, false);
3607 ni_enable_smc_cac(rdev, false);
3608 cypress_enable_spread_spectrum(rdev, false);
3609 rv770_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, false);
3610 if (pi->dynamic_pcie_gen2)
3611 ni_enable_dynamic_pcie_gen2(rdev, false);
3612
3613 if (rdev->irq.installed &&
3614 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
3615 rdev->irq.dpm_thermal = false;
3616 radeon_irq_set(rdev);
3617 }
3618
3619 if (pi->gfx_clock_gating)
3620 ni_gfx_clockgating_enable(rdev, false);
3621 if (pi->mg_clock_gating)
3622 ni_mg_clockgating_enable(rdev, false);
3623 if (eg_pi->ls_clock_gating)
3624 ni_ls_clockgating_enable(rdev, false);
3625 ni_stop_dpm(rdev);
3626 btc_reset_to_default(rdev);
3627 ni_stop_smc(rdev);
3628 ni_force_switch_to_arb_f0(rdev);
3629}
3630
3631int ni_power_control_set_level(struct radeon_device *rdev)
3632{
3633 ni_restrict_performance_levels_before_switch(rdev);
3634 rv770_halt_smc(rdev);
3635 ni_populate_smc_tdp_limits(rdev);
3636 rv770_resume_smc(rdev);
3637 rv770_set_sw_state(rdev);
3638
3639 return 0;
3640}
3641
3642int ni_dpm_set_power_state(struct radeon_device *rdev)
3643{
3644 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3645 int ret;
3646
3647 ni_apply_state_adjust_rules(rdev);
3648
3649 ni_restrict_performance_levels_before_switch(rdev);
3650 ni_enable_power_containment(rdev, false);
3651 ni_enable_smc_cac(rdev, false);
3652 rv770_halt_smc(rdev);
3653 if (eg_pi->smu_uvd_hs)
3654 btc_notify_uvd_to_smc(rdev);
3655 ni_upload_sw_state(rdev);
3656 if (eg_pi->dynamic_ac_timing)
3657 ni_upload_mc_reg_table(rdev);
3658 ret = ni_program_memory_timing_parameters(rdev);
3659 if (ret)
3660 return ret;
3661 ni_populate_smc_tdp_limits(rdev);
3662 rv770_resume_smc(rdev);
3663 rv770_set_sw_state(rdev);
3664 ni_enable_smc_cac(rdev, true);
3665 ni_enable_power_containment(rdev, true);
3666
3667#if 0
3668 /* XXX */
3669 ni_unrestrict_performance_levels_after_switch(rdev);
3670#endif
3671
3672 return 0;
3673}
3674
3675void ni_dpm_reset_asic(struct radeon_device *rdev)
3676{
3677 ni_restrict_performance_levels_before_switch(rdev);
3678 rv770_set_boot_state(rdev);
3679}
3680
3681union power_info {
3682 struct _ATOM_POWERPLAY_INFO info;
3683 struct _ATOM_POWERPLAY_INFO_V2 info_2;
3684 struct _ATOM_POWERPLAY_INFO_V3 info_3;
3685 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
3686 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
3687 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
3688};
3689
3690union pplib_clock_info {
3691 struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
3692 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
3693 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
3694 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
3695};
3696
3697union pplib_power_state {
3698 struct _ATOM_PPLIB_STATE v1;
3699 struct _ATOM_PPLIB_STATE_V2 v2;
3700};
3701
3702static void ni_parse_pplib_non_clock_info(struct radeon_device *rdev,
3703 struct radeon_ps *rps,
3704 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
3705 u8 table_rev)
3706{
3707 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
3708 rps->class = le16_to_cpu(non_clock_info->usClassification);
3709 rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
3710
3711 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
3712 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
3713 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
3714 } else if (r600_is_uvd_state(rps->class, rps->class2)) {
3715 rps->vclk = RV770_DEFAULT_VCLK_FREQ;
3716 rps->dclk = RV770_DEFAULT_DCLK_FREQ;
3717 } else {
3718 rps->vclk = 0;
3719 rps->dclk = 0;
3720 }
3721
3722 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
3723 rdev->pm.dpm.boot_ps = rps;
3724 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
3725 rdev->pm.dpm.uvd_ps = rps;
3726}
3727
3728static void ni_parse_pplib_clock_info(struct radeon_device *rdev,
3729 struct radeon_ps *rps, int index,
3730 union pplib_clock_info *clock_info)
3731{
3732 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3733 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3734 struct ni_ps *ps = ni_get_ps(rps);
3735 u16 vddc;
3736 struct rv7xx_pl *pl = &ps->performance_levels[index];
3737
3738 ps->performance_level_count = index + 1;
3739
3740 pl->sclk = le16_to_cpu(clock_info->evergreen.usEngineClockLow);
3741 pl->sclk |= clock_info->evergreen.ucEngineClockHigh << 16;
3742 pl->mclk = le16_to_cpu(clock_info->evergreen.usMemoryClockLow);
3743 pl->mclk |= clock_info->evergreen.ucMemoryClockHigh << 16;
3744
3745 pl->vddc = le16_to_cpu(clock_info->evergreen.usVDDC);
3746 pl->vddci = le16_to_cpu(clock_info->evergreen.usVDDCI);
3747 pl->flags = le32_to_cpu(clock_info->evergreen.ulFlags);
3748
3749 /* patch up vddc if necessary */
3750 if (pl->vddc == 0xff01) {
3751 if (radeon_atom_get_max_vddc(rdev, 0, 0, &vddc) == 0)
3752 pl->vddc = vddc;
3753 }
3754
3755 if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) {
3756 pi->acpi_vddc = pl->vddc;
3757 eg_pi->acpi_vddci = pl->vddci;
3758 if (ps->performance_levels[0].flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2)
3759 pi->acpi_pcie_gen2 = true;
3760 else
3761 pi->acpi_pcie_gen2 = false;
3762 }
3763
3764 if (rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) {
3765 eg_pi->ulv.supported = true;
3766 eg_pi->ulv.pl = pl;
3767 }
3768
3769 if (pi->min_vddc_in_table > pl->vddc)
3770 pi->min_vddc_in_table = pl->vddc;
3771
3772 if (pi->max_vddc_in_table < pl->vddc)
3773 pi->max_vddc_in_table = pl->vddc;
3774
3775 /* patch up boot state */
3776 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
3777 u16 vddc, vddci;
3778 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci);
3779 pl->mclk = rdev->clock.default_mclk;
3780 pl->sclk = rdev->clock.default_sclk;
3781 pl->vddc = vddc;
3782 pl->vddci = vddci;
3783 }
3784
3785 if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) ==
3786 ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
3787 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk;
3788 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk;
3789 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc;
3790 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci;
3791 }
3792}
3793
3794static int ni_parse_power_table(struct radeon_device *rdev)
3795{
3796 struct radeon_mode_info *mode_info = &rdev->mode_info;
3797 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
3798 union pplib_power_state *power_state;
3799 int i, j;
3800 union pplib_clock_info *clock_info;
3801 union power_info *power_info;
3802 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
3803 u16 data_offset;
3804 u8 frev, crev;
3805 struct ni_ps *ps;
3806
3807 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
3808 &frev, &crev, &data_offset))
3809 return -EINVAL;
3810 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
3811
3812 rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) *
3813 power_info->pplib.ucNumStates, GFP_KERNEL);
3814 if (!rdev->pm.dpm.ps)
3815 return -ENOMEM;
3816 rdev->pm.dpm.platform_caps = le32_to_cpu(power_info->pplib.ulPlatformCaps);
3817 rdev->pm.dpm.backbias_response_time = le16_to_cpu(power_info->pplib.usBackbiasTime);
3818 rdev->pm.dpm.voltage_response_time = le16_to_cpu(power_info->pplib.usVoltageTime);
3819
3820 for (i = 0; i < power_info->pplib.ucNumStates; i++) {
3821 power_state = (union pplib_power_state *)
3822 (mode_info->atom_context->bios + data_offset +
3823 le16_to_cpu(power_info->pplib.usStateArrayOffset) +
3824 i * power_info->pplib.ucStateEntrySize);
3825 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
3826 (mode_info->atom_context->bios + data_offset +
3827 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset) +
3828 (power_state->v1.ucNonClockStateIndex *
3829 power_info->pplib.ucNonClockSize));
3830 if (power_info->pplib.ucStateEntrySize - 1) {
3831 ps = kzalloc(sizeof(struct ni_ps), GFP_KERNEL);
3832 if (ps == NULL) {
3833 kfree(rdev->pm.dpm.ps);
3834 return -ENOMEM;
3835 }
3836 rdev->pm.dpm.ps[i].ps_priv = ps;
3837 ni_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],
3838 non_clock_info,
3839 power_info->pplib.ucNonClockSize);
3840 for (j = 0; j < (power_info->pplib.ucStateEntrySize - 1); j++) {
3841 clock_info = (union pplib_clock_info *)
3842 (mode_info->atom_context->bios + data_offset +
3843 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset) +
3844 (power_state->v1.ucClockStateIndices[j] *
3845 power_info->pplib.ucClockInfoSize));
3846 ni_parse_pplib_clock_info(rdev,
3847 &rdev->pm.dpm.ps[i], j,
3848 clock_info);
3849 }
3850 }
3851 }
3852 rdev->pm.dpm.num_ps = power_info->pplib.ucNumStates;
3853 return 0;
3854}
3855
3856int ni_dpm_init(struct radeon_device *rdev)
3857{
3858 struct rv7xx_power_info *pi;
3859 struct evergreen_power_info *eg_pi;
3860 struct ni_power_info *ni_pi;
3861 int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
3862 u16 data_offset, size;
3863 u8 frev, crev;
3864 struct atom_clock_dividers dividers;
3865 int ret;
3866
3867 ni_pi = kzalloc(sizeof(struct ni_power_info), GFP_KERNEL);
3868 if (ni_pi == NULL)
3869 return -ENOMEM;
3870 rdev->pm.dpm.priv = ni_pi;
3871 eg_pi = &ni_pi->eg;
3872 pi = &eg_pi->rv7xx;
3873
3874 rv770_get_max_vddc(rdev);
3875
3876 eg_pi->ulv.supported = false;
3877 pi->acpi_vddc = 0;
3878 eg_pi->acpi_vddci = 0;
3879 pi->min_vddc_in_table = 0;
3880 pi->max_vddc_in_table = 0;
3881
3882 ret = ni_parse_power_table(rdev);
3883 if (ret)
3884 return ret;
3885 ret = r600_parse_extended_power_table(rdev);
3886 if (ret)
3887 return ret;
3888
3889 ni_patch_dependency_tables_based_on_leakage(rdev);
3890
3891 if (rdev->pm.dpm.voltage_response_time == 0)
3892 rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT;
3893 if (rdev->pm.dpm.backbias_response_time == 0)
3894 rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT;
3895
3896 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
3897 0, false, &dividers);
3898 if (ret)
3899 pi->ref_div = dividers.ref_div + 1;
3900 else
3901 pi->ref_div = R600_REFERENCEDIVIDER_DFLT;
3902
3903 pi->rlp = RV770_RLP_DFLT;
3904 pi->rmp = RV770_RMP_DFLT;
3905 pi->lhp = RV770_LHP_DFLT;
3906 pi->lmp = RV770_LMP_DFLT;
3907
3908 eg_pi->ats[0].rlp = RV770_RLP_DFLT;
3909 eg_pi->ats[0].rmp = RV770_RMP_DFLT;
3910 eg_pi->ats[0].lhp = RV770_LHP_DFLT;
3911 eg_pi->ats[0].lmp = RV770_LMP_DFLT;
3912
3913 eg_pi->ats[1].rlp = BTC_RLP_UVD_DFLT;
3914 eg_pi->ats[1].rmp = BTC_RMP_UVD_DFLT;
3915 eg_pi->ats[1].lhp = BTC_LHP_UVD_DFLT;
3916 eg_pi->ats[1].lmp = BTC_LMP_UVD_DFLT;
3917
3918 eg_pi->smu_uvd_hs = true;
3919
3920 if (rdev->pdev->device == 0x6707) {
3921 pi->mclk_strobe_mode_threshold = 55000;
3922 pi->mclk_edc_enable_threshold = 55000;
3923 eg_pi->mclk_edc_wr_enable_threshold = 55000;
3924 } else {
3925 pi->mclk_strobe_mode_threshold = 40000;
3926 pi->mclk_edc_enable_threshold = 40000;
3927 eg_pi->mclk_edc_wr_enable_threshold = 40000;
3928 }
3929 ni_pi->mclk_rtt_mode_threshold = eg_pi->mclk_edc_wr_enable_threshold;
3930
3931 pi->voltage_control =
3932 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC);
3933
3934 pi->mvdd_control =
3935 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_MVDDC);
3936
3937 eg_pi->vddci_control =
3938 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI);
3939
3940 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3941 &frev, &crev, &data_offset)) {
3942 pi->sclk_ss = true;
3943 pi->mclk_ss = true;
3944 pi->dynamic_ss = true;
3945 } else {
3946 pi->sclk_ss = false;
3947 pi->mclk_ss = false;
3948 pi->dynamic_ss = true;
3949 }
3950
3951 pi->asi = RV770_ASI_DFLT;
3952 pi->pasi = CYPRESS_HASI_DFLT;
3953 pi->vrc = CYPRESS_VRC_DFLT;
3954
3955 pi->power_gating = false;
3956
3957 pi->gfx_clock_gating = true;
3958
3959 pi->mg_clock_gating = true;
3960 pi->mgcgtssm = true;
3961 eg_pi->ls_clock_gating = false;
3962 eg_pi->sclk_deep_sleep = false;
3963
3964 pi->dynamic_pcie_gen2 = true;
3965
3966 if (pi->gfx_clock_gating &&
3967 (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE))
3968 pi->thermal_protection = true;
3969 else
3970 pi->thermal_protection = false;
3971
3972 pi->display_gap = true;
3973
3974 pi->dcodt = true;
3975
3976 pi->ulps = true;
3977
3978 eg_pi->dynamic_ac_timing = true;
3979 eg_pi->abm = true;
3980 eg_pi->mcls = true;
3981 eg_pi->light_sleep = true;
3982 eg_pi->memory_transition = true;
3983#if defined(CONFIG_ACPI)
3984 eg_pi->pcie_performance_request =
3985 radeon_acpi_is_pcie_performance_request_supported(rdev);
3986#else
3987 eg_pi->pcie_performance_request = false;
3988#endif
3989
3990 eg_pi->dll_default_on = false;
3991
3992 eg_pi->sclk_deep_sleep = false;
3993
3994 pi->mclk_stutter_mode_threshold = 0;
3995
3996 pi->sram_end = SMC_RAM_END;
3997
3998 rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 3;
3999 rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200;
4000 rdev->pm.dpm.dyn_state.min_vddc_for_pcie_gen2 = 900;
4001 rdev->pm.dpm.dyn_state.valid_sclk_values.count = ARRAY_SIZE(btc_valid_sclk);
4002 rdev->pm.dpm.dyn_state.valid_sclk_values.values = btc_valid_sclk;
4003 rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0;
4004 rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL;
4005 rdev->pm.dpm.dyn_state.sclk_mclk_delta = 12500;
4006
4007 ni_pi->cac_data.leakage_coefficients.at = 516;
4008 ni_pi->cac_data.leakage_coefficients.bt = 18;
4009 ni_pi->cac_data.leakage_coefficients.av = 51;
4010 ni_pi->cac_data.leakage_coefficients.bv = 2957;
4011
4012 switch (rdev->pdev->device) {
4013 case 0x6700:
4014 case 0x6701:
4015 case 0x6702:
4016 case 0x6703:
4017 case 0x6718:
4018 ni_pi->cac_weights = &cac_weights_cayman_xt;
4019 break;
4020 case 0x6705:
4021 case 0x6719:
4022 case 0x671D:
4023 case 0x671C:
4024 default:
4025 ni_pi->cac_weights = &cac_weights_cayman_pro;
4026 break;
4027 case 0x6704:
4028 case 0x6706:
4029 case 0x6707:
4030 case 0x6708:
4031 case 0x6709:
4032 ni_pi->cac_weights = &cac_weights_cayman_le;
4033 break;
4034 }
4035
4036 if (ni_pi->cac_weights->enable_power_containment_by_default) {
4037 ni_pi->enable_power_containment = true;
4038 ni_pi->enable_cac = true;
4039 ni_pi->enable_sq_ramping = true;
4040 } else {
4041 ni_pi->enable_power_containment = false;
4042 ni_pi->enable_cac = false;
4043 ni_pi->enable_sq_ramping = false;
4044 }
4045
4046 ni_pi->driver_calculate_cac_leakage = false;
4047 ni_pi->cac_configuration_required = true;
4048
4049 if (ni_pi->cac_configuration_required) {
4050 ni_pi->support_cac_long_term_average = true;
4051 ni_pi->lta_window_size = ni_pi->cac_weights->l2_lta_window_size;
4052 ni_pi->lts_truncate = ni_pi->cac_weights->lts_truncate;
4053 } else {
4054 ni_pi->support_cac_long_term_average = false;
4055 ni_pi->lta_window_size = 0;
4056 ni_pi->lts_truncate = 0;
4057 }
4058
4059 ni_pi->use_power_boost_limit = true;
4060
4061 return 0;
4062}
4063
4064void ni_dpm_fini(struct radeon_device *rdev)
4065{
4066 int i;
4067
4068 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
4069 kfree(rdev->pm.dpm.ps[i].ps_priv);
4070 }
4071 kfree(rdev->pm.dpm.ps);
4072 kfree(rdev->pm.dpm.priv);
4073 r600_free_extended_power_table(rdev);
4074}
4075
4076void ni_dpm_print_power_state(struct radeon_device *rdev,
4077 struct radeon_ps *rps)
4078{
4079 struct ni_ps *ps = ni_get_ps(rps);
4080 struct rv7xx_pl *pl;
4081 int i;
4082
4083 r600_dpm_print_class_info(rps->class, rps->class2);
4084 r600_dpm_print_cap_info(rps->caps);
4085 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
4086 for (i = 0; i < ps->performance_level_count; i++) {
4087 pl = &ps->performance_levels[i];
4088 printk("\t\tpower level 0 sclk: %u mclk: %u vddc: %u vddci: %u\n",
4089 pl->sclk, pl->mclk, pl->vddc, pl->vddci);
4090 }
4091 r600_dpm_print_ps_status(rdev, rps);
4092}
4093
4094u32 ni_dpm_get_sclk(struct radeon_device *rdev, bool low)
4095{
4096 struct ni_ps *requested_state = ni_get_ps(rdev->pm.dpm.requested_ps);
4097
4098 if (low)
4099 return requested_state->performance_levels[0].sclk;
4100 else
4101 return requested_state->performance_levels[requested_state->performance_level_count - 1].sclk;
4102}
4103
4104u32 ni_dpm_get_mclk(struct radeon_device *rdev, bool low)
4105{
4106 struct ni_ps *requested_state = ni_get_ps(rdev->pm.dpm.requested_ps);
4107
4108 if (low)
4109 return requested_state->performance_levels[0].mclk;
4110 else
4111 return requested_state->performance_levels[requested_state->performance_level_count - 1].mclk;
4112}
4113
Linux kernel - Deliverables
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