projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 0af62b01 AD |
1 | /* |
| 2 | * Copyright 2010 Advanced Micro Devices, Inc. | |
| 3 | * | |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
| 5 | * copy of this software and associated documentation files (the "Software"), | |
| 6 | * to deal in the Software without restriction, including without limitation | |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the | |
| 9 | * Software is furnished to do so, subject to the following conditions: | |
| 10 | * | |
| 11 | * The above copyright notice and this permission notice shall be included in | |
| 12 | * all copies or substantial portions of the Software. | |
| 13 | * | |
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 20 | * OTHER DEALINGS IN THE SOFTWARE. | |
| 21 | * | |
| 22 | * Authors: Alex Deucher | |
| 23 | */ | |
| 24 | #ifndef NI_H | |
| 25 | #define NI_H | |
| 26 | ||
| fecf1d07 AD |
27 | #define CAYMAN_MAX_SH_GPRS 256 |
| 28 | #define CAYMAN_MAX_TEMP_GPRS 16 | |
| 29 | #define CAYMAN_MAX_SH_THREADS 256 | |
| 30 | #define CAYMAN_MAX_SH_STACK_ENTRIES 4096 | |
| 31 | #define CAYMAN_MAX_FRC_EOV_CNT 16384 | |
| 32 | #define CAYMAN_MAX_BACKENDS 8 | |
| 33 | #define CAYMAN_MAX_BACKENDS_MASK 0xFF | |
| 34 | #define CAYMAN_MAX_BACKENDS_PER_SE_MASK 0xF | |
| 35 | #define CAYMAN_MAX_SIMDS 16 | |
| 36 | #define CAYMAN_MAX_SIMDS_MASK 0xFFFF | |
| 37 | #define CAYMAN_MAX_SIMDS_PER_SE_MASK 0xFFF | |
| 38 | #define CAYMAN_MAX_PIPES 8 | |
| 39 | #define CAYMAN_MAX_PIPES_MASK 0xFF | |
| 40 | #define CAYMAN_MAX_LDS_NUM 0xFFFF | |
| 41 | #define CAYMAN_MAX_TCC 16 | |
| 42 | #define CAYMAN_MAX_TCC_MASK 0xFF | |
| 43 | ||
| 416a2bd2 AD |
44 | #define CAYMAN_GB_ADDR_CONFIG_GOLDEN 0x02011003 |
| 45 | #define ARUBA_GB_ADDR_CONFIG_GOLDEN 0x12010001 | |
| 46 | ||
| fecf1d07 | 47 | #define DMIF_ADDR_CONFIG 0xBD4 |
| 7c1c7c18 AD |
48 | |
| 49 | /* DCE6 only */ | |
| 50 | #define DMIF_ADDR_CALC 0xC00 | |
| 51 | ||
| 1b37078b AD |
52 | #define SRBM_GFX_CNTL 0x0E44 |
| 53 | #define RINGID(x) (((x) & 0x3) << 0) | |
| 54 | #define VMID(x) (((x) & 0x7) << 0) | |
| b9952a8a | 55 | #define SRBM_STATUS 0x0E50 |
| 168757ea AD |
56 | #define RLC_RQ_PENDING (1 << 3) |
| 57 | #define GRBM_RQ_PENDING (1 << 5) | |
| 58 | #define VMC_BUSY (1 << 8) | |
| 59 | #define MCB_BUSY (1 << 9) | |
| 60 | #define MCB_NON_DISPLAY_BUSY (1 << 10) | |
| 61 | #define MCC_BUSY (1 << 11) | |
| 62 | #define MCD_BUSY (1 << 12) | |
| 63 | #define SEM_BUSY (1 << 14) | |
| 64 | #define RLC_BUSY (1 << 15) | |
| 65 | #define IH_BUSY (1 << 17) | |
| fecf1d07 | 66 | |
| f60cbd11 AD |
67 | #define SRBM_SOFT_RESET 0x0E60 |
| 68 | #define SOFT_RESET_BIF (1 << 1) | |
| 69 | #define SOFT_RESET_CG (1 << 2) | |
| 70 | #define SOFT_RESET_DC (1 << 5) | |
| 71 | #define SOFT_RESET_DMA1 (1 << 6) | |
| 72 | #define SOFT_RESET_GRBM (1 << 8) | |
| 73 | #define SOFT_RESET_HDP (1 << 9) | |
| 74 | #define SOFT_RESET_IH (1 << 10) | |
| 75 | #define SOFT_RESET_MC (1 << 11) | |
| 76 | #define SOFT_RESET_RLC (1 << 13) | |
| 77 | #define SOFT_RESET_ROM (1 << 14) | |
| 78 | #define SOFT_RESET_SEM (1 << 15) | |
| 79 | #define SOFT_RESET_VMC (1 << 17) | |
| 80 | #define SOFT_RESET_DMA (1 << 20) | |
| 81 | #define SOFT_RESET_TST (1 << 21) | |
| 64c56e8c | 82 | #define SOFT_RESET_REGBB (1 << 22) |
| f60cbd11 AD |
83 | #define SOFT_RESET_ORB (1 << 23) |
| 84 | ||
| 168757ea AD |
85 | #define SRBM_STATUS2 0x0EC4 |
| 86 | #define DMA_BUSY (1 << 5) | |
| 87 | #define DMA1_BUSY (1 << 6) | |
| 88 | ||
| fa8198ea AD |
89 | #define VM_CONTEXT0_REQUEST_RESPONSE 0x1470 |
| 90 | #define REQUEST_TYPE(x) (((x) & 0xf) << 0) | |
| 91 | #define RESPONSE_TYPE_MASK 0x000000F0 | |
| 92 | #define RESPONSE_TYPE_SHIFT 4 | |
| 93 | #define VM_L2_CNTL 0x1400 | |
| 94 | #define ENABLE_L2_CACHE (1 << 0) | |
| 95 | #define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1) | |
| 96 | #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) | |
| 97 | #define ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE (1 << 10) | |
| 98 | #define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 14) | |
| 99 | #define CONTEXT1_IDENTITY_ACCESS_MODE(x) (((x) & 3) << 18) | |
| 100 | /* CONTEXT1_IDENTITY_ACCESS_MODE | |
| 101 | * 0 physical = logical | |
| 102 | * 1 logical via context1 page table | |
| 103 | * 2 inside identity aperture use translation, outside physical = logical | |
| 104 | * 3 inside identity aperture physical = logical, outside use translation | |
| 105 | */ | |
| 106 | #define VM_L2_CNTL2 0x1404 | |
| 107 | #define INVALIDATE_ALL_L1_TLBS (1 << 0) | |
| 108 | #define INVALIDATE_L2_CACHE (1 << 1) | |
| 109 | #define VM_L2_CNTL3 0x1408 | |
| 110 | #define BANK_SELECT(x) ((x) << 0) | |
| 111 | #define CACHE_UPDATE_MODE(x) ((x) << 6) | |
| 112 | #define L2_CACHE_BIGK_ASSOCIATIVITY (1 << 20) | |
| 113 | #define L2_CACHE_BIGK_FRAGMENT_SIZE(x) ((x) << 15) | |
| 114 | #define VM_L2_STATUS 0x140C | |
| 115 | #define L2_BUSY (1 << 0) | |
| 116 | #define VM_CONTEXT0_CNTL 0x1410 | |
| 117 | #define ENABLE_CONTEXT (1 << 0) | |
| 118 | #define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1) | |
| ae133a11 | 119 | #define RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 3) |
| fa8198ea | 120 | #define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4) |
| ae133a11 CK |
121 | #define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 6) |
| 122 | #define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 7) | |
| 123 | #define PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 9) | |
| 124 | #define PDE0_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 10) | |
| 125 | #define VALID_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 12) | |
| 126 | #define VALID_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 13) | |
| 127 | #define READ_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 15) | |
| 128 | #define READ_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 16) | |
| 129 | #define WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 18) | |
| 130 | #define WRITE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 19) | |
| 1c89d27f | 131 | #define PAGE_TABLE_BLOCK_SIZE(x) (((x) & 0xF) << 24) |
| fa8198ea AD |
132 | #define VM_CONTEXT1_CNTL 0x1414 |
| 133 | #define VM_CONTEXT0_CNTL2 0x1430 | |
| 134 | #define VM_CONTEXT1_CNTL2 0x1434 | |
| 135 | #define VM_INVALIDATE_REQUEST 0x1478 | |
| 136 | #define VM_INVALIDATE_RESPONSE 0x147c | |
| 54e2e49c AD |
137 | #define VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x14FC |
| 138 | #define VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x14DC | |
| 139 | #define PROTECTIONS_MASK (0xf << 0) | |
| 140 | #define PROTECTIONS_SHIFT 0 | |
| 141 | /* bit 0: range | |
| 142 | * bit 2: pde0 | |
| 143 | * bit 3: valid | |
| 144 | * bit 4: read | |
| 145 | * bit 5: write | |
| 146 | */ | |
| 147 | #define MEMORY_CLIENT_ID_MASK (0xff << 12) | |
| 148 | #define MEMORY_CLIENT_ID_SHIFT 12 | |
| 149 | #define MEMORY_CLIENT_RW_MASK (1 << 24) | |
| 150 | #define MEMORY_CLIENT_RW_SHIFT 24 | |
| 151 | #define FAULT_VMID_MASK (0x7 << 25) | |
| 152 | #define FAULT_VMID_SHIFT 25 | |
| fa8198ea AD |
153 | #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518 |
| 154 | #define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR 0x151c | |
| 155 | #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153C | |
| 156 | #define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155C | |
| 157 | #define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C | |
| 158 | ||
| fecf1d07 AD |
159 | #define MC_SHARED_CHMAP 0x2004 |
| 160 | #define NOOFCHAN_SHIFT 12 | |
| 161 | #define NOOFCHAN_MASK 0x00003000 | |
| 162 | #define MC_SHARED_CHREMAP 0x2008 | |
| fa8198ea AD |
163 | |
| 164 | #define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034 | |
| 165 | #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038 | |
| 166 | #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C | |
| 167 | #define MC_VM_MX_L1_TLB_CNTL 0x2064 | |
| 168 | #define ENABLE_L1_TLB (1 << 0) | |
| 169 | #define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) | |
| 170 | #define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3) | |
| 171 | #define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3) | |
| 172 | #define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3) | |
| 173 | #define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3) | |
| 174 | #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5) | |
| 175 | #define ENABLE_ADVANCED_DRIVER_MODEL (1 << 6) | |
| 05b3ef69 | 176 | #define FUS_MC_VM_FB_OFFSET 0x2068 |
| fa8198ea | 177 | |
| 0af62b01 | 178 | #define MC_SHARED_BLACKOUT_CNTL 0x20ac |
| fecf1d07 AD |
179 | #define MC_ARB_RAMCFG 0x2760 |
| 180 | #define NOOFBANK_SHIFT 0 | |
| 181 | #define NOOFBANK_MASK 0x00000003 | |
| 182 | #define NOOFRANK_SHIFT 2 | |
| 183 | #define NOOFRANK_MASK 0x00000004 | |
| 184 | #define NOOFROWS_SHIFT 3 | |
| 185 | #define NOOFROWS_MASK 0x00000038 | |
| 186 | #define NOOFCOLS_SHIFT 6 | |
| 187 | #define NOOFCOLS_MASK 0x000000C0 | |
| 188 | #define CHANSIZE_SHIFT 8 | |
| 189 | #define CHANSIZE_MASK 0x00000100 | |
| 190 | #define BURSTLENGTH_SHIFT 9 | |
| 191 | #define BURSTLENGTH_MASK 0x00000200 | |
| 192 | #define CHANSIZE_OVERRIDE (1 << 11) | |
| 0af62b01 AD |
193 | #define MC_SEQ_SUP_CNTL 0x28c8 |
| 194 | #define RUN_MASK (1 << 0) | |
| 195 | #define MC_SEQ_SUP_PGM 0x28cc | |
| 196 | #define MC_IO_PAD_CNTL_D0 0x29d0 | |
| 197 | #define MEM_FALL_OUT_CMD (1 << 8) | |
| 198 | #define MC_SEQ_MISC0 0x2a00 | |
| 199 | #define MC_SEQ_MISC0_GDDR5_SHIFT 28 | |
| 200 | #define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000 | |
| 201 | #define MC_SEQ_MISC0_GDDR5_VALUE 5 | |
| 202 | #define MC_SEQ_IO_DEBUG_INDEX 0x2a44 | |
| 203 | #define MC_SEQ_IO_DEBUG_DATA 0x2a48 | |
| 204 | ||
| fecf1d07 AD |
205 | #define HDP_HOST_PATH_CNTL 0x2C00 |
| 206 | #define HDP_NONSURFACE_BASE 0x2C04 | |
| 207 | #define HDP_NONSURFACE_INFO 0x2C08 | |
| 208 | #define HDP_NONSURFACE_SIZE 0x2C0C | |
| 209 | #define HDP_ADDR_CONFIG 0x2F48 | |
| 0b65f83f DA |
210 | #define HDP_MISC_CNTL 0x2F4C |
| 211 | #define HDP_FLUSH_INVALIDATE_CACHE (1 << 0) | |
| fecf1d07 AD |
212 | |
| 213 | #define CC_SYS_RB_BACKEND_DISABLE 0x3F88 | |
| 214 | #define GC_USER_SYS_RB_BACKEND_DISABLE 0x3F8C | |
| 215 | #define CGTS_SYS_TCC_DISABLE 0x3F90 | |
| 216 | #define CGTS_USER_SYS_TCC_DISABLE 0x3F94 | |
| 217 | ||
| 416a2bd2 AD |
218 | #define RLC_GFX_INDEX 0x3FC4 |
| 219 | ||
| fecf1d07 AD |
220 | #define CONFIG_MEMSIZE 0x5428 |
| 221 | ||
| fa8198ea | 222 | #define HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480 |
| fecf1d07 AD |
223 | #define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 |
| 224 | ||
| 225 | #define GRBM_CNTL 0x8000 | |
| 226 | #define GRBM_READ_TIMEOUT(x) ((x) << 0) | |
| 227 | #define GRBM_STATUS 0x8010 | |
| 228 | #define CMDFIFO_AVAIL_MASK 0x0000000F | |
| 229 | #define RING2_RQ_PENDING (1 << 4) | |
| 230 | #define SRBM_RQ_PENDING (1 << 5) | |
| 231 | #define RING1_RQ_PENDING (1 << 6) | |
| 232 | #define CF_RQ_PENDING (1 << 7) | |
| 233 | #define PF_RQ_PENDING (1 << 8) | |
| 234 | #define GDS_DMA_RQ_PENDING (1 << 9) | |
| 235 | #define GRBM_EE_BUSY (1 << 10) | |
| 236 | #define SX_CLEAN (1 << 11) | |
| 237 | #define DB_CLEAN (1 << 12) | |
| 238 | #define CB_CLEAN (1 << 13) | |
| 239 | #define TA_BUSY (1 << 14) | |
| 240 | #define GDS_BUSY (1 << 15) | |
| 241 | #define VGT_BUSY_NO_DMA (1 << 16) | |
| 242 | #define VGT_BUSY (1 << 17) | |
| 243 | #define IA_BUSY_NO_DMA (1 << 18) | |
| 244 | #define IA_BUSY (1 << 19) | |
| 245 | #define SX_BUSY (1 << 20) | |
| 246 | #define SH_BUSY (1 << 21) | |
| 247 | #define SPI_BUSY (1 << 22) | |
| 248 | #define SC_BUSY (1 << 24) | |
| 249 | #define PA_BUSY (1 << 25) | |
| 250 | #define DB_BUSY (1 << 26) | |
| 251 | #define CP_COHERENCY_BUSY (1 << 28) | |
| 252 | #define CP_BUSY (1 << 29) | |
| 253 | #define CB_BUSY (1 << 30) | |
| 254 | #define GUI_ACTIVE (1 << 31) | |
| 255 | #define GRBM_STATUS_SE0 0x8014 | |
| 256 | #define GRBM_STATUS_SE1 0x8018 | |
| 257 | #define SE_SX_CLEAN (1 << 0) | |
| 258 | #define SE_DB_CLEAN (1 << 1) | |
| 259 | #define SE_CB_CLEAN (1 << 2) | |
| 260 | #define SE_VGT_BUSY (1 << 23) | |
| 261 | #define SE_PA_BUSY (1 << 24) | |
| 262 | #define SE_TA_BUSY (1 << 25) | |
| 263 | #define SE_SX_BUSY (1 << 26) | |
| 264 | #define SE_SPI_BUSY (1 << 27) | |
| 265 | #define SE_SH_BUSY (1 << 28) | |
| 266 | #define SE_SC_BUSY (1 << 29) | |
| 267 | #define SE_DB_BUSY (1 << 30) | |
| 268 | #define SE_CB_BUSY (1 << 31) | |
| 269 | #define GRBM_SOFT_RESET 0x8020 | |
| 270 | #define SOFT_RESET_CP (1 << 0) | |
| 271 | #define SOFT_RESET_CB (1 << 1) | |
| 272 | #define SOFT_RESET_DB (1 << 3) | |
| 273 | #define SOFT_RESET_GDS (1 << 4) | |
| 274 | #define SOFT_RESET_PA (1 << 5) | |
| 275 | #define SOFT_RESET_SC (1 << 6) | |
| 276 | #define SOFT_RESET_SPI (1 << 8) | |
| 277 | #define SOFT_RESET_SH (1 << 9) | |
| 278 | #define SOFT_RESET_SX (1 << 10) | |
| 279 | #define SOFT_RESET_TC (1 << 11) | |
| 280 | #define SOFT_RESET_TA (1 << 12) | |
| 281 | #define SOFT_RESET_VGT (1 << 14) | |
| 282 | #define SOFT_RESET_IA (1 << 15) | |
| 283 | ||
| 416a2bd2 AD |
284 | #define GRBM_GFX_INDEX 0x802C |
| 285 | #define INSTANCE_INDEX(x) ((x) << 0) | |
| 286 | #define SE_INDEX(x) ((x) << 16) | |
| 287 | #define INSTANCE_BROADCAST_WRITES (1 << 30) | |
| 288 | #define SE_BROADCAST_WRITES (1 << 31) | |
| 289 | ||
| 0c88a02e AD |
290 | #define SCRATCH_REG0 0x8500 |
| 291 | #define SCRATCH_REG1 0x8504 | |
| 292 | #define SCRATCH_REG2 0x8508 | |
| 293 | #define SCRATCH_REG3 0x850C | |
| 294 | #define SCRATCH_REG4 0x8510 | |
| 295 | #define SCRATCH_REG5 0x8514 | |
| 296 | #define SCRATCH_REG6 0x8518 | |
| 297 | #define SCRATCH_REG7 0x851C | |
| 298 | #define SCRATCH_UMSK 0x8540 | |
| 299 | #define SCRATCH_ADDR 0x8544 | |
| 300 | #define CP_SEM_WAIT_TIMER 0x85BC | |
| 11ef3f1f | 301 | #define CP_SEM_INCOMPLETE_TIMER_CNTL 0x85C8 |
| 721604a1 | 302 | #define CP_COHER_CNTL2 0x85E8 |
| 440a7cd8 JG |
303 | #define CP_STALLED_STAT1 0x8674 |
| 304 | #define CP_STALLED_STAT2 0x8678 | |
| 305 | #define CP_BUSY_STAT 0x867C | |
| 306 | #define CP_STAT 0x8680 | |
| 0c88a02e AD |
307 | #define CP_ME_CNTL 0x86D8 |
| 308 | #define CP_ME_HALT (1 << 28) | |
| 309 | #define CP_PFP_HALT (1 << 26) | |
| 310 | #define CP_RB2_RPTR 0x86f8 | |
| 311 | #define CP_RB1_RPTR 0x86fc | |
| 312 | #define CP_RB0_RPTR 0x8700 | |
| 313 | #define CP_RB_WPTR_DELAY 0x8704 | |
| fecf1d07 AD |
314 | #define CP_MEQ_THRESHOLDS 0x8764 |
| 315 | #define MEQ1_START(x) ((x) << 0) | |
| 316 | #define MEQ2_START(x) ((x) << 8) | |
| 317 | #define CP_PERFMON_CNTL 0x87FC | |
| 318 | ||
| 319 | #define VGT_CACHE_INVALIDATION 0x88C4 | |
| 320 | #define CACHE_INVALIDATION(x) ((x) << 0) | |
| 321 | #define VC_ONLY 0 | |
| 322 | #define TC_ONLY 1 | |
| 323 | #define VC_AND_TC 2 | |
| 324 | #define AUTO_INVLD_EN(x) ((x) << 6) | |
| 325 | #define NO_AUTO 0 | |
| 326 | #define ES_AUTO 1 | |
| 327 | #define GS_AUTO 2 | |
| 328 | #define ES_AND_GS_AUTO 3 | |
| 329 | #define VGT_GS_VERTEX_REUSE 0x88D4 | |
| 330 | ||
| 331 | #define CC_GC_SHADER_PIPE_CONFIG 0x8950 | |
| 332 | #define GC_USER_SHADER_PIPE_CONFIG 0x8954 | |
| 333 | #define INACTIVE_QD_PIPES(x) ((x) << 8) | |
| 334 | #define INACTIVE_QD_PIPES_MASK 0x0000FF00 | |
| 335 | #define INACTIVE_QD_PIPES_SHIFT 8 | |
| 336 | #define INACTIVE_SIMDS(x) ((x) << 16) | |
| 337 | #define INACTIVE_SIMDS_MASK 0xFFFF0000 | |
| 338 | #define INACTIVE_SIMDS_SHIFT 16 | |
| 339 | ||
| 340 | #define VGT_PRIMITIVE_TYPE 0x8958 | |
| 341 | #define VGT_NUM_INSTANCES 0x8974 | |
| 342 | #define VGT_TF_RING_SIZE 0x8988 | |
| 343 | #define VGT_OFFCHIP_LDS_BASE 0x89b4 | |
| 344 | ||
| 345 | #define PA_SC_LINE_STIPPLE_STATE 0x8B10 | |
| 346 | #define PA_CL_ENHANCE 0x8A14 | |
| 347 | #define CLIP_VTX_REORDER_ENA (1 << 0) | |
| 348 | #define NUM_CLIP_SEQ(x) ((x) << 1) | |
| 349 | #define PA_SC_FIFO_SIZE 0x8BCC | |
| 350 | #define SC_PRIM_FIFO_SIZE(x) ((x) << 0) | |
| 351 | #define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 12) | |
| 352 | #define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 20) | |
| 353 | #define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24 | |
| 354 | #define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0) | |
| 355 | #define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16) | |
| 356 | ||
| 357 | #define SQ_CONFIG 0x8C00 | |
| 358 | #define VC_ENABLE (1 << 0) | |
| 359 | #define EXPORT_SRC_C (1 << 1) | |
| 360 | #define GFX_PRIO(x) ((x) << 2) | |
| 361 | #define CS1_PRIO(x) ((x) << 4) | |
| 362 | #define CS2_PRIO(x) ((x) << 6) | |
| 363 | #define SQ_GPR_RESOURCE_MGMT_1 0x8C04 | |
| 364 | #define NUM_PS_GPRS(x) ((x) << 0) | |
| 365 | #define NUM_VS_GPRS(x) ((x) << 16) | |
| 366 | #define NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28) | |
| 367 | #define SQ_ESGS_RING_SIZE 0x8c44 | |
| 368 | #define SQ_GSVS_RING_SIZE 0x8c4c | |
| 369 | #define SQ_ESTMP_RING_BASE 0x8c50 | |
| 370 | #define SQ_ESTMP_RING_SIZE 0x8c54 | |
| 371 | #define SQ_GSTMP_RING_BASE 0x8c58 | |
| 372 | #define SQ_GSTMP_RING_SIZE 0x8c5c | |
| 373 | #define SQ_VSTMP_RING_BASE 0x8c60 | |
| 374 | #define SQ_VSTMP_RING_SIZE 0x8c64 | |
| 375 | #define SQ_PSTMP_RING_BASE 0x8c68 | |
| 376 | #define SQ_PSTMP_RING_SIZE 0x8c6c | |
| 377 | #define SQ_MS_FIFO_SIZES 0x8CF0 | |
| 378 | #define CACHE_FIFO_SIZE(x) ((x) << 0) | |
| 379 | #define FETCH_FIFO_HIWATER(x) ((x) << 8) | |
| 380 | #define DONE_FIFO_HIWATER(x) ((x) << 16) | |
| 381 | #define ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24) | |
| 382 | #define SQ_LSTMP_RING_BASE 0x8e10 | |
| 383 | #define SQ_LSTMP_RING_SIZE 0x8e14 | |
| 384 | #define SQ_HSTMP_RING_BASE 0x8e18 | |
| 385 | #define SQ_HSTMP_RING_SIZE 0x8e1c | |
| 386 | #define SQ_DYN_GPR_CNTL_PS_FLUSH_REQ 0x8D8C | |
| 387 | #define DYN_GPR_ENABLE (1 << 8) | |
| 388 | #define SQ_CONST_MEM_BASE 0x8df8 | |
| 389 | ||
| 390 | #define SX_EXPORT_BUFFER_SIZES 0x900C | |
| 391 | #define COLOR_BUFFER_SIZE(x) ((x) << 0) | |
| 392 | #define POSITION_BUFFER_SIZE(x) ((x) << 8) | |
| 393 | #define SMX_BUFFER_SIZE(x) ((x) << 16) | |
| 394 | #define SX_DEBUG_1 0x9058 | |
| 395 | #define ENABLE_NEW_SMX_ADDRESS (1 << 16) | |
| 396 | ||
| 397 | #define SPI_CONFIG_CNTL 0x9100 | |
| 398 | #define GPR_WRITE_PRIORITY(x) ((x) << 0) | |
| 399 | #define SPI_CONFIG_CNTL_1 0x913C | |
| 400 | #define VTX_DONE_DELAY(x) ((x) << 0) | |
| 401 | #define INTERP_ONE_PRIM_PER_ROW (1 << 4) | |
| 402 | #define CRC_SIMD_ID_WADDR_DISABLE (1 << 8) | |
| 403 | ||
| 404 | #define CGTS_TCC_DISABLE 0x9148 | |
| 405 | #define CGTS_USER_TCC_DISABLE 0x914C | |
| 406 | #define TCC_DISABLE_MASK 0xFFFF0000 | |
| 407 | #define TCC_DISABLE_SHIFT 16 | |
| 2498c41e | 408 | #define CGTS_SM_CTRL_REG 0x9150 |
| fecf1d07 AD |
409 | #define OVERRIDE (1 << 21) |
| 410 | ||
| 411 | #define TA_CNTL_AUX 0x9508 | |
| 412 | #define DISABLE_CUBE_WRAP (1 << 0) | |
| 413 | #define DISABLE_CUBE_ANISO (1 << 1) | |
| 414 | ||
| 415 | #define TCP_CHAN_STEER_LO 0x960c | |
| 416 | #define TCP_CHAN_STEER_HI 0x9610 | |
| 417 | ||
| 418 | #define CC_RB_BACKEND_DISABLE 0x98F4 | |
| 419 | #define BACKEND_DISABLE(x) ((x) << 16) | |
| 420 | #define GB_ADDR_CONFIG 0x98F8 | |
| 421 | #define NUM_PIPES(x) ((x) << 0) | |
| 422 | #define NUM_PIPES_MASK 0x00000007 | |
| 423 | #define NUM_PIPES_SHIFT 0 | |
| 424 | #define PIPE_INTERLEAVE_SIZE(x) ((x) << 4) | |
| 425 | #define PIPE_INTERLEAVE_SIZE_MASK 0x00000070 | |
| 426 | #define PIPE_INTERLEAVE_SIZE_SHIFT 4 | |
| 427 | #define BANK_INTERLEAVE_SIZE(x) ((x) << 8) | |
| 428 | #define NUM_SHADER_ENGINES(x) ((x) << 12) | |
| 429 | #define NUM_SHADER_ENGINES_MASK 0x00003000 | |
| 430 | #define NUM_SHADER_ENGINES_SHIFT 12 | |
| 431 | #define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16) | |
| 432 | #define SHADER_ENGINE_TILE_SIZE_MASK 0x00070000 | |
| 433 | #define SHADER_ENGINE_TILE_SIZE_SHIFT 16 | |
| 434 | #define NUM_GPUS(x) ((x) << 20) | |
| 435 | #define NUM_GPUS_MASK 0x00700000 | |
| 436 | #define NUM_GPUS_SHIFT 20 | |
| 437 | #define MULTI_GPU_TILE_SIZE(x) ((x) << 24) | |
| 438 | #define MULTI_GPU_TILE_SIZE_MASK 0x03000000 | |
| 439 | #define MULTI_GPU_TILE_SIZE_SHIFT 24 | |
| 440 | #define ROW_SIZE(x) ((x) << 28) | |
| bb92091a | 441 | #define ROW_SIZE_MASK 0x30000000 |
| fecf1d07 AD |
442 | #define ROW_SIZE_SHIFT 28 |
| 443 | #define NUM_LOWER_PIPES(x) ((x) << 30) | |
| 444 | #define NUM_LOWER_PIPES_MASK 0x40000000 | |
| 445 | #define NUM_LOWER_PIPES_SHIFT 30 | |
| 446 | #define GB_BACKEND_MAP 0x98FC | |
| 447 | ||
| 448 | #define CB_PERF_CTR0_SEL_0 0x9A20 | |
| 449 | #define CB_PERF_CTR0_SEL_1 0x9A24 | |
| 450 | #define CB_PERF_CTR1_SEL_0 0x9A28 | |
| 451 | #define CB_PERF_CTR1_SEL_1 0x9A2C | |
| 452 | #define CB_PERF_CTR2_SEL_0 0x9A30 | |
| 453 | #define CB_PERF_CTR2_SEL_1 0x9A34 | |
| 454 | #define CB_PERF_CTR3_SEL_0 0x9A38 | |
| 455 | #define CB_PERF_CTR3_SEL_1 0x9A3C | |
| 456 | ||
| 457 | #define GC_USER_RB_BACKEND_DISABLE 0x9B7C | |
| 458 | #define BACKEND_DISABLE_MASK 0x00FF0000 | |
| 459 | #define BACKEND_DISABLE_SHIFT 16 | |
| 460 | ||
| 461 | #define SMX_DC_CTL0 0xA020 | |
| 462 | #define USE_HASH_FUNCTION (1 << 0) | |
| 463 | #define NUMBER_OF_SETS(x) ((x) << 1) | |
| 464 | #define FLUSH_ALL_ON_EVENT (1 << 10) | |
| 465 | #define STALL_ON_EVENT (1 << 11) | |
| 466 | #define SMX_EVENT_CTL 0xA02C | |
| 467 | #define ES_FLUSH_CTL(x) ((x) << 0) | |
| 468 | #define GS_FLUSH_CTL(x) ((x) << 3) | |
| 469 | #define ACK_FLUSH_CTL(x) ((x) << 6) | |
| 470 | #define SYNC_FLUSH_CTL (1 << 8) | |
| 471 | ||
| 0c88a02e AD |
472 | #define CP_RB0_BASE 0xC100 |
| 473 | #define CP_RB0_CNTL 0xC104 | |
| 474 | #define RB_BUFSZ(x) ((x) << 0) | |
| 475 | #define RB_BLKSZ(x) ((x) << 8) | |
| 476 | #define RB_NO_UPDATE (1 << 27) | |
| 477 | #define RB_RPTR_WR_ENA (1 << 31) | |
| 478 | #define BUF_SWAP_32BIT (2 << 16) | |
| 479 | #define CP_RB0_RPTR_ADDR 0xC10C | |
| 480 | #define CP_RB0_RPTR_ADDR_HI 0xC110 | |
| 481 | #define CP_RB0_WPTR 0xC114 | |
| 1b37078b AD |
482 | |
| 483 | #define CP_INT_CNTL 0xC124 | |
| 484 | # define CNTX_BUSY_INT_ENABLE (1 << 19) | |
| 485 | # define CNTX_EMPTY_INT_ENABLE (1 << 20) | |
| 486 | # define TIME_STAMP_INT_ENABLE (1 << 26) | |
| 487 | ||
| 0c88a02e AD |
488 | #define CP_RB1_BASE 0xC180 |
| 489 | #define CP_RB1_CNTL 0xC184 | |
| 490 | #define CP_RB1_RPTR_ADDR 0xC188 | |
| 491 | #define CP_RB1_RPTR_ADDR_HI 0xC18C | |
| 492 | #define CP_RB1_WPTR 0xC190 | |
| 493 | #define CP_RB2_BASE 0xC194 | |
| 494 | #define CP_RB2_CNTL 0xC198 | |
| 495 | #define CP_RB2_RPTR_ADDR 0xC19C | |
| 496 | #define CP_RB2_RPTR_ADDR_HI 0xC1A0 | |
| 497 | #define CP_RB2_WPTR 0xC1A4 | |
| 498 | #define CP_PFP_UCODE_ADDR 0xC150 | |
| 499 | #define CP_PFP_UCODE_DATA 0xC154 | |
| 500 | #define CP_ME_RAM_RADDR 0xC158 | |
| 501 | #define CP_ME_RAM_WADDR 0xC15C | |
| 502 | #define CP_ME_RAM_DATA 0xC160 | |
| 503 | #define CP_DEBUG 0xC1FC | |
| 504 | ||
| b40e7e16 AD |
505 | #define VGT_EVENT_INITIATOR 0x28a90 |
| 506 | # define CACHE_FLUSH_AND_INV_EVENT_TS (0x14 << 0) | |
| 507 | # define CACHE_FLUSH_AND_INV_EVENT (0x16 << 0) | |
| 508 | ||
| 29a15221 AD |
509 | /* TN SMU registers */ |
| 510 | #define TN_CURRENT_GNB_TEMP 0x1F390 | |
| 511 | ||
| 69e0b57a AD |
512 | /* pm registers */ |
| 513 | #define SMC_MSG 0x20c | |
| 514 | #define HOST_SMC_MSG(x) ((x) << 0) | |
| 515 | #define HOST_SMC_MSG_MASK (0xff << 0) | |
| 516 | #define HOST_SMC_MSG_SHIFT 0 | |
| 517 | #define HOST_SMC_RESP(x) ((x) << 8) | |
| 518 | #define HOST_SMC_RESP_MASK (0xff << 8) | |
| 519 | #define HOST_SMC_RESP_SHIFT 8 | |
| 520 | #define SMC_HOST_MSG(x) ((x) << 16) | |
| 521 | #define SMC_HOST_MSG_MASK (0xff << 16) | |
| 522 | #define SMC_HOST_MSG_SHIFT 16 | |
| 523 | #define SMC_HOST_RESP(x) ((x) << 24) | |
| 524 | #define SMC_HOST_RESP_MASK (0xff << 24) | |
| 525 | #define SMC_HOST_RESP_SHIFT 24 | |
| 526 | ||
| 527 | #define CG_SPLL_FUNC_CNTL 0x600 | |
| 528 | #define SPLL_RESET (1 << 0) | |
| 529 | #define SPLL_SLEEP (1 << 1) | |
| 530 | #define SPLL_BYPASS_EN (1 << 3) | |
| 531 | #define SPLL_REF_DIV(x) ((x) << 4) | |
| 532 | #define SPLL_REF_DIV_MASK (0x3f << 4) | |
| 533 | #define SPLL_PDIV_A(x) ((x) << 20) | |
| 534 | #define SPLL_PDIV_A_MASK (0x7f << 20) | |
| 535 | #define SPLL_PDIV_A_SHIFT 20 | |
| 536 | #define CG_SPLL_FUNC_CNTL_2 0x604 | |
| 537 | #define SCLK_MUX_SEL(x) ((x) << 0) | |
| 538 | #define SCLK_MUX_SEL_MASK (0x1ff << 0) | |
| 539 | #define CG_SPLL_FUNC_CNTL_3 0x608 | |
| 540 | #define SPLL_FB_DIV(x) ((x) << 0) | |
| 541 | #define SPLL_FB_DIV_MASK (0x3ffffff << 0) | |
| 542 | #define SPLL_FB_DIV_SHIFT 0 | |
| 543 | #define SPLL_DITHEN (1 << 28) | |
| 544 | ||
| 545 | #define MPLL_CNTL_MODE 0x61c | |
| 546 | # define SS_SSEN (1 << 24) | |
| 547 | # define SS_DSMODE_EN (1 << 25) | |
| 548 | ||
| 549 | #define MPLL_AD_FUNC_CNTL 0x624 | |
| 550 | #define CLKF(x) ((x) << 0) | |
| 551 | #define CLKF_MASK (0x7f << 0) | |
| 552 | #define CLKR(x) ((x) << 7) | |
| 553 | #define CLKR_MASK (0x1f << 7) | |
| 554 | #define CLKFRAC(x) ((x) << 12) | |
| 555 | #define CLKFRAC_MASK (0x1f << 12) | |
| 556 | #define YCLK_POST_DIV(x) ((x) << 17) | |
| 557 | #define YCLK_POST_DIV_MASK (3 << 17) | |
| 558 | #define IBIAS(x) ((x) << 20) | |
| 559 | #define IBIAS_MASK (0x3ff << 20) | |
| 560 | #define RESET (1 << 30) | |
| 561 | #define PDNB (1 << 31) | |
| 562 | #define MPLL_AD_FUNC_CNTL_2 0x628 | |
| 563 | #define BYPASS (1 << 19) | |
| 564 | #define BIAS_GEN_PDNB (1 << 24) | |
| 565 | #define RESET_EN (1 << 25) | |
| 566 | #define VCO_MODE (1 << 29) | |
| 567 | #define MPLL_DQ_FUNC_CNTL 0x62c | |
| 568 | #define MPLL_DQ_FUNC_CNTL_2 0x630 | |
| 569 | ||
| 570 | #define GENERAL_PWRMGT 0x63c | |
| 571 | # define GLOBAL_PWRMGT_EN (1 << 0) | |
| 572 | # define STATIC_PM_EN (1 << 1) | |
| 573 | # define THERMAL_PROTECTION_DIS (1 << 2) | |
| 574 | # define THERMAL_PROTECTION_TYPE (1 << 3) | |
| 575 | # define ENABLE_GEN2PCIE (1 << 4) | |
| 576 | # define ENABLE_GEN2XSP (1 << 5) | |
| 577 | # define SW_SMIO_INDEX(x) ((x) << 6) | |
| 578 | # define SW_SMIO_INDEX_MASK (3 << 6) | |
| 579 | # define SW_SMIO_INDEX_SHIFT 6 | |
| 580 | # define LOW_VOLT_D2_ACPI (1 << 8) | |
| 581 | # define LOW_VOLT_D3_ACPI (1 << 9) | |
| 582 | # define VOLT_PWRMGT_EN (1 << 10) | |
| 583 | # define BACKBIAS_PAD_EN (1 << 18) | |
| 584 | # define BACKBIAS_VALUE (1 << 19) | |
| 585 | # define DYN_SPREAD_SPECTRUM_EN (1 << 23) | |
| 586 | # define AC_DC_SW (1 << 24) | |
| 587 | ||
| 588 | #define SCLK_PWRMGT_CNTL 0x644 | |
| 589 | # define SCLK_PWRMGT_OFF (1 << 0) | |
| 590 | # define SCLK_LOW_D1 (1 << 1) | |
| 591 | # define FIR_RESET (1 << 4) | |
| 592 | # define FIR_FORCE_TREND_SEL (1 << 5) | |
| 593 | # define FIR_TREND_MODE (1 << 6) | |
| 594 | # define DYN_GFX_CLK_OFF_EN (1 << 7) | |
| 595 | # define GFX_CLK_FORCE_ON (1 << 8) | |
| 596 | # define GFX_CLK_REQUEST_OFF (1 << 9) | |
| 597 | # define GFX_CLK_FORCE_OFF (1 << 10) | |
| 598 | # define GFX_CLK_OFF_ACPI_D1 (1 << 11) | |
| 599 | # define GFX_CLK_OFF_ACPI_D2 (1 << 12) | |
| 600 | # define GFX_CLK_OFF_ACPI_D3 (1 << 13) | |
| 601 | # define DYN_LIGHT_SLEEP_EN (1 << 14) | |
| 602 | #define MCLK_PWRMGT_CNTL 0x648 | |
| 603 | # define DLL_SPEED(x) ((x) << 0) | |
| 604 | # define DLL_SPEED_MASK (0x1f << 0) | |
| 605 | # define MPLL_PWRMGT_OFF (1 << 5) | |
| 606 | # define DLL_READY (1 << 6) | |
| 607 | # define MC_INT_CNTL (1 << 7) | |
| 608 | # define MRDCKA0_PDNB (1 << 8) | |
| 609 | # define MRDCKA1_PDNB (1 << 9) | |
| 610 | # define MRDCKB0_PDNB (1 << 10) | |
| 611 | # define MRDCKB1_PDNB (1 << 11) | |
| 612 | # define MRDCKC0_PDNB (1 << 12) | |
| 613 | # define MRDCKC1_PDNB (1 << 13) | |
| 614 | # define MRDCKD0_PDNB (1 << 14) | |
| 615 | # define MRDCKD1_PDNB (1 << 15) | |
| 616 | # define MRDCKA0_RESET (1 << 16) | |
| 617 | # define MRDCKA1_RESET (1 << 17) | |
| 618 | # define MRDCKB0_RESET (1 << 18) | |
| 619 | # define MRDCKB1_RESET (1 << 19) | |
| 620 | # define MRDCKC0_RESET (1 << 20) | |
| 621 | # define MRDCKC1_RESET (1 << 21) | |
| 622 | # define MRDCKD0_RESET (1 << 22) | |
| 623 | # define MRDCKD1_RESET (1 << 23) | |
| 624 | # define DLL_READY_READ (1 << 24) | |
| 625 | # define USE_DISPLAY_GAP (1 << 25) | |
| 626 | # define USE_DISPLAY_URGENT_NORMAL (1 << 26) | |
| 627 | # define MPLL_TURNOFF_D2 (1 << 28) | |
| 628 | #define DLL_CNTL 0x64c | |
| 629 | # define MRDCKA0_BYPASS (1 << 24) | |
| 630 | # define MRDCKA1_BYPASS (1 << 25) | |
| 631 | # define MRDCKB0_BYPASS (1 << 26) | |
| 632 | # define MRDCKB1_BYPASS (1 << 27) | |
| 633 | # define MRDCKC0_BYPASS (1 << 28) | |
| 634 | # define MRDCKC1_BYPASS (1 << 29) | |
| 635 | # define MRDCKD0_BYPASS (1 << 30) | |
| 636 | # define MRDCKD1_BYPASS (1 << 31) | |
| 637 | ||
| bdf0c4f0 AD |
638 | #define TARGET_AND_CURRENT_PROFILE_INDEX 0x66c |
| 639 | # define CURRENT_STATE_INDEX_MASK (0xf << 4) | |
| 640 | # define CURRENT_STATE_INDEX_SHIFT 4 | |
| 641 | ||
| 69e0b57a AD |
642 | #define CG_AT 0x6d4 |
| 643 | # define CG_R(x) ((x) << 0) | |
| 644 | # define CG_R_MASK (0xffff << 0) | |
| 645 | # define CG_L(x) ((x) << 16) | |
| 646 | # define CG_L_MASK (0xffff << 16) | |
| 647 | ||
| 648 | #define CG_BIF_REQ_AND_RSP 0x7f4 | |
| 649 | #define CG_CLIENT_REQ(x) ((x) << 0) | |
| 650 | #define CG_CLIENT_REQ_MASK (0xff << 0) | |
| 651 | #define CG_CLIENT_REQ_SHIFT 0 | |
| 652 | #define CG_CLIENT_RESP(x) ((x) << 8) | |
| 653 | #define CG_CLIENT_RESP_MASK (0xff << 8) | |
| 654 | #define CG_CLIENT_RESP_SHIFT 8 | |
| 655 | #define CLIENT_CG_REQ(x) ((x) << 16) | |
| 656 | #define CLIENT_CG_REQ_MASK (0xff << 16) | |
| 657 | #define CLIENT_CG_REQ_SHIFT 16 | |
| 658 | #define CLIENT_CG_RESP(x) ((x) << 24) | |
| 659 | #define CLIENT_CG_RESP_MASK (0xff << 24) | |
| 660 | #define CLIENT_CG_RESP_SHIFT 24 | |
| 661 | ||
| 662 | #define CG_SPLL_SPREAD_SPECTRUM 0x790 | |
| 663 | #define SSEN (1 << 0) | |
| 664 | #define CLK_S(x) ((x) << 4) | |
| 665 | #define CLK_S_MASK (0xfff << 4) | |
| 666 | #define CLK_S_SHIFT 4 | |
| 667 | #define CG_SPLL_SPREAD_SPECTRUM_2 0x794 | |
| 668 | #define CLK_V(x) ((x) << 0) | |
| 669 | #define CLK_V_MASK (0x3ffffff << 0) | |
| 670 | #define CLK_V_SHIFT 0 | |
| 671 | ||
| 672 | #define SMC_SCRATCH0 0x81c | |
| 673 | ||
| 674 | #define CG_SPLL_FUNC_CNTL_4 0x850 | |
| 675 | ||
| 676 | #define MPLL_SS1 0x85c | |
| 677 | #define CLKV(x) ((x) << 0) | |
| 678 | #define CLKV_MASK (0x3ffffff << 0) | |
| 679 | #define MPLL_SS2 0x860 | |
| 680 | #define CLKS(x) ((x) << 0) | |
| 681 | #define CLKS_MASK (0xfff << 0) | |
| 682 | ||
| 683 | #define CG_CAC_CTRL 0x88c | |
| 684 | #define TID_CNT(x) ((x) << 0) | |
| 685 | #define TID_CNT_MASK (0x3fff << 0) | |
| 686 | #define TID_UNIT(x) ((x) << 14) | |
| 687 | #define TID_UNIT_MASK (0xf << 14) | |
| 688 | ||
| 8ba10463 AD |
689 | #define CG_IND_ADDR 0x8f8 |
| 690 | #define CG_IND_DATA 0x8fc | |
| 691 | /* CGIND regs */ | |
| 692 | #define CG_CGTT_LOCAL_0 0x00 | |
| 693 | #define CG_CGTT_LOCAL_1 0x01 | |
| 694 | ||
| 69e0b57a AD |
695 | #define MC_CG_CONFIG 0x25bc |
| 696 | #define MCDW_WR_ENABLE (1 << 0) | |
| 697 | #define MCDX_WR_ENABLE (1 << 1) | |
| 698 | #define MCDY_WR_ENABLE (1 << 2) | |
| 699 | #define MCDZ_WR_ENABLE (1 << 3) | |
| 700 | #define MC_RD_ENABLE(x) ((x) << 4) | |
| 701 | #define MC_RD_ENABLE_MASK (3 << 4) | |
| 702 | #define INDEX(x) ((x) << 6) | |
| 703 | #define INDEX_MASK (0xfff << 6) | |
| 704 | #define INDEX_SHIFT 6 | |
| 705 | ||
| 706 | #define MC_ARB_CAC_CNTL 0x2750 | |
| 707 | #define ENABLE (1 << 0) | |
| 708 | #define READ_WEIGHT(x) ((x) << 1) | |
| 709 | #define READ_WEIGHT_MASK (0x3f << 1) | |
| 710 | #define READ_WEIGHT_SHIFT 1 | |
| 711 | #define WRITE_WEIGHT(x) ((x) << 7) | |
| 712 | #define WRITE_WEIGHT_MASK (0x3f << 7) | |
| 713 | #define WRITE_WEIGHT_SHIFT 7 | |
| 714 | #define ALLOW_OVERFLOW (1 << 13) | |
| 715 | ||
| 716 | #define MC_ARB_DRAM_TIMING 0x2774 | |
| 717 | #define MC_ARB_DRAM_TIMING2 0x2778 | |
| 718 | ||
| 719 | #define MC_ARB_RFSH_RATE 0x27b0 | |
| 720 | #define POWERMODE0(x) ((x) << 0) | |
| 721 | #define POWERMODE0_MASK (0xff << 0) | |
| 722 | #define POWERMODE0_SHIFT 0 | |
| 723 | #define POWERMODE1(x) ((x) << 8) | |
| 724 | #define POWERMODE1_MASK (0xff << 8) | |
| 725 | #define POWERMODE1_SHIFT 8 | |
| 726 | #define POWERMODE2(x) ((x) << 16) | |
| 727 | #define POWERMODE2_MASK (0xff << 16) | |
| 728 | #define POWERMODE2_SHIFT 16 | |
| 729 | #define POWERMODE3(x) ((x) << 24) | |
| 730 | #define POWERMODE3_MASK (0xff << 24) | |
| 731 | #define POWERMODE3_SHIFT 24 | |
| 732 | ||
| 733 | #define MC_ARB_CG 0x27e8 | |
| 734 | #define CG_ARB_REQ(x) ((x) << 0) | |
| 735 | #define CG_ARB_REQ_MASK (0xff << 0) | |
| 736 | #define CG_ARB_REQ_SHIFT 0 | |
| 737 | #define CG_ARB_RESP(x) ((x) << 8) | |
| 738 | #define CG_ARB_RESP_MASK (0xff << 8) | |
| 739 | #define CG_ARB_RESP_SHIFT 8 | |
| 740 | #define ARB_CG_REQ(x) ((x) << 16) | |
| 741 | #define ARB_CG_REQ_MASK (0xff << 16) | |
| 742 | #define ARB_CG_REQ_SHIFT 16 | |
| 743 | #define ARB_CG_RESP(x) ((x) << 24) | |
| 744 | #define ARB_CG_RESP_MASK (0xff << 24) | |
| 745 | #define ARB_CG_RESP_SHIFT 24 | |
| 746 | ||
| 747 | #define MC_ARB_DRAM_TIMING_1 0x27f0 | |
| 748 | #define MC_ARB_DRAM_TIMING_2 0x27f4 | |
| 749 | #define MC_ARB_DRAM_TIMING_3 0x27f8 | |
| 750 | #define MC_ARB_DRAM_TIMING2_1 0x27fc | |
| 751 | #define MC_ARB_DRAM_TIMING2_2 0x2800 | |
| 752 | #define MC_ARB_DRAM_TIMING2_3 0x2804 | |
| 753 | #define MC_ARB_BURST_TIME 0x2808 | |
| 754 | #define STATE0(x) ((x) << 0) | |
| 755 | #define STATE0_MASK (0x1f << 0) | |
| 756 | #define STATE0_SHIFT 0 | |
| 757 | #define STATE1(x) ((x) << 5) | |
| 758 | #define STATE1_MASK (0x1f << 5) | |
| 759 | #define STATE1_SHIFT 5 | |
| 760 | #define STATE2(x) ((x) << 10) | |
| 761 | #define STATE2_MASK (0x1f << 10) | |
| 762 | #define STATE2_SHIFT 10 | |
| 763 | #define STATE3(x) ((x) << 15) | |
| 764 | #define STATE3_MASK (0x1f << 15) | |
| 765 | #define STATE3_SHIFT 15 | |
| 766 | ||
| 767 | #define MC_CG_DATAPORT 0x2884 | |
| 768 | ||
| 769 | #define MC_SEQ_RAS_TIMING 0x28a0 | |
| 770 | #define MC_SEQ_CAS_TIMING 0x28a4 | |
| 771 | #define MC_SEQ_MISC_TIMING 0x28a8 | |
| 772 | #define MC_SEQ_MISC_TIMING2 0x28ac | |
| 773 | #define MC_SEQ_PMG_TIMING 0x28b0 | |
| 774 | #define MC_SEQ_RD_CTL_D0 0x28b4 | |
| 775 | #define MC_SEQ_RD_CTL_D1 0x28b8 | |
| 776 | #define MC_SEQ_WR_CTL_D0 0x28bc | |
| 777 | #define MC_SEQ_WR_CTL_D1 0x28c0 | |
| 778 | ||
| 779 | #define MC_SEQ_MISC0 0x2a00 | |
| 780 | #define MC_SEQ_MISC0_GDDR5_SHIFT 28 | |
| 781 | #define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000 | |
| 782 | #define MC_SEQ_MISC0_GDDR5_VALUE 5 | |
| 783 | #define MC_SEQ_MISC1 0x2a04 | |
| 784 | #define MC_SEQ_RESERVE_M 0x2a08 | |
| 785 | #define MC_PMG_CMD_EMRS 0x2a0c | |
| 786 | ||
| 787 | #define MC_SEQ_MISC3 0x2a2c | |
| 788 | ||
| 789 | #define MC_SEQ_MISC5 0x2a54 | |
| 790 | #define MC_SEQ_MISC6 0x2a58 | |
| 791 | ||
| 792 | #define MC_SEQ_MISC7 0x2a64 | |
| 793 | ||
| 794 | #define MC_SEQ_RAS_TIMING_LP 0x2a6c | |
| 795 | #define MC_SEQ_CAS_TIMING_LP 0x2a70 | |
| 796 | #define MC_SEQ_MISC_TIMING_LP 0x2a74 | |
| 797 | #define MC_SEQ_MISC_TIMING2_LP 0x2a78 | |
| 798 | #define MC_SEQ_WR_CTL_D0_LP 0x2a7c | |
| 799 | #define MC_SEQ_WR_CTL_D1_LP 0x2a80 | |
| 800 | #define MC_SEQ_PMG_CMD_EMRS_LP 0x2a84 | |
| 801 | #define MC_SEQ_PMG_CMD_MRS_LP 0x2a88 | |
| 802 | ||
| 803 | #define MC_PMG_CMD_MRS 0x2aac | |
| 804 | ||
| 805 | #define MC_SEQ_RD_CTL_D0_LP 0x2b1c | |
| 806 | #define MC_SEQ_RD_CTL_D1_LP 0x2b20 | |
| 807 | ||
| 808 | #define MC_PMG_CMD_MRS1 0x2b44 | |
| 809 | #define MC_SEQ_PMG_CMD_MRS1_LP 0x2b48 | |
| 810 | #define MC_SEQ_PMG_TIMING_LP 0x2b4c | |
| 811 | ||
| 812 | #define MC_PMG_CMD_MRS2 0x2b5c | |
| 813 | #define MC_SEQ_PMG_CMD_MRS2_LP 0x2b60 | |
| 814 | ||
| 815 | #define LB_SYNC_RESET_SEL 0x6b28 | |
| 816 | #define LB_SYNC_RESET_SEL_MASK (3 << 0) | |
| 817 | #define LB_SYNC_RESET_SEL_SHIFT 0 | |
| 818 | ||
| 819 | #define DC_STUTTER_CNTL 0x6b30 | |
| 820 | #define DC_STUTTER_ENABLE_A (1 << 0) | |
| 821 | #define DC_STUTTER_ENABLE_B (1 << 1) | |
| 822 | ||
| 823 | #define SQ_CAC_THRESHOLD 0x8e4c | |
| 824 | #define VSP(x) ((x) << 0) | |
| 825 | #define VSP_MASK (0xff << 0) | |
| 826 | #define VSP_SHIFT 0 | |
| 827 | #define VSP0(x) ((x) << 8) | |
| 828 | #define VSP0_MASK (0xff << 8) | |
| 829 | #define VSP0_SHIFT 8 | |
| 830 | #define GPR(x) ((x) << 16) | |
| 831 | #define GPR_MASK (0xff << 16) | |
| 832 | #define GPR_SHIFT 16 | |
| 833 | ||
| 834 | #define SQ_POWER_THROTTLE 0x8e58 | |
| 835 | #define MIN_POWER(x) ((x) << 0) | |
| 836 | #define MIN_POWER_MASK (0x3fff << 0) | |
| 837 | #define MIN_POWER_SHIFT 0 | |
| 838 | #define MAX_POWER(x) ((x) << 16) | |
| 839 | #define MAX_POWER_MASK (0x3fff << 16) | |
| 840 | #define MAX_POWER_SHIFT 0 | |
| 841 | #define SQ_POWER_THROTTLE2 0x8e5c | |
| 842 | #define MAX_POWER_DELTA(x) ((x) << 0) | |
| 843 | #define MAX_POWER_DELTA_MASK (0x3fff << 0) | |
| 844 | #define MAX_POWER_DELTA_SHIFT 0 | |
| 845 | #define STI_SIZE(x) ((x) << 16) | |
| 846 | #define STI_SIZE_MASK (0x3ff << 16) | |
| 847 | #define STI_SIZE_SHIFT 16 | |
| 848 | #define LTI_RATIO(x) ((x) << 27) | |
| 849 | #define LTI_RATIO_MASK (0xf << 27) | |
| 850 | #define LTI_RATIO_SHIFT 27 | |
| 851 | ||
| 852 | /* CG indirect registers */ | |
| 853 | #define CG_CAC_REGION_1_WEIGHT_0 0x83 | |
| 854 | #define WEIGHT_TCP_SIG0(x) ((x) << 0) | |
| 855 | #define WEIGHT_TCP_SIG0_MASK (0x3f << 0) | |
| 856 | #define WEIGHT_TCP_SIG0_SHIFT 0 | |
| 857 | #define WEIGHT_TCP_SIG1(x) ((x) << 6) | |
| 858 | #define WEIGHT_TCP_SIG1_MASK (0x3f << 6) | |
| 859 | #define WEIGHT_TCP_SIG1_SHIFT 6 | |
| 860 | #define WEIGHT_TA_SIG(x) ((x) << 12) | |
| 861 | #define WEIGHT_TA_SIG_MASK (0x3f << 12) | |
| 862 | #define WEIGHT_TA_SIG_SHIFT 12 | |
| 863 | #define CG_CAC_REGION_1_WEIGHT_1 0x84 | |
| 864 | #define WEIGHT_TCC_EN0(x) ((x) << 0) | |
| 865 | #define WEIGHT_TCC_EN0_MASK (0x3f << 0) | |
| 866 | #define WEIGHT_TCC_EN0_SHIFT 0 | |
| 867 | #define WEIGHT_TCC_EN1(x) ((x) << 6) | |
| 868 | #define WEIGHT_TCC_EN1_MASK (0x3f << 6) | |
| 869 | #define WEIGHT_TCC_EN1_SHIFT 6 | |
| 870 | #define WEIGHT_TCC_EN2(x) ((x) << 12) | |
| 871 | #define WEIGHT_TCC_EN2_MASK (0x3f << 12) | |
| 872 | #define WEIGHT_TCC_EN2_SHIFT 12 | |
| 873 | #define WEIGHT_TCC_EN3(x) ((x) << 18) | |
| 874 | #define WEIGHT_TCC_EN3_MASK (0x3f << 18) | |
| 875 | #define WEIGHT_TCC_EN3_SHIFT 18 | |
| 876 | #define CG_CAC_REGION_2_WEIGHT_0 0x85 | |
| 877 | #define WEIGHT_CB_EN0(x) ((x) << 0) | |
| 878 | #define WEIGHT_CB_EN0_MASK (0x3f << 0) | |
| 879 | #define WEIGHT_CB_EN0_SHIFT 0 | |
| 880 | #define WEIGHT_CB_EN1(x) ((x) << 6) | |
| 881 | #define WEIGHT_CB_EN1_MASK (0x3f << 6) | |
| 882 | #define WEIGHT_CB_EN1_SHIFT 6 | |
| 883 | #define WEIGHT_CB_EN2(x) ((x) << 12) | |
| 884 | #define WEIGHT_CB_EN2_MASK (0x3f << 12) | |
| 885 | #define WEIGHT_CB_EN2_SHIFT 12 | |
| 886 | #define WEIGHT_CB_EN3(x) ((x) << 18) | |
| 887 | #define WEIGHT_CB_EN3_MASK (0x3f << 18) | |
| 888 | #define WEIGHT_CB_EN3_SHIFT 18 | |
| 889 | #define CG_CAC_REGION_2_WEIGHT_1 0x86 | |
| 890 | #define WEIGHT_DB_SIG0(x) ((x) << 0) | |
| 891 | #define WEIGHT_DB_SIG0_MASK (0x3f << 0) | |
| 892 | #define WEIGHT_DB_SIG0_SHIFT 0 | |
| 893 | #define WEIGHT_DB_SIG1(x) ((x) << 6) | |
| 894 | #define WEIGHT_DB_SIG1_MASK (0x3f << 6) | |
| 895 | #define WEIGHT_DB_SIG1_SHIFT 6 | |
| 896 | #define WEIGHT_DB_SIG2(x) ((x) << 12) | |
| 897 | #define WEIGHT_DB_SIG2_MASK (0x3f << 12) | |
| 898 | #define WEIGHT_DB_SIG2_SHIFT 12 | |
| 899 | #define WEIGHT_DB_SIG3(x) ((x) << 18) | |
| 900 | #define WEIGHT_DB_SIG3_MASK (0x3f << 18) | |
| 901 | #define WEIGHT_DB_SIG3_SHIFT 18 | |
| 902 | #define CG_CAC_REGION_2_WEIGHT_2 0x87 | |
| 903 | #define WEIGHT_SXM_SIG0(x) ((x) << 0) | |
| 904 | #define WEIGHT_SXM_SIG0_MASK (0x3f << 0) | |
| 905 | #define WEIGHT_SXM_SIG0_SHIFT 0 | |
| 906 | #define WEIGHT_SXM_SIG1(x) ((x) << 6) | |
| 907 | #define WEIGHT_SXM_SIG1_MASK (0x3f << 6) | |
| 908 | #define WEIGHT_SXM_SIG1_SHIFT 6 | |
| 909 | #define WEIGHT_SXM_SIG2(x) ((x) << 12) | |
| 910 | #define WEIGHT_SXM_SIG2_MASK (0x3f << 12) | |
| 911 | #define WEIGHT_SXM_SIG2_SHIFT 12 | |
| 912 | #define WEIGHT_SXS_SIG0(x) ((x) << 18) | |
| 913 | #define WEIGHT_SXS_SIG0_MASK (0x3f << 18) | |
| 914 | #define WEIGHT_SXS_SIG0_SHIFT 18 | |
| 915 | #define WEIGHT_SXS_SIG1(x) ((x) << 24) | |
| 916 | #define WEIGHT_SXS_SIG1_MASK (0x3f << 24) | |
| 917 | #define WEIGHT_SXS_SIG1_SHIFT 24 | |
| 918 | #define CG_CAC_REGION_3_WEIGHT_0 0x88 | |
| 919 | #define WEIGHT_XBR_0(x) ((x) << 0) | |
| 920 | #define WEIGHT_XBR_0_MASK (0x3f << 0) | |
| 921 | #define WEIGHT_XBR_0_SHIFT 0 | |
| 922 | #define WEIGHT_XBR_1(x) ((x) << 6) | |
| 923 | #define WEIGHT_XBR_1_MASK (0x3f << 6) | |
| 924 | #define WEIGHT_XBR_1_SHIFT 6 | |
| 925 | #define WEIGHT_XBR_2(x) ((x) << 12) | |
| 926 | #define WEIGHT_XBR_2_MASK (0x3f << 12) | |
| 927 | #define WEIGHT_XBR_2_SHIFT 12 | |
| 928 | #define WEIGHT_SPI_SIG0(x) ((x) << 18) | |
| 929 | #define WEIGHT_SPI_SIG0_MASK (0x3f << 18) | |
| 930 | #define WEIGHT_SPI_SIG0_SHIFT 18 | |
| 931 | #define CG_CAC_REGION_3_WEIGHT_1 0x89 | |
| 932 | #define WEIGHT_SPI_SIG1(x) ((x) << 0) | |
| 933 | #define WEIGHT_SPI_SIG1_MASK (0x3f << 0) | |
| 934 | #define WEIGHT_SPI_SIG1_SHIFT 0 | |
| 935 | #define WEIGHT_SPI_SIG2(x) ((x) << 6) | |
| 936 | #define WEIGHT_SPI_SIG2_MASK (0x3f << 6) | |
| 937 | #define WEIGHT_SPI_SIG2_SHIFT 6 | |
| 938 | #define WEIGHT_SPI_SIG3(x) ((x) << 12) | |
| 939 | #define WEIGHT_SPI_SIG3_MASK (0x3f << 12) | |
| 940 | #define WEIGHT_SPI_SIG3_SHIFT 12 | |
| 941 | #define WEIGHT_SPI_SIG4(x) ((x) << 18) | |
| 942 | #define WEIGHT_SPI_SIG4_MASK (0x3f << 18) | |
| 943 | #define WEIGHT_SPI_SIG4_SHIFT 18 | |
| 944 | #define WEIGHT_SPI_SIG5(x) ((x) << 24) | |
| 945 | #define WEIGHT_SPI_SIG5_MASK (0x3f << 24) | |
| 946 | #define WEIGHT_SPI_SIG5_SHIFT 24 | |
| 947 | #define CG_CAC_REGION_4_WEIGHT_0 0x8a | |
| 948 | #define WEIGHT_LDS_SIG0(x) ((x) << 0) | |
| 949 | #define WEIGHT_LDS_SIG0_MASK (0x3f << 0) | |
| 950 | #define WEIGHT_LDS_SIG0_SHIFT 0 | |
| 951 | #define WEIGHT_LDS_SIG1(x) ((x) << 6) | |
| 952 | #define WEIGHT_LDS_SIG1_MASK (0x3f << 6) | |
| 953 | #define WEIGHT_LDS_SIG1_SHIFT 6 | |
| 954 | #define WEIGHT_SC(x) ((x) << 24) | |
| 955 | #define WEIGHT_SC_MASK (0x3f << 24) | |
| 956 | #define WEIGHT_SC_SHIFT 24 | |
| 957 | #define CG_CAC_REGION_4_WEIGHT_1 0x8b | |
| 958 | #define WEIGHT_BIF(x) ((x) << 0) | |
| 959 | #define WEIGHT_BIF_MASK (0x3f << 0) | |
| 960 | #define WEIGHT_BIF_SHIFT 0 | |
| 961 | #define WEIGHT_CP(x) ((x) << 6) | |
| 962 | #define WEIGHT_CP_MASK (0x3f << 6) | |
| 963 | #define WEIGHT_CP_SHIFT 6 | |
| 964 | #define WEIGHT_PA_SIG0(x) ((x) << 12) | |
| 965 | #define WEIGHT_PA_SIG0_MASK (0x3f << 12) | |
| 966 | #define WEIGHT_PA_SIG0_SHIFT 12 | |
| 967 | #define WEIGHT_PA_SIG1(x) ((x) << 18) | |
| 968 | #define WEIGHT_PA_SIG1_MASK (0x3f << 18) | |
| 969 | #define WEIGHT_PA_SIG1_SHIFT 18 | |
| 970 | #define WEIGHT_VGT_SIG0(x) ((x) << 24) | |
| 971 | #define WEIGHT_VGT_SIG0_MASK (0x3f << 24) | |
| 972 | #define WEIGHT_VGT_SIG0_SHIFT 24 | |
| 973 | #define CG_CAC_REGION_4_WEIGHT_2 0x8c | |
| 974 | #define WEIGHT_VGT_SIG1(x) ((x) << 0) | |
| 975 | #define WEIGHT_VGT_SIG1_MASK (0x3f << 0) | |
| 976 | #define WEIGHT_VGT_SIG1_SHIFT 0 | |
| 977 | #define WEIGHT_VGT_SIG2(x) ((x) << 6) | |
| 978 | #define WEIGHT_VGT_SIG2_MASK (0x3f << 6) | |
| 979 | #define WEIGHT_VGT_SIG2_SHIFT 6 | |
| 980 | #define WEIGHT_DC_SIG0(x) ((x) << 12) | |
| 981 | #define WEIGHT_DC_SIG0_MASK (0x3f << 12) | |
| 982 | #define WEIGHT_DC_SIG0_SHIFT 12 | |
| 983 | #define WEIGHT_DC_SIG1(x) ((x) << 18) | |
| 984 | #define WEIGHT_DC_SIG1_MASK (0x3f << 18) | |
| 985 | #define WEIGHT_DC_SIG1_SHIFT 18 | |
| 986 | #define WEIGHT_DC_SIG2(x) ((x) << 24) | |
| 987 | #define WEIGHT_DC_SIG2_MASK (0x3f << 24) | |
| 988 | #define WEIGHT_DC_SIG2_SHIFT 24 | |
| 989 | #define CG_CAC_REGION_4_WEIGHT_3 0x8d | |
| 990 | #define WEIGHT_DC_SIG3(x) ((x) << 0) | |
| 991 | #define WEIGHT_DC_SIG3_MASK (0x3f << 0) | |
| 992 | #define WEIGHT_DC_SIG3_SHIFT 0 | |
| 993 | #define WEIGHT_UVD_SIG0(x) ((x) << 6) | |
| 994 | #define WEIGHT_UVD_SIG0_MASK (0x3f << 6) | |
| 995 | #define WEIGHT_UVD_SIG0_SHIFT 6 | |
| 996 | #define WEIGHT_UVD_SIG1(x) ((x) << 12) | |
| 997 | #define WEIGHT_UVD_SIG1_MASK (0x3f << 12) | |
| 998 | #define WEIGHT_UVD_SIG1_SHIFT 12 | |
| 999 | #define WEIGHT_SPARE0(x) ((x) << 18) | |
| 1000 | #define WEIGHT_SPARE0_MASK (0x3f << 18) | |
| 1001 | #define WEIGHT_SPARE0_SHIFT 18 | |
| 1002 | #define WEIGHT_SPARE1(x) ((x) << 24) | |
| 1003 | #define WEIGHT_SPARE1_MASK (0x3f << 24) | |
| 1004 | #define WEIGHT_SPARE1_SHIFT 24 | |
| 1005 | #define CG_CAC_REGION_5_WEIGHT_0 0x8e | |
| 1006 | #define WEIGHT_SQ_VSP(x) ((x) << 0) | |
| 1007 | #define WEIGHT_SQ_VSP_MASK (0x3fff << 0) | |
| 1008 | #define WEIGHT_SQ_VSP_SHIFT 0 | |
| 1009 | #define WEIGHT_SQ_VSP0(x) ((x) << 14) | |
| 1010 | #define WEIGHT_SQ_VSP0_MASK (0x3fff << 14) | |
| 1011 | #define WEIGHT_SQ_VSP0_SHIFT 14 | |
| 1012 | #define CG_CAC_REGION_4_OVERRIDE_4 0xab | |
| 1013 | #define OVR_MODE_SPARE_0(x) ((x) << 16) | |
| 1014 | #define OVR_MODE_SPARE_0_MASK (0x1 << 16) | |
| 1015 | #define OVR_MODE_SPARE_0_SHIFT 16 | |
| 1016 | #define OVR_VAL_SPARE_0(x) ((x) << 17) | |
| 1017 | #define OVR_VAL_SPARE_0_MASK (0x1 << 17) | |
| 1018 | #define OVR_VAL_SPARE_0_SHIFT 17 | |
| 1019 | #define OVR_MODE_SPARE_1(x) ((x) << 18) | |
| 1020 | #define OVR_MODE_SPARE_1_MASK (0x3f << 18) | |
| 1021 | #define OVR_MODE_SPARE_1_SHIFT 18 | |
| 1022 | #define OVR_VAL_SPARE_1(x) ((x) << 19) | |
| 1023 | #define OVR_VAL_SPARE_1_MASK (0x3f << 19) | |
| 1024 | #define OVR_VAL_SPARE_1_SHIFT 19 | |
| 1025 | #define CG_CAC_REGION_5_WEIGHT_1 0xb7 | |
| 1026 | #define WEIGHT_SQ_GPR(x) ((x) << 0) | |
| 1027 | #define WEIGHT_SQ_GPR_MASK (0x3fff << 0) | |
| 1028 | #define WEIGHT_SQ_GPR_SHIFT 0 | |
| 1029 | #define WEIGHT_SQ_LDS(x) ((x) << 14) | |
| 1030 | #define WEIGHT_SQ_LDS_MASK (0x3fff << 14) | |
| 1031 | #define WEIGHT_SQ_LDS_SHIFT 14 | |
| 1032 | ||
| 1033 | /* PCIE link stuff */ | |
| 1034 | #define PCIE_LC_TRAINING_CNTL 0xa1 /* PCIE_P */ | |
| 1035 | #define PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */ | |
| 1036 | # define LC_LINK_WIDTH_SHIFT 0 | |
| 1037 | # define LC_LINK_WIDTH_MASK 0x7 | |
| 1038 | # define LC_LINK_WIDTH_X0 0 | |
| 1039 | # define LC_LINK_WIDTH_X1 1 | |
| 1040 | # define LC_LINK_WIDTH_X2 2 | |
| 1041 | # define LC_LINK_WIDTH_X4 3 | |
| 1042 | # define LC_LINK_WIDTH_X8 4 | |
| 1043 | # define LC_LINK_WIDTH_X16 6 | |
| 1044 | # define LC_LINK_WIDTH_RD_SHIFT 4 | |
| 1045 | # define LC_LINK_WIDTH_RD_MASK 0x70 | |
| 1046 | # define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7) | |
| 1047 | # define LC_RECONFIG_NOW (1 << 8) | |
| 1048 | # define LC_RENEGOTIATION_SUPPORT (1 << 9) | |
| 1049 | # define LC_RENEGOTIATE_EN (1 << 10) | |
| 1050 | # define LC_SHORT_RECONFIG_EN (1 << 11) | |
| 1051 | # define LC_UPCONFIGURE_SUPPORT (1 << 12) | |
| 1052 | # define LC_UPCONFIGURE_DIS (1 << 13) | |
| 1053 | #define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */ | |
| 1054 | # define LC_GEN2_EN_STRAP (1 << 0) | |
| 1055 | # define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 1) | |
| 1056 | # define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 5) | |
| 1057 | # define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 6) | |
| 1058 | # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 8) | |
| 1059 | # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 3 | |
| 1060 | # define LC_CURRENT_DATA_RATE (1 << 11) | |
| 1061 | # define LC_HW_VOLTAGE_IF_CONTROL(x) ((x) << 12) | |
| 1062 | # define LC_HW_VOLTAGE_IF_CONTROL_MASK (3 << 12) | |
| 1063 | # define LC_HW_VOLTAGE_IF_CONTROL_SHIFT 12 | |
| 1064 | # define LC_VOLTAGE_TIMER_SEL_MASK (0xf << 14) | |
| 1065 | # define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 21) | |
| 1066 | # define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 23) | |
| 1067 | # define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 24) | |
| 1068 | #define MM_CFGREGS_CNTL 0x544c | |
| 1069 | # define MM_WR_TO_CFG_EN (1 << 3) | |
| 1070 | #define LINK_CNTL2 0x88 /* F0 */ | |
| 1071 | # define TARGET_LINK_SPEED_MASK (0xf << 0) | |
| 1072 | # define SELECTABLE_DEEMPHASIS (1 << 6) | |
| 1073 | ||
| f2ba57b5 CK |
1074 | /* |
| 1075 | * UVD | |
| 1076 | */ | |
| 1077 | #define UVD_SEMA_ADDR_LOW 0xEF00 | |
| 1078 | #define UVD_SEMA_ADDR_HIGH 0xEF04 | |
| 1079 | #define UVD_SEMA_CMD 0xEF08 | |
| 9a21059d CK |
1080 | #define UVD_UDEC_ADDR_CONFIG 0xEF4C |
| 1081 | #define UVD_UDEC_DB_ADDR_CONFIG 0xEF50 | |
| 1082 | #define UVD_UDEC_DBW_ADDR_CONFIG 0xEF54 | |
| f2ba57b5 CK |
1083 | #define UVD_RBC_RB_RPTR 0xF690 |
| 1084 | #define UVD_RBC_RB_WPTR 0xF694 | |
| 1085 | ||
| 0c88a02e AD |
1086 | /* |
| 1087 | * PM4 | |
| 1088 | */ | |
| 4e872ae2 | 1089 | #define PACKET0(reg, n) ((RADEON_PACKET_TYPE0 << 30) | \ |
| 0c88a02e AD |
1090 | (((reg) >> 2) & 0xFFFF) | \ |
| 1091 | ((n) & 0x3FFF) << 16) | |
| 1092 | #define CP_PACKET2 0x80000000 | |
| 1093 | #define PACKET2_PAD_SHIFT 0 | |
| 1094 | #define PACKET2_PAD_MASK (0x3fffffff << 0) | |
| 1095 | ||
| 1096 | #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) | |
| 1097 | ||
| 4e872ae2 | 1098 | #define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \ |
| 0c88a02e AD |
1099 | (((op) & 0xFF) << 8) | \ |
| 1100 | ((n) & 0x3FFF) << 16) | |
| 1101 | ||
| 1102 | /* Packet 3 types */ | |
| 1103 | #define PACKET3_NOP 0x10 | |
| 1104 | #define PACKET3_SET_BASE 0x11 | |
| 1105 | #define PACKET3_CLEAR_STATE 0x12 | |
| 1106 | #define PACKET3_INDEX_BUFFER_SIZE 0x13 | |
| 1107 | #define PACKET3_DEALLOC_STATE 0x14 | |
| 1108 | #define PACKET3_DISPATCH_DIRECT 0x15 | |
| 1109 | #define PACKET3_DISPATCH_INDIRECT 0x16 | |
| 1110 | #define PACKET3_INDIRECT_BUFFER_END 0x17 | |
| 721604a1 | 1111 | #define PACKET3_MODE_CONTROL 0x18 |
| 0c88a02e AD |
1112 | #define PACKET3_SET_PREDICATION 0x20 |
| 1113 | #define PACKET3_REG_RMW 0x21 | |
| 1114 | #define PACKET3_COND_EXEC 0x22 | |
| 1115 | #define PACKET3_PRED_EXEC 0x23 | |
| 1116 | #define PACKET3_DRAW_INDIRECT 0x24 | |
| 1117 | #define PACKET3_DRAW_INDEX_INDIRECT 0x25 | |
| 1118 | #define PACKET3_INDEX_BASE 0x26 | |
| 1119 | #define PACKET3_DRAW_INDEX_2 0x27 | |
| 1120 | #define PACKET3_CONTEXT_CONTROL 0x28 | |
| 1121 | #define PACKET3_DRAW_INDEX_OFFSET 0x29 | |
| 1122 | #define PACKET3_INDEX_TYPE 0x2A | |
| 1123 | #define PACKET3_DRAW_INDEX 0x2B | |
| 1124 | #define PACKET3_DRAW_INDEX_AUTO 0x2D | |
| 1125 | #define PACKET3_DRAW_INDEX_IMMD 0x2E | |
| 1126 | #define PACKET3_NUM_INSTANCES 0x2F | |
| 1127 | #define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30 | |
| 1128 | #define PACKET3_INDIRECT_BUFFER 0x32 | |
| 1129 | #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 | |
| 1130 | #define PACKET3_DRAW_INDEX_OFFSET_2 0x35 | |
| 1131 | #define PACKET3_DRAW_INDEX_MULTI_ELEMENT 0x36 | |
| 1132 | #define PACKET3_WRITE_DATA 0x37 | |
| 1133 | #define PACKET3_MEM_SEMAPHORE 0x39 | |
| 1134 | #define PACKET3_MPEG_INDEX 0x3A | |
| 1135 | #define PACKET3_WAIT_REG_MEM 0x3C | |
| 1136 | #define PACKET3_MEM_WRITE 0x3D | |
| 58f8cf56 | 1137 | #define PACKET3_PFP_SYNC_ME 0x42 |
| 0c88a02e AD |
1138 | #define PACKET3_SURFACE_SYNC 0x43 |
| 1139 | # define PACKET3_CB0_DEST_BASE_ENA (1 << 6) | |
| 1140 | # define PACKET3_CB1_DEST_BASE_ENA (1 << 7) | |
| 1141 | # define PACKET3_CB2_DEST_BASE_ENA (1 << 8) | |
| 1142 | # define PACKET3_CB3_DEST_BASE_ENA (1 << 9) | |
| 1143 | # define PACKET3_CB4_DEST_BASE_ENA (1 << 10) | |
| 1144 | # define PACKET3_CB5_DEST_BASE_ENA (1 << 11) | |
| 1145 | # define PACKET3_CB6_DEST_BASE_ENA (1 << 12) | |
| 1146 | # define PACKET3_CB7_DEST_BASE_ENA (1 << 13) | |
| 1147 | # define PACKET3_DB_DEST_BASE_ENA (1 << 14) | |
| 1148 | # define PACKET3_CB8_DEST_BASE_ENA (1 << 15) | |
| 1149 | # define PACKET3_CB9_DEST_BASE_ENA (1 << 16) | |
| 1150 | # define PACKET3_CB10_DEST_BASE_ENA (1 << 17) | |
| 1151 | # define PACKET3_CB11_DEST_BASE_ENA (1 << 18) | |
| 1152 | # define PACKET3_FULL_CACHE_ENA (1 << 20) | |
| 1153 | # define PACKET3_TC_ACTION_ENA (1 << 23) | |
| 1154 | # define PACKET3_CB_ACTION_ENA (1 << 25) | |
| 1155 | # define PACKET3_DB_ACTION_ENA (1 << 26) | |
| 1156 | # define PACKET3_SH_ACTION_ENA (1 << 27) | |
| 1157 | # define PACKET3_SX_ACTION_ENA (1 << 28) | |
| 10e9ffae | 1158 | # define PACKET3_ENGINE_ME (1 << 31) |
| 0c88a02e AD |
1159 | #define PACKET3_ME_INITIALIZE 0x44 |
| 1160 | #define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16) | |
| 1161 | #define PACKET3_COND_WRITE 0x45 | |
| 1162 | #define PACKET3_EVENT_WRITE 0x46 | |
| b40e7e16 AD |
1163 | #define EVENT_TYPE(x) ((x) << 0) |
| 1164 | #define EVENT_INDEX(x) ((x) << 8) | |
| 1165 | /* 0 - any non-TS event | |
| 1166 | * 1 - ZPASS_DONE | |
| 1167 | * 2 - SAMPLE_PIPELINESTAT | |
| 1168 | * 3 - SAMPLE_STREAMOUTSTAT* | |
| 1169 | * 4 - *S_PARTIAL_FLUSH | |
| 1170 | * 5 - TS events | |
| 1171 | */ | |
| 0c88a02e | 1172 | #define PACKET3_EVENT_WRITE_EOP 0x47 |
| b40e7e16 AD |
1173 | #define DATA_SEL(x) ((x) << 29) |
| 1174 | /* 0 - discard | |
| 1175 | * 1 - send low 32bit data | |
| 1176 | * 2 - send 64bit data | |
| 1177 | * 3 - send 64bit counter value | |
| 1178 | */ | |
| 1179 | #define INT_SEL(x) ((x) << 24) | |
| 1180 | /* 0 - none | |
| 1181 | * 1 - interrupt only (DATA_SEL = 0) | |
| 1182 | * 2 - interrupt when data write is confirmed | |
| 1183 | */ | |
| 0c88a02e AD |
1184 | #define PACKET3_EVENT_WRITE_EOS 0x48 |
| 1185 | #define PACKET3_PREAMBLE_CNTL 0x4A | |
| 1186 | # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) | |
| 1187 | # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) | |
| 1188 | #define PACKET3_ALU_PS_CONST_BUFFER_COPY 0x4C | |
| 1189 | #define PACKET3_ALU_VS_CONST_BUFFER_COPY 0x4D | |
| 1190 | #define PACKET3_ALU_PS_CONST_UPDATE 0x4E | |
| 1191 | #define PACKET3_ALU_VS_CONST_UPDATE 0x4F | |
| 1192 | #define PACKET3_ONE_REG_WRITE 0x57 | |
| 1193 | #define PACKET3_SET_CONFIG_REG 0x68 | |
| 1194 | #define PACKET3_SET_CONFIG_REG_START 0x00008000 | |
| 1195 | #define PACKET3_SET_CONFIG_REG_END 0x0000ac00 | |
| 1196 | #define PACKET3_SET_CONTEXT_REG 0x69 | |
| 1197 | #define PACKET3_SET_CONTEXT_REG_START 0x00028000 | |
| 1198 | #define PACKET3_SET_CONTEXT_REG_END 0x00029000 | |
| 1199 | #define PACKET3_SET_ALU_CONST 0x6A | |
| 1200 | /* alu const buffers only; no reg file */ | |
| 1201 | #define PACKET3_SET_BOOL_CONST 0x6B | |
| 1202 | #define PACKET3_SET_BOOL_CONST_START 0x0003a500 | |
| 1203 | #define PACKET3_SET_BOOL_CONST_END 0x0003a518 | |
| 1204 | #define PACKET3_SET_LOOP_CONST 0x6C | |
| 1205 | #define PACKET3_SET_LOOP_CONST_START 0x0003a200 | |
| 1206 | #define PACKET3_SET_LOOP_CONST_END 0x0003a500 | |
| 1207 | #define PACKET3_SET_RESOURCE 0x6D | |
| 1208 | #define PACKET3_SET_RESOURCE_START 0x00030000 | |
| 1209 | #define PACKET3_SET_RESOURCE_END 0x00038000 | |
| 1210 | #define PACKET3_SET_SAMPLER 0x6E | |
| 1211 | #define PACKET3_SET_SAMPLER_START 0x0003c000 | |
| 1212 | #define PACKET3_SET_SAMPLER_END 0x0003c600 | |
| 1213 | #define PACKET3_SET_CTL_CONST 0x6F | |
| 1214 | #define PACKET3_SET_CTL_CONST_START 0x0003cff0 | |
| 1215 | #define PACKET3_SET_CTL_CONST_END 0x0003ff0c | |
| 1216 | #define PACKET3_SET_RESOURCE_OFFSET 0x70 | |
| 1217 | #define PACKET3_SET_ALU_CONST_VS 0x71 | |
| 1218 | #define PACKET3_SET_ALU_CONST_DI 0x72 | |
| 1219 | #define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73 | |
| 1220 | #define PACKET3_SET_RESOURCE_INDIRECT 0x74 | |
| 1221 | #define PACKET3_SET_APPEND_CNT 0x75 | |
| 2a6f1abb | 1222 | #define PACKET3_ME_WRITE 0x7A |
| 0c88a02e | 1223 | |
| f60cbd11 AD |
1224 | /* ASYNC DMA - first instance at 0xd000, second at 0xd800 */ |
| 1225 | #define DMA0_REGISTER_OFFSET 0x0 /* not a register */ | |
| 1226 | #define DMA1_REGISTER_OFFSET 0x800 /* not a register */ | |
| 1227 | ||
| 1228 | #define DMA_RB_CNTL 0xd000 | |
| 1229 | # define DMA_RB_ENABLE (1 << 0) | |
| 1230 | # define DMA_RB_SIZE(x) ((x) << 1) /* log2 */ | |
| 1231 | # define DMA_RB_SWAP_ENABLE (1 << 9) /* 8IN32 */ | |
| 1232 | # define DMA_RPTR_WRITEBACK_ENABLE (1 << 12) | |
| 1233 | # define DMA_RPTR_WRITEBACK_SWAP_ENABLE (1 << 13) /* 8IN32 */ | |
| 1234 | # define DMA_RPTR_WRITEBACK_TIMER(x) ((x) << 16) /* log2 */ | |
| 1235 | #define DMA_RB_BASE 0xd004 | |
| 1236 | #define DMA_RB_RPTR 0xd008 | |
| 1237 | #define DMA_RB_WPTR 0xd00c | |
| 1238 | ||
| 1239 | #define DMA_RB_RPTR_ADDR_HI 0xd01c | |
| 1240 | #define DMA_RB_RPTR_ADDR_LO 0xd020 | |
| 1241 | ||
| 1242 | #define DMA_IB_CNTL 0xd024 | |
| 1243 | # define DMA_IB_ENABLE (1 << 0) | |
| 1244 | # define DMA_IB_SWAP_ENABLE (1 << 4) | |
| 1245 | # define CMD_VMID_FORCE (1 << 31) | |
| 1246 | #define DMA_IB_RPTR 0xd028 | |
| 1247 | #define DMA_CNTL 0xd02c | |
| 1248 | # define TRAP_ENABLE (1 << 0) | |
| 1249 | # define SEM_INCOMPLETE_INT_ENABLE (1 << 1) | |
| 1250 | # define SEM_WAIT_INT_ENABLE (1 << 2) | |
| 1251 | # define DATA_SWAP_ENABLE (1 << 3) | |
| 1252 | # define FENCE_SWAP_ENABLE (1 << 4) | |
| 1253 | # define CTXEMPTY_INT_ENABLE (1 << 28) | |
| 1254 | #define DMA_STATUS_REG 0xd034 | |
| 1255 | # define DMA_IDLE (1 << 0) | |
| 1256 | #define DMA_SEM_INCOMPLETE_TIMER_CNTL 0xd044 | |
| 1257 | #define DMA_SEM_WAIT_FAIL_TIMER_CNTL 0xd048 | |
| 1258 | #define DMA_TILING_CONFIG 0xd0b8 | |
| 1259 | #define DMA_MODE 0xd0bc | |
| 1260 | ||
| 1261 | #define DMA_PACKET(cmd, t, s, n) ((((cmd) & 0xF) << 28) | \ | |
| 1262 | (((t) & 0x1) << 23) | \ | |
| 1263 | (((s) & 0x1) << 22) | \ | |
| 1264 | (((n) & 0xFFFFF) << 0)) | |
| 1265 | ||
| 1266 | #define DMA_IB_PACKET(cmd, vmid, n) ((((cmd) & 0xF) << 28) | \ | |
| 1267 | (((vmid) & 0xF) << 20) | \ | |
| 1268 | (((n) & 0xFFFFF) << 0)) | |
| 1269 | ||
| 2ab91ada AD |
1270 | #define DMA_PTE_PDE_PACKET(n) ((2 << 28) | \ |
| 1271 | (1 << 26) | \ | |
| 1272 | (1 << 21) | \ | |
| 1273 | (((n) & 0xFFFFF) << 0)) | |
| 1274 | ||
| f60cbd11 AD |
1275 | /* async DMA Packet types */ |
| 1276 | #define DMA_PACKET_WRITE 0x2 | |
| 1277 | #define DMA_PACKET_COPY 0x3 | |
| 1278 | #define DMA_PACKET_INDIRECT_BUFFER 0x4 | |
| 1279 | #define DMA_PACKET_SEMAPHORE 0x5 | |
| 1280 | #define DMA_PACKET_FENCE 0x6 | |
| 1281 | #define DMA_PACKET_TRAP 0x7 | |
| 1282 | #define DMA_PACKET_SRBM_WRITE 0x9 | |
| 1283 | #define DMA_PACKET_CONSTANT_FILL 0xd | |
| 1284 | #define DMA_PACKET_NOP 0xf | |
| 1285 | ||
| 0af62b01 | 1286 | #endif |