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771fe6b9 JG |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
28 | #include <linux/seq_file.h> | |
5a0e3ad6 | 29 | #include <linux/slab.h> |
760285e7 DH |
30 | #include <drm/drmP.h> |
31 | #include <drm/radeon_drm.h> | |
771fe6b9 JG |
32 | #include "radeon_reg.h" |
33 | #include "radeon.h" | |
e6990375 | 34 | #include "radeon_asic.h" |
3ce0a23d | 35 | #include "r100d.h" |
d4550907 JG |
36 | #include "rs100d.h" |
37 | #include "rv200d.h" | |
38 | #include "rv250d.h" | |
49e02b73 | 39 | #include "atom.h" |
3ce0a23d | 40 | |
70967ab9 | 41 | #include <linux/firmware.h> |
e0cd3608 | 42 | #include <linux/module.h> |
70967ab9 | 43 | |
551ebd83 DA |
44 | #include "r100_reg_safe.h" |
45 | #include "rn50_reg_safe.h" | |
46 | ||
70967ab9 BH |
47 | /* Firmware Names */ |
48 | #define FIRMWARE_R100 "radeon/R100_cp.bin" | |
49 | #define FIRMWARE_R200 "radeon/R200_cp.bin" | |
50 | #define FIRMWARE_R300 "radeon/R300_cp.bin" | |
51 | #define FIRMWARE_R420 "radeon/R420_cp.bin" | |
52 | #define FIRMWARE_RS690 "radeon/RS690_cp.bin" | |
53 | #define FIRMWARE_RS600 "radeon/RS600_cp.bin" | |
54 | #define FIRMWARE_R520 "radeon/R520_cp.bin" | |
55 | ||
56 | MODULE_FIRMWARE(FIRMWARE_R100); | |
57 | MODULE_FIRMWARE(FIRMWARE_R200); | |
58 | MODULE_FIRMWARE(FIRMWARE_R300); | |
59 | MODULE_FIRMWARE(FIRMWARE_R420); | |
60 | MODULE_FIRMWARE(FIRMWARE_RS690); | |
61 | MODULE_FIRMWARE(FIRMWARE_RS600); | |
62 | MODULE_FIRMWARE(FIRMWARE_R520); | |
771fe6b9 | 63 | |
551ebd83 DA |
64 | #include "r100_track.h" |
65 | ||
48ef779f AD |
66 | /* This files gather functions specifics to: |
67 | * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 | |
68 | * and others in some cases. | |
69 | */ | |
70 | ||
2b48b968 AD |
71 | static bool r100_is_in_vblank(struct radeon_device *rdev, int crtc) |
72 | { | |
73 | if (crtc == 0) { | |
74 | if (RREG32(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_CUR) | |
75 | return true; | |
76 | else | |
77 | return false; | |
78 | } else { | |
79 | if (RREG32(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_CUR) | |
80 | return true; | |
81 | else | |
82 | return false; | |
83 | } | |
84 | } | |
85 | ||
86 | static bool r100_is_counter_moving(struct radeon_device *rdev, int crtc) | |
87 | { | |
88 | u32 vline1, vline2; | |
89 | ||
90 | if (crtc == 0) { | |
91 | vline1 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; | |
92 | vline2 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; | |
93 | } else { | |
94 | vline1 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; | |
95 | vline2 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; | |
96 | } | |
97 | if (vline1 != vline2) | |
98 | return true; | |
99 | else | |
100 | return false; | |
101 | } | |
102 | ||
48ef779f AD |
103 | /** |
104 | * r100_wait_for_vblank - vblank wait asic callback. | |
105 | * | |
106 | * @rdev: radeon_device pointer | |
107 | * @crtc: crtc to wait for vblank on | |
108 | * | |
109 | * Wait for vblank on the requested crtc (r1xx-r4xx). | |
110 | */ | |
3ae19b75 AD |
111 | void r100_wait_for_vblank(struct radeon_device *rdev, int crtc) |
112 | { | |
2b48b968 | 113 | unsigned i = 0; |
3ae19b75 | 114 | |
94f768fd AD |
115 | if (crtc >= rdev->num_crtc) |
116 | return; | |
117 | ||
118 | if (crtc == 0) { | |
2b48b968 AD |
119 | if (!(RREG32(RADEON_CRTC_GEN_CNTL) & RADEON_CRTC_EN)) |
120 | return; | |
3ae19b75 | 121 | } else { |
2b48b968 AD |
122 | if (!(RREG32(RADEON_CRTC2_GEN_CNTL) & RADEON_CRTC2_EN)) |
123 | return; | |
124 | } | |
125 | ||
126 | /* depending on when we hit vblank, we may be close to active; if so, | |
127 | * wait for another frame. | |
128 | */ | |
129 | while (r100_is_in_vblank(rdev, crtc)) { | |
130 | if (i++ % 100 == 0) { | |
131 | if (!r100_is_counter_moving(rdev, crtc)) | |
132 | break; | |
133 | } | |
134 | } | |
135 | ||
136 | while (!r100_is_in_vblank(rdev, crtc)) { | |
137 | if (i++ % 100 == 0) { | |
138 | if (!r100_is_counter_moving(rdev, crtc)) | |
139 | break; | |
3ae19b75 AD |
140 | } |
141 | } | |
142 | } | |
143 | ||
48ef779f AD |
144 | /** |
145 | * r100_page_flip - pageflip callback. | |
146 | * | |
147 | * @rdev: radeon_device pointer | |
148 | * @crtc_id: crtc to cleanup pageflip on | |
149 | * @crtc_base: new address of the crtc (GPU MC address) | |
150 | * | |
151 | * Does the actual pageflip (r1xx-r4xx). | |
152 | * During vblank we take the crtc lock and wait for the update_pending | |
153 | * bit to go high, when it does, we release the lock, and allow the | |
154 | * double buffered update to take place. | |
48ef779f | 155 | */ |
157fa14d | 156 | void r100_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base) |
6f34be50 AD |
157 | { |
158 | struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; | |
159 | u32 tmp = ((u32)crtc_base) | RADEON_CRTC_OFFSET__OFFSET_LOCK; | |
f6496479 | 160 | int i; |
6f34be50 AD |
161 | |
162 | /* Lock the graphics update lock */ | |
163 | /* update the scanout addresses */ | |
164 | WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp); | |
165 | ||
acb32506 | 166 | /* Wait for update_pending to go high. */ |
f6496479 AD |
167 | for (i = 0; i < rdev->usec_timeout; i++) { |
168 | if (RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET) | |
169 | break; | |
170 | udelay(1); | |
171 | } | |
acb32506 | 172 | DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n"); |
6f34be50 AD |
173 | |
174 | /* Unlock the lock, so double-buffering can take place inside vblank */ | |
175 | tmp &= ~RADEON_CRTC_OFFSET__OFFSET_LOCK; | |
176 | WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp); | |
177 | ||
157fa14d CK |
178 | } |
179 | ||
180 | /** | |
181 | * r100_page_flip_pending - check if page flip is still pending | |
182 | * | |
183 | * @rdev: radeon_device pointer | |
184 | * @crtc_id: crtc to check | |
185 | * | |
186 | * Check if the last pagefilp is still pending (r1xx-r4xx). | |
187 | * Returns the current update pending status. | |
188 | */ | |
189 | bool r100_page_flip_pending(struct radeon_device *rdev, int crtc_id) | |
190 | { | |
191 | struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; | |
192 | ||
6f34be50 | 193 | /* Return current update_pending status: */ |
157fa14d CK |
194 | return !!(RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & |
195 | RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET); | |
6f34be50 AD |
196 | } |
197 | ||
48ef779f AD |
198 | /** |
199 | * r100_pm_get_dynpm_state - look up dynpm power state callback. | |
200 | * | |
201 | * @rdev: radeon_device pointer | |
202 | * | |
203 | * Look up the optimal power state based on the | |
204 | * current state of the GPU (r1xx-r5xx). | |
205 | * Used for dynpm only. | |
206 | */ | |
ce8f5370 | 207 | void r100_pm_get_dynpm_state(struct radeon_device *rdev) |
a48b9b4e AD |
208 | { |
209 | int i; | |
ce8f5370 AD |
210 | rdev->pm.dynpm_can_upclock = true; |
211 | rdev->pm.dynpm_can_downclock = true; | |
a48b9b4e | 212 | |
ce8f5370 AD |
213 | switch (rdev->pm.dynpm_planned_action) { |
214 | case DYNPM_ACTION_MINIMUM: | |
a48b9b4e | 215 | rdev->pm.requested_power_state_index = 0; |
ce8f5370 | 216 | rdev->pm.dynpm_can_downclock = false; |
a48b9b4e | 217 | break; |
ce8f5370 | 218 | case DYNPM_ACTION_DOWNCLOCK: |
a48b9b4e AD |
219 | if (rdev->pm.current_power_state_index == 0) { |
220 | rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; | |
ce8f5370 | 221 | rdev->pm.dynpm_can_downclock = false; |
a48b9b4e AD |
222 | } else { |
223 | if (rdev->pm.active_crtc_count > 1) { | |
224 | for (i = 0; i < rdev->pm.num_power_states; i++) { | |
d7311171 | 225 | if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) |
a48b9b4e AD |
226 | continue; |
227 | else if (i >= rdev->pm.current_power_state_index) { | |
228 | rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; | |
229 | break; | |
230 | } else { | |
231 | rdev->pm.requested_power_state_index = i; | |
232 | break; | |
233 | } | |
234 | } | |
235 | } else | |
236 | rdev->pm.requested_power_state_index = | |
237 | rdev->pm.current_power_state_index - 1; | |
238 | } | |
d7311171 AD |
239 | /* don't use the power state if crtcs are active and no display flag is set */ |
240 | if ((rdev->pm.active_crtc_count > 0) && | |
241 | (rdev->pm.power_state[rdev->pm.requested_power_state_index].clock_info[0].flags & | |
242 | RADEON_PM_MODE_NO_DISPLAY)) { | |
243 | rdev->pm.requested_power_state_index++; | |
244 | } | |
a48b9b4e | 245 | break; |
ce8f5370 | 246 | case DYNPM_ACTION_UPCLOCK: |
a48b9b4e AD |
247 | if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) { |
248 | rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; | |
ce8f5370 | 249 | rdev->pm.dynpm_can_upclock = false; |
a48b9b4e AD |
250 | } else { |
251 | if (rdev->pm.active_crtc_count > 1) { | |
252 | for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) { | |
d7311171 | 253 | if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) |
a48b9b4e AD |
254 | continue; |
255 | else if (i <= rdev->pm.current_power_state_index) { | |
256 | rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; | |
257 | break; | |
258 | } else { | |
259 | rdev->pm.requested_power_state_index = i; | |
260 | break; | |
261 | } | |
262 | } | |
263 | } else | |
264 | rdev->pm.requested_power_state_index = | |
265 | rdev->pm.current_power_state_index + 1; | |
266 | } | |
267 | break; | |
ce8f5370 | 268 | case DYNPM_ACTION_DEFAULT: |
58e21dff | 269 | rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index; |
ce8f5370 | 270 | rdev->pm.dynpm_can_upclock = false; |
58e21dff | 271 | break; |
ce8f5370 | 272 | case DYNPM_ACTION_NONE: |
a48b9b4e AD |
273 | default: |
274 | DRM_ERROR("Requested mode for not defined action\n"); | |
275 | return; | |
276 | } | |
277 | /* only one clock mode per power state */ | |
278 | rdev->pm.requested_clock_mode_index = 0; | |
279 | ||
d9fdaafb | 280 | DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n", |
ce8a3eb2 AD |
281 | rdev->pm.power_state[rdev->pm.requested_power_state_index]. |
282 | clock_info[rdev->pm.requested_clock_mode_index].sclk, | |
283 | rdev->pm.power_state[rdev->pm.requested_power_state_index]. | |
284 | clock_info[rdev->pm.requested_clock_mode_index].mclk, | |
285 | rdev->pm.power_state[rdev->pm.requested_power_state_index]. | |
286 | pcie_lanes); | |
a48b9b4e AD |
287 | } |
288 | ||
48ef779f AD |
289 | /** |
290 | * r100_pm_init_profile - Initialize power profiles callback. | |
291 | * | |
292 | * @rdev: radeon_device pointer | |
293 | * | |
294 | * Initialize the power states used in profile mode | |
295 | * (r1xx-r3xx). | |
296 | * Used for profile mode only. | |
297 | */ | |
ce8f5370 AD |
298 | void r100_pm_init_profile(struct radeon_device *rdev) |
299 | { | |
300 | /* default */ | |
301 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; | |
302 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; | |
303 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; | |
304 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; | |
305 | /* low sh */ | |
306 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0; | |
307 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0; | |
308 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; | |
309 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; | |
c9e75b21 AD |
310 | /* mid sh */ |
311 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0; | |
312 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0; | |
313 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; | |
314 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; | |
ce8f5370 AD |
315 | /* high sh */ |
316 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0; | |
317 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; | |
318 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; | |
319 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; | |
320 | /* low mh */ | |
321 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0; | |
322 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; | |
323 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; | |
324 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; | |
c9e75b21 AD |
325 | /* mid mh */ |
326 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0; | |
327 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; | |
328 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; | |
329 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; | |
ce8f5370 AD |
330 | /* high mh */ |
331 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0; | |
332 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; | |
333 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; | |
334 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; | |
bae6b562 AD |
335 | } |
336 | ||
48ef779f AD |
337 | /** |
338 | * r100_pm_misc - set additional pm hw parameters callback. | |
339 | * | |
340 | * @rdev: radeon_device pointer | |
341 | * | |
342 | * Set non-clock parameters associated with a power state | |
343 | * (voltage, pcie lanes, etc.) (r1xx-r4xx). | |
344 | */ | |
49e02b73 AD |
345 | void r100_pm_misc(struct radeon_device *rdev) |
346 | { | |
49e02b73 AD |
347 | int requested_index = rdev->pm.requested_power_state_index; |
348 | struct radeon_power_state *ps = &rdev->pm.power_state[requested_index]; | |
349 | struct radeon_voltage *voltage = &ps->clock_info[0].voltage; | |
350 | u32 tmp, sclk_cntl, sclk_cntl2, sclk_more_cntl; | |
351 | ||
352 | if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) { | |
353 | if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) { | |
354 | tmp = RREG32(voltage->gpio.reg); | |
355 | if (voltage->active_high) | |
356 | tmp |= voltage->gpio.mask; | |
357 | else | |
358 | tmp &= ~(voltage->gpio.mask); | |
359 | WREG32(voltage->gpio.reg, tmp); | |
360 | if (voltage->delay) | |
361 | udelay(voltage->delay); | |
362 | } else { | |
363 | tmp = RREG32(voltage->gpio.reg); | |
364 | if (voltage->active_high) | |
365 | tmp &= ~voltage->gpio.mask; | |
366 | else | |
367 | tmp |= voltage->gpio.mask; | |
368 | WREG32(voltage->gpio.reg, tmp); | |
369 | if (voltage->delay) | |
370 | udelay(voltage->delay); | |
371 | } | |
372 | } | |
373 | ||
374 | sclk_cntl = RREG32_PLL(SCLK_CNTL); | |
375 | sclk_cntl2 = RREG32_PLL(SCLK_CNTL2); | |
376 | sclk_cntl2 &= ~REDUCED_SPEED_SCLK_SEL(3); | |
377 | sclk_more_cntl = RREG32_PLL(SCLK_MORE_CNTL); | |
378 | sclk_more_cntl &= ~VOLTAGE_DELAY_SEL(3); | |
379 | if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) { | |
380 | sclk_more_cntl |= REDUCED_SPEED_SCLK_EN; | |
381 | if (ps->misc & ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE) | |
382 | sclk_cntl2 |= REDUCED_SPEED_SCLK_MODE; | |
383 | else | |
384 | sclk_cntl2 &= ~REDUCED_SPEED_SCLK_MODE; | |
385 | if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2) | |
386 | sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(0); | |
387 | else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4) | |
388 | sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(2); | |
389 | } else | |
390 | sclk_more_cntl &= ~REDUCED_SPEED_SCLK_EN; | |
391 | ||
392 | if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) { | |
393 | sclk_more_cntl |= IO_CG_VOLTAGE_DROP; | |
394 | if (voltage->delay) { | |
395 | sclk_more_cntl |= VOLTAGE_DROP_SYNC; | |
396 | switch (voltage->delay) { | |
397 | case 33: | |
398 | sclk_more_cntl |= VOLTAGE_DELAY_SEL(0); | |
399 | break; | |
400 | case 66: | |
401 | sclk_more_cntl |= VOLTAGE_DELAY_SEL(1); | |
402 | break; | |
403 | case 99: | |
404 | sclk_more_cntl |= VOLTAGE_DELAY_SEL(2); | |
405 | break; | |
406 | case 132: | |
407 | sclk_more_cntl |= VOLTAGE_DELAY_SEL(3); | |
408 | break; | |
409 | } | |
410 | } else | |
411 | sclk_more_cntl &= ~VOLTAGE_DROP_SYNC; | |
412 | } else | |
413 | sclk_more_cntl &= ~IO_CG_VOLTAGE_DROP; | |
414 | ||
415 | if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN) | |
416 | sclk_cntl &= ~FORCE_HDP; | |
417 | else | |
418 | sclk_cntl |= FORCE_HDP; | |
419 | ||
420 | WREG32_PLL(SCLK_CNTL, sclk_cntl); | |
421 | WREG32_PLL(SCLK_CNTL2, sclk_cntl2); | |
422 | WREG32_PLL(SCLK_MORE_CNTL, sclk_more_cntl); | |
423 | ||
424 | /* set pcie lanes */ | |
425 | if ((rdev->flags & RADEON_IS_PCIE) && | |
426 | !(rdev->flags & RADEON_IS_IGP) && | |
798bcf73 | 427 | rdev->asic->pm.set_pcie_lanes && |
49e02b73 AD |
428 | (ps->pcie_lanes != |
429 | rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) { | |
430 | radeon_set_pcie_lanes(rdev, | |
431 | ps->pcie_lanes); | |
d9fdaafb | 432 | DRM_DEBUG_DRIVER("Setting: p: %d\n", ps->pcie_lanes); |
49e02b73 | 433 | } |
49e02b73 AD |
434 | } |
435 | ||
48ef779f AD |
436 | /** |
437 | * r100_pm_prepare - pre-power state change callback. | |
438 | * | |
439 | * @rdev: radeon_device pointer | |
440 | * | |
441 | * Prepare for a power state change (r1xx-r4xx). | |
442 | */ | |
49e02b73 AD |
443 | void r100_pm_prepare(struct radeon_device *rdev) |
444 | { | |
445 | struct drm_device *ddev = rdev->ddev; | |
446 | struct drm_crtc *crtc; | |
447 | struct radeon_crtc *radeon_crtc; | |
448 | u32 tmp; | |
449 | ||
450 | /* disable any active CRTCs */ | |
451 | list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) { | |
452 | radeon_crtc = to_radeon_crtc(crtc); | |
453 | if (radeon_crtc->enabled) { | |
454 | if (radeon_crtc->crtc_id) { | |
455 | tmp = RREG32(RADEON_CRTC2_GEN_CNTL); | |
456 | tmp |= RADEON_CRTC2_DISP_REQ_EN_B; | |
457 | WREG32(RADEON_CRTC2_GEN_CNTL, tmp); | |
458 | } else { | |
459 | tmp = RREG32(RADEON_CRTC_GEN_CNTL); | |
460 | tmp |= RADEON_CRTC_DISP_REQ_EN_B; | |
461 | WREG32(RADEON_CRTC_GEN_CNTL, tmp); | |
462 | } | |
463 | } | |
464 | } | |
465 | } | |
466 | ||
48ef779f AD |
467 | /** |
468 | * r100_pm_finish - post-power state change callback. | |
469 | * | |
470 | * @rdev: radeon_device pointer | |
471 | * | |
472 | * Clean up after a power state change (r1xx-r4xx). | |
473 | */ | |
49e02b73 AD |
474 | void r100_pm_finish(struct radeon_device *rdev) |
475 | { | |
476 | struct drm_device *ddev = rdev->ddev; | |
477 | struct drm_crtc *crtc; | |
478 | struct radeon_crtc *radeon_crtc; | |
479 | u32 tmp; | |
480 | ||
481 | /* enable any active CRTCs */ | |
482 | list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) { | |
483 | radeon_crtc = to_radeon_crtc(crtc); | |
484 | if (radeon_crtc->enabled) { | |
485 | if (radeon_crtc->crtc_id) { | |
486 | tmp = RREG32(RADEON_CRTC2_GEN_CNTL); | |
487 | tmp &= ~RADEON_CRTC2_DISP_REQ_EN_B; | |
488 | WREG32(RADEON_CRTC2_GEN_CNTL, tmp); | |
489 | } else { | |
490 | tmp = RREG32(RADEON_CRTC_GEN_CNTL); | |
491 | tmp &= ~RADEON_CRTC_DISP_REQ_EN_B; | |
492 | WREG32(RADEON_CRTC_GEN_CNTL, tmp); | |
493 | } | |
494 | } | |
495 | } | |
496 | } | |
497 | ||
48ef779f AD |
498 | /** |
499 | * r100_gui_idle - gui idle callback. | |
500 | * | |
501 | * @rdev: radeon_device pointer | |
502 | * | |
503 | * Check of the GUI (2D/3D engines) are idle (r1xx-r5xx). | |
504 | * Returns true if idle, false if not. | |
505 | */ | |
def9ba9c AD |
506 | bool r100_gui_idle(struct radeon_device *rdev) |
507 | { | |
508 | if (RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE) | |
509 | return false; | |
510 | else | |
511 | return true; | |
512 | } | |
513 | ||
05a05c50 | 514 | /* hpd for digital panel detect/disconnect */ |
48ef779f AD |
515 | /** |
516 | * r100_hpd_sense - hpd sense callback. | |
517 | * | |
518 | * @rdev: radeon_device pointer | |
519 | * @hpd: hpd (hotplug detect) pin | |
520 | * | |
521 | * Checks if a digital monitor is connected (r1xx-r4xx). | |
522 | * Returns true if connected, false if not connected. | |
523 | */ | |
05a05c50 AD |
524 | bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) |
525 | { | |
526 | bool connected = false; | |
527 | ||
528 | switch (hpd) { | |
529 | case RADEON_HPD_1: | |
530 | if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE) | |
531 | connected = true; | |
532 | break; | |
533 | case RADEON_HPD_2: | |
534 | if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE) | |
535 | connected = true; | |
536 | break; | |
537 | default: | |
538 | break; | |
539 | } | |
540 | return connected; | |
541 | } | |
542 | ||
48ef779f AD |
543 | /** |
544 | * r100_hpd_set_polarity - hpd set polarity callback. | |
545 | * | |
546 | * @rdev: radeon_device pointer | |
547 | * @hpd: hpd (hotplug detect) pin | |
548 | * | |
549 | * Set the polarity of the hpd pin (r1xx-r4xx). | |
550 | */ | |
05a05c50 AD |
551 | void r100_hpd_set_polarity(struct radeon_device *rdev, |
552 | enum radeon_hpd_id hpd) | |
553 | { | |
554 | u32 tmp; | |
555 | bool connected = r100_hpd_sense(rdev, hpd); | |
556 | ||
557 | switch (hpd) { | |
558 | case RADEON_HPD_1: | |
559 | tmp = RREG32(RADEON_FP_GEN_CNTL); | |
560 | if (connected) | |
561 | tmp &= ~RADEON_FP_DETECT_INT_POL; | |
562 | else | |
563 | tmp |= RADEON_FP_DETECT_INT_POL; | |
564 | WREG32(RADEON_FP_GEN_CNTL, tmp); | |
565 | break; | |
566 | case RADEON_HPD_2: | |
567 | tmp = RREG32(RADEON_FP2_GEN_CNTL); | |
568 | if (connected) | |
569 | tmp &= ~RADEON_FP2_DETECT_INT_POL; | |
570 | else | |
571 | tmp |= RADEON_FP2_DETECT_INT_POL; | |
572 | WREG32(RADEON_FP2_GEN_CNTL, tmp); | |
573 | break; | |
574 | default: | |
575 | break; | |
576 | } | |
577 | } | |
578 | ||
48ef779f AD |
579 | /** |
580 | * r100_hpd_init - hpd setup callback. | |
581 | * | |
582 | * @rdev: radeon_device pointer | |
583 | * | |
584 | * Setup the hpd pins used by the card (r1xx-r4xx). | |
585 | * Set the polarity, and enable the hpd interrupts. | |
586 | */ | |
05a05c50 AD |
587 | void r100_hpd_init(struct radeon_device *rdev) |
588 | { | |
589 | struct drm_device *dev = rdev->ddev; | |
590 | struct drm_connector *connector; | |
fb98257a | 591 | unsigned enable = 0; |
05a05c50 AD |
592 | |
593 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
594 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
fb98257a | 595 | enable |= 1 << radeon_connector->hpd.hpd; |
64912e99 | 596 | radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd); |
05a05c50 | 597 | } |
fb98257a | 598 | radeon_irq_kms_enable_hpd(rdev, enable); |
05a05c50 AD |
599 | } |
600 | ||
48ef779f AD |
601 | /** |
602 | * r100_hpd_fini - hpd tear down callback. | |
603 | * | |
604 | * @rdev: radeon_device pointer | |
605 | * | |
606 | * Tear down the hpd pins used by the card (r1xx-r4xx). | |
607 | * Disable the hpd interrupts. | |
608 | */ | |
05a05c50 AD |
609 | void r100_hpd_fini(struct radeon_device *rdev) |
610 | { | |
611 | struct drm_device *dev = rdev->ddev; | |
612 | struct drm_connector *connector; | |
fb98257a | 613 | unsigned disable = 0; |
05a05c50 AD |
614 | |
615 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
616 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
fb98257a | 617 | disable |= 1 << radeon_connector->hpd.hpd; |
05a05c50 | 618 | } |
fb98257a | 619 | radeon_irq_kms_disable_hpd(rdev, disable); |
05a05c50 AD |
620 | } |
621 | ||
771fe6b9 JG |
622 | /* |
623 | * PCI GART | |
624 | */ | |
625 | void r100_pci_gart_tlb_flush(struct radeon_device *rdev) | |
626 | { | |
627 | /* TODO: can we do somethings here ? */ | |
628 | /* It seems hw only cache one entry so we should discard this | |
629 | * entry otherwise if first GPU GART read hit this entry it | |
630 | * could end up in wrong address. */ | |
631 | } | |
632 | ||
4aac0473 | 633 | int r100_pci_gart_init(struct radeon_device *rdev) |
771fe6b9 | 634 | { |
771fe6b9 JG |
635 | int r; |
636 | ||
c9a1be96 | 637 | if (rdev->gart.ptr) { |
fce7d61b | 638 | WARN(1, "R100 PCI GART already initialized\n"); |
4aac0473 JG |
639 | return 0; |
640 | } | |
771fe6b9 JG |
641 | /* Initialize common gart structure */ |
642 | r = radeon_gart_init(rdev); | |
4aac0473 | 643 | if (r) |
771fe6b9 | 644 | return r; |
4aac0473 | 645 | rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; |
c5b3b850 AD |
646 | rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush; |
647 | rdev->asic->gart.set_page = &r100_pci_gart_set_page; | |
4aac0473 JG |
648 | return radeon_gart_table_ram_alloc(rdev); |
649 | } | |
650 | ||
651 | int r100_pci_gart_enable(struct radeon_device *rdev) | |
652 | { | |
653 | uint32_t tmp; | |
654 | ||
82568565 | 655 | radeon_gart_restore(rdev); |
771fe6b9 JG |
656 | /* discard memory request outside of configured range */ |
657 | tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS; | |
658 | WREG32(RADEON_AIC_CNTL, tmp); | |
659 | /* set address range for PCI address translate */ | |
d594e46a JG |
660 | WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start); |
661 | WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end); | |
771fe6b9 JG |
662 | /* set PCI GART page-table base address */ |
663 | WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr); | |
664 | tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN; | |
665 | WREG32(RADEON_AIC_CNTL, tmp); | |
666 | r100_pci_gart_tlb_flush(rdev); | |
43caf451 | 667 | DRM_INFO("PCI GART of %uM enabled (table at 0x%016llX).\n", |
fcf4de5a TV |
668 | (unsigned)(rdev->mc.gtt_size >> 20), |
669 | (unsigned long long)rdev->gart.table_addr); | |
771fe6b9 JG |
670 | rdev->gart.ready = true; |
671 | return 0; | |
672 | } | |
673 | ||
674 | void r100_pci_gart_disable(struct radeon_device *rdev) | |
675 | { | |
676 | uint32_t tmp; | |
677 | ||
678 | /* discard memory request outside of configured range */ | |
679 | tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS; | |
680 | WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN); | |
681 | WREG32(RADEON_AIC_LO_ADDR, 0); | |
682 | WREG32(RADEON_AIC_HI_ADDR, 0); | |
683 | } | |
684 | ||
685 | int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) | |
686 | { | |
c9a1be96 JG |
687 | u32 *gtt = rdev->gart.ptr; |
688 | ||
771fe6b9 JG |
689 | if (i < 0 || i > rdev->gart.num_gpu_pages) { |
690 | return -EINVAL; | |
691 | } | |
c9a1be96 | 692 | gtt[i] = cpu_to_le32(lower_32_bits(addr)); |
771fe6b9 JG |
693 | return 0; |
694 | } | |
695 | ||
4aac0473 | 696 | void r100_pci_gart_fini(struct radeon_device *rdev) |
771fe6b9 | 697 | { |
f9274562 | 698 | radeon_gart_fini(rdev); |
4aac0473 JG |
699 | r100_pci_gart_disable(rdev); |
700 | radeon_gart_table_ram_free(rdev); | |
771fe6b9 JG |
701 | } |
702 | ||
7ed220d7 MD |
703 | int r100_irq_set(struct radeon_device *rdev) |
704 | { | |
705 | uint32_t tmp = 0; | |
706 | ||
003e69f9 | 707 | if (!rdev->irq.installed) { |
fce7d61b | 708 | WARN(1, "Can't enable IRQ/MSI because no handler is installed\n"); |
003e69f9 JG |
709 | WREG32(R_000040_GEN_INT_CNTL, 0); |
710 | return -EINVAL; | |
711 | } | |
736fc37f | 712 | if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) { |
7ed220d7 MD |
713 | tmp |= RADEON_SW_INT_ENABLE; |
714 | } | |
6f34be50 | 715 | if (rdev->irq.crtc_vblank_int[0] || |
736fc37f | 716 | atomic_read(&rdev->irq.pflip[0])) { |
7ed220d7 MD |
717 | tmp |= RADEON_CRTC_VBLANK_MASK; |
718 | } | |
6f34be50 | 719 | if (rdev->irq.crtc_vblank_int[1] || |
736fc37f | 720 | atomic_read(&rdev->irq.pflip[1])) { |
7ed220d7 MD |
721 | tmp |= RADEON_CRTC2_VBLANK_MASK; |
722 | } | |
05a05c50 AD |
723 | if (rdev->irq.hpd[0]) { |
724 | tmp |= RADEON_FP_DETECT_MASK; | |
725 | } | |
726 | if (rdev->irq.hpd[1]) { | |
727 | tmp |= RADEON_FP2_DETECT_MASK; | |
728 | } | |
7ed220d7 MD |
729 | WREG32(RADEON_GEN_INT_CNTL, tmp); |
730 | return 0; | |
731 | } | |
732 | ||
9f022ddf JG |
733 | void r100_irq_disable(struct radeon_device *rdev) |
734 | { | |
735 | u32 tmp; | |
736 | ||
737 | WREG32(R_000040_GEN_INT_CNTL, 0); | |
738 | /* Wait and acknowledge irq */ | |
739 | mdelay(1); | |
740 | tmp = RREG32(R_000044_GEN_INT_STATUS); | |
741 | WREG32(R_000044_GEN_INT_STATUS, tmp); | |
742 | } | |
743 | ||
cbdd4501 | 744 | static uint32_t r100_irq_ack(struct radeon_device *rdev) |
7ed220d7 MD |
745 | { |
746 | uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS); | |
05a05c50 AD |
747 | uint32_t irq_mask = RADEON_SW_INT_TEST | |
748 | RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT | | |
749 | RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT; | |
7ed220d7 MD |
750 | |
751 | if (irqs) { | |
752 | WREG32(RADEON_GEN_INT_STATUS, irqs); | |
753 | } | |
754 | return irqs & irq_mask; | |
755 | } | |
756 | ||
757 | int r100_irq_process(struct radeon_device *rdev) | |
758 | { | |
3e5cb98d | 759 | uint32_t status, msi_rearm; |
d4877cf2 | 760 | bool queue_hotplug = false; |
7ed220d7 MD |
761 | |
762 | status = r100_irq_ack(rdev); | |
763 | if (!status) { | |
764 | return IRQ_NONE; | |
765 | } | |
a513c184 JG |
766 | if (rdev->shutdown) { |
767 | return IRQ_NONE; | |
768 | } | |
7ed220d7 MD |
769 | while (status) { |
770 | /* SW interrupt */ | |
771 | if (status & RADEON_SW_INT_TEST) { | |
7465280c | 772 | radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); |
7ed220d7 MD |
773 | } |
774 | /* Vertical blank interrupts */ | |
775 | if (status & RADEON_CRTC_VBLANK_STAT) { | |
6f34be50 AD |
776 | if (rdev->irq.crtc_vblank_int[0]) { |
777 | drm_handle_vblank(rdev->ddev, 0); | |
778 | rdev->pm.vblank_sync = true; | |
779 | wake_up(&rdev->irq.vblank_queue); | |
780 | } | |
736fc37f | 781 | if (atomic_read(&rdev->irq.pflip[0])) |
1a0e7918 | 782 | radeon_crtc_handle_vblank(rdev, 0); |
7ed220d7 MD |
783 | } |
784 | if (status & RADEON_CRTC2_VBLANK_STAT) { | |
6f34be50 AD |
785 | if (rdev->irq.crtc_vblank_int[1]) { |
786 | drm_handle_vblank(rdev->ddev, 1); | |
787 | rdev->pm.vblank_sync = true; | |
788 | wake_up(&rdev->irq.vblank_queue); | |
789 | } | |
736fc37f | 790 | if (atomic_read(&rdev->irq.pflip[1])) |
1a0e7918 | 791 | radeon_crtc_handle_vblank(rdev, 1); |
7ed220d7 | 792 | } |
05a05c50 | 793 | if (status & RADEON_FP_DETECT_STAT) { |
d4877cf2 AD |
794 | queue_hotplug = true; |
795 | DRM_DEBUG("HPD1\n"); | |
05a05c50 AD |
796 | } |
797 | if (status & RADEON_FP2_DETECT_STAT) { | |
d4877cf2 AD |
798 | queue_hotplug = true; |
799 | DRM_DEBUG("HPD2\n"); | |
05a05c50 | 800 | } |
7ed220d7 MD |
801 | status = r100_irq_ack(rdev); |
802 | } | |
d4877cf2 | 803 | if (queue_hotplug) |
32c87fca | 804 | schedule_work(&rdev->hotplug_work); |
3e5cb98d AD |
805 | if (rdev->msi_enabled) { |
806 | switch (rdev->family) { | |
807 | case CHIP_RS400: | |
808 | case CHIP_RS480: | |
809 | msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM; | |
810 | WREG32(RADEON_AIC_CNTL, msi_rearm); | |
811 | WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM); | |
812 | break; | |
813 | default: | |
b7f5b7de | 814 | WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN); |
3e5cb98d AD |
815 | break; |
816 | } | |
817 | } | |
7ed220d7 MD |
818 | return IRQ_HANDLED; |
819 | } | |
820 | ||
821 | u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc) | |
822 | { | |
823 | if (crtc == 0) | |
824 | return RREG32(RADEON_CRTC_CRNT_FRAME); | |
825 | else | |
826 | return RREG32(RADEON_CRTC2_CRNT_FRAME); | |
827 | } | |
828 | ||
9e5b2af7 PN |
829 | /* Who ever call radeon_fence_emit should call ring_lock and ask |
830 | * for enough space (today caller are ib schedule and buffer move) */ | |
771fe6b9 JG |
831 | void r100_fence_ring_emit(struct radeon_device *rdev, |
832 | struct radeon_fence *fence) | |
833 | { | |
e32eb50d | 834 | struct radeon_ring *ring = &rdev->ring[fence->ring]; |
7b1f2485 | 835 | |
9e5b2af7 PN |
836 | /* We have to make sure that caches are flushed before |
837 | * CPU might read something from VRAM. */ | |
e32eb50d CK |
838 | radeon_ring_write(ring, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); |
839 | radeon_ring_write(ring, RADEON_RB3D_DC_FLUSH_ALL); | |
840 | radeon_ring_write(ring, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); | |
841 | radeon_ring_write(ring, RADEON_RB3D_ZC_FLUSH_ALL); | |
771fe6b9 | 842 | /* Wait until IDLE & CLEAN */ |
e32eb50d CK |
843 | radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); |
844 | radeon_ring_write(ring, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN); | |
845 | radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0)); | |
846 | radeon_ring_write(ring, rdev->config.r100.hdp_cntl | | |
cafe6609 | 847 | RADEON_HDP_READ_BUFFER_INVALIDATE); |
e32eb50d CK |
848 | radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0)); |
849 | radeon_ring_write(ring, rdev->config.r100.hdp_cntl); | |
771fe6b9 | 850 | /* Emit fence sequence & fire IRQ */ |
e32eb50d CK |
851 | radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0)); |
852 | radeon_ring_write(ring, fence->seq); | |
853 | radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0)); | |
854 | radeon_ring_write(ring, RADEON_SW_INT_FIRE); | |
771fe6b9 JG |
855 | } |
856 | ||
1654b817 | 857 | bool r100_semaphore_ring_emit(struct radeon_device *rdev, |
e32eb50d | 858 | struct radeon_ring *ring, |
15d3332f | 859 | struct radeon_semaphore *semaphore, |
7b1f2485 | 860 | bool emit_wait) |
15d3332f CK |
861 | { |
862 | /* Unused on older asics, since we don't have semaphores or multiple rings */ | |
863 | BUG(); | |
1654b817 | 864 | return false; |
15d3332f CK |
865 | } |
866 | ||
771fe6b9 JG |
867 | int r100_copy_blit(struct radeon_device *rdev, |
868 | uint64_t src_offset, | |
869 | uint64_t dst_offset, | |
003cefe0 | 870 | unsigned num_gpu_pages, |
876dc9f3 | 871 | struct radeon_fence **fence) |
771fe6b9 | 872 | { |
e32eb50d | 873 | struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
771fe6b9 | 874 | uint32_t cur_pages; |
003cefe0 | 875 | uint32_t stride_bytes = RADEON_GPU_PAGE_SIZE; |
771fe6b9 JG |
876 | uint32_t pitch; |
877 | uint32_t stride_pixels; | |
878 | unsigned ndw; | |
879 | int num_loops; | |
880 | int r = 0; | |
881 | ||
882 | /* radeon limited to 16k stride */ | |
883 | stride_bytes &= 0x3fff; | |
884 | /* radeon pitch is /64 */ | |
885 | pitch = stride_bytes / 64; | |
886 | stride_pixels = stride_bytes / 4; | |
003cefe0 | 887 | num_loops = DIV_ROUND_UP(num_gpu_pages, 8191); |
771fe6b9 JG |
888 | |
889 | /* Ask for enough room for blit + flush + fence */ | |
890 | ndw = 64 + (10 * num_loops); | |
e32eb50d | 891 | r = radeon_ring_lock(rdev, ring, ndw); |
771fe6b9 JG |
892 | if (r) { |
893 | DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw); | |
894 | return -EINVAL; | |
895 | } | |
003cefe0 AD |
896 | while (num_gpu_pages > 0) { |
897 | cur_pages = num_gpu_pages; | |
771fe6b9 JG |
898 | if (cur_pages > 8191) { |
899 | cur_pages = 8191; | |
900 | } | |
003cefe0 | 901 | num_gpu_pages -= cur_pages; |
771fe6b9 JG |
902 | |
903 | /* pages are in Y direction - height | |
904 | page width in X direction - width */ | |
e32eb50d CK |
905 | radeon_ring_write(ring, PACKET3(PACKET3_BITBLT_MULTI, 8)); |
906 | radeon_ring_write(ring, | |
771fe6b9 JG |
907 | RADEON_GMC_SRC_PITCH_OFFSET_CNTL | |
908 | RADEON_GMC_DST_PITCH_OFFSET_CNTL | | |
909 | RADEON_GMC_SRC_CLIPPING | | |
910 | RADEON_GMC_DST_CLIPPING | | |
911 | RADEON_GMC_BRUSH_NONE | | |
912 | (RADEON_COLOR_FORMAT_ARGB8888 << 8) | | |
913 | RADEON_GMC_SRC_DATATYPE_COLOR | | |
914 | RADEON_ROP3_S | | |
915 | RADEON_DP_SRC_SOURCE_MEMORY | | |
916 | RADEON_GMC_CLR_CMP_CNTL_DIS | | |
917 | RADEON_GMC_WR_MSK_DIS); | |
e32eb50d CK |
918 | radeon_ring_write(ring, (pitch << 22) | (src_offset >> 10)); |
919 | radeon_ring_write(ring, (pitch << 22) | (dst_offset >> 10)); | |
920 | radeon_ring_write(ring, (0x1fff) | (0x1fff << 16)); | |
921 | radeon_ring_write(ring, 0); | |
922 | radeon_ring_write(ring, (0x1fff) | (0x1fff << 16)); | |
923 | radeon_ring_write(ring, num_gpu_pages); | |
924 | radeon_ring_write(ring, num_gpu_pages); | |
925 | radeon_ring_write(ring, cur_pages | (stride_pixels << 16)); | |
926 | } | |
927 | radeon_ring_write(ring, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0)); | |
928 | radeon_ring_write(ring, RADEON_RB2D_DC_FLUSH_ALL); | |
929 | radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); | |
930 | radeon_ring_write(ring, | |
771fe6b9 JG |
931 | RADEON_WAIT_2D_IDLECLEAN | |
932 | RADEON_WAIT_HOST_IDLECLEAN | | |
933 | RADEON_WAIT_DMA_GUI_IDLE); | |
934 | if (fence) { | |
876dc9f3 | 935 | r = radeon_fence_emit(rdev, fence, RADEON_RING_TYPE_GFX_INDEX); |
771fe6b9 | 936 | } |
e32eb50d | 937 | radeon_ring_unlock_commit(rdev, ring); |
771fe6b9 JG |
938 | return r; |
939 | } | |
940 | ||
45600232 JG |
941 | static int r100_cp_wait_for_idle(struct radeon_device *rdev) |
942 | { | |
943 | unsigned i; | |
944 | u32 tmp; | |
945 | ||
946 | for (i = 0; i < rdev->usec_timeout; i++) { | |
947 | tmp = RREG32(R_000E40_RBBM_STATUS); | |
948 | if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) { | |
949 | return 0; | |
950 | } | |
951 | udelay(1); | |
952 | } | |
953 | return -1; | |
954 | } | |
955 | ||
f712812e | 956 | void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring) |
771fe6b9 JG |
957 | { |
958 | int r; | |
959 | ||
e32eb50d | 960 | r = radeon_ring_lock(rdev, ring, 2); |
771fe6b9 JG |
961 | if (r) { |
962 | return; | |
963 | } | |
e32eb50d CK |
964 | radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0)); |
965 | radeon_ring_write(ring, | |
771fe6b9 JG |
966 | RADEON_ISYNC_ANY2D_IDLE3D | |
967 | RADEON_ISYNC_ANY3D_IDLE2D | | |
968 | RADEON_ISYNC_WAIT_IDLEGUI | | |
969 | RADEON_ISYNC_CPSCRATCH_IDLEGUI); | |
e32eb50d | 970 | radeon_ring_unlock_commit(rdev, ring); |
771fe6b9 JG |
971 | } |
972 | ||
70967ab9 BH |
973 | |
974 | /* Load the microcode for the CP */ | |
975 | static int r100_cp_init_microcode(struct radeon_device *rdev) | |
771fe6b9 | 976 | { |
70967ab9 BH |
977 | const char *fw_name = NULL; |
978 | int err; | |
771fe6b9 | 979 | |
d9fdaafb | 980 | DRM_DEBUG_KMS("\n"); |
771fe6b9 | 981 | |
771fe6b9 JG |
982 | if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) || |
983 | (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) || | |
984 | (rdev->family == CHIP_RS200)) { | |
985 | DRM_INFO("Loading R100 Microcode\n"); | |
70967ab9 | 986 | fw_name = FIRMWARE_R100; |
771fe6b9 JG |
987 | } else if ((rdev->family == CHIP_R200) || |
988 | (rdev->family == CHIP_RV250) || | |
989 | (rdev->family == CHIP_RV280) || | |
990 | (rdev->family == CHIP_RS300)) { | |
991 | DRM_INFO("Loading R200 Microcode\n"); | |
70967ab9 | 992 | fw_name = FIRMWARE_R200; |
771fe6b9 JG |
993 | } else if ((rdev->family == CHIP_R300) || |
994 | (rdev->family == CHIP_R350) || | |
995 | (rdev->family == CHIP_RV350) || | |
996 | (rdev->family == CHIP_RV380) || | |
997 | (rdev->family == CHIP_RS400) || | |
998 | (rdev->family == CHIP_RS480)) { | |
999 | DRM_INFO("Loading R300 Microcode\n"); | |
70967ab9 | 1000 | fw_name = FIRMWARE_R300; |
771fe6b9 JG |
1001 | } else if ((rdev->family == CHIP_R420) || |
1002 | (rdev->family == CHIP_R423) || | |
1003 | (rdev->family == CHIP_RV410)) { | |
1004 | DRM_INFO("Loading R400 Microcode\n"); | |
70967ab9 | 1005 | fw_name = FIRMWARE_R420; |
771fe6b9 JG |
1006 | } else if ((rdev->family == CHIP_RS690) || |
1007 | (rdev->family == CHIP_RS740)) { | |
1008 | DRM_INFO("Loading RS690/RS740 Microcode\n"); | |
70967ab9 | 1009 | fw_name = FIRMWARE_RS690; |
771fe6b9 JG |
1010 | } else if (rdev->family == CHIP_RS600) { |
1011 | DRM_INFO("Loading RS600 Microcode\n"); | |
70967ab9 | 1012 | fw_name = FIRMWARE_RS600; |
771fe6b9 JG |
1013 | } else if ((rdev->family == CHIP_RV515) || |
1014 | (rdev->family == CHIP_R520) || | |
1015 | (rdev->family == CHIP_RV530) || | |
1016 | (rdev->family == CHIP_R580) || | |
1017 | (rdev->family == CHIP_RV560) || | |
1018 | (rdev->family == CHIP_RV570)) { | |
1019 | DRM_INFO("Loading R500 Microcode\n"); | |
70967ab9 BH |
1020 | fw_name = FIRMWARE_R520; |
1021 | } | |
1022 | ||
0a168933 | 1023 | err = request_firmware(&rdev->me_fw, fw_name, rdev->dev); |
70967ab9 BH |
1024 | if (err) { |
1025 | printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n", | |
1026 | fw_name); | |
3ce0a23d | 1027 | } else if (rdev->me_fw->size % 8) { |
70967ab9 BH |
1028 | printk(KERN_ERR |
1029 | "radeon_cp: Bogus length %zu in firmware \"%s\"\n", | |
3ce0a23d | 1030 | rdev->me_fw->size, fw_name); |
70967ab9 | 1031 | err = -EINVAL; |
3ce0a23d JG |
1032 | release_firmware(rdev->me_fw); |
1033 | rdev->me_fw = NULL; | |
70967ab9 BH |
1034 | } |
1035 | return err; | |
1036 | } | |
d4550907 | 1037 | |
ea31bf69 AD |
1038 | u32 r100_gfx_get_rptr(struct radeon_device *rdev, |
1039 | struct radeon_ring *ring) | |
1040 | { | |
1041 | u32 rptr; | |
1042 | ||
1043 | if (rdev->wb.enabled) | |
1044 | rptr = le32_to_cpu(rdev->wb.wb[ring->rptr_offs/4]); | |
1045 | else | |
1046 | rptr = RREG32(RADEON_CP_RB_RPTR); | |
1047 | ||
1048 | return rptr; | |
1049 | } | |
1050 | ||
1051 | u32 r100_gfx_get_wptr(struct radeon_device *rdev, | |
1052 | struct radeon_ring *ring) | |
1053 | { | |
1054 | u32 wptr; | |
1055 | ||
1056 | wptr = RREG32(RADEON_CP_RB_WPTR); | |
1057 | ||
1058 | return wptr; | |
1059 | } | |
1060 | ||
1061 | void r100_gfx_set_wptr(struct radeon_device *rdev, | |
1062 | struct radeon_ring *ring) | |
1063 | { | |
1064 | WREG32(RADEON_CP_RB_WPTR, ring->wptr); | |
1065 | (void)RREG32(RADEON_CP_RB_WPTR); | |
1066 | } | |
1067 | ||
70967ab9 BH |
1068 | static void r100_cp_load_microcode(struct radeon_device *rdev) |
1069 | { | |
1070 | const __be32 *fw_data; | |
1071 | int i, size; | |
1072 | ||
1073 | if (r100_gui_wait_for_idle(rdev)) { | |
1074 | printk(KERN_WARNING "Failed to wait GUI idle while " | |
1075 | "programming pipes. Bad things might happen.\n"); | |
1076 | } | |
1077 | ||
3ce0a23d JG |
1078 | if (rdev->me_fw) { |
1079 | size = rdev->me_fw->size / 4; | |
1080 | fw_data = (const __be32 *)&rdev->me_fw->data[0]; | |
70967ab9 BH |
1081 | WREG32(RADEON_CP_ME_RAM_ADDR, 0); |
1082 | for (i = 0; i < size; i += 2) { | |
1083 | WREG32(RADEON_CP_ME_RAM_DATAH, | |
1084 | be32_to_cpup(&fw_data[i])); | |
1085 | WREG32(RADEON_CP_ME_RAM_DATAL, | |
1086 | be32_to_cpup(&fw_data[i + 1])); | |
771fe6b9 JG |
1087 | } |
1088 | } | |
1089 | } | |
1090 | ||
1091 | int r100_cp_init(struct radeon_device *rdev, unsigned ring_size) | |
1092 | { | |
e32eb50d | 1093 | struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
771fe6b9 JG |
1094 | unsigned rb_bufsz; |
1095 | unsigned rb_blksz; | |
1096 | unsigned max_fetch; | |
1097 | unsigned pre_write_timer; | |
1098 | unsigned pre_write_limit; | |
1099 | unsigned indirect2_start; | |
1100 | unsigned indirect1_start; | |
1101 | uint32_t tmp; | |
1102 | int r; | |
1103 | ||
1104 | if (r100_debugfs_cp_init(rdev)) { | |
1105 | DRM_ERROR("Failed to register debugfs file for CP !\n"); | |
1106 | } | |
3ce0a23d | 1107 | if (!rdev->me_fw) { |
70967ab9 BH |
1108 | r = r100_cp_init_microcode(rdev); |
1109 | if (r) { | |
1110 | DRM_ERROR("Failed to load firmware!\n"); | |
1111 | return r; | |
1112 | } | |
1113 | } | |
1114 | ||
771fe6b9 | 1115 | /* Align ring size */ |
b72a8925 | 1116 | rb_bufsz = order_base_2(ring_size / 8); |
771fe6b9 JG |
1117 | ring_size = (1 << (rb_bufsz + 1)) * 4; |
1118 | r100_cp_load_microcode(rdev); | |
e32eb50d | 1119 | r = radeon_ring_init(rdev, ring, ring_size, RADEON_WB_CP_RPTR_OFFSET, |
2e1e6dad | 1120 | RADEON_CP_PACKET2); |
771fe6b9 JG |
1121 | if (r) { |
1122 | return r; | |
1123 | } | |
1124 | /* Each time the cp read 1024 bytes (16 dword/quadword) update | |
1125 | * the rptr copy in system ram */ | |
1126 | rb_blksz = 9; | |
1127 | /* cp will read 128bytes at a time (4 dwords) */ | |
1128 | max_fetch = 1; | |
e32eb50d | 1129 | ring->align_mask = 16 - 1; |
771fe6b9 JG |
1130 | /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */ |
1131 | pre_write_timer = 64; | |
1132 | /* Force CP_RB_WPTR write if written more than one time before the | |
1133 | * delay expire | |
1134 | */ | |
1135 | pre_write_limit = 0; | |
1136 | /* Setup the cp cache like this (cache size is 96 dwords) : | |
1137 | * RING 0 to 15 | |
1138 | * INDIRECT1 16 to 79 | |
1139 | * INDIRECT2 80 to 95 | |
1140 | * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords)) | |
1141 | * indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords)) | |
1142 | * indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords)) | |
1143 | * Idea being that most of the gpu cmd will be through indirect1 buffer | |
1144 | * so it gets the bigger cache. | |
1145 | */ | |
1146 | indirect2_start = 80; | |
1147 | indirect1_start = 16; | |
1148 | /* cp setup */ | |
1149 | WREG32(0x718, pre_write_timer | (pre_write_limit << 28)); | |
d6f28938 | 1150 | tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) | |
771fe6b9 | 1151 | REG_SET(RADEON_RB_BLKSZ, rb_blksz) | |
724c80e1 | 1152 | REG_SET(RADEON_MAX_FETCH, max_fetch)); |
d6f28938 AD |
1153 | #ifdef __BIG_ENDIAN |
1154 | tmp |= RADEON_BUF_SWAP_32BIT; | |
1155 | #endif | |
724c80e1 | 1156 | WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_NO_UPDATE); |
d6f28938 | 1157 | |
771fe6b9 | 1158 | /* Set ring address */ |
e32eb50d CK |
1159 | DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)ring->gpu_addr); |
1160 | WREG32(RADEON_CP_RB_BASE, ring->gpu_addr); | |
771fe6b9 | 1161 | /* Force read & write ptr to 0 */ |
724c80e1 | 1162 | WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA | RADEON_RB_NO_UPDATE); |
771fe6b9 | 1163 | WREG32(RADEON_CP_RB_RPTR_WR, 0); |
e32eb50d CK |
1164 | ring->wptr = 0; |
1165 | WREG32(RADEON_CP_RB_WPTR, ring->wptr); | |
724c80e1 AD |
1166 | |
1167 | /* set the wb address whether it's enabled or not */ | |
1168 | WREG32(R_00070C_CP_RB_RPTR_ADDR, | |
1169 | S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) >> 2)); | |
1170 | WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET); | |
1171 | ||
1172 | if (rdev->wb.enabled) | |
1173 | WREG32(R_000770_SCRATCH_UMSK, 0xff); | |
1174 | else { | |
1175 | tmp |= RADEON_RB_NO_UPDATE; | |
1176 | WREG32(R_000770_SCRATCH_UMSK, 0); | |
1177 | } | |
1178 | ||
771fe6b9 JG |
1179 | WREG32(RADEON_CP_RB_CNTL, tmp); |
1180 | udelay(10); | |
771fe6b9 JG |
1181 | /* Set cp mode to bus mastering & enable cp*/ |
1182 | WREG32(RADEON_CP_CSQ_MODE, | |
1183 | REG_SET(RADEON_INDIRECT2_START, indirect2_start) | | |
1184 | REG_SET(RADEON_INDIRECT1_START, indirect1_start)); | |
d75ee3be AD |
1185 | WREG32(RADEON_CP_RB_WPTR_DELAY, 0); |
1186 | WREG32(RADEON_CP_CSQ_MODE, 0x00004D4D); | |
771fe6b9 | 1187 | WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM); |
2099810f DA |
1188 | |
1189 | /* at this point everything should be setup correctly to enable master */ | |
1190 | pci_set_master(rdev->pdev); | |
1191 | ||
f712812e AD |
1192 | radeon_ring_start(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]); |
1193 | r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring); | |
771fe6b9 JG |
1194 | if (r) { |
1195 | DRM_ERROR("radeon: cp isn't working (%d).\n", r); | |
1196 | return r; | |
1197 | } | |
e32eb50d | 1198 | ring->ready = true; |
53595338 | 1199 | radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size); |
c7eff978 | 1200 | |
16c58081 SK |
1201 | if (!ring->rptr_save_reg /* not resuming from suspend */ |
1202 | && radeon_ring_supports_scratch_reg(rdev, ring)) { | |
c7eff978 AD |
1203 | r = radeon_scratch_get(rdev, &ring->rptr_save_reg); |
1204 | if (r) { | |
1205 | DRM_ERROR("failed to get scratch reg for rptr save (%d).\n", r); | |
1206 | ring->rptr_save_reg = 0; | |
1207 | } | |
1208 | } | |
771fe6b9 JG |
1209 | return 0; |
1210 | } | |
1211 | ||
1212 | void r100_cp_fini(struct radeon_device *rdev) | |
1213 | { | |
45600232 JG |
1214 | if (r100_cp_wait_for_idle(rdev)) { |
1215 | DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n"); | |
1216 | } | |
771fe6b9 | 1217 | /* Disable ring */ |
a18d7ea1 | 1218 | r100_cp_disable(rdev); |
c7eff978 | 1219 | radeon_scratch_free(rdev, rdev->ring[RADEON_RING_TYPE_GFX_INDEX].rptr_save_reg); |
e32eb50d | 1220 | radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]); |
771fe6b9 JG |
1221 | DRM_INFO("radeon: cp finalized\n"); |
1222 | } | |
1223 | ||
1224 | void r100_cp_disable(struct radeon_device *rdev) | |
1225 | { | |
1226 | /* Disable ring */ | |
53595338 | 1227 | radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); |
e32eb50d | 1228 | rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; |
771fe6b9 JG |
1229 | WREG32(RADEON_CP_CSQ_MODE, 0); |
1230 | WREG32(RADEON_CP_CSQ_CNTL, 0); | |
724c80e1 | 1231 | WREG32(R_000770_SCRATCH_UMSK, 0); |
771fe6b9 JG |
1232 | if (r100_gui_wait_for_idle(rdev)) { |
1233 | printk(KERN_WARNING "Failed to wait GUI idle while " | |
1234 | "programming pipes. Bad things might happen.\n"); | |
1235 | } | |
1236 | } | |
1237 | ||
771fe6b9 JG |
1238 | /* |
1239 | * CS functions | |
1240 | */ | |
0242f74d AD |
1241 | int r100_reloc_pitch_offset(struct radeon_cs_parser *p, |
1242 | struct radeon_cs_packet *pkt, | |
1243 | unsigned idx, | |
1244 | unsigned reg) | |
1245 | { | |
1246 | int r; | |
1247 | u32 tile_flags = 0; | |
1248 | u32 tmp; | |
1249 | struct radeon_cs_reloc *reloc; | |
1250 | u32 value; | |
1251 | ||
012e976d | 1252 | r = radeon_cs_packet_next_reloc(p, &reloc, 0); |
0242f74d AD |
1253 | if (r) { |
1254 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", | |
1255 | idx, reg); | |
c3ad63af | 1256 | radeon_cs_dump_packet(p, pkt); |
0242f74d AD |
1257 | return r; |
1258 | } | |
1259 | ||
1260 | value = radeon_get_ib_value(p, idx); | |
1261 | tmp = value & 0x003fffff; | |
df0af440 | 1262 | tmp += (((u32)reloc->gpu_offset) >> 10); |
0242f74d AD |
1263 | |
1264 | if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { | |
df0af440 | 1265 | if (reloc->tiling_flags & RADEON_TILING_MACRO) |
0242f74d | 1266 | tile_flags |= RADEON_DST_TILE_MACRO; |
df0af440 | 1267 | if (reloc->tiling_flags & RADEON_TILING_MICRO) { |
0242f74d AD |
1268 | if (reg == RADEON_SRC_PITCH_OFFSET) { |
1269 | DRM_ERROR("Cannot src blit from microtiled surface\n"); | |
c3ad63af | 1270 | radeon_cs_dump_packet(p, pkt); |
0242f74d AD |
1271 | return -EINVAL; |
1272 | } | |
1273 | tile_flags |= RADEON_DST_TILE_MICRO; | |
1274 | } | |
1275 | ||
1276 | tmp |= tile_flags; | |
1277 | p->ib.ptr[idx] = (value & 0x3fc00000) | tmp; | |
1278 | } else | |
1279 | p->ib.ptr[idx] = (value & 0xffc00000) | tmp; | |
1280 | return 0; | |
1281 | } | |
1282 | ||
1283 | int r100_packet3_load_vbpntr(struct radeon_cs_parser *p, | |
1284 | struct radeon_cs_packet *pkt, | |
1285 | int idx) | |
1286 | { | |
1287 | unsigned c, i; | |
1288 | struct radeon_cs_reloc *reloc; | |
1289 | struct r100_cs_track *track; | |
1290 | int r = 0; | |
1291 | volatile uint32_t *ib; | |
1292 | u32 idx_value; | |
1293 | ||
1294 | ib = p->ib.ptr; | |
1295 | track = (struct r100_cs_track *)p->track; | |
1296 | c = radeon_get_ib_value(p, idx++) & 0x1F; | |
1297 | if (c > 16) { | |
1298 | DRM_ERROR("Only 16 vertex buffers are allowed %d\n", | |
1299 | pkt->opcode); | |
c3ad63af | 1300 | radeon_cs_dump_packet(p, pkt); |
0242f74d AD |
1301 | return -EINVAL; |
1302 | } | |
1303 | track->num_arrays = c; | |
1304 | for (i = 0; i < (c - 1); i+=2, idx+=3) { | |
012e976d | 1305 | r = radeon_cs_packet_next_reloc(p, &reloc, 0); |
0242f74d AD |
1306 | if (r) { |
1307 | DRM_ERROR("No reloc for packet3 %d\n", | |
1308 | pkt->opcode); | |
c3ad63af | 1309 | radeon_cs_dump_packet(p, pkt); |
0242f74d AD |
1310 | return r; |
1311 | } | |
1312 | idx_value = radeon_get_ib_value(p, idx); | |
df0af440 | 1313 | ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset); |
0242f74d AD |
1314 | |
1315 | track->arrays[i + 0].esize = idx_value >> 8; | |
1316 | track->arrays[i + 0].robj = reloc->robj; | |
1317 | track->arrays[i + 0].esize &= 0x7F; | |
012e976d | 1318 | r = radeon_cs_packet_next_reloc(p, &reloc, 0); |
0242f74d AD |
1319 | if (r) { |
1320 | DRM_ERROR("No reloc for packet3 %d\n", | |
1321 | pkt->opcode); | |
c3ad63af | 1322 | radeon_cs_dump_packet(p, pkt); |
0242f74d AD |
1323 | return r; |
1324 | } | |
df0af440 | 1325 | ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->gpu_offset); |
0242f74d AD |
1326 | track->arrays[i + 1].robj = reloc->robj; |
1327 | track->arrays[i + 1].esize = idx_value >> 24; | |
1328 | track->arrays[i + 1].esize &= 0x7F; | |
1329 | } | |
1330 | if (c & 1) { | |
012e976d | 1331 | r = radeon_cs_packet_next_reloc(p, &reloc, 0); |
0242f74d AD |
1332 | if (r) { |
1333 | DRM_ERROR("No reloc for packet3 %d\n", | |
1334 | pkt->opcode); | |
c3ad63af | 1335 | radeon_cs_dump_packet(p, pkt); |
0242f74d AD |
1336 | return r; |
1337 | } | |
1338 | idx_value = radeon_get_ib_value(p, idx); | |
df0af440 | 1339 | ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset); |
0242f74d AD |
1340 | track->arrays[i + 0].robj = reloc->robj; |
1341 | track->arrays[i + 0].esize = idx_value >> 8; | |
1342 | track->arrays[i + 0].esize &= 0x7F; | |
1343 | } | |
1344 | return r; | |
1345 | } | |
1346 | ||
771fe6b9 JG |
1347 | int r100_cs_parse_packet0(struct radeon_cs_parser *p, |
1348 | struct radeon_cs_packet *pkt, | |
068a117c | 1349 | const unsigned *auth, unsigned n, |
771fe6b9 JG |
1350 | radeon_packet0_check_t check) |
1351 | { | |
1352 | unsigned reg; | |
1353 | unsigned i, j, m; | |
1354 | unsigned idx; | |
1355 | int r; | |
1356 | ||
1357 | idx = pkt->idx + 1; | |
1358 | reg = pkt->reg; | |
068a117c JG |
1359 | /* Check that register fall into register range |
1360 | * determined by the number of entry (n) in the | |
1361 | * safe register bitmap. | |
1362 | */ | |
771fe6b9 JG |
1363 | if (pkt->one_reg_wr) { |
1364 | if ((reg >> 7) > n) { | |
1365 | return -EINVAL; | |
1366 | } | |
1367 | } else { | |
1368 | if (((reg + (pkt->count << 2)) >> 7) > n) { | |
1369 | return -EINVAL; | |
1370 | } | |
1371 | } | |
1372 | for (i = 0; i <= pkt->count; i++, idx++) { | |
1373 | j = (reg >> 7); | |
1374 | m = 1 << ((reg >> 2) & 31); | |
1375 | if (auth[j] & m) { | |
1376 | r = check(p, pkt, idx, reg); | |
1377 | if (r) { | |
1378 | return r; | |
1379 | } | |
1380 | } | |
1381 | if (pkt->one_reg_wr) { | |
1382 | if (!(auth[j] & m)) { | |
1383 | break; | |
1384 | } | |
1385 | } else { | |
1386 | reg += 4; | |
1387 | } | |
1388 | } | |
1389 | return 0; | |
1390 | } | |
1391 | ||
531369e6 DA |
1392 | /** |
1393 | * r100_cs_packet_next_vline() - parse userspace VLINE packet | |
1394 | * @parser: parser structure holding parsing context. | |
1395 | * | |
1396 | * Userspace sends a special sequence for VLINE waits. | |
1397 | * PACKET0 - VLINE_START_END + value | |
1398 | * PACKET0 - WAIT_UNTIL +_value | |
1399 | * RELOC (P3) - crtc_id in reloc. | |
1400 | * | |
1401 | * This function parses this and relocates the VLINE START END | |
1402 | * and WAIT UNTIL packets to the correct crtc. | |
1403 | * It also detects a switched off crtc and nulls out the | |
1404 | * wait in that case. | |
1405 | */ | |
1406 | int r100_cs_packet_parse_vline(struct radeon_cs_parser *p) | |
1407 | { | |
531369e6 DA |
1408 | struct drm_mode_object *obj; |
1409 | struct drm_crtc *crtc; | |
1410 | struct radeon_crtc *radeon_crtc; | |
1411 | struct radeon_cs_packet p3reloc, waitreloc; | |
1412 | int crtc_id; | |
1413 | int r; | |
1414 | uint32_t header, h_idx, reg; | |
513bcb46 | 1415 | volatile uint32_t *ib; |
531369e6 | 1416 | |
f2e39221 | 1417 | ib = p->ib.ptr; |
531369e6 DA |
1418 | |
1419 | /* parse the wait until */ | |
c38f34b5 | 1420 | r = radeon_cs_packet_parse(p, &waitreloc, p->idx); |
531369e6 DA |
1421 | if (r) |
1422 | return r; | |
1423 | ||
1424 | /* check its a wait until and only 1 count */ | |
1425 | if (waitreloc.reg != RADEON_WAIT_UNTIL || | |
1426 | waitreloc.count != 0) { | |
1427 | DRM_ERROR("vline wait had illegal wait until segment\n"); | |
a3a88a66 | 1428 | return -EINVAL; |
531369e6 DA |
1429 | } |
1430 | ||
513bcb46 | 1431 | if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) { |
531369e6 | 1432 | DRM_ERROR("vline wait had illegal wait until\n"); |
a3a88a66 | 1433 | return -EINVAL; |
531369e6 DA |
1434 | } |
1435 | ||
1436 | /* jump over the NOP */ | |
c38f34b5 | 1437 | r = radeon_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2); |
531369e6 DA |
1438 | if (r) |
1439 | return r; | |
1440 | ||
1441 | h_idx = p->idx - 2; | |
90ebd065 AD |
1442 | p->idx += waitreloc.count + 2; |
1443 | p->idx += p3reloc.count + 2; | |
531369e6 | 1444 | |
513bcb46 DA |
1445 | header = radeon_get_ib_value(p, h_idx); |
1446 | crtc_id = radeon_get_ib_value(p, h_idx + 5); | |
4e872ae2 | 1447 | reg = R100_CP_PACKET0_GET_REG(header); |
531369e6 DA |
1448 | obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC); |
1449 | if (!obj) { | |
1450 | DRM_ERROR("cannot find crtc %d\n", crtc_id); | |
10e10d34 | 1451 | return -ENOENT; |
531369e6 DA |
1452 | } |
1453 | crtc = obj_to_crtc(obj); | |
1454 | radeon_crtc = to_radeon_crtc(crtc); | |
1455 | crtc_id = radeon_crtc->crtc_id; | |
1456 | ||
1457 | if (!crtc->enabled) { | |
1458 | /* if the CRTC isn't enabled - we need to nop out the wait until */ | |
513bcb46 DA |
1459 | ib[h_idx + 2] = PACKET2(0); |
1460 | ib[h_idx + 3] = PACKET2(0); | |
531369e6 DA |
1461 | } else if (crtc_id == 1) { |
1462 | switch (reg) { | |
1463 | case AVIVO_D1MODE_VLINE_START_END: | |
90ebd065 | 1464 | header &= ~R300_CP_PACKET0_REG_MASK; |
531369e6 DA |
1465 | header |= AVIVO_D2MODE_VLINE_START_END >> 2; |
1466 | break; | |
1467 | case RADEON_CRTC_GUI_TRIG_VLINE: | |
90ebd065 | 1468 | header &= ~R300_CP_PACKET0_REG_MASK; |
531369e6 DA |
1469 | header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2; |
1470 | break; | |
1471 | default: | |
1472 | DRM_ERROR("unknown crtc reloc\n"); | |
a3a88a66 | 1473 | return -EINVAL; |
531369e6 | 1474 | } |
513bcb46 DA |
1475 | ib[h_idx] = header; |
1476 | ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1; | |
531369e6 | 1477 | } |
a3a88a66 PB |
1478 | |
1479 | return 0; | |
531369e6 DA |
1480 | } |
1481 | ||
551ebd83 DA |
1482 | static int r100_get_vtx_size(uint32_t vtx_fmt) |
1483 | { | |
1484 | int vtx_size; | |
1485 | vtx_size = 2; | |
1486 | /* ordered according to bits in spec */ | |
1487 | if (vtx_fmt & RADEON_SE_VTX_FMT_W0) | |
1488 | vtx_size++; | |
1489 | if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR) | |
1490 | vtx_size += 3; | |
1491 | if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA) | |
1492 | vtx_size++; | |
1493 | if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR) | |
1494 | vtx_size++; | |
1495 | if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC) | |
1496 | vtx_size += 3; | |
1497 | if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG) | |
1498 | vtx_size++; | |
1499 | if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC) | |
1500 | vtx_size++; | |
1501 | if (vtx_fmt & RADEON_SE_VTX_FMT_ST0) | |
1502 | vtx_size += 2; | |
1503 | if (vtx_fmt & RADEON_SE_VTX_FMT_ST1) | |
1504 | vtx_size += 2; | |
1505 | if (vtx_fmt & RADEON_SE_VTX_FMT_Q1) | |
1506 | vtx_size++; | |
1507 | if (vtx_fmt & RADEON_SE_VTX_FMT_ST2) | |
1508 | vtx_size += 2; | |
1509 | if (vtx_fmt & RADEON_SE_VTX_FMT_Q2) | |
1510 | vtx_size++; | |
1511 | if (vtx_fmt & RADEON_SE_VTX_FMT_ST3) | |
1512 | vtx_size += 2; | |
1513 | if (vtx_fmt & RADEON_SE_VTX_FMT_Q3) | |
1514 | vtx_size++; | |
1515 | if (vtx_fmt & RADEON_SE_VTX_FMT_Q0) | |
1516 | vtx_size++; | |
1517 | /* blend weight */ | |
1518 | if (vtx_fmt & (0x7 << 15)) | |
1519 | vtx_size += (vtx_fmt >> 15) & 0x7; | |
1520 | if (vtx_fmt & RADEON_SE_VTX_FMT_N0) | |
1521 | vtx_size += 3; | |
1522 | if (vtx_fmt & RADEON_SE_VTX_FMT_XY1) | |
1523 | vtx_size += 2; | |
1524 | if (vtx_fmt & RADEON_SE_VTX_FMT_Z1) | |
1525 | vtx_size++; | |
1526 | if (vtx_fmt & RADEON_SE_VTX_FMT_W1) | |
1527 | vtx_size++; | |
1528 | if (vtx_fmt & RADEON_SE_VTX_FMT_N1) | |
1529 | vtx_size++; | |
1530 | if (vtx_fmt & RADEON_SE_VTX_FMT_Z) | |
1531 | vtx_size++; | |
1532 | return vtx_size; | |
1533 | } | |
1534 | ||
771fe6b9 | 1535 | static int r100_packet0_check(struct radeon_cs_parser *p, |
551ebd83 DA |
1536 | struct radeon_cs_packet *pkt, |
1537 | unsigned idx, unsigned reg) | |
771fe6b9 | 1538 | { |
771fe6b9 | 1539 | struct radeon_cs_reloc *reloc; |
551ebd83 | 1540 | struct r100_cs_track *track; |
771fe6b9 JG |
1541 | volatile uint32_t *ib; |
1542 | uint32_t tmp; | |
771fe6b9 | 1543 | int r; |
551ebd83 | 1544 | int i, face; |
e024e110 | 1545 | u32 tile_flags = 0; |
513bcb46 | 1546 | u32 idx_value; |
771fe6b9 | 1547 | |
f2e39221 | 1548 | ib = p->ib.ptr; |
551ebd83 DA |
1549 | track = (struct r100_cs_track *)p->track; |
1550 | ||
513bcb46 DA |
1551 | idx_value = radeon_get_ib_value(p, idx); |
1552 | ||
551ebd83 DA |
1553 | switch (reg) { |
1554 | case RADEON_CRTC_GUI_TRIG_VLINE: | |
1555 | r = r100_cs_packet_parse_vline(p); | |
1556 | if (r) { | |
1557 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", | |
1558 | idx, reg); | |
c3ad63af | 1559 | radeon_cs_dump_packet(p, pkt); |
551ebd83 DA |
1560 | return r; |
1561 | } | |
1562 | break; | |
771fe6b9 JG |
1563 | /* FIXME: only allow PACKET3 blit? easier to check for out of |
1564 | * range access */ | |
551ebd83 DA |
1565 | case RADEON_DST_PITCH_OFFSET: |
1566 | case RADEON_SRC_PITCH_OFFSET: | |
1567 | r = r100_reloc_pitch_offset(p, pkt, idx, reg); | |
1568 | if (r) | |
1569 | return r; | |
1570 | break; | |
1571 | case RADEON_RB3D_DEPTHOFFSET: | |
012e976d | 1572 | r = radeon_cs_packet_next_reloc(p, &reloc, 0); |
551ebd83 DA |
1573 | if (r) { |
1574 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", | |
1575 | idx, reg); | |
c3ad63af | 1576 | radeon_cs_dump_packet(p, pkt); |
551ebd83 DA |
1577 | return r; |
1578 | } | |
1579 | track->zb.robj = reloc->robj; | |
513bcb46 | 1580 | track->zb.offset = idx_value; |
40b4a759 | 1581 | track->zb_dirty = true; |
df0af440 | 1582 | ib[idx] = idx_value + ((u32)reloc->gpu_offset); |
551ebd83 DA |
1583 | break; |
1584 | case RADEON_RB3D_COLOROFFSET: | |
012e976d | 1585 | r = radeon_cs_packet_next_reloc(p, &reloc, 0); |
551ebd83 DA |
1586 | if (r) { |
1587 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", | |
1588 | idx, reg); | |
c3ad63af | 1589 | radeon_cs_dump_packet(p, pkt); |
551ebd83 DA |
1590 | return r; |
1591 | } | |
1592 | track->cb[0].robj = reloc->robj; | |
513bcb46 | 1593 | track->cb[0].offset = idx_value; |
40b4a759 | 1594 | track->cb_dirty = true; |
df0af440 | 1595 | ib[idx] = idx_value + ((u32)reloc->gpu_offset); |
551ebd83 DA |
1596 | break; |
1597 | case RADEON_PP_TXOFFSET_0: | |
1598 | case RADEON_PP_TXOFFSET_1: | |
1599 | case RADEON_PP_TXOFFSET_2: | |
1600 | i = (reg - RADEON_PP_TXOFFSET_0) / 24; | |
012e976d | 1601 | r = radeon_cs_packet_next_reloc(p, &reloc, 0); |
551ebd83 DA |
1602 | if (r) { |
1603 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", | |
1604 | idx, reg); | |
c3ad63af | 1605 | radeon_cs_dump_packet(p, pkt); |
551ebd83 DA |
1606 | return r; |
1607 | } | |
f2746f83 | 1608 | if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { |
df0af440 | 1609 | if (reloc->tiling_flags & RADEON_TILING_MACRO) |
f2746f83 | 1610 | tile_flags |= RADEON_TXO_MACRO_TILE; |
df0af440 | 1611 | if (reloc->tiling_flags & RADEON_TILING_MICRO) |
f2746f83 AD |
1612 | tile_flags |= RADEON_TXO_MICRO_TILE_X2; |
1613 | ||
1614 | tmp = idx_value & ~(0x7 << 2); | |
1615 | tmp |= tile_flags; | |
df0af440 | 1616 | ib[idx] = tmp + ((u32)reloc->gpu_offset); |
f2746f83 | 1617 | } else |
df0af440 | 1618 | ib[idx] = idx_value + ((u32)reloc->gpu_offset); |
551ebd83 | 1619 | track->textures[i].robj = reloc->robj; |
40b4a759 | 1620 | track->tex_dirty = true; |
551ebd83 DA |
1621 | break; |
1622 | case RADEON_PP_CUBIC_OFFSET_T0_0: | |
1623 | case RADEON_PP_CUBIC_OFFSET_T0_1: | |
1624 | case RADEON_PP_CUBIC_OFFSET_T0_2: | |
1625 | case RADEON_PP_CUBIC_OFFSET_T0_3: | |
1626 | case RADEON_PP_CUBIC_OFFSET_T0_4: | |
1627 | i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4; | |
012e976d | 1628 | r = radeon_cs_packet_next_reloc(p, &reloc, 0); |
551ebd83 DA |
1629 | if (r) { |
1630 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", | |
1631 | idx, reg); | |
c3ad63af | 1632 | radeon_cs_dump_packet(p, pkt); |
551ebd83 DA |
1633 | return r; |
1634 | } | |
513bcb46 | 1635 | track->textures[0].cube_info[i].offset = idx_value; |
df0af440 | 1636 | ib[idx] = idx_value + ((u32)reloc->gpu_offset); |
551ebd83 | 1637 | track->textures[0].cube_info[i].robj = reloc->robj; |
40b4a759 | 1638 | track->tex_dirty = true; |
551ebd83 DA |
1639 | break; |
1640 | case RADEON_PP_CUBIC_OFFSET_T1_0: | |
1641 | case RADEON_PP_CUBIC_OFFSET_T1_1: | |
1642 | case RADEON_PP_CUBIC_OFFSET_T1_2: | |
1643 | case RADEON_PP_CUBIC_OFFSET_T1_3: | |
1644 | case RADEON_PP_CUBIC_OFFSET_T1_4: | |
1645 | i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4; | |
012e976d | 1646 | r = radeon_cs_packet_next_reloc(p, &reloc, 0); |
551ebd83 DA |
1647 | if (r) { |
1648 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", | |
1649 | idx, reg); | |
c3ad63af | 1650 | radeon_cs_dump_packet(p, pkt); |
551ebd83 DA |
1651 | return r; |
1652 | } | |
513bcb46 | 1653 | track->textures[1].cube_info[i].offset = idx_value; |
df0af440 | 1654 | ib[idx] = idx_value + ((u32)reloc->gpu_offset); |
551ebd83 | 1655 | track->textures[1].cube_info[i].robj = reloc->robj; |
40b4a759 | 1656 | track->tex_dirty = true; |
551ebd83 DA |
1657 | break; |
1658 | case RADEON_PP_CUBIC_OFFSET_T2_0: | |
1659 | case RADEON_PP_CUBIC_OFFSET_T2_1: | |
1660 | case RADEON_PP_CUBIC_OFFSET_T2_2: | |
1661 | case RADEON_PP_CUBIC_OFFSET_T2_3: | |
1662 | case RADEON_PP_CUBIC_OFFSET_T2_4: | |
1663 | i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4; | |
012e976d | 1664 | r = radeon_cs_packet_next_reloc(p, &reloc, 0); |
551ebd83 DA |
1665 | if (r) { |
1666 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", | |
1667 | idx, reg); | |
c3ad63af | 1668 | radeon_cs_dump_packet(p, pkt); |
551ebd83 DA |
1669 | return r; |
1670 | } | |
513bcb46 | 1671 | track->textures[2].cube_info[i].offset = idx_value; |
df0af440 | 1672 | ib[idx] = idx_value + ((u32)reloc->gpu_offset); |
551ebd83 | 1673 | track->textures[2].cube_info[i].robj = reloc->robj; |
40b4a759 | 1674 | track->tex_dirty = true; |
551ebd83 DA |
1675 | break; |
1676 | case RADEON_RE_WIDTH_HEIGHT: | |
513bcb46 | 1677 | track->maxy = ((idx_value >> 16) & 0x7FF); |
40b4a759 MO |
1678 | track->cb_dirty = true; |
1679 | track->zb_dirty = true; | |
551ebd83 DA |
1680 | break; |
1681 | case RADEON_RB3D_COLORPITCH: | |
012e976d | 1682 | r = radeon_cs_packet_next_reloc(p, &reloc, 0); |
551ebd83 DA |
1683 | if (r) { |
1684 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", | |
1685 | idx, reg); | |
c3ad63af | 1686 | radeon_cs_dump_packet(p, pkt); |
551ebd83 DA |
1687 | return r; |
1688 | } | |
c9068eb2 | 1689 | if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { |
df0af440 | 1690 | if (reloc->tiling_flags & RADEON_TILING_MACRO) |
c9068eb2 | 1691 | tile_flags |= RADEON_COLOR_TILE_ENABLE; |
df0af440 | 1692 | if (reloc->tiling_flags & RADEON_TILING_MICRO) |
c9068eb2 AD |
1693 | tile_flags |= RADEON_COLOR_MICROTILE_ENABLE; |
1694 | ||
1695 | tmp = idx_value & ~(0x7 << 16); | |
1696 | tmp |= tile_flags; | |
1697 | ib[idx] = tmp; | |
1698 | } else | |
1699 | ib[idx] = idx_value; | |
e024e110 | 1700 | |
513bcb46 | 1701 | track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK; |
40b4a759 | 1702 | track->cb_dirty = true; |
551ebd83 DA |
1703 | break; |
1704 | case RADEON_RB3D_DEPTHPITCH: | |
513bcb46 | 1705 | track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK; |
40b4a759 | 1706 | track->zb_dirty = true; |
551ebd83 DA |
1707 | break; |
1708 | case RADEON_RB3D_CNTL: | |
513bcb46 | 1709 | switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) { |
551ebd83 DA |
1710 | case 7: |
1711 | case 8: | |
1712 | case 9: | |
1713 | case 11: | |
1714 | case 12: | |
1715 | track->cb[0].cpp = 1; | |
e024e110 | 1716 | break; |
551ebd83 DA |
1717 | case 3: |
1718 | case 4: | |
1719 | case 15: | |
1720 | track->cb[0].cpp = 2; | |
1721 | break; | |
1722 | case 6: | |
1723 | track->cb[0].cpp = 4; | |
1724 | break; | |
1725 | default: | |
1726 | DRM_ERROR("Invalid color buffer format (%d) !\n", | |
513bcb46 | 1727 | ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f)); |
551ebd83 DA |
1728 | return -EINVAL; |
1729 | } | |
513bcb46 | 1730 | track->z_enabled = !!(idx_value & RADEON_Z_ENABLE); |
40b4a759 MO |
1731 | track->cb_dirty = true; |
1732 | track->zb_dirty = true; | |
551ebd83 DA |
1733 | break; |
1734 | case RADEON_RB3D_ZSTENCILCNTL: | |
513bcb46 | 1735 | switch (idx_value & 0xf) { |
551ebd83 DA |
1736 | case 0: |
1737 | track->zb.cpp = 2; | |
1738 | break; | |
1739 | case 2: | |
1740 | case 3: | |
1741 | case 4: | |
1742 | case 5: | |
1743 | case 9: | |
1744 | case 11: | |
1745 | track->zb.cpp = 4; | |
17782d99 | 1746 | break; |
771fe6b9 | 1747 | default: |
771fe6b9 JG |
1748 | break; |
1749 | } | |
40b4a759 | 1750 | track->zb_dirty = true; |
551ebd83 DA |
1751 | break; |
1752 | case RADEON_RB3D_ZPASS_ADDR: | |
012e976d | 1753 | r = radeon_cs_packet_next_reloc(p, &reloc, 0); |
551ebd83 DA |
1754 | if (r) { |
1755 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", | |
1756 | idx, reg); | |
c3ad63af | 1757 | radeon_cs_dump_packet(p, pkt); |
551ebd83 DA |
1758 | return r; |
1759 | } | |
df0af440 | 1760 | ib[idx] = idx_value + ((u32)reloc->gpu_offset); |
551ebd83 DA |
1761 | break; |
1762 | case RADEON_PP_CNTL: | |
1763 | { | |
513bcb46 | 1764 | uint32_t temp = idx_value >> 4; |
551ebd83 DA |
1765 | for (i = 0; i < track->num_texture; i++) |
1766 | track->textures[i].enabled = !!(temp & (1 << i)); | |
40b4a759 | 1767 | track->tex_dirty = true; |
551ebd83 DA |
1768 | } |
1769 | break; | |
1770 | case RADEON_SE_VF_CNTL: | |
513bcb46 | 1771 | track->vap_vf_cntl = idx_value; |
551ebd83 DA |
1772 | break; |
1773 | case RADEON_SE_VTX_FMT: | |
513bcb46 | 1774 | track->vtx_size = r100_get_vtx_size(idx_value); |
551ebd83 DA |
1775 | break; |
1776 | case RADEON_PP_TEX_SIZE_0: | |
1777 | case RADEON_PP_TEX_SIZE_1: | |
1778 | case RADEON_PP_TEX_SIZE_2: | |
1779 | i = (reg - RADEON_PP_TEX_SIZE_0) / 8; | |
513bcb46 DA |
1780 | track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1; |
1781 | track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1; | |
40b4a759 | 1782 | track->tex_dirty = true; |
551ebd83 DA |
1783 | break; |
1784 | case RADEON_PP_TEX_PITCH_0: | |
1785 | case RADEON_PP_TEX_PITCH_1: | |
1786 | case RADEON_PP_TEX_PITCH_2: | |
1787 | i = (reg - RADEON_PP_TEX_PITCH_0) / 8; | |
513bcb46 | 1788 | track->textures[i].pitch = idx_value + 32; |
40b4a759 | 1789 | track->tex_dirty = true; |
551ebd83 DA |
1790 | break; |
1791 | case RADEON_PP_TXFILTER_0: | |
1792 | case RADEON_PP_TXFILTER_1: | |
1793 | case RADEON_PP_TXFILTER_2: | |
1794 | i = (reg - RADEON_PP_TXFILTER_0) / 24; | |
513bcb46 | 1795 | track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK) |
551ebd83 | 1796 | >> RADEON_MAX_MIP_LEVEL_SHIFT); |
513bcb46 | 1797 | tmp = (idx_value >> 23) & 0x7; |
551ebd83 DA |
1798 | if (tmp == 2 || tmp == 6) |
1799 | track->textures[i].roundup_w = false; | |
513bcb46 | 1800 | tmp = (idx_value >> 27) & 0x7; |
551ebd83 DA |
1801 | if (tmp == 2 || tmp == 6) |
1802 | track->textures[i].roundup_h = false; | |
40b4a759 | 1803 | track->tex_dirty = true; |
551ebd83 DA |
1804 | break; |
1805 | case RADEON_PP_TXFORMAT_0: | |
1806 | case RADEON_PP_TXFORMAT_1: | |
1807 | case RADEON_PP_TXFORMAT_2: | |
1808 | i = (reg - RADEON_PP_TXFORMAT_0) / 24; | |
513bcb46 | 1809 | if (idx_value & RADEON_TXFORMAT_NON_POWER2) { |
551ebd83 DA |
1810 | track->textures[i].use_pitch = 1; |
1811 | } else { | |
1812 | track->textures[i].use_pitch = 0; | |
513bcb46 DA |
1813 | track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK); |
1814 | track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK); | |
551ebd83 | 1815 | } |
513bcb46 | 1816 | if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE) |
551ebd83 | 1817 | track->textures[i].tex_coord_type = 2; |
513bcb46 | 1818 | switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) { |
551ebd83 DA |
1819 | case RADEON_TXFORMAT_I8: |
1820 | case RADEON_TXFORMAT_RGB332: | |
1821 | case RADEON_TXFORMAT_Y8: | |
1822 | track->textures[i].cpp = 1; | |
f9da52d5 | 1823 | track->textures[i].compress_format = R100_TRACK_COMP_NONE; |
551ebd83 DA |
1824 | break; |
1825 | case RADEON_TXFORMAT_AI88: | |
1826 | case RADEON_TXFORMAT_ARGB1555: | |
1827 | case RADEON_TXFORMAT_RGB565: | |
1828 | case RADEON_TXFORMAT_ARGB4444: | |
1829 | case RADEON_TXFORMAT_VYUY422: | |
1830 | case RADEON_TXFORMAT_YVYU422: | |
551ebd83 DA |
1831 | case RADEON_TXFORMAT_SHADOW16: |
1832 | case RADEON_TXFORMAT_LDUDV655: | |
1833 | case RADEON_TXFORMAT_DUDV88: | |
1834 | track->textures[i].cpp = 2; | |
f9da52d5 | 1835 | track->textures[i].compress_format = R100_TRACK_COMP_NONE; |
771fe6b9 | 1836 | break; |
551ebd83 DA |
1837 | case RADEON_TXFORMAT_ARGB8888: |
1838 | case RADEON_TXFORMAT_RGBA8888: | |
551ebd83 DA |
1839 | case RADEON_TXFORMAT_SHADOW32: |
1840 | case RADEON_TXFORMAT_LDUDUV8888: | |
1841 | track->textures[i].cpp = 4; | |
f9da52d5 | 1842 | track->textures[i].compress_format = R100_TRACK_COMP_NONE; |
551ebd83 | 1843 | break; |
d785d78b DA |
1844 | case RADEON_TXFORMAT_DXT1: |
1845 | track->textures[i].cpp = 1; | |
1846 | track->textures[i].compress_format = R100_TRACK_COMP_DXT1; | |
1847 | break; | |
1848 | case RADEON_TXFORMAT_DXT23: | |
1849 | case RADEON_TXFORMAT_DXT45: | |
1850 | track->textures[i].cpp = 1; | |
1851 | track->textures[i].compress_format = R100_TRACK_COMP_DXT35; | |
1852 | break; | |
551ebd83 | 1853 | } |
513bcb46 DA |
1854 | track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf); |
1855 | track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf); | |
40b4a759 | 1856 | track->tex_dirty = true; |
551ebd83 DA |
1857 | break; |
1858 | case RADEON_PP_CUBIC_FACES_0: | |
1859 | case RADEON_PP_CUBIC_FACES_1: | |
1860 | case RADEON_PP_CUBIC_FACES_2: | |
513bcb46 | 1861 | tmp = idx_value; |
551ebd83 DA |
1862 | i = (reg - RADEON_PP_CUBIC_FACES_0) / 4; |
1863 | for (face = 0; face < 4; face++) { | |
1864 | track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf); | |
1865 | track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf); | |
771fe6b9 | 1866 | } |
40b4a759 | 1867 | track->tex_dirty = true; |
551ebd83 DA |
1868 | break; |
1869 | default: | |
1870 | printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n", | |
1871 | reg, idx); | |
1872 | return -EINVAL; | |
771fe6b9 JG |
1873 | } |
1874 | return 0; | |
1875 | } | |
1876 | ||
068a117c JG |
1877 | int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p, |
1878 | struct radeon_cs_packet *pkt, | |
4c788679 | 1879 | struct radeon_bo *robj) |
068a117c | 1880 | { |
068a117c | 1881 | unsigned idx; |
513bcb46 | 1882 | u32 value; |
068a117c | 1883 | idx = pkt->idx + 1; |
513bcb46 | 1884 | value = radeon_get_ib_value(p, idx + 2); |
4c788679 | 1885 | if ((value + 1) > radeon_bo_size(robj)) { |
068a117c JG |
1886 | DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER " |
1887 | "(need %u have %lu) !\n", | |
513bcb46 | 1888 | value + 1, |
4c788679 | 1889 | radeon_bo_size(robj)); |
068a117c JG |
1890 | return -EINVAL; |
1891 | } | |
1892 | return 0; | |
1893 | } | |
1894 | ||
771fe6b9 JG |
1895 | static int r100_packet3_check(struct radeon_cs_parser *p, |
1896 | struct radeon_cs_packet *pkt) | |
1897 | { | |
771fe6b9 | 1898 | struct radeon_cs_reloc *reloc; |
551ebd83 | 1899 | struct r100_cs_track *track; |
771fe6b9 | 1900 | unsigned idx; |
771fe6b9 JG |
1901 | volatile uint32_t *ib; |
1902 | int r; | |
1903 | ||
f2e39221 | 1904 | ib = p->ib.ptr; |
771fe6b9 | 1905 | idx = pkt->idx + 1; |
551ebd83 | 1906 | track = (struct r100_cs_track *)p->track; |
771fe6b9 JG |
1907 | switch (pkt->opcode) { |
1908 | case PACKET3_3D_LOAD_VBPNTR: | |
513bcb46 DA |
1909 | r = r100_packet3_load_vbpntr(p, pkt, idx); |
1910 | if (r) | |
1911 | return r; | |
771fe6b9 JG |
1912 | break; |
1913 | case PACKET3_INDX_BUFFER: | |
012e976d | 1914 | r = radeon_cs_packet_next_reloc(p, &reloc, 0); |
771fe6b9 JG |
1915 | if (r) { |
1916 | DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode); | |
c3ad63af | 1917 | radeon_cs_dump_packet(p, pkt); |
771fe6b9 JG |
1918 | return r; |
1919 | } | |
df0af440 | 1920 | ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->gpu_offset); |
068a117c JG |
1921 | r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj); |
1922 | if (r) { | |
1923 | return r; | |
1924 | } | |
771fe6b9 JG |
1925 | break; |
1926 | case 0x23: | |
771fe6b9 | 1927 | /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */ |
012e976d | 1928 | r = radeon_cs_packet_next_reloc(p, &reloc, 0); |
771fe6b9 JG |
1929 | if (r) { |
1930 | DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode); | |
c3ad63af | 1931 | radeon_cs_dump_packet(p, pkt); |
771fe6b9 JG |
1932 | return r; |
1933 | } | |
df0af440 | 1934 | ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->gpu_offset); |
551ebd83 | 1935 | track->num_arrays = 1; |
513bcb46 | 1936 | track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2)); |
551ebd83 DA |
1937 | |
1938 | track->arrays[0].robj = reloc->robj; | |
1939 | track->arrays[0].esize = track->vtx_size; | |
1940 | ||
513bcb46 | 1941 | track->max_indx = radeon_get_ib_value(p, idx+1); |
551ebd83 | 1942 | |
513bcb46 | 1943 | track->vap_vf_cntl = radeon_get_ib_value(p, idx+3); |
551ebd83 DA |
1944 | track->immd_dwords = pkt->count - 1; |
1945 | r = r100_cs_track_check(p->rdev, track); | |
1946 | if (r) | |
1947 | return r; | |
771fe6b9 JG |
1948 | break; |
1949 | case PACKET3_3D_DRAW_IMMD: | |
513bcb46 | 1950 | if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) { |
551ebd83 DA |
1951 | DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); |
1952 | return -EINVAL; | |
1953 | } | |
cf57fc7a | 1954 | track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0)); |
513bcb46 | 1955 | track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); |
551ebd83 DA |
1956 | track->immd_dwords = pkt->count - 1; |
1957 | r = r100_cs_track_check(p->rdev, track); | |
1958 | if (r) | |
1959 | return r; | |
1960 | break; | |
771fe6b9 JG |
1961 | /* triggers drawing using in-packet vertex data */ |
1962 | case PACKET3_3D_DRAW_IMMD_2: | |
513bcb46 | 1963 | if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) { |
551ebd83 DA |
1964 | DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); |
1965 | return -EINVAL; | |
1966 | } | |
513bcb46 | 1967 | track->vap_vf_cntl = radeon_get_ib_value(p, idx); |
551ebd83 DA |
1968 | track->immd_dwords = pkt->count; |
1969 | r = r100_cs_track_check(p->rdev, track); | |
1970 | if (r) | |
1971 | return r; | |
1972 | break; | |
771fe6b9 JG |
1973 | /* triggers drawing using in-packet vertex data */ |
1974 | case PACKET3_3D_DRAW_VBUF_2: | |
513bcb46 | 1975 | track->vap_vf_cntl = radeon_get_ib_value(p, idx); |
551ebd83 DA |
1976 | r = r100_cs_track_check(p->rdev, track); |
1977 | if (r) | |
1978 | return r; | |
1979 | break; | |
771fe6b9 JG |
1980 | /* triggers drawing of vertex buffers setup elsewhere */ |
1981 | case PACKET3_3D_DRAW_INDX_2: | |
513bcb46 | 1982 | track->vap_vf_cntl = radeon_get_ib_value(p, idx); |
551ebd83 DA |
1983 | r = r100_cs_track_check(p->rdev, track); |
1984 | if (r) | |
1985 | return r; | |
1986 | break; | |
771fe6b9 JG |
1987 | /* triggers drawing using indices to vertex buffer */ |
1988 | case PACKET3_3D_DRAW_VBUF: | |
513bcb46 | 1989 | track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); |
551ebd83 DA |
1990 | r = r100_cs_track_check(p->rdev, track); |
1991 | if (r) | |
1992 | return r; | |
1993 | break; | |
771fe6b9 JG |
1994 | /* triggers drawing of vertex buffers setup elsewhere */ |
1995 | case PACKET3_3D_DRAW_INDX: | |
513bcb46 | 1996 | track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); |
551ebd83 DA |
1997 | r = r100_cs_track_check(p->rdev, track); |
1998 | if (r) | |
1999 | return r; | |
2000 | break; | |
771fe6b9 | 2001 | /* triggers drawing using indices to vertex buffer */ |
ab9e1f59 DA |
2002 | case PACKET3_3D_CLEAR_HIZ: |
2003 | case PACKET3_3D_CLEAR_ZMASK: | |
2004 | if (p->rdev->hyperz_filp != p->filp) | |
2005 | return -EINVAL; | |
2006 | break; | |
771fe6b9 JG |
2007 | case PACKET3_NOP: |
2008 | break; | |
2009 | default: | |
2010 | DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode); | |
2011 | return -EINVAL; | |
2012 | } | |
2013 | return 0; | |
2014 | } | |
2015 | ||
2016 | int r100_cs_parse(struct radeon_cs_parser *p) | |
2017 | { | |
2018 | struct radeon_cs_packet pkt; | |
9f022ddf | 2019 | struct r100_cs_track *track; |
771fe6b9 JG |
2020 | int r; |
2021 | ||
9f022ddf | 2022 | track = kzalloc(sizeof(*track), GFP_KERNEL); |
ce067913 DC |
2023 | if (!track) |
2024 | return -ENOMEM; | |
9f022ddf JG |
2025 | r100_cs_track_clear(p->rdev, track); |
2026 | p->track = track; | |
771fe6b9 | 2027 | do { |
c38f34b5 | 2028 | r = radeon_cs_packet_parse(p, &pkt, p->idx); |
771fe6b9 JG |
2029 | if (r) { |
2030 | return r; | |
2031 | } | |
2032 | p->idx += pkt.count + 2; | |
2033 | switch (pkt.type) { | |
4e872ae2 | 2034 | case RADEON_PACKET_TYPE0: |
66b3543e IH |
2035 | if (p->rdev->family >= CHIP_R200) |
2036 | r = r100_cs_parse_packet0(p, &pkt, | |
2037 | p->rdev->config.r100.reg_safe_bm, | |
2038 | p->rdev->config.r100.reg_safe_bm_size, | |
2039 | &r200_packet0_check); | |
2040 | else | |
2041 | r = r100_cs_parse_packet0(p, &pkt, | |
2042 | p->rdev->config.r100.reg_safe_bm, | |
2043 | p->rdev->config.r100.reg_safe_bm_size, | |
2044 | &r100_packet0_check); | |
2045 | break; | |
4e872ae2 | 2046 | case RADEON_PACKET_TYPE2: |
66b3543e | 2047 | break; |
4e872ae2 | 2048 | case RADEON_PACKET_TYPE3: |
66b3543e IH |
2049 | r = r100_packet3_check(p, &pkt); |
2050 | break; | |
2051 | default: | |
2052 | DRM_ERROR("Unknown packet type %d !\n", | |
2053 | pkt.type); | |
2054 | return -EINVAL; | |
771fe6b9 | 2055 | } |
66b3543e | 2056 | if (r) |
771fe6b9 | 2057 | return r; |
771fe6b9 JG |
2058 | } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw); |
2059 | return 0; | |
2060 | } | |
2061 | ||
0242f74d | 2062 | static void r100_cs_track_texture_print(struct r100_cs_track_texture *t) |
771fe6b9 | 2063 | { |
0242f74d AD |
2064 | DRM_ERROR("pitch %d\n", t->pitch); |
2065 | DRM_ERROR("use_pitch %d\n", t->use_pitch); | |
2066 | DRM_ERROR("width %d\n", t->width); | |
2067 | DRM_ERROR("width_11 %d\n", t->width_11); | |
2068 | DRM_ERROR("height %d\n", t->height); | |
2069 | DRM_ERROR("height_11 %d\n", t->height_11); | |
2070 | DRM_ERROR("num levels %d\n", t->num_levels); | |
2071 | DRM_ERROR("depth %d\n", t->txdepth); | |
2072 | DRM_ERROR("bpp %d\n", t->cpp); | |
2073 | DRM_ERROR("coordinate type %d\n", t->tex_coord_type); | |
2074 | DRM_ERROR("width round to power of 2 %d\n", t->roundup_w); | |
2075 | DRM_ERROR("height round to power of 2 %d\n", t->roundup_h); | |
2076 | DRM_ERROR("compress format %d\n", t->compress_format); | |
771fe6b9 JG |
2077 | } |
2078 | ||
0242f74d | 2079 | static int r100_track_compress_size(int compress_format, int w, int h) |
771fe6b9 | 2080 | { |
0242f74d AD |
2081 | int block_width, block_height, block_bytes; |
2082 | int wblocks, hblocks; | |
2083 | int min_wblocks; | |
2084 | int sz; | |
771fe6b9 | 2085 | |
0242f74d AD |
2086 | block_width = 4; |
2087 | block_height = 4; | |
2088 | ||
2089 | switch (compress_format) { | |
2090 | case R100_TRACK_COMP_DXT1: | |
2091 | block_bytes = 8; | |
2092 | min_wblocks = 4; | |
2093 | break; | |
2094 | default: | |
2095 | case R100_TRACK_COMP_DXT35: | |
2096 | block_bytes = 16; | |
2097 | min_wblocks = 2; | |
2098 | break; | |
771fe6b9 | 2099 | } |
0242f74d AD |
2100 | |
2101 | hblocks = (h + block_height - 1) / block_height; | |
2102 | wblocks = (w + block_width - 1) / block_width; | |
2103 | if (wblocks < min_wblocks) | |
2104 | wblocks = min_wblocks; | |
2105 | sz = wblocks * hblocks * block_bytes; | |
2106 | return sz; | |
771fe6b9 JG |
2107 | } |
2108 | ||
0242f74d AD |
2109 | static int r100_cs_track_cube(struct radeon_device *rdev, |
2110 | struct r100_cs_track *track, unsigned idx) | |
771fe6b9 | 2111 | { |
0242f74d AD |
2112 | unsigned face, w, h; |
2113 | struct radeon_bo *cube_robj; | |
2114 | unsigned long size; | |
2115 | unsigned compress_format = track->textures[idx].compress_format; | |
771fe6b9 | 2116 | |
0242f74d AD |
2117 | for (face = 0; face < 5; face++) { |
2118 | cube_robj = track->textures[idx].cube_info[face].robj; | |
2119 | w = track->textures[idx].cube_info[face].width; | |
2120 | h = track->textures[idx].cube_info[face].height; | |
771fe6b9 | 2121 | |
0242f74d AD |
2122 | if (compress_format) { |
2123 | size = r100_track_compress_size(compress_format, w, h); | |
2124 | } else | |
2125 | size = w * h; | |
2126 | size *= track->textures[idx].cpp; | |
2127 | ||
2128 | size += track->textures[idx].cube_info[face].offset; | |
2129 | ||
2130 | if (size > radeon_bo_size(cube_robj)) { | |
2131 | DRM_ERROR("Cube texture offset greater than object size %lu %lu\n", | |
2132 | size, radeon_bo_size(cube_robj)); | |
2133 | r100_cs_track_texture_print(&track->textures[idx]); | |
2134 | return -1; | |
771fe6b9 | 2135 | } |
771fe6b9 | 2136 | } |
0242f74d | 2137 | return 0; |
771fe6b9 JG |
2138 | } |
2139 | ||
0242f74d AD |
2140 | static int r100_cs_track_texture_check(struct radeon_device *rdev, |
2141 | struct r100_cs_track *track) | |
771fe6b9 | 2142 | { |
0242f74d AD |
2143 | struct radeon_bo *robj; |
2144 | unsigned long size; | |
2145 | unsigned u, i, w, h, d; | |
2146 | int ret; | |
771fe6b9 | 2147 | |
0242f74d AD |
2148 | for (u = 0; u < track->num_texture; u++) { |
2149 | if (!track->textures[u].enabled) | |
2150 | continue; | |
2151 | if (track->textures[u].lookup_disable) | |
2152 | continue; | |
2153 | robj = track->textures[u].robj; | |
2154 | if (robj == NULL) { | |
2155 | DRM_ERROR("No texture bound to unit %u\n", u); | |
2156 | return -EINVAL; | |
771fe6b9 | 2157 | } |
0242f74d AD |
2158 | size = 0; |
2159 | for (i = 0; i <= track->textures[u].num_levels; i++) { | |
2160 | if (track->textures[u].use_pitch) { | |
2161 | if (rdev->family < CHIP_R300) | |
2162 | w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i); | |
2163 | else | |
2164 | w = track->textures[u].pitch / (1 << i); | |
2165 | } else { | |
2166 | w = track->textures[u].width; | |
2167 | if (rdev->family >= CHIP_RV515) | |
2168 | w |= track->textures[u].width_11; | |
2169 | w = w / (1 << i); | |
2170 | if (track->textures[u].roundup_w) | |
2171 | w = roundup_pow_of_two(w); | |
2172 | } | |
2173 | h = track->textures[u].height; | |
2174 | if (rdev->family >= CHIP_RV515) | |
2175 | h |= track->textures[u].height_11; | |
2176 | h = h / (1 << i); | |
2177 | if (track->textures[u].roundup_h) | |
2178 | h = roundup_pow_of_two(h); | |
2179 | if (track->textures[u].tex_coord_type == 1) { | |
2180 | d = (1 << track->textures[u].txdepth) / (1 << i); | |
2181 | if (!d) | |
2182 | d = 1; | |
2183 | } else { | |
2184 | d = 1; | |
2185 | } | |
2186 | if (track->textures[u].compress_format) { | |
771fe6b9 | 2187 | |
0242f74d AD |
2188 | size += r100_track_compress_size(track->textures[u].compress_format, w, h) * d; |
2189 | /* compressed textures are block based */ | |
2190 | } else | |
2191 | size += w * h * d; | |
2192 | } | |
2193 | size *= track->textures[u].cpp; | |
771fe6b9 | 2194 | |
0242f74d AD |
2195 | switch (track->textures[u].tex_coord_type) { |
2196 | case 0: | |
2197 | case 1: | |
2198 | break; | |
2199 | case 2: | |
2200 | if (track->separate_cube) { | |
2201 | ret = r100_cs_track_cube(rdev, track, u); | |
2202 | if (ret) | |
2203 | return ret; | |
2204 | } else | |
2205 | size *= 6; | |
2206 | break; | |
2207 | default: | |
2208 | DRM_ERROR("Invalid texture coordinate type %u for unit " | |
2209 | "%u\n", track->textures[u].tex_coord_type, u); | |
2210 | return -EINVAL; | |
2211 | } | |
2212 | if (size > radeon_bo_size(robj)) { | |
2213 | DRM_ERROR("Texture of unit %u needs %lu bytes but is " | |
2214 | "%lu\n", u, size, radeon_bo_size(robj)); | |
2215 | r100_cs_track_texture_print(&track->textures[u]); | |
2216 | return -EINVAL; | |
771fe6b9 | 2217 | } |
771fe6b9 | 2218 | } |
0242f74d | 2219 | return 0; |
771fe6b9 JG |
2220 | } |
2221 | ||
0242f74d | 2222 | int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track) |
771fe6b9 JG |
2223 | { |
2224 | unsigned i; | |
0242f74d AD |
2225 | unsigned long size; |
2226 | unsigned prim_walk; | |
2227 | unsigned nverts; | |
2228 | unsigned num_cb = track->cb_dirty ? track->num_cb : 0; | |
771fe6b9 | 2229 | |
0242f74d AD |
2230 | if (num_cb && !track->zb_cb_clear && !track->color_channel_mask && |
2231 | !track->blend_read_enable) | |
2232 | num_cb = 0; | |
2233 | ||
2234 | for (i = 0; i < num_cb; i++) { | |
2235 | if (track->cb[i].robj == NULL) { | |
2236 | DRM_ERROR("[drm] No buffer for color buffer %d !\n", i); | |
2237 | return -EINVAL; | |
2238 | } | |
2239 | size = track->cb[i].pitch * track->cb[i].cpp * track->maxy; | |
2240 | size += track->cb[i].offset; | |
2241 | if (size > radeon_bo_size(track->cb[i].robj)) { | |
2242 | DRM_ERROR("[drm] Buffer too small for color buffer %d " | |
2243 | "(need %lu have %lu) !\n", i, size, | |
2244 | radeon_bo_size(track->cb[i].robj)); | |
2245 | DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n", | |
2246 | i, track->cb[i].pitch, track->cb[i].cpp, | |
2247 | track->cb[i].offset, track->maxy); | |
2248 | return -EINVAL; | |
771fe6b9 | 2249 | } |
771fe6b9 | 2250 | } |
0242f74d | 2251 | track->cb_dirty = false; |
771fe6b9 | 2252 | |
0242f74d AD |
2253 | if (track->zb_dirty && track->z_enabled) { |
2254 | if (track->zb.robj == NULL) { | |
2255 | DRM_ERROR("[drm] No buffer for z buffer !\n"); | |
2256 | return -EINVAL; | |
2257 | } | |
2258 | size = track->zb.pitch * track->zb.cpp * track->maxy; | |
2259 | size += track->zb.offset; | |
2260 | if (size > radeon_bo_size(track->zb.robj)) { | |
2261 | DRM_ERROR("[drm] Buffer too small for z buffer " | |
2262 | "(need %lu have %lu) !\n", size, | |
2263 | radeon_bo_size(track->zb.robj)); | |
2264 | DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n", | |
2265 | track->zb.pitch, track->zb.cpp, | |
2266 | track->zb.offset, track->maxy); | |
2267 | return -EINVAL; | |
2268 | } | |
225758d8 | 2269 | } |
0242f74d | 2270 | track->zb_dirty = false; |
771fe6b9 | 2271 | |
0242f74d AD |
2272 | if (track->aa_dirty && track->aaresolve) { |
2273 | if (track->aa.robj == NULL) { | |
2274 | DRM_ERROR("[drm] No buffer for AA resolve buffer %d !\n", i); | |
2275 | return -EINVAL; | |
2276 | } | |
2277 | /* I believe the format comes from colorbuffer0. */ | |
2278 | size = track->aa.pitch * track->cb[0].cpp * track->maxy; | |
2279 | size += track->aa.offset; | |
2280 | if (size > radeon_bo_size(track->aa.robj)) { | |
2281 | DRM_ERROR("[drm] Buffer too small for AA resolve buffer %d " | |
2282 | "(need %lu have %lu) !\n", i, size, | |
2283 | radeon_bo_size(track->aa.robj)); | |
2284 | DRM_ERROR("[drm] AA resolve buffer %d (%u %u %u %u)\n", | |
2285 | i, track->aa.pitch, track->cb[0].cpp, | |
2286 | track->aa.offset, track->maxy); | |
2287 | return -EINVAL; | |
2288 | } | |
2289 | } | |
2290 | track->aa_dirty = false; | |
771fe6b9 | 2291 | |
0242f74d AD |
2292 | prim_walk = (track->vap_vf_cntl >> 4) & 0x3; |
2293 | if (track->vap_vf_cntl & (1 << 14)) { | |
2294 | nverts = track->vap_alt_nverts; | |
2295 | } else { | |
2296 | nverts = (track->vap_vf_cntl >> 16) & 0xFFFF; | |
2739d49c | 2297 | } |
0242f74d AD |
2298 | switch (prim_walk) { |
2299 | case 1: | |
2300 | for (i = 0; i < track->num_arrays; i++) { | |
2301 | size = track->arrays[i].esize * track->max_indx * 4; | |
2302 | if (track->arrays[i].robj == NULL) { | |
2303 | DRM_ERROR("(PW %u) Vertex array %u no buffer " | |
2304 | "bound\n", prim_walk, i); | |
2305 | return -EINVAL; | |
2306 | } | |
2307 | if (size > radeon_bo_size(track->arrays[i].robj)) { | |
2308 | dev_err(rdev->dev, "(PW %u) Vertex array %u " | |
2309 | "need %lu dwords have %lu dwords\n", | |
2310 | prim_walk, i, size >> 2, | |
2311 | radeon_bo_size(track->arrays[i].robj) | |
2312 | >> 2); | |
2313 | DRM_ERROR("Max indices %u\n", track->max_indx); | |
2314 | return -EINVAL; | |
2315 | } | |
771fe6b9 | 2316 | } |
0242f74d AD |
2317 | break; |
2318 | case 2: | |
2319 | for (i = 0; i < track->num_arrays; i++) { | |
2320 | size = track->arrays[i].esize * (nverts - 1) * 4; | |
2321 | if (track->arrays[i].robj == NULL) { | |
2322 | DRM_ERROR("(PW %u) Vertex array %u no buffer " | |
2323 | "bound\n", prim_walk, i); | |
2324 | return -EINVAL; | |
2325 | } | |
2326 | if (size > radeon_bo_size(track->arrays[i].robj)) { | |
2327 | dev_err(rdev->dev, "(PW %u) Vertex array %u " | |
2328 | "need %lu dwords have %lu dwords\n", | |
2329 | prim_walk, i, size >> 2, | |
2330 | radeon_bo_size(track->arrays[i].robj) | |
2331 | >> 2); | |
2332 | return -EINVAL; | |
2333 | } | |
771fe6b9 | 2334 | } |
0242f74d AD |
2335 | break; |
2336 | case 3: | |
2337 | size = track->vtx_size * nverts; | |
2338 | if (size != track->immd_dwords) { | |
2339 | DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n", | |
2340 | track->immd_dwords, size); | |
2341 | DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n", | |
2342 | nverts, track->vtx_size); | |
2343 | return -EINVAL; | |
771fe6b9 | 2344 | } |
0242f74d AD |
2345 | break; |
2346 | default: | |
2347 | DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n", | |
2348 | prim_walk); | |
2349 | return -EINVAL; | |
2a0f8918 DA |
2350 | } |
2351 | ||
0242f74d AD |
2352 | if (track->tex_dirty) { |
2353 | track->tex_dirty = false; | |
2354 | return r100_cs_track_texture_check(rdev, track); | |
2a0f8918 | 2355 | } |
0242f74d | 2356 | return 0; |
2a0f8918 DA |
2357 | } |
2358 | ||
0242f74d | 2359 | void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track) |
2a0f8918 | 2360 | { |
0242f74d | 2361 | unsigned i, face; |
2a0f8918 | 2362 | |
0242f74d AD |
2363 | track->cb_dirty = true; |
2364 | track->zb_dirty = true; | |
2365 | track->tex_dirty = true; | |
2366 | track->aa_dirty = true; | |
b7d8cce5 | 2367 | |
0242f74d AD |
2368 | if (rdev->family < CHIP_R300) { |
2369 | track->num_cb = 1; | |
2370 | if (rdev->family <= CHIP_RS200) | |
2371 | track->num_texture = 3; | |
7a50f01a | 2372 | else |
0242f74d AD |
2373 | track->num_texture = 6; |
2374 | track->maxy = 2048; | |
2375 | track->separate_cube = 1; | |
28d52043 | 2376 | } else { |
0242f74d AD |
2377 | track->num_cb = 4; |
2378 | track->num_texture = 16; | |
2379 | track->maxy = 4096; | |
2380 | track->separate_cube = 0; | |
2381 | track->aaresolve = false; | |
2382 | track->aa.robj = NULL; | |
28d52043 | 2383 | } |
2a0f8918 | 2384 | |
0242f74d AD |
2385 | for (i = 0; i < track->num_cb; i++) { |
2386 | track->cb[i].robj = NULL; | |
2387 | track->cb[i].pitch = 8192; | |
2388 | track->cb[i].cpp = 16; | |
2389 | track->cb[i].offset = 0; | |
771fe6b9 | 2390 | } |
0242f74d AD |
2391 | track->z_enabled = true; |
2392 | track->zb.robj = NULL; | |
2393 | track->zb.pitch = 8192; | |
2394 | track->zb.cpp = 4; | |
2395 | track->zb.offset = 0; | |
2396 | track->vtx_size = 0x7F; | |
2397 | track->immd_dwords = 0xFFFFFFFFUL; | |
2398 | track->num_arrays = 11; | |
2399 | track->max_indx = 0x00FFFFFFUL; | |
2400 | for (i = 0; i < track->num_arrays; i++) { | |
2401 | track->arrays[i].robj = NULL; | |
2402 | track->arrays[i].esize = 0x7F; | |
771fe6b9 | 2403 | } |
0242f74d AD |
2404 | for (i = 0; i < track->num_texture; i++) { |
2405 | track->textures[i].compress_format = R100_TRACK_COMP_NONE; | |
2406 | track->textures[i].pitch = 16536; | |
2407 | track->textures[i].width = 16536; | |
2408 | track->textures[i].height = 16536; | |
2409 | track->textures[i].width_11 = 1 << 11; | |
2410 | track->textures[i].height_11 = 1 << 11; | |
2411 | track->textures[i].num_levels = 12; | |
2412 | if (rdev->family <= CHIP_RS200) { | |
2413 | track->textures[i].tex_coord_type = 0; | |
2414 | track->textures[i].txdepth = 0; | |
2415 | } else { | |
2416 | track->textures[i].txdepth = 16; | |
2417 | track->textures[i].tex_coord_type = 1; | |
2418 | } | |
2419 | track->textures[i].cpp = 64; | |
2420 | track->textures[i].robj = NULL; | |
2421 | /* CS IB emission code makes sure texture unit are disabled */ | |
2422 | track->textures[i].enabled = false; | |
2423 | track->textures[i].lookup_disable = false; | |
2424 | track->textures[i].roundup_w = true; | |
2425 | track->textures[i].roundup_h = true; | |
2426 | if (track->separate_cube) | |
2427 | for (face = 0; face < 5; face++) { | |
2428 | track->textures[i].cube_info[face].robj = NULL; | |
2429 | track->textures[i].cube_info[face].width = 16536; | |
2430 | track->textures[i].cube_info[face].height = 16536; | |
2431 | track->textures[i].cube_info[face].offset = 0; | |
2432 | } | |
771fe6b9 JG |
2433 | } |
2434 | } | |
2435 | ||
0242f74d AD |
2436 | /* |
2437 | * Global GPU functions | |
2438 | */ | |
1109ca09 | 2439 | static void r100_errata(struct radeon_device *rdev) |
771fe6b9 | 2440 | { |
0242f74d | 2441 | rdev->pll_errata = 0; |
771fe6b9 | 2442 | |
0242f74d AD |
2443 | if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) { |
2444 | rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS; | |
2445 | } | |
771fe6b9 | 2446 | |
0242f74d AD |
2447 | if (rdev->family == CHIP_RV100 || |
2448 | rdev->family == CHIP_RS100 || | |
2449 | rdev->family == CHIP_RS200) { | |
2450 | rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY; | |
2451 | } | |
771fe6b9 JG |
2452 | } |
2453 | ||
1109ca09 | 2454 | static int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n) |
771fe6b9 | 2455 | { |
0242f74d AD |
2456 | unsigned i; |
2457 | uint32_t tmp; | |
771fe6b9 | 2458 | |
0242f74d AD |
2459 | for (i = 0; i < rdev->usec_timeout; i++) { |
2460 | tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK; | |
2461 | if (tmp >= n) { | |
2462 | return 0; | |
2463 | } | |
2464 | DRM_UDELAY(1); | |
771fe6b9 | 2465 | } |
0242f74d | 2466 | return -1; |
771fe6b9 JG |
2467 | } |
2468 | ||
0242f74d | 2469 | int r100_gui_wait_for_idle(struct radeon_device *rdev) |
771fe6b9 | 2470 | { |
771fe6b9 | 2471 | unsigned i; |
0242f74d | 2472 | uint32_t tmp; |
771fe6b9 | 2473 | |
0242f74d AD |
2474 | if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) { |
2475 | printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !" | |
2476 | " Bad things might happen.\n"); | |
771fe6b9 | 2477 | } |
0242f74d AD |
2478 | for (i = 0; i < rdev->usec_timeout; i++) { |
2479 | tmp = RREG32(RADEON_RBBM_STATUS); | |
2480 | if (!(tmp & RADEON_RBBM_ACTIVE)) { | |
2481 | return 0; | |
2482 | } | |
2483 | DRM_UDELAY(1); | |
771fe6b9 | 2484 | } |
0242f74d | 2485 | return -1; |
771fe6b9 JG |
2486 | } |
2487 | ||
0242f74d | 2488 | int r100_mc_wait_for_idle(struct radeon_device *rdev) |
771fe6b9 | 2489 | { |
0242f74d | 2490 | unsigned i; |
771fe6b9 JG |
2491 | uint32_t tmp; |
2492 | ||
0242f74d AD |
2493 | for (i = 0; i < rdev->usec_timeout; i++) { |
2494 | /* read MC_STATUS */ | |
2495 | tmp = RREG32(RADEON_MC_STATUS); | |
2496 | if (tmp & RADEON_MC_IDLE) { | |
2497 | return 0; | |
2498 | } | |
2499 | DRM_UDELAY(1); | |
2500 | } | |
2501 | return -1; | |
771fe6b9 JG |
2502 | } |
2503 | ||
0242f74d | 2504 | bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) |
771fe6b9 | 2505 | { |
0242f74d | 2506 | u32 rbbm_status; |
771fe6b9 | 2507 | |
0242f74d AD |
2508 | rbbm_status = RREG32(R_000E40_RBBM_STATUS); |
2509 | if (!G_000E40_GUI_ACTIVE(rbbm_status)) { | |
ff212f25 | 2510 | radeon_ring_lockup_update(rdev, ring); |
0242f74d AD |
2511 | return false; |
2512 | } | |
0242f74d | 2513 | return radeon_ring_test_lockup(rdev, ring); |
771fe6b9 JG |
2514 | } |
2515 | ||
74da01dc AD |
2516 | /* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */ |
2517 | void r100_enable_bm(struct radeon_device *rdev) | |
2518 | { | |
2519 | uint32_t tmp; | |
2520 | /* Enable bus mastering */ | |
2521 | tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS; | |
2522 | WREG32(RADEON_BUS_CNTL, tmp); | |
2523 | } | |
2524 | ||
0242f74d | 2525 | void r100_bm_disable(struct radeon_device *rdev) |
771fe6b9 | 2526 | { |
0242f74d AD |
2527 | u32 tmp; |
2528 | ||
2529 | /* disable bus mastering */ | |
2530 | tmp = RREG32(R_000030_BUS_CNTL); | |
2531 | WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000044); | |
2532 | mdelay(1); | |
2533 | WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000042); | |
2534 | mdelay(1); | |
2535 | WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000040); | |
2536 | tmp = RREG32(RADEON_BUS_CNTL); | |
2537 | mdelay(1); | |
2538 | pci_clear_master(rdev->pdev); | |
2539 | mdelay(1); | |
771fe6b9 | 2540 | } |
e024e110 | 2541 | |
0242f74d | 2542 | int r100_asic_reset(struct radeon_device *rdev) |
e024e110 | 2543 | { |
0242f74d AD |
2544 | struct r100_mc_save save; |
2545 | u32 status, tmp; | |
2546 | int ret = 0; | |
e024e110 | 2547 | |
0242f74d AD |
2548 | status = RREG32(R_000E40_RBBM_STATUS); |
2549 | if (!G_000E40_GUI_ACTIVE(status)) { | |
2550 | return 0; | |
e024e110 | 2551 | } |
0242f74d AD |
2552 | r100_mc_stop(rdev, &save); |
2553 | status = RREG32(R_000E40_RBBM_STATUS); | |
2554 | dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); | |
2555 | /* stop CP */ | |
2556 | WREG32(RADEON_CP_CSQ_CNTL, 0); | |
2557 | tmp = RREG32(RADEON_CP_RB_CNTL); | |
2558 | WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA); | |
2559 | WREG32(RADEON_CP_RB_RPTR_WR, 0); | |
2560 | WREG32(RADEON_CP_RB_WPTR, 0); | |
2561 | WREG32(RADEON_CP_RB_CNTL, tmp); | |
2562 | /* save PCI state */ | |
2563 | pci_save_state(rdev->pdev); | |
2564 | /* disable bus mastering */ | |
2565 | r100_bm_disable(rdev); | |
2566 | WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_SE(1) | | |
2567 | S_0000F0_SOFT_RESET_RE(1) | | |
2568 | S_0000F0_SOFT_RESET_PP(1) | | |
2569 | S_0000F0_SOFT_RESET_RB(1)); | |
2570 | RREG32(R_0000F0_RBBM_SOFT_RESET); | |
2571 | mdelay(500); | |
2572 | WREG32(R_0000F0_RBBM_SOFT_RESET, 0); | |
2573 | mdelay(1); | |
2574 | status = RREG32(R_000E40_RBBM_STATUS); | |
2575 | dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); | |
2576 | /* reset CP */ | |
2577 | WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1)); | |
2578 | RREG32(R_0000F0_RBBM_SOFT_RESET); | |
2579 | mdelay(500); | |
2580 | WREG32(R_0000F0_RBBM_SOFT_RESET, 0); | |
2581 | mdelay(1); | |
2582 | status = RREG32(R_000E40_RBBM_STATUS); | |
2583 | dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); | |
2584 | /* restore PCI & busmastering */ | |
2585 | pci_restore_state(rdev->pdev); | |
2586 | r100_enable_bm(rdev); | |
2587 | /* Check if GPU is idle */ | |
2588 | if (G_000E40_SE_BUSY(status) || G_000E40_RE_BUSY(status) || | |
2589 | G_000E40_TAM_BUSY(status) || G_000E40_PB_BUSY(status)) { | |
2590 | dev_err(rdev->dev, "failed to reset GPU\n"); | |
2591 | ret = -1; | |
2592 | } else | |
2593 | dev_info(rdev->dev, "GPU reset succeed\n"); | |
2594 | r100_mc_resume(rdev, &save); | |
2595 | return ret; | |
2596 | } | |
e024e110 | 2597 | |
0242f74d AD |
2598 | void r100_set_common_regs(struct radeon_device *rdev) |
2599 | { | |
2600 | struct drm_device *dev = rdev->ddev; | |
2601 | bool force_dac2 = false; | |
2602 | u32 tmp; | |
f5c5f040 | 2603 | |
0242f74d AD |
2604 | /* set these so they don't interfere with anything */ |
2605 | WREG32(RADEON_OV0_SCALE_CNTL, 0); | |
2606 | WREG32(RADEON_SUBPIC_CNTL, 0); | |
2607 | WREG32(RADEON_VIPH_CONTROL, 0); | |
2608 | WREG32(RADEON_I2C_CNTL_1, 0); | |
2609 | WREG32(RADEON_DVI_I2C_CNTL_1, 0); | |
2610 | WREG32(RADEON_CAP0_TRIG_CNTL, 0); | |
2611 | WREG32(RADEON_CAP1_TRIG_CNTL, 0); | |
f5c5f040 | 2612 | |
0242f74d AD |
2613 | /* always set up dac2 on rn50 and some rv100 as lots |
2614 | * of servers seem to wire it up to a VGA port but | |
2615 | * don't report it in the bios connector | |
2616 | * table. | |
2617 | */ | |
2618 | switch (dev->pdev->device) { | |
2619 | /* RN50 */ | |
2620 | case 0x515e: | |
2621 | case 0x5969: | |
2622 | force_dac2 = true; | |
2623 | break; | |
2624 | /* RV100*/ | |
2625 | case 0x5159: | |
2626 | case 0x515a: | |
2627 | /* DELL triple head servers */ | |
2628 | if ((dev->pdev->subsystem_vendor == 0x1028 /* DELL */) && | |
2629 | ((dev->pdev->subsystem_device == 0x016c) || | |
2630 | (dev->pdev->subsystem_device == 0x016d) || | |
2631 | (dev->pdev->subsystem_device == 0x016e) || | |
2632 | (dev->pdev->subsystem_device == 0x016f) || | |
2633 | (dev->pdev->subsystem_device == 0x0170) || | |
2634 | (dev->pdev->subsystem_device == 0x017d) || | |
2635 | (dev->pdev->subsystem_device == 0x017e) || | |
2636 | (dev->pdev->subsystem_device == 0x0183) || | |
2637 | (dev->pdev->subsystem_device == 0x018a) || | |
2638 | (dev->pdev->subsystem_device == 0x019a))) | |
2639 | force_dac2 = true; | |
2640 | break; | |
2641 | } | |
f5c5f040 | 2642 | |
0242f74d AD |
2643 | if (force_dac2) { |
2644 | u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG); | |
2645 | u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); | |
2646 | u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2); | |
e024e110 | 2647 | |
0242f74d AD |
2648 | /* For CRT on DAC2, don't turn it on if BIOS didn't |
2649 | enable it, even it's detected. | |
2650 | */ | |
c93bb85b | 2651 | |
0242f74d AD |
2652 | /* force it to crtc0 */ |
2653 | dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL; | |
2654 | dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL; | |
2655 | disp_hw_debug |= RADEON_CRT2_DISP1_SEL; | |
c93bb85b | 2656 | |
0242f74d AD |
2657 | /* set up the TV DAC */ |
2658 | tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL | | |
2659 | RADEON_TV_DAC_STD_MASK | | |
2660 | RADEON_TV_DAC_RDACPD | | |
2661 | RADEON_TV_DAC_GDACPD | | |
2662 | RADEON_TV_DAC_BDACPD | | |
2663 | RADEON_TV_DAC_BGADJ_MASK | | |
2664 | RADEON_TV_DAC_DACADJ_MASK); | |
2665 | tv_dac_cntl |= (RADEON_TV_DAC_NBLANK | | |
2666 | RADEON_TV_DAC_NHOLD | | |
2667 | RADEON_TV_DAC_STD_PS2 | | |
2668 | (0x58 << 16)); | |
f46c0120 | 2669 | |
0242f74d AD |
2670 | WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); |
2671 | WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug); | |
2672 | WREG32(RADEON_DAC_CNTL2, dac2_cntl); | |
c93bb85b | 2673 | } |
0242f74d AD |
2674 | |
2675 | /* switch PM block to ACPI mode */ | |
2676 | tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL); | |
2677 | tmp &= ~RADEON_PM_MODE_SEL; | |
2678 | WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp); | |
2679 | ||
2680 | } | |
2681 | ||
2682 | /* | |
2683 | * VRAM info | |
2684 | */ | |
2685 | static void r100_vram_get_type(struct radeon_device *rdev) | |
2686 | { | |
2687 | uint32_t tmp; | |
2688 | ||
2689 | rdev->mc.vram_is_ddr = false; | |
2690 | if (rdev->flags & RADEON_IS_IGP) | |
2691 | rdev->mc.vram_is_ddr = true; | |
2692 | else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR) | |
2693 | rdev->mc.vram_is_ddr = true; | |
2694 | if ((rdev->family == CHIP_RV100) || | |
2695 | (rdev->family == CHIP_RS100) || | |
2696 | (rdev->family == CHIP_RS200)) { | |
2697 | tmp = RREG32(RADEON_MEM_CNTL); | |
2698 | if (tmp & RV100_HALF_MODE) { | |
2699 | rdev->mc.vram_width = 32; | |
2700 | } else { | |
2701 | rdev->mc.vram_width = 64; | |
2702 | } | |
2703 | if (rdev->flags & RADEON_SINGLE_CRTC) { | |
2704 | rdev->mc.vram_width /= 4; | |
2705 | rdev->mc.vram_is_ddr = true; | |
dfee5614 | 2706 | } |
0242f74d AD |
2707 | } else if (rdev->family <= CHIP_RV280) { |
2708 | tmp = RREG32(RADEON_MEM_CNTL); | |
2709 | if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) { | |
2710 | rdev->mc.vram_width = 128; | |
2711 | } else { | |
2712 | rdev->mc.vram_width = 64; | |
2713 | } | |
2714 | } else { | |
2715 | /* newer IGPs */ | |
2716 | rdev->mc.vram_width = 128; | |
c93bb85b | 2717 | } |
0242f74d | 2718 | } |
c93bb85b | 2719 | |
0242f74d AD |
2720 | static u32 r100_get_accessible_vram(struct radeon_device *rdev) |
2721 | { | |
2722 | u32 aper_size; | |
2723 | u8 byte; | |
2724 | ||
2725 | aper_size = RREG32(RADEON_CONFIG_APER_SIZE); | |
2726 | ||
2727 | /* Set HDP_APER_CNTL only on cards that are known not to be broken, | |
2728 | * that is has the 2nd generation multifunction PCI interface | |
2729 | */ | |
2730 | if (rdev->family == CHIP_RV280 || | |
2731 | rdev->family >= CHIP_RV350) { | |
2732 | WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL, | |
2733 | ~RADEON_HDP_APER_CNTL); | |
2734 | DRM_INFO("Generation 2 PCI interface, using max accessible memory\n"); | |
2735 | return aper_size * 2; | |
c93bb85b JG |
2736 | } |
2737 | ||
0242f74d AD |
2738 | /* Older cards have all sorts of funny issues to deal with. First |
2739 | * check if it's a multifunction card by reading the PCI config | |
2740 | * header type... Limit those to one aperture size | |
c93bb85b | 2741 | */ |
0242f74d AD |
2742 | pci_read_config_byte(rdev->pdev, 0xe, &byte); |
2743 | if (byte & 0x80) { | |
2744 | DRM_INFO("Generation 1 PCI interface in multifunction mode\n"); | |
2745 | DRM_INFO("Limiting VRAM to one aperture\n"); | |
2746 | return aper_size; | |
2747 | } | |
c93bb85b | 2748 | |
0242f74d AD |
2749 | /* Single function older card. We read HDP_APER_CNTL to see how the BIOS |
2750 | * have set it up. We don't write this as it's broken on some ASICs but | |
2751 | * we expect the BIOS to have done the right thing (might be too optimistic...) | |
2752 | */ | |
2753 | if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL) | |
2754 | return aper_size * 2; | |
2755 | return aper_size; | |
2756 | } | |
c93bb85b | 2757 | |
0242f74d AD |
2758 | void r100_vram_init_sizes(struct radeon_device *rdev) |
2759 | { | |
2760 | u64 config_aper_size; | |
c93bb85b | 2761 | |
0242f74d AD |
2762 | /* work out accessible VRAM */ |
2763 | rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); | |
2764 | rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); | |
2765 | rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev); | |
2766 | /* FIXME we don't use the second aperture yet when we could use it */ | |
2767 | if (rdev->mc.visible_vram_size > rdev->mc.aper_size) | |
2768 | rdev->mc.visible_vram_size = rdev->mc.aper_size; | |
2769 | config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE); | |
2770 | if (rdev->flags & RADEON_IS_IGP) { | |
2771 | uint32_t tom; | |
2772 | /* read NB_TOM to get the amount of ram stolen for the GPU */ | |
2773 | tom = RREG32(RADEON_NB_TOM); | |
2774 | rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16); | |
2775 | WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size); | |
2776 | rdev->mc.mc_vram_size = rdev->mc.real_vram_size; | |
2777 | } else { | |
2778 | rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); | |
2779 | /* Some production boards of m6 will report 0 | |
2780 | * if it's 8 MB | |
2781 | */ | |
2782 | if (rdev->mc.real_vram_size == 0) { | |
2783 | rdev->mc.real_vram_size = 8192 * 1024; | |
2784 | WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size); | |
2785 | } | |
2786 | /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM - | |
2787 | * Novell bug 204882 + along with lots of ubuntu ones | |
2788 | */ | |
2789 | if (rdev->mc.aper_size > config_aper_size) | |
2790 | config_aper_size = rdev->mc.aper_size; | |
2791 | ||
2792 | if (config_aper_size > rdev->mc.real_vram_size) | |
2793 | rdev->mc.mc_vram_size = config_aper_size; | |
2794 | else | |
2795 | rdev->mc.mc_vram_size = rdev->mc.real_vram_size; | |
c93bb85b | 2796 | } |
0242f74d | 2797 | } |
c93bb85b | 2798 | |
0242f74d AD |
2799 | void r100_vga_set_state(struct radeon_device *rdev, bool state) |
2800 | { | |
2801 | uint32_t temp; | |
2802 | ||
2803 | temp = RREG32(RADEON_CONFIG_CNTL); | |
2804 | if (state == false) { | |
2805 | temp &= ~RADEON_CFG_VGA_RAM_EN; | |
2806 | temp |= RADEON_CFG_VGA_IO_DIS; | |
2807 | } else { | |
2808 | temp &= ~RADEON_CFG_VGA_IO_DIS; | |
c93bb85b | 2809 | } |
0242f74d AD |
2810 | WREG32(RADEON_CONFIG_CNTL, temp); |
2811 | } | |
c93bb85b | 2812 | |
1109ca09 | 2813 | static void r100_mc_init(struct radeon_device *rdev) |
0242f74d AD |
2814 | { |
2815 | u64 base; | |
c93bb85b | 2816 | |
0242f74d AD |
2817 | r100_vram_get_type(rdev); |
2818 | r100_vram_init_sizes(rdev); | |
2819 | base = rdev->mc.aper_base; | |
2820 | if (rdev->flags & RADEON_IS_IGP) | |
2821 | base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16; | |
2822 | radeon_vram_location(rdev, &rdev->mc, base); | |
2823 | rdev->mc.gtt_base_align = 0; | |
2824 | if (!(rdev->flags & RADEON_IS_AGP)) | |
2825 | radeon_gtt_location(rdev, &rdev->mc); | |
2826 | radeon_update_bandwidth_info(rdev); | |
2827 | } | |
2828 | ||
2829 | ||
2830 | /* | |
2831 | * Indirect registers accessor | |
2832 | */ | |
2833 | void r100_pll_errata_after_index(struct radeon_device *rdev) | |
2834 | { | |
2835 | if (rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS) { | |
2836 | (void)RREG32(RADEON_CLOCK_CNTL_DATA); | |
2837 | (void)RREG32(RADEON_CRTC_GEN_CNTL); | |
c93bb85b | 2838 | } |
0242f74d | 2839 | } |
c93bb85b | 2840 | |
0242f74d AD |
2841 | static void r100_pll_errata_after_data(struct radeon_device *rdev) |
2842 | { | |
2843 | /* This workarounds is necessary on RV100, RS100 and RS200 chips | |
2844 | * or the chip could hang on a subsequent access | |
2845 | */ | |
2846 | if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) { | |
2847 | mdelay(5); | |
c93bb85b JG |
2848 | } |
2849 | ||
0242f74d AD |
2850 | /* This function is required to workaround a hardware bug in some (all?) |
2851 | * revisions of the R300. This workaround should be called after every | |
2852 | * CLOCK_CNTL_INDEX register access. If not, register reads afterward | |
2853 | * may not be correct. | |
2854 | */ | |
2855 | if (rdev->pll_errata & CHIP_ERRATA_R300_CG) { | |
2856 | uint32_t save, tmp; | |
c93bb85b | 2857 | |
0242f74d AD |
2858 | save = RREG32(RADEON_CLOCK_CNTL_INDEX); |
2859 | tmp = save & ~(0x3f | RADEON_PLL_WR_EN); | |
2860 | WREG32(RADEON_CLOCK_CNTL_INDEX, tmp); | |
2861 | tmp = RREG32(RADEON_CLOCK_CNTL_DATA); | |
2862 | WREG32(RADEON_CLOCK_CNTL_INDEX, save); | |
c93bb85b | 2863 | } |
0242f74d | 2864 | } |
c93bb85b | 2865 | |
0242f74d AD |
2866 | uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg) |
2867 | { | |
0a5b7b0b | 2868 | unsigned long flags; |
0242f74d | 2869 | uint32_t data; |
c93bb85b | 2870 | |
0a5b7b0b | 2871 | spin_lock_irqsave(&rdev->pll_idx_lock, flags); |
0242f74d AD |
2872 | WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f); |
2873 | r100_pll_errata_after_index(rdev); | |
2874 | data = RREG32(RADEON_CLOCK_CNTL_DATA); | |
2875 | r100_pll_errata_after_data(rdev); | |
0a5b7b0b | 2876 | spin_unlock_irqrestore(&rdev->pll_idx_lock, flags); |
0242f74d AD |
2877 | return data; |
2878 | } | |
c93bb85b | 2879 | |
0242f74d AD |
2880 | void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
2881 | { | |
0a5b7b0b AD |
2882 | unsigned long flags; |
2883 | ||
2884 | spin_lock_irqsave(&rdev->pll_idx_lock, flags); | |
0242f74d AD |
2885 | WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN)); |
2886 | r100_pll_errata_after_index(rdev); | |
2887 | WREG32(RADEON_CLOCK_CNTL_DATA, v); | |
2888 | r100_pll_errata_after_data(rdev); | |
0a5b7b0b | 2889 | spin_unlock_irqrestore(&rdev->pll_idx_lock, flags); |
0242f74d AD |
2890 | } |
2891 | ||
1109ca09 | 2892 | static void r100_set_safe_registers(struct radeon_device *rdev) |
0242f74d AD |
2893 | { |
2894 | if (ASIC_IS_RN50(rdev)) { | |
2895 | rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm; | |
2896 | rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm); | |
2897 | } else if (rdev->family < CHIP_R200) { | |
2898 | rdev->config.r100.reg_safe_bm = r100_reg_safe_bm; | |
2899 | rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm); | |
c93bb85b | 2900 | } else { |
0242f74d | 2901 | r200_set_safe_registers(rdev); |
c93bb85b | 2902 | } |
0242f74d | 2903 | } |
c93bb85b | 2904 | |
0242f74d AD |
2905 | /* |
2906 | * Debugfs info | |
2907 | */ | |
2908 | #if defined(CONFIG_DEBUG_FS) | |
2909 | static int r100_debugfs_rbbm_info(struct seq_file *m, void *data) | |
2910 | { | |
2911 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
2912 | struct drm_device *dev = node->minor->dev; | |
2913 | struct radeon_device *rdev = dev->dev_private; | |
2914 | uint32_t reg, value; | |
2915 | unsigned i; | |
c93bb85b | 2916 | |
0242f74d AD |
2917 | seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS)); |
2918 | seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C)); | |
2919 | seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT)); | |
2920 | for (i = 0; i < 64; i++) { | |
2921 | WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100); | |
2922 | reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2; | |
2923 | WREG32(RADEON_RBBM_CMDFIFO_ADDR, i); | |
2924 | value = RREG32(RADEON_RBBM_CMDFIFO_DATA); | |
2925 | seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value); | |
2926 | } | |
2927 | return 0; | |
2928 | } | |
c93bb85b | 2929 | |
0242f74d AD |
2930 | static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data) |
2931 | { | |
2932 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
2933 | struct drm_device *dev = node->minor->dev; | |
2934 | struct radeon_device *rdev = dev->dev_private; | |
2935 | struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; | |
2936 | uint32_t rdp, wdp; | |
2937 | unsigned count, i, j; | |
c93bb85b | 2938 | |
0242f74d AD |
2939 | radeon_ring_free_size(rdev, ring); |
2940 | rdp = RREG32(RADEON_CP_RB_RPTR); | |
2941 | wdp = RREG32(RADEON_CP_RB_WPTR); | |
2942 | count = (rdp + ring->ring_size - wdp) & ring->ptr_mask; | |
2943 | seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT)); | |
2944 | seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp); | |
2945 | seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp); | |
2946 | seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw); | |
2947 | seq_printf(m, "%u dwords in ring\n", count); | |
0eb3448a AI |
2948 | if (ring->ready) { |
2949 | for (j = 0; j <= count; j++) { | |
2950 | i = (rdp + j) & ring->ptr_mask; | |
2951 | seq_printf(m, "r[%04d]=0x%08x\n", i, ring->ring[i]); | |
2952 | } | |
0242f74d AD |
2953 | } |
2954 | return 0; | |
2955 | } | |
c93bb85b | 2956 | |
c93bb85b | 2957 | |
0242f74d AD |
2958 | static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data) |
2959 | { | |
2960 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
2961 | struct drm_device *dev = node->minor->dev; | |
2962 | struct radeon_device *rdev = dev->dev_private; | |
2963 | uint32_t csq_stat, csq2_stat, tmp; | |
2964 | unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr; | |
2965 | unsigned i; | |
c93bb85b | 2966 | |
0242f74d AD |
2967 | seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT)); |
2968 | seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE)); | |
2969 | csq_stat = RREG32(RADEON_CP_CSQ_STAT); | |
2970 | csq2_stat = RREG32(RADEON_CP_CSQ2_STAT); | |
2971 | r_rptr = (csq_stat >> 0) & 0x3ff; | |
2972 | r_wptr = (csq_stat >> 10) & 0x3ff; | |
2973 | ib1_rptr = (csq_stat >> 20) & 0x3ff; | |
2974 | ib1_wptr = (csq2_stat >> 0) & 0x3ff; | |
2975 | ib2_rptr = (csq2_stat >> 10) & 0x3ff; | |
2976 | ib2_wptr = (csq2_stat >> 20) & 0x3ff; | |
2977 | seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat); | |
2978 | seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat); | |
2979 | seq_printf(m, "Ring rptr %u\n", r_rptr); | |
2980 | seq_printf(m, "Ring wptr %u\n", r_wptr); | |
2981 | seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr); | |
2982 | seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr); | |
2983 | seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr); | |
2984 | seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr); | |
2985 | /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms | |
2986 | * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */ | |
2987 | seq_printf(m, "Ring fifo:\n"); | |
2988 | for (i = 0; i < 256; i++) { | |
2989 | WREG32(RADEON_CP_CSQ_ADDR, i << 2); | |
2990 | tmp = RREG32(RADEON_CP_CSQ_DATA); | |
2991 | seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp); | |
2992 | } | |
2993 | seq_printf(m, "Indirect1 fifo:\n"); | |
2994 | for (i = 256; i <= 512; i++) { | |
2995 | WREG32(RADEON_CP_CSQ_ADDR, i << 2); | |
2996 | tmp = RREG32(RADEON_CP_CSQ_DATA); | |
2997 | seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp); | |
2998 | } | |
2999 | seq_printf(m, "Indirect2 fifo:\n"); | |
3000 | for (i = 640; i < ib1_wptr; i++) { | |
3001 | WREG32(RADEON_CP_CSQ_ADDR, i << 2); | |
3002 | tmp = RREG32(RADEON_CP_CSQ_DATA); | |
3003 | seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp); | |
3004 | } | |
3005 | return 0; | |
3006 | } | |
3007 | ||
3008 | static int r100_debugfs_mc_info(struct seq_file *m, void *data) | |
3009 | { | |
3010 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
3011 | struct drm_device *dev = node->minor->dev; | |
3012 | struct radeon_device *rdev = dev->dev_private; | |
3013 | uint32_t tmp; | |
c93bb85b | 3014 | |
0242f74d AD |
3015 | tmp = RREG32(RADEON_CONFIG_MEMSIZE); |
3016 | seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp); | |
3017 | tmp = RREG32(RADEON_MC_FB_LOCATION); | |
3018 | seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp); | |
3019 | tmp = RREG32(RADEON_BUS_CNTL); | |
3020 | seq_printf(m, "BUS_CNTL 0x%08x\n", tmp); | |
3021 | tmp = RREG32(RADEON_MC_AGP_LOCATION); | |
3022 | seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp); | |
3023 | tmp = RREG32(RADEON_AGP_BASE); | |
3024 | seq_printf(m, "AGP_BASE 0x%08x\n", tmp); | |
3025 | tmp = RREG32(RADEON_HOST_PATH_CNTL); | |
3026 | seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp); | |
3027 | tmp = RREG32(0x01D0); | |
3028 | seq_printf(m, "AIC_CTRL 0x%08x\n", tmp); | |
3029 | tmp = RREG32(RADEON_AIC_LO_ADDR); | |
3030 | seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp); | |
3031 | tmp = RREG32(RADEON_AIC_HI_ADDR); | |
3032 | seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp); | |
3033 | tmp = RREG32(0x01E4); | |
3034 | seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp); | |
3035 | return 0; | |
3036 | } | |
c93bb85b | 3037 | |
0242f74d AD |
3038 | static struct drm_info_list r100_debugfs_rbbm_list[] = { |
3039 | {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL}, | |
3040 | }; | |
c93bb85b | 3041 | |
0242f74d AD |
3042 | static struct drm_info_list r100_debugfs_cp_list[] = { |
3043 | {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL}, | |
3044 | {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL}, | |
3045 | }; | |
c93bb85b | 3046 | |
0242f74d AD |
3047 | static struct drm_info_list r100_debugfs_mc_info_list[] = { |
3048 | {"r100_mc_info", r100_debugfs_mc_info, 0, NULL}, | |
3049 | }; | |
3050 | #endif | |
c93bb85b | 3051 | |
0242f74d AD |
3052 | int r100_debugfs_rbbm_init(struct radeon_device *rdev) |
3053 | { | |
3054 | #if defined(CONFIG_DEBUG_FS) | |
3055 | return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1); | |
3056 | #else | |
3057 | return 0; | |
3058 | #endif | |
3059 | } | |
c93bb85b | 3060 | |
0242f74d AD |
3061 | int r100_debugfs_cp_init(struct radeon_device *rdev) |
3062 | { | |
3063 | #if defined(CONFIG_DEBUG_FS) | |
3064 | return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2); | |
3065 | #else | |
3066 | return 0; | |
3067 | #endif | |
3068 | } | |
c93bb85b | 3069 | |
0242f74d AD |
3070 | int r100_debugfs_mc_info_init(struct radeon_device *rdev) |
3071 | { | |
3072 | #if defined(CONFIG_DEBUG_FS) | |
3073 | return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1); | |
3074 | #else | |
3075 | return 0; | |
3076 | #endif | |
3077 | } | |
c93bb85b | 3078 | |
0242f74d AD |
3079 | int r100_set_surface_reg(struct radeon_device *rdev, int reg, |
3080 | uint32_t tiling_flags, uint32_t pitch, | |
3081 | uint32_t offset, uint32_t obj_size) | |
3082 | { | |
3083 | int surf_index = reg * 16; | |
3084 | int flags = 0; | |
c93bb85b | 3085 | |
0242f74d AD |
3086 | if (rdev->family <= CHIP_RS200) { |
3087 | if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO)) | |
3088 | == (RADEON_TILING_MACRO|RADEON_TILING_MICRO)) | |
3089 | flags |= RADEON_SURF_TILE_COLOR_BOTH; | |
3090 | if (tiling_flags & RADEON_TILING_MACRO) | |
3091 | flags |= RADEON_SURF_TILE_COLOR_MACRO; | |
67d5ced5 AD |
3092 | /* setting pitch to 0 disables tiling */ |
3093 | if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO)) | |
3094 | == 0) | |
3095 | pitch = 0; | |
0242f74d AD |
3096 | } else if (rdev->family <= CHIP_RV280) { |
3097 | if (tiling_flags & (RADEON_TILING_MACRO)) | |
3098 | flags |= R200_SURF_TILE_COLOR_MACRO; | |
3099 | if (tiling_flags & RADEON_TILING_MICRO) | |
3100 | flags |= R200_SURF_TILE_COLOR_MICRO; | |
3101 | } else { | |
3102 | if (tiling_flags & RADEON_TILING_MACRO) | |
3103 | flags |= R300_SURF_TILE_MACRO; | |
3104 | if (tiling_flags & RADEON_TILING_MICRO) | |
3105 | flags |= R300_SURF_TILE_MICRO; | |
3106 | } | |
c93bb85b | 3107 | |
0242f74d AD |
3108 | if (tiling_flags & RADEON_TILING_SWAP_16BIT) |
3109 | flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP; | |
3110 | if (tiling_flags & RADEON_TILING_SWAP_32BIT) | |
3111 | flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP; | |
3112 | ||
0242f74d AD |
3113 | /* r100/r200 divide by 16 */ |
3114 | if (rdev->family < CHIP_R300) | |
3115 | flags |= pitch / 16; | |
3116 | else | |
3117 | flags |= pitch / 8; | |
c93bb85b | 3118 | |
c93bb85b | 3119 | |
0242f74d AD |
3120 | DRM_DEBUG_KMS("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1); |
3121 | WREG32(RADEON_SURFACE0_INFO + surf_index, flags); | |
3122 | WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset); | |
3123 | WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1); | |
3124 | return 0; | |
3125 | } | |
c93bb85b | 3126 | |
0242f74d AD |
3127 | void r100_clear_surface_reg(struct radeon_device *rdev, int reg) |
3128 | { | |
3129 | int surf_index = reg * 16; | |
3130 | WREG32(RADEON_SURFACE0_INFO + surf_index, 0); | |
3131 | } | |
c93bb85b | 3132 | |
0242f74d AD |
3133 | void r100_bandwidth_update(struct radeon_device *rdev) |
3134 | { | |
3135 | fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff; | |
3136 | fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff; | |
3137 | fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff; | |
3138 | uint32_t temp, data, mem_trcd, mem_trp, mem_tras; | |
3139 | fixed20_12 memtcas_ff[8] = { | |
3140 | dfixed_init(1), | |
3141 | dfixed_init(2), | |
3142 | dfixed_init(3), | |
3143 | dfixed_init(0), | |
3144 | dfixed_init_half(1), | |
3145 | dfixed_init_half(2), | |
3146 | dfixed_init(0), | |
3147 | }; | |
3148 | fixed20_12 memtcas_rs480_ff[8] = { | |
3149 | dfixed_init(0), | |
3150 | dfixed_init(1), | |
3151 | dfixed_init(2), | |
3152 | dfixed_init(3), | |
3153 | dfixed_init(0), | |
3154 | dfixed_init_half(1), | |
3155 | dfixed_init_half(2), | |
3156 | dfixed_init_half(3), | |
3157 | }; | |
3158 | fixed20_12 memtcas2_ff[8] = { | |
3159 | dfixed_init(0), | |
3160 | dfixed_init(1), | |
3161 | dfixed_init(2), | |
3162 | dfixed_init(3), | |
3163 | dfixed_init(4), | |
3164 | dfixed_init(5), | |
3165 | dfixed_init(6), | |
3166 | dfixed_init(7), | |
3167 | }; | |
3168 | fixed20_12 memtrbs[8] = { | |
3169 | dfixed_init(1), | |
3170 | dfixed_init_half(1), | |
3171 | dfixed_init(2), | |
3172 | dfixed_init_half(2), | |
3173 | dfixed_init(3), | |
3174 | dfixed_init_half(3), | |
3175 | dfixed_init(4), | |
3176 | dfixed_init_half(4) | |
3177 | }; | |
3178 | fixed20_12 memtrbs_r4xx[8] = { | |
3179 | dfixed_init(4), | |
3180 | dfixed_init(5), | |
3181 | dfixed_init(6), | |
3182 | dfixed_init(7), | |
3183 | dfixed_init(8), | |
3184 | dfixed_init(9), | |
3185 | dfixed_init(10), | |
3186 | dfixed_init(11) | |
3187 | }; | |
3188 | fixed20_12 min_mem_eff; | |
3189 | fixed20_12 mc_latency_sclk, mc_latency_mclk, k1; | |
3190 | fixed20_12 cur_latency_mclk, cur_latency_sclk; | |
3191 | fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate, | |
3192 | disp_drain_rate2, read_return_rate; | |
3193 | fixed20_12 time_disp1_drop_priority; | |
3194 | int c; | |
3195 | int cur_size = 16; /* in octawords */ | |
3196 | int critical_point = 0, critical_point2; | |
3197 | /* uint32_t read_return_rate, time_disp1_drop_priority; */ | |
3198 | int stop_req, max_stop_req; | |
3199 | struct drm_display_mode *mode1 = NULL; | |
3200 | struct drm_display_mode *mode2 = NULL; | |
3201 | uint32_t pixel_bytes1 = 0; | |
3202 | uint32_t pixel_bytes2 = 0; | |
c93bb85b | 3203 | |
0242f74d | 3204 | radeon_update_display_priority(rdev); |
c93bb85b | 3205 | |
0242f74d AD |
3206 | if (rdev->mode_info.crtcs[0]->base.enabled) { |
3207 | mode1 = &rdev->mode_info.crtcs[0]->base.mode; | |
f4510a27 | 3208 | pixel_bytes1 = rdev->mode_info.crtcs[0]->base.primary->fb->bits_per_pixel / 8; |
0242f74d AD |
3209 | } |
3210 | if (!(rdev->flags & RADEON_SINGLE_CRTC)) { | |
3211 | if (rdev->mode_info.crtcs[1]->base.enabled) { | |
3212 | mode2 = &rdev->mode_info.crtcs[1]->base.mode; | |
f4510a27 | 3213 | pixel_bytes2 = rdev->mode_info.crtcs[1]->base.primary->fb->bits_per_pixel / 8; |
0242f74d AD |
3214 | } |
3215 | } | |
c93bb85b | 3216 | |
0242f74d AD |
3217 | min_mem_eff.full = dfixed_const_8(0); |
3218 | /* get modes */ | |
3219 | if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) { | |
3220 | uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER); | |
3221 | mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT); | |
3222 | mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT); | |
3223 | /* check crtc enables */ | |
3224 | if (mode2) | |
3225 | mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT); | |
3226 | if (mode1) | |
3227 | mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT); | |
3228 | WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer); | |
3229 | } | |
c93bb85b | 3230 | |
0242f74d AD |
3231 | /* |
3232 | * determine is there is enough bw for current mode | |
3233 | */ | |
3234 | sclk_ff = rdev->pm.sclk; | |
3235 | mclk_ff = rdev->pm.mclk; | |
c93bb85b | 3236 | |
0242f74d AD |
3237 | temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1); |
3238 | temp_ff.full = dfixed_const(temp); | |
3239 | mem_bw.full = dfixed_mul(mclk_ff, temp_ff); | |
c93bb85b | 3240 | |
0242f74d AD |
3241 | pix_clk.full = 0; |
3242 | pix_clk2.full = 0; | |
3243 | peak_disp_bw.full = 0; | |
3244 | if (mode1) { | |
3245 | temp_ff.full = dfixed_const(1000); | |
3246 | pix_clk.full = dfixed_const(mode1->clock); /* convert to fixed point */ | |
3247 | pix_clk.full = dfixed_div(pix_clk, temp_ff); | |
3248 | temp_ff.full = dfixed_const(pixel_bytes1); | |
3249 | peak_disp_bw.full += dfixed_mul(pix_clk, temp_ff); | |
3250 | } | |
3251 | if (mode2) { | |
3252 | temp_ff.full = dfixed_const(1000); | |
3253 | pix_clk2.full = dfixed_const(mode2->clock); /* convert to fixed point */ | |
3254 | pix_clk2.full = dfixed_div(pix_clk2, temp_ff); | |
3255 | temp_ff.full = dfixed_const(pixel_bytes2); | |
3256 | peak_disp_bw.full += dfixed_mul(pix_clk2, temp_ff); | |
3257 | } | |
c93bb85b | 3258 | |
0242f74d AD |
3259 | mem_bw.full = dfixed_mul(mem_bw, min_mem_eff); |
3260 | if (peak_disp_bw.full >= mem_bw.full) { | |
3261 | DRM_ERROR("You may not have enough display bandwidth for current mode\n" | |
3262 | "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n"); | |
3263 | } | |
c93bb85b | 3264 | |
0242f74d AD |
3265 | /* Get values from the EXT_MEM_CNTL register...converting its contents. */ |
3266 | temp = RREG32(RADEON_MEM_TIMING_CNTL); | |
3267 | if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */ | |
3268 | mem_trcd = ((temp >> 2) & 0x3) + 1; | |
3269 | mem_trp = ((temp & 0x3)) + 1; | |
3270 | mem_tras = ((temp & 0x70) >> 4) + 1; | |
3271 | } else if (rdev->family == CHIP_R300 || | |
3272 | rdev->family == CHIP_R350) { /* r300, r350 */ | |
3273 | mem_trcd = (temp & 0x7) + 1; | |
3274 | mem_trp = ((temp >> 8) & 0x7) + 1; | |
3275 | mem_tras = ((temp >> 11) & 0xf) + 4; | |
3276 | } else if (rdev->family == CHIP_RV350 || | |
3277 | rdev->family <= CHIP_RV380) { | |
3278 | /* rv3x0 */ | |
3279 | mem_trcd = (temp & 0x7) + 3; | |
3280 | mem_trp = ((temp >> 8) & 0x7) + 3; | |
3281 | mem_tras = ((temp >> 11) & 0xf) + 6; | |
3282 | } else if (rdev->family == CHIP_R420 || | |
3283 | rdev->family == CHIP_R423 || | |
3284 | rdev->family == CHIP_RV410) { | |
3285 | /* r4xx */ | |
3286 | mem_trcd = (temp & 0xf) + 3; | |
3287 | if (mem_trcd > 15) | |
3288 | mem_trcd = 15; | |
3289 | mem_trp = ((temp >> 8) & 0xf) + 3; | |
3290 | if (mem_trp > 15) | |
3291 | mem_trp = 15; | |
3292 | mem_tras = ((temp >> 12) & 0x1f) + 6; | |
3293 | if (mem_tras > 31) | |
3294 | mem_tras = 31; | |
3295 | } else { /* RV200, R200 */ | |
3296 | mem_trcd = (temp & 0x7) + 1; | |
3297 | mem_trp = ((temp >> 8) & 0x7) + 1; | |
3298 | mem_tras = ((temp >> 12) & 0xf) + 4; | |
3299 | } | |
3300 | /* convert to FF */ | |
3301 | trcd_ff.full = dfixed_const(mem_trcd); | |
3302 | trp_ff.full = dfixed_const(mem_trp); | |
3303 | tras_ff.full = dfixed_const(mem_tras); | |
c93bb85b | 3304 | |
0242f74d AD |
3305 | /* Get values from the MEM_SDRAM_MODE_REG register...converting its */ |
3306 | temp = RREG32(RADEON_MEM_SDRAM_MODE_REG); | |
3307 | data = (temp & (7 << 20)) >> 20; | |
3308 | if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) { | |
3309 | if (rdev->family == CHIP_RS480) /* don't think rs400 */ | |
3310 | tcas_ff = memtcas_rs480_ff[data]; | |
3311 | else | |
3312 | tcas_ff = memtcas_ff[data]; | |
3313 | } else | |
3314 | tcas_ff = memtcas2_ff[data]; | |
c93bb85b | 3315 | |
0242f74d AD |
3316 | if (rdev->family == CHIP_RS400 || |
3317 | rdev->family == CHIP_RS480) { | |
3318 | /* extra cas latency stored in bits 23-25 0-4 clocks */ | |
3319 | data = (temp >> 23) & 0x7; | |
3320 | if (data < 5) | |
3321 | tcas_ff.full += dfixed_const(data); | |
c93bb85b | 3322 | } |
551ebd83 | 3323 | |
0242f74d AD |
3324 | if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) { |
3325 | /* on the R300, Tcas is included in Trbs. | |
3326 | */ | |
3327 | temp = RREG32(RADEON_MEM_CNTL); | |
3328 | data = (R300_MEM_NUM_CHANNELS_MASK & temp); | |
3329 | if (data == 1) { | |
3330 | if (R300_MEM_USE_CD_CH_ONLY & temp) { | |
3331 | temp = RREG32(R300_MC_IND_INDEX); | |
3332 | temp &= ~R300_MC_IND_ADDR_MASK; | |
3333 | temp |= R300_MC_READ_CNTL_CD_mcind; | |
3334 | WREG32(R300_MC_IND_INDEX, temp); | |
3335 | temp = RREG32(R300_MC_IND_DATA); | |
3336 | data = (R300_MEM_RBS_POSITION_C_MASK & temp); | |
3337 | } else { | |
3338 | temp = RREG32(R300_MC_READ_CNTL_AB); | |
3339 | data = (R300_MEM_RBS_POSITION_A_MASK & temp); | |
3340 | } | |
3341 | } else { | |
3342 | temp = RREG32(R300_MC_READ_CNTL_AB); | |
3343 | data = (R300_MEM_RBS_POSITION_A_MASK & temp); | |
3344 | } | |
3345 | if (rdev->family == CHIP_RV410 || | |
3346 | rdev->family == CHIP_R420 || | |
3347 | rdev->family == CHIP_R423) | |
3348 | trbs_ff = memtrbs_r4xx[data]; | |
3349 | else | |
3350 | trbs_ff = memtrbs[data]; | |
3351 | tcas_ff.full += trbs_ff.full; | |
3352 | } | |
551ebd83 | 3353 | |
0242f74d | 3354 | sclk_eff_ff.full = sclk_ff.full; |
d785d78b | 3355 | |
0242f74d AD |
3356 | if (rdev->flags & RADEON_IS_AGP) { |
3357 | fixed20_12 agpmode_ff; | |
3358 | agpmode_ff.full = dfixed_const(radeon_agpmode); | |
3359 | temp_ff.full = dfixed_const_666(16); | |
3360 | sclk_eff_ff.full -= dfixed_mul(agpmode_ff, temp_ff); | |
3361 | } | |
3362 | /* TODO PCIE lanes may affect this - agpmode == 16?? */ | |
d785d78b | 3363 | |
0242f74d AD |
3364 | if (ASIC_IS_R300(rdev)) { |
3365 | sclk_delay_ff.full = dfixed_const(250); | |
3366 | } else { | |
3367 | if ((rdev->family == CHIP_RV100) || | |
3368 | rdev->flags & RADEON_IS_IGP) { | |
3369 | if (rdev->mc.vram_is_ddr) | |
3370 | sclk_delay_ff.full = dfixed_const(41); | |
3371 | else | |
3372 | sclk_delay_ff.full = dfixed_const(33); | |
3373 | } else { | |
3374 | if (rdev->mc.vram_width == 128) | |
3375 | sclk_delay_ff.full = dfixed_const(57); | |
3376 | else | |
3377 | sclk_delay_ff.full = dfixed_const(41); | |
3378 | } | |
d785d78b DA |
3379 | } |
3380 | ||
0242f74d | 3381 | mc_latency_sclk.full = dfixed_div(sclk_delay_ff, sclk_eff_ff); |
d785d78b | 3382 | |
0242f74d AD |
3383 | if (rdev->mc.vram_is_ddr) { |
3384 | if (rdev->mc.vram_width == 32) { | |
3385 | k1.full = dfixed_const(40); | |
3386 | c = 3; | |
3387 | } else { | |
3388 | k1.full = dfixed_const(20); | |
3389 | c = 1; | |
3390 | } | |
3391 | } else { | |
3392 | k1.full = dfixed_const(40); | |
3393 | c = 3; | |
3394 | } | |
37cf6b03 | 3395 | |
0242f74d AD |
3396 | temp_ff.full = dfixed_const(2); |
3397 | mc_latency_mclk.full = dfixed_mul(trcd_ff, temp_ff); | |
3398 | temp_ff.full = dfixed_const(c); | |
3399 | mc_latency_mclk.full += dfixed_mul(tcas_ff, temp_ff); | |
3400 | temp_ff.full = dfixed_const(4); | |
3401 | mc_latency_mclk.full += dfixed_mul(tras_ff, temp_ff); | |
3402 | mc_latency_mclk.full += dfixed_mul(trp_ff, temp_ff); | |
3403 | mc_latency_mclk.full += k1.full; | |
37cf6b03 | 3404 | |
0242f74d AD |
3405 | mc_latency_mclk.full = dfixed_div(mc_latency_mclk, mclk_ff); |
3406 | mc_latency_mclk.full += dfixed_div(temp_ff, sclk_eff_ff); | |
37cf6b03 | 3407 | |
0242f74d AD |
3408 | /* |
3409 | HW cursor time assuming worst case of full size colour cursor. | |
3410 | */ | |
3411 | temp_ff.full = dfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1)))); | |
3412 | temp_ff.full += trcd_ff.full; | |
3413 | if (temp_ff.full < tras_ff.full) | |
3414 | temp_ff.full = tras_ff.full; | |
3415 | cur_latency_mclk.full = dfixed_div(temp_ff, mclk_ff); | |
37cf6b03 | 3416 | |
0242f74d AD |
3417 | temp_ff.full = dfixed_const(cur_size); |
3418 | cur_latency_sclk.full = dfixed_div(temp_ff, sclk_eff_ff); | |
3419 | /* | |
3420 | Find the total latency for the display data. | |
3421 | */ | |
3422 | disp_latency_overhead.full = dfixed_const(8); | |
3423 | disp_latency_overhead.full = dfixed_div(disp_latency_overhead, sclk_ff); | |
3424 | mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full; | |
3425 | mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full; | |
37cf6b03 | 3426 | |
0242f74d AD |
3427 | if (mc_latency_mclk.full > mc_latency_sclk.full) |
3428 | disp_latency.full = mc_latency_mclk.full; | |
3429 | else | |
3430 | disp_latency.full = mc_latency_sclk.full; | |
551ebd83 | 3431 | |
0242f74d AD |
3432 | /* setup Max GRPH_STOP_REQ default value */ |
3433 | if (ASIC_IS_RV100(rdev)) | |
3434 | max_stop_req = 0x5c; | |
3435 | else | |
3436 | max_stop_req = 0x7c; | |
d785d78b | 3437 | |
0242f74d AD |
3438 | if (mode1) { |
3439 | /* CRTC1 | |
3440 | Set GRPH_BUFFER_CNTL register using h/w defined optimal values. | |
3441 | GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ] | |
3442 | */ | |
3443 | stop_req = mode1->hdisplay * pixel_bytes1 / 16; | |
d785d78b | 3444 | |
0242f74d AD |
3445 | if (stop_req > max_stop_req) |
3446 | stop_req = max_stop_req; | |
551ebd83 | 3447 | |
0242f74d AD |
3448 | /* |
3449 | Find the drain rate of the display buffer. | |
3450 | */ | |
3451 | temp_ff.full = dfixed_const((16/pixel_bytes1)); | |
3452 | disp_drain_rate.full = dfixed_div(pix_clk, temp_ff); | |
551ebd83 | 3453 | |
0242f74d AD |
3454 | /* |
3455 | Find the critical point of the display buffer. | |
3456 | */ | |
3457 | crit_point_ff.full = dfixed_mul(disp_drain_rate, disp_latency); | |
3458 | crit_point_ff.full += dfixed_const_half(0); | |
a41ceb1c | 3459 | |
0242f74d AD |
3460 | critical_point = dfixed_trunc(crit_point_ff); |
3461 | ||
3462 | if (rdev->disp_priority == 2) { | |
3463 | critical_point = 0; | |
551ebd83 | 3464 | } |
40b4a759 | 3465 | |
0242f74d AD |
3466 | /* |
3467 | The critical point should never be above max_stop_req-4. Setting | |
3468 | GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time. | |
3469 | */ | |
3470 | if (max_stop_req - critical_point < 4) | |
3471 | critical_point = 0; | |
3472 | ||
3473 | if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) { | |
3474 | /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/ | |
3475 | critical_point = 0x10; | |
551ebd83 | 3476 | } |
0242f74d AD |
3477 | |
3478 | temp = RREG32(RADEON_GRPH_BUFFER_CNTL); | |
3479 | temp &= ~(RADEON_GRPH_STOP_REQ_MASK); | |
3480 | temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT); | |
3481 | temp &= ~(RADEON_GRPH_START_REQ_MASK); | |
3482 | if ((rdev->family == CHIP_R350) && | |
3483 | (stop_req > 0x15)) { | |
3484 | stop_req -= 0x10; | |
551ebd83 | 3485 | } |
0242f74d AD |
3486 | temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT); |
3487 | temp |= RADEON_GRPH_BUFFER_SIZE; | |
3488 | temp &= ~(RADEON_GRPH_CRITICAL_CNTL | | |
3489 | RADEON_GRPH_CRITICAL_AT_SOF | | |
3490 | RADEON_GRPH_STOP_CNTL); | |
3491 | /* | |
3492 | Write the result into the register. | |
3493 | */ | |
3494 | WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) | | |
3495 | (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT))); | |
40b4a759 | 3496 | |
0242f74d AD |
3497 | #if 0 |
3498 | if ((rdev->family == CHIP_RS400) || | |
3499 | (rdev->family == CHIP_RS480)) { | |
3500 | /* attempt to program RS400 disp regs correctly ??? */ | |
3501 | temp = RREG32(RS400_DISP1_REG_CNTL); | |
3502 | temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK | | |
3503 | RS400_DISP1_STOP_REQ_LEVEL_MASK); | |
3504 | WREG32(RS400_DISP1_REQ_CNTL1, (temp | | |
3505 | (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) | | |
3506 | (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT))); | |
3507 | temp = RREG32(RS400_DMIF_MEM_CNTL1); | |
3508 | temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK | | |
3509 | RS400_DISP1_CRITICAL_POINT_STOP_MASK); | |
3510 | WREG32(RS400_DMIF_MEM_CNTL1, (temp | | |
3511 | (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) | | |
3512 | (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT))); | |
fff1ce4d | 3513 | } |
0242f74d | 3514 | #endif |
fff1ce4d | 3515 | |
0242f74d AD |
3516 | DRM_DEBUG_KMS("GRPH_BUFFER_CNTL from to %x\n", |
3517 | /* (unsigned int)info->SavedReg->grph_buffer_cntl, */ | |
3518 | (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL)); | |
cae94b0a | 3519 | } |
0242f74d AD |
3520 | |
3521 | if (mode2) { | |
3522 | u32 grph2_cntl; | |
3523 | stop_req = mode2->hdisplay * pixel_bytes2 / 16; | |
3524 | ||
3525 | if (stop_req > max_stop_req) | |
3526 | stop_req = max_stop_req; | |
3527 | ||
3528 | /* | |
3529 | Find the drain rate of the display buffer. | |
3530 | */ | |
3531 | temp_ff.full = dfixed_const((16/pixel_bytes2)); | |
3532 | disp_drain_rate2.full = dfixed_div(pix_clk2, temp_ff); | |
3533 | ||
3534 | grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL); | |
3535 | grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK); | |
3536 | grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT); | |
3537 | grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK); | |
3538 | if ((rdev->family == CHIP_R350) && | |
3539 | (stop_req > 0x15)) { | |
3540 | stop_req -= 0x10; | |
551ebd83 | 3541 | } |
0242f74d AD |
3542 | grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT); |
3543 | grph2_cntl |= RADEON_GRPH_BUFFER_SIZE; | |
3544 | grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL | | |
3545 | RADEON_GRPH_CRITICAL_AT_SOF | | |
3546 | RADEON_GRPH_STOP_CNTL); | |
3547 | ||
3548 | if ((rdev->family == CHIP_RS100) || | |
3549 | (rdev->family == CHIP_RS200)) | |
3550 | critical_point2 = 0; | |
3551 | else { | |
3552 | temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128; | |
3553 | temp_ff.full = dfixed_const(temp); | |
3554 | temp_ff.full = dfixed_mul(mclk_ff, temp_ff); | |
3555 | if (sclk_ff.full < temp_ff.full) | |
3556 | temp_ff.full = sclk_ff.full; | |
3557 | ||
3558 | read_return_rate.full = temp_ff.full; | |
3559 | ||
3560 | if (mode1) { | |
3561 | temp_ff.full = read_return_rate.full - disp_drain_rate.full; | |
3562 | time_disp1_drop_priority.full = dfixed_div(crit_point_ff, temp_ff); | |
3563 | } else { | |
3564 | time_disp1_drop_priority.full = 0; | |
551ebd83 | 3565 | } |
0242f74d AD |
3566 | crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full; |
3567 | crit_point_ff.full = dfixed_mul(crit_point_ff, disp_drain_rate2); | |
3568 | crit_point_ff.full += dfixed_const_half(0); | |
3569 | ||
3570 | critical_point2 = dfixed_trunc(crit_point_ff); | |
3571 | ||
3572 | if (rdev->disp_priority == 2) { | |
3573 | critical_point2 = 0; | |
551ebd83 | 3574 | } |
40b4a759 | 3575 | |
0242f74d AD |
3576 | if (max_stop_req - critical_point2 < 4) |
3577 | critical_point2 = 0; | |
551ebd83 | 3578 | |
0242f74d | 3579 | } |
551ebd83 | 3580 | |
0242f74d AD |
3581 | if (critical_point2 == 0 && rdev->family == CHIP_R300) { |
3582 | /* some R300 cards have problem with this set to 0 */ | |
3583 | critical_point2 = 0x10; | |
3584 | } | |
40b4a759 | 3585 | |
0242f74d AD |
3586 | WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) | |
3587 | (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT))); | |
551ebd83 | 3588 | |
0242f74d AD |
3589 | if ((rdev->family == CHIP_RS400) || |
3590 | (rdev->family == CHIP_RS480)) { | |
3591 | #if 0 | |
3592 | /* attempt to program RS400 disp2 regs correctly ??? */ | |
3593 | temp = RREG32(RS400_DISP2_REQ_CNTL1); | |
3594 | temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK | | |
3595 | RS400_DISP2_STOP_REQ_LEVEL_MASK); | |
3596 | WREG32(RS400_DISP2_REQ_CNTL1, (temp | | |
3597 | (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) | | |
3598 | (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT))); | |
3599 | temp = RREG32(RS400_DISP2_REQ_CNTL2); | |
3600 | temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK | | |
3601 | RS400_DISP2_CRITICAL_POINT_STOP_MASK); | |
3602 | WREG32(RS400_DISP2_REQ_CNTL2, (temp | | |
3603 | (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) | | |
3604 | (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT))); | |
3605 | #endif | |
3606 | WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC); | |
3607 | WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000); | |
3608 | WREG32(RS400_DMIF_MEM_CNTL1, 0x29CA71DC); | |
3609 | WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC); | |
551ebd83 | 3610 | } |
0242f74d AD |
3611 | |
3612 | DRM_DEBUG_KMS("GRPH2_BUFFER_CNTL from to %x\n", | |
3613 | (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL)); | |
551ebd83 DA |
3614 | } |
3615 | } | |
3ce0a23d | 3616 | |
e32eb50d | 3617 | int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *ring) |
3ce0a23d JG |
3618 | { |
3619 | uint32_t scratch; | |
3620 | uint32_t tmp = 0; | |
3621 | unsigned i; | |
3622 | int r; | |
3623 | ||
3624 | r = radeon_scratch_get(rdev, &scratch); | |
3625 | if (r) { | |
3626 | DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r); | |
3627 | return r; | |
3628 | } | |
3629 | WREG32(scratch, 0xCAFEDEAD); | |
e32eb50d | 3630 | r = radeon_ring_lock(rdev, ring, 2); |
3ce0a23d JG |
3631 | if (r) { |
3632 | DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); | |
3633 | radeon_scratch_free(rdev, scratch); | |
3634 | return r; | |
3635 | } | |
e32eb50d CK |
3636 | radeon_ring_write(ring, PACKET0(scratch, 0)); |
3637 | radeon_ring_write(ring, 0xDEADBEEF); | |
3638 | radeon_ring_unlock_commit(rdev, ring); | |
3ce0a23d JG |
3639 | for (i = 0; i < rdev->usec_timeout; i++) { |
3640 | tmp = RREG32(scratch); | |
3641 | if (tmp == 0xDEADBEEF) { | |
3642 | break; | |
3643 | } | |
3644 | DRM_UDELAY(1); | |
3645 | } | |
3646 | if (i < rdev->usec_timeout) { | |
3647 | DRM_INFO("ring test succeeded in %d usecs\n", i); | |
3648 | } else { | |
369d7ec1 | 3649 | DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n", |
3ce0a23d JG |
3650 | scratch, tmp); |
3651 | r = -EINVAL; | |
3652 | } | |
3653 | radeon_scratch_free(rdev, scratch); | |
3654 | return r; | |
3655 | } | |
3656 | ||
3657 | void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) | |
3658 | { | |
e32eb50d | 3659 | struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
7b1f2485 | 3660 | |
c7eff978 AD |
3661 | if (ring->rptr_save_reg) { |
3662 | u32 next_rptr = ring->wptr + 2 + 3; | |
3663 | radeon_ring_write(ring, PACKET0(ring->rptr_save_reg, 0)); | |
3664 | radeon_ring_write(ring, next_rptr); | |
3665 | } | |
3666 | ||
e32eb50d CK |
3667 | radeon_ring_write(ring, PACKET0(RADEON_CP_IB_BASE, 1)); |
3668 | radeon_ring_write(ring, ib->gpu_addr); | |
3669 | radeon_ring_write(ring, ib->length_dw); | |
3ce0a23d JG |
3670 | } |
3671 | ||
f712812e | 3672 | int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring) |
3ce0a23d | 3673 | { |
f2e39221 | 3674 | struct radeon_ib ib; |
3ce0a23d JG |
3675 | uint32_t scratch; |
3676 | uint32_t tmp = 0; | |
3677 | unsigned i; | |
3678 | int r; | |
3679 | ||
3680 | r = radeon_scratch_get(rdev, &scratch); | |
3681 | if (r) { | |
3682 | DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r); | |
3683 | return r; | |
3684 | } | |
3685 | WREG32(scratch, 0xCAFEDEAD); | |
4bf3dd92 | 3686 | r = radeon_ib_get(rdev, RADEON_RING_TYPE_GFX_INDEX, &ib, NULL, 256); |
3ce0a23d | 3687 | if (r) { |
af026c5b MD |
3688 | DRM_ERROR("radeon: failed to get ib (%d).\n", r); |
3689 | goto free_scratch; | |
3ce0a23d | 3690 | } |
f2e39221 JG |
3691 | ib.ptr[0] = PACKET0(scratch, 0); |
3692 | ib.ptr[1] = 0xDEADBEEF; | |
3693 | ib.ptr[2] = PACKET2(0); | |
3694 | ib.ptr[3] = PACKET2(0); | |
3695 | ib.ptr[4] = PACKET2(0); | |
3696 | ib.ptr[5] = PACKET2(0); | |
3697 | ib.ptr[6] = PACKET2(0); | |
3698 | ib.ptr[7] = PACKET2(0); | |
3699 | ib.length_dw = 8; | |
4ef72566 | 3700 | r = radeon_ib_schedule(rdev, &ib, NULL); |
3ce0a23d | 3701 | if (r) { |
af026c5b MD |
3702 | DRM_ERROR("radeon: failed to schedule ib (%d).\n", r); |
3703 | goto free_ib; | |
3ce0a23d | 3704 | } |
f2e39221 | 3705 | r = radeon_fence_wait(ib.fence, false); |
3ce0a23d | 3706 | if (r) { |
af026c5b MD |
3707 | DRM_ERROR("radeon: fence wait failed (%d).\n", r); |
3708 | goto free_ib; | |
3ce0a23d JG |
3709 | } |
3710 | for (i = 0; i < rdev->usec_timeout; i++) { | |
3711 | tmp = RREG32(scratch); | |
3712 | if (tmp == 0xDEADBEEF) { | |
3713 | break; | |
3714 | } | |
3715 | DRM_UDELAY(1); | |
3716 | } | |
3717 | if (i < rdev->usec_timeout) { | |
3718 | DRM_INFO("ib test succeeded in %u usecs\n", i); | |
3719 | } else { | |
62f288cf | 3720 | DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n", |
3ce0a23d JG |
3721 | scratch, tmp); |
3722 | r = -EINVAL; | |
3723 | } | |
af026c5b | 3724 | free_ib: |
3ce0a23d | 3725 | radeon_ib_free(rdev, &ib); |
af026c5b MD |
3726 | free_scratch: |
3727 | radeon_scratch_free(rdev, scratch); | |
3ce0a23d JG |
3728 | return r; |
3729 | } | |
9f022ddf | 3730 | |
9f022ddf JG |
3731 | void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save) |
3732 | { | |
3733 | /* Shutdown CP we shouldn't need to do that but better be safe than | |
3734 | * sorry | |
3735 | */ | |
e32eb50d | 3736 | rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; |
9f022ddf JG |
3737 | WREG32(R_000740_CP_CSQ_CNTL, 0); |
3738 | ||
3739 | /* Save few CRTC registers */ | |
ca6ffc64 | 3740 | save->GENMO_WT = RREG8(R_0003C2_GENMO_WT); |
9f022ddf JG |
3741 | save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL); |
3742 | save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL); | |
3743 | save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET); | |
3744 | if (!(rdev->flags & RADEON_SINGLE_CRTC)) { | |
3745 | save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL); | |
3746 | save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET); | |
3747 | } | |
3748 | ||
3749 | /* Disable VGA aperture access */ | |
ca6ffc64 | 3750 | WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT); |
9f022ddf JG |
3751 | /* Disable cursor, overlay, crtc */ |
3752 | WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1)); | |
3753 | WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL | | |
3754 | S_000054_CRTC_DISPLAY_DIS(1)); | |
3755 | WREG32(R_000050_CRTC_GEN_CNTL, | |
3756 | (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) | | |
3757 | S_000050_CRTC_DISP_REQ_EN_B(1)); | |
3758 | WREG32(R_000420_OV0_SCALE_CNTL, | |
3759 | C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL)); | |
3760 | WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET); | |
3761 | if (!(rdev->flags & RADEON_SINGLE_CRTC)) { | |
3762 | WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET | | |
3763 | S_000360_CUR2_LOCK(1)); | |
3764 | WREG32(R_0003F8_CRTC2_GEN_CNTL, | |
3765 | (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) | | |
3766 | S_0003F8_CRTC2_DISPLAY_DIS(1) | | |
3767 | S_0003F8_CRTC2_DISP_REQ_EN_B(1)); | |
3768 | WREG32(R_000360_CUR2_OFFSET, | |
3769 | C_000360_CUR2_LOCK & save->CUR2_OFFSET); | |
3770 | } | |
3771 | } | |
3772 | ||
3773 | void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save) | |
3774 | { | |
3775 | /* Update base address for crtc */ | |
d594e46a | 3776 | WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start); |
9f022ddf | 3777 | if (!(rdev->flags & RADEON_SINGLE_CRTC)) { |
d594e46a | 3778 | WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start); |
9f022ddf JG |
3779 | } |
3780 | /* Restore CRTC registers */ | |
ca6ffc64 | 3781 | WREG8(R_0003C2_GENMO_WT, save->GENMO_WT); |
9f022ddf JG |
3782 | WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL); |
3783 | WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL); | |
3784 | if (!(rdev->flags & RADEON_SINGLE_CRTC)) { | |
3785 | WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL); | |
3786 | } | |
3787 | } | |
ca6ffc64 JG |
3788 | |
3789 | void r100_vga_render_disable(struct radeon_device *rdev) | |
3790 | { | |
d4550907 | 3791 | u32 tmp; |
ca6ffc64 | 3792 | |
d4550907 | 3793 | tmp = RREG8(R_0003C2_GENMO_WT); |
ca6ffc64 JG |
3794 | WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp); |
3795 | } | |
d4550907 JG |
3796 | |
3797 | static void r100_debugfs(struct radeon_device *rdev) | |
3798 | { | |
3799 | int r; | |
3800 | ||
3801 | r = r100_debugfs_mc_info_init(rdev); | |
3802 | if (r) | |
3803 | dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n"); | |
3804 | } | |
3805 | ||
3806 | static void r100_mc_program(struct radeon_device *rdev) | |
3807 | { | |
3808 | struct r100_mc_save save; | |
3809 | ||
3810 | /* Stops all mc clients */ | |
3811 | r100_mc_stop(rdev, &save); | |
3812 | if (rdev->flags & RADEON_IS_AGP) { | |
3813 | WREG32(R_00014C_MC_AGP_LOCATION, | |
3814 | S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) | | |
3815 | S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16)); | |
3816 | WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); | |
3817 | if (rdev->family > CHIP_RV200) | |
3818 | WREG32(R_00015C_AGP_BASE_2, | |
3819 | upper_32_bits(rdev->mc.agp_base) & 0xff); | |
3820 | } else { | |
3821 | WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF); | |
3822 | WREG32(R_000170_AGP_BASE, 0); | |
3823 | if (rdev->family > CHIP_RV200) | |
3824 | WREG32(R_00015C_AGP_BASE_2, 0); | |
3825 | } | |
3826 | /* Wait for mc idle */ | |
3827 | if (r100_mc_wait_for_idle(rdev)) | |
3828 | dev_warn(rdev->dev, "Wait for MC idle timeout.\n"); | |
3829 | /* Program MC, should be a 32bits limited address space */ | |
3830 | WREG32(R_000148_MC_FB_LOCATION, | |
3831 | S_000148_MC_FB_START(rdev->mc.vram_start >> 16) | | |
3832 | S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16)); | |
3833 | r100_mc_resume(rdev, &save); | |
3834 | } | |
3835 | ||
1109ca09 | 3836 | static void r100_clock_startup(struct radeon_device *rdev) |
d4550907 JG |
3837 | { |
3838 | u32 tmp; | |
3839 | ||
3840 | if (radeon_dynclks != -1 && radeon_dynclks) | |
3841 | radeon_legacy_set_clock_gating(rdev, 1); | |
3842 | /* We need to force on some of the block */ | |
3843 | tmp = RREG32_PLL(R_00000D_SCLK_CNTL); | |
3844 | tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1); | |
3845 | if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280)) | |
3846 | tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1); | |
3847 | WREG32_PLL(R_00000D_SCLK_CNTL, tmp); | |
3848 | } | |
3849 | ||
3850 | static int r100_startup(struct radeon_device *rdev) | |
3851 | { | |
3852 | int r; | |
3853 | ||
92cde00c AD |
3854 | /* set common regs */ |
3855 | r100_set_common_regs(rdev); | |
3856 | /* program mc */ | |
d4550907 JG |
3857 | r100_mc_program(rdev); |
3858 | /* Resume clock */ | |
3859 | r100_clock_startup(rdev); | |
d4550907 JG |
3860 | /* Initialize GART (initialize after TTM so we can allocate |
3861 | * memory through TTM but finalize after TTM) */ | |
17e15b0c | 3862 | r100_enable_bm(rdev); |
d4550907 JG |
3863 | if (rdev->flags & RADEON_IS_PCI) { |
3864 | r = r100_pci_gart_enable(rdev); | |
3865 | if (r) | |
3866 | return r; | |
3867 | } | |
724c80e1 AD |
3868 | |
3869 | /* allocate wb buffer */ | |
3870 | r = radeon_wb_init(rdev); | |
3871 | if (r) | |
3872 | return r; | |
3873 | ||
30eb77f4 JG |
3874 | r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); |
3875 | if (r) { | |
3876 | dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); | |
3877 | return r; | |
3878 | } | |
3879 | ||
d4550907 | 3880 | /* Enable IRQ */ |
e49f3959 AH |
3881 | if (!rdev->irq.installed) { |
3882 | r = radeon_irq_kms_init(rdev); | |
3883 | if (r) | |
3884 | return r; | |
3885 | } | |
3886 | ||
d4550907 | 3887 | r100_irq_set(rdev); |
cafe6609 | 3888 | rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); |
d4550907 JG |
3889 | /* 1M ring buffer */ |
3890 | r = r100_cp_init(rdev, 1024 * 1024); | |
3891 | if (r) { | |
ec4f2ac4 | 3892 | dev_err(rdev->dev, "failed initializing CP (%d).\n", r); |
d4550907 JG |
3893 | return r; |
3894 | } | |
b15ba512 | 3895 | |
2898c348 CK |
3896 | r = radeon_ib_pool_init(rdev); |
3897 | if (r) { | |
3898 | dev_err(rdev->dev, "IB initialization failed (%d).\n", r); | |
b15ba512 | 3899 | return r; |
2898c348 | 3900 | } |
b15ba512 | 3901 | |
d4550907 JG |
3902 | return 0; |
3903 | } | |
3904 | ||
3905 | int r100_resume(struct radeon_device *rdev) | |
3906 | { | |
6b7746e8 JG |
3907 | int r; |
3908 | ||
d4550907 JG |
3909 | /* Make sur GART are not working */ |
3910 | if (rdev->flags & RADEON_IS_PCI) | |
3911 | r100_pci_gart_disable(rdev); | |
3912 | /* Resume clock before doing reset */ | |
3913 | r100_clock_startup(rdev); | |
3914 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ | |
a2d07b74 | 3915 | if (radeon_asic_reset(rdev)) { |
d4550907 JG |
3916 | dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", |
3917 | RREG32(R_000E40_RBBM_STATUS), | |
3918 | RREG32(R_0007C0_CP_STAT)); | |
3919 | } | |
3920 | /* post */ | |
3921 | radeon_combios_asic_init(rdev->ddev); | |
3922 | /* Resume clock after posting */ | |
3923 | r100_clock_startup(rdev); | |
550e2d92 DA |
3924 | /* Initialize surface registers */ |
3925 | radeon_surface_init(rdev); | |
b15ba512 JG |
3926 | |
3927 | rdev->accel_working = true; | |
6b7746e8 JG |
3928 | r = r100_startup(rdev); |
3929 | if (r) { | |
3930 | rdev->accel_working = false; | |
3931 | } | |
3932 | return r; | |
d4550907 JG |
3933 | } |
3934 | ||
3935 | int r100_suspend(struct radeon_device *rdev) | |
3936 | { | |
6c7bccea | 3937 | radeon_pm_suspend(rdev); |
d4550907 | 3938 | r100_cp_disable(rdev); |
724c80e1 | 3939 | radeon_wb_disable(rdev); |
d4550907 JG |
3940 | r100_irq_disable(rdev); |
3941 | if (rdev->flags & RADEON_IS_PCI) | |
3942 | r100_pci_gart_disable(rdev); | |
3943 | return 0; | |
3944 | } | |
3945 | ||
3946 | void r100_fini(struct radeon_device *rdev) | |
3947 | { | |
6c7bccea | 3948 | radeon_pm_fini(rdev); |
d4550907 | 3949 | r100_cp_fini(rdev); |
724c80e1 | 3950 | radeon_wb_fini(rdev); |
2898c348 | 3951 | radeon_ib_pool_fini(rdev); |
d4550907 JG |
3952 | radeon_gem_fini(rdev); |
3953 | if (rdev->flags & RADEON_IS_PCI) | |
3954 | r100_pci_gart_fini(rdev); | |
d0269ed8 | 3955 | radeon_agp_fini(rdev); |
d4550907 JG |
3956 | radeon_irq_kms_fini(rdev); |
3957 | radeon_fence_driver_fini(rdev); | |
4c788679 | 3958 | radeon_bo_fini(rdev); |
d4550907 JG |
3959 | radeon_atombios_fini(rdev); |
3960 | kfree(rdev->bios); | |
3961 | rdev->bios = NULL; | |
3962 | } | |
3963 | ||
4c712e6c DA |
3964 | /* |
3965 | * Due to how kexec works, it can leave the hw fully initialised when it | |
3966 | * boots the new kernel. However doing our init sequence with the CP and | |
3967 | * WB stuff setup causes GPU hangs on the RN50 at least. So at startup | |
3968 | * do some quick sanity checks and restore sane values to avoid this | |
3969 | * problem. | |
3970 | */ | |
3971 | void r100_restore_sanity(struct radeon_device *rdev) | |
3972 | { | |
3973 | u32 tmp; | |
3974 | ||
3975 | tmp = RREG32(RADEON_CP_CSQ_CNTL); | |
3976 | if (tmp) { | |
3977 | WREG32(RADEON_CP_CSQ_CNTL, 0); | |
3978 | } | |
3979 | tmp = RREG32(RADEON_CP_RB_CNTL); | |
3980 | if (tmp) { | |
3981 | WREG32(RADEON_CP_RB_CNTL, 0); | |
3982 | } | |
3983 | tmp = RREG32(RADEON_SCRATCH_UMSK); | |
3984 | if (tmp) { | |
3985 | WREG32(RADEON_SCRATCH_UMSK, 0); | |
3986 | } | |
3987 | } | |
3988 | ||
d4550907 JG |
3989 | int r100_init(struct radeon_device *rdev) |
3990 | { | |
3991 | int r; | |
3992 | ||
d4550907 JG |
3993 | /* Register debugfs file specific to this group of asics */ |
3994 | r100_debugfs(rdev); | |
3995 | /* Disable VGA */ | |
3996 | r100_vga_render_disable(rdev); | |
3997 | /* Initialize scratch registers */ | |
3998 | radeon_scratch_init(rdev); | |
3999 | /* Initialize surface registers */ | |
4000 | radeon_surface_init(rdev); | |
4c712e6c DA |
4001 | /* sanity check some register to avoid hangs like after kexec */ |
4002 | r100_restore_sanity(rdev); | |
d4550907 JG |
4003 | /* TODO: disable VGA need to use VGA request */ |
4004 | /* BIOS*/ | |
4005 | if (!radeon_get_bios(rdev)) { | |
4006 | if (ASIC_IS_AVIVO(rdev)) | |
4007 | return -EINVAL; | |
4008 | } | |
4009 | if (rdev->is_atom_bios) { | |
4010 | dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n"); | |
4011 | return -EINVAL; | |
4012 | } else { | |
4013 | r = radeon_combios_init(rdev); | |
4014 | if (r) | |
4015 | return r; | |
4016 | } | |
4017 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ | |
a2d07b74 | 4018 | if (radeon_asic_reset(rdev)) { |
d4550907 JG |
4019 | dev_warn(rdev->dev, |
4020 | "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", | |
4021 | RREG32(R_000E40_RBBM_STATUS), | |
4022 | RREG32(R_0007C0_CP_STAT)); | |
4023 | } | |
4024 | /* check if cards are posted or not */ | |
72542d77 DA |
4025 | if (radeon_boot_test_post_card(rdev) == false) |
4026 | return -EINVAL; | |
d4550907 JG |
4027 | /* Set asic errata */ |
4028 | r100_errata(rdev); | |
4029 | /* Initialize clocks */ | |
4030 | radeon_get_clock_info(rdev->ddev); | |
d594e46a JG |
4031 | /* initialize AGP */ |
4032 | if (rdev->flags & RADEON_IS_AGP) { | |
4033 | r = radeon_agp_init(rdev); | |
4034 | if (r) { | |
4035 | radeon_agp_disable(rdev); | |
4036 | } | |
4037 | } | |
4038 | /* initialize VRAM */ | |
4039 | r100_mc_init(rdev); | |
d4550907 | 4040 | /* Fence driver */ |
30eb77f4 | 4041 | r = radeon_fence_driver_init(rdev); |
d4550907 JG |
4042 | if (r) |
4043 | return r; | |
d4550907 | 4044 | /* Memory manager */ |
4c788679 | 4045 | r = radeon_bo_init(rdev); |
d4550907 JG |
4046 | if (r) |
4047 | return r; | |
4048 | if (rdev->flags & RADEON_IS_PCI) { | |
4049 | r = r100_pci_gart_init(rdev); | |
4050 | if (r) | |
4051 | return r; | |
4052 | } | |
4053 | r100_set_safe_registers(rdev); | |
b15ba512 | 4054 | |
6c7bccea AD |
4055 | /* Initialize power management */ |
4056 | radeon_pm_init(rdev); | |
4057 | ||
d4550907 JG |
4058 | rdev->accel_working = true; |
4059 | r = r100_startup(rdev); | |
4060 | if (r) { | |
4061 | /* Somethings want wront with the accel init stop accel */ | |
4062 | dev_err(rdev->dev, "Disabling GPU acceleration\n"); | |
d4550907 | 4063 | r100_cp_fini(rdev); |
724c80e1 | 4064 | radeon_wb_fini(rdev); |
2898c348 | 4065 | radeon_ib_pool_fini(rdev); |
655efd3d | 4066 | radeon_irq_kms_fini(rdev); |
d4550907 JG |
4067 | if (rdev->flags & RADEON_IS_PCI) |
4068 | r100_pci_gart_fini(rdev); | |
d4550907 JG |
4069 | rdev->accel_working = false; |
4070 | } | |
4071 | return 0; | |
4072 | } | |
6fcbef7a | 4073 | |
2ef9bdfe DV |
4074 | uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg, |
4075 | bool always_indirect) | |
6fcbef7a | 4076 | { |
2ef9bdfe | 4077 | if (reg < rdev->rmmio_size && !always_indirect) |
6fcbef7a AK |
4078 | return readl(((void __iomem *)rdev->rmmio) + reg); |
4079 | else { | |
2c385151 DV |
4080 | unsigned long flags; |
4081 | uint32_t ret; | |
4082 | ||
4083 | spin_lock_irqsave(&rdev->mmio_idx_lock, flags); | |
6fcbef7a | 4084 | writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); |
2c385151 DV |
4085 | ret = readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); |
4086 | spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags); | |
4087 | ||
4088 | return ret; | |
6fcbef7a AK |
4089 | } |
4090 | } | |
4091 | ||
2ef9bdfe DV |
4092 | void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v, |
4093 | bool always_indirect) | |
6fcbef7a | 4094 | { |
2ef9bdfe | 4095 | if (reg < rdev->rmmio_size && !always_indirect) |
6fcbef7a AK |
4096 | writel(v, ((void __iomem *)rdev->rmmio) + reg); |
4097 | else { | |
2c385151 DV |
4098 | unsigned long flags; |
4099 | ||
4100 | spin_lock_irqsave(&rdev->mmio_idx_lock, flags); | |
6fcbef7a AK |
4101 | writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); |
4102 | writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); | |
2c385151 | 4103 | spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags); |
6fcbef7a AK |
4104 | } |
4105 | } | |
4106 | ||
4107 | u32 r100_io_rreg(struct radeon_device *rdev, u32 reg) | |
4108 | { | |
4109 | if (reg < rdev->rio_mem_size) | |
4110 | return ioread32(rdev->rio_mem + reg); | |
4111 | else { | |
4112 | iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX); | |
4113 | return ioread32(rdev->rio_mem + RADEON_MM_DATA); | |
4114 | } | |
4115 | } | |
4116 | ||
4117 | void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v) | |
4118 | { | |
4119 | if (reg < rdev->rio_mem_size) | |
4120 | iowrite32(v, rdev->rio_mem + reg); | |
4121 | else { | |
4122 | iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX); | |
4123 | iowrite32(v, rdev->rio_mem + RADEON_MM_DATA); | |
4124 | } | |
4125 | } |