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drm/radeon/kms: add rn50/r100/r200 CS tracker.
[deliverable/linux.git] / drivers / gpu / drm / radeon / r100.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#include <linux/seq_file.h>
29#include "drmP.h"
30#include "drm.h"
31#include "radeon_drm.h"
771fe6b9
JG		 32#include "radeon_reg.h"
33#include "radeon.h"
70967ab9
BH		 34#include <linux/firmware.h>
35#include <linux/platform_device.h>
36
551ebd83
DA		 37#include "r100_reg_safe.h"
38#include "rn50_reg_safe.h"
39
70967ab9
BH		 40/* Firmware Names */
41#define FIRMWARE_R100 "radeon/R100_cp.bin"
42#define FIRMWARE_R200 "radeon/R200_cp.bin"
43#define FIRMWARE_R300 "radeon/R300_cp.bin"
44#define FIRMWARE_R420 "radeon/R420_cp.bin"
45#define FIRMWARE_RS690 "radeon/RS690_cp.bin"
46#define FIRMWARE_RS600 "radeon/RS600_cp.bin"
47#define FIRMWARE_R520 "radeon/R520_cp.bin"
48
49MODULE_FIRMWARE(FIRMWARE_R100);
50MODULE_FIRMWARE(FIRMWARE_R200);
51MODULE_FIRMWARE(FIRMWARE_R300);
52MODULE_FIRMWARE(FIRMWARE_R420);
53MODULE_FIRMWARE(FIRMWARE_RS690);
54MODULE_FIRMWARE(FIRMWARE_RS600);
55MODULE_FIRMWARE(FIRMWARE_R520);
771fe6b9 56
551ebd83
DA		 57#include "r100_track.h"
58
771fe6b9
JG		 59/* This files gather functions specifics to:
60 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
61 *
62 * Some of these functions might be used by newer ASICs.
63 */
551ebd83 64int r200_init(struct radeon_device *rdev);
771fe6b9
JG		 65void r100_hdp_reset(struct radeon_device *rdev);
66void r100_gpu_init(struct radeon_device *rdev);
67int r100_gui_wait_for_idle(struct radeon_device *rdev);
68int r100_mc_wait_for_idle(struct radeon_device *rdev);
69void r100_gpu_wait_for_vsync(struct radeon_device *rdev);
70void r100_gpu_wait_for_vsync2(struct radeon_device *rdev);
71int r100_debugfs_mc_info_init(struct radeon_device *rdev);
72
73
74/*
75 * PCI GART
76 */
77void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
78{
79 /* TODO: can we do somethings here ? */
80 /* It seems hw only cache one entry so we should discard this
81 * entry otherwise if first GPU GART read hit this entry it
82 * could end up in wrong address. */
83}
84
85int r100_pci_gart_enable(struct radeon_device *rdev)
86{
87 uint32_t tmp;
88 int r;
89
90 /* Initialize common gart structure */
91 r = radeon_gart_init(rdev);
92 if (r) {
93 return r;
94 }
95 if (rdev->gart.table.ram.ptr == NULL) {
96 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
97 r = radeon_gart_table_ram_alloc(rdev);
98 if (r) {
99 return r;
100 }
101 }
102 /* discard memory request outside of configured range */
103 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
104 WREG32(RADEON_AIC_CNTL, tmp);
105 /* set address range for PCI address translate */
106 WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_location);
107 tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
108 WREG32(RADEON_AIC_HI_ADDR, tmp);
109 /* Enable bus mastering */
110 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
111 WREG32(RADEON_BUS_CNTL, tmp);
112 /* set PCI GART page-table base address */
113 WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
114 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
115 WREG32(RADEON_AIC_CNTL, tmp);
116 r100_pci_gart_tlb_flush(rdev);
117 rdev->gart.ready = true;
118 return 0;
119}
120
121void r100_pci_gart_disable(struct radeon_device *rdev)
122{
123 uint32_t tmp;
124
125 /* discard memory request outside of configured range */
126 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
127 WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
128 WREG32(RADEON_AIC_LO_ADDR, 0);
129 WREG32(RADEON_AIC_HI_ADDR, 0);
130}
131
132int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
133{
134 if (i < 0 || i > rdev->gart.num_gpu_pages) {
135 return -EINVAL;
136 }
ed10f95d 137 rdev->gart.table.ram.ptr[i] = cpu_to_le32(lower_32_bits(addr));
771fe6b9
JG		 138 return 0;
139}
140
141int r100_gart_enable(struct radeon_device *rdev)
142{
143 if (rdev->flags & RADEON_IS_AGP) {
144 r100_pci_gart_disable(rdev);
145 return 0;
146 }
147 return r100_pci_gart_enable(rdev);
148}
149
150
151/*
152 * MC
153 */
154void r100_mc_disable_clients(struct radeon_device *rdev)
155{
156 uint32_t ov0_scale_cntl, crtc_ext_cntl, crtc_gen_cntl, crtc2_gen_cntl;
157
158 /* FIXME: is this function correct for rs100,rs200,rs300 ? */
159 if (r100_gui_wait_for_idle(rdev)) {
160 printk(KERN_WARNING "Failed to wait GUI idle while "
161 "programming pipes. Bad things might happen.\n");
162 }
163
164 /* stop display and memory access */
165 ov0_scale_cntl = RREG32(RADEON_OV0_SCALE_CNTL);
166 WREG32(RADEON_OV0_SCALE_CNTL, ov0_scale_cntl & ~RADEON_SCALER_ENABLE);
167 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
168 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl | RADEON_CRTC_DISPLAY_DIS);
169 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
170
171 r100_gpu_wait_for_vsync(rdev);
172
173 WREG32(RADEON_CRTC_GEN_CNTL,
174 (crtc_gen_cntl & ~(RADEON_CRTC_CUR_EN | RADEON_CRTC_ICON_EN)) |
175 RADEON_CRTC_DISP_REQ_EN_B | RADEON_CRTC_EXT_DISP_EN);
176
177 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
178 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
179
180 r100_gpu_wait_for_vsync2(rdev);
181 WREG32(RADEON_CRTC2_GEN_CNTL,
182 (crtc2_gen_cntl &
183 ~(RADEON_CRTC2_CUR_EN | RADEON_CRTC2_ICON_EN)) |
184 RADEON_CRTC2_DISP_REQ_EN_B);
185 }
186
187 udelay(500);
188}
189
190void r100_mc_setup(struct radeon_device *rdev)
191{
192 uint32_t tmp;
193 int r;
194
195 r = r100_debugfs_mc_info_init(rdev);
196 if (r) {
197 DRM_ERROR("Failed to register debugfs file for R100 MC !\n");
198 }
199 /* Write VRAM size in case we are limiting it */
7a50f01a
DA		 200 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
201 /* Novell bug 204882 for RN50/M6/M7 with 8/16/32MB VRAM,
202 * if the aperture is 64MB but we have 32MB VRAM
203 * we report only 32MB VRAM but we have to set MC_FB_LOCATION
204 * to 64MB, otherwise the gpu accidentially dies */
205 tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;
771fe6b9
JG		 206 tmp = REG_SET(RADEON_MC_FB_TOP, tmp >> 16);
207 tmp |= REG_SET(RADEON_MC_FB_START, rdev->mc.vram_location >> 16);
208 WREG32(RADEON_MC_FB_LOCATION, tmp);
209
210 /* Enable bus mastering */
211 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
212 WREG32(RADEON_BUS_CNTL, tmp);
213
214 if (rdev->flags & RADEON_IS_AGP) {
215 tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
216 tmp = REG_SET(RADEON_MC_AGP_TOP, tmp >> 16);
217 tmp |= REG_SET(RADEON_MC_AGP_START, rdev->mc.gtt_location >> 16);
218 WREG32(RADEON_MC_AGP_LOCATION, tmp);
219 WREG32(RADEON_AGP_BASE, rdev->mc.agp_base);
220 } else {
221 WREG32(RADEON_MC_AGP_LOCATION, 0x0FFFFFFF);
222 WREG32(RADEON_AGP_BASE, 0);
223 }
224
225 tmp = RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL;
226 tmp |= (7 << 28);
227 WREG32(RADEON_HOST_PATH_CNTL, tmp | RADEON_HDP_SOFT_RESET | RADEON_HDP_READ_BUFFER_INVALIDATE);
228 (void)RREG32(RADEON_HOST_PATH_CNTL);
229 WREG32(RADEON_HOST_PATH_CNTL, tmp);
230 (void)RREG32(RADEON_HOST_PATH_CNTL);
231}
232
233int r100_mc_init(struct radeon_device *rdev)
234{
235 int r;
236
237 if (r100_debugfs_rbbm_init(rdev)) {
238 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
239 }
240
241 r100_gpu_init(rdev);
242 /* Disable gart which also disable out of gart access */
243 r100_pci_gart_disable(rdev);
244
245 /* Setup GPU memory space */
771fe6b9
JG		 246 rdev->mc.gtt_location = 0xFFFFFFFFUL;
247 if (rdev->flags & RADEON_IS_AGP) {
248 r = radeon_agp_init(rdev);
249 if (r) {
250 printk(KERN_WARNING "[drm] Disabling AGP\n");
251 rdev->flags &= ~RADEON_IS_AGP;
252 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
253 } else {
254 rdev->mc.gtt_location = rdev->mc.agp_base;
255 }
256 }
257 r = radeon_mc_setup(rdev);
258 if (r) {
259 return r;
260 }
261
262 r100_mc_disable_clients(rdev);
263 if (r100_mc_wait_for_idle(rdev)) {
264 printk(KERN_WARNING "Failed to wait MC idle while "
265 "programming pipes. Bad things might happen.\n");
266 }
267
268 r100_mc_setup(rdev);
269 return 0;
270}
271
272void r100_mc_fini(struct radeon_device *rdev)
273{
274 r100_pci_gart_disable(rdev);
275 radeon_gart_table_ram_free(rdev);
276 radeon_gart_fini(rdev);
277}
278
279
7ed220d7
MD		 280/*
281 * Interrupts
282 */
283int r100_irq_set(struct radeon_device *rdev)
284{
285 uint32_t tmp = 0;
286
287 if (rdev->irq.sw_int) {
288 tmp |= RADEON_SW_INT_ENABLE;
289 }
290 if (rdev->irq.crtc_vblank_int[0]) {
291 tmp |= RADEON_CRTC_VBLANK_MASK;
292 }
293 if (rdev->irq.crtc_vblank_int[1]) {
294 tmp |= RADEON_CRTC2_VBLANK_MASK;
295 }
296 WREG32(RADEON_GEN_INT_CNTL, tmp);
297 return 0;
298}
299
300static inline uint32_t r100_irq_ack(struct radeon_device *rdev)
301{
302 uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
303 uint32_t irq_mask = RADEON_SW_INT_TEST | RADEON_CRTC_VBLANK_STAT |
304 RADEON_CRTC2_VBLANK_STAT;
305
306 if (irqs) {
307 WREG32(RADEON_GEN_INT_STATUS, irqs);
308 }
309 return irqs & irq_mask;
310}
311
312int r100_irq_process(struct radeon_device *rdev)
313{
314 uint32_t status;
315
316 status = r100_irq_ack(rdev);
317 if (!status) {
318 return IRQ_NONE;
319 }
320 while (status) {
321 /* SW interrupt */
322 if (status & RADEON_SW_INT_TEST) {
323 radeon_fence_process(rdev);
324 }
325 /* Vertical blank interrupts */
326 if (status & RADEON_CRTC_VBLANK_STAT) {
327 drm_handle_vblank(rdev->ddev, 0);
328 }
329 if (status & RADEON_CRTC2_VBLANK_STAT) {
330 drm_handle_vblank(rdev->ddev, 1);
331 }
332 status = r100_irq_ack(rdev);
333 }
334 return IRQ_HANDLED;
335}
336
337u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
338{
339 if (crtc == 0)
340 return RREG32(RADEON_CRTC_CRNT_FRAME);
341 else
342 return RREG32(RADEON_CRTC2_CRNT_FRAME);
343}
344
345
771fe6b9
JG		 346/*
347 * Fence emission
348 */
349void r100_fence_ring_emit(struct radeon_device *rdev,
350 struct radeon_fence *fence)
351{
352 /* Who ever call radeon_fence_emit should call ring_lock and ask
353 * for enough space (today caller are ib schedule and buffer move) */
354 /* Wait until IDLE & CLEAN */
355 radeon_ring_write(rdev, PACKET0(0x1720, 0));
356 radeon_ring_write(rdev, (1 << 16) | (1 << 17));
357 /* Emit fence sequence & fire IRQ */
358 radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
359 radeon_ring_write(rdev, fence->seq);
360 radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0));
361 radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
362}
363
364
365/*
366 * Writeback
367 */
368int r100_wb_init(struct radeon_device *rdev)
369{
370 int r;
371
372 if (rdev->wb.wb_obj == NULL) {
373 r = radeon_object_create(rdev, NULL, 4096,
374 true,
375 RADEON_GEM_DOMAIN_GTT,
376 false, &rdev->wb.wb_obj);
377 if (r) {
378 DRM_ERROR("radeon: failed to create WB buffer (%d).\n", r);
379 return r;
380 }
381 r = radeon_object_pin(rdev->wb.wb_obj,
382 RADEON_GEM_DOMAIN_GTT,
383 &rdev->wb.gpu_addr);
384 if (r) {
385 DRM_ERROR("radeon: failed to pin WB buffer (%d).\n", r);
386 return r;
387 }
388 r = radeon_object_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
389 if (r) {
390 DRM_ERROR("radeon: failed to map WB buffer (%d).\n", r);
391 return r;
392 }
393 }
394 WREG32(0x774, rdev->wb.gpu_addr);
395 WREG32(0x70C, rdev->wb.gpu_addr + 1024);
396 WREG32(0x770, 0xff);
397 return 0;
398}
399
400void r100_wb_fini(struct radeon_device *rdev)
401{
402 if (rdev->wb.wb_obj) {
403 radeon_object_kunmap(rdev->wb.wb_obj);
404 radeon_object_unpin(rdev->wb.wb_obj);
405 radeon_object_unref(&rdev->wb.wb_obj);
406 rdev->wb.wb = NULL;
407 rdev->wb.wb_obj = NULL;
408 }
409}
410
411int r100_copy_blit(struct radeon_device *rdev,
412 uint64_t src_offset,
413 uint64_t dst_offset,
414 unsigned num_pages,
415 struct radeon_fence *fence)
416{
417 uint32_t cur_pages;
418 uint32_t stride_bytes = PAGE_SIZE;
419 uint32_t pitch;
420 uint32_t stride_pixels;
421 unsigned ndw;
422 int num_loops;
423 int r = 0;
424
425 /* radeon limited to 16k stride */
426 stride_bytes &= 0x3fff;
427 /* radeon pitch is /64 */
428 pitch = stride_bytes / 64;
429 stride_pixels = stride_bytes / 4;
430 num_loops = DIV_ROUND_UP(num_pages, 8191);
431
432 /* Ask for enough room for blit + flush + fence */
433 ndw = 64 + (10 * num_loops);
434 r = radeon_ring_lock(rdev, ndw);
435 if (r) {
436 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
437 return -EINVAL;
438 }
439 while (num_pages > 0) {
440 cur_pages = num_pages;
441 if (cur_pages > 8191) {
442 cur_pages = 8191;
443 }
444 num_pages -= cur_pages;
445
446 /* pages are in Y direction - height
447 page width in X direction - width */
448 radeon_ring_write(rdev, PACKET3(PACKET3_BITBLT_MULTI, 8));
449 radeon_ring_write(rdev,
450 RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
451 RADEON_GMC_DST_PITCH_OFFSET_CNTL |
452 RADEON_GMC_SRC_CLIPPING |
453 RADEON_GMC_DST_CLIPPING |
454 RADEON_GMC_BRUSH_NONE |
455 (RADEON_COLOR_FORMAT_ARGB8888 << 8) |
456 RADEON_GMC_SRC_DATATYPE_COLOR |
457 RADEON_ROP3_S |
458 RADEON_DP_SRC_SOURCE_MEMORY |
459 RADEON_GMC_CLR_CMP_CNTL_DIS |
460 RADEON_GMC_WR_MSK_DIS);
461 radeon_ring_write(rdev, (pitch << 22) | (src_offset >> 10));
462 radeon_ring_write(rdev, (pitch << 22) | (dst_offset >> 10));
463 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
464 radeon_ring_write(rdev, 0);
465 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
466 radeon_ring_write(rdev, num_pages);
467 radeon_ring_write(rdev, num_pages);
468 radeon_ring_write(rdev, cur_pages | (stride_pixels << 16));
469 }
470 radeon_ring_write(rdev, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
471 radeon_ring_write(rdev, RADEON_RB2D_DC_FLUSH_ALL);
472 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
473 radeon_ring_write(rdev,
474 RADEON_WAIT_2D_IDLECLEAN |
475 RADEON_WAIT_HOST_IDLECLEAN |
476 RADEON_WAIT_DMA_GUI_IDLE);
477 if (fence) {
478 r = radeon_fence_emit(rdev, fence);
479 }
480 radeon_ring_unlock_commit(rdev);
481 return r;
482}
483
484
485/*
486 * CP
487 */
488void r100_ring_start(struct radeon_device *rdev)
489{
490 int r;
491
492 r = radeon_ring_lock(rdev, 2);
493 if (r) {
494 return;
495 }
496 radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
497 radeon_ring_write(rdev,
498 RADEON_ISYNC_ANY2D_IDLE3D |
499 RADEON_ISYNC_ANY3D_IDLE2D |
500 RADEON_ISYNC_WAIT_IDLEGUI |
501 RADEON_ISYNC_CPSCRATCH_IDLEGUI);
502 radeon_ring_unlock_commit(rdev);
503}
504
70967ab9
BH		 505
506/* Load the microcode for the CP */
507static int r100_cp_init_microcode(struct radeon_device *rdev)
771fe6b9 508{
70967ab9
BH		 509 struct platform_device *pdev;
510 const char *fw_name = NULL;
511 int err;
771fe6b9 512
70967ab9 513 DRM_DEBUG("\n");
771fe6b9 514
70967ab9
BH		 515 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
516 err = IS_ERR(pdev);
517 if (err) {
518 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
519 return -EINVAL;
520 }
771fe6b9
JG		 521 if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) ||
522 (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) ||
523 (rdev->family == CHIP_RS200)) {
524 DRM_INFO("Loading R100 Microcode\n");
70967ab9 525 fw_name = FIRMWARE_R100;
771fe6b9
JG		 526 } else if ((rdev->family == CHIP_R200) ||
527 (rdev->family == CHIP_RV250) ||
528 (rdev->family == CHIP_RV280) ||
529 (rdev->family == CHIP_RS300)) {
530 DRM_INFO("Loading R200 Microcode\n");
70967ab9 531 fw_name = FIRMWARE_R200;
771fe6b9
JG		 532 } else if ((rdev->family == CHIP_R300) ||
533 (rdev->family == CHIP_R350) ||
534 (rdev->family == CHIP_RV350) ||
535 (rdev->family == CHIP_RV380) ||
536 (rdev->family == CHIP_RS400) ||
537 (rdev->family == CHIP_RS480)) {
538 DRM_INFO("Loading R300 Microcode\n");
70967ab9 539 fw_name = FIRMWARE_R300;
771fe6b9
JG		 540 } else if ((rdev->family == CHIP_R420) ||
541 (rdev->family == CHIP_R423) ||
542 (rdev->family == CHIP_RV410)) {
543 DRM_INFO("Loading R400 Microcode\n");
70967ab9 544 fw_name = FIRMWARE_R420;
771fe6b9
JG		 545 } else if ((rdev->family == CHIP_RS690) ||
546 (rdev->family == CHIP_RS740)) {
547 DRM_INFO("Loading RS690/RS740 Microcode\n");
70967ab9 548 fw_name = FIRMWARE_RS690;
771fe6b9
JG		 549 } else if (rdev->family == CHIP_RS600) {
550 DRM_INFO("Loading RS600 Microcode\n");
70967ab9 551 fw_name = FIRMWARE_RS600;
771fe6b9
JG		 552 } else if ((rdev->family == CHIP_RV515) ||
553 (rdev->family == CHIP_R520) ||
554 (rdev->family == CHIP_RV530) ||
555 (rdev->family == CHIP_R580) ||
556 (rdev->family == CHIP_RV560) ||
557 (rdev->family == CHIP_RV570)) {
558 DRM_INFO("Loading R500 Microcode\n");
70967ab9
BH		 559 fw_name = FIRMWARE_R520;
560 }
561
562 err = request_firmware(&rdev->fw, fw_name, &pdev->dev);
563 platform_device_unregister(pdev);
564 if (err) {
565 printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
566 fw_name);
567 } else if (rdev->fw->size % 8) {
568 printk(KERN_ERR
569 "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
570 rdev->fw->size, fw_name);
571 err = -EINVAL;
572 release_firmware(rdev->fw);
573 rdev->fw = NULL;
574 }
575 return err;
576}
577static void r100_cp_load_microcode(struct radeon_device *rdev)
578{
579 const __be32 *fw_data;
580 int i, size;
581
582 if (r100_gui_wait_for_idle(rdev)) {
583 printk(KERN_WARNING "Failed to wait GUI idle while "
584 "programming pipes. Bad things might happen.\n");
585 }
586
587 if (rdev->fw) {
588 size = rdev->fw->size / 4;
589 fw_data = (const __be32 *)&rdev->fw->data[0];
590 WREG32(RADEON_CP_ME_RAM_ADDR, 0);
591 for (i = 0; i < size; i += 2) {
592 WREG32(RADEON_CP_ME_RAM_DATAH,
593 be32_to_cpup(&fw_data[i]));
594 WREG32(RADEON_CP_ME_RAM_DATAL,
595 be32_to_cpup(&fw_data[i + 1]));
771fe6b9
JG		 596 }
597 }
598}
599
600int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
601{
602 unsigned rb_bufsz;
603 unsigned rb_blksz;
604 unsigned max_fetch;
605 unsigned pre_write_timer;
606 unsigned pre_write_limit;
607 unsigned indirect2_start;
608 unsigned indirect1_start;
609 uint32_t tmp;
610 int r;
611
612 if (r100_debugfs_cp_init(rdev)) {
613 DRM_ERROR("Failed to register debugfs file for CP !\n");
614 }
615 /* Reset CP */
616 tmp = RREG32(RADEON_CP_CSQ_STAT);
617 if ((tmp & (1 << 31))) {
618 DRM_INFO("radeon: cp busy (0x%08X) resetting\n", tmp);
619 WREG32(RADEON_CP_CSQ_MODE, 0);
620 WREG32(RADEON_CP_CSQ_CNTL, 0);
621 WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_CP);
622 tmp = RREG32(RADEON_RBBM_SOFT_RESET);
623 mdelay(2);
624 WREG32(RADEON_RBBM_SOFT_RESET, 0);
625 tmp = RREG32(RADEON_RBBM_SOFT_RESET);
626 mdelay(2);
627 tmp = RREG32(RADEON_CP_CSQ_STAT);
628 if ((tmp & (1 << 31))) {
629 DRM_INFO("radeon: cp reset failed (0x%08X)\n", tmp);
630 }
631 } else {
632 DRM_INFO("radeon: cp idle (0x%08X)\n", tmp);
633 }
70967ab9
BH		 634
635 if (!rdev->fw) {
636 r = r100_cp_init_microcode(rdev);
637 if (r) {
638 DRM_ERROR("Failed to load firmware!\n");
639 return r;
640 }
641 }
642
771fe6b9
JG		 643 /* Align ring size */
644 rb_bufsz = drm_order(ring_size / 8);
645 ring_size = (1 << (rb_bufsz + 1)) * 4;
646 r100_cp_load_microcode(rdev);
647 r = radeon_ring_init(rdev, ring_size);
648 if (r) {
649 return r;
650 }
651 /* Each time the cp read 1024 bytes (16 dword/quadword) update
652 * the rptr copy in system ram */
653 rb_blksz = 9;
654 /* cp will read 128bytes at a time (4 dwords) */
655 max_fetch = 1;
656 rdev->cp.align_mask = 16 - 1;
657 /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
658 pre_write_timer = 64;
659 /* Force CP_RB_WPTR write if written more than one time before the
660 * delay expire
661 */
662 pre_write_limit = 0;
663 /* Setup the cp cache like this (cache size is 96 dwords) :
664 * RING 0 to 15
665 * INDIRECT1 16 to 79
666 * INDIRECT2 80 to 95
667 * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
668 * indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
669 * indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
670 * Idea being that most of the gpu cmd will be through indirect1 buffer
671 * so it gets the bigger cache.
672 */
673 indirect2_start = 80;
674 indirect1_start = 16;
675 /* cp setup */
676 WREG32(0x718, pre_write_timer | (pre_write_limit << 28));
677 WREG32(RADEON_CP_RB_CNTL,
4e484e7d
MD		 678#ifdef __BIG_ENDIAN
679 RADEON_BUF_SWAP_32BIT |
680#endif
771fe6b9
JG		 681 REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
682 REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
683 REG_SET(RADEON_MAX_FETCH, max_fetch) |
684 RADEON_RB_NO_UPDATE);
685 /* Set ring address */
686 DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)rdev->cp.gpu_addr);
687 WREG32(RADEON_CP_RB_BASE, rdev->cp.gpu_addr);
688 /* Force read & write ptr to 0 */
689 tmp = RREG32(RADEON_CP_RB_CNTL);
690 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
691 WREG32(RADEON_CP_RB_RPTR_WR, 0);
692 WREG32(RADEON_CP_RB_WPTR, 0);
693 WREG32(RADEON_CP_RB_CNTL, tmp);
694 udelay(10);
695 rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
696 rdev->cp.wptr = RREG32(RADEON_CP_RB_WPTR);
697 /* Set cp mode to bus mastering & enable cp*/
698 WREG32(RADEON_CP_CSQ_MODE,
699 REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
700 REG_SET(RADEON_INDIRECT1_START, indirect1_start));
701 WREG32(0x718, 0);
702 WREG32(0x744, 0x00004D4D);
703 WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
704 radeon_ring_start(rdev);
705 r = radeon_ring_test(rdev);
706 if (r) {
707 DRM_ERROR("radeon: cp isn't working (%d).\n", r);
708 return r;
709 }
710 rdev->cp.ready = true;
711 return 0;
712}
713
714void r100_cp_fini(struct radeon_device *rdev)
715{
716 /* Disable ring */
717 rdev->cp.ready = false;
718 WREG32(RADEON_CP_CSQ_CNTL, 0);
719 radeon_ring_fini(rdev);
720 DRM_INFO("radeon: cp finalized\n");
721}
722
723void r100_cp_disable(struct radeon_device *rdev)
724{
725 /* Disable ring */
726 rdev->cp.ready = false;
727 WREG32(RADEON_CP_CSQ_MODE, 0);
728 WREG32(RADEON_CP_CSQ_CNTL, 0);
729 if (r100_gui_wait_for_idle(rdev)) {
730 printk(KERN_WARNING "Failed to wait GUI idle while "
731 "programming pipes. Bad things might happen.\n");
732 }
733}
734
735int r100_cp_reset(struct radeon_device *rdev)
736{
737 uint32_t tmp;
738 bool reinit_cp;
739 int i;
740
741 reinit_cp = rdev->cp.ready;
742 rdev->cp.ready = false;
743 WREG32(RADEON_CP_CSQ_MODE, 0);
744 WREG32(RADEON_CP_CSQ_CNTL, 0);
745 WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_CP);
746 (void)RREG32(RADEON_RBBM_SOFT_RESET);
747 udelay(200);
748 WREG32(RADEON_RBBM_SOFT_RESET, 0);
749 /* Wait to prevent race in RBBM_STATUS */
750 mdelay(1);
751 for (i = 0; i < rdev->usec_timeout; i++) {
752 tmp = RREG32(RADEON_RBBM_STATUS);
753 if (!(tmp & (1 << 16))) {
754 DRM_INFO("CP reset succeed (RBBM_STATUS=0x%08X)\n",
755 tmp);
756 if (reinit_cp) {
757 return r100_cp_init(rdev, rdev->cp.ring_size);
758 }
759 return 0;
760 }
761 DRM_UDELAY(1);
762 }
763 tmp = RREG32(RADEON_RBBM_STATUS);
764 DRM_ERROR("Failed to reset CP (RBBM_STATUS=0x%08X)!\n", tmp);
765 return -1;
766}
767
768
769/*
770 * CS functions
771 */
772int r100_cs_parse_packet0(struct radeon_cs_parser *p,
773 struct radeon_cs_packet *pkt,
068a117c 774 const unsigned *auth, unsigned n,
771fe6b9
JG		 775 radeon_packet0_check_t check)
776{
777 unsigned reg;
778 unsigned i, j, m;
779 unsigned idx;
780 int r;
781
782 idx = pkt->idx + 1;
783 reg = pkt->reg;
068a117c
JG		 784 /* Check that register fall into register range
785 * determined by the number of entry (n) in the
786 * safe register bitmap.
787 */
771fe6b9
JG		 788 if (pkt->one_reg_wr) {
789 if ((reg >> 7) > n) {
790 return -EINVAL;
791 }
792 } else {
793 if (((reg + (pkt->count << 2)) >> 7) > n) {
794 return -EINVAL;
795 }
796 }
797 for (i = 0; i <= pkt->count; i++, idx++) {
798 j = (reg >> 7);
799 m = 1 << ((reg >> 2) & 31);
800 if (auth[j] & m) {
801 r = check(p, pkt, idx, reg);
802 if (r) {
803 return r;
804 }
805 }
806 if (pkt->one_reg_wr) {
807 if (!(auth[j] & m)) {
808 break;
809 }
810 } else {
811 reg += 4;
812 }
813 }
814 return 0;
815}
816
771fe6b9
JG		 817void r100_cs_dump_packet(struct radeon_cs_parser *p,
818 struct radeon_cs_packet *pkt)
819{
820 struct radeon_cs_chunk *ib_chunk;
821 volatile uint32_t *ib;
822 unsigned i;
823 unsigned idx;
824
825 ib = p->ib->ptr;
826 ib_chunk = &p->chunks[p->chunk_ib_idx];
827 idx = pkt->idx;
828 for (i = 0; i <= (pkt->count + 1); i++, idx++) {
829 DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]);
830 }
831}
832
833/**
834 * r100_cs_packet_parse() - parse cp packet and point ib index to next packet
835 * @parser: parser structure holding parsing context.
836 * @pkt: where to store packet informations
837 *
838 * Assume that chunk_ib_index is properly set. Will return -EINVAL
839 * if packet is bigger than remaining ib size. or if packets is unknown.
840 **/
841int r100_cs_packet_parse(struct radeon_cs_parser *p,
842 struct radeon_cs_packet *pkt,
843 unsigned idx)
844{
845 struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
fa99239c 846 uint32_t header;
771fe6b9
JG		 847
848 if (idx >= ib_chunk->length_dw) {
849 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
850 idx, ib_chunk->length_dw);
851 return -EINVAL;
852 }
fa99239c 853 header = ib_chunk->kdata[idx];
771fe6b9
JG		 854 pkt->idx = idx;
855 pkt->type = CP_PACKET_GET_TYPE(header);
856 pkt->count = CP_PACKET_GET_COUNT(header);
857 switch (pkt->type) {
858 case PACKET_TYPE0:
859 pkt->reg = CP_PACKET0_GET_REG(header);
860 pkt->one_reg_wr = CP_PACKET0_GET_ONE_REG_WR(header);
861 break;
862 case PACKET_TYPE3:
863 pkt->opcode = CP_PACKET3_GET_OPCODE(header);
864 break;
865 case PACKET_TYPE2:
866 pkt->count = -1;
867 break;
868 default:
869 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
870 return -EINVAL;
871 }
872 if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
873 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
874 pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
875 return -EINVAL;
876 }
877 return 0;
878}
879
531369e6
DA		 880/**
881 * r100_cs_packet_next_vline() - parse userspace VLINE packet
882 * @parser: parser structure holding parsing context.
883 *
884 * Userspace sends a special sequence for VLINE waits.
885 * PACKET0 - VLINE_START_END + value
886 * PACKET0 - WAIT_UNTIL +_value
887 * RELOC (P3) - crtc_id in reloc.
888 *
889 * This function parses this and relocates the VLINE START END
890 * and WAIT UNTIL packets to the correct crtc.
891 * It also detects a switched off crtc and nulls out the
892 * wait in that case.
893 */
894int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
895{
896 struct radeon_cs_chunk *ib_chunk;
897 struct drm_mode_object *obj;
898 struct drm_crtc *crtc;
899 struct radeon_crtc *radeon_crtc;
900 struct radeon_cs_packet p3reloc, waitreloc;
901 int crtc_id;
902 int r;
903 uint32_t header, h_idx, reg;
904
905 ib_chunk = &p->chunks[p->chunk_ib_idx];
906
907 /* parse the wait until */
908 r = r100_cs_packet_parse(p, &waitreloc, p->idx);
909 if (r)
910 return r;
911
912 /* check its a wait until and only 1 count */
913 if (waitreloc.reg != RADEON_WAIT_UNTIL ||
914 waitreloc.count != 0) {
915 DRM_ERROR("vline wait had illegal wait until segment\n");
916 r = -EINVAL;
917 return r;
918 }
919
920 if (ib_chunk->kdata[waitreloc.idx + 1] != RADEON_WAIT_CRTC_VLINE) {
921 DRM_ERROR("vline wait had illegal wait until\n");
922 r = -EINVAL;
923 return r;
924 }
925
926 /* jump over the NOP */
927 r = r100_cs_packet_parse(p, &p3reloc, p->idx);
928 if (r)
929 return r;
930
931 h_idx = p->idx - 2;
932 p->idx += waitreloc.count;
933 p->idx += p3reloc.count;
934
935 header = ib_chunk->kdata[h_idx];
936 crtc_id = ib_chunk->kdata[h_idx + 5];
937 reg = ib_chunk->kdata[h_idx] >> 2;
938 mutex_lock(&p->rdev->ddev->mode_config.mutex);
939 obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
940 if (!obj) {
941 DRM_ERROR("cannot find crtc %d\n", crtc_id);
942 r = -EINVAL;
943 goto out;
944 }
945 crtc = obj_to_crtc(obj);
946 radeon_crtc = to_radeon_crtc(crtc);
947 crtc_id = radeon_crtc->crtc_id;
948
949 if (!crtc->enabled) {
950 /* if the CRTC isn't enabled - we need to nop out the wait until */
951 ib_chunk->kdata[h_idx + 2] = PACKET2(0);
952 ib_chunk->kdata[h_idx + 3] = PACKET2(0);
953 } else if (crtc_id == 1) {
954 switch (reg) {
955 case AVIVO_D1MODE_VLINE_START_END:
956 header &= R300_CP_PACKET0_REG_MASK;
957 header |= AVIVO_D2MODE_VLINE_START_END >> 2;
958 break;
959 case RADEON_CRTC_GUI_TRIG_VLINE:
960 header &= R300_CP_PACKET0_REG_MASK;
961 header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2;
962 break;
963 default:
964 DRM_ERROR("unknown crtc reloc\n");
965 r = -EINVAL;
966 goto out;
967 }
968 ib_chunk->kdata[h_idx] = header;
969 ib_chunk->kdata[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1;
970 }
971out:
972 mutex_unlock(&p->rdev->ddev->mode_config.mutex);
973 return r;
974}
975
771fe6b9
JG		 976/**
977 * r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3
978 * @parser: parser structure holding parsing context.
979 * @data: pointer to relocation data
980 * @offset_start: starting offset
981 * @offset_mask: offset mask (to align start offset on)
982 * @reloc: reloc informations
983 *
984 * Check next packet is relocation packet3, do bo validation and compute
985 * GPU offset using the provided start.
986 **/
987int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
988 struct radeon_cs_reloc **cs_reloc)
989{
990 struct radeon_cs_chunk *ib_chunk;
991 struct radeon_cs_chunk *relocs_chunk;
992 struct radeon_cs_packet p3reloc;
993 unsigned idx;
994 int r;
995
996 if (p->chunk_relocs_idx == -1) {
997 DRM_ERROR("No relocation chunk !\n");
998 return -EINVAL;
999 }
1000 *cs_reloc = NULL;
1001 ib_chunk = &p->chunks[p->chunk_ib_idx];
1002 relocs_chunk = &p->chunks[p->chunk_relocs_idx];
1003 r = r100_cs_packet_parse(p, &p3reloc, p->idx);
1004 if (r) {
1005 return r;
1006 }
1007 p->idx += p3reloc.count + 2;
1008 if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
1009 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
1010 p3reloc.idx);
1011 r100_cs_dump_packet(p, &p3reloc);
1012 return -EINVAL;
1013 }
1014 idx = ib_chunk->kdata[p3reloc.idx + 1];
1015 if (idx >= relocs_chunk->length_dw) {
1016 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
1017 idx, relocs_chunk->length_dw);
1018 r100_cs_dump_packet(p, &p3reloc);
1019 return -EINVAL;
1020 }
1021 /* FIXME: we assume reloc size is 4 dwords */
1022 *cs_reloc = p->relocs_ptr[(idx / 4)];
1023 return 0;
1024}
1025
551ebd83
DA		 1026static int r100_get_vtx_size(uint32_t vtx_fmt)
1027{
1028 int vtx_size;
1029 vtx_size = 2;
1030 /* ordered according to bits in spec */
1031 if (vtx_fmt & RADEON_SE_VTX_FMT_W0)
1032 vtx_size++;
1033 if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR)
1034 vtx_size += 3;
1035 if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA)
1036 vtx_size++;
1037 if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR)
1038 vtx_size++;
1039 if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC)
1040 vtx_size += 3;
1041 if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG)
1042 vtx_size++;
1043 if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC)
1044 vtx_size++;
1045 if (vtx_fmt & RADEON_SE_VTX_FMT_ST0)
1046 vtx_size += 2;
1047 if (vtx_fmt & RADEON_SE_VTX_FMT_ST1)
1048 vtx_size += 2;
1049 if (vtx_fmt & RADEON_SE_VTX_FMT_Q1)
1050 vtx_size++;
1051 if (vtx_fmt & RADEON_SE_VTX_FMT_ST2)
1052 vtx_size += 2;
1053 if (vtx_fmt & RADEON_SE_VTX_FMT_Q2)
1054 vtx_size++;
1055 if (vtx_fmt & RADEON_SE_VTX_FMT_ST3)
1056 vtx_size += 2;
1057 if (vtx_fmt & RADEON_SE_VTX_FMT_Q3)
1058 vtx_size++;
1059 if (vtx_fmt & RADEON_SE_VTX_FMT_Q0)
1060 vtx_size++;
1061 /* blend weight */
1062 if (vtx_fmt & (0x7 << 15))
1063 vtx_size += (vtx_fmt >> 15) & 0x7;
1064 if (vtx_fmt & RADEON_SE_VTX_FMT_N0)
1065 vtx_size += 3;
1066 if (vtx_fmt & RADEON_SE_VTX_FMT_XY1)
1067 vtx_size += 2;
1068 if (vtx_fmt & RADEON_SE_VTX_FMT_Z1)
1069 vtx_size++;
1070 if (vtx_fmt & RADEON_SE_VTX_FMT_W1)
1071 vtx_size++;
1072 if (vtx_fmt & RADEON_SE_VTX_FMT_N1)
1073 vtx_size++;
1074 if (vtx_fmt & RADEON_SE_VTX_FMT_Z)
1075 vtx_size++;
1076 return vtx_size;
1077}
1078
771fe6b9 1079static int r100_packet0_check(struct radeon_cs_parser *p,
551ebd83
DA		 1080 struct radeon_cs_packet *pkt,
1081 unsigned idx, unsigned reg)
771fe6b9
JG		 1082{
1083 struct radeon_cs_chunk *ib_chunk;
1084 struct radeon_cs_reloc *reloc;
551ebd83 1085 struct r100_cs_track *track;
771fe6b9
JG		 1086 volatile uint32_t *ib;
1087 uint32_t tmp;
771fe6b9 1088 int r;
551ebd83 1089 int i, face;
e024e110 1090 u32 tile_flags = 0;
771fe6b9
JG		 1091
1092 ib = p->ib->ptr;
1093 ib_chunk = &p->chunks[p->chunk_ib_idx];
551ebd83
DA		 1094 track = (struct r100_cs_track *)p->track;
1095
1096 switch (reg) {
1097 case RADEON_CRTC_GUI_TRIG_VLINE:
1098 r = r100_cs_packet_parse_vline(p);
1099 if (r) {
1100 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1101 idx, reg);
1102 r100_cs_dump_packet(p, pkt);
1103 return r;
1104 }
1105 break;
771fe6b9
JG		 1106 /* FIXME: only allow PACKET3 blit? easier to check for out of
1107 * range access */
551ebd83
DA		 1108 case RADEON_DST_PITCH_OFFSET:
1109 case RADEON_SRC_PITCH_OFFSET:
1110 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
1111 if (r)
1112 return r;
1113 break;
1114 case RADEON_RB3D_DEPTHOFFSET:
1115 r = r100_cs_packet_next_reloc(p, &reloc);
1116 if (r) {
1117 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1118 idx, reg);
1119 r100_cs_dump_packet(p, pkt);
1120 return r;
1121 }
1122 track->zb.robj = reloc->robj;
1123 track->zb.offset = ib_chunk->kdata[idx];
1124 ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
1125 break;
1126 case RADEON_RB3D_COLOROFFSET:
1127 r = r100_cs_packet_next_reloc(p, &reloc);
1128 if (r) {
1129 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1130 idx, reg);
1131 r100_cs_dump_packet(p, pkt);
1132 return r;
1133 }
1134 track->cb[0].robj = reloc->robj;
1135 track->cb[0].offset = ib_chunk->kdata[idx];
1136 ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
1137 break;
1138 case RADEON_PP_TXOFFSET_0:
1139 case RADEON_PP_TXOFFSET_1:
1140 case RADEON_PP_TXOFFSET_2:
1141 i = (reg - RADEON_PP_TXOFFSET_0) / 24;
1142 r = r100_cs_packet_next_reloc(p, &reloc);
1143 if (r) {
1144 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1145 idx, reg);
1146 r100_cs_dump_packet(p, pkt);
1147 return r;
1148 }
1149 ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
1150 track->textures[i].robj = reloc->robj;
1151 break;
1152 case RADEON_PP_CUBIC_OFFSET_T0_0:
1153 case RADEON_PP_CUBIC_OFFSET_T0_1:
1154 case RADEON_PP_CUBIC_OFFSET_T0_2:
1155 case RADEON_PP_CUBIC_OFFSET_T0_3:
1156 case RADEON_PP_CUBIC_OFFSET_T0_4:
1157 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
1158 r = r100_cs_packet_next_reloc(p, &reloc);
1159 if (r) {
1160 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1161 idx, reg);
1162 r100_cs_dump_packet(p, pkt);
1163 return r;
1164 }
1165 track->textures[0].cube_info[i].offset = ib_chunk->kdata[idx];
1166 ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
1167 track->textures[0].cube_info[i].robj = reloc->robj;
1168 break;
1169 case RADEON_PP_CUBIC_OFFSET_T1_0:
1170 case RADEON_PP_CUBIC_OFFSET_T1_1:
1171 case RADEON_PP_CUBIC_OFFSET_T1_2:
1172 case RADEON_PP_CUBIC_OFFSET_T1_3:
1173 case RADEON_PP_CUBIC_OFFSET_T1_4:
1174 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
1175 r = r100_cs_packet_next_reloc(p, &reloc);
1176 if (r) {
1177 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1178 idx, reg);
1179 r100_cs_dump_packet(p, pkt);
1180 return r;
1181 }
1182 track->textures[1].cube_info[i].offset = ib_chunk->kdata[idx];
1183 ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
1184 track->textures[1].cube_info[i].robj = reloc->robj;
1185 break;
1186 case RADEON_PP_CUBIC_OFFSET_T2_0:
1187 case RADEON_PP_CUBIC_OFFSET_T2_1:
1188 case RADEON_PP_CUBIC_OFFSET_T2_2:
1189 case RADEON_PP_CUBIC_OFFSET_T2_3:
1190 case RADEON_PP_CUBIC_OFFSET_T2_4:
1191 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
1192 r = r100_cs_packet_next_reloc(p, &reloc);
1193 if (r) {
1194 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1195 idx, reg);
1196 r100_cs_dump_packet(p, pkt);
1197 return r;
1198 }
1199 track->textures[2].cube_info[i].offset = ib_chunk->kdata[idx];
1200 ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
1201 track->textures[2].cube_info[i].robj = reloc->robj;
1202 break;
1203 case RADEON_RE_WIDTH_HEIGHT:
1204 track->maxy = ((ib_chunk->kdata[idx] >> 16) & 0x7FF);
1205 break;
1206 case RADEON_RB3D_COLORPITCH:
1207 r = r100_cs_packet_next_reloc(p, &reloc);
1208 if (r) {
1209 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1210 idx, reg);
1211 r100_cs_dump_packet(p, pkt);
1212 return r;
1213 }
e024e110 1214
551ebd83
DA		 1215 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1216 tile_flags |= RADEON_COLOR_TILE_ENABLE;
1217 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1218 tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
e024e110 1219
551ebd83
DA		 1220 tmp = ib_chunk->kdata[idx] & ~(0x7 << 16);
1221 tmp |= tile_flags;
1222 ib[idx] = tmp;
e024e110 1223
551ebd83
DA		 1224 track->cb[0].pitch = ib_chunk->kdata[idx] & RADEON_COLORPITCH_MASK;
1225 break;
1226 case RADEON_RB3D_DEPTHPITCH:
1227 track->zb.pitch = ib_chunk->kdata[idx] & RADEON_DEPTHPITCH_MASK;
1228 break;
1229 case RADEON_RB3D_CNTL:
1230 switch ((ib_chunk->kdata[idx] >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
1231 case 7:
1232 case 8:
1233 case 9:
1234 case 11:
1235 case 12:
1236 track->cb[0].cpp = 1;
e024e110 1237 break;
551ebd83
DA		 1238 case 3:
1239 case 4:
1240 case 15:
1241 track->cb[0].cpp = 2;
1242 break;
1243 case 6:
1244 track->cb[0].cpp = 4;
1245 break;
1246 default:
1247 DRM_ERROR("Invalid color buffer format (%d) !\n",
1248 ((ib_chunk->kdata[idx] >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
1249 return -EINVAL;
1250 }
1251 track->z_enabled = !!(ib_chunk->kdata[idx] & RADEON_Z_ENABLE);
1252 break;
1253 case RADEON_RB3D_ZSTENCILCNTL:
1254 switch (ib_chunk->kdata[idx] & 0xf) {
1255 case 0:
1256 track->zb.cpp = 2;
1257 break;
1258 case 2:
1259 case 3:
1260 case 4:
1261 case 5:
1262 case 9:
1263 case 11:
1264 track->zb.cpp = 4;
17782d99 1265 break;
771fe6b9 1266 default:
771fe6b9
JG		 1267 break;
1268 }
551ebd83
DA		 1269 break;
1270 case RADEON_RB3D_ZPASS_ADDR:
1271 r = r100_cs_packet_next_reloc(p, &reloc);
1272 if (r) {
1273 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1274 idx, reg);
1275 r100_cs_dump_packet(p, pkt);
1276 return r;
1277 }
1278 ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
1279 break;
1280 case RADEON_PP_CNTL:
1281 {
1282 uint32_t temp = ib_chunk->kdata[idx] >> 4;
1283 for (i = 0; i < track->num_texture; i++)
1284 track->textures[i].enabled = !!(temp & (1 << i));
1285 }
1286 break;
1287 case RADEON_SE_VF_CNTL:
1288 track->vap_vf_cntl = ib_chunk->kdata[idx];
1289 break;
1290 case RADEON_SE_VTX_FMT:
1291 track->vtx_size = r100_get_vtx_size(ib_chunk->kdata[idx]);
1292 break;
1293 case RADEON_PP_TEX_SIZE_0:
1294 case RADEON_PP_TEX_SIZE_1:
1295 case RADEON_PP_TEX_SIZE_2:
1296 i = (reg - RADEON_PP_TEX_SIZE_0) / 8;
1297 track->textures[i].width = (ib_chunk->kdata[idx] & RADEON_TEX_USIZE_MASK) + 1;
1298 track->textures[i].height = ((ib_chunk->kdata[idx] & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
1299 break;
1300 case RADEON_PP_TEX_PITCH_0:
1301 case RADEON_PP_TEX_PITCH_1:
1302 case RADEON_PP_TEX_PITCH_2:
1303 i = (reg - RADEON_PP_TEX_PITCH_0) / 8;
1304 track->textures[i].pitch = ib_chunk->kdata[idx] + 32;
1305 break;
1306 case RADEON_PP_TXFILTER_0:
1307 case RADEON_PP_TXFILTER_1:
1308 case RADEON_PP_TXFILTER_2:
1309 i = (reg - RADEON_PP_TXFILTER_0) / 24;
1310 track->textures[i].num_levels = ((ib_chunk->kdata[idx] & RADEON_MAX_MIP_LEVEL_MASK)
1311 >> RADEON_MAX_MIP_LEVEL_SHIFT);
1312 tmp = (ib_chunk->kdata[idx] >> 23) & 0x7;
1313 if (tmp == 2 || tmp == 6)
1314 track->textures[i].roundup_w = false;
1315 tmp = (ib_chunk->kdata[idx] >> 27) & 0x7;
1316 if (tmp == 2 || tmp == 6)
1317 track->textures[i].roundup_h = false;
1318 break;
1319 case RADEON_PP_TXFORMAT_0:
1320 case RADEON_PP_TXFORMAT_1:
1321 case RADEON_PP_TXFORMAT_2:
1322 i = (reg - RADEON_PP_TXFORMAT_0) / 24;
1323 if (ib_chunk->kdata[idx] & RADEON_TXFORMAT_NON_POWER2) {
1324 track->textures[i].use_pitch = 1;
1325 } else {
1326 track->textures[i].use_pitch = 0;
1327 track->textures[i].width = 1 << ((ib_chunk->kdata[idx] >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
1328 track->textures[i].height = 1 << ((ib_chunk->kdata[idx] >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
1329 }
1330 if (ib_chunk->kdata[idx] & RADEON_TXFORMAT_CUBIC_MAP_ENABLE)
1331 track->textures[i].tex_coord_type = 2;
1332 switch ((ib_chunk->kdata[idx] & RADEON_TXFORMAT_FORMAT_MASK)) {
1333 case RADEON_TXFORMAT_I8:
1334 case RADEON_TXFORMAT_RGB332:
1335 case RADEON_TXFORMAT_Y8:
1336 track->textures[i].cpp = 1;
1337 break;
1338 case RADEON_TXFORMAT_AI88:
1339 case RADEON_TXFORMAT_ARGB1555:
1340 case RADEON_TXFORMAT_RGB565:
1341 case RADEON_TXFORMAT_ARGB4444:
1342 case RADEON_TXFORMAT_VYUY422:
1343 case RADEON_TXFORMAT_YVYU422:
1344 case RADEON_TXFORMAT_DXT1:
1345 case RADEON_TXFORMAT_SHADOW16:
1346 case RADEON_TXFORMAT_LDUDV655:
1347 case RADEON_TXFORMAT_DUDV88:
1348 track->textures[i].cpp = 2;
771fe6b9 1349 break;
551ebd83
DA		 1350 case RADEON_TXFORMAT_ARGB8888:
1351 case RADEON_TXFORMAT_RGBA8888:
1352 case RADEON_TXFORMAT_DXT23:
1353 case RADEON_TXFORMAT_DXT45:
1354 case RADEON_TXFORMAT_SHADOW32:
1355 case RADEON_TXFORMAT_LDUDUV8888:
1356 track->textures[i].cpp = 4;
1357 break;
1358 }
1359 track->textures[i].cube_info[4].width = 1 << ((ib_chunk->kdata[idx] >> 16) & 0xf);
1360 track->textures[i].cube_info[4].height = 1 << ((ib_chunk->kdata[idx] >> 20) & 0xf);
1361 break;
1362 case RADEON_PP_CUBIC_FACES_0:
1363 case RADEON_PP_CUBIC_FACES_1:
1364 case RADEON_PP_CUBIC_FACES_2:
1365 tmp = ib_chunk->kdata[idx];
1366 i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;
1367 for (face = 0; face < 4; face++) {
1368 track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
1369 track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
771fe6b9 1370 }
551ebd83
DA		 1371 break;
1372 default:
1373 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1374 reg, idx);
1375 return -EINVAL;
771fe6b9
JG		 1376 }
1377 return 0;
1378}
1379
068a117c
JG		 1380int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1381 struct radeon_cs_packet *pkt,
1382 struct radeon_object *robj)
1383{
1384 struct radeon_cs_chunk *ib_chunk;
1385 unsigned idx;
1386
1387 ib_chunk = &p->chunks[p->chunk_ib_idx];
1388 idx = pkt->idx + 1;
1389 if ((ib_chunk->kdata[idx+2] + 1) > radeon_object_size(robj)) {
1390 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
1391 "(need %u have %lu) !\n",
1392 ib_chunk->kdata[idx+2] + 1,
1393 radeon_object_size(robj));
1394 return -EINVAL;
1395 }
1396 return 0;
1397}
1398
771fe6b9
JG		 1399static int r100_packet3_check(struct radeon_cs_parser *p,
1400 struct radeon_cs_packet *pkt)
1401{
1402 struct radeon_cs_chunk *ib_chunk;
1403 struct radeon_cs_reloc *reloc;
551ebd83 1404 struct r100_cs_track *track;
771fe6b9
JG		 1405 unsigned idx;
1406 unsigned i, c;
1407 volatile uint32_t *ib;
1408 int r;
1409
1410 ib = p->ib->ptr;
1411 ib_chunk = &p->chunks[p->chunk_ib_idx];
1412 idx = pkt->idx + 1;
551ebd83 1413 track = (struct r100_cs_track *)p->track;
771fe6b9
JG		 1414 switch (pkt->opcode) {
1415 case PACKET3_3D_LOAD_VBPNTR:
1416 c = ib_chunk->kdata[idx++];
551ebd83 1417 track->num_arrays = c;
771fe6b9
JG		 1418 for (i = 0; i < (c - 1); i += 2, idx += 3) {
1419 r = r100_cs_packet_next_reloc(p, &reloc);
1420 if (r) {
1421 DRM_ERROR("No reloc for packet3 %d\n",
1422 pkt->opcode);
1423 r100_cs_dump_packet(p, pkt);
1424 return r;
1425 }
1426 ib[idx+1] = ib_chunk->kdata[idx+1] + ((u32)reloc->lobj.gpu_offset);
551ebd83
DA		 1427 track->arrays[i + 0].robj = reloc->robj;
1428 track->arrays[i + 0].esize = ib_chunk->kdata[idx] >> 8;
1429 track->arrays[i + 0].esize &= 0x7F;
771fe6b9
JG		 1430 r = r100_cs_packet_next_reloc(p, &reloc);
1431 if (r) {
1432 DRM_ERROR("No reloc for packet3 %d\n",
1433 pkt->opcode);
1434 r100_cs_dump_packet(p, pkt);
1435 return r;
1436 }
1437 ib[idx+2] = ib_chunk->kdata[idx+2] + ((u32)reloc->lobj.gpu_offset);
551ebd83
DA		 1438 track->arrays[i + 1].robj = reloc->robj;
1439 track->arrays[i + 1].esize = ib_chunk->kdata[idx] >> 24;
1440 track->arrays[i + 1].esize &= 0x7F;
771fe6b9
JG		 1441 }
1442 if (c & 1) {
1443 r = r100_cs_packet_next_reloc(p, &reloc);
1444 if (r) {
1445 DRM_ERROR("No reloc for packet3 %d\n",
1446 pkt->opcode);
1447 r100_cs_dump_packet(p, pkt);
1448 return r;
1449 }
1450 ib[idx+1] = ib_chunk->kdata[idx+1] + ((u32)reloc->lobj.gpu_offset);
551ebd83
DA		 1451 track->arrays[i + 0].robj = reloc->robj;
1452 track->arrays[i + 0].esize = ib_chunk->kdata[idx] >> 8;
1453 track->arrays[i + 0].esize &= 0x7F;
771fe6b9
JG		 1454 }
1455 break;
1456 case PACKET3_INDX_BUFFER:
1457 r = r100_cs_packet_next_reloc(p, &reloc);
1458 if (r) {
1459 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1460 r100_cs_dump_packet(p, pkt);
1461 return r;
1462 }
1463 ib[idx+1] = ib_chunk->kdata[idx+1] + ((u32)reloc->lobj.gpu_offset);
068a117c
JG		 1464 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1465 if (r) {
1466 return r;
1467 }
771fe6b9
JG		 1468 break;
1469 case 0x23:
771fe6b9
JG		 1470 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
1471 r = r100_cs_packet_next_reloc(p, &reloc);
1472 if (r) {
1473 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1474 r100_cs_dump_packet(p, pkt);
1475 return r;
1476 }
1477 ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
551ebd83
DA		 1478 track->num_arrays = 1;
1479 track->vtx_size = r100_get_vtx_size(ib_chunk->kdata[idx+2]);
1480
1481 track->arrays[0].robj = reloc->robj;
1482 track->arrays[0].esize = track->vtx_size;
1483
1484 track->max_indx = ib_chunk->kdata[idx+1];
1485
1486 track->vap_vf_cntl = ib_chunk->kdata[idx+3];
1487 track->immd_dwords = pkt->count - 1;
1488 r = r100_cs_track_check(p->rdev, track);
1489 if (r)
1490 return r;
771fe6b9
JG		 1491 break;
1492 case PACKET3_3D_DRAW_IMMD:
551ebd83
DA		 1493 if (((ib_chunk->kdata[idx+1] >> 4) & 0x3) != 3) {
1494 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1495 return -EINVAL;
1496 }
1497 track->vap_vf_cntl = ib_chunk->kdata[idx+1];
1498 track->immd_dwords = pkt->count - 1;
1499 r = r100_cs_track_check(p->rdev, track);
1500 if (r)
1501 return r;
1502 break;
771fe6b9
JG		 1503 /* triggers drawing using in-packet vertex data */
1504 case PACKET3_3D_DRAW_IMMD_2:
551ebd83
DA		 1505 if (((ib_chunk->kdata[idx] >> 4) & 0x3) != 3) {
1506 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1507 return -EINVAL;
1508 }
1509 track->vap_vf_cntl = ib_chunk->kdata[idx];
1510 track->immd_dwords = pkt->count;
1511 r = r100_cs_track_check(p->rdev, track);
1512 if (r)
1513 return r;
1514 break;
771fe6b9
JG		 1515 /* triggers drawing using in-packet vertex data */
1516 case PACKET3_3D_DRAW_VBUF_2:
551ebd83
DA		 1517 track->vap_vf_cntl = ib_chunk->kdata[idx];
1518 r = r100_cs_track_check(p->rdev, track);
1519 if (r)
1520 return r;
1521 break;
771fe6b9
JG		 1522 /* triggers drawing of vertex buffers setup elsewhere */
1523 case PACKET3_3D_DRAW_INDX_2:
551ebd83
DA		 1524 track->vap_vf_cntl = ib_chunk->kdata[idx];
1525 r = r100_cs_track_check(p->rdev, track);
1526 if (r)
1527 return r;
1528 break;
771fe6b9
JG		 1529 /* triggers drawing using indices to vertex buffer */
1530 case PACKET3_3D_DRAW_VBUF:
551ebd83
DA		 1531 track->vap_vf_cntl = ib_chunk->kdata[idx + 1];
1532 r = r100_cs_track_check(p->rdev, track);
1533 if (r)
1534 return r;
1535 break;
771fe6b9
JG		 1536 /* triggers drawing of vertex buffers setup elsewhere */
1537 case PACKET3_3D_DRAW_INDX:
551ebd83
DA		 1538 track->vap_vf_cntl = ib_chunk->kdata[idx + 1];
1539 r = r100_cs_track_check(p->rdev, track);
1540 if (r)
1541 return r;
1542 break;
771fe6b9
JG		 1543 /* triggers drawing using indices to vertex buffer */
1544 case PACKET3_NOP:
1545 break;
1546 default:
1547 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1548 return -EINVAL;
1549 }
1550 return 0;
1551}
1552
1553int r100_cs_parse(struct radeon_cs_parser *p)
1554{
1555 struct radeon_cs_packet pkt;
551ebd83 1556 struct r100_cs_track track;
771fe6b9
JG		 1557 int r;
1558
551ebd83
DA		 1559 r100_cs_track_clear(p->rdev, &track);
1560 p->track = &track;
771fe6b9
JG		 1561 do {
1562 r = r100_cs_packet_parse(p, &pkt, p->idx);
1563 if (r) {
1564 return r;
1565 }
1566 p->idx += pkt.count + 2;
1567 switch (pkt.type) {
068a117c 1568 case PACKET_TYPE0:
551ebd83
DA		 1569 if (p->rdev->family >= CHIP_R200)
1570 r = r100_cs_parse_packet0(p, &pkt,
1571 p->rdev->config.r100.reg_safe_bm,
1572 p->rdev->config.r100.reg_safe_bm_size,
1573 &r200_packet0_check);
1574 else
1575 r = r100_cs_parse_packet0(p, &pkt,
1576 p->rdev->config.r100.reg_safe_bm,
1577 p->rdev->config.r100.reg_safe_bm_size,
1578 &r100_packet0_check);
068a117c
JG		 1579 break;
1580 case PACKET_TYPE2:
1581 break;
1582 case PACKET_TYPE3:
1583 r = r100_packet3_check(p, &pkt);
1584 break;
1585 default:
1586 DRM_ERROR("Unknown packet type %d !\n",
1587 pkt.type);
1588 return -EINVAL;
771fe6b9
JG		 1589 }
1590 if (r) {
1591 return r;
1592 }
1593 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
1594 return 0;
1595}
1596
1597
1598/*
1599 * Global GPU functions
1600 */
1601void r100_errata(struct radeon_device *rdev)
1602{
1603 rdev->pll_errata = 0;
1604
1605 if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) {
1606 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS;
1607 }
1608
1609 if (rdev->family == CHIP_RV100 ||
1610 rdev->family == CHIP_RS100 ||
1611 rdev->family == CHIP_RS200) {
1612 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY;
1613 }
1614}
1615
1616/* Wait for vertical sync on primary CRTC */
1617void r100_gpu_wait_for_vsync(struct radeon_device *rdev)
1618{
1619 uint32_t crtc_gen_cntl, tmp;
1620 int i;
1621
1622 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
1623 if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) ||
1624 !(crtc_gen_cntl & RADEON_CRTC_EN)) {
1625 return;
1626 }
1627 /* Clear the CRTC_VBLANK_SAVE bit */
1628 WREG32(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR);
1629 for (i = 0; i < rdev->usec_timeout; i++) {
1630 tmp = RREG32(RADEON_CRTC_STATUS);
1631 if (tmp & RADEON_CRTC_VBLANK_SAVE) {
1632 return;
1633 }
1634 DRM_UDELAY(1);
1635 }
1636}
1637
1638/* Wait for vertical sync on secondary CRTC */
1639void r100_gpu_wait_for_vsync2(struct radeon_device *rdev)
1640{
1641 uint32_t crtc2_gen_cntl, tmp;
1642 int i;
1643
1644 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1645 if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) ||
1646 !(crtc2_gen_cntl & RADEON_CRTC2_EN))
1647 return;
1648
1649 /* Clear the CRTC_VBLANK_SAVE bit */
1650 WREG32(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR);
1651 for (i = 0; i < rdev->usec_timeout; i++) {
1652 tmp = RREG32(RADEON_CRTC2_STATUS);
1653 if (tmp & RADEON_CRTC2_VBLANK_SAVE) {
1654 return;
1655 }
1656 DRM_UDELAY(1);
1657 }
1658}
1659
1660int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
1661{
1662 unsigned i;
1663 uint32_t tmp;
1664
1665 for (i = 0; i < rdev->usec_timeout; i++) {
1666 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
1667 if (tmp >= n) {
1668 return 0;
1669 }
1670 DRM_UDELAY(1);
1671 }
1672 return -1;
1673}
1674
1675int r100_gui_wait_for_idle(struct radeon_device *rdev)
1676{
1677 unsigned i;
1678 uint32_t tmp;
1679
1680 if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
1681 printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !"
1682 " Bad things might happen.\n");
1683 }
1684 for (i = 0; i < rdev->usec_timeout; i++) {
1685 tmp = RREG32(RADEON_RBBM_STATUS);
1686 if (!(tmp & (1 << 31))) {
1687 return 0;
1688 }
1689 DRM_UDELAY(1);
1690 }
1691 return -1;
1692}
1693
1694int r100_mc_wait_for_idle(struct radeon_device *rdev)
1695{
1696 unsigned i;
1697 uint32_t tmp;
1698
1699 for (i = 0; i < rdev->usec_timeout; i++) {
1700 /* read MC_STATUS */
1701 tmp = RREG32(0x0150);
1702 if (tmp & (1 << 2)) {
1703 return 0;
1704 }
1705 DRM_UDELAY(1);
1706 }
1707 return -1;
1708}
1709
1710void r100_gpu_init(struct radeon_device *rdev)
1711{
1712 /* TODO: anythings to do here ? pipes ? */
1713 r100_hdp_reset(rdev);
1714}
1715
1716void r100_hdp_reset(struct radeon_device *rdev)
1717{
1718 uint32_t tmp;
1719
1720 tmp = RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL;
1721 tmp |= (7 << 28);
1722 WREG32(RADEON_HOST_PATH_CNTL, tmp | RADEON_HDP_SOFT_RESET | RADEON_HDP_READ_BUFFER_INVALIDATE);
1723 (void)RREG32(RADEON_HOST_PATH_CNTL);
1724 udelay(200);
1725 WREG32(RADEON_RBBM_SOFT_RESET, 0);
1726 WREG32(RADEON_HOST_PATH_CNTL, tmp);
1727 (void)RREG32(RADEON_HOST_PATH_CNTL);
1728}
1729
1730int r100_rb2d_reset(struct radeon_device *rdev)
1731{
1732 uint32_t tmp;
1733 int i;
1734
1735 WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_E2);
1736 (void)RREG32(RADEON_RBBM_SOFT_RESET);
1737 udelay(200);
1738 WREG32(RADEON_RBBM_SOFT_RESET, 0);
1739 /* Wait to prevent race in RBBM_STATUS */
1740 mdelay(1);
1741 for (i = 0; i < rdev->usec_timeout; i++) {
1742 tmp = RREG32(RADEON_RBBM_STATUS);
1743 if (!(tmp & (1 << 26))) {
1744 DRM_INFO("RB2D reset succeed (RBBM_STATUS=0x%08X)\n",
1745 tmp);
1746 return 0;
1747 }
1748 DRM_UDELAY(1);
1749 }
1750 tmp = RREG32(RADEON_RBBM_STATUS);
1751 DRM_ERROR("Failed to reset RB2D (RBBM_STATUS=0x%08X)!\n", tmp);
1752 return -1;
1753}
1754
1755int r100_gpu_reset(struct radeon_device *rdev)
1756{
1757 uint32_t status;
1758
1759 /* reset order likely matter */
1760 status = RREG32(RADEON_RBBM_STATUS);
1761 /* reset HDP */
1762 r100_hdp_reset(rdev);
1763 /* reset rb2d */
1764 if (status & ((1 << 17) | (1 << 18) | (1 << 27))) {
1765 r100_rb2d_reset(rdev);
1766 }
1767 /* TODO: reset 3D engine */
1768 /* reset CP */
1769 status = RREG32(RADEON_RBBM_STATUS);
1770 if (status & (1 << 16)) {
1771 r100_cp_reset(rdev);
1772 }
1773 /* Check if GPU is idle */
1774 status = RREG32(RADEON_RBBM_STATUS);
1775 if (status & (1 << 31)) {
1776 DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status);
1777 return -1;
1778 }
1779 DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status);
1780 return 0;
1781}
1782
1783
1784/*
1785 * VRAM info
1786 */
1787static void r100_vram_get_type(struct radeon_device *rdev)
1788{
1789 uint32_t tmp;
1790
1791 rdev->mc.vram_is_ddr = false;
1792 if (rdev->flags & RADEON_IS_IGP)
1793 rdev->mc.vram_is_ddr = true;
1794 else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
1795 rdev->mc.vram_is_ddr = true;
1796 if ((rdev->family == CHIP_RV100) ||
1797 (rdev->family == CHIP_RS100) ||
1798 (rdev->family == CHIP_RS200)) {
1799 tmp = RREG32(RADEON_MEM_CNTL);
1800 if (tmp & RV100_HALF_MODE) {
1801 rdev->mc.vram_width = 32;
1802 } else {
1803 rdev->mc.vram_width = 64;
1804 }
1805 if (rdev->flags & RADEON_SINGLE_CRTC) {
1806 rdev->mc.vram_width /= 4;
1807 rdev->mc.vram_is_ddr = true;
1808 }
1809 } else if (rdev->family <= CHIP_RV280) {
1810 tmp = RREG32(RADEON_MEM_CNTL);
1811 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
1812 rdev->mc.vram_width = 128;
1813 } else {
1814 rdev->mc.vram_width = 64;
1815 }
1816 } else {
1817 /* newer IGPs */
1818 rdev->mc.vram_width = 128;
1819 }
1820}
1821
2a0f8918 1822static u32 r100_get_accessible_vram(struct radeon_device *rdev)
771fe6b9 1823{
2a0f8918
DA		 1824 u32 aper_size;
1825 u8 byte;
1826
1827 aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
1828
1829 /* Set HDP_APER_CNTL only on cards that are known not to be broken,
1830 * that is has the 2nd generation multifunction PCI interface
1831 */
1832 if (rdev->family == CHIP_RV280 ||
1833 rdev->family >= CHIP_RV350) {
1834 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
1835 ~RADEON_HDP_APER_CNTL);
1836 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
1837 return aper_size * 2;
1838 }
1839
1840 /* Older cards have all sorts of funny issues to deal with. First
1841 * check if it's a multifunction card by reading the PCI config
1842 * header type... Limit those to one aperture size
1843 */
1844 pci_read_config_byte(rdev->pdev, 0xe, &byte);
1845 if (byte & 0x80) {
1846 DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
1847 DRM_INFO("Limiting VRAM to one aperture\n");
1848 return aper_size;
1849 }
1850
1851 /* Single function older card. We read HDP_APER_CNTL to see how the BIOS
1852 * have set it up. We don't write this as it's broken on some ASICs but
1853 * we expect the BIOS to have done the right thing (might be too optimistic...)
1854 */
1855 if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
1856 return aper_size * 2;
1857 return aper_size;
1858}
1859
1860void r100_vram_init_sizes(struct radeon_device *rdev)
1861{
1862 u64 config_aper_size;
1863 u32 accessible;
1864
1865 config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
771fe6b9
JG		 1866
1867 if (rdev->flags & RADEON_IS_IGP) {
1868 uint32_t tom;
1869 /* read NB_TOM to get the amount of ram stolen for the GPU */
1870 tom = RREG32(RADEON_NB_TOM);
7a50f01a 1871 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
3e43d821
DA		 1872 /* for IGPs we need to keep VRAM where it was put by the BIOS */
1873 rdev->mc.vram_location = (tom & 0xffff) << 16;
7a50f01a
DA		 1874 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
1875 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
771fe6b9 1876 } else {
7a50f01a 1877 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
771fe6b9
JG		 1878 /* Some production boards of m6 will report 0
1879 * if it's 8 MB
1880 */
7a50f01a
DA		 1881 if (rdev->mc.real_vram_size == 0) {
1882 rdev->mc.real_vram_size = 8192 * 1024;
1883 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
771fe6b9 1884 }
3e43d821
DA		 1885 /* let driver place VRAM */
1886 rdev->mc.vram_location = 0xFFFFFFFFUL;
2a0f8918
DA		 1887 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
1888 * Novell bug 204882 + along with lots of ubuntu ones */
7a50f01a
DA		 1889 if (config_aper_size > rdev->mc.real_vram_size)
1890 rdev->mc.mc_vram_size = config_aper_size;
1891 else
1892 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
771fe6b9
JG		 1893 }
1894
2a0f8918
DA		 1895 /* work out accessible VRAM */
1896 accessible = r100_get_accessible_vram(rdev);
1897
771fe6b9
JG		 1898 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
1899 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
2a0f8918
DA		 1900
1901 if (accessible > rdev->mc.aper_size)
1902 accessible = rdev->mc.aper_size;
1903
7a50f01a
DA		 1904 if (rdev->mc.mc_vram_size > rdev->mc.aper_size)
1905 rdev->mc.mc_vram_size = rdev->mc.aper_size;
1906
1907 if (rdev->mc.real_vram_size > rdev->mc.aper_size)
1908 rdev->mc.real_vram_size = rdev->mc.aper_size;
2a0f8918
DA		 1909}
1910
1911void r100_vram_info(struct radeon_device *rdev)
1912{
1913 r100_vram_get_type(rdev);
1914
1915 r100_vram_init_sizes(rdev);
771fe6b9
JG		 1916}
1917
1918
1919/*
1920 * Indirect registers accessor
1921 */
1922void r100_pll_errata_after_index(struct radeon_device *rdev)
1923{
1924 if (!(rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS)) {
1925 return;
1926 }
1927 (void)RREG32(RADEON_CLOCK_CNTL_DATA);
1928 (void)RREG32(RADEON_CRTC_GEN_CNTL);
1929}
1930
1931static void r100_pll_errata_after_data(struct radeon_device *rdev)
1932{
1933 /* This workarounds is necessary on RV100, RS100 and RS200 chips
1934 * or the chip could hang on a subsequent access
1935 */
1936 if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
1937 udelay(5000);
1938 }
1939
1940 /* This function is required to workaround a hardware bug in some (all?)
1941 * revisions of the R300. This workaround should be called after every
1942 * CLOCK_CNTL_INDEX register access. If not, register reads afterward
1943 * may not be correct.
1944 */
1945 if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
1946 uint32_t save, tmp;
1947
1948 save = RREG32(RADEON_CLOCK_CNTL_INDEX);
1949 tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
1950 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
1951 tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
1952 WREG32(RADEON_CLOCK_CNTL_INDEX, save);
1953 }
1954}
1955
1956uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
1957{
1958 uint32_t data;
1959
1960 WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
1961 r100_pll_errata_after_index(rdev);
1962 data = RREG32(RADEON_CLOCK_CNTL_DATA);
1963 r100_pll_errata_after_data(rdev);
1964 return data;
1965}
1966
1967void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1968{
1969 WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN));
1970 r100_pll_errata_after_index(rdev);
1971 WREG32(RADEON_CLOCK_CNTL_DATA, v);
1972 r100_pll_errata_after_data(rdev);
1973}
1974
068a117c
JG		 1975int r100_init(struct radeon_device *rdev)
1976{
551ebd83
DA		 1977 if (ASIC_IS_RN50(rdev)) {
1978 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
1979 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
1980 } else if (rdev->family < CHIP_R200) {
1981 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
1982 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
1983 } else {
1984 return r200_init(rdev);
1985 }
068a117c
JG		 1986 return 0;
1987}
1988
771fe6b9
JG		 1989/*
1990 * Debugfs info
1991 */
1992#if defined(CONFIG_DEBUG_FS)
1993static int r100_debugfs_rbbm_info(struct seq_file *m, void *data)
1994{
1995 struct drm_info_node *node = (struct drm_info_node *) m->private;
1996 struct drm_device *dev = node->minor->dev;
1997 struct radeon_device *rdev = dev->dev_private;
1998 uint32_t reg, value;
1999 unsigned i;
2000
2001 seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
2002 seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
2003 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2004 for (i = 0; i < 64; i++) {
2005 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100);
2006 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
2007 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
2008 value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
2009 seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
2010 }
2011 return 0;
2012}
2013
2014static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data)
2015{
2016 struct drm_info_node *node = (struct drm_info_node *) m->private;
2017 struct drm_device *dev = node->minor->dev;
2018 struct radeon_device *rdev = dev->dev_private;
2019 uint32_t rdp, wdp;
2020 unsigned count, i, j;
2021
2022 radeon_ring_free_size(rdev);
2023 rdp = RREG32(RADEON_CP_RB_RPTR);
2024 wdp = RREG32(RADEON_CP_RB_WPTR);
2025 count = (rdp + rdev->cp.ring_size - wdp) & rdev->cp.ptr_mask;
2026 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2027 seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
2028 seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
2029 seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
2030 seq_printf(m, "%u dwords in ring\n", count);
2031 for (j = 0; j <= count; j++) {
2032 i = (rdp + j) & rdev->cp.ptr_mask;
2033 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
2034 }
2035 return 0;
2036}
2037
2038
2039static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data)
2040{
2041 struct drm_info_node *node = (struct drm_info_node *) m->private;
2042 struct drm_device *dev = node->minor->dev;
2043 struct radeon_device *rdev = dev->dev_private;
2044 uint32_t csq_stat, csq2_stat, tmp;
2045 unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
2046 unsigned i;
2047
2048 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2049 seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
2050 csq_stat = RREG32(RADEON_CP_CSQ_STAT);
2051 csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
2052 r_rptr = (csq_stat >> 0) & 0x3ff;
2053 r_wptr = (csq_stat >> 10) & 0x3ff;
2054 ib1_rptr = (csq_stat >> 20) & 0x3ff;
2055 ib1_wptr = (csq2_stat >> 0) & 0x3ff;
2056 ib2_rptr = (csq2_stat >> 10) & 0x3ff;
2057 ib2_wptr = (csq2_stat >> 20) & 0x3ff;
2058 seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
2059 seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
2060 seq_printf(m, "Ring rptr %u\n", r_rptr);
2061 seq_printf(m, "Ring wptr %u\n", r_wptr);
2062 seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
2063 seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
2064 seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
2065 seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
2066 /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
2067 * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
2068 seq_printf(m, "Ring fifo:\n");
2069 for (i = 0; i < 256; i++) {
2070 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2071 tmp = RREG32(RADEON_CP_CSQ_DATA);
2072 seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
2073 }
2074 seq_printf(m, "Indirect1 fifo:\n");
2075 for (i = 256; i <= 512; i++) {
2076 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2077 tmp = RREG32(RADEON_CP_CSQ_DATA);
2078 seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
2079 }
2080 seq_printf(m, "Indirect2 fifo:\n");
2081 for (i = 640; i < ib1_wptr; i++) {
2082 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2083 tmp = RREG32(RADEON_CP_CSQ_DATA);
2084 seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
2085 }
2086 return 0;
2087}
2088
2089static int r100_debugfs_mc_info(struct seq_file *m, void *data)
2090{
2091 struct drm_info_node *node = (struct drm_info_node *) m->private;
2092 struct drm_device *dev = node->minor->dev;
2093 struct radeon_device *rdev = dev->dev_private;
2094 uint32_t tmp;
2095
2096 tmp = RREG32(RADEON_CONFIG_MEMSIZE);
2097 seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
2098 tmp = RREG32(RADEON_MC_FB_LOCATION);
2099 seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
2100 tmp = RREG32(RADEON_BUS_CNTL);
2101 seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
2102 tmp = RREG32(RADEON_MC_AGP_LOCATION);
2103 seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
2104 tmp = RREG32(RADEON_AGP_BASE);
2105 seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
2106 tmp = RREG32(RADEON_HOST_PATH_CNTL);
2107 seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
2108 tmp = RREG32(0x01D0);
2109 seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
2110 tmp = RREG32(RADEON_AIC_LO_ADDR);
2111 seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
2112 tmp = RREG32(RADEON_AIC_HI_ADDR);
2113 seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
2114 tmp = RREG32(0x01E4);
2115 seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
2116 return 0;
2117}
2118
2119static struct drm_info_list r100_debugfs_rbbm_list[] = {
2120 {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL},
2121};
2122
2123static struct drm_info_list r100_debugfs_cp_list[] = {
2124 {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL},
2125 {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL},
2126};
2127
2128static struct drm_info_list r100_debugfs_mc_info_list[] = {
2129 {"r100_mc_info", r100_debugfs_mc_info, 0, NULL},
2130};
2131#endif
2132
2133int r100_debugfs_rbbm_init(struct radeon_device *rdev)
2134{
2135#if defined(CONFIG_DEBUG_FS)
2136 return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1);
2137#else
2138 return 0;
2139#endif
2140}
2141
2142int r100_debugfs_cp_init(struct radeon_device *rdev)
2143{
2144#if defined(CONFIG_DEBUG_FS)
2145 return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2);
2146#else
2147 return 0;
2148#endif
2149}
2150
2151int r100_debugfs_mc_info_init(struct radeon_device *rdev)
2152{
2153#if defined(CONFIG_DEBUG_FS)
2154 return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1);
2155#else
2156 return 0;
2157#endif
2158}
e024e110
DA		 2159
2160int r100_set_surface_reg(struct radeon_device *rdev, int reg,
2161 uint32_t tiling_flags, uint32_t pitch,
2162 uint32_t offset, uint32_t obj_size)
2163{
2164 int surf_index = reg * 16;
2165 int flags = 0;
2166
2167 /* r100/r200 divide by 16 */
2168 if (rdev->family < CHIP_R300)
2169 flags = pitch / 16;
2170 else
2171 flags = pitch / 8;
2172
2173 if (rdev->family <= CHIP_RS200) {
2174 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2175 == (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2176 flags |= RADEON_SURF_TILE_COLOR_BOTH;
2177 if (tiling_flags & RADEON_TILING_MACRO)
2178 flags |= RADEON_SURF_TILE_COLOR_MACRO;
2179 } else if (rdev->family <= CHIP_RV280) {
2180 if (tiling_flags & (RADEON_TILING_MACRO))
2181 flags |= R200_SURF_TILE_COLOR_MACRO;
2182 if (tiling_flags & RADEON_TILING_MICRO)
2183 flags |= R200_SURF_TILE_COLOR_MICRO;
2184 } else {
2185 if (tiling_flags & RADEON_TILING_MACRO)
2186 flags |= R300_SURF_TILE_MACRO;
2187 if (tiling_flags & RADEON_TILING_MICRO)
2188 flags |= R300_SURF_TILE_MICRO;
2189 }
2190
2191 DRM_DEBUG("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
2192 WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
2193 WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
2194 WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);
2195 return 0;
2196}
2197
2198void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
2199{
2200 int surf_index = reg * 16;
2201 WREG32(RADEON_SURFACE0_INFO + surf_index, 0);
2202}
c93bb85b
JG		 2203
2204void r100_bandwidth_update(struct radeon_device *rdev)
2205{
2206 fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff;
2207 fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff;
2208 fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff;
2209 uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
2210 fixed20_12 memtcas_ff[8] = {
2211 fixed_init(1),
2212 fixed_init(2),
2213 fixed_init(3),
2214 fixed_init(0),
2215 fixed_init_half(1),
2216 fixed_init_half(2),
2217 fixed_init(0),
2218 };
2219 fixed20_12 memtcas_rs480_ff[8] = {
2220 fixed_init(0),
2221 fixed_init(1),
2222 fixed_init(2),
2223 fixed_init(3),
2224 fixed_init(0),
2225 fixed_init_half(1),
2226 fixed_init_half(2),
2227 fixed_init_half(3),
2228 };
2229 fixed20_12 memtcas2_ff[8] = {
2230 fixed_init(0),
2231 fixed_init(1),
2232 fixed_init(2),
2233 fixed_init(3),
2234 fixed_init(4),
2235 fixed_init(5),
2236 fixed_init(6),
2237 fixed_init(7),
2238 };
2239 fixed20_12 memtrbs[8] = {
2240 fixed_init(1),
2241 fixed_init_half(1),
2242 fixed_init(2),
2243 fixed_init_half(2),
2244 fixed_init(3),
2245 fixed_init_half(3),
2246 fixed_init(4),
2247 fixed_init_half(4)
2248 };
2249 fixed20_12 memtrbs_r4xx[8] = {
2250 fixed_init(4),
2251 fixed_init(5),
2252 fixed_init(6),
2253 fixed_init(7),
2254 fixed_init(8),
2255 fixed_init(9),
2256 fixed_init(10),
2257 fixed_init(11)
2258 };
2259 fixed20_12 min_mem_eff;
2260 fixed20_12 mc_latency_sclk, mc_latency_mclk, k1;
2261 fixed20_12 cur_latency_mclk, cur_latency_sclk;
2262 fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate,
2263 disp_drain_rate2, read_return_rate;
2264 fixed20_12 time_disp1_drop_priority;
2265 int c;
2266 int cur_size = 16; /* in octawords */
2267 int critical_point = 0, critical_point2;
2268/* uint32_t read_return_rate, time_disp1_drop_priority; */
2269 int stop_req, max_stop_req;
2270 struct drm_display_mode *mode1 = NULL;
2271 struct drm_display_mode *mode2 = NULL;
2272 uint32_t pixel_bytes1 = 0;
2273 uint32_t pixel_bytes2 = 0;
2274
2275 if (rdev->mode_info.crtcs[0]->base.enabled) {
2276 mode1 = &rdev->mode_info.crtcs[0]->base.mode;
2277 pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8;
2278 }
2279 if (rdev->mode_info.crtcs[1]->base.enabled) {
2280 mode2 = &rdev->mode_info.crtcs[1]->base.mode;
2281 pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8;
2282 }
2283
2284 min_mem_eff.full = rfixed_const_8(0);
2285 /* get modes */
2286 if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
2287 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);
2288 mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT);
2289 mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT);
2290 /* check crtc enables */
2291 if (mode2)
2292 mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
2293 if (mode1)
2294 mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
2295 WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
2296 }
2297
2298 /*
2299 * determine is there is enough bw for current mode
2300 */
2301 mclk_ff.full = rfixed_const(rdev->clock.default_mclk);
2302 temp_ff.full = rfixed_const(100);
2303 mclk_ff.full = rfixed_div(mclk_ff, temp_ff);
2304 sclk_ff.full = rfixed_const(rdev->clock.default_sclk);
2305 sclk_ff.full = rfixed_div(sclk_ff, temp_ff);
2306
2307 temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
2308 temp_ff.full = rfixed_const(temp);
2309 mem_bw.full = rfixed_mul(mclk_ff, temp_ff);
2310
2311 pix_clk.full = 0;
2312 pix_clk2.full = 0;
2313 peak_disp_bw.full = 0;
2314 if (mode1) {
2315 temp_ff.full = rfixed_const(1000);
2316 pix_clk.full = rfixed_const(mode1->clock); /* convert to fixed point */
2317 pix_clk.full = rfixed_div(pix_clk, temp_ff);
2318 temp_ff.full = rfixed_const(pixel_bytes1);
2319 peak_disp_bw.full += rfixed_mul(pix_clk, temp_ff);
2320 }
2321 if (mode2) {
2322 temp_ff.full = rfixed_const(1000);
2323 pix_clk2.full = rfixed_const(mode2->clock); /* convert to fixed point */
2324 pix_clk2.full = rfixed_div(pix_clk2, temp_ff);
2325 temp_ff.full = rfixed_const(pixel_bytes2);
2326 peak_disp_bw.full += rfixed_mul(pix_clk2, temp_ff);
2327 }
2328
2329 mem_bw.full = rfixed_mul(mem_bw, min_mem_eff);
2330 if (peak_disp_bw.full >= mem_bw.full) {
2331 DRM_ERROR("You may not have enough display bandwidth for current mode\n"
2332 "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
2333 }
2334
2335 /* Get values from the EXT_MEM_CNTL register...converting its contents. */
2336 temp = RREG32(RADEON_MEM_TIMING_CNTL);
2337 if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
2338 mem_trcd = ((temp >> 2) & 0x3) + 1;
2339 mem_trp = ((temp & 0x3)) + 1;
2340 mem_tras = ((temp & 0x70) >> 4) + 1;
2341 } else if (rdev->family == CHIP_R300 ||
2342 rdev->family == CHIP_R350) { /* r300, r350 */
2343 mem_trcd = (temp & 0x7) + 1;
2344 mem_trp = ((temp >> 8) & 0x7) + 1;
2345 mem_tras = ((temp >> 11) & 0xf) + 4;
2346 } else if (rdev->family == CHIP_RV350 ||
2347 rdev->family <= CHIP_RV380) {
2348 /* rv3x0 */
2349 mem_trcd = (temp & 0x7) + 3;
2350 mem_trp = ((temp >> 8) & 0x7) + 3;
2351 mem_tras = ((temp >> 11) & 0xf) + 6;
2352 } else if (rdev->family == CHIP_R420 ||
2353 rdev->family == CHIP_R423 ||
2354 rdev->family == CHIP_RV410) {
2355 /* r4xx */
2356 mem_trcd = (temp & 0xf) + 3;
2357 if (mem_trcd > 15)
2358 mem_trcd = 15;
2359 mem_trp = ((temp >> 8) & 0xf) + 3;
2360 if (mem_trp > 15)
2361 mem_trp = 15;
2362 mem_tras = ((temp >> 12) & 0x1f) + 6;
2363 if (mem_tras > 31)
2364 mem_tras = 31;
2365 } else { /* RV200, R200 */
2366 mem_trcd = (temp & 0x7) + 1;
2367 mem_trp = ((temp >> 8) & 0x7) + 1;
2368 mem_tras = ((temp >> 12) & 0xf) + 4;
2369 }
2370 /* convert to FF */
2371 trcd_ff.full = rfixed_const(mem_trcd);
2372 trp_ff.full = rfixed_const(mem_trp);
2373 tras_ff.full = rfixed_const(mem_tras);
2374
2375 /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
2376 temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2377 data = (temp & (7 << 20)) >> 20;
2378 if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) {
2379 if (rdev->family == CHIP_RS480) /* don't think rs400 */
2380 tcas_ff = memtcas_rs480_ff[data];
2381 else
2382 tcas_ff = memtcas_ff[data];
2383 } else
2384 tcas_ff = memtcas2_ff[data];
2385
2386 if (rdev->family == CHIP_RS400 ||
2387 rdev->family == CHIP_RS480) {
2388 /* extra cas latency stored in bits 23-25 0-4 clocks */
2389 data = (temp >> 23) & 0x7;
2390 if (data < 5)
2391 tcas_ff.full += rfixed_const(data);
2392 }
2393
2394 if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
2395 /* on the R300, Tcas is included in Trbs.
2396 */
2397 temp = RREG32(RADEON_MEM_CNTL);
2398 data = (R300_MEM_NUM_CHANNELS_MASK & temp);
2399 if (data == 1) {
2400 if (R300_MEM_USE_CD_CH_ONLY & temp) {
2401 temp = RREG32(R300_MC_IND_INDEX);
2402 temp &= ~R300_MC_IND_ADDR_MASK;
2403 temp |= R300_MC_READ_CNTL_CD_mcind;
2404 WREG32(R300_MC_IND_INDEX, temp);
2405 temp = RREG32(R300_MC_IND_DATA);
2406 data = (R300_MEM_RBS_POSITION_C_MASK & temp);
2407 } else {
2408 temp = RREG32(R300_MC_READ_CNTL_AB);
2409 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2410 }
2411 } else {
2412 temp = RREG32(R300_MC_READ_CNTL_AB);
2413 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2414 }
2415 if (rdev->family == CHIP_RV410 ||
2416 rdev->family == CHIP_R420 ||
2417 rdev->family == CHIP_R423)
2418 trbs_ff = memtrbs_r4xx[data];
2419 else
2420 trbs_ff = memtrbs[data];
2421 tcas_ff.full += trbs_ff.full;
2422 }
2423
2424 sclk_eff_ff.full = sclk_ff.full;
2425
2426 if (rdev->flags & RADEON_IS_AGP) {
2427 fixed20_12 agpmode_ff;
2428 agpmode_ff.full = rfixed_const(radeon_agpmode);
2429 temp_ff.full = rfixed_const_666(16);
2430 sclk_eff_ff.full -= rfixed_mul(agpmode_ff, temp_ff);
2431 }
2432 /* TODO PCIE lanes may affect this - agpmode == 16?? */
2433
2434 if (ASIC_IS_R300(rdev)) {
2435 sclk_delay_ff.full = rfixed_const(250);
2436 } else {
2437 if ((rdev->family == CHIP_RV100) ||
2438 rdev->flags & RADEON_IS_IGP) {
2439 if (rdev->mc.vram_is_ddr)
2440 sclk_delay_ff.full = rfixed_const(41);
2441 else
2442 sclk_delay_ff.full = rfixed_const(33);
2443 } else {
2444 if (rdev->mc.vram_width == 128)
2445 sclk_delay_ff.full = rfixed_const(57);
2446 else
2447 sclk_delay_ff.full = rfixed_const(41);
2448 }
2449 }
2450
2451 mc_latency_sclk.full = rfixed_div(sclk_delay_ff, sclk_eff_ff);
2452
2453 if (rdev->mc.vram_is_ddr) {
2454 if (rdev->mc.vram_width == 32) {
2455 k1.full = rfixed_const(40);
2456 c = 3;
2457 } else {
2458 k1.full = rfixed_const(20);
2459 c = 1;
2460 }
2461 } else {
2462 k1.full = rfixed_const(40);
2463 c = 3;
2464 }
2465
2466 temp_ff.full = rfixed_const(2);
2467 mc_latency_mclk.full = rfixed_mul(trcd_ff, temp_ff);
2468 temp_ff.full = rfixed_const(c);
2469 mc_latency_mclk.full += rfixed_mul(tcas_ff, temp_ff);
2470 temp_ff.full = rfixed_const(4);
2471 mc_latency_mclk.full += rfixed_mul(tras_ff, temp_ff);
2472 mc_latency_mclk.full += rfixed_mul(trp_ff, temp_ff);
2473 mc_latency_mclk.full += k1.full;
2474
2475 mc_latency_mclk.full = rfixed_div(mc_latency_mclk, mclk_ff);
2476 mc_latency_mclk.full += rfixed_div(temp_ff, sclk_eff_ff);
2477
2478 /*
2479 HW cursor time assuming worst case of full size colour cursor.
2480 */
2481 temp_ff.full = rfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
2482 temp_ff.full += trcd_ff.full;
2483 if (temp_ff.full < tras_ff.full)
2484 temp_ff.full = tras_ff.full;
2485 cur_latency_mclk.full = rfixed_div(temp_ff, mclk_ff);
2486
2487 temp_ff.full = rfixed_const(cur_size);
2488 cur_latency_sclk.full = rfixed_div(temp_ff, sclk_eff_ff);
2489 /*
2490 Find the total latency for the display data.
2491 */
2492 disp_latency_overhead.full = rfixed_const(80);
2493 disp_latency_overhead.full = rfixed_div(disp_latency_overhead, sclk_ff);
2494 mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
2495 mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
2496
2497 if (mc_latency_mclk.full > mc_latency_sclk.full)
2498 disp_latency.full = mc_latency_mclk.full;
2499 else
2500 disp_latency.full = mc_latency_sclk.full;
2501
2502 /* setup Max GRPH_STOP_REQ default value */
2503 if (ASIC_IS_RV100(rdev))
2504 max_stop_req = 0x5c;
2505 else
2506 max_stop_req = 0x7c;
2507
2508 if (mode1) {
2509 /* CRTC1
2510 Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
2511 GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
2512 */
2513 stop_req = mode1->hdisplay * pixel_bytes1 / 16;
2514
2515 if (stop_req > max_stop_req)
2516 stop_req = max_stop_req;
2517
2518 /*
2519 Find the drain rate of the display buffer.
2520 */
2521 temp_ff.full = rfixed_const((16/pixel_bytes1));
2522 disp_drain_rate.full = rfixed_div(pix_clk, temp_ff);
2523
2524 /*
2525 Find the critical point of the display buffer.
2526 */
2527 crit_point_ff.full = rfixed_mul(disp_drain_rate, disp_latency);
2528 crit_point_ff.full += rfixed_const_half(0);
2529
2530 critical_point = rfixed_trunc(crit_point_ff);
2531
2532 if (rdev->disp_priority == 2) {
2533 critical_point = 0;
2534 }
2535
2536 /*
2537 The critical point should never be above max_stop_req-4. Setting
2538 GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
2539 */
2540 if (max_stop_req - critical_point < 4)
2541 critical_point = 0;
2542
2543 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
2544 /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
2545 critical_point = 0x10;
2546 }
2547
2548 temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
2549 temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
2550 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
2551 temp &= ~(RADEON_GRPH_START_REQ_MASK);
2552 if ((rdev->family == CHIP_R350) &&
2553 (stop_req > 0x15)) {
2554 stop_req -= 0x10;
2555 }
2556 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
2557 temp |= RADEON_GRPH_BUFFER_SIZE;
2558 temp &= ~(RADEON_GRPH_CRITICAL_CNTL |
2559 RADEON_GRPH_CRITICAL_AT_SOF |
2560 RADEON_GRPH_STOP_CNTL);
2561 /*
2562 Write the result into the register.
2563 */
2564 WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
2565 (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
2566
2567#if 0
2568 if ((rdev->family == CHIP_RS400) ||
2569 (rdev->family == CHIP_RS480)) {
2570 /* attempt to program RS400 disp regs correctly ??? */
2571 temp = RREG32(RS400_DISP1_REG_CNTL);
2572 temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK |
2573 RS400_DISP1_STOP_REQ_LEVEL_MASK);
2574 WREG32(RS400_DISP1_REQ_CNTL1, (temp |
2575 (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
2576 (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
2577 temp = RREG32(RS400_DMIF_MEM_CNTL1);
2578 temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK |
2579 RS400_DISP1_CRITICAL_POINT_STOP_MASK);
2580 WREG32(RS400_DMIF_MEM_CNTL1, (temp |
2581 (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) |
2582 (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
2583 }
2584#endif
2585
2586 DRM_DEBUG("GRPH_BUFFER_CNTL from to %x\n",
2587 /* (unsigned int)info->SavedReg->grph_buffer_cntl, */
2588 (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
2589 }
2590
2591 if (mode2) {
2592 u32 grph2_cntl;
2593 stop_req = mode2->hdisplay * pixel_bytes2 / 16;
2594
2595 if (stop_req > max_stop_req)
2596 stop_req = max_stop_req;
2597
2598 /*
2599 Find the drain rate of the display buffer.
2600 */
2601 temp_ff.full = rfixed_const((16/pixel_bytes2));
2602 disp_drain_rate2.full = rfixed_div(pix_clk2, temp_ff);
2603
2604 grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL);
2605 grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK);
2606 grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
2607 grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK);
2608 if ((rdev->family == CHIP_R350) &&
2609 (stop_req > 0x15)) {
2610 stop_req -= 0x10;
2611 }
2612 grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
2613 grph2_cntl |= RADEON_GRPH_BUFFER_SIZE;
2614 grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL |
2615 RADEON_GRPH_CRITICAL_AT_SOF |
2616 RADEON_GRPH_STOP_CNTL);
2617
2618 if ((rdev->family == CHIP_RS100) ||
2619 (rdev->family == CHIP_RS200))
2620 critical_point2 = 0;
2621 else {
2622 temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
2623 temp_ff.full = rfixed_const(temp);
2624 temp_ff.full = rfixed_mul(mclk_ff, temp_ff);
2625 if (sclk_ff.full < temp_ff.full)
2626 temp_ff.full = sclk_ff.full;
2627
2628 read_return_rate.full = temp_ff.full;
2629
2630 if (mode1) {
2631 temp_ff.full = read_return_rate.full - disp_drain_rate.full;
2632 time_disp1_drop_priority.full = rfixed_div(crit_point_ff, temp_ff);
2633 } else {
2634 time_disp1_drop_priority.full = 0;
2635 }
2636 crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full;
2637 crit_point_ff.full = rfixed_mul(crit_point_ff, disp_drain_rate2);
2638 crit_point_ff.full += rfixed_const_half(0);
2639
2640 critical_point2 = rfixed_trunc(crit_point_ff);
2641
2642 if (rdev->disp_priority == 2) {
2643 critical_point2 = 0;
2644 }
2645
2646 if (max_stop_req - critical_point2 < 4)
2647 critical_point2 = 0;
2648
2649 }
2650
2651 if (critical_point2 == 0 && rdev->family == CHIP_R300) {
2652 /* some R300 cards have problem with this set to 0 */
2653 critical_point2 = 0x10;
2654 }
2655
2656 WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
2657 (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
2658
2659 if ((rdev->family == CHIP_RS400) ||
2660 (rdev->family == CHIP_RS480)) {
2661#if 0
2662 /* attempt to program RS400 disp2 regs correctly ??? */
2663 temp = RREG32(RS400_DISP2_REQ_CNTL1);
2664 temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK |
2665 RS400_DISP2_STOP_REQ_LEVEL_MASK);
2666 WREG32(RS400_DISP2_REQ_CNTL1, (temp |
2667 (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
2668 (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
2669 temp = RREG32(RS400_DISP2_REQ_CNTL2);
2670 temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK |
2671 RS400_DISP2_CRITICAL_POINT_STOP_MASK);
2672 WREG32(RS400_DISP2_REQ_CNTL2, (temp |
2673 (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) |
2674 (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT)));
2675#endif
2676 WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);
2677 WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000);
2678 WREG32(RS400_DMIF_MEM_CNTL1, 0x29CA71DC);
2679 WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
2680 }
2681
2682 DRM_DEBUG("GRPH2_BUFFER_CNTL from to %x\n",
2683 (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
2684 }
2685}
551ebd83
DA		 2686
2687static inline void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
2688{
2689 DRM_ERROR("pitch %d\n", t->pitch);
2690 DRM_ERROR("width %d\n", t->width);
2691 DRM_ERROR("height %d\n", t->height);
2692 DRM_ERROR("num levels %d\n", t->num_levels);
2693 DRM_ERROR("depth %d\n", t->txdepth);
2694 DRM_ERROR("bpp %d\n", t->cpp);
2695 DRM_ERROR("coordinate type %d\n", t->tex_coord_type);
2696 DRM_ERROR("width round to power of 2 %d\n", t->roundup_w);
2697 DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
2698}
2699
2700static int r100_cs_track_cube(struct radeon_device *rdev,
2701 struct r100_cs_track *track, unsigned idx)
2702{
2703 unsigned face, w, h;
2704 struct radeon_object *cube_robj;
2705 unsigned long size;
2706
2707 for (face = 0; face < 5; face++) {
2708 cube_robj = track->textures[idx].cube_info[face].robj;
2709 w = track->textures[idx].cube_info[face].width;
2710 h = track->textures[idx].cube_info[face].height;
2711
2712 size = w * h;
2713 size *= track->textures[idx].cpp;
2714
2715 size += track->textures[idx].cube_info[face].offset;
2716
2717 if (size > radeon_object_size(cube_robj)) {
2718 DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
2719 size, radeon_object_size(cube_robj));
2720 r100_cs_track_texture_print(&track->textures[idx]);
2721 return -1;
2722 }
2723 }
2724 return 0;
2725}
2726
2727static int r100_cs_track_texture_check(struct radeon_device *rdev,
2728 struct r100_cs_track *track)
2729{
2730 struct radeon_object *robj;
2731 unsigned long size;
2732 unsigned u, i, w, h;
2733 int ret;
2734
2735 for (u = 0; u < track->num_texture; u++) {
2736 if (!track->textures[u].enabled)
2737 continue;
2738 robj = track->textures[u].robj;
2739 if (robj == NULL) {
2740 DRM_ERROR("No texture bound to unit %u\n", u);
2741 return -EINVAL;
2742 }
2743 size = 0;
2744 for (i = 0; i <= track->textures[u].num_levels; i++) {
2745 if (track->textures[u].use_pitch) {
2746 if (rdev->family < CHIP_R300)
2747 w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i);
2748 else
2749 w = track->textures[u].pitch / (1 << i);
2750 } else {
2751 w = track->textures[u].width / (1 << i);
2752 if (rdev->family >= CHIP_RV515)
2753 w |= track->textures[u].width_11;
2754 if (track->textures[u].roundup_w)
2755 w = roundup_pow_of_two(w);
2756 }
2757 h = track->textures[u].height / (1 << i);
2758 if (rdev->family >= CHIP_RV515)
2759 h |= track->textures[u].height_11;
2760 if (track->textures[u].roundup_h)
2761 h = roundup_pow_of_two(h);
2762 size += w * h;
2763 }
2764 size *= track->textures[u].cpp;
2765 switch (track->textures[u].tex_coord_type) {
2766 case 0:
2767 break;
2768 case 1:
2769 size *= (1 << track->textures[u].txdepth);
2770 break;
2771 case 2:
2772 if (track->separate_cube) {
2773 ret = r100_cs_track_cube(rdev, track, u);
2774 if (ret)
2775 return ret;
2776 } else
2777 size *= 6;
2778 break;
2779 default:
2780 DRM_ERROR("Invalid texture coordinate type %u for unit "
2781 "%u\n", track->textures[u].tex_coord_type, u);
2782 return -EINVAL;
2783 }
2784 if (size > radeon_object_size(robj)) {
2785 DRM_ERROR("Texture of unit %u needs %lu bytes but is "
2786 "%lu\n", u, size, radeon_object_size(robj));
2787 r100_cs_track_texture_print(&track->textures[u]);
2788 return -EINVAL;
2789 }
2790 }
2791 return 0;
2792}
2793
2794int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
2795{
2796 unsigned i;
2797 unsigned long size;
2798 unsigned prim_walk;
2799 unsigned nverts;
2800
2801 for (i = 0; i < track->num_cb; i++) {
2802 if (track->cb[i].robj == NULL) {
2803 DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
2804 return -EINVAL;
2805 }
2806 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
2807 size += track->cb[i].offset;
2808 if (size > radeon_object_size(track->cb[i].robj)) {
2809 DRM_ERROR("[drm] Buffer too small for color buffer %d "
2810 "(need %lu have %lu) !\n", i, size,
2811 radeon_object_size(track->cb[i].robj));
2812 DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
2813 i, track->cb[i].pitch, track->cb[i].cpp,
2814 track->cb[i].offset, track->maxy);
2815 return -EINVAL;
2816 }
2817 }
2818 if (track->z_enabled) {
2819 if (track->zb.robj == NULL) {
2820 DRM_ERROR("[drm] No buffer for z buffer !\n");
2821 return -EINVAL;
2822 }
2823 size = track->zb.pitch * track->zb.cpp * track->maxy;
2824 size += track->zb.offset;
2825 if (size > radeon_object_size(track->zb.robj)) {
2826 DRM_ERROR("[drm] Buffer too small for z buffer "
2827 "(need %lu have %lu) !\n", size,
2828 radeon_object_size(track->zb.robj));
2829 DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
2830 track->zb.pitch, track->zb.cpp,
2831 track->zb.offset, track->maxy);
2832 return -EINVAL;
2833 }
2834 }
2835 prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
2836 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
2837 switch (prim_walk) {
2838 case 1:
2839 for (i = 0; i < track->num_arrays; i++) {
2840 size = track->arrays[i].esize * track->max_indx * 4;
2841 if (track->arrays[i].robj == NULL) {
2842 DRM_ERROR("(PW %u) Vertex array %u no buffer "
2843 "bound\n", prim_walk, i);
2844 return -EINVAL;
2845 }
2846 if (size > radeon_object_size(track->arrays[i].robj)) {
2847 DRM_ERROR("(PW %u) Vertex array %u need %lu dwords "
2848 "have %lu dwords\n", prim_walk, i,
2849 size >> 2,
2850 radeon_object_size(track->arrays[i].robj) >> 2);
2851 DRM_ERROR("Max indices %u\n", track->max_indx);
2852 return -EINVAL;
2853 }
2854 }
2855 break;
2856 case 2:
2857 for (i = 0; i < track->num_arrays; i++) {
2858 size = track->arrays[i].esize * (nverts - 1) * 4;
2859 if (track->arrays[i].robj == NULL) {
2860 DRM_ERROR("(PW %u) Vertex array %u no buffer "
2861 "bound\n", prim_walk, i);
2862 return -EINVAL;
2863 }
2864 if (size > radeon_object_size(track->arrays[i].robj)) {
2865 DRM_ERROR("(PW %u) Vertex array %u need %lu dwords "
2866 "have %lu dwords\n", prim_walk, i, size >> 2,
2867 radeon_object_size(track->arrays[i].robj) >> 2);
2868 return -EINVAL;
2869 }
2870 }
2871 break;
2872 case 3:
2873 size = track->vtx_size * nverts;
2874 if (size != track->immd_dwords) {
2875 DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
2876 track->immd_dwords, size);
2877 DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
2878 nverts, track->vtx_size);
2879 return -EINVAL;
2880 }
2881 break;
2882 default:
2883 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
2884 prim_walk);
2885 return -EINVAL;
2886 }
2887 return r100_cs_track_texture_check(rdev, track);
2888}
2889
2890void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track)
2891{
2892 unsigned i, face;
2893
2894 if (rdev->family < CHIP_R300) {
2895 track->num_cb = 1;
2896 if (rdev->family <= CHIP_RS200)
2897 track->num_texture = 3;
2898 else
2899 track->num_texture = 6;
2900 track->maxy = 2048;
2901 track->separate_cube = 1;
2902 } else {
2903 track->num_cb = 4;
2904 track->num_texture = 16;
2905 track->maxy = 4096;
2906 track->separate_cube = 0;
2907 }
2908
2909 for (i = 0; i < track->num_cb; i++) {
2910 track->cb[i].robj = NULL;
2911 track->cb[i].pitch = 8192;
2912 track->cb[i].cpp = 16;
2913 track->cb[i].offset = 0;
2914 }
2915 track->z_enabled = true;
2916 track->zb.robj = NULL;
2917 track->zb.pitch = 8192;
2918 track->zb.cpp = 4;
2919 track->zb.offset = 0;
2920 track->vtx_size = 0x7F;
2921 track->immd_dwords = 0xFFFFFFFFUL;
2922 track->num_arrays = 11;
2923 track->max_indx = 0x00FFFFFFUL;
2924 for (i = 0; i < track->num_arrays; i++) {
2925 track->arrays[i].robj = NULL;
2926 track->arrays[i].esize = 0x7F;
2927 }
2928 for (i = 0; i < track->num_texture; i++) {
2929 track->textures[i].pitch = 16536;
2930 track->textures[i].width = 16536;
2931 track->textures[i].height = 16536;
2932 track->textures[i].width_11 = 1 << 11;
2933 track->textures[i].height_11 = 1 << 11;
2934 track->textures[i].num_levels = 12;
2935 if (rdev->family <= CHIP_RS200) {
2936 track->textures[i].tex_coord_type = 0;
2937 track->textures[i].txdepth = 0;
2938 } else {
2939 track->textures[i].txdepth = 16;
2940 track->textures[i].tex_coord_type = 1;
2941 }
2942 track->textures[i].cpp = 64;
2943 track->textures[i].robj = NULL;
2944 /* CS IB emission code makes sure texture unit are disabled */
2945 track->textures[i].enabled = false;
2946 track->textures[i].roundup_w = true;
2947 track->textures[i].roundup_h = true;
2948 if (track->separate_cube)
2949 for (face = 0; face < 5; face++) {
2950 track->textures[i].cube_info[face].robj = NULL;
2951 track->textures[i].cube_info[face].width = 16536;
2952 track->textures[i].cube_info[face].height = 16536;
2953 track->textures[i].cube_info[face].offset = 0;
2954 }
2955 }
2956}
Linux kernel - Deliverables
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