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drm: add CRTC properties
[deliverable/linux.git] / drivers / gpu / drm / radeon / r100.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#include <linux/seq_file.h>
5a0e3ad6 29#include <linux/slab.h>
771fe6b9
JG		 30#include "drmP.h"
31#include "drm.h"
32#include "radeon_drm.h"
771fe6b9
JG		 33#include "radeon_reg.h"
34#include "radeon.h"
e6990375 35#include "radeon_asic.h"
3ce0a23d 36#include "r100d.h"
d4550907
JG		 37#include "rs100d.h"
38#include "rv200d.h"
39#include "rv250d.h"
49e02b73 40#include "atom.h"
3ce0a23d 41
70967ab9
BH		 42#include <linux/firmware.h>
43#include <linux/platform_device.h>
e0cd3608 44#include <linux/module.h>
70967ab9 45
551ebd83
DA		 46#include "r100_reg_safe.h"
47#include "rn50_reg_safe.h"
48
70967ab9
BH		 49/* Firmware Names */
50#define FIRMWARE_R100 "radeon/R100_cp.bin"
51#define FIRMWARE_R200 "radeon/R200_cp.bin"
52#define FIRMWARE_R300 "radeon/R300_cp.bin"
53#define FIRMWARE_R420 "radeon/R420_cp.bin"
54#define FIRMWARE_RS690 "radeon/RS690_cp.bin"
55#define FIRMWARE_RS600 "radeon/RS600_cp.bin"
56#define FIRMWARE_R520 "radeon/R520_cp.bin"
57
58MODULE_FIRMWARE(FIRMWARE_R100);
59MODULE_FIRMWARE(FIRMWARE_R200);
60MODULE_FIRMWARE(FIRMWARE_R300);
61MODULE_FIRMWARE(FIRMWARE_R420);
62MODULE_FIRMWARE(FIRMWARE_RS690);
63MODULE_FIRMWARE(FIRMWARE_RS600);
64MODULE_FIRMWARE(FIRMWARE_R520);
771fe6b9 65
551ebd83
DA		 66#include "r100_track.h"
67
3ae19b75
AD		 68void r100_wait_for_vblank(struct radeon_device *rdev, int crtc)
69{
70 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc];
71 int i;
72
73 if (radeon_crtc->crtc_id == 0) {
74 if (RREG32(RADEON_CRTC_GEN_CNTL) & RADEON_CRTC_EN) {
75 for (i = 0; i < rdev->usec_timeout; i++) {
76 if (!(RREG32(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_CUR))
77 break;
78 udelay(1);
79 }
80 for (i = 0; i < rdev->usec_timeout; i++) {
81 if (RREG32(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_CUR)
82 break;
83 udelay(1);
84 }
85 }
86 } else {
87 if (RREG32(RADEON_CRTC2_GEN_CNTL) & RADEON_CRTC2_EN) {
88 for (i = 0; i < rdev->usec_timeout; i++) {
89 if (!(RREG32(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_CUR))
90 break;
91 udelay(1);
92 }
93 for (i = 0; i < rdev->usec_timeout; i++) {
94 if (RREG32(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_CUR)
95 break;
96 udelay(1);
97 }
98 }
99 }
100}
101
771fe6b9
JG		 102/* This files gather functions specifics to:
103 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
771fe6b9 104 */
771fe6b9 105
cbdd4501
AK		 106int r100_reloc_pitch_offset(struct radeon_cs_parser *p,
107 struct radeon_cs_packet *pkt,
108 unsigned idx,
109 unsigned reg)
110{
111 int r;
112 u32 tile_flags = 0;
113 u32 tmp;
114 struct radeon_cs_reloc *reloc;
115 u32 value;
116
117 r = r100_cs_packet_next_reloc(p, &reloc);
118 if (r) {
119 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
120 idx, reg);
121 r100_cs_dump_packet(p, pkt);
122 return r;
123 }
c9068eb2 124
cbdd4501
AK		 125 value = radeon_get_ib_value(p, idx);
126 tmp = value & 0x003fffff;
127 tmp += (((u32)reloc->lobj.gpu_offset) >> 10);
128
c9068eb2
AD		 129 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
130 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
131 tile_flags |= RADEON_DST_TILE_MACRO;
132 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
133 if (reg == RADEON_SRC_PITCH_OFFSET) {
134 DRM_ERROR("Cannot src blit from microtiled surface\n");
135 r100_cs_dump_packet(p, pkt);
136 return -EINVAL;
137 }
138 tile_flags |= RADEON_DST_TILE_MICRO;
cbdd4501 139 }
cbdd4501 140
c9068eb2 141 tmp |= tile_flags;
f2e39221 142 p->ib.ptr[idx] = (value & 0x3fc00000) | tmp;
c9068eb2 143 } else
f2e39221 144 p->ib.ptr[idx] = (value & 0xffc00000) | tmp;
cbdd4501
AK		 145 return 0;
146}
147
148int r100_packet3_load_vbpntr(struct radeon_cs_parser *p,
149 struct radeon_cs_packet *pkt,
150 int idx)
151{
152 unsigned c, i;
153 struct radeon_cs_reloc *reloc;
154 struct r100_cs_track *track;
155 int r = 0;
156 volatile uint32_t *ib;
157 u32 idx_value;
158
f2e39221 159 ib = p->ib.ptr;
cbdd4501
AK		 160 track = (struct r100_cs_track *)p->track;
161 c = radeon_get_ib_value(p, idx++) & 0x1F;
162 if (c > 16) {
163 DRM_ERROR("Only 16 vertex buffers are allowed %d\n",
164 pkt->opcode);
165 r100_cs_dump_packet(p, pkt);
166 return -EINVAL;
167 }
168 track->num_arrays = c;
169 for (i = 0; i < (c - 1); i+=2, idx+=3) {
170 r = r100_cs_packet_next_reloc(p, &reloc);
171 if (r) {
172 DRM_ERROR("No reloc for packet3 %d\n",
173 pkt->opcode);
174 r100_cs_dump_packet(p, pkt);
175 return r;
176 }
177 idx_value = radeon_get_ib_value(p, idx);
178 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
179
180 track->arrays[i + 0].esize = idx_value >> 8;
181 track->arrays[i + 0].robj = reloc->robj;
182 track->arrays[i + 0].esize &= 0x7F;
183 r = r100_cs_packet_next_reloc(p, &reloc);
184 if (r) {
185 DRM_ERROR("No reloc for packet3 %d\n",
186 pkt->opcode);
187 r100_cs_dump_packet(p, pkt);
188 return r;
189 }
190 ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->lobj.gpu_offset);
191 track->arrays[i + 1].robj = reloc->robj;
192 track->arrays[i + 1].esize = idx_value >> 24;
193 track->arrays[i + 1].esize &= 0x7F;
194 }
195 if (c & 1) {
196 r = r100_cs_packet_next_reloc(p, &reloc);
197 if (r) {
198 DRM_ERROR("No reloc for packet3 %d\n",
199 pkt->opcode);
200 r100_cs_dump_packet(p, pkt);
201 return r;
202 }
203 idx_value = radeon_get_ib_value(p, idx);
204 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
205 track->arrays[i + 0].robj = reloc->robj;
206 track->arrays[i + 0].esize = idx_value >> 8;
207 track->arrays[i + 0].esize &= 0x7F;
208 }
209 return r;
210}
211
6f34be50
AD		 212void r100_pre_page_flip(struct radeon_device *rdev, int crtc)
213{
6f34be50
AD		 214 /* enable the pflip int */
215 radeon_irq_kms_pflip_irq_get(rdev, crtc);
216}
217
218void r100_post_page_flip(struct radeon_device *rdev, int crtc)
219{
220 /* disable the pflip int */
221 radeon_irq_kms_pflip_irq_put(rdev, crtc);
222}
223
224u32 r100_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
225{
226 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
227 u32 tmp = ((u32)crtc_base) | RADEON_CRTC_OFFSET__OFFSET_LOCK;
f6496479 228 int i;
6f34be50
AD		 229
230 /* Lock the graphics update lock */
231 /* update the scanout addresses */
232 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
233
acb32506 234 /* Wait for update_pending to go high. */
f6496479
AD		 235 for (i = 0; i < rdev->usec_timeout; i++) {
236 if (RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET)
237 break;
238 udelay(1);
239 }
acb32506 240 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
6f34be50
AD		 241
242 /* Unlock the lock, so double-buffering can take place inside vblank */
243 tmp &= ~RADEON_CRTC_OFFSET__OFFSET_LOCK;
244 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
245
246 /* Return current update_pending status: */
247 return RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET;
248}
249
ce8f5370 250void r100_pm_get_dynpm_state(struct radeon_device *rdev)
a48b9b4e
AD		 251{
252 int i;
ce8f5370
AD		 253 rdev->pm.dynpm_can_upclock = true;
254 rdev->pm.dynpm_can_downclock = true;
a48b9b4e 255
ce8f5370
AD		 256 switch (rdev->pm.dynpm_planned_action) {
257 case DYNPM_ACTION_MINIMUM:
a48b9b4e 258 rdev->pm.requested_power_state_index = 0;
ce8f5370 259 rdev->pm.dynpm_can_downclock = false;
a48b9b4e 260 break;
ce8f5370 261 case DYNPM_ACTION_DOWNCLOCK:
a48b9b4e
AD		 262 if (rdev->pm.current_power_state_index == 0) {
263 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
ce8f5370 264 rdev->pm.dynpm_can_downclock = false;
a48b9b4e
AD		 265 } else {
266 if (rdev->pm.active_crtc_count > 1) {
267 for (i = 0; i < rdev->pm.num_power_states; i++) {
d7311171 268 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
a48b9b4e
AD		 269 continue;
270 else if (i >= rdev->pm.current_power_state_index) {
271 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
272 break;
273 } else {
274 rdev->pm.requested_power_state_index = i;
275 break;
276 }
277 }
278 } else
279 rdev->pm.requested_power_state_index =
280 rdev->pm.current_power_state_index - 1;
281 }
d7311171
AD		 282 /* don't use the power state if crtcs are active and no display flag is set */
283 if ((rdev->pm.active_crtc_count > 0) &&
284 (rdev->pm.power_state[rdev->pm.requested_power_state_index].clock_info[0].flags &
285 RADEON_PM_MODE_NO_DISPLAY)) {
286 rdev->pm.requested_power_state_index++;
287 }
a48b9b4e 288 break;
ce8f5370 289 case DYNPM_ACTION_UPCLOCK:
a48b9b4e
AD		 290 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
291 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
ce8f5370 292 rdev->pm.dynpm_can_upclock = false;
a48b9b4e
AD		 293 } else {
294 if (rdev->pm.active_crtc_count > 1) {
295 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
d7311171 296 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
a48b9b4e
AD		 297 continue;
298 else if (i <= rdev->pm.current_power_state_index) {
299 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
300 break;
301 } else {
302 rdev->pm.requested_power_state_index = i;
303 break;
304 }
305 }
306 } else
307 rdev->pm.requested_power_state_index =
308 rdev->pm.current_power_state_index + 1;
309 }
310 break;
ce8f5370 311 case DYNPM_ACTION_DEFAULT:
58e21dff 312 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
ce8f5370 313 rdev->pm.dynpm_can_upclock = false;
58e21dff 314 break;
ce8f5370 315 case DYNPM_ACTION_NONE:
a48b9b4e
AD		 316 default:
317 DRM_ERROR("Requested mode for not defined action\n");
318 return;
319 }
320 /* only one clock mode per power state */
321 rdev->pm.requested_clock_mode_index = 0;
322
d9fdaafb 323 DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
ce8a3eb2
AD		 324 rdev->pm.power_state[rdev->pm.requested_power_state_index].
325 clock_info[rdev->pm.requested_clock_mode_index].sclk,
326 rdev->pm.power_state[rdev->pm.requested_power_state_index].
327 clock_info[rdev->pm.requested_clock_mode_index].mclk,
328 rdev->pm.power_state[rdev->pm.requested_power_state_index].
329 pcie_lanes);
a48b9b4e
AD		 330}
331
ce8f5370
AD		 332void r100_pm_init_profile(struct radeon_device *rdev)
333{
334 /* default */
335 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
336 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
337 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
338 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
339 /* low sh */
340 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
341 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
342 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
343 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 344 /* mid sh */
345 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
346 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
347 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
348 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 349 /* high sh */
350 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
351 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
352 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
353 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
354 /* low mh */
355 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
356 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
357 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
358 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 359 /* mid mh */
360 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
361 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
362 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
363 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 364 /* high mh */
365 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
366 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
367 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
368 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
bae6b562
AD		 369}
370
49e02b73
AD		 371void r100_pm_misc(struct radeon_device *rdev)
372{
49e02b73
AD		 373 int requested_index = rdev->pm.requested_power_state_index;
374 struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
375 struct radeon_voltage *voltage = &ps->clock_info[0].voltage;
376 u32 tmp, sclk_cntl, sclk_cntl2, sclk_more_cntl;
377
378 if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) {
379 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
380 tmp = RREG32(voltage->gpio.reg);
381 if (voltage->active_high)
382 tmp |= voltage->gpio.mask;
383 else
384 tmp &= ~(voltage->gpio.mask);
385 WREG32(voltage->gpio.reg, tmp);
386 if (voltage->delay)
387 udelay(voltage->delay);
388 } else {
389 tmp = RREG32(voltage->gpio.reg);
390 if (voltage->active_high)
391 tmp &= ~voltage->gpio.mask;
392 else
393 tmp |= voltage->gpio.mask;
394 WREG32(voltage->gpio.reg, tmp);
395 if (voltage->delay)
396 udelay(voltage->delay);
397 }
398 }
399
400 sclk_cntl = RREG32_PLL(SCLK_CNTL);
401 sclk_cntl2 = RREG32_PLL(SCLK_CNTL2);
402 sclk_cntl2 &= ~REDUCED_SPEED_SCLK_SEL(3);
403 sclk_more_cntl = RREG32_PLL(SCLK_MORE_CNTL);
404 sclk_more_cntl &= ~VOLTAGE_DELAY_SEL(3);
405 if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) {
406 sclk_more_cntl |= REDUCED_SPEED_SCLK_EN;
407 if (ps->misc & ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE)
408 sclk_cntl2 |= REDUCED_SPEED_SCLK_MODE;
409 else
410 sclk_cntl2 &= ~REDUCED_SPEED_SCLK_MODE;
411 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2)
412 sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(0);
413 else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4)
414 sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(2);
415 } else
416 sclk_more_cntl &= ~REDUCED_SPEED_SCLK_EN;
417
418 if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) {
419 sclk_more_cntl |= IO_CG_VOLTAGE_DROP;
420 if (voltage->delay) {
421 sclk_more_cntl |= VOLTAGE_DROP_SYNC;
422 switch (voltage->delay) {
423 case 33:
424 sclk_more_cntl |= VOLTAGE_DELAY_SEL(0);
425 break;
426 case 66:
427 sclk_more_cntl |= VOLTAGE_DELAY_SEL(1);
428 break;
429 case 99:
430 sclk_more_cntl |= VOLTAGE_DELAY_SEL(2);
431 break;
432 case 132:
433 sclk_more_cntl |= VOLTAGE_DELAY_SEL(3);
434 break;
435 }
436 } else
437 sclk_more_cntl &= ~VOLTAGE_DROP_SYNC;
438 } else
439 sclk_more_cntl &= ~IO_CG_VOLTAGE_DROP;
440
441 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN)
442 sclk_cntl &= ~FORCE_HDP;
443 else
444 sclk_cntl |= FORCE_HDP;
445
446 WREG32_PLL(SCLK_CNTL, sclk_cntl);
447 WREG32_PLL(SCLK_CNTL2, sclk_cntl2);
448 WREG32_PLL(SCLK_MORE_CNTL, sclk_more_cntl);
449
450 /* set pcie lanes */
451 if ((rdev->flags & RADEON_IS_PCIE) &&
452 !(rdev->flags & RADEON_IS_IGP) &&
798bcf73 453 rdev->asic->pm.set_pcie_lanes &&
49e02b73
AD		 454 (ps->pcie_lanes !=
455 rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {
456 radeon_set_pcie_lanes(rdev,
457 ps->pcie_lanes);
d9fdaafb 458 DRM_DEBUG_DRIVER("Setting: p: %d\n", ps->pcie_lanes);
49e02b73 459 }
49e02b73
AD		 460}
461
462void r100_pm_prepare(struct radeon_device *rdev)
463{
464 struct drm_device *ddev = rdev->ddev;
465 struct drm_crtc *crtc;
466 struct radeon_crtc *radeon_crtc;
467 u32 tmp;
468
469 /* disable any active CRTCs */
470 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
471 radeon_crtc = to_radeon_crtc(crtc);
472 if (radeon_crtc->enabled) {
473 if (radeon_crtc->crtc_id) {
474 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
475 tmp |= RADEON_CRTC2_DISP_REQ_EN_B;
476 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
477 } else {
478 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
479 tmp |= RADEON_CRTC_DISP_REQ_EN_B;
480 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
481 }
482 }
483 }
484}
485
486void r100_pm_finish(struct radeon_device *rdev)
487{
488 struct drm_device *ddev = rdev->ddev;
489 struct drm_crtc *crtc;
490 struct radeon_crtc *radeon_crtc;
491 u32 tmp;
492
493 /* enable any active CRTCs */
494 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
495 radeon_crtc = to_radeon_crtc(crtc);
496 if (radeon_crtc->enabled) {
497 if (radeon_crtc->crtc_id) {
498 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
499 tmp &= ~RADEON_CRTC2_DISP_REQ_EN_B;
500 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
501 } else {
502 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
503 tmp &= ~RADEON_CRTC_DISP_REQ_EN_B;
504 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
505 }
506 }
507 }
508}
509
def9ba9c
AD		 510bool r100_gui_idle(struct radeon_device *rdev)
511{
512 if (RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE)
513 return false;
514 else
515 return true;
516}
517
05a05c50
AD		 518/* hpd for digital panel detect/disconnect */
519bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
520{
521 bool connected = false;
522
523 switch (hpd) {
524 case RADEON_HPD_1:
525 if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE)
526 connected = true;
527 break;
528 case RADEON_HPD_2:
529 if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE)
530 connected = true;
531 break;
532 default:
533 break;
534 }
535 return connected;
536}
537
538void r100_hpd_set_polarity(struct radeon_device *rdev,
539 enum radeon_hpd_id hpd)
540{
541 u32 tmp;
542 bool connected = r100_hpd_sense(rdev, hpd);
543
544 switch (hpd) {
545 case RADEON_HPD_1:
546 tmp = RREG32(RADEON_FP_GEN_CNTL);
547 if (connected)
548 tmp &= ~RADEON_FP_DETECT_INT_POL;
549 else
550 tmp |= RADEON_FP_DETECT_INT_POL;
551 WREG32(RADEON_FP_GEN_CNTL, tmp);
552 break;
553 case RADEON_HPD_2:
554 tmp = RREG32(RADEON_FP2_GEN_CNTL);
555 if (connected)
556 tmp &= ~RADEON_FP2_DETECT_INT_POL;
557 else
558 tmp |= RADEON_FP2_DETECT_INT_POL;
559 WREG32(RADEON_FP2_GEN_CNTL, tmp);
560 break;
561 default:
562 break;
563 }
564}
565
566void r100_hpd_init(struct radeon_device *rdev)
567{
568 struct drm_device *dev = rdev->ddev;
569 struct drm_connector *connector;
570
571 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
572 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
573 switch (radeon_connector->hpd.hpd) {
574 case RADEON_HPD_1:
575 rdev->irq.hpd[0] = true;
576 break;
577 case RADEON_HPD_2:
578 rdev->irq.hpd[1] = true;
579 break;
580 default:
581 break;
582 }
64912e99 583 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
05a05c50 584 }
003e69f9
JG		 585 if (rdev->irq.installed)
586 r100_irq_set(rdev);
05a05c50
AD		 587}
588
589void r100_hpd_fini(struct radeon_device *rdev)
590{
591 struct drm_device *dev = rdev->ddev;
592 struct drm_connector *connector;
593
594 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
595 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
596 switch (radeon_connector->hpd.hpd) {
597 case RADEON_HPD_1:
598 rdev->irq.hpd[0] = false;
599 break;
600 case RADEON_HPD_2:
601 rdev->irq.hpd[1] = false;
602 break;
603 default:
604 break;
605 }
606 }
607}
608
771fe6b9
JG		 609/*
610 * PCI GART
611 */
612void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
613{
614 /* TODO: can we do somethings here ? */
615 /* It seems hw only cache one entry so we should discard this
616 * entry otherwise if first GPU GART read hit this entry it
617 * could end up in wrong address. */
618}
619
4aac0473 620int r100_pci_gart_init(struct radeon_device *rdev)
771fe6b9 621{
771fe6b9
JG		 622 int r;
623
c9a1be96 624 if (rdev->gart.ptr) {
fce7d61b 625 WARN(1, "R100 PCI GART already initialized\n");
4aac0473
JG		 626 return 0;
627 }
771fe6b9
JG		 628 /* Initialize common gart structure */
629 r = radeon_gart_init(rdev);
4aac0473 630 if (r)
771fe6b9 631 return r;
4aac0473 632 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
c5b3b850
AD		 633 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
634 rdev->asic->gart.set_page = &r100_pci_gart_set_page;
4aac0473
JG		 635 return radeon_gart_table_ram_alloc(rdev);
636}
637
17e15b0c
DA		 638/* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
639void r100_enable_bm(struct radeon_device *rdev)
640{
641 uint32_t tmp;
642 /* Enable bus mastering */
643 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
644 WREG32(RADEON_BUS_CNTL, tmp);
645}
646
4aac0473
JG		 647int r100_pci_gart_enable(struct radeon_device *rdev)
648{
649 uint32_t tmp;
650
82568565 651 radeon_gart_restore(rdev);
771fe6b9
JG		 652 /* discard memory request outside of configured range */
653 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
654 WREG32(RADEON_AIC_CNTL, tmp);
655 /* set address range for PCI address translate */
d594e46a
JG		 656 WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start);
657 WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end);
771fe6b9
JG		 658 /* set PCI GART page-table base address */
659 WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
660 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
661 WREG32(RADEON_AIC_CNTL, tmp);
662 r100_pci_gart_tlb_flush(rdev);
43caf451 663 DRM_INFO("PCI GART of %uM enabled (table at 0x%016llX).\n",
fcf4de5a
TV		 664 (unsigned)(rdev->mc.gtt_size >> 20),
665 (unsigned long long)rdev->gart.table_addr);
771fe6b9
JG		 666 rdev->gart.ready = true;
667 return 0;
668}
669
670void r100_pci_gart_disable(struct radeon_device *rdev)
671{
672 uint32_t tmp;
673
674 /* discard memory request outside of configured range */
675 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
676 WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
677 WREG32(RADEON_AIC_LO_ADDR, 0);
678 WREG32(RADEON_AIC_HI_ADDR, 0);
679}
680
681int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
682{
c9a1be96
JG		 683 u32 *gtt = rdev->gart.ptr;
684
771fe6b9
JG		 685 if (i < 0 || i > rdev->gart.num_gpu_pages) {
686 return -EINVAL;
687 }
c9a1be96 688 gtt[i] = cpu_to_le32(lower_32_bits(addr));
771fe6b9
JG		 689 return 0;
690}
691
4aac0473 692void r100_pci_gart_fini(struct radeon_device *rdev)
771fe6b9 693{
f9274562 694 radeon_gart_fini(rdev);
4aac0473
JG		 695 r100_pci_gart_disable(rdev);
696 radeon_gart_table_ram_free(rdev);
771fe6b9
JG		 697}
698
7ed220d7
MD		 699int r100_irq_set(struct radeon_device *rdev)
700{
701 uint32_t tmp = 0;
702
003e69f9 703 if (!rdev->irq.installed) {
fce7d61b 704 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
003e69f9
JG		 705 WREG32(R_000040_GEN_INT_CNTL, 0);
706 return -EINVAL;
707 }
1b37078b 708 if (rdev->irq.sw_int[RADEON_RING_TYPE_GFX_INDEX]) {
7ed220d7
MD		 709 tmp |= RADEON_SW_INT_ENABLE;
710 }
2031f77c
AD		 711 if (rdev->irq.gui_idle) {
712 tmp |= RADEON_GUI_IDLE_MASK;
713 }
6f34be50
AD		 714 if (rdev->irq.crtc_vblank_int[0] ||
715 rdev->irq.pflip[0]) {
7ed220d7
MD		 716 tmp |= RADEON_CRTC_VBLANK_MASK;
717 }
6f34be50
AD		 718 if (rdev->irq.crtc_vblank_int[1] ||
719 rdev->irq.pflip[1]) {
7ed220d7
MD		 720 tmp |= RADEON_CRTC2_VBLANK_MASK;
721 }
05a05c50
AD		 722 if (rdev->irq.hpd[0]) {
723 tmp |= RADEON_FP_DETECT_MASK;
724 }
725 if (rdev->irq.hpd[1]) {
726 tmp |= RADEON_FP2_DETECT_MASK;
727 }
7ed220d7
MD		 728 WREG32(RADEON_GEN_INT_CNTL, tmp);
729 return 0;
730}
731
9f022ddf
JG		 732void r100_irq_disable(struct radeon_device *rdev)
733{
734 u32 tmp;
735
736 WREG32(R_000040_GEN_INT_CNTL, 0);
737 /* Wait and acknowledge irq */
738 mdelay(1);
739 tmp = RREG32(R_000044_GEN_INT_STATUS);
740 WREG32(R_000044_GEN_INT_STATUS, tmp);
741}
742
cbdd4501 743static uint32_t r100_irq_ack(struct radeon_device *rdev)
7ed220d7
MD		 744{
745 uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
05a05c50
AD		 746 uint32_t irq_mask = RADEON_SW_INT_TEST |
747 RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT |
748 RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT;
7ed220d7 749
2031f77c
AD		 750 /* the interrupt works, but the status bit is permanently asserted */
751 if (rdev->irq.gui_idle && radeon_gui_idle(rdev)) {
752 if (!rdev->irq.gui_idle_acked)
753 irq_mask |= RADEON_GUI_IDLE_STAT;
754 }
755
7ed220d7
MD		 756 if (irqs) {
757 WREG32(RADEON_GEN_INT_STATUS, irqs);
758 }
759 return irqs & irq_mask;
760}
761
762int r100_irq_process(struct radeon_device *rdev)
763{
3e5cb98d 764 uint32_t status, msi_rearm;
d4877cf2 765 bool queue_hotplug = false;
7ed220d7 766
2031f77c
AD		 767 /* reset gui idle ack. the status bit is broken */
768 rdev->irq.gui_idle_acked = false;
769
7ed220d7
MD		 770 status = r100_irq_ack(rdev);
771 if (!status) {
772 return IRQ_NONE;
773 }
a513c184
JG		 774 if (rdev->shutdown) {
775 return IRQ_NONE;
776 }
7ed220d7
MD		 777 while (status) {
778 /* SW interrupt */
779 if (status & RADEON_SW_INT_TEST) {
7465280c 780 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
7ed220d7 781 }
2031f77c
AD		 782 /* gui idle interrupt */
783 if (status & RADEON_GUI_IDLE_STAT) {
784 rdev->irq.gui_idle_acked = true;
785 rdev->pm.gui_idle = true;
786 wake_up(&rdev->irq.idle_queue);
787 }
7ed220d7
MD		 788 /* Vertical blank interrupts */
789 if (status & RADEON_CRTC_VBLANK_STAT) {
6f34be50
AD		 790 if (rdev->irq.crtc_vblank_int[0]) {
791 drm_handle_vblank(rdev->ddev, 0);
792 rdev->pm.vblank_sync = true;
793 wake_up(&rdev->irq.vblank_queue);
794 }
3e4ea742
MK		 795 if (rdev->irq.pflip[0])
796 radeon_crtc_handle_flip(rdev, 0);
7ed220d7
MD		 797 }
798 if (status & RADEON_CRTC2_VBLANK_STAT) {
6f34be50
AD		 799 if (rdev->irq.crtc_vblank_int[1]) {
800 drm_handle_vblank(rdev->ddev, 1);
801 rdev->pm.vblank_sync = true;
802 wake_up(&rdev->irq.vblank_queue);
803 }
3e4ea742
MK		 804 if (rdev->irq.pflip[1])
805 radeon_crtc_handle_flip(rdev, 1);
7ed220d7 806 }
05a05c50 807 if (status & RADEON_FP_DETECT_STAT) {
d4877cf2
AD		 808 queue_hotplug = true;
809 DRM_DEBUG("HPD1\n");
05a05c50
AD		 810 }
811 if (status & RADEON_FP2_DETECT_STAT) {
d4877cf2
AD		 812 queue_hotplug = true;
813 DRM_DEBUG("HPD2\n");
05a05c50 814 }
7ed220d7
MD		 815 status = r100_irq_ack(rdev);
816 }
2031f77c
AD		 817 /* reset gui idle ack. the status bit is broken */
818 rdev->irq.gui_idle_acked = false;
d4877cf2 819 if (queue_hotplug)
32c87fca 820 schedule_work(&rdev->hotplug_work);
3e5cb98d
AD		 821 if (rdev->msi_enabled) {
822 switch (rdev->family) {
823 case CHIP_RS400:
824 case CHIP_RS480:
825 msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM;
826 WREG32(RADEON_AIC_CNTL, msi_rearm);
827 WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM);
828 break;
829 default:
b7f5b7de 830 WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN);
3e5cb98d
AD		 831 break;
832 }
833 }
7ed220d7
MD		 834 return IRQ_HANDLED;
835}
836
837u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
838{
839 if (crtc == 0)
840 return RREG32(RADEON_CRTC_CRNT_FRAME);
841 else
842 return RREG32(RADEON_CRTC2_CRNT_FRAME);
843}
844
9e5b2af7
PN		 845/* Who ever call radeon_fence_emit should call ring_lock and ask
846 * for enough space (today caller are ib schedule and buffer move) */
771fe6b9
JG		 847void r100_fence_ring_emit(struct radeon_device *rdev,
848 struct radeon_fence *fence)
849{
e32eb50d 850 struct radeon_ring *ring = &rdev->ring[fence->ring];
7b1f2485 851
9e5b2af7
PN		 852 /* We have to make sure that caches are flushed before
853 * CPU might read something from VRAM. */
e32eb50d
CK		 854 radeon_ring_write(ring, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));
855 radeon_ring_write(ring, RADEON_RB3D_DC_FLUSH_ALL);
856 radeon_ring_write(ring, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));
857 radeon_ring_write(ring, RADEON_RB3D_ZC_FLUSH_ALL);
771fe6b9 858 /* Wait until IDLE & CLEAN */
e32eb50d
CK		 859 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
860 radeon_ring_write(ring, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
861 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
862 radeon_ring_write(ring, rdev->config.r100.hdp_cntl |
cafe6609 863 RADEON_HDP_READ_BUFFER_INVALIDATE);
e32eb50d
CK		 864 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
865 radeon_ring_write(ring, rdev->config.r100.hdp_cntl);
771fe6b9 866 /* Emit fence sequence & fire IRQ */
e32eb50d
CK		 867 radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0));
868 radeon_ring_write(ring, fence->seq);
869 radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0));
870 radeon_ring_write(ring, RADEON_SW_INT_FIRE);
771fe6b9
JG		 871}
872
15d3332f 873void r100_semaphore_ring_emit(struct radeon_device *rdev,
e32eb50d 874 struct radeon_ring *ring,
15d3332f 875 struct radeon_semaphore *semaphore,
7b1f2485 876 bool emit_wait)
15d3332f
CK		 877{
878 /* Unused on older asics, since we don't have semaphores or multiple rings */
879 BUG();
880}
881
771fe6b9
JG		 882int r100_copy_blit(struct radeon_device *rdev,
883 uint64_t src_offset,
884 uint64_t dst_offset,
003cefe0 885 unsigned num_gpu_pages,
771fe6b9
JG		 886 struct radeon_fence *fence)
887{
e32eb50d 888 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
771fe6b9 889 uint32_t cur_pages;
003cefe0 890 uint32_t stride_bytes = RADEON_GPU_PAGE_SIZE;
771fe6b9
JG		 891 uint32_t pitch;
892 uint32_t stride_pixels;
893 unsigned ndw;
894 int num_loops;
895 int r = 0;
896
897 /* radeon limited to 16k stride */
898 stride_bytes &= 0x3fff;
899 /* radeon pitch is /64 */
900 pitch = stride_bytes / 64;
901 stride_pixels = stride_bytes / 4;
003cefe0 902 num_loops = DIV_ROUND_UP(num_gpu_pages, 8191);
771fe6b9
JG		 903
904 /* Ask for enough room for blit + flush + fence */
905 ndw = 64 + (10 * num_loops);
e32eb50d 906 r = radeon_ring_lock(rdev, ring, ndw);
771fe6b9
JG		 907 if (r) {
908 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
909 return -EINVAL;
910 }
003cefe0
AD		 911 while (num_gpu_pages > 0) {
912 cur_pages = num_gpu_pages;
771fe6b9
JG		 913 if (cur_pages > 8191) {
914 cur_pages = 8191;
915 }
003cefe0 916 num_gpu_pages -= cur_pages;
771fe6b9
JG		 917
918 /* pages are in Y direction - height
919 page width in X direction - width */
e32eb50d
CK		 920 radeon_ring_write(ring, PACKET3(PACKET3_BITBLT_MULTI, 8));
921 radeon_ring_write(ring,
771fe6b9
JG		 922 RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
923 RADEON_GMC_DST_PITCH_OFFSET_CNTL |
924 RADEON_GMC_SRC_CLIPPING |
925 RADEON_GMC_DST_CLIPPING |
926 RADEON_GMC_BRUSH_NONE |
927 (RADEON_COLOR_FORMAT_ARGB8888 << 8) |
928 RADEON_GMC_SRC_DATATYPE_COLOR |
929 RADEON_ROP3_S |
930 RADEON_DP_SRC_SOURCE_MEMORY |
931 RADEON_GMC_CLR_CMP_CNTL_DIS |
932 RADEON_GMC_WR_MSK_DIS);
e32eb50d
CK		 933 radeon_ring_write(ring, (pitch << 22) | (src_offset >> 10));
934 radeon_ring_write(ring, (pitch << 22) | (dst_offset >> 10));
935 radeon_ring_write(ring, (0x1fff) | (0x1fff << 16));
936 radeon_ring_write(ring, 0);
937 radeon_ring_write(ring, (0x1fff) | (0x1fff << 16));
938 radeon_ring_write(ring, num_gpu_pages);
939 radeon_ring_write(ring, num_gpu_pages);
940 radeon_ring_write(ring, cur_pages | (stride_pixels << 16));
941 }
942 radeon_ring_write(ring, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
943 radeon_ring_write(ring, RADEON_RB2D_DC_FLUSH_ALL);
944 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
945 radeon_ring_write(ring,
771fe6b9
JG		 946 RADEON_WAIT_2D_IDLECLEAN |
947 RADEON_WAIT_HOST_IDLECLEAN |
948 RADEON_WAIT_DMA_GUI_IDLE);
949 if (fence) {
950 r = radeon_fence_emit(rdev, fence);
951 }
e32eb50d 952 radeon_ring_unlock_commit(rdev, ring);
771fe6b9
JG		 953 return r;
954}
955
45600232
JG		 956static int r100_cp_wait_for_idle(struct radeon_device *rdev)
957{
958 unsigned i;
959 u32 tmp;
960
961 for (i = 0; i < rdev->usec_timeout; i++) {
962 tmp = RREG32(R_000E40_RBBM_STATUS);
963 if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) {
964 return 0;
965 }
966 udelay(1);
967 }
968 return -1;
969}
970
f712812e 971void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring)
771fe6b9
JG		 972{
973 int r;
974
e32eb50d 975 r = radeon_ring_lock(rdev, ring, 2);
771fe6b9
JG		 976 if (r) {
977 return;
978 }
e32eb50d
CK		 979 radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0));
980 radeon_ring_write(ring,
771fe6b9
JG		 981 RADEON_ISYNC_ANY2D_IDLE3D |
982 RADEON_ISYNC_ANY3D_IDLE2D |
983 RADEON_ISYNC_WAIT_IDLEGUI |
984 RADEON_ISYNC_CPSCRATCH_IDLEGUI);
e32eb50d 985 radeon_ring_unlock_commit(rdev, ring);
771fe6b9
JG		 986}
987
70967ab9
BH		 988
989/* Load the microcode for the CP */
990static int r100_cp_init_microcode(struct radeon_device *rdev)
771fe6b9 991{
70967ab9
BH		 992 struct platform_device *pdev;
993 const char *fw_name = NULL;
994 int err;
771fe6b9 995
d9fdaafb 996 DRM_DEBUG_KMS("\n");
771fe6b9 997
70967ab9
BH		 998 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
999 err = IS_ERR(pdev);
1000 if (err) {
1001 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
1002 return -EINVAL;
1003 }
771fe6b9
JG		 1004 if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) ||
1005 (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) ||
1006 (rdev->family == CHIP_RS200)) {
1007 DRM_INFO("Loading R100 Microcode\n");
70967ab9 1008 fw_name = FIRMWARE_R100;
771fe6b9
JG		 1009 } else if ((rdev->family == CHIP_R200) ||
1010 (rdev->family == CHIP_RV250) ||
1011 (rdev->family == CHIP_RV280) ||
1012 (rdev->family == CHIP_RS300)) {
1013 DRM_INFO("Loading R200 Microcode\n");
70967ab9 1014 fw_name = FIRMWARE_R200;
771fe6b9
JG		 1015 } else if ((rdev->family == CHIP_R300) ||
1016 (rdev->family == CHIP_R350) ||
1017 (rdev->family == CHIP_RV350) ||
1018 (rdev->family == CHIP_RV380) ||
1019 (rdev->family == CHIP_RS400) ||
1020 (rdev->family == CHIP_RS480)) {
1021 DRM_INFO("Loading R300 Microcode\n");
70967ab9 1022 fw_name = FIRMWARE_R300;
771fe6b9
JG		 1023 } else if ((rdev->family == CHIP_R420) ||
1024 (rdev->family == CHIP_R423) ||
1025 (rdev->family == CHIP_RV410)) {
1026 DRM_INFO("Loading R400 Microcode\n");
70967ab9 1027 fw_name = FIRMWARE_R420;
771fe6b9
JG		 1028 } else if ((rdev->family == CHIP_RS690) ||
1029 (rdev->family == CHIP_RS740)) {
1030 DRM_INFO("Loading RS690/RS740 Microcode\n");
70967ab9 1031 fw_name = FIRMWARE_RS690;
771fe6b9
JG		 1032 } else if (rdev->family == CHIP_RS600) {
1033 DRM_INFO("Loading RS600 Microcode\n");
70967ab9 1034 fw_name = FIRMWARE_RS600;
771fe6b9
JG		 1035 } else if ((rdev->family == CHIP_RV515) ||
1036 (rdev->family == CHIP_R520) ||
1037 (rdev->family == CHIP_RV530) ||
1038 (rdev->family == CHIP_R580) ||
1039 (rdev->family == CHIP_RV560) ||
1040 (rdev->family == CHIP_RV570)) {
1041 DRM_INFO("Loading R500 Microcode\n");
70967ab9
BH		 1042 fw_name = FIRMWARE_R520;
1043 }
1044
3ce0a23d 1045 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
70967ab9
BH		 1046 platform_device_unregister(pdev);
1047 if (err) {
1048 printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
1049 fw_name);
3ce0a23d 1050 } else if (rdev->me_fw->size % 8) {
70967ab9
BH		 1051 printk(KERN_ERR
1052 "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
3ce0a23d 1053 rdev->me_fw->size, fw_name);
70967ab9 1054 err = -EINVAL;
3ce0a23d
JG		 1055 release_firmware(rdev->me_fw);
1056 rdev->me_fw = NULL;
70967ab9
BH		 1057 }
1058 return err;
1059}
d4550907 1060
70967ab9
BH		 1061static void r100_cp_load_microcode(struct radeon_device *rdev)
1062{
1063 const __be32 *fw_data;
1064 int i, size;
1065
1066 if (r100_gui_wait_for_idle(rdev)) {
1067 printk(KERN_WARNING "Failed to wait GUI idle while "
1068 "programming pipes. Bad things might happen.\n");
1069 }
1070
3ce0a23d
JG		 1071 if (rdev->me_fw) {
1072 size = rdev->me_fw->size / 4;
1073 fw_data = (const __be32 *)&rdev->me_fw->data[0];
70967ab9
BH		 1074 WREG32(RADEON_CP_ME_RAM_ADDR, 0);
1075 for (i = 0; i < size; i += 2) {
1076 WREG32(RADEON_CP_ME_RAM_DATAH,
1077 be32_to_cpup(&fw_data[i]));
1078 WREG32(RADEON_CP_ME_RAM_DATAL,
1079 be32_to_cpup(&fw_data[i + 1]));
771fe6b9
JG		 1080 }
1081 }
1082}
1083
1084int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
1085{
e32eb50d 1086 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
771fe6b9
JG		 1087 unsigned rb_bufsz;
1088 unsigned rb_blksz;
1089 unsigned max_fetch;
1090 unsigned pre_write_timer;
1091 unsigned pre_write_limit;
1092 unsigned indirect2_start;
1093 unsigned indirect1_start;
1094 uint32_t tmp;
1095 int r;
1096
1097 if (r100_debugfs_cp_init(rdev)) {
1098 DRM_ERROR("Failed to register debugfs file for CP !\n");
1099 }
3ce0a23d 1100 if (!rdev->me_fw) {
70967ab9
BH		 1101 r = r100_cp_init_microcode(rdev);
1102 if (r) {
1103 DRM_ERROR("Failed to load firmware!\n");
1104 return r;
1105 }
1106 }
1107
771fe6b9
JG		 1108 /* Align ring size */
1109 rb_bufsz = drm_order(ring_size / 8);
1110 ring_size = (1 << (rb_bufsz + 1)) * 4;
1111 r100_cp_load_microcode(rdev);
e32eb50d 1112 r = radeon_ring_init(rdev, ring, ring_size, RADEON_WB_CP_RPTR_OFFSET,
78c5560a
AD		 1113 RADEON_CP_RB_RPTR, RADEON_CP_RB_WPTR,
1114 0, 0x7fffff, RADEON_CP_PACKET2);
771fe6b9
JG		 1115 if (r) {
1116 return r;
1117 }
1118 /* Each time the cp read 1024 bytes (16 dword/quadword) update
1119 * the rptr copy in system ram */
1120 rb_blksz = 9;
1121 /* cp will read 128bytes at a time (4 dwords) */
1122 max_fetch = 1;
e32eb50d 1123 ring->align_mask = 16 - 1;
771fe6b9
JG		 1124 /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
1125 pre_write_timer = 64;
1126 /* Force CP_RB_WPTR write if written more than one time before the
1127 * delay expire
1128 */
1129 pre_write_limit = 0;
1130 /* Setup the cp cache like this (cache size is 96 dwords) :
1131 * RING 0 to 15
1132 * INDIRECT1 16 to 79
1133 * INDIRECT2 80 to 95
1134 * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
1135 * indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
1136 * indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
1137 * Idea being that most of the gpu cmd will be through indirect1 buffer
1138 * so it gets the bigger cache.
1139 */
1140 indirect2_start = 80;
1141 indirect1_start = 16;
1142 /* cp setup */
1143 WREG32(0x718, pre_write_timer | (pre_write_limit << 28));
d6f28938 1144 tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
771fe6b9 1145 REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
724c80e1 1146 REG_SET(RADEON_MAX_FETCH, max_fetch));
d6f28938
AD		 1147#ifdef __BIG_ENDIAN
1148 tmp |= RADEON_BUF_SWAP_32BIT;
1149#endif
724c80e1 1150 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_NO_UPDATE);
d6f28938 1151
771fe6b9 1152 /* Set ring address */
e32eb50d
CK		 1153 DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)ring->gpu_addr);
1154 WREG32(RADEON_CP_RB_BASE, ring->gpu_addr);
771fe6b9 1155 /* Force read & write ptr to 0 */
724c80e1 1156 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA | RADEON_RB_NO_UPDATE);
771fe6b9 1157 WREG32(RADEON_CP_RB_RPTR_WR, 0);
e32eb50d
CK		 1158 ring->wptr = 0;
1159 WREG32(RADEON_CP_RB_WPTR, ring->wptr);
724c80e1
AD		 1160
1161 /* set the wb address whether it's enabled or not */
1162 WREG32(R_00070C_CP_RB_RPTR_ADDR,
1163 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) >> 2));
1164 WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET);
1165
1166 if (rdev->wb.enabled)
1167 WREG32(R_000770_SCRATCH_UMSK, 0xff);
1168 else {
1169 tmp |= RADEON_RB_NO_UPDATE;
1170 WREG32(R_000770_SCRATCH_UMSK, 0);
1171 }
1172
771fe6b9
JG		 1173 WREG32(RADEON_CP_RB_CNTL, tmp);
1174 udelay(10);
e32eb50d 1175 ring->rptr = RREG32(RADEON_CP_RB_RPTR);
771fe6b9
JG		 1176 /* Set cp mode to bus mastering & enable cp*/
1177 WREG32(RADEON_CP_CSQ_MODE,
1178 REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
1179 REG_SET(RADEON_INDIRECT1_START, indirect1_start));
d75ee3be
AD		 1180 WREG32(RADEON_CP_RB_WPTR_DELAY, 0);
1181 WREG32(RADEON_CP_CSQ_MODE, 0x00004D4D);
771fe6b9 1182 WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
2099810f
DA		 1183
1184 /* at this point everything should be setup correctly to enable master */
1185 pci_set_master(rdev->pdev);
1186
f712812e
AD		 1187 radeon_ring_start(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
1188 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
771fe6b9
JG		 1189 if (r) {
1190 DRM_ERROR("radeon: cp isn't working (%d).\n", r);
1191 return r;
1192 }
e32eb50d 1193 ring->ready = true;
53595338 1194 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
771fe6b9
JG		 1195 return 0;
1196}
1197
1198void r100_cp_fini(struct radeon_device *rdev)
1199{
45600232
JG		 1200 if (r100_cp_wait_for_idle(rdev)) {
1201 DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
1202 }
771fe6b9 1203 /* Disable ring */
a18d7ea1 1204 r100_cp_disable(rdev);
e32eb50d 1205 radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
771fe6b9
JG		 1206 DRM_INFO("radeon: cp finalized\n");
1207}
1208
1209void r100_cp_disable(struct radeon_device *rdev)
1210{
1211 /* Disable ring */
53595338 1212 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
e32eb50d 1213 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
771fe6b9
JG		 1214 WREG32(RADEON_CP_CSQ_MODE, 0);
1215 WREG32(RADEON_CP_CSQ_CNTL, 0);
724c80e1 1216 WREG32(R_000770_SCRATCH_UMSK, 0);
771fe6b9
JG		 1217 if (r100_gui_wait_for_idle(rdev)) {
1218 printk(KERN_WARNING "Failed to wait GUI idle while "
1219 "programming pipes. Bad things might happen.\n");
1220 }
1221}
1222
771fe6b9
JG		 1223/*
1224 * CS functions
1225 */
1226int r100_cs_parse_packet0(struct radeon_cs_parser *p,
1227 struct radeon_cs_packet *pkt,
068a117c 1228 const unsigned *auth, unsigned n,
771fe6b9
JG		 1229 radeon_packet0_check_t check)
1230{
1231 unsigned reg;
1232 unsigned i, j, m;
1233 unsigned idx;
1234 int r;
1235
1236 idx = pkt->idx + 1;
1237 reg = pkt->reg;
068a117c
JG		 1238 /* Check that register fall into register range
1239 * determined by the number of entry (n) in the
1240 * safe register bitmap.
1241 */
771fe6b9
JG		 1242 if (pkt->one_reg_wr) {
1243 if ((reg >> 7) > n) {
1244 return -EINVAL;
1245 }
1246 } else {
1247 if (((reg + (pkt->count << 2)) >> 7) > n) {
1248 return -EINVAL;
1249 }
1250 }
1251 for (i = 0; i <= pkt->count; i++, idx++) {
1252 j = (reg >> 7);
1253 m = 1 << ((reg >> 2) & 31);
1254 if (auth[j] & m) {
1255 r = check(p, pkt, idx, reg);
1256 if (r) {
1257 return r;
1258 }
1259 }
1260 if (pkt->one_reg_wr) {
1261 if (!(auth[j] & m)) {
1262 break;
1263 }
1264 } else {
1265 reg += 4;
1266 }
1267 }
1268 return 0;
1269}
1270
771fe6b9
JG		 1271void r100_cs_dump_packet(struct radeon_cs_parser *p,
1272 struct radeon_cs_packet *pkt)
1273{
771fe6b9
JG		 1274 volatile uint32_t *ib;
1275 unsigned i;
1276 unsigned idx;
1277
f2e39221 1278 ib = p->ib.ptr;
771fe6b9
JG		 1279 idx = pkt->idx;
1280 for (i = 0; i <= (pkt->count + 1); i++, idx++) {
1281 DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]);
1282 }
1283}
1284
1285/**
1286 * r100_cs_packet_parse() - parse cp packet and point ib index to next packet
1287 * @parser: parser structure holding parsing context.
1288 * @pkt: where to store packet informations
1289 *
1290 * Assume that chunk_ib_index is properly set. Will return -EINVAL
1291 * if packet is bigger than remaining ib size. or if packets is unknown.
1292 **/
1293int r100_cs_packet_parse(struct radeon_cs_parser *p,
1294 struct radeon_cs_packet *pkt,
1295 unsigned idx)
1296{
1297 struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
fa99239c 1298 uint32_t header;
771fe6b9
JG		 1299
1300 if (idx >= ib_chunk->length_dw) {
1301 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
1302 idx, ib_chunk->length_dw);
1303 return -EINVAL;
1304 }
513bcb46 1305 header = radeon_get_ib_value(p, idx);
771fe6b9
JG		 1306 pkt->idx = idx;
1307 pkt->type = CP_PACKET_GET_TYPE(header);
1308 pkt->count = CP_PACKET_GET_COUNT(header);
1309 switch (pkt->type) {
1310 case PACKET_TYPE0:
1311 pkt->reg = CP_PACKET0_GET_REG(header);
1312 pkt->one_reg_wr = CP_PACKET0_GET_ONE_REG_WR(header);
1313 break;
1314 case PACKET_TYPE3:
1315 pkt->opcode = CP_PACKET3_GET_OPCODE(header);
1316 break;
1317 case PACKET_TYPE2:
1318 pkt->count = -1;
1319 break;
1320 default:
1321 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
1322 return -EINVAL;
1323 }
1324 if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
1325 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
1326 pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
1327 return -EINVAL;
1328 }
1329 return 0;
1330}
1331
531369e6
DA		 1332/**
1333 * r100_cs_packet_next_vline() - parse userspace VLINE packet
1334 * @parser: parser structure holding parsing context.
1335 *
1336 * Userspace sends a special sequence for VLINE waits.
1337 * PACKET0 - VLINE_START_END + value
1338 * PACKET0 - WAIT_UNTIL +_value
1339 * RELOC (P3) - crtc_id in reloc.
1340 *
1341 * This function parses this and relocates the VLINE START END
1342 * and WAIT UNTIL packets to the correct crtc.
1343 * It also detects a switched off crtc and nulls out the
1344 * wait in that case.
1345 */
1346int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
1347{
531369e6
DA		 1348 struct drm_mode_object *obj;
1349 struct drm_crtc *crtc;
1350 struct radeon_crtc *radeon_crtc;
1351 struct radeon_cs_packet p3reloc, waitreloc;
1352 int crtc_id;
1353 int r;
1354 uint32_t header, h_idx, reg;
513bcb46 1355 volatile uint32_t *ib;
531369e6 1356
f2e39221 1357 ib = p->ib.ptr;
531369e6
DA		 1358
1359 /* parse the wait until */
1360 r = r100_cs_packet_parse(p, &waitreloc, p->idx);
1361 if (r)
1362 return r;
1363
1364 /* check its a wait until and only 1 count */
1365 if (waitreloc.reg != RADEON_WAIT_UNTIL ||
1366 waitreloc.count != 0) {
1367 DRM_ERROR("vline wait had illegal wait until segment\n");
a3a88a66 1368 return -EINVAL;
531369e6
DA		 1369 }
1370
513bcb46 1371 if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) {
531369e6 1372 DRM_ERROR("vline wait had illegal wait until\n");
a3a88a66 1373 return -EINVAL;
531369e6
DA		 1374 }
1375
1376 /* jump over the NOP */
90ebd065 1377 r = r100_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2);
531369e6
DA		 1378 if (r)
1379 return r;
1380
1381 h_idx = p->idx - 2;
90ebd065
AD		 1382 p->idx += waitreloc.count + 2;
1383 p->idx += p3reloc.count + 2;
531369e6 1384
513bcb46
DA		 1385 header = radeon_get_ib_value(p, h_idx);
1386 crtc_id = radeon_get_ib_value(p, h_idx + 5);
d4ac6a05 1387 reg = CP_PACKET0_GET_REG(header);
531369e6
DA		 1388 obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
1389 if (!obj) {
1390 DRM_ERROR("cannot find crtc %d\n", crtc_id);
a3a88a66 1391 return -EINVAL;
531369e6
DA		 1392 }
1393 crtc = obj_to_crtc(obj);
1394 radeon_crtc = to_radeon_crtc(crtc);
1395 crtc_id = radeon_crtc->crtc_id;
1396
1397 if (!crtc->enabled) {
1398 /* if the CRTC isn't enabled - we need to nop out the wait until */
513bcb46
DA		 1399 ib[h_idx + 2] = PACKET2(0);
1400 ib[h_idx + 3] = PACKET2(0);
531369e6
DA		 1401 } else if (crtc_id == 1) {
1402 switch (reg) {
1403 case AVIVO_D1MODE_VLINE_START_END:
90ebd065 1404 header &= ~R300_CP_PACKET0_REG_MASK;
531369e6
DA		 1405 header |= AVIVO_D2MODE_VLINE_START_END >> 2;
1406 break;
1407 case RADEON_CRTC_GUI_TRIG_VLINE:
90ebd065 1408 header &= ~R300_CP_PACKET0_REG_MASK;
531369e6
DA		 1409 header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2;
1410 break;
1411 default:
1412 DRM_ERROR("unknown crtc reloc\n");
a3a88a66 1413 return -EINVAL;
531369e6 1414 }
513bcb46
DA		 1415 ib[h_idx] = header;
1416 ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1;
531369e6 1417 }
a3a88a66
PB		 1418
1419 return 0;
531369e6
DA		 1420}
1421
771fe6b9
JG		 1422/**
1423 * r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3
1424 * @parser: parser structure holding parsing context.
1425 * @data: pointer to relocation data
1426 * @offset_start: starting offset
1427 * @offset_mask: offset mask (to align start offset on)
1428 * @reloc: reloc informations
1429 *
1430 * Check next packet is relocation packet3, do bo validation and compute
1431 * GPU offset using the provided start.
1432 **/
1433int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
1434 struct radeon_cs_reloc **cs_reloc)
1435{
771fe6b9
JG		 1436 struct radeon_cs_chunk *relocs_chunk;
1437 struct radeon_cs_packet p3reloc;
1438 unsigned idx;
1439 int r;
1440
1441 if (p->chunk_relocs_idx == -1) {
1442 DRM_ERROR("No relocation chunk !\n");
1443 return -EINVAL;
1444 }
1445 *cs_reloc = NULL;
771fe6b9
JG		 1446 relocs_chunk = &p->chunks[p->chunk_relocs_idx];
1447 r = r100_cs_packet_parse(p, &p3reloc, p->idx);
1448 if (r) {
1449 return r;
1450 }
1451 p->idx += p3reloc.count + 2;
1452 if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
1453 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
1454 p3reloc.idx);
1455 r100_cs_dump_packet(p, &p3reloc);
1456 return -EINVAL;
1457 }
513bcb46 1458 idx = radeon_get_ib_value(p, p3reloc.idx + 1);
771fe6b9
JG		 1459 if (idx >= relocs_chunk->length_dw) {
1460 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
1461 idx, relocs_chunk->length_dw);
1462 r100_cs_dump_packet(p, &p3reloc);
1463 return -EINVAL;
1464 }
1465 /* FIXME: we assume reloc size is 4 dwords */
1466 *cs_reloc = p->relocs_ptr[(idx / 4)];
1467 return 0;
1468}
1469
551ebd83
DA		 1470static int r100_get_vtx_size(uint32_t vtx_fmt)
1471{
1472 int vtx_size;
1473 vtx_size = 2;
1474 /* ordered according to bits in spec */
1475 if (vtx_fmt & RADEON_SE_VTX_FMT_W0)
1476 vtx_size++;
1477 if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR)
1478 vtx_size += 3;
1479 if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA)
1480 vtx_size++;
1481 if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR)
1482 vtx_size++;
1483 if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC)
1484 vtx_size += 3;
1485 if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG)
1486 vtx_size++;
1487 if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC)
1488 vtx_size++;
1489 if (vtx_fmt & RADEON_SE_VTX_FMT_ST0)
1490 vtx_size += 2;
1491 if (vtx_fmt & RADEON_SE_VTX_FMT_ST1)
1492 vtx_size += 2;
1493 if (vtx_fmt & RADEON_SE_VTX_FMT_Q1)
1494 vtx_size++;
1495 if (vtx_fmt & RADEON_SE_VTX_FMT_ST2)
1496 vtx_size += 2;
1497 if (vtx_fmt & RADEON_SE_VTX_FMT_Q2)
1498 vtx_size++;
1499 if (vtx_fmt & RADEON_SE_VTX_FMT_ST3)
1500 vtx_size += 2;
1501 if (vtx_fmt & RADEON_SE_VTX_FMT_Q3)
1502 vtx_size++;
1503 if (vtx_fmt & RADEON_SE_VTX_FMT_Q0)
1504 vtx_size++;
1505 /* blend weight */
1506 if (vtx_fmt & (0x7 << 15))
1507 vtx_size += (vtx_fmt >> 15) & 0x7;
1508 if (vtx_fmt & RADEON_SE_VTX_FMT_N0)
1509 vtx_size += 3;
1510 if (vtx_fmt & RADEON_SE_VTX_FMT_XY1)
1511 vtx_size += 2;
1512 if (vtx_fmt & RADEON_SE_VTX_FMT_Z1)
1513 vtx_size++;
1514 if (vtx_fmt & RADEON_SE_VTX_FMT_W1)
1515 vtx_size++;
1516 if (vtx_fmt & RADEON_SE_VTX_FMT_N1)
1517 vtx_size++;
1518 if (vtx_fmt & RADEON_SE_VTX_FMT_Z)
1519 vtx_size++;
1520 return vtx_size;
1521}
1522
771fe6b9 1523static int r100_packet0_check(struct radeon_cs_parser *p,
551ebd83
DA		 1524 struct radeon_cs_packet *pkt,
1525 unsigned idx, unsigned reg)
771fe6b9 1526{
771fe6b9 1527 struct radeon_cs_reloc *reloc;
551ebd83 1528 struct r100_cs_track *track;
771fe6b9
JG		 1529 volatile uint32_t *ib;
1530 uint32_t tmp;
771fe6b9 1531 int r;
551ebd83 1532 int i, face;
e024e110 1533 u32 tile_flags = 0;
513bcb46 1534 u32 idx_value;
771fe6b9 1535
f2e39221 1536 ib = p->ib.ptr;
551ebd83
DA		 1537 track = (struct r100_cs_track *)p->track;
1538
513bcb46
DA		 1539 idx_value = radeon_get_ib_value(p, idx);
1540
551ebd83
DA		 1541 switch (reg) {
1542 case RADEON_CRTC_GUI_TRIG_VLINE:
1543 r = r100_cs_packet_parse_vline(p);
1544 if (r) {
1545 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1546 idx, reg);
1547 r100_cs_dump_packet(p, pkt);
1548 return r;
1549 }
1550 break;
771fe6b9
JG		 1551 /* FIXME: only allow PACKET3 blit? easier to check for out of
1552 * range access */
551ebd83
DA		 1553 case RADEON_DST_PITCH_OFFSET:
1554 case RADEON_SRC_PITCH_OFFSET:
1555 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
1556 if (r)
1557 return r;
1558 break;
1559 case RADEON_RB3D_DEPTHOFFSET:
1560 r = r100_cs_packet_next_reloc(p, &reloc);
1561 if (r) {
1562 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1563 idx, reg);
1564 r100_cs_dump_packet(p, pkt);
1565 return r;
1566 }
1567 track->zb.robj = reloc->robj;
513bcb46 1568 track->zb.offset = idx_value;
40b4a759 1569 track->zb_dirty = true;
513bcb46 1570 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83
DA		 1571 break;
1572 case RADEON_RB3D_COLOROFFSET:
1573 r = r100_cs_packet_next_reloc(p, &reloc);
1574 if (r) {
1575 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1576 idx, reg);
1577 r100_cs_dump_packet(p, pkt);
1578 return r;
1579 }
1580 track->cb[0].robj = reloc->robj;
513bcb46 1581 track->cb[0].offset = idx_value;
40b4a759 1582 track->cb_dirty = true;
513bcb46 1583 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83
DA		 1584 break;
1585 case RADEON_PP_TXOFFSET_0:
1586 case RADEON_PP_TXOFFSET_1:
1587 case RADEON_PP_TXOFFSET_2:
1588 i = (reg - RADEON_PP_TXOFFSET_0) / 24;
1589 r = r100_cs_packet_next_reloc(p, &reloc);
1590 if (r) {
1591 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1592 idx, reg);
1593 r100_cs_dump_packet(p, pkt);
1594 return r;
1595 }
f2746f83
AD		 1596 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1597 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1598 tile_flags |= RADEON_TXO_MACRO_TILE;
1599 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1600 tile_flags |= RADEON_TXO_MICRO_TILE_X2;
1601
1602 tmp = idx_value & ~(0x7 << 2);
1603 tmp |= tile_flags;
1604 ib[idx] = tmp + ((u32)reloc->lobj.gpu_offset);
1605 } else
1606 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83 1607 track->textures[i].robj = reloc->robj;
40b4a759 1608 track->tex_dirty = true;
551ebd83
DA		 1609 break;
1610 case RADEON_PP_CUBIC_OFFSET_T0_0:
1611 case RADEON_PP_CUBIC_OFFSET_T0_1:
1612 case RADEON_PP_CUBIC_OFFSET_T0_2:
1613 case RADEON_PP_CUBIC_OFFSET_T0_3:
1614 case RADEON_PP_CUBIC_OFFSET_T0_4:
1615 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
1616 r = r100_cs_packet_next_reloc(p, &reloc);
1617 if (r) {
1618 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1619 idx, reg);
1620 r100_cs_dump_packet(p, pkt);
1621 return r;
1622 }
513bcb46
DA		 1623 track->textures[0].cube_info[i].offset = idx_value;
1624 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83 1625 track->textures[0].cube_info[i].robj = reloc->robj;
40b4a759 1626 track->tex_dirty = true;
551ebd83
DA		 1627 break;
1628 case RADEON_PP_CUBIC_OFFSET_T1_0:
1629 case RADEON_PP_CUBIC_OFFSET_T1_1:
1630 case RADEON_PP_CUBIC_OFFSET_T1_2:
1631 case RADEON_PP_CUBIC_OFFSET_T1_3:
1632 case RADEON_PP_CUBIC_OFFSET_T1_4:
1633 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
1634 r = r100_cs_packet_next_reloc(p, &reloc);
1635 if (r) {
1636 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1637 idx, reg);
1638 r100_cs_dump_packet(p, pkt);
1639 return r;
1640 }
513bcb46
DA		 1641 track->textures[1].cube_info[i].offset = idx_value;
1642 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83 1643 track->textures[1].cube_info[i].robj = reloc->robj;
40b4a759 1644 track->tex_dirty = true;
551ebd83
DA		 1645 break;
1646 case RADEON_PP_CUBIC_OFFSET_T2_0:
1647 case RADEON_PP_CUBIC_OFFSET_T2_1:
1648 case RADEON_PP_CUBIC_OFFSET_T2_2:
1649 case RADEON_PP_CUBIC_OFFSET_T2_3:
1650 case RADEON_PP_CUBIC_OFFSET_T2_4:
1651 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
1652 r = r100_cs_packet_next_reloc(p, &reloc);
1653 if (r) {
1654 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1655 idx, reg);
1656 r100_cs_dump_packet(p, pkt);
1657 return r;
1658 }
513bcb46
DA		 1659 track->textures[2].cube_info[i].offset = idx_value;
1660 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83 1661 track->textures[2].cube_info[i].robj = reloc->robj;
40b4a759 1662 track->tex_dirty = true;
551ebd83
DA		 1663 break;
1664 case RADEON_RE_WIDTH_HEIGHT:
513bcb46 1665 track->maxy = ((idx_value >> 16) & 0x7FF);
40b4a759
MO		 1666 track->cb_dirty = true;
1667 track->zb_dirty = true;
551ebd83
DA		 1668 break;
1669 case RADEON_RB3D_COLORPITCH:
1670 r = r100_cs_packet_next_reloc(p, &reloc);
1671 if (r) {
1672 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1673 idx, reg);
1674 r100_cs_dump_packet(p, pkt);
1675 return r;
1676 }
c9068eb2
AD		 1677 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1678 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1679 tile_flags |= RADEON_COLOR_TILE_ENABLE;
1680 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1681 tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
1682
1683 tmp = idx_value & ~(0x7 << 16);
1684 tmp |= tile_flags;
1685 ib[idx] = tmp;
1686 } else
1687 ib[idx] = idx_value;
e024e110 1688
513bcb46 1689 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
40b4a759 1690 track->cb_dirty = true;
551ebd83
DA		 1691 break;
1692 case RADEON_RB3D_DEPTHPITCH:
513bcb46 1693 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
40b4a759 1694 track->zb_dirty = true;
551ebd83
DA		 1695 break;
1696 case RADEON_RB3D_CNTL:
513bcb46 1697 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
551ebd83
DA		 1698 case 7:
1699 case 8:
1700 case 9:
1701 case 11:
1702 case 12:
1703 track->cb[0].cpp = 1;
e024e110 1704 break;
551ebd83
DA		 1705 case 3:
1706 case 4:
1707 case 15:
1708 track->cb[0].cpp = 2;
1709 break;
1710 case 6:
1711 track->cb[0].cpp = 4;
1712 break;
1713 default:
1714 DRM_ERROR("Invalid color buffer format (%d) !\n",
513bcb46 1715 ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
551ebd83
DA		 1716 return -EINVAL;
1717 }
513bcb46 1718 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
40b4a759
MO		 1719 track->cb_dirty = true;
1720 track->zb_dirty = true;
551ebd83
DA		 1721 break;
1722 case RADEON_RB3D_ZSTENCILCNTL:
513bcb46 1723 switch (idx_value & 0xf) {
551ebd83
DA		 1724 case 0:
1725 track->zb.cpp = 2;
1726 break;
1727 case 2:
1728 case 3:
1729 case 4:
1730 case 5:
1731 case 9:
1732 case 11:
1733 track->zb.cpp = 4;
17782d99 1734 break;
771fe6b9 1735 default:
771fe6b9
JG		 1736 break;
1737 }
40b4a759 1738 track->zb_dirty = true;
551ebd83
DA		 1739 break;
1740 case RADEON_RB3D_ZPASS_ADDR:
1741 r = r100_cs_packet_next_reloc(p, &reloc);
1742 if (r) {
1743 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1744 idx, reg);
1745 r100_cs_dump_packet(p, pkt);
1746 return r;
1747 }
513bcb46 1748 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83
DA		 1749 break;
1750 case RADEON_PP_CNTL:
1751 {
513bcb46 1752 uint32_t temp = idx_value >> 4;
551ebd83
DA		 1753 for (i = 0; i < track->num_texture; i++)
1754 track->textures[i].enabled = !!(temp & (1 << i));
40b4a759 1755 track->tex_dirty = true;
551ebd83
DA		 1756 }
1757 break;
1758 case RADEON_SE_VF_CNTL:
513bcb46 1759 track->vap_vf_cntl = idx_value;
551ebd83
DA		 1760 break;
1761 case RADEON_SE_VTX_FMT:
513bcb46 1762 track->vtx_size = r100_get_vtx_size(idx_value);
551ebd83
DA		 1763 break;
1764 case RADEON_PP_TEX_SIZE_0:
1765 case RADEON_PP_TEX_SIZE_1:
1766 case RADEON_PP_TEX_SIZE_2:
1767 i = (reg - RADEON_PP_TEX_SIZE_0) / 8;
513bcb46
DA		 1768 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
1769 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
40b4a759 1770 track->tex_dirty = true;
551ebd83
DA		 1771 break;
1772 case RADEON_PP_TEX_PITCH_0:
1773 case RADEON_PP_TEX_PITCH_1:
1774 case RADEON_PP_TEX_PITCH_2:
1775 i = (reg - RADEON_PP_TEX_PITCH_0) / 8;
513bcb46 1776 track->textures[i].pitch = idx_value + 32;
40b4a759 1777 track->tex_dirty = true;
551ebd83
DA		 1778 break;
1779 case RADEON_PP_TXFILTER_0:
1780 case RADEON_PP_TXFILTER_1:
1781 case RADEON_PP_TXFILTER_2:
1782 i = (reg - RADEON_PP_TXFILTER_0) / 24;
513bcb46 1783 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK)
551ebd83 1784 >> RADEON_MAX_MIP_LEVEL_SHIFT);
513bcb46 1785 tmp = (idx_value >> 23) & 0x7;
551ebd83
DA		 1786 if (tmp == 2 || tmp == 6)
1787 track->textures[i].roundup_w = false;
513bcb46 1788 tmp = (idx_value >> 27) & 0x7;
551ebd83
DA		 1789 if (tmp == 2 || tmp == 6)
1790 track->textures[i].roundup_h = false;
40b4a759 1791 track->tex_dirty = true;
551ebd83
DA		 1792 break;
1793 case RADEON_PP_TXFORMAT_0:
1794 case RADEON_PP_TXFORMAT_1:
1795 case RADEON_PP_TXFORMAT_2:
1796 i = (reg - RADEON_PP_TXFORMAT_0) / 24;
513bcb46 1797 if (idx_value & RADEON_TXFORMAT_NON_POWER2) {
551ebd83
DA		 1798 track->textures[i].use_pitch = 1;
1799 } else {
1800 track->textures[i].use_pitch = 0;
513bcb46
DA		 1801 track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
1802 track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
551ebd83 1803 }
513bcb46 1804 if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE)
551ebd83 1805 track->textures[i].tex_coord_type = 2;
513bcb46 1806 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
551ebd83
DA		 1807 case RADEON_TXFORMAT_I8:
1808 case RADEON_TXFORMAT_RGB332:
1809 case RADEON_TXFORMAT_Y8:
1810 track->textures[i].cpp = 1;
f9da52d5 1811 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
551ebd83
DA		 1812 break;
1813 case RADEON_TXFORMAT_AI88:
1814 case RADEON_TXFORMAT_ARGB1555:
1815 case RADEON_TXFORMAT_RGB565:
1816 case RADEON_TXFORMAT_ARGB4444:
1817 case RADEON_TXFORMAT_VYUY422:
1818 case RADEON_TXFORMAT_YVYU422:
551ebd83
DA		 1819 case RADEON_TXFORMAT_SHADOW16:
1820 case RADEON_TXFORMAT_LDUDV655:
1821 case RADEON_TXFORMAT_DUDV88:
1822 track->textures[i].cpp = 2;
f9da52d5 1823 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
771fe6b9 1824 break;
551ebd83
DA		 1825 case RADEON_TXFORMAT_ARGB8888:
1826 case RADEON_TXFORMAT_RGBA8888:
551ebd83
DA		 1827 case RADEON_TXFORMAT_SHADOW32:
1828 case RADEON_TXFORMAT_LDUDUV8888:
1829 track->textures[i].cpp = 4;
f9da52d5 1830 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
551ebd83 1831 break;
d785d78b
DA		 1832 case RADEON_TXFORMAT_DXT1:
1833 track->textures[i].cpp = 1;
1834 track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
1835 break;
1836 case RADEON_TXFORMAT_DXT23:
1837 case RADEON_TXFORMAT_DXT45:
1838 track->textures[i].cpp = 1;
1839 track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
1840 break;
551ebd83 1841 }
513bcb46
DA		 1842 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
1843 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
40b4a759 1844 track->tex_dirty = true;
551ebd83
DA		 1845 break;
1846 case RADEON_PP_CUBIC_FACES_0:
1847 case RADEON_PP_CUBIC_FACES_1:
1848 case RADEON_PP_CUBIC_FACES_2:
513bcb46 1849 tmp = idx_value;
551ebd83
DA		 1850 i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;
1851 for (face = 0; face < 4; face++) {
1852 track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
1853 track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
771fe6b9 1854 }
40b4a759 1855 track->tex_dirty = true;
551ebd83
DA		 1856 break;
1857 default:
1858 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1859 reg, idx);
1860 return -EINVAL;
771fe6b9
JG		 1861 }
1862 return 0;
1863}
1864
068a117c
JG		 1865int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1866 struct radeon_cs_packet *pkt,
4c788679 1867 struct radeon_bo *robj)
068a117c 1868{
068a117c 1869 unsigned idx;
513bcb46 1870 u32 value;
068a117c 1871 idx = pkt->idx + 1;
513bcb46 1872 value = radeon_get_ib_value(p, idx + 2);
4c788679 1873 if ((value + 1) > radeon_bo_size(robj)) {
068a117c
JG		 1874 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
1875 "(need %u have %lu) !\n",
513bcb46 1876 value + 1,
4c788679 1877 radeon_bo_size(robj));
068a117c
JG		 1878 return -EINVAL;
1879 }
1880 return 0;
1881}
1882
771fe6b9
JG		 1883static int r100_packet3_check(struct radeon_cs_parser *p,
1884 struct radeon_cs_packet *pkt)
1885{
771fe6b9 1886 struct radeon_cs_reloc *reloc;
551ebd83 1887 struct r100_cs_track *track;
771fe6b9 1888 unsigned idx;
771fe6b9
JG		 1889 volatile uint32_t *ib;
1890 int r;
1891
f2e39221 1892 ib = p->ib.ptr;
771fe6b9 1893 idx = pkt->idx + 1;
551ebd83 1894 track = (struct r100_cs_track *)p->track;
771fe6b9
JG		 1895 switch (pkt->opcode) {
1896 case PACKET3_3D_LOAD_VBPNTR:
513bcb46
DA		 1897 r = r100_packet3_load_vbpntr(p, pkt, idx);
1898 if (r)
1899 return r;
771fe6b9
JG		 1900 break;
1901 case PACKET3_INDX_BUFFER:
1902 r = r100_cs_packet_next_reloc(p, &reloc);
1903 if (r) {
1904 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1905 r100_cs_dump_packet(p, pkt);
1906 return r;
1907 }
513bcb46 1908 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset);
068a117c
JG		 1909 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1910 if (r) {
1911 return r;
1912 }
771fe6b9
JG		 1913 break;
1914 case 0x23:
771fe6b9
JG		 1915 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
1916 r = r100_cs_packet_next_reloc(p, &reloc);
1917 if (r) {
1918 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1919 r100_cs_dump_packet(p, pkt);
1920 return r;
1921 }
513bcb46 1922 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset);
551ebd83 1923 track->num_arrays = 1;
513bcb46 1924 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2));
551ebd83
DA		 1925
1926 track->arrays[0].robj = reloc->robj;
1927 track->arrays[0].esize = track->vtx_size;
1928
513bcb46 1929 track->max_indx = radeon_get_ib_value(p, idx+1);
551ebd83 1930
513bcb46 1931 track->vap_vf_cntl = radeon_get_ib_value(p, idx+3);
551ebd83
DA		 1932 track->immd_dwords = pkt->count - 1;
1933 r = r100_cs_track_check(p->rdev, track);
1934 if (r)
1935 return r;
771fe6b9
JG		 1936 break;
1937 case PACKET3_3D_DRAW_IMMD:
513bcb46 1938 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
551ebd83
DA		 1939 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1940 return -EINVAL;
1941 }
cf57fc7a 1942 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0));
513bcb46 1943 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
551ebd83
DA		 1944 track->immd_dwords = pkt->count - 1;
1945 r = r100_cs_track_check(p->rdev, track);
1946 if (r)
1947 return r;
1948 break;
771fe6b9
JG		 1949 /* triggers drawing using in-packet vertex data */
1950 case PACKET3_3D_DRAW_IMMD_2:
513bcb46 1951 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
551ebd83
DA		 1952 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1953 return -EINVAL;
1954 }
513bcb46 1955 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
551ebd83
DA		 1956 track->immd_dwords = pkt->count;
1957 r = r100_cs_track_check(p->rdev, track);
1958 if (r)
1959 return r;
1960 break;
771fe6b9
JG		 1961 /* triggers drawing using in-packet vertex data */
1962 case PACKET3_3D_DRAW_VBUF_2:
513bcb46 1963 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
551ebd83
DA		 1964 r = r100_cs_track_check(p->rdev, track);
1965 if (r)
1966 return r;
1967 break;
771fe6b9
JG		 1968 /* triggers drawing of vertex buffers setup elsewhere */
1969 case PACKET3_3D_DRAW_INDX_2:
513bcb46 1970 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
551ebd83
DA		 1971 r = r100_cs_track_check(p->rdev, track);
1972 if (r)
1973 return r;
1974 break;
771fe6b9
JG		 1975 /* triggers drawing using indices to vertex buffer */
1976 case PACKET3_3D_DRAW_VBUF:
513bcb46 1977 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
551ebd83
DA		 1978 r = r100_cs_track_check(p->rdev, track);
1979 if (r)
1980 return r;
1981 break;
771fe6b9
JG		 1982 /* triggers drawing of vertex buffers setup elsewhere */
1983 case PACKET3_3D_DRAW_INDX:
513bcb46 1984 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
551ebd83
DA		 1985 r = r100_cs_track_check(p->rdev, track);
1986 if (r)
1987 return r;
1988 break;
771fe6b9 1989 /* triggers drawing using indices to vertex buffer */
ab9e1f59
DA		 1990 case PACKET3_3D_CLEAR_HIZ:
1991 case PACKET3_3D_CLEAR_ZMASK:
1992 if (p->rdev->hyperz_filp != p->filp)
1993 return -EINVAL;
1994 break;
771fe6b9
JG		 1995 case PACKET3_NOP:
1996 break;
1997 default:
1998 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1999 return -EINVAL;
2000 }
2001 return 0;
2002}
2003
2004int r100_cs_parse(struct radeon_cs_parser *p)
2005{
2006 struct radeon_cs_packet pkt;
9f022ddf 2007 struct r100_cs_track *track;
771fe6b9
JG		 2008 int r;
2009
9f022ddf
JG		 2010 track = kzalloc(sizeof(*track), GFP_KERNEL);
2011 r100_cs_track_clear(p->rdev, track);
2012 p->track = track;
771fe6b9
JG		 2013 do {
2014 r = r100_cs_packet_parse(p, &pkt, p->idx);
2015 if (r) {
2016 return r;
2017 }
2018 p->idx += pkt.count + 2;
2019 switch (pkt.type) {
068a117c 2020 case PACKET_TYPE0:
551ebd83
DA		 2021 if (p->rdev->family >= CHIP_R200)
2022 r = r100_cs_parse_packet0(p, &pkt,
2023 p->rdev->config.r100.reg_safe_bm,
2024 p->rdev->config.r100.reg_safe_bm_size,
2025 &r200_packet0_check);
2026 else
2027 r = r100_cs_parse_packet0(p, &pkt,
2028 p->rdev->config.r100.reg_safe_bm,
2029 p->rdev->config.r100.reg_safe_bm_size,
2030 &r100_packet0_check);
068a117c
JG		 2031 break;
2032 case PACKET_TYPE2:
2033 break;
2034 case PACKET_TYPE3:
2035 r = r100_packet3_check(p, &pkt);
2036 break;
2037 default:
2038 DRM_ERROR("Unknown packet type %d !\n",
2039 pkt.type);
2040 return -EINVAL;
771fe6b9
JG		 2041 }
2042 if (r) {
2043 return r;
2044 }
2045 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
2046 return 0;
2047}
2048
2049
2050/*
2051 * Global GPU functions
2052 */
2053void r100_errata(struct radeon_device *rdev)
2054{
2055 rdev->pll_errata = 0;
2056
2057 if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) {
2058 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS;
2059 }
2060
2061 if (rdev->family == CHIP_RV100 ||
2062 rdev->family == CHIP_RS100 ||
2063 rdev->family == CHIP_RS200) {
2064 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY;
2065 }
2066}
2067
2068/* Wait for vertical sync on primary CRTC */
2069void r100_gpu_wait_for_vsync(struct radeon_device *rdev)
2070{
2071 uint32_t crtc_gen_cntl, tmp;
2072 int i;
2073
2074 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
2075 if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) ||
2076 !(crtc_gen_cntl & RADEON_CRTC_EN)) {
2077 return;
2078 }
2079 /* Clear the CRTC_VBLANK_SAVE bit */
2080 WREG32(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR);
2081 for (i = 0; i < rdev->usec_timeout; i++) {
2082 tmp = RREG32(RADEON_CRTC_STATUS);
2083 if (tmp & RADEON_CRTC_VBLANK_SAVE) {
2084 return;
2085 }
2086 DRM_UDELAY(1);
2087 }
2088}
2089
2090/* Wait for vertical sync on secondary CRTC */
2091void r100_gpu_wait_for_vsync2(struct radeon_device *rdev)
2092{
2093 uint32_t crtc2_gen_cntl, tmp;
2094 int i;
2095
2096 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
2097 if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) ||
2098 !(crtc2_gen_cntl & RADEON_CRTC2_EN))
2099 return;
2100
2101 /* Clear the CRTC_VBLANK_SAVE bit */
2102 WREG32(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR);
2103 for (i = 0; i < rdev->usec_timeout; i++) {
2104 tmp = RREG32(RADEON_CRTC2_STATUS);
2105 if (tmp & RADEON_CRTC2_VBLANK_SAVE) {
2106 return;
2107 }
2108 DRM_UDELAY(1);
2109 }
2110}
2111
2112int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
2113{
2114 unsigned i;
2115 uint32_t tmp;
2116
2117 for (i = 0; i < rdev->usec_timeout; i++) {
2118 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
2119 if (tmp >= n) {
2120 return 0;
2121 }
2122 DRM_UDELAY(1);
2123 }
2124 return -1;
2125}
2126
2127int r100_gui_wait_for_idle(struct radeon_device *rdev)
2128{
2129 unsigned i;
2130 uint32_t tmp;
2131
2132 if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
2133 printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !"
2134 " Bad things might happen.\n");
2135 }
2136 for (i = 0; i < rdev->usec_timeout; i++) {
2137 tmp = RREG32(RADEON_RBBM_STATUS);
4612dc97 2138 if (!(tmp & RADEON_RBBM_ACTIVE)) {
771fe6b9
JG		 2139 return 0;
2140 }
2141 DRM_UDELAY(1);
2142 }
2143 return -1;
2144}
2145
2146int r100_mc_wait_for_idle(struct radeon_device *rdev)
2147{
2148 unsigned i;
2149 uint32_t tmp;
2150
2151 for (i = 0; i < rdev->usec_timeout; i++) {
2152 /* read MC_STATUS */
4612dc97
AD		 2153 tmp = RREG32(RADEON_MC_STATUS);
2154 if (tmp & RADEON_MC_IDLE) {
771fe6b9
JG		 2155 return 0;
2156 }
2157 DRM_UDELAY(1);
2158 }
2159 return -1;
2160}
2161
e32eb50d 2162bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
771fe6b9 2163{
225758d8 2164 u32 rbbm_status;
771fe6b9 2165
225758d8
JG		 2166 rbbm_status = RREG32(R_000E40_RBBM_STATUS);
2167 if (!G_000E40_GUI_ACTIVE(rbbm_status)) {
069211e5 2168 radeon_ring_lockup_update(ring);
225758d8
JG		 2169 return false;
2170 }
2171 /* force CP activities */
7b9ef16b 2172 radeon_ring_force_activity(rdev, ring);
069211e5 2173 return radeon_ring_test_lockup(rdev, ring);
771fe6b9
JG		 2174}
2175
90aca4d2 2176void r100_bm_disable(struct radeon_device *rdev)
771fe6b9 2177{
90aca4d2 2178 u32 tmp;
771fe6b9 2179
90aca4d2
JG		 2180 /* disable bus mastering */
2181 tmp = RREG32(R_000030_BUS_CNTL);
2182 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000044);
2183 mdelay(1);
2184 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000042);
2185 mdelay(1);
2186 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000040);
2187 tmp = RREG32(RADEON_BUS_CNTL);
2188 mdelay(1);
642ce525 2189 pci_clear_master(rdev->pdev);
771fe6b9 2190 mdelay(1);
771fe6b9
JG		 2191}
2192
a2d07b74 2193int r100_asic_reset(struct radeon_device *rdev)
771fe6b9 2194{
90aca4d2
JG		 2195 struct r100_mc_save save;
2196 u32 status, tmp;
25b2ec5b 2197 int ret = 0;
771fe6b9 2198
90aca4d2
JG		 2199 status = RREG32(R_000E40_RBBM_STATUS);
2200 if (!G_000E40_GUI_ACTIVE(status)) {
2201 return 0;
771fe6b9 2202 }
25b2ec5b 2203 r100_mc_stop(rdev, &save);
90aca4d2
JG		 2204 status = RREG32(R_000E40_RBBM_STATUS);
2205 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2206 /* stop CP */
2207 WREG32(RADEON_CP_CSQ_CNTL, 0);
2208 tmp = RREG32(RADEON_CP_RB_CNTL);
2209 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
2210 WREG32(RADEON_CP_RB_RPTR_WR, 0);
2211 WREG32(RADEON_CP_RB_WPTR, 0);
2212 WREG32(RADEON_CP_RB_CNTL, tmp);
2213 /* save PCI state */
2214 pci_save_state(rdev->pdev);
2215 /* disable bus mastering */
2216 r100_bm_disable(rdev);
2217 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_SE(1) |
2218 S_0000F0_SOFT_RESET_RE(1) |
2219 S_0000F0_SOFT_RESET_PP(1) |
2220 S_0000F0_SOFT_RESET_RB(1));
2221 RREG32(R_0000F0_RBBM_SOFT_RESET);
2222 mdelay(500);
2223 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2224 mdelay(1);
2225 status = RREG32(R_000E40_RBBM_STATUS);
2226 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
771fe6b9 2227 /* reset CP */
90aca4d2
JG		 2228 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
2229 RREG32(R_0000F0_RBBM_SOFT_RESET);
2230 mdelay(500);
2231 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2232 mdelay(1);
2233 status = RREG32(R_000E40_RBBM_STATUS);
2234 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2235 /* restore PCI & busmastering */
2236 pci_restore_state(rdev->pdev);
2237 r100_enable_bm(rdev);
771fe6b9 2238 /* Check if GPU is idle */
90aca4d2
JG		 2239 if (G_000E40_SE_BUSY(status) || G_000E40_RE_BUSY(status) ||
2240 G_000E40_TAM_BUSY(status) || G_000E40_PB_BUSY(status)) {
2241 dev_err(rdev->dev, "failed to reset GPU\n");
25b2ec5b
AD		 2242 ret = -1;
2243 } else
2244 dev_info(rdev->dev, "GPU reset succeed\n");
90aca4d2 2245 r100_mc_resume(rdev, &save);
25b2ec5b 2246 return ret;
771fe6b9
JG		 2247}
2248
92cde00c
AD		 2249void r100_set_common_regs(struct radeon_device *rdev)
2250{
2739d49c
AD		 2251 struct drm_device *dev = rdev->ddev;
2252 bool force_dac2 = false;
d668046c 2253 u32 tmp;
2739d49c 2254
92cde00c
AD		 2255 /* set these so they don't interfere with anything */
2256 WREG32(RADEON_OV0_SCALE_CNTL, 0);
2257 WREG32(RADEON_SUBPIC_CNTL, 0);
2258 WREG32(RADEON_VIPH_CONTROL, 0);
2259 WREG32(RADEON_I2C_CNTL_1, 0);
2260 WREG32(RADEON_DVI_I2C_CNTL_1, 0);
2261 WREG32(RADEON_CAP0_TRIG_CNTL, 0);
2262 WREG32(RADEON_CAP1_TRIG_CNTL, 0);
2739d49c
AD		 2263
2264 /* always set up dac2 on rn50 and some rv100 as lots
2265 * of servers seem to wire it up to a VGA port but
2266 * don't report it in the bios connector
2267 * table.
2268 */
2269 switch (dev->pdev->device) {
2270 /* RN50 */
2271 case 0x515e:
2272 case 0x5969:
2273 force_dac2 = true;
2274 break;
2275 /* RV100*/
2276 case 0x5159:
2277 case 0x515a:
2278 /* DELL triple head servers */
2279 if ((dev->pdev->subsystem_vendor == 0x1028 /* DELL */) &&
2280 ((dev->pdev->subsystem_device == 0x016c) ||
2281 (dev->pdev->subsystem_device == 0x016d) ||
2282 (dev->pdev->subsystem_device == 0x016e) ||
2283 (dev->pdev->subsystem_device == 0x016f) ||
2284 (dev->pdev->subsystem_device == 0x0170) ||
2285 (dev->pdev->subsystem_device == 0x017d) ||
2286 (dev->pdev->subsystem_device == 0x017e) ||
2287 (dev->pdev->subsystem_device == 0x0183) ||
2288 (dev->pdev->subsystem_device == 0x018a) ||
2289 (dev->pdev->subsystem_device == 0x019a)))
2290 force_dac2 = true;
2291 break;
2292 }
2293
2294 if (force_dac2) {
2295 u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
2296 u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
2297 u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
2298
2299 /* For CRT on DAC2, don't turn it on if BIOS didn't
2300 enable it, even it's detected.
2301 */
2302
2303 /* force it to crtc0 */
2304 dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
2305 dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
2306 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
2307
2308 /* set up the TV DAC */
2309 tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL |
2310 RADEON_TV_DAC_STD_MASK |
2311 RADEON_TV_DAC_RDACPD |
2312 RADEON_TV_DAC_GDACPD |
2313 RADEON_TV_DAC_BDACPD |
2314 RADEON_TV_DAC_BGADJ_MASK |
2315 RADEON_TV_DAC_DACADJ_MASK);
2316 tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
2317 RADEON_TV_DAC_NHOLD |
2318 RADEON_TV_DAC_STD_PS2 |
2319 (0x58 << 16));
2320
2321 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
2322 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
2323 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
2324 }
d668046c
DA		 2325
2326 /* switch PM block to ACPI mode */
2327 tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL);
2328 tmp &= ~RADEON_PM_MODE_SEL;
2329 WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);
2330
92cde00c 2331}
771fe6b9
JG		 2332
2333/*
2334 * VRAM info
2335 */
2336static void r100_vram_get_type(struct radeon_device *rdev)
2337{
2338 uint32_t tmp;
2339
2340 rdev->mc.vram_is_ddr = false;
2341 if (rdev->flags & RADEON_IS_IGP)
2342 rdev->mc.vram_is_ddr = true;
2343 else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
2344 rdev->mc.vram_is_ddr = true;
2345 if ((rdev->family == CHIP_RV100) ||
2346 (rdev->family == CHIP_RS100) ||
2347 (rdev->family == CHIP_RS200)) {
2348 tmp = RREG32(RADEON_MEM_CNTL);
2349 if (tmp & RV100_HALF_MODE) {
2350 rdev->mc.vram_width = 32;
2351 } else {
2352 rdev->mc.vram_width = 64;
2353 }
2354 if (rdev->flags & RADEON_SINGLE_CRTC) {
2355 rdev->mc.vram_width /= 4;
2356 rdev->mc.vram_is_ddr = true;
2357 }
2358 } else if (rdev->family <= CHIP_RV280) {
2359 tmp = RREG32(RADEON_MEM_CNTL);
2360 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
2361 rdev->mc.vram_width = 128;
2362 } else {
2363 rdev->mc.vram_width = 64;
2364 }
2365 } else {
2366 /* newer IGPs */
2367 rdev->mc.vram_width = 128;
2368 }
2369}
2370
2a0f8918 2371static u32 r100_get_accessible_vram(struct radeon_device *rdev)
771fe6b9 2372{
2a0f8918
DA		 2373 u32 aper_size;
2374 u8 byte;
2375
2376 aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2377
2378 /* Set HDP_APER_CNTL only on cards that are known not to be broken,
2379 * that is has the 2nd generation multifunction PCI interface
2380 */
2381 if (rdev->family == CHIP_RV280 ||
2382 rdev->family >= CHIP_RV350) {
2383 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
2384 ~RADEON_HDP_APER_CNTL);
2385 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
2386 return aper_size * 2;
2387 }
2388
2389 /* Older cards have all sorts of funny issues to deal with. First
2390 * check if it's a multifunction card by reading the PCI config
2391 * header type... Limit those to one aperture size
2392 */
2393 pci_read_config_byte(rdev->pdev, 0xe, &byte);
2394 if (byte & 0x80) {
2395 DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
2396 DRM_INFO("Limiting VRAM to one aperture\n");
2397 return aper_size;
2398 }
2399
2400 /* Single function older card. We read HDP_APER_CNTL to see how the BIOS
2401 * have set it up. We don't write this as it's broken on some ASICs but
2402 * we expect the BIOS to have done the right thing (might be too optimistic...)
2403 */
2404 if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
2405 return aper_size * 2;
2406 return aper_size;
2407}
2408
2409void r100_vram_init_sizes(struct radeon_device *rdev)
2410{
2411 u64 config_aper_size;
2a0f8918 2412
d594e46a 2413 /* work out accessible VRAM */
01d73a69
JC		 2414 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
2415 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
51e5fcd3
JG		 2416 rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev);
2417 /* FIXME we don't use the second aperture yet when we could use it */
2418 if (rdev->mc.visible_vram_size > rdev->mc.aper_size)
2419 rdev->mc.visible_vram_size = rdev->mc.aper_size;
2a0f8918 2420 config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
771fe6b9
JG		 2421 if (rdev->flags & RADEON_IS_IGP) {
2422 uint32_t tom;
2423 /* read NB_TOM to get the amount of ram stolen for the GPU */
2424 tom = RREG32(RADEON_NB_TOM);
7a50f01a 2425 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
7a50f01a
DA		 2426 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2427 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
771fe6b9 2428 } else {
7a50f01a 2429 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
771fe6b9
JG		 2430 /* Some production boards of m6 will report 0
2431 * if it's 8 MB
2432 */
7a50f01a
DA		 2433 if (rdev->mc.real_vram_size == 0) {
2434 rdev->mc.real_vram_size = 8192 * 1024;
2435 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
771fe6b9 2436 }
d594e46a
JG		 2437 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
2438 * Novell bug 204882 + along with lots of ubuntu ones
2439 */
b7d8cce5
AD		 2440 if (rdev->mc.aper_size > config_aper_size)
2441 config_aper_size = rdev->mc.aper_size;
2442
7a50f01a
DA		 2443 if (config_aper_size > rdev->mc.real_vram_size)
2444 rdev->mc.mc_vram_size = config_aper_size;
2445 else
2446 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
771fe6b9 2447 }
2a0f8918
DA		 2448}
2449
28d52043
DA		 2450void r100_vga_set_state(struct radeon_device *rdev, bool state)
2451{
2452 uint32_t temp;
2453
2454 temp = RREG32(RADEON_CONFIG_CNTL);
2455 if (state == false) {
d75ee3be
AD		 2456 temp &= ~RADEON_CFG_VGA_RAM_EN;
2457 temp |= RADEON_CFG_VGA_IO_DIS;
28d52043 2458 } else {
d75ee3be 2459 temp &= ~RADEON_CFG_VGA_IO_DIS;
28d52043
DA		 2460 }
2461 WREG32(RADEON_CONFIG_CNTL, temp);
2462}
2463
d594e46a 2464void r100_mc_init(struct radeon_device *rdev)
2a0f8918 2465{
d594e46a 2466 u64 base;
2a0f8918 2467
d594e46a 2468 r100_vram_get_type(rdev);
2a0f8918 2469 r100_vram_init_sizes(rdev);
d594e46a
JG		 2470 base = rdev->mc.aper_base;
2471 if (rdev->flags & RADEON_IS_IGP)
2472 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
2473 radeon_vram_location(rdev, &rdev->mc, base);
8d369bb1 2474 rdev->mc.gtt_base_align = 0;
d594e46a
JG		 2475 if (!(rdev->flags & RADEON_IS_AGP))
2476 radeon_gtt_location(rdev, &rdev->mc);
f47299c5 2477 radeon_update_bandwidth_info(rdev);
771fe6b9
JG		 2478}
2479
2480
2481/*
2482 * Indirect registers accessor
2483 */
2484void r100_pll_errata_after_index(struct radeon_device *rdev)
2485{
4ce9198e
AD		 2486 if (rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS) {
2487 (void)RREG32(RADEON_CLOCK_CNTL_DATA);
2488 (void)RREG32(RADEON_CRTC_GEN_CNTL);
771fe6b9 2489 }
771fe6b9
JG		 2490}
2491
2492static void r100_pll_errata_after_data(struct radeon_device *rdev)
2493{
2494 /* This workarounds is necessary on RV100, RS100 and RS200 chips
2495 * or the chip could hang on a subsequent access
2496 */
2497 if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
4de833c3 2498 mdelay(5);
771fe6b9
JG		 2499 }
2500
2501 /* This function is required to workaround a hardware bug in some (all?)
2502 * revisions of the R300. This workaround should be called after every
2503 * CLOCK_CNTL_INDEX register access. If not, register reads afterward
2504 * may not be correct.
2505 */
2506 if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
2507 uint32_t save, tmp;
2508
2509 save = RREG32(RADEON_CLOCK_CNTL_INDEX);
2510 tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
2511 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
2512 tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
2513 WREG32(RADEON_CLOCK_CNTL_INDEX, save);
2514 }
2515}
2516
2517uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
2518{
2519 uint32_t data;
2520
2521 WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
2522 r100_pll_errata_after_index(rdev);
2523 data = RREG32(RADEON_CLOCK_CNTL_DATA);
2524 r100_pll_errata_after_data(rdev);
2525 return data;
2526}
2527
2528void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2529{
2530 WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN));
2531 r100_pll_errata_after_index(rdev);
2532 WREG32(RADEON_CLOCK_CNTL_DATA, v);
2533 r100_pll_errata_after_data(rdev);
2534}
2535
d4550907 2536void r100_set_safe_registers(struct radeon_device *rdev)
068a117c 2537{
551ebd83
DA		 2538 if (ASIC_IS_RN50(rdev)) {
2539 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
2540 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
2541 } else if (rdev->family < CHIP_R200) {
2542 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
2543 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
2544 } else {
d4550907 2545 r200_set_safe_registers(rdev);
551ebd83 2546 }
068a117c
JG		 2547}
2548
771fe6b9
JG		 2549/*
2550 * Debugfs info
2551 */
2552#if defined(CONFIG_DEBUG_FS)
2553static int r100_debugfs_rbbm_info(struct seq_file *m, void *data)
2554{
2555 struct drm_info_node *node = (struct drm_info_node *) m->private;
2556 struct drm_device *dev = node->minor->dev;
2557 struct radeon_device *rdev = dev->dev_private;
2558 uint32_t reg, value;
2559 unsigned i;
2560
2561 seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
2562 seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
2563 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2564 for (i = 0; i < 64; i++) {
2565 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100);
2566 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
2567 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
2568 value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
2569 seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
2570 }
2571 return 0;
2572}
2573
2574static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data)
2575{
2576 struct drm_info_node *node = (struct drm_info_node *) m->private;
2577 struct drm_device *dev = node->minor->dev;
2578 struct radeon_device *rdev = dev->dev_private;
e32eb50d 2579 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
771fe6b9
JG		 2580 uint32_t rdp, wdp;
2581 unsigned count, i, j;
2582
e32eb50d 2583 radeon_ring_free_size(rdev, ring);
771fe6b9
JG		 2584 rdp = RREG32(RADEON_CP_RB_RPTR);
2585 wdp = RREG32(RADEON_CP_RB_WPTR);
e32eb50d 2586 count = (rdp + ring->ring_size - wdp) & ring->ptr_mask;
771fe6b9
JG		 2587 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2588 seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
2589 seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
e32eb50d 2590 seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw);
771fe6b9
JG		 2591 seq_printf(m, "%u dwords in ring\n", count);
2592 for (j = 0; j <= count; j++) {
e32eb50d
CK		 2593 i = (rdp + j) & ring->ptr_mask;
2594 seq_printf(m, "r[%04d]=0x%08x\n", i, ring->ring[i]);
771fe6b9
JG		 2595 }
2596 return 0;
2597}
2598
2599
2600static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data)
2601{
2602 struct drm_info_node *node = (struct drm_info_node *) m->private;
2603 struct drm_device *dev = node->minor->dev;
2604 struct radeon_device *rdev = dev->dev_private;
2605 uint32_t csq_stat, csq2_stat, tmp;
2606 unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
2607 unsigned i;
2608
2609 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2610 seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
2611 csq_stat = RREG32(RADEON_CP_CSQ_STAT);
2612 csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
2613 r_rptr = (csq_stat >> 0) & 0x3ff;
2614 r_wptr = (csq_stat >> 10) & 0x3ff;
2615 ib1_rptr = (csq_stat >> 20) & 0x3ff;
2616 ib1_wptr = (csq2_stat >> 0) & 0x3ff;
2617 ib2_rptr = (csq2_stat >> 10) & 0x3ff;
2618 ib2_wptr = (csq2_stat >> 20) & 0x3ff;
2619 seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
2620 seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
2621 seq_printf(m, "Ring rptr %u\n", r_rptr);
2622 seq_printf(m, "Ring wptr %u\n", r_wptr);
2623 seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
2624 seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
2625 seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
2626 seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
2627 /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
2628 * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
2629 seq_printf(m, "Ring fifo:\n");
2630 for (i = 0; i < 256; i++) {
2631 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2632 tmp = RREG32(RADEON_CP_CSQ_DATA);
2633 seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
2634 }
2635 seq_printf(m, "Indirect1 fifo:\n");
2636 for (i = 256; i <= 512; i++) {
2637 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2638 tmp = RREG32(RADEON_CP_CSQ_DATA);
2639 seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
2640 }
2641 seq_printf(m, "Indirect2 fifo:\n");
2642 for (i = 640; i < ib1_wptr; i++) {
2643 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2644 tmp = RREG32(RADEON_CP_CSQ_DATA);
2645 seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
2646 }
2647 return 0;
2648}
2649
2650static int r100_debugfs_mc_info(struct seq_file *m, void *data)
2651{
2652 struct drm_info_node *node = (struct drm_info_node *) m->private;
2653 struct drm_device *dev = node->minor->dev;
2654 struct radeon_device *rdev = dev->dev_private;
2655 uint32_t tmp;
2656
2657 tmp = RREG32(RADEON_CONFIG_MEMSIZE);
2658 seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
2659 tmp = RREG32(RADEON_MC_FB_LOCATION);
2660 seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
2661 tmp = RREG32(RADEON_BUS_CNTL);
2662 seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
2663 tmp = RREG32(RADEON_MC_AGP_LOCATION);
2664 seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
2665 tmp = RREG32(RADEON_AGP_BASE);
2666 seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
2667 tmp = RREG32(RADEON_HOST_PATH_CNTL);
2668 seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
2669 tmp = RREG32(0x01D0);
2670 seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
2671 tmp = RREG32(RADEON_AIC_LO_ADDR);
2672 seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
2673 tmp = RREG32(RADEON_AIC_HI_ADDR);
2674 seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
2675 tmp = RREG32(0x01E4);
2676 seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
2677 return 0;
2678}
2679
2680static struct drm_info_list r100_debugfs_rbbm_list[] = {
2681 {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL},
2682};
2683
2684static struct drm_info_list r100_debugfs_cp_list[] = {
2685 {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL},
2686 {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL},
2687};
2688
2689static struct drm_info_list r100_debugfs_mc_info_list[] = {
2690 {"r100_mc_info", r100_debugfs_mc_info, 0, NULL},
2691};
2692#endif
2693
2694int r100_debugfs_rbbm_init(struct radeon_device *rdev)
2695{
2696#if defined(CONFIG_DEBUG_FS)
2697 return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1);
2698#else
2699 return 0;
2700#endif
2701}
2702
2703int r100_debugfs_cp_init(struct radeon_device *rdev)
2704{
2705#if defined(CONFIG_DEBUG_FS)
2706 return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2);
2707#else
2708 return 0;
2709#endif
2710}
2711
2712int r100_debugfs_mc_info_init(struct radeon_device *rdev)
2713{
2714#if defined(CONFIG_DEBUG_FS)
2715 return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1);
2716#else
2717 return 0;
2718#endif
2719}
e024e110
DA		 2720
2721int r100_set_surface_reg(struct radeon_device *rdev, int reg,
2722 uint32_t tiling_flags, uint32_t pitch,
2723 uint32_t offset, uint32_t obj_size)
2724{
2725 int surf_index = reg * 16;
2726 int flags = 0;
2727
e024e110
DA		 2728 if (rdev->family <= CHIP_RS200) {
2729 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2730 == (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2731 flags |= RADEON_SURF_TILE_COLOR_BOTH;
2732 if (tiling_flags & RADEON_TILING_MACRO)
2733 flags |= RADEON_SURF_TILE_COLOR_MACRO;
2734 } else if (rdev->family <= CHIP_RV280) {
2735 if (tiling_flags & (RADEON_TILING_MACRO))
2736 flags |= R200_SURF_TILE_COLOR_MACRO;
2737 if (tiling_flags & RADEON_TILING_MICRO)
2738 flags |= R200_SURF_TILE_COLOR_MICRO;
2739 } else {
2740 if (tiling_flags & RADEON_TILING_MACRO)
2741 flags |= R300_SURF_TILE_MACRO;
2742 if (tiling_flags & RADEON_TILING_MICRO)
2743 flags |= R300_SURF_TILE_MICRO;
2744 }
2745
c88f9f0c
MD		 2746 if (tiling_flags & RADEON_TILING_SWAP_16BIT)
2747 flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP;
2748 if (tiling_flags & RADEON_TILING_SWAP_32BIT)
2749 flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP;
2750
f5c5f040
DA		 2751 /* when we aren't tiling the pitch seems to needs to be furtherdivided down. - tested on power5 + rn50 server */
2752 if (tiling_flags & (RADEON_TILING_SWAP_16BIT | RADEON_TILING_SWAP_32BIT)) {
2753 if (!(tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO)))
2754 if (ASIC_IS_RN50(rdev))
2755 pitch /= 16;
2756 }
2757
2758 /* r100/r200 divide by 16 */
2759 if (rdev->family < CHIP_R300)
2760 flags |= pitch / 16;
2761 else
2762 flags |= pitch / 8;
2763
2764
d9fdaafb 2765 DRM_DEBUG_KMS("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
e024e110
DA		 2766 WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
2767 WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
2768 WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);
2769 return 0;
2770}
2771
2772void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
2773{
2774 int surf_index = reg * 16;
2775 WREG32(RADEON_SURFACE0_INFO + surf_index, 0);
2776}
c93bb85b
JG		 2777
2778void r100_bandwidth_update(struct radeon_device *rdev)
2779{
2780 fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff;
2781 fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff;
2782 fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff;
2783 uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
2784 fixed20_12 memtcas_ff[8] = {
68adac5e
BS		 2785 dfixed_init(1),
2786 dfixed_init(2),
2787 dfixed_init(3),
2788 dfixed_init(0),
2789 dfixed_init_half(1),
2790 dfixed_init_half(2),
2791 dfixed_init(0),
c93bb85b
JG		 2792 };
2793 fixed20_12 memtcas_rs480_ff[8] = {
68adac5e
BS		 2794 dfixed_init(0),
2795 dfixed_init(1),
2796 dfixed_init(2),
2797 dfixed_init(3),
2798 dfixed_init(0),
2799 dfixed_init_half(1),
2800 dfixed_init_half(2),
2801 dfixed_init_half(3),
c93bb85b
JG		 2802 };
2803 fixed20_12 memtcas2_ff[8] = {
68adac5e
BS		 2804 dfixed_init(0),
2805 dfixed_init(1),
2806 dfixed_init(2),
2807 dfixed_init(3),
2808 dfixed_init(4),
2809 dfixed_init(5),
2810 dfixed_init(6),
2811 dfixed_init(7),
c93bb85b
JG		 2812 };
2813 fixed20_12 memtrbs[8] = {
68adac5e
BS		 2814 dfixed_init(1),
2815 dfixed_init_half(1),
2816 dfixed_init(2),
2817 dfixed_init_half(2),
2818 dfixed_init(3),
2819 dfixed_init_half(3),
2820 dfixed_init(4),
2821 dfixed_init_half(4)
c93bb85b
JG		 2822 };
2823 fixed20_12 memtrbs_r4xx[8] = {
68adac5e
BS		 2824 dfixed_init(4),
2825 dfixed_init(5),
2826 dfixed_init(6),
2827 dfixed_init(7),
2828 dfixed_init(8),
2829 dfixed_init(9),
2830 dfixed_init(10),
2831 dfixed_init(11)
c93bb85b
JG		 2832 };
2833 fixed20_12 min_mem_eff;
2834 fixed20_12 mc_latency_sclk, mc_latency_mclk, k1;
2835 fixed20_12 cur_latency_mclk, cur_latency_sclk;
2836 fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate,
2837 disp_drain_rate2, read_return_rate;
2838 fixed20_12 time_disp1_drop_priority;
2839 int c;
2840 int cur_size = 16; /* in octawords */
2841 int critical_point = 0, critical_point2;
2842/* uint32_t read_return_rate, time_disp1_drop_priority; */
2843 int stop_req, max_stop_req;
2844 struct drm_display_mode *mode1 = NULL;
2845 struct drm_display_mode *mode2 = NULL;
2846 uint32_t pixel_bytes1 = 0;
2847 uint32_t pixel_bytes2 = 0;
2848
f46c0120
AD		 2849 radeon_update_display_priority(rdev);
2850
c93bb85b
JG		 2851 if (rdev->mode_info.crtcs[0]->base.enabled) {
2852 mode1 = &rdev->mode_info.crtcs[0]->base.mode;
2853 pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8;
2854 }
dfee5614
DA		 2855 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
2856 if (rdev->mode_info.crtcs[1]->base.enabled) {
2857 mode2 = &rdev->mode_info.crtcs[1]->base.mode;
2858 pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8;
2859 }
c93bb85b
JG		 2860 }
2861
68adac5e 2862 min_mem_eff.full = dfixed_const_8(0);
c93bb85b
JG		 2863 /* get modes */
2864 if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
2865 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);
2866 mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT);
2867 mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT);
2868 /* check crtc enables */
2869 if (mode2)
2870 mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
2871 if (mode1)
2872 mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
2873 WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
2874 }
2875
2876 /*
2877 * determine is there is enough bw for current mode
2878 */
f47299c5
AD		 2879 sclk_ff = rdev->pm.sclk;
2880 mclk_ff = rdev->pm.mclk;
c93bb85b
JG		 2881
2882 temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
68adac5e
BS		 2883 temp_ff.full = dfixed_const(temp);
2884 mem_bw.full = dfixed_mul(mclk_ff, temp_ff);
c93bb85b
JG		 2885
2886 pix_clk.full = 0;
2887 pix_clk2.full = 0;
2888 peak_disp_bw.full = 0;
2889 if (mode1) {
68adac5e
BS		 2890 temp_ff.full = dfixed_const(1000);
2891 pix_clk.full = dfixed_const(mode1->clock); /* convert to fixed point */
2892 pix_clk.full = dfixed_div(pix_clk, temp_ff);
2893 temp_ff.full = dfixed_const(pixel_bytes1);
2894 peak_disp_bw.full += dfixed_mul(pix_clk, temp_ff);
c93bb85b
JG		 2895 }
2896 if (mode2) {
68adac5e
BS		 2897 temp_ff.full = dfixed_const(1000);
2898 pix_clk2.full = dfixed_const(mode2->clock); /* convert to fixed point */
2899 pix_clk2.full = dfixed_div(pix_clk2, temp_ff);
2900 temp_ff.full = dfixed_const(pixel_bytes2);
2901 peak_disp_bw.full += dfixed_mul(pix_clk2, temp_ff);
c93bb85b
JG		 2902 }
2903
68adac5e 2904 mem_bw.full = dfixed_mul(mem_bw, min_mem_eff);
c93bb85b
JG		 2905 if (peak_disp_bw.full >= mem_bw.full) {
2906 DRM_ERROR("You may not have enough display bandwidth for current mode\n"
2907 "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
2908 }
2909
2910 /* Get values from the EXT_MEM_CNTL register...converting its contents. */
2911 temp = RREG32(RADEON_MEM_TIMING_CNTL);
2912 if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
2913 mem_trcd = ((temp >> 2) & 0x3) + 1;
2914 mem_trp = ((temp & 0x3)) + 1;
2915 mem_tras = ((temp & 0x70) >> 4) + 1;
2916 } else if (rdev->family == CHIP_R300 ||
2917 rdev->family == CHIP_R350) { /* r300, r350 */
2918 mem_trcd = (temp & 0x7) + 1;
2919 mem_trp = ((temp >> 8) & 0x7) + 1;
2920 mem_tras = ((temp >> 11) & 0xf) + 4;
2921 } else if (rdev->family == CHIP_RV350 ||
2922 rdev->family <= CHIP_RV380) {
2923 /* rv3x0 */
2924 mem_trcd = (temp & 0x7) + 3;
2925 mem_trp = ((temp >> 8) & 0x7) + 3;
2926 mem_tras = ((temp >> 11) & 0xf) + 6;
2927 } else if (rdev->family == CHIP_R420 ||
2928 rdev->family == CHIP_R423 ||
2929 rdev->family == CHIP_RV410) {
2930 /* r4xx */
2931 mem_trcd = (temp & 0xf) + 3;
2932 if (mem_trcd > 15)
2933 mem_trcd = 15;
2934 mem_trp = ((temp >> 8) & 0xf) + 3;
2935 if (mem_trp > 15)
2936 mem_trp = 15;
2937 mem_tras = ((temp >> 12) & 0x1f) + 6;
2938 if (mem_tras > 31)
2939 mem_tras = 31;
2940 } else { /* RV200, R200 */
2941 mem_trcd = (temp & 0x7) + 1;
2942 mem_trp = ((temp >> 8) & 0x7) + 1;
2943 mem_tras = ((temp >> 12) & 0xf) + 4;
2944 }
2945 /* convert to FF */
68adac5e
BS		 2946 trcd_ff.full = dfixed_const(mem_trcd);
2947 trp_ff.full = dfixed_const(mem_trp);
2948 tras_ff.full = dfixed_const(mem_tras);
c93bb85b
JG		 2949
2950 /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
2951 temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2952 data = (temp & (7 << 20)) >> 20;
2953 if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) {
2954 if (rdev->family == CHIP_RS480) /* don't think rs400 */
2955 tcas_ff = memtcas_rs480_ff[data];
2956 else
2957 tcas_ff = memtcas_ff[data];
2958 } else
2959 tcas_ff = memtcas2_ff[data];
2960
2961 if (rdev->family == CHIP_RS400 ||
2962 rdev->family == CHIP_RS480) {
2963 /* extra cas latency stored in bits 23-25 0-4 clocks */
2964 data = (temp >> 23) & 0x7;
2965 if (data < 5)
68adac5e 2966 tcas_ff.full += dfixed_const(data);
c93bb85b
JG		 2967 }
2968
2969 if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
2970 /* on the R300, Tcas is included in Trbs.
2971 */
2972 temp = RREG32(RADEON_MEM_CNTL);
2973 data = (R300_MEM_NUM_CHANNELS_MASK & temp);
2974 if (data == 1) {
2975 if (R300_MEM_USE_CD_CH_ONLY & temp) {
2976 temp = RREG32(R300_MC_IND_INDEX);
2977 temp &= ~R300_MC_IND_ADDR_MASK;
2978 temp |= R300_MC_READ_CNTL_CD_mcind;
2979 WREG32(R300_MC_IND_INDEX, temp);
2980 temp = RREG32(R300_MC_IND_DATA);
2981 data = (R300_MEM_RBS_POSITION_C_MASK & temp);
2982 } else {
2983 temp = RREG32(R300_MC_READ_CNTL_AB);
2984 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2985 }
2986 } else {
2987 temp = RREG32(R300_MC_READ_CNTL_AB);
2988 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2989 }
2990 if (rdev->family == CHIP_RV410 ||
2991 rdev->family == CHIP_R420 ||
2992 rdev->family == CHIP_R423)
2993 trbs_ff = memtrbs_r4xx[data];
2994 else
2995 trbs_ff = memtrbs[data];
2996 tcas_ff.full += trbs_ff.full;
2997 }
2998
2999 sclk_eff_ff.full = sclk_ff.full;
3000
3001 if (rdev->flags & RADEON_IS_AGP) {
3002 fixed20_12 agpmode_ff;
68adac5e
BS		 3003 agpmode_ff.full = dfixed_const(radeon_agpmode);
3004 temp_ff.full = dfixed_const_666(16);
3005 sclk_eff_ff.full -= dfixed_mul(agpmode_ff, temp_ff);
c93bb85b
JG		 3006 }
3007 /* TODO PCIE lanes may affect this - agpmode == 16?? */
3008
3009 if (ASIC_IS_R300(rdev)) {
68adac5e 3010 sclk_delay_ff.full = dfixed_const(250);
c93bb85b
JG		 3011 } else {
3012 if ((rdev->family == CHIP_RV100) ||
3013 rdev->flags & RADEON_IS_IGP) {
3014 if (rdev->mc.vram_is_ddr)
68adac5e 3015 sclk_delay_ff.full = dfixed_const(41);
c93bb85b 3016 else
68adac5e 3017 sclk_delay_ff.full = dfixed_const(33);
c93bb85b
JG		 3018 } else {
3019 if (rdev->mc.vram_width == 128)
68adac5e 3020 sclk_delay_ff.full = dfixed_const(57);
c93bb85b 3021 else
68adac5e 3022 sclk_delay_ff.full = dfixed_const(41);
c93bb85b
JG		 3023 }
3024 }
3025
68adac5e 3026 mc_latency_sclk.full = dfixed_div(sclk_delay_ff, sclk_eff_ff);
c93bb85b
JG		 3027
3028 if (rdev->mc.vram_is_ddr) {
3029 if (rdev->mc.vram_width == 32) {
68adac5e 3030 k1.full = dfixed_const(40);
c93bb85b
JG		 3031 c = 3;
3032 } else {
68adac5e 3033 k1.full = dfixed_const(20);
c93bb85b
JG		 3034 c = 1;
3035 }
3036 } else {
68adac5e 3037 k1.full = dfixed_const(40);
c93bb85b
JG		 3038 c = 3;
3039 }
3040
68adac5e
BS		 3041 temp_ff.full = dfixed_const(2);
3042 mc_latency_mclk.full = dfixed_mul(trcd_ff, temp_ff);
3043 temp_ff.full = dfixed_const(c);
3044 mc_latency_mclk.full += dfixed_mul(tcas_ff, temp_ff);
3045 temp_ff.full = dfixed_const(4);
3046 mc_latency_mclk.full += dfixed_mul(tras_ff, temp_ff);
3047 mc_latency_mclk.full += dfixed_mul(trp_ff, temp_ff);
c93bb85b
JG		 3048 mc_latency_mclk.full += k1.full;
3049
68adac5e
BS		 3050 mc_latency_mclk.full = dfixed_div(mc_latency_mclk, mclk_ff);
3051 mc_latency_mclk.full += dfixed_div(temp_ff, sclk_eff_ff);
c93bb85b
JG		 3052
3053 /*
3054 HW cursor time assuming worst case of full size colour cursor.
3055 */
68adac5e 3056 temp_ff.full = dfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
c93bb85b
JG		 3057 temp_ff.full += trcd_ff.full;
3058 if (temp_ff.full < tras_ff.full)
3059 temp_ff.full = tras_ff.full;
68adac5e 3060 cur_latency_mclk.full = dfixed_div(temp_ff, mclk_ff);
c93bb85b 3061
68adac5e
BS		 3062 temp_ff.full = dfixed_const(cur_size);
3063 cur_latency_sclk.full = dfixed_div(temp_ff, sclk_eff_ff);
c93bb85b
JG		 3064 /*
3065 Find the total latency for the display data.
3066 */
68adac5e
BS		 3067 disp_latency_overhead.full = dfixed_const(8);
3068 disp_latency_overhead.full = dfixed_div(disp_latency_overhead, sclk_ff);
c93bb85b
JG		 3069 mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
3070 mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
3071
3072 if (mc_latency_mclk.full > mc_latency_sclk.full)
3073 disp_latency.full = mc_latency_mclk.full;
3074 else
3075 disp_latency.full = mc_latency_sclk.full;
3076
3077 /* setup Max GRPH_STOP_REQ default value */
3078 if (ASIC_IS_RV100(rdev))
3079 max_stop_req = 0x5c;
3080 else
3081 max_stop_req = 0x7c;
3082
3083 if (mode1) {
3084 /* CRTC1
3085 Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
3086 GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
3087 */
3088 stop_req = mode1->hdisplay * pixel_bytes1 / 16;
3089
3090 if (stop_req > max_stop_req)
3091 stop_req = max_stop_req;
3092
3093 /*
3094 Find the drain rate of the display buffer.
3095 */
68adac5e
BS		 3096 temp_ff.full = dfixed_const((16/pixel_bytes1));
3097 disp_drain_rate.full = dfixed_div(pix_clk, temp_ff);
c93bb85b
JG		 3098
3099 /*
3100 Find the critical point of the display buffer.
3101 */
68adac5e
BS		 3102 crit_point_ff.full = dfixed_mul(disp_drain_rate, disp_latency);
3103 crit_point_ff.full += dfixed_const_half(0);
c93bb85b 3104
68adac5e 3105 critical_point = dfixed_trunc(crit_point_ff);
c93bb85b
JG		 3106
3107 if (rdev->disp_priority == 2) {
3108 critical_point = 0;
3109 }
3110
3111 /*
3112 The critical point should never be above max_stop_req-4. Setting
3113 GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
3114 */
3115 if (max_stop_req - critical_point < 4)
3116 critical_point = 0;
3117
3118 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
3119 /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
3120 critical_point = 0x10;
3121 }
3122
3123 temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
3124 temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
3125 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3126 temp &= ~(RADEON_GRPH_START_REQ_MASK);
3127 if ((rdev->family == CHIP_R350) &&
3128 (stop_req > 0x15)) {
3129 stop_req -= 0x10;
3130 }
3131 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3132 temp |= RADEON_GRPH_BUFFER_SIZE;
3133 temp &= ~(RADEON_GRPH_CRITICAL_CNTL |
3134 RADEON_GRPH_CRITICAL_AT_SOF |
3135 RADEON_GRPH_STOP_CNTL);
3136 /*
3137 Write the result into the register.
3138 */
3139 WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3140 (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
3141
3142#if 0
3143 if ((rdev->family == CHIP_RS400) ||
3144 (rdev->family == CHIP_RS480)) {
3145 /* attempt to program RS400 disp regs correctly ??? */
3146 temp = RREG32(RS400_DISP1_REG_CNTL);
3147 temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK |
3148 RS400_DISP1_STOP_REQ_LEVEL_MASK);
3149 WREG32(RS400_DISP1_REQ_CNTL1, (temp |
3150 (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3151 (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3152 temp = RREG32(RS400_DMIF_MEM_CNTL1);
3153 temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK |
3154 RS400_DISP1_CRITICAL_POINT_STOP_MASK);
3155 WREG32(RS400_DMIF_MEM_CNTL1, (temp |
3156 (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) |
3157 (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
3158 }
3159#endif
3160
d9fdaafb 3161 DRM_DEBUG_KMS("GRPH_BUFFER_CNTL from to %x\n",
c93bb85b
JG		 3162 /* (unsigned int)info->SavedReg->grph_buffer_cntl, */
3163 (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
3164 }
3165
3166 if (mode2) {
3167 u32 grph2_cntl;
3168 stop_req = mode2->hdisplay * pixel_bytes2 / 16;
3169
3170 if (stop_req > max_stop_req)
3171 stop_req = max_stop_req;
3172
3173 /*
3174 Find the drain rate of the display buffer.
3175 */
68adac5e
BS		 3176 temp_ff.full = dfixed_const((16/pixel_bytes2));
3177 disp_drain_rate2.full = dfixed_div(pix_clk2, temp_ff);
c93bb85b
JG		 3178
3179 grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL);
3180 grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK);
3181 grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3182 grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK);
3183 if ((rdev->family == CHIP_R350) &&
3184 (stop_req > 0x15)) {
3185 stop_req -= 0x10;
3186 }
3187 grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3188 grph2_cntl |= RADEON_GRPH_BUFFER_SIZE;
3189 grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL |
3190 RADEON_GRPH_CRITICAL_AT_SOF |
3191 RADEON_GRPH_STOP_CNTL);
3192
3193 if ((rdev->family == CHIP_RS100) ||
3194 (rdev->family == CHIP_RS200))
3195 critical_point2 = 0;
3196 else {
3197 temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
68adac5e
BS		 3198 temp_ff.full = dfixed_const(temp);
3199 temp_ff.full = dfixed_mul(mclk_ff, temp_ff);
c93bb85b
JG		 3200 if (sclk_ff.full < temp_ff.full)
3201 temp_ff.full = sclk_ff.full;
3202
3203 read_return_rate.full = temp_ff.full;
3204
3205 if (mode1) {
3206 temp_ff.full = read_return_rate.full - disp_drain_rate.full;
68adac5e 3207 time_disp1_drop_priority.full = dfixed_div(crit_point_ff, temp_ff);
c93bb85b
JG		 3208 } else {
3209 time_disp1_drop_priority.full = 0;
3210 }
3211 crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full;
68adac5e
BS		 3212 crit_point_ff.full = dfixed_mul(crit_point_ff, disp_drain_rate2);
3213 crit_point_ff.full += dfixed_const_half(0);
c93bb85b 3214
68adac5e 3215 critical_point2 = dfixed_trunc(crit_point_ff);
c93bb85b
JG		 3216
3217 if (rdev->disp_priority == 2) {
3218 critical_point2 = 0;
3219 }
3220
3221 if (max_stop_req - critical_point2 < 4)
3222 critical_point2 = 0;
3223
3224 }
3225
3226 if (critical_point2 == 0 && rdev->family == CHIP_R300) {
3227 /* some R300 cards have problem with this set to 0 */
3228 critical_point2 = 0x10;
3229 }
3230
3231 WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3232 (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
3233
3234 if ((rdev->family == CHIP_RS400) ||
3235 (rdev->family == CHIP_RS480)) {
3236#if 0
3237 /* attempt to program RS400 disp2 regs correctly ??? */
3238 temp = RREG32(RS400_DISP2_REQ_CNTL1);
3239 temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK |
3240 RS400_DISP2_STOP_REQ_LEVEL_MASK);
3241 WREG32(RS400_DISP2_REQ_CNTL1, (temp |
3242 (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3243 (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3244 temp = RREG32(RS400_DISP2_REQ_CNTL2);
3245 temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK |
3246 RS400_DISP2_CRITICAL_POINT_STOP_MASK);
3247 WREG32(RS400_DISP2_REQ_CNTL2, (temp |
3248 (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) |
3249 (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT)));
3250#endif
3251 WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);
3252 WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000);
3253 WREG32(RS400_DMIF_MEM_CNTL1, 0x29CA71DC);
3254 WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
3255 }
3256
d9fdaafb 3257 DRM_DEBUG_KMS("GRPH2_BUFFER_CNTL from to %x\n",
c93bb85b
JG		 3258 (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
3259 }
3260}
551ebd83 3261
cbdd4501 3262static void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
551ebd83
DA		 3263{
3264 DRM_ERROR("pitch %d\n", t->pitch);
ceb776bc 3265 DRM_ERROR("use_pitch %d\n", t->use_pitch);
551ebd83 3266 DRM_ERROR("width %d\n", t->width);
ceb776bc 3267 DRM_ERROR("width_11 %d\n", t->width_11);
551ebd83 3268 DRM_ERROR("height %d\n", t->height);
ceb776bc 3269 DRM_ERROR("height_11 %d\n", t->height_11);
551ebd83
DA		 3270 DRM_ERROR("num levels %d\n", t->num_levels);
3271 DRM_ERROR("depth %d\n", t->txdepth);
3272 DRM_ERROR("bpp %d\n", t->cpp);
3273 DRM_ERROR("coordinate type %d\n", t->tex_coord_type);
3274 DRM_ERROR("width round to power of 2 %d\n", t->roundup_w);
3275 DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
d785d78b 3276 DRM_ERROR("compress format %d\n", t->compress_format);
551ebd83
DA		 3277}
3278
d785d78b
DA		 3279static int r100_track_compress_size(int compress_format, int w, int h)
3280{
3281 int block_width, block_height, block_bytes;
3282 int wblocks, hblocks;
3283 int min_wblocks;
3284 int sz;
3285
3286 block_width = 4;
3287 block_height = 4;
3288
3289 switch (compress_format) {
3290 case R100_TRACK_COMP_DXT1:
3291 block_bytes = 8;
3292 min_wblocks = 4;
3293 break;
3294 default:
3295 case R100_TRACK_COMP_DXT35:
3296 block_bytes = 16;
3297 min_wblocks = 2;
3298 break;
3299 }
3300
3301 hblocks = (h + block_height - 1) / block_height;
3302 wblocks = (w + block_width - 1) / block_width;
3303 if (wblocks < min_wblocks)
3304 wblocks = min_wblocks;
3305 sz = wblocks * hblocks * block_bytes;
3306 return sz;
3307}
3308
37cf6b03
RS		 3309static int r100_cs_track_cube(struct radeon_device *rdev,
3310 struct r100_cs_track *track, unsigned idx)
3311{
3312 unsigned face, w, h;
3313 struct radeon_bo *cube_robj;
3314 unsigned long size;
3315 unsigned compress_format = track->textures[idx].compress_format;
3316
3317 for (face = 0; face < 5; face++) {
3318 cube_robj = track->textures[idx].cube_info[face].robj;
3319 w = track->textures[idx].cube_info[face].width;
3320 h = track->textures[idx].cube_info[face].height;
3321
3322 if (compress_format) {
3323 size = r100_track_compress_size(compress_format, w, h);
3324 } else
3325 size = w * h;
3326 size *= track->textures[idx].cpp;
3327
3328 size += track->textures[idx].cube_info[face].offset;
3329
3330 if (size > radeon_bo_size(cube_robj)) {
3331 DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
3332 size, radeon_bo_size(cube_robj));
3333 r100_cs_track_texture_print(&track->textures[idx]);
3334 return -1;
3335 }
3336 }
3337 return 0;
3338}
3339
551ebd83
DA		 3340static int r100_cs_track_texture_check(struct radeon_device *rdev,
3341 struct r100_cs_track *track)
3342{
4c788679 3343 struct radeon_bo *robj;
551ebd83 3344 unsigned long size;
b73c5f8b 3345 unsigned u, i, w, h, d;
551ebd83
DA		 3346 int ret;
3347
3348 for (u = 0; u < track->num_texture; u++) {
3349 if (!track->textures[u].enabled)
3350 continue;
43b93fbf
AD		 3351 if (track->textures[u].lookup_disable)
3352 continue;
551ebd83
DA		 3353 robj = track->textures[u].robj;
3354 if (robj == NULL) {
3355 DRM_ERROR("No texture bound to unit %u\n", u);
3356 return -EINVAL;
3357 }
3358 size = 0;
3359 for (i = 0; i <= track->textures[u].num_levels; i++) {
3360 if (track->textures[u].use_pitch) {
3361 if (rdev->family < CHIP_R300)
3362 w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i);
3363 else
3364 w = track->textures[u].pitch / (1 << i);
3365 } else {
ceb776bc 3366 w = track->textures[u].width;
551ebd83
DA		 3367 if (rdev->family >= CHIP_RV515)
3368 w |= track->textures[u].width_11;
ceb776bc 3369 w = w / (1 << i);
551ebd83
DA		 3370 if (track->textures[u].roundup_w)
3371 w = roundup_pow_of_two(w);
3372 }
ceb776bc 3373 h = track->textures[u].height;
551ebd83
DA		 3374 if (rdev->family >= CHIP_RV515)
3375 h |= track->textures[u].height_11;
ceb776bc 3376 h = h / (1 << i);
551ebd83
DA		 3377 if (track->textures[u].roundup_h)
3378 h = roundup_pow_of_two(h);
b73c5f8b
MO		 3379 if (track->textures[u].tex_coord_type == 1) {
3380 d = (1 << track->textures[u].txdepth) / (1 << i);
3381 if (!d)
3382 d = 1;
3383 } else {
3384 d = 1;
3385 }
d785d78b
DA		 3386 if (track->textures[u].compress_format) {
3387
b73c5f8b 3388 size += r100_track_compress_size(track->textures[u].compress_format, w, h) * d;
d785d78b
DA		 3389 /* compressed textures are block based */
3390 } else
b73c5f8b 3391 size += w * h * d;
551ebd83
DA		 3392 }
3393 size *= track->textures[u].cpp;
d785d78b 3394
551ebd83
DA		 3395 switch (track->textures[u].tex_coord_type) {
3396 case 0:
551ebd83 3397 case 1:
551ebd83
DA		 3398 break;
3399 case 2:
3400 if (track->separate_cube) {
3401 ret = r100_cs_track_cube(rdev, track, u);
3402 if (ret)
3403 return ret;
3404 } else
3405 size *= 6;
3406 break;
3407 default:
3408 DRM_ERROR("Invalid texture coordinate type %u for unit "
3409 "%u\n", track->textures[u].tex_coord_type, u);
3410 return -EINVAL;
3411 }
4c788679 3412 if (size > radeon_bo_size(robj)) {
551ebd83 3413 DRM_ERROR("Texture of unit %u needs %lu bytes but is "
4c788679 3414 "%lu\n", u, size, radeon_bo_size(robj));
551ebd83
DA		 3415 r100_cs_track_texture_print(&track->textures[u]);
3416 return -EINVAL;
3417 }
3418 }
3419 return 0;
3420}
3421
3422int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
3423{
3424 unsigned i;
3425 unsigned long size;
3426 unsigned prim_walk;
3427 unsigned nverts;
40b4a759 3428 unsigned num_cb = track->cb_dirty ? track->num_cb : 0;
551ebd83 3429
40b4a759 3430 if (num_cb && !track->zb_cb_clear && !track->color_channel_mask &&
a41ceb1c
MO		 3431 !track->blend_read_enable)
3432 num_cb = 0;
3433
3434 for (i = 0; i < num_cb; i++) {
551ebd83
DA		 3435 if (track->cb[i].robj == NULL) {
3436 DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
3437 return -EINVAL;
3438 }
3439 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
3440 size += track->cb[i].offset;
4c788679 3441 if (size > radeon_bo_size(track->cb[i].robj)) {
551ebd83
DA		 3442 DRM_ERROR("[drm] Buffer too small for color buffer %d "
3443 "(need %lu have %lu) !\n", i, size,
4c788679 3444 radeon_bo_size(track->cb[i].robj));
551ebd83
DA		 3445 DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
3446 i, track->cb[i].pitch, track->cb[i].cpp,
3447 track->cb[i].offset, track->maxy);
3448 return -EINVAL;
3449 }
3450 }
40b4a759
MO		 3451 track->cb_dirty = false;
3452
3453 if (track->zb_dirty && track->z_enabled) {
551ebd83
DA		 3454 if (track->zb.robj == NULL) {
3455 DRM_ERROR("[drm] No buffer for z buffer !\n");
3456 return -EINVAL;
3457 }
3458 size = track->zb.pitch * track->zb.cpp * track->maxy;
3459 size += track->zb.offset;
4c788679 3460 if (size > radeon_bo_size(track->zb.robj)) {
551ebd83
DA		 3461 DRM_ERROR("[drm] Buffer too small for z buffer "
3462 "(need %lu have %lu) !\n", size,
4c788679 3463 radeon_bo_size(track->zb.robj));
551ebd83
DA		 3464 DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
3465 track->zb.pitch, track->zb.cpp,
3466 track->zb.offset, track->maxy);
3467 return -EINVAL;
3468 }
3469 }
40b4a759
MO		 3470 track->zb_dirty = false;
3471
fff1ce4d
MO		 3472 if (track->aa_dirty && track->aaresolve) {
3473 if (track->aa.robj == NULL) {
3474 DRM_ERROR("[drm] No buffer for AA resolve buffer %d !\n", i);
3475 return -EINVAL;
3476 }
3477 /* I believe the format comes from colorbuffer0. */
3478 size = track->aa.pitch * track->cb[0].cpp * track->maxy;
3479 size += track->aa.offset;
3480 if (size > radeon_bo_size(track->aa.robj)) {
3481 DRM_ERROR("[drm] Buffer too small for AA resolve buffer %d "
3482 "(need %lu have %lu) !\n", i, size,
3483 radeon_bo_size(track->aa.robj));
3484 DRM_ERROR("[drm] AA resolve buffer %d (%u %u %u %u)\n",
3485 i, track->aa.pitch, track->cb[0].cpp,
3486 track->aa.offset, track->maxy);
3487 return -EINVAL;
3488 }
3489 }
3490 track->aa_dirty = false;
3491
551ebd83 3492 prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
cae94b0a
MO		 3493 if (track->vap_vf_cntl & (1 << 14)) {
3494 nverts = track->vap_alt_nverts;
3495 } else {
3496 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
3497 }
551ebd83
DA		 3498 switch (prim_walk) {
3499 case 1:
3500 for (i = 0; i < track->num_arrays; i++) {
3501 size = track->arrays[i].esize * track->max_indx * 4;
3502 if (track->arrays[i].robj == NULL) {
3503 DRM_ERROR("(PW %u) Vertex array %u no buffer "
3504 "bound\n", prim_walk, i);
3505 return -EINVAL;
3506 }
4c788679
JG		 3507 if (size > radeon_bo_size(track->arrays[i].robj)) {
3508 dev_err(rdev->dev, "(PW %u) Vertex array %u "
3509 "need %lu dwords have %lu dwords\n",
3510 prim_walk, i, size >> 2,
3511 radeon_bo_size(track->arrays[i].robj)
3512 >> 2);
551ebd83
DA		 3513 DRM_ERROR("Max indices %u\n", track->max_indx);
3514 return -EINVAL;
3515 }
3516 }
3517 break;
3518 case 2:
3519 for (i = 0; i < track->num_arrays; i++) {
3520 size = track->arrays[i].esize * (nverts - 1) * 4;
3521 if (track->arrays[i].robj == NULL) {
3522 DRM_ERROR("(PW %u) Vertex array %u no buffer "
3523 "bound\n", prim_walk, i);
3524 return -EINVAL;
3525 }
4c788679
JG		 3526 if (size > radeon_bo_size(track->arrays[i].robj)) {
3527 dev_err(rdev->dev, "(PW %u) Vertex array %u "
3528 "need %lu dwords have %lu dwords\n",
3529 prim_walk, i, size >> 2,
3530 radeon_bo_size(track->arrays[i].robj)
3531 >> 2);
551ebd83
DA		 3532 return -EINVAL;
3533 }
3534 }
3535 break;
3536 case 3:
3537 size = track->vtx_size * nverts;
3538 if (size != track->immd_dwords) {
3539 DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
3540 track->immd_dwords, size);
3541 DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
3542 nverts, track->vtx_size);
3543 return -EINVAL;
3544 }
3545 break;
3546 default:
3547 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
3548 prim_walk);
3549 return -EINVAL;
3550 }
40b4a759
MO		 3551
3552 if (track->tex_dirty) {
3553 track->tex_dirty = false;
3554 return r100_cs_track_texture_check(rdev, track);
3555 }
3556 return 0;
551ebd83
DA		 3557}
3558
3559void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track)
3560{
3561 unsigned i, face;
3562
40b4a759
MO		 3563 track->cb_dirty = true;
3564 track->zb_dirty = true;
3565 track->tex_dirty = true;
fff1ce4d 3566 track->aa_dirty = true;
40b4a759 3567
551ebd83
DA		 3568 if (rdev->family < CHIP_R300) {
3569 track->num_cb = 1;
3570 if (rdev->family <= CHIP_RS200)
3571 track->num_texture = 3;
3572 else
3573 track->num_texture = 6;
3574 track->maxy = 2048;
3575 track->separate_cube = 1;
3576 } else {
3577 track->num_cb = 4;
3578 track->num_texture = 16;
3579 track->maxy = 4096;
3580 track->separate_cube = 0;
45e4039c 3581 track->aaresolve = false;
fff1ce4d 3582 track->aa.robj = NULL;
551ebd83
DA		 3583 }
3584
3585 for (i = 0; i < track->num_cb; i++) {
3586 track->cb[i].robj = NULL;
3587 track->cb[i].pitch = 8192;
3588 track->cb[i].cpp = 16;
3589 track->cb[i].offset = 0;
3590 }
3591 track->z_enabled = true;
3592 track->zb.robj = NULL;
3593 track->zb.pitch = 8192;
3594 track->zb.cpp = 4;
3595 track->zb.offset = 0;
3596 track->vtx_size = 0x7F;
3597 track->immd_dwords = 0xFFFFFFFFUL;
3598 track->num_arrays = 11;
3599 track->max_indx = 0x00FFFFFFUL;
3600 for (i = 0; i < track->num_arrays; i++) {
3601 track->arrays[i].robj = NULL;
3602 track->arrays[i].esize = 0x7F;
3603 }
3604 for (i = 0; i < track->num_texture; i++) {
d785d78b 3605 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
551ebd83
DA		 3606 track->textures[i].pitch = 16536;
3607 track->textures[i].width = 16536;
3608 track->textures[i].height = 16536;
3609 track->textures[i].width_11 = 1 << 11;
3610 track->textures[i].height_11 = 1 << 11;
3611 track->textures[i].num_levels = 12;
3612 if (rdev->family <= CHIP_RS200) {
3613 track->textures[i].tex_coord_type = 0;
3614 track->textures[i].txdepth = 0;
3615 } else {
3616 track->textures[i].txdepth = 16;
3617 track->textures[i].tex_coord_type = 1;
3618 }
3619 track->textures[i].cpp = 64;
3620 track->textures[i].robj = NULL;
3621 /* CS IB emission code makes sure texture unit are disabled */
3622 track->textures[i].enabled = false;
43b93fbf 3623 track->textures[i].lookup_disable = false;
551ebd83
DA		 3624 track->textures[i].roundup_w = true;
3625 track->textures[i].roundup_h = true;
3626 if (track->separate_cube)
3627 for (face = 0; face < 5; face++) {
3628 track->textures[i].cube_info[face].robj = NULL;
3629 track->textures[i].cube_info[face].width = 16536;
3630 track->textures[i].cube_info[face].height = 16536;
3631 track->textures[i].cube_info[face].offset = 0;
3632 }
3633 }
3634}
3ce0a23d 3635
e32eb50d 3636int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
3ce0a23d
JG		 3637{
3638 uint32_t scratch;
3639 uint32_t tmp = 0;
3640 unsigned i;
3641 int r;
3642
3643 r = radeon_scratch_get(rdev, &scratch);
3644 if (r) {
3645 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
3646 return r;
3647 }
3648 WREG32(scratch, 0xCAFEDEAD);
e32eb50d 3649 r = radeon_ring_lock(rdev, ring, 2);
3ce0a23d
JG		 3650 if (r) {
3651 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
3652 radeon_scratch_free(rdev, scratch);
3653 return r;
3654 }
e32eb50d
CK		 3655 radeon_ring_write(ring, PACKET0(scratch, 0));
3656 radeon_ring_write(ring, 0xDEADBEEF);
3657 radeon_ring_unlock_commit(rdev, ring);
3ce0a23d
JG		 3658 for (i = 0; i < rdev->usec_timeout; i++) {
3659 tmp = RREG32(scratch);
3660 if (tmp == 0xDEADBEEF) {
3661 break;
3662 }
3663 DRM_UDELAY(1);
3664 }
3665 if (i < rdev->usec_timeout) {
3666 DRM_INFO("ring test succeeded in %d usecs\n", i);
3667 } else {
369d7ec1 3668 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
3ce0a23d
JG		 3669 scratch, tmp);
3670 r = -EINVAL;
3671 }
3672 radeon_scratch_free(rdev, scratch);
3673 return r;
3674}
3675
3676void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3677{
e32eb50d 3678 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
7b1f2485 3679
e32eb50d
CK		 3680 radeon_ring_write(ring, PACKET0(RADEON_CP_IB_BASE, 1));
3681 radeon_ring_write(ring, ib->gpu_addr);
3682 radeon_ring_write(ring, ib->length_dw);
3ce0a23d
JG		 3683}
3684
f712812e 3685int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
3ce0a23d 3686{
f2e39221 3687 struct radeon_ib ib;
3ce0a23d
JG		 3688 uint32_t scratch;
3689 uint32_t tmp = 0;
3690 unsigned i;
3691 int r;
3692
3693 r = radeon_scratch_get(rdev, &scratch);
3694 if (r) {
3695 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3696 return r;
3697 }
3698 WREG32(scratch, 0xCAFEDEAD);
69e130a6 3699 r = radeon_ib_get(rdev, RADEON_RING_TYPE_GFX_INDEX, &ib, 256);
3ce0a23d
JG		 3700 if (r) {
3701 return r;
3702 }
f2e39221
JG		 3703 ib.ptr[0] = PACKET0(scratch, 0);
3704 ib.ptr[1] = 0xDEADBEEF;
3705 ib.ptr[2] = PACKET2(0);
3706 ib.ptr[3] = PACKET2(0);
3707 ib.ptr[4] = PACKET2(0);
3708 ib.ptr[5] = PACKET2(0);
3709 ib.ptr[6] = PACKET2(0);
3710 ib.ptr[7] = PACKET2(0);
3711 ib.length_dw = 8;
3712 r = radeon_ib_schedule(rdev, &ib);
3ce0a23d
JG		 3713 if (r) {
3714 radeon_scratch_free(rdev, scratch);
3715 radeon_ib_free(rdev, &ib);
3716 return r;
3717 }
f2e39221 3718 r = radeon_fence_wait(ib.fence, false);
3ce0a23d
JG		 3719 if (r) {
3720 return r;
3721 }
3722 for (i = 0; i < rdev->usec_timeout; i++) {
3723 tmp = RREG32(scratch);
3724 if (tmp == 0xDEADBEEF) {
3725 break;
3726 }
3727 DRM_UDELAY(1);
3728 }
3729 if (i < rdev->usec_timeout) {
3730 DRM_INFO("ib test succeeded in %u usecs\n", i);
3731 } else {
62f288cf 3732 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
3ce0a23d
JG		 3733 scratch, tmp);
3734 r = -EINVAL;
3735 }
3736 radeon_scratch_free(rdev, scratch);
3737 radeon_ib_free(rdev, &ib);
3738 return r;
3739}
9f022ddf
JG		 3740
3741void r100_ib_fini(struct radeon_device *rdev)
3742{
b15ba512 3743 radeon_ib_pool_suspend(rdev);
9f022ddf
JG		 3744 radeon_ib_pool_fini(rdev);
3745}
3746
9f022ddf
JG		 3747void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
3748{
3749 /* Shutdown CP we shouldn't need to do that but better be safe than
3750 * sorry
3751 */
e32eb50d 3752 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
9f022ddf
JG		 3753 WREG32(R_000740_CP_CSQ_CNTL, 0);
3754
3755 /* Save few CRTC registers */
ca6ffc64 3756 save->GENMO_WT = RREG8(R_0003C2_GENMO_WT);
9f022ddf
JG		 3757 save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
3758 save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
3759 save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
3760 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3761 save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL);
3762 save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET);
3763 }
3764
3765 /* Disable VGA aperture access */
ca6ffc64 3766 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT);
9f022ddf
JG		 3767 /* Disable cursor, overlay, crtc */
3768 WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1));
3769 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL |
3770 S_000054_CRTC_DISPLAY_DIS(1));
3771 WREG32(R_000050_CRTC_GEN_CNTL,
3772 (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) |
3773 S_000050_CRTC_DISP_REQ_EN_B(1));
3774 WREG32(R_000420_OV0_SCALE_CNTL,
3775 C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL));
3776 WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET);
3777 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3778 WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET |
3779 S_000360_CUR2_LOCK(1));
3780 WREG32(R_0003F8_CRTC2_GEN_CNTL,
3781 (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) |
3782 S_0003F8_CRTC2_DISPLAY_DIS(1) |
3783 S_0003F8_CRTC2_DISP_REQ_EN_B(1));
3784 WREG32(R_000360_CUR2_OFFSET,
3785 C_000360_CUR2_LOCK & save->CUR2_OFFSET);
3786 }
3787}
3788
3789void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save)
3790{
3791 /* Update base address for crtc */
d594e46a 3792 WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
9f022ddf 3793 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
d594e46a 3794 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
9f022ddf
JG		 3795 }
3796 /* Restore CRTC registers */
ca6ffc64 3797 WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);
9f022ddf
JG		 3798 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
3799 WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
3800 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3801 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
3802 }
3803}
ca6ffc64
JG		 3804
3805void r100_vga_render_disable(struct radeon_device *rdev)
3806{
d4550907 3807 u32 tmp;
ca6ffc64 3808
d4550907 3809 tmp = RREG8(R_0003C2_GENMO_WT);
ca6ffc64
JG		 3810 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);
3811}
d4550907
JG		 3812
3813static void r100_debugfs(struct radeon_device *rdev)
3814{
3815 int r;
3816
3817 r = r100_debugfs_mc_info_init(rdev);
3818 if (r)
3819 dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n");
3820}
3821
3822static void r100_mc_program(struct radeon_device *rdev)
3823{
3824 struct r100_mc_save save;
3825
3826 /* Stops all mc clients */
3827 r100_mc_stop(rdev, &save);
3828 if (rdev->flags & RADEON_IS_AGP) {
3829 WREG32(R_00014C_MC_AGP_LOCATION,
3830 S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
3831 S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
3832 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
3833 if (rdev->family > CHIP_RV200)
3834 WREG32(R_00015C_AGP_BASE_2,
3835 upper_32_bits(rdev->mc.agp_base) & 0xff);
3836 } else {
3837 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
3838 WREG32(R_000170_AGP_BASE, 0);
3839 if (rdev->family > CHIP_RV200)
3840 WREG32(R_00015C_AGP_BASE_2, 0);
3841 }
3842 /* Wait for mc idle */
3843 if (r100_mc_wait_for_idle(rdev))
3844 dev_warn(rdev->dev, "Wait for MC idle timeout.\n");
3845 /* Program MC, should be a 32bits limited address space */
3846 WREG32(R_000148_MC_FB_LOCATION,
3847 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
3848 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
3849 r100_mc_resume(rdev, &save);
3850}
3851
3852void r100_clock_startup(struct radeon_device *rdev)
3853{
3854 u32 tmp;
3855
3856 if (radeon_dynclks != -1 && radeon_dynclks)
3857 radeon_legacy_set_clock_gating(rdev, 1);
3858 /* We need to force on some of the block */
3859 tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
3860 tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
3861 if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280))
3862 tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1);
3863 WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
3864}
3865
3866static int r100_startup(struct radeon_device *rdev)
3867{
3868 int r;
3869
92cde00c
AD		 3870 /* set common regs */
3871 r100_set_common_regs(rdev);
3872 /* program mc */
d4550907
JG		 3873 r100_mc_program(rdev);
3874 /* Resume clock */
3875 r100_clock_startup(rdev);
d4550907
JG		 3876 /* Initialize GART (initialize after TTM so we can allocate
3877 * memory through TTM but finalize after TTM) */
17e15b0c 3878 r100_enable_bm(rdev);
d4550907
JG		 3879 if (rdev->flags & RADEON_IS_PCI) {
3880 r = r100_pci_gart_enable(rdev);
3881 if (r)
3882 return r;
3883 }
724c80e1
AD		 3884
3885 /* allocate wb buffer */
3886 r = radeon_wb_init(rdev);
3887 if (r)
3888 return r;
3889
30eb77f4
JG		 3890 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
3891 if (r) {
3892 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
3893 return r;
3894 }
3895
d4550907 3896 /* Enable IRQ */
d4550907 3897 r100_irq_set(rdev);
cafe6609 3898 rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
d4550907
JG		 3899 /* 1M ring buffer */
3900 r = r100_cp_init(rdev, 1024 * 1024);
3901 if (r) {
ec4f2ac4 3902 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
d4550907
JG		 3903 return r;
3904 }
b15ba512
JG		 3905
3906 r = radeon_ib_pool_start(rdev);
3907 if (r)
3908 return r;
3909
7bd560e8
CK		 3910 r = radeon_ib_ring_tests(rdev);
3911 if (r)
d4550907 3912 return r;
b15ba512 3913
d4550907
JG		 3914 return 0;
3915}
3916
3917int r100_resume(struct radeon_device *rdev)
3918{
6b7746e8
JG		 3919 int r;
3920
d4550907
JG		 3921 /* Make sur GART are not working */
3922 if (rdev->flags & RADEON_IS_PCI)
3923 r100_pci_gart_disable(rdev);
3924 /* Resume clock before doing reset */
3925 r100_clock_startup(rdev);
3926 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
a2d07b74 3927 if (radeon_asic_reset(rdev)) {
d4550907
JG		 3928 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3929 RREG32(R_000E40_RBBM_STATUS),
3930 RREG32(R_0007C0_CP_STAT));
3931 }
3932 /* post */
3933 radeon_combios_asic_init(rdev->ddev);
3934 /* Resume clock after posting */
3935 r100_clock_startup(rdev);
550e2d92
DA		 3936 /* Initialize surface registers */
3937 radeon_surface_init(rdev);
b15ba512
JG		 3938
3939 rdev->accel_working = true;
6b7746e8
JG		 3940 r = r100_startup(rdev);
3941 if (r) {
3942 rdev->accel_working = false;
3943 }
3944 return r;
d4550907
JG		 3945}
3946
3947int r100_suspend(struct radeon_device *rdev)
3948{
b15ba512 3949 radeon_ib_pool_suspend(rdev);
d4550907 3950 r100_cp_disable(rdev);
724c80e1 3951 radeon_wb_disable(rdev);
d4550907
JG		 3952 r100_irq_disable(rdev);
3953 if (rdev->flags & RADEON_IS_PCI)
3954 r100_pci_gart_disable(rdev);
3955 return 0;
3956}
3957
3958void r100_fini(struct radeon_device *rdev)
3959{
d4550907 3960 r100_cp_fini(rdev);
724c80e1 3961 radeon_wb_fini(rdev);
d4550907
JG		 3962 r100_ib_fini(rdev);
3963 radeon_gem_fini(rdev);
3964 if (rdev->flags & RADEON_IS_PCI)
3965 r100_pci_gart_fini(rdev);
d0269ed8 3966 radeon_agp_fini(rdev);
d4550907
JG		 3967 radeon_irq_kms_fini(rdev);
3968 radeon_fence_driver_fini(rdev);
4c788679 3969 radeon_bo_fini(rdev);
d4550907
JG		 3970 radeon_atombios_fini(rdev);
3971 kfree(rdev->bios);
3972 rdev->bios = NULL;
3973}
3974
4c712e6c
DA		 3975/*
3976 * Due to how kexec works, it can leave the hw fully initialised when it
3977 * boots the new kernel. However doing our init sequence with the CP and
3978 * WB stuff setup causes GPU hangs on the RN50 at least. So at startup
3979 * do some quick sanity checks and restore sane values to avoid this
3980 * problem.
3981 */
3982void r100_restore_sanity(struct radeon_device *rdev)
3983{
3984 u32 tmp;
3985
3986 tmp = RREG32(RADEON_CP_CSQ_CNTL);
3987 if (tmp) {
3988 WREG32(RADEON_CP_CSQ_CNTL, 0);
3989 }
3990 tmp = RREG32(RADEON_CP_RB_CNTL);
3991 if (tmp) {
3992 WREG32(RADEON_CP_RB_CNTL, 0);
3993 }
3994 tmp = RREG32(RADEON_SCRATCH_UMSK);
3995 if (tmp) {
3996 WREG32(RADEON_SCRATCH_UMSK, 0);
3997 }
3998}
3999
d4550907
JG		 4000int r100_init(struct radeon_device *rdev)
4001{
4002 int r;
4003
d4550907
JG		 4004 /* Register debugfs file specific to this group of asics */
4005 r100_debugfs(rdev);
4006 /* Disable VGA */
4007 r100_vga_render_disable(rdev);
4008 /* Initialize scratch registers */
4009 radeon_scratch_init(rdev);
4010 /* Initialize surface registers */
4011 radeon_surface_init(rdev);
4c712e6c
DA		 4012 /* sanity check some register to avoid hangs like after kexec */
4013 r100_restore_sanity(rdev);
d4550907
JG		 4014 /* TODO: disable VGA need to use VGA request */
4015 /* BIOS*/
4016 if (!radeon_get_bios(rdev)) {
4017 if (ASIC_IS_AVIVO(rdev))
4018 return -EINVAL;
4019 }
4020 if (rdev->is_atom_bios) {
4021 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
4022 return -EINVAL;
4023 } else {
4024 r = radeon_combios_init(rdev);
4025 if (r)
4026 return r;
4027 }
4028 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
a2d07b74 4029 if (radeon_asic_reset(rdev)) {
d4550907
JG		 4030 dev_warn(rdev->dev,
4031 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
4032 RREG32(R_000E40_RBBM_STATUS),
4033 RREG32(R_0007C0_CP_STAT));
4034 }
4035 /* check if cards are posted or not */
72542d77
DA		 4036 if (radeon_boot_test_post_card(rdev) == false)
4037 return -EINVAL;
d4550907
JG		 4038 /* Set asic errata */
4039 r100_errata(rdev);
4040 /* Initialize clocks */
4041 radeon_get_clock_info(rdev->ddev);
d594e46a
JG		 4042 /* initialize AGP */
4043 if (rdev->flags & RADEON_IS_AGP) {
4044 r = radeon_agp_init(rdev);
4045 if (r) {
4046 radeon_agp_disable(rdev);
4047 }
4048 }
4049 /* initialize VRAM */
4050 r100_mc_init(rdev);
d4550907 4051 /* Fence driver */
30eb77f4 4052 r = radeon_fence_driver_init(rdev);
d4550907
JG		 4053 if (r)
4054 return r;
4055 r = radeon_irq_kms_init(rdev);
4056 if (r)
4057 return r;
4058 /* Memory manager */
4c788679 4059 r = radeon_bo_init(rdev);
d4550907
JG		 4060 if (r)
4061 return r;
4062 if (rdev->flags & RADEON_IS_PCI) {
4063 r = r100_pci_gart_init(rdev);
4064 if (r)
4065 return r;
4066 }
4067 r100_set_safe_registers(rdev);
b15ba512
JG		 4068
4069 r = radeon_ib_pool_init(rdev);
d4550907 4070 rdev->accel_working = true;
b15ba512
JG		 4071 if (r) {
4072 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
4073 rdev->accel_working = false;
4074 }
4075
d4550907
JG		 4076 r = r100_startup(rdev);
4077 if (r) {
4078 /* Somethings want wront with the accel init stop accel */
4079 dev_err(rdev->dev, "Disabling GPU acceleration\n");
d4550907 4080 r100_cp_fini(rdev);
724c80e1 4081 radeon_wb_fini(rdev);
d4550907 4082 r100_ib_fini(rdev);
655efd3d 4083 radeon_irq_kms_fini(rdev);
d4550907
JG		 4084 if (rdev->flags & RADEON_IS_PCI)
4085 r100_pci_gart_fini(rdev);
d4550907
JG		 4086 rdev->accel_working = false;
4087 }
4088 return 0;
4089}
6fcbef7a
AK		 4090
4091uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
4092{
4093 if (reg < rdev->rmmio_size)
4094 return readl(((void __iomem *)rdev->rmmio) + reg);
4095 else {
4096 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
4097 return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
4098 }
4099}
4100
4101void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
4102{
4103 if (reg < rdev->rmmio_size)
4104 writel(v, ((void __iomem *)rdev->rmmio) + reg);
4105 else {
4106 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
4107 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
4108 }
4109}
4110
4111u32 r100_io_rreg(struct radeon_device *rdev, u32 reg)
4112{
4113 if (reg < rdev->rio_mem_size)
4114 return ioread32(rdev->rio_mem + reg);
4115 else {
4116 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
4117 return ioread32(rdev->rio_mem + RADEON_MM_DATA);
4118 }
4119}
4120
4121void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v)
4122{
4123 if (reg < rdev->rio_mem_size)
4124 iowrite32(v, rdev->rio_mem + reg);
4125 else {
4126 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
4127 iowrite32(v, rdev->rio_mem + RADEON_MM_DATA);
4128 }
4129}
Linux kernel - Deliverables
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