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Merge tag 'master-2014-11-25' of git://git.kernel.org/pub/scm/linux/kernel/git/linvil...
[deliverable/linux.git] / drivers / gpu / drm / radeon / r100.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#include <linux/seq_file.h>
5a0e3ad6 29#include <linux/slab.h>
760285e7
DH		 30#include <drm/drmP.h>
31#include <drm/radeon_drm.h>
771fe6b9
JG		 32#include "radeon_reg.h"
33#include "radeon.h"
e6990375 34#include "radeon_asic.h"
3ce0a23d 35#include "r100d.h"
d4550907
JG		 36#include "rs100d.h"
37#include "rv200d.h"
38#include "rv250d.h"
49e02b73 39#include "atom.h"
3ce0a23d 40
70967ab9 41#include <linux/firmware.h>
e0cd3608 42#include <linux/module.h>
70967ab9 43
551ebd83
DA		 44#include "r100_reg_safe.h"
45#include "rn50_reg_safe.h"
46
70967ab9
BH		 47/* Firmware Names */
48#define FIRMWARE_R100 "radeon/R100_cp.bin"
49#define FIRMWARE_R200 "radeon/R200_cp.bin"
50#define FIRMWARE_R300 "radeon/R300_cp.bin"
51#define FIRMWARE_R420 "radeon/R420_cp.bin"
52#define FIRMWARE_RS690 "radeon/RS690_cp.bin"
53#define FIRMWARE_RS600 "radeon/RS600_cp.bin"
54#define FIRMWARE_R520 "radeon/R520_cp.bin"
55
56MODULE_FIRMWARE(FIRMWARE_R100);
57MODULE_FIRMWARE(FIRMWARE_R200);
58MODULE_FIRMWARE(FIRMWARE_R300);
59MODULE_FIRMWARE(FIRMWARE_R420);
60MODULE_FIRMWARE(FIRMWARE_RS690);
61MODULE_FIRMWARE(FIRMWARE_RS600);
62MODULE_FIRMWARE(FIRMWARE_R520);
771fe6b9 63
551ebd83
DA		 64#include "r100_track.h"
65
48ef779f
AD		 66/* This files gather functions specifics to:
67 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
68 * and others in some cases.
69 */
70
2b48b968
AD		 71static bool r100_is_in_vblank(struct radeon_device *rdev, int crtc)
72{
73 if (crtc == 0) {
74 if (RREG32(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_CUR)
75 return true;
76 else
77 return false;
78 } else {
79 if (RREG32(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_CUR)
80 return true;
81 else
82 return false;
83 }
84}
85
86static bool r100_is_counter_moving(struct radeon_device *rdev, int crtc)
87{
88 u32 vline1, vline2;
89
90 if (crtc == 0) {
91 vline1 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
92 vline2 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
93 } else {
94 vline1 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
95 vline2 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
96 }
97 if (vline1 != vline2)
98 return true;
99 else
100 return false;
101}
102
48ef779f
AD		 103/**
104 * r100_wait_for_vblank - vblank wait asic callback.
105 *
106 * @rdev: radeon_device pointer
107 * @crtc: crtc to wait for vblank on
108 *
109 * Wait for vblank on the requested crtc (r1xx-r4xx).
110 */
3ae19b75
AD		 111void r100_wait_for_vblank(struct radeon_device *rdev, int crtc)
112{
2b48b968 113 unsigned i = 0;
3ae19b75 114
94f768fd
AD		 115 if (crtc >= rdev->num_crtc)
116 return;
117
118 if (crtc == 0) {
2b48b968
AD		 119 if (!(RREG32(RADEON_CRTC_GEN_CNTL) & RADEON_CRTC_EN))
120 return;
3ae19b75 121 } else {
2b48b968
AD		 122 if (!(RREG32(RADEON_CRTC2_GEN_CNTL) & RADEON_CRTC2_EN))
123 return;
124 }
125
126 /* depending on when we hit vblank, we may be close to active; if so,
127 * wait for another frame.
128 */
129 while (r100_is_in_vblank(rdev, crtc)) {
130 if (i++ % 100 == 0) {
131 if (!r100_is_counter_moving(rdev, crtc))
132 break;
133 }
134 }
135
136 while (!r100_is_in_vblank(rdev, crtc)) {
137 if (i++ % 100 == 0) {
138 if (!r100_is_counter_moving(rdev, crtc))
139 break;
3ae19b75
AD		 140 }
141 }
142}
143
48ef779f
AD		 144/**
145 * r100_page_flip - pageflip callback.
146 *
147 * @rdev: radeon_device pointer
148 * @crtc_id: crtc to cleanup pageflip on
149 * @crtc_base: new address of the crtc (GPU MC address)
150 *
151 * Does the actual pageflip (r1xx-r4xx).
152 * During vblank we take the crtc lock and wait for the update_pending
153 * bit to go high, when it does, we release the lock, and allow the
154 * double buffered update to take place.
48ef779f 155 */
157fa14d 156void r100_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
6f34be50
AD		 157{
158 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
159 u32 tmp = ((u32)crtc_base) | RADEON_CRTC_OFFSET__OFFSET_LOCK;
f6496479 160 int i;
6f34be50
AD		 161
162 /* Lock the graphics update lock */
163 /* update the scanout addresses */
164 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
165
acb32506 166 /* Wait for update_pending to go high. */
f6496479
AD		 167 for (i = 0; i < rdev->usec_timeout; i++) {
168 if (RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET)
169 break;
170 udelay(1);
171 }
acb32506 172 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
6f34be50
AD		 173
174 /* Unlock the lock, so double-buffering can take place inside vblank */
175 tmp &= ~RADEON_CRTC_OFFSET__OFFSET_LOCK;
176 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
177
157fa14d
CK		 178}
179
180/**
181 * r100_page_flip_pending - check if page flip is still pending
182 *
183 * @rdev: radeon_device pointer
184 * @crtc_id: crtc to check
185 *
186 * Check if the last pagefilp is still pending (r1xx-r4xx).
187 * Returns the current update pending status.
188 */
189bool r100_page_flip_pending(struct radeon_device *rdev, int crtc_id)
190{
191 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
192
6f34be50 193 /* Return current update_pending status: */
157fa14d
CK		 194 return !!(RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) &
195 RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET);
6f34be50
AD		 196}
197
48ef779f
AD		 198/**
199 * r100_pm_get_dynpm_state - look up dynpm power state callback.
200 *
201 * @rdev: radeon_device pointer
202 *
203 * Look up the optimal power state based on the
204 * current state of the GPU (r1xx-r5xx).
205 * Used for dynpm only.
206 */
ce8f5370 207void r100_pm_get_dynpm_state(struct radeon_device *rdev)
a48b9b4e
AD		 208{
209 int i;
ce8f5370
AD		 210 rdev->pm.dynpm_can_upclock = true;
211 rdev->pm.dynpm_can_downclock = true;
a48b9b4e 212
ce8f5370
AD		 213 switch (rdev->pm.dynpm_planned_action) {
214 case DYNPM_ACTION_MINIMUM:
a48b9b4e 215 rdev->pm.requested_power_state_index = 0;
ce8f5370 216 rdev->pm.dynpm_can_downclock = false;
a48b9b4e 217 break;
ce8f5370 218 case DYNPM_ACTION_DOWNCLOCK:
a48b9b4e
AD		 219 if (rdev->pm.current_power_state_index == 0) {
220 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
ce8f5370 221 rdev->pm.dynpm_can_downclock = false;
a48b9b4e
AD		 222 } else {
223 if (rdev->pm.active_crtc_count > 1) {
224 for (i = 0; i < rdev->pm.num_power_states; i++) {
d7311171 225 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
a48b9b4e
AD		 226 continue;
227 else if (i >= rdev->pm.current_power_state_index) {
228 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
229 break;
230 } else {
231 rdev->pm.requested_power_state_index = i;
232 break;
233 }
234 }
235 } else
236 rdev->pm.requested_power_state_index =
237 rdev->pm.current_power_state_index - 1;
238 }
d7311171
AD		 239 /* don't use the power state if crtcs are active and no display flag is set */
240 if ((rdev->pm.active_crtc_count > 0) &&
241 (rdev->pm.power_state[rdev->pm.requested_power_state_index].clock_info[0].flags &
242 RADEON_PM_MODE_NO_DISPLAY)) {
243 rdev->pm.requested_power_state_index++;
244 }
a48b9b4e 245 break;
ce8f5370 246 case DYNPM_ACTION_UPCLOCK:
a48b9b4e
AD		 247 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
248 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
ce8f5370 249 rdev->pm.dynpm_can_upclock = false;
a48b9b4e
AD		 250 } else {
251 if (rdev->pm.active_crtc_count > 1) {
252 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
d7311171 253 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
a48b9b4e
AD		 254 continue;
255 else if (i <= rdev->pm.current_power_state_index) {
256 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
257 break;
258 } else {
259 rdev->pm.requested_power_state_index = i;
260 break;
261 }
262 }
263 } else
264 rdev->pm.requested_power_state_index =
265 rdev->pm.current_power_state_index + 1;
266 }
267 break;
ce8f5370 268 case DYNPM_ACTION_DEFAULT:
58e21dff 269 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
ce8f5370 270 rdev->pm.dynpm_can_upclock = false;
58e21dff 271 break;
ce8f5370 272 case DYNPM_ACTION_NONE:
a48b9b4e
AD		 273 default:
274 DRM_ERROR("Requested mode for not defined action\n");
275 return;
276 }
277 /* only one clock mode per power state */
278 rdev->pm.requested_clock_mode_index = 0;
279
d9fdaafb 280 DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
ce8a3eb2
AD		 281 rdev->pm.power_state[rdev->pm.requested_power_state_index].
282 clock_info[rdev->pm.requested_clock_mode_index].sclk,
283 rdev->pm.power_state[rdev->pm.requested_power_state_index].
284 clock_info[rdev->pm.requested_clock_mode_index].mclk,
285 rdev->pm.power_state[rdev->pm.requested_power_state_index].
286 pcie_lanes);
a48b9b4e
AD		 287}
288
48ef779f
AD		 289/**
290 * r100_pm_init_profile - Initialize power profiles callback.
291 *
292 * @rdev: radeon_device pointer
293 *
294 * Initialize the power states used in profile mode
295 * (r1xx-r3xx).
296 * Used for profile mode only.
297 */
ce8f5370
AD		 298void r100_pm_init_profile(struct radeon_device *rdev)
299{
300 /* default */
301 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
302 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
303 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
304 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
305 /* low sh */
306 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
307 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
308 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
309 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 310 /* mid sh */
311 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
312 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
313 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
314 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 315 /* high sh */
316 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
317 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
318 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
319 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
320 /* low mh */
321 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
322 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
323 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
324 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 325 /* mid mh */
326 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
327 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
328 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
329 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 330 /* high mh */
331 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
332 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
333 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
334 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
bae6b562
AD		 335}
336
48ef779f
AD		 337/**
338 * r100_pm_misc - set additional pm hw parameters callback.
339 *
340 * @rdev: radeon_device pointer
341 *
342 * Set non-clock parameters associated with a power state
343 * (voltage, pcie lanes, etc.) (r1xx-r4xx).
344 */
49e02b73
AD		 345void r100_pm_misc(struct radeon_device *rdev)
346{
49e02b73
AD		 347 int requested_index = rdev->pm.requested_power_state_index;
348 struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
349 struct radeon_voltage *voltage = &ps->clock_info[0].voltage;
350 u32 tmp, sclk_cntl, sclk_cntl2, sclk_more_cntl;
351
352 if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) {
353 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
354 tmp = RREG32(voltage->gpio.reg);
355 if (voltage->active_high)
356 tmp |= voltage->gpio.mask;
357 else
358 tmp &= ~(voltage->gpio.mask);
359 WREG32(voltage->gpio.reg, tmp);
360 if (voltage->delay)
361 udelay(voltage->delay);
362 } else {
363 tmp = RREG32(voltage->gpio.reg);
364 if (voltage->active_high)
365 tmp &= ~voltage->gpio.mask;
366 else
367 tmp |= voltage->gpio.mask;
368 WREG32(voltage->gpio.reg, tmp);
369 if (voltage->delay)
370 udelay(voltage->delay);
371 }
372 }
373
374 sclk_cntl = RREG32_PLL(SCLK_CNTL);
375 sclk_cntl2 = RREG32_PLL(SCLK_CNTL2);
376 sclk_cntl2 &= ~REDUCED_SPEED_SCLK_SEL(3);
377 sclk_more_cntl = RREG32_PLL(SCLK_MORE_CNTL);
378 sclk_more_cntl &= ~VOLTAGE_DELAY_SEL(3);
379 if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) {
380 sclk_more_cntl |= REDUCED_SPEED_SCLK_EN;
381 if (ps->misc & ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE)
382 sclk_cntl2 |= REDUCED_SPEED_SCLK_MODE;
383 else
384 sclk_cntl2 &= ~REDUCED_SPEED_SCLK_MODE;
385 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2)
386 sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(0);
387 else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4)
388 sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(2);
389 } else
390 sclk_more_cntl &= ~REDUCED_SPEED_SCLK_EN;
391
392 if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) {
393 sclk_more_cntl |= IO_CG_VOLTAGE_DROP;
394 if (voltage->delay) {
395 sclk_more_cntl |= VOLTAGE_DROP_SYNC;
396 switch (voltage->delay) {
397 case 33:
398 sclk_more_cntl |= VOLTAGE_DELAY_SEL(0);
399 break;
400 case 66:
401 sclk_more_cntl |= VOLTAGE_DELAY_SEL(1);
402 break;
403 case 99:
404 sclk_more_cntl |= VOLTAGE_DELAY_SEL(2);
405 break;
406 case 132:
407 sclk_more_cntl |= VOLTAGE_DELAY_SEL(3);
408 break;
409 }
410 } else
411 sclk_more_cntl &= ~VOLTAGE_DROP_SYNC;
412 } else
413 sclk_more_cntl &= ~IO_CG_VOLTAGE_DROP;
414
415 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN)
416 sclk_cntl &= ~FORCE_HDP;
417 else
418 sclk_cntl |= FORCE_HDP;
419
420 WREG32_PLL(SCLK_CNTL, sclk_cntl);
421 WREG32_PLL(SCLK_CNTL2, sclk_cntl2);
422 WREG32_PLL(SCLK_MORE_CNTL, sclk_more_cntl);
423
424 /* set pcie lanes */
425 if ((rdev->flags & RADEON_IS_PCIE) &&
426 !(rdev->flags & RADEON_IS_IGP) &&
798bcf73 427 rdev->asic->pm.set_pcie_lanes &&
49e02b73
AD		 428 (ps->pcie_lanes !=
429 rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {
430 radeon_set_pcie_lanes(rdev,
431 ps->pcie_lanes);
d9fdaafb 432 DRM_DEBUG_DRIVER("Setting: p: %d\n", ps->pcie_lanes);
49e02b73 433 }
49e02b73
AD		 434}
435
48ef779f
AD		 436/**
437 * r100_pm_prepare - pre-power state change callback.
438 *
439 * @rdev: radeon_device pointer
440 *
441 * Prepare for a power state change (r1xx-r4xx).
442 */
49e02b73
AD		 443void r100_pm_prepare(struct radeon_device *rdev)
444{
445 struct drm_device *ddev = rdev->ddev;
446 struct drm_crtc *crtc;
447 struct radeon_crtc *radeon_crtc;
448 u32 tmp;
449
450 /* disable any active CRTCs */
451 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
452 radeon_crtc = to_radeon_crtc(crtc);
453 if (radeon_crtc->enabled) {
454 if (radeon_crtc->crtc_id) {
455 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
456 tmp |= RADEON_CRTC2_DISP_REQ_EN_B;
457 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
458 } else {
459 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
460 tmp |= RADEON_CRTC_DISP_REQ_EN_B;
461 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
462 }
463 }
464 }
465}
466
48ef779f
AD		 467/**
468 * r100_pm_finish - post-power state change callback.
469 *
470 * @rdev: radeon_device pointer
471 *
472 * Clean up after a power state change (r1xx-r4xx).
473 */
49e02b73
AD		 474void r100_pm_finish(struct radeon_device *rdev)
475{
476 struct drm_device *ddev = rdev->ddev;
477 struct drm_crtc *crtc;
478 struct radeon_crtc *radeon_crtc;
479 u32 tmp;
480
481 /* enable any active CRTCs */
482 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
483 radeon_crtc = to_radeon_crtc(crtc);
484 if (radeon_crtc->enabled) {
485 if (radeon_crtc->crtc_id) {
486 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
487 tmp &= ~RADEON_CRTC2_DISP_REQ_EN_B;
488 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
489 } else {
490 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
491 tmp &= ~RADEON_CRTC_DISP_REQ_EN_B;
492 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
493 }
494 }
495 }
496}
497
48ef779f
AD		 498/**
499 * r100_gui_idle - gui idle callback.
500 *
501 * @rdev: radeon_device pointer
502 *
503 * Check of the GUI (2D/3D engines) are idle (r1xx-r5xx).
504 * Returns true if idle, false if not.
505 */
def9ba9c
AD		 506bool r100_gui_idle(struct radeon_device *rdev)
507{
508 if (RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE)
509 return false;
510 else
511 return true;
512}
513
05a05c50 514/* hpd for digital panel detect/disconnect */
48ef779f
AD		 515/**
516 * r100_hpd_sense - hpd sense callback.
517 *
518 * @rdev: radeon_device pointer
519 * @hpd: hpd (hotplug detect) pin
520 *
521 * Checks if a digital monitor is connected (r1xx-r4xx).
522 * Returns true if connected, false if not connected.
523 */
05a05c50
AD		 524bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
525{
526 bool connected = false;
527
528 switch (hpd) {
529 case RADEON_HPD_1:
530 if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE)
531 connected = true;
532 break;
533 case RADEON_HPD_2:
534 if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE)
535 connected = true;
536 break;
537 default:
538 break;
539 }
540 return connected;
541}
542
48ef779f
AD		 543/**
544 * r100_hpd_set_polarity - hpd set polarity callback.
545 *
546 * @rdev: radeon_device pointer
547 * @hpd: hpd (hotplug detect) pin
548 *
549 * Set the polarity of the hpd pin (r1xx-r4xx).
550 */
05a05c50
AD		 551void r100_hpd_set_polarity(struct radeon_device *rdev,
552 enum radeon_hpd_id hpd)
553{
554 u32 tmp;
555 bool connected = r100_hpd_sense(rdev, hpd);
556
557 switch (hpd) {
558 case RADEON_HPD_1:
559 tmp = RREG32(RADEON_FP_GEN_CNTL);
560 if (connected)
561 tmp &= ~RADEON_FP_DETECT_INT_POL;
562 else
563 tmp |= RADEON_FP_DETECT_INT_POL;
564 WREG32(RADEON_FP_GEN_CNTL, tmp);
565 break;
566 case RADEON_HPD_2:
567 tmp = RREG32(RADEON_FP2_GEN_CNTL);
568 if (connected)
569 tmp &= ~RADEON_FP2_DETECT_INT_POL;
570 else
571 tmp |= RADEON_FP2_DETECT_INT_POL;
572 WREG32(RADEON_FP2_GEN_CNTL, tmp);
573 break;
574 default:
575 break;
576 }
577}
578
48ef779f
AD		 579/**
580 * r100_hpd_init - hpd setup callback.
581 *
582 * @rdev: radeon_device pointer
583 *
584 * Setup the hpd pins used by the card (r1xx-r4xx).
585 * Set the polarity, and enable the hpd interrupts.
586 */
05a05c50
AD		 587void r100_hpd_init(struct radeon_device *rdev)
588{
589 struct drm_device *dev = rdev->ddev;
590 struct drm_connector *connector;
fb98257a 591 unsigned enable = 0;
05a05c50
AD		 592
593 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
594 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
fb98257a 595 enable |= 1 << radeon_connector->hpd.hpd;
64912e99 596 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
05a05c50 597 }
fb98257a 598 radeon_irq_kms_enable_hpd(rdev, enable);
05a05c50
AD		 599}
600
48ef779f
AD		 601/**
602 * r100_hpd_fini - hpd tear down callback.
603 *
604 * @rdev: radeon_device pointer
605 *
606 * Tear down the hpd pins used by the card (r1xx-r4xx).
607 * Disable the hpd interrupts.
608 */
05a05c50
AD		 609void r100_hpd_fini(struct radeon_device *rdev)
610{
611 struct drm_device *dev = rdev->ddev;
612 struct drm_connector *connector;
fb98257a 613 unsigned disable = 0;
05a05c50
AD		 614
615 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
616 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
fb98257a 617 disable |= 1 << radeon_connector->hpd.hpd;
05a05c50 618 }
fb98257a 619 radeon_irq_kms_disable_hpd(rdev, disable);
05a05c50
AD		 620}
621
771fe6b9
JG		 622/*
623 * PCI GART
624 */
625void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
626{
627 /* TODO: can we do somethings here ? */
628 /* It seems hw only cache one entry so we should discard this
629 * entry otherwise if first GPU GART read hit this entry it
630 * could end up in wrong address. */
631}
632
4aac0473 633int r100_pci_gart_init(struct radeon_device *rdev)
771fe6b9 634{
771fe6b9
JG		 635 int r;
636
c9a1be96 637 if (rdev->gart.ptr) {
fce7d61b 638 WARN(1, "R100 PCI GART already initialized\n");
4aac0473
JG		 639 return 0;
640 }
771fe6b9
JG		 641 /* Initialize common gart structure */
642 r = radeon_gart_init(rdev);
4aac0473 643 if (r)
771fe6b9 644 return r;
4aac0473 645 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
c5b3b850
AD		 646 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
647 rdev->asic->gart.set_page = &r100_pci_gart_set_page;
4aac0473
JG		 648 return radeon_gart_table_ram_alloc(rdev);
649}
650
651int r100_pci_gart_enable(struct radeon_device *rdev)
652{
653 uint32_t tmp;
654
771fe6b9
JG		 655 /* discard memory request outside of configured range */
656 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
657 WREG32(RADEON_AIC_CNTL, tmp);
658 /* set address range for PCI address translate */
d594e46a
JG		 659 WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start);
660 WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end);
771fe6b9
JG		 661 /* set PCI GART page-table base address */
662 WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
663 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
664 WREG32(RADEON_AIC_CNTL, tmp);
665 r100_pci_gart_tlb_flush(rdev);
43caf451 666 DRM_INFO("PCI GART of %uM enabled (table at 0x%016llX).\n",
fcf4de5a
TV		 667 (unsigned)(rdev->mc.gtt_size >> 20),
668 (unsigned long long)rdev->gart.table_addr);
771fe6b9
JG		 669 rdev->gart.ready = true;
670 return 0;
671}
672
673void r100_pci_gart_disable(struct radeon_device *rdev)
674{
675 uint32_t tmp;
676
677 /* discard memory request outside of configured range */
678 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
679 WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
680 WREG32(RADEON_AIC_LO_ADDR, 0);
681 WREG32(RADEON_AIC_HI_ADDR, 0);
682}
683
7f90fc96 684void r100_pci_gart_set_page(struct radeon_device *rdev, unsigned i,
77497f27 685 uint64_t addr, uint32_t flags)
771fe6b9 686{
c9a1be96 687 u32 *gtt = rdev->gart.ptr;
c9a1be96 688 gtt[i] = cpu_to_le32(lower_32_bits(addr));
771fe6b9
JG		 689}
690
4aac0473 691void r100_pci_gart_fini(struct radeon_device *rdev)
771fe6b9 692{
f9274562 693 radeon_gart_fini(rdev);
4aac0473
JG		 694 r100_pci_gart_disable(rdev);
695 radeon_gart_table_ram_free(rdev);
771fe6b9
JG		 696}
697
7ed220d7
MD		 698int r100_irq_set(struct radeon_device *rdev)
699{
700 uint32_t tmp = 0;
701
003e69f9 702 if (!rdev->irq.installed) {
fce7d61b 703 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
003e69f9
JG		 704 WREG32(R_000040_GEN_INT_CNTL, 0);
705 return -EINVAL;
706 }
736fc37f 707 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
7ed220d7
MD		 708 tmp |= RADEON_SW_INT_ENABLE;
709 }
6f34be50 710 if (rdev->irq.crtc_vblank_int[0] ||
736fc37f 711 atomic_read(&rdev->irq.pflip[0])) {
7ed220d7
MD		 712 tmp |= RADEON_CRTC_VBLANK_MASK;
713 }
6f34be50 714 if (rdev->irq.crtc_vblank_int[1] ||
736fc37f 715 atomic_read(&rdev->irq.pflip[1])) {
7ed220d7
MD		 716 tmp |= RADEON_CRTC2_VBLANK_MASK;
717 }
05a05c50
AD		 718 if (rdev->irq.hpd[0]) {
719 tmp |= RADEON_FP_DETECT_MASK;
720 }
721 if (rdev->irq.hpd[1]) {
722 tmp |= RADEON_FP2_DETECT_MASK;
723 }
7ed220d7
MD		 724 WREG32(RADEON_GEN_INT_CNTL, tmp);
725 return 0;
726}
727
9f022ddf
JG		 728void r100_irq_disable(struct radeon_device *rdev)
729{
730 u32 tmp;
731
732 WREG32(R_000040_GEN_INT_CNTL, 0);
733 /* Wait and acknowledge irq */
734 mdelay(1);
735 tmp = RREG32(R_000044_GEN_INT_STATUS);
736 WREG32(R_000044_GEN_INT_STATUS, tmp);
737}
738
cbdd4501 739static uint32_t r100_irq_ack(struct radeon_device *rdev)
7ed220d7
MD		 740{
741 uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
05a05c50
AD		 742 uint32_t irq_mask = RADEON_SW_INT_TEST |
743 RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT |
744 RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT;
7ed220d7
MD		 745
746 if (irqs) {
747 WREG32(RADEON_GEN_INT_STATUS, irqs);
748 }
749 return irqs & irq_mask;
750}
751
752int r100_irq_process(struct radeon_device *rdev)
753{
3e5cb98d 754 uint32_t status, msi_rearm;
d4877cf2 755 bool queue_hotplug = false;
7ed220d7
MD		 756
757 status = r100_irq_ack(rdev);
758 if (!status) {
759 return IRQ_NONE;
760 }
a513c184
JG		 761 if (rdev->shutdown) {
762 return IRQ_NONE;
763 }
7ed220d7
MD		 764 while (status) {
765 /* SW interrupt */
766 if (status & RADEON_SW_INT_TEST) {
7465280c 767 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
7ed220d7
MD		 768 }
769 /* Vertical blank interrupts */
770 if (status & RADEON_CRTC_VBLANK_STAT) {
6f34be50
AD		 771 if (rdev->irq.crtc_vblank_int[0]) {
772 drm_handle_vblank(rdev->ddev, 0);
773 rdev->pm.vblank_sync = true;
774 wake_up(&rdev->irq.vblank_queue);
775 }
736fc37f 776 if (atomic_read(&rdev->irq.pflip[0]))
1a0e7918 777 radeon_crtc_handle_vblank(rdev, 0);
7ed220d7
MD		 778 }
779 if (status & RADEON_CRTC2_VBLANK_STAT) {
6f34be50
AD		 780 if (rdev->irq.crtc_vblank_int[1]) {
781 drm_handle_vblank(rdev->ddev, 1);
782 rdev->pm.vblank_sync = true;
783 wake_up(&rdev->irq.vblank_queue);
784 }
736fc37f 785 if (atomic_read(&rdev->irq.pflip[1]))
1a0e7918 786 radeon_crtc_handle_vblank(rdev, 1);
7ed220d7 787 }
05a05c50 788 if (status & RADEON_FP_DETECT_STAT) {
d4877cf2
AD		 789 queue_hotplug = true;
790 DRM_DEBUG("HPD1\n");
05a05c50
AD		 791 }
792 if (status & RADEON_FP2_DETECT_STAT) {
d4877cf2
AD		 793 queue_hotplug = true;
794 DRM_DEBUG("HPD2\n");
05a05c50 795 }
7ed220d7
MD		 796 status = r100_irq_ack(rdev);
797 }
d4877cf2 798 if (queue_hotplug)
32c87fca 799 schedule_work(&rdev->hotplug_work);
3e5cb98d
AD		 800 if (rdev->msi_enabled) {
801 switch (rdev->family) {
802 case CHIP_RS400:
803 case CHIP_RS480:
804 msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM;
805 WREG32(RADEON_AIC_CNTL, msi_rearm);
806 WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM);
807 break;
808 default:
b7f5b7de 809 WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN);
3e5cb98d
AD		 810 break;
811 }
812 }
7ed220d7
MD		 813 return IRQ_HANDLED;
814}
815
816u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
817{
818 if (crtc == 0)
819 return RREG32(RADEON_CRTC_CRNT_FRAME);
820 else
821 return RREG32(RADEON_CRTC2_CRNT_FRAME);
822}
823
897eba82
MD		 824/**
825 * r100_ring_hdp_flush - flush Host Data Path via the ring buffer
826 * rdev: radeon device structure
827 * ring: ring buffer struct for emitting packets
828 */
829static void r100_ring_hdp_flush(struct radeon_device *rdev, struct radeon_ring *ring)
830{
831 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
832 radeon_ring_write(ring, rdev->config.r100.hdp_cntl |
833 RADEON_HDP_READ_BUFFER_INVALIDATE);
834 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
835 radeon_ring_write(ring, rdev->config.r100.hdp_cntl);
836}
837
9e5b2af7
PN		 838/* Who ever call radeon_fence_emit should call ring_lock and ask
839 * for enough space (today caller are ib schedule and buffer move) */
771fe6b9
JG		 840void r100_fence_ring_emit(struct radeon_device *rdev,
841 struct radeon_fence *fence)
842{
e32eb50d 843 struct radeon_ring *ring = &rdev->ring[fence->ring];
7b1f2485 844
9e5b2af7
PN		 845 /* We have to make sure that caches are flushed before
846 * CPU might read something from VRAM. */
e32eb50d
CK		 847 radeon_ring_write(ring, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));
848 radeon_ring_write(ring, RADEON_RB3D_DC_FLUSH_ALL);
849 radeon_ring_write(ring, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));
850 radeon_ring_write(ring, RADEON_RB3D_ZC_FLUSH_ALL);
771fe6b9 851 /* Wait until IDLE & CLEAN */
e32eb50d
CK		 852 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
853 radeon_ring_write(ring, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
72a9987e 854 r100_ring_hdp_flush(rdev, ring);
771fe6b9 855 /* Emit fence sequence & fire IRQ */
e32eb50d
CK		 856 radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0));
857 radeon_ring_write(ring, fence->seq);
858 radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0));
859 radeon_ring_write(ring, RADEON_SW_INT_FIRE);
771fe6b9
JG		 860}
861
1654b817 862bool r100_semaphore_ring_emit(struct radeon_device *rdev,
e32eb50d 863 struct radeon_ring *ring,
15d3332f 864 struct radeon_semaphore *semaphore,
7b1f2485 865 bool emit_wait)
15d3332f
CK		 866{
867 /* Unused on older asics, since we don't have semaphores or multiple rings */
868 BUG();
1654b817 869 return false;
15d3332f
CK		 870}
871
57d20a43
CK		 872struct radeon_fence *r100_copy_blit(struct radeon_device *rdev,
873 uint64_t src_offset,
874 uint64_t dst_offset,
875 unsigned num_gpu_pages,
876 struct reservation_object *resv)
771fe6b9 877{
e32eb50d 878 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
57d20a43 879 struct radeon_fence *fence;
771fe6b9 880 uint32_t cur_pages;
003cefe0 881 uint32_t stride_bytes = RADEON_GPU_PAGE_SIZE;
771fe6b9
JG		 882 uint32_t pitch;
883 uint32_t stride_pixels;
884 unsigned ndw;
885 int num_loops;
886 int r = 0;
887
888 /* radeon limited to 16k stride */
889 stride_bytes &= 0x3fff;
890 /* radeon pitch is /64 */
891 pitch = stride_bytes / 64;
892 stride_pixels = stride_bytes / 4;
003cefe0 893 num_loops = DIV_ROUND_UP(num_gpu_pages, 8191);
771fe6b9
JG		 894
895 /* Ask for enough room for blit + flush + fence */
896 ndw = 64 + (10 * num_loops);
e32eb50d 897 r = radeon_ring_lock(rdev, ring, ndw);
771fe6b9
JG		 898 if (r) {
899 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
57d20a43 900 return ERR_PTR(-EINVAL);
771fe6b9 901 }
003cefe0
AD		 902 while (num_gpu_pages > 0) {
903 cur_pages = num_gpu_pages;
771fe6b9
JG		 904 if (cur_pages > 8191) {
905 cur_pages = 8191;
906 }
003cefe0 907 num_gpu_pages -= cur_pages;
771fe6b9
JG		 908
909 /* pages are in Y direction - height
910 page width in X direction - width */
e32eb50d
CK		 911 radeon_ring_write(ring, PACKET3(PACKET3_BITBLT_MULTI, 8));
912 radeon_ring_write(ring,
771fe6b9
JG		 913 RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
914 RADEON_GMC_DST_PITCH_OFFSET_CNTL |
915 RADEON_GMC_SRC_CLIPPING |
916 RADEON_GMC_DST_CLIPPING |
917 RADEON_GMC_BRUSH_NONE |
918 (RADEON_COLOR_FORMAT_ARGB8888 << 8) |
919 RADEON_GMC_SRC_DATATYPE_COLOR |
920 RADEON_ROP3_S |
921 RADEON_DP_SRC_SOURCE_MEMORY |
922 RADEON_GMC_CLR_CMP_CNTL_DIS |
923 RADEON_GMC_WR_MSK_DIS);
e32eb50d
CK		 924 radeon_ring_write(ring, (pitch << 22) | (src_offset >> 10));
925 radeon_ring_write(ring, (pitch << 22) | (dst_offset >> 10));
926 radeon_ring_write(ring, (0x1fff) | (0x1fff << 16));
927 radeon_ring_write(ring, 0);
928 radeon_ring_write(ring, (0x1fff) | (0x1fff << 16));
929 radeon_ring_write(ring, num_gpu_pages);
930 radeon_ring_write(ring, num_gpu_pages);
931 radeon_ring_write(ring, cur_pages | (stride_pixels << 16));
932 }
933 radeon_ring_write(ring, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
934 radeon_ring_write(ring, RADEON_RB2D_DC_FLUSH_ALL);
935 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
936 radeon_ring_write(ring,
771fe6b9
JG		 937 RADEON_WAIT_2D_IDLECLEAN |
938 RADEON_WAIT_HOST_IDLECLEAN |
939 RADEON_WAIT_DMA_GUI_IDLE);
57d20a43
CK		 940 r = radeon_fence_emit(rdev, &fence, RADEON_RING_TYPE_GFX_INDEX);
941 if (r) {
942 radeon_ring_unlock_undo(rdev, ring);
943 return ERR_PTR(r);
771fe6b9 944 }
1538a9e0 945 radeon_ring_unlock_commit(rdev, ring, false);
57d20a43 946 return fence;
771fe6b9
JG		 947}
948
45600232
JG		 949static int r100_cp_wait_for_idle(struct radeon_device *rdev)
950{
951 unsigned i;
952 u32 tmp;
953
954 for (i = 0; i < rdev->usec_timeout; i++) {
955 tmp = RREG32(R_000E40_RBBM_STATUS);
956 if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) {
957 return 0;
958 }
959 udelay(1);
960 }
961 return -1;
962}
963
f712812e 964void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring)
771fe6b9
JG		 965{
966 int r;
967
e32eb50d 968 r = radeon_ring_lock(rdev, ring, 2);
771fe6b9
JG		 969 if (r) {
970 return;
971 }
e32eb50d
CK		 972 radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0));
973 radeon_ring_write(ring,
771fe6b9
JG		 974 RADEON_ISYNC_ANY2D_IDLE3D |
975 RADEON_ISYNC_ANY3D_IDLE2D |
976 RADEON_ISYNC_WAIT_IDLEGUI |
977 RADEON_ISYNC_CPSCRATCH_IDLEGUI);
1538a9e0 978 radeon_ring_unlock_commit(rdev, ring, false);
771fe6b9
JG		 979}
980
70967ab9
BH		 981
982/* Load the microcode for the CP */
983static int r100_cp_init_microcode(struct radeon_device *rdev)
771fe6b9 984{
70967ab9
BH		 985 const char *fw_name = NULL;
986 int err;
771fe6b9 987
d9fdaafb 988 DRM_DEBUG_KMS("\n");
771fe6b9 989
771fe6b9
JG		 990 if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) ||
991 (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) ||
992 (rdev->family == CHIP_RS200)) {
993 DRM_INFO("Loading R100 Microcode\n");
70967ab9 994 fw_name = FIRMWARE_R100;
771fe6b9
JG		 995 } else if ((rdev->family == CHIP_R200) ||
996 (rdev->family == CHIP_RV250) ||
997 (rdev->family == CHIP_RV280) ||
998 (rdev->family == CHIP_RS300)) {
999 DRM_INFO("Loading R200 Microcode\n");
70967ab9 1000 fw_name = FIRMWARE_R200;
771fe6b9
JG		 1001 } else if ((rdev->family == CHIP_R300) ||
1002 (rdev->family == CHIP_R350) ||
1003 (rdev->family == CHIP_RV350) ||
1004 (rdev->family == CHIP_RV380) ||
1005 (rdev->family == CHIP_RS400) ||
1006 (rdev->family == CHIP_RS480)) {
1007 DRM_INFO("Loading R300 Microcode\n");
70967ab9 1008 fw_name = FIRMWARE_R300;
771fe6b9
JG		 1009 } else if ((rdev->family == CHIP_R420) ||
1010 (rdev->family == CHIP_R423) ||
1011 (rdev->family == CHIP_RV410)) {
1012 DRM_INFO("Loading R400 Microcode\n");
70967ab9 1013 fw_name = FIRMWARE_R420;
771fe6b9
JG		 1014 } else if ((rdev->family == CHIP_RS690) ||
1015 (rdev->family == CHIP_RS740)) {
1016 DRM_INFO("Loading RS690/RS740 Microcode\n");
70967ab9 1017 fw_name = FIRMWARE_RS690;
771fe6b9
JG		 1018 } else if (rdev->family == CHIP_RS600) {
1019 DRM_INFO("Loading RS600 Microcode\n");
70967ab9 1020 fw_name = FIRMWARE_RS600;
771fe6b9
JG		 1021 } else if ((rdev->family == CHIP_RV515) ||
1022 (rdev->family == CHIP_R520) ||
1023 (rdev->family == CHIP_RV530) ||
1024 (rdev->family == CHIP_R580) ||
1025 (rdev->family == CHIP_RV560) ||
1026 (rdev->family == CHIP_RV570)) {
1027 DRM_INFO("Loading R500 Microcode\n");
70967ab9
BH		 1028 fw_name = FIRMWARE_R520;
1029 }
1030
0a168933 1031 err = request_firmware(&rdev->me_fw, fw_name, rdev->dev);
70967ab9
BH		 1032 if (err) {
1033 printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
1034 fw_name);
3ce0a23d 1035 } else if (rdev->me_fw->size % 8) {
70967ab9
BH		 1036 printk(KERN_ERR
1037 "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
3ce0a23d 1038 rdev->me_fw->size, fw_name);
70967ab9 1039 err = -EINVAL;
3ce0a23d
JG		 1040 release_firmware(rdev->me_fw);
1041 rdev->me_fw = NULL;
70967ab9
BH		 1042 }
1043 return err;
1044}
d4550907 1045
ea31bf69
AD		 1046u32 r100_gfx_get_rptr(struct radeon_device *rdev,
1047 struct radeon_ring *ring)
1048{
1049 u32 rptr;
1050
1051 if (rdev->wb.enabled)
1052 rptr = le32_to_cpu(rdev->wb.wb[ring->rptr_offs/4]);
1053 else
1054 rptr = RREG32(RADEON_CP_RB_RPTR);
1055
1056 return rptr;
1057}
1058
1059u32 r100_gfx_get_wptr(struct radeon_device *rdev,
1060 struct radeon_ring *ring)
1061{
1062 u32 wptr;
1063
1064 wptr = RREG32(RADEON_CP_RB_WPTR);
1065
1066 return wptr;
1067}
1068
1069void r100_gfx_set_wptr(struct radeon_device *rdev,
1070 struct radeon_ring *ring)
1071{
1072 WREG32(RADEON_CP_RB_WPTR, ring->wptr);
1073 (void)RREG32(RADEON_CP_RB_WPTR);
1074}
1075
70967ab9
BH		 1076static void r100_cp_load_microcode(struct radeon_device *rdev)
1077{
1078 const __be32 *fw_data;
1079 int i, size;
1080
1081 if (r100_gui_wait_for_idle(rdev)) {
1082 printk(KERN_WARNING "Failed to wait GUI idle while "
1083 "programming pipes. Bad things might happen.\n");
1084 }
1085
3ce0a23d
JG		 1086 if (rdev->me_fw) {
1087 size = rdev->me_fw->size / 4;
1088 fw_data = (const __be32 *)&rdev->me_fw->data[0];
70967ab9
BH		 1089 WREG32(RADEON_CP_ME_RAM_ADDR, 0);
1090 for (i = 0; i < size; i += 2) {
1091 WREG32(RADEON_CP_ME_RAM_DATAH,
1092 be32_to_cpup(&fw_data[i]));
1093 WREG32(RADEON_CP_ME_RAM_DATAL,
1094 be32_to_cpup(&fw_data[i + 1]));
771fe6b9
JG		 1095 }
1096 }
1097}
1098
1099int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
1100{
e32eb50d 1101 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
771fe6b9
JG		 1102 unsigned rb_bufsz;
1103 unsigned rb_blksz;
1104 unsigned max_fetch;
1105 unsigned pre_write_timer;
1106 unsigned pre_write_limit;
1107 unsigned indirect2_start;
1108 unsigned indirect1_start;
1109 uint32_t tmp;
1110 int r;
1111
1112 if (r100_debugfs_cp_init(rdev)) {
1113 DRM_ERROR("Failed to register debugfs file for CP !\n");
1114 }
3ce0a23d 1115 if (!rdev->me_fw) {
70967ab9
BH		 1116 r = r100_cp_init_microcode(rdev);
1117 if (r) {
1118 DRM_ERROR("Failed to load firmware!\n");
1119 return r;
1120 }
1121 }
1122
771fe6b9 1123 /* Align ring size */
b72a8925 1124 rb_bufsz = order_base_2(ring_size / 8);
771fe6b9
JG		 1125 ring_size = (1 << (rb_bufsz + 1)) * 4;
1126 r100_cp_load_microcode(rdev);
e32eb50d 1127 r = radeon_ring_init(rdev, ring, ring_size, RADEON_WB_CP_RPTR_OFFSET,
2e1e6dad 1128 RADEON_CP_PACKET2);
771fe6b9
JG		 1129 if (r) {
1130 return r;
1131 }
1132 /* Each time the cp read 1024 bytes (16 dword/quadword) update
1133 * the rptr copy in system ram */
1134 rb_blksz = 9;
1135 /* cp will read 128bytes at a time (4 dwords) */
1136 max_fetch = 1;
e32eb50d 1137 ring->align_mask = 16 - 1;
771fe6b9
JG		 1138 /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
1139 pre_write_timer = 64;
1140 /* Force CP_RB_WPTR write if written more than one time before the
1141 * delay expire
1142 */
1143 pre_write_limit = 0;
1144 /* Setup the cp cache like this (cache size is 96 dwords) :
1145 * RING 0 to 15
1146 * INDIRECT1 16 to 79
1147 * INDIRECT2 80 to 95
1148 * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
1149 * indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
1150 * indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
1151 * Idea being that most of the gpu cmd will be through indirect1 buffer
1152 * so it gets the bigger cache.
1153 */
1154 indirect2_start = 80;
1155 indirect1_start = 16;
1156 /* cp setup */
1157 WREG32(0x718, pre_write_timer | (pre_write_limit << 28));
d6f28938 1158 tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
771fe6b9 1159 REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
724c80e1 1160 REG_SET(RADEON_MAX_FETCH, max_fetch));
d6f28938
AD		 1161#ifdef __BIG_ENDIAN
1162 tmp |= RADEON_BUF_SWAP_32BIT;
1163#endif
724c80e1 1164 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_NO_UPDATE);
d6f28938 1165
771fe6b9 1166 /* Set ring address */
e32eb50d
CK		 1167 DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)ring->gpu_addr);
1168 WREG32(RADEON_CP_RB_BASE, ring->gpu_addr);
771fe6b9 1169 /* Force read & write ptr to 0 */
724c80e1 1170 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA | RADEON_RB_NO_UPDATE);
771fe6b9 1171 WREG32(RADEON_CP_RB_RPTR_WR, 0);
e32eb50d
CK		 1172 ring->wptr = 0;
1173 WREG32(RADEON_CP_RB_WPTR, ring->wptr);
724c80e1
AD		 1174
1175 /* set the wb address whether it's enabled or not */
1176 WREG32(R_00070C_CP_RB_RPTR_ADDR,
1177 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) >> 2));
1178 WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET);
1179
1180 if (rdev->wb.enabled)
1181 WREG32(R_000770_SCRATCH_UMSK, 0xff);
1182 else {
1183 tmp |= RADEON_RB_NO_UPDATE;
1184 WREG32(R_000770_SCRATCH_UMSK, 0);
1185 }
1186
771fe6b9
JG		 1187 WREG32(RADEON_CP_RB_CNTL, tmp);
1188 udelay(10);
771fe6b9
JG		 1189 /* Set cp mode to bus mastering & enable cp*/
1190 WREG32(RADEON_CP_CSQ_MODE,
1191 REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
1192 REG_SET(RADEON_INDIRECT1_START, indirect1_start));
d75ee3be
AD		 1193 WREG32(RADEON_CP_RB_WPTR_DELAY, 0);
1194 WREG32(RADEON_CP_CSQ_MODE, 0x00004D4D);
771fe6b9 1195 WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
2099810f
DA		 1196
1197 /* at this point everything should be setup correctly to enable master */
1198 pci_set_master(rdev->pdev);
1199
f712812e
AD		 1200 radeon_ring_start(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
1201 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
771fe6b9
JG		 1202 if (r) {
1203 DRM_ERROR("radeon: cp isn't working (%d).\n", r);
1204 return r;
1205 }
e32eb50d 1206 ring->ready = true;
53595338 1207 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
c7eff978 1208
16c58081
SK		 1209 if (!ring->rptr_save_reg /* not resuming from suspend */
1210 && radeon_ring_supports_scratch_reg(rdev, ring)) {
c7eff978
AD		 1211 r = radeon_scratch_get(rdev, &ring->rptr_save_reg);
1212 if (r) {
1213 DRM_ERROR("failed to get scratch reg for rptr save (%d).\n", r);
1214 ring->rptr_save_reg = 0;
1215 }
1216 }
771fe6b9
JG		 1217 return 0;
1218}
1219
1220void r100_cp_fini(struct radeon_device *rdev)
1221{
45600232
JG		 1222 if (r100_cp_wait_for_idle(rdev)) {
1223 DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
1224 }
771fe6b9 1225 /* Disable ring */
a18d7ea1 1226 r100_cp_disable(rdev);
c7eff978 1227 radeon_scratch_free(rdev, rdev->ring[RADEON_RING_TYPE_GFX_INDEX].rptr_save_reg);
e32eb50d 1228 radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
771fe6b9
JG		 1229 DRM_INFO("radeon: cp finalized\n");
1230}
1231
1232void r100_cp_disable(struct radeon_device *rdev)
1233{
1234 /* Disable ring */
53595338 1235 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
e32eb50d 1236 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
771fe6b9
JG		 1237 WREG32(RADEON_CP_CSQ_MODE, 0);
1238 WREG32(RADEON_CP_CSQ_CNTL, 0);
724c80e1 1239 WREG32(R_000770_SCRATCH_UMSK, 0);
771fe6b9
JG		 1240 if (r100_gui_wait_for_idle(rdev)) {
1241 printk(KERN_WARNING "Failed to wait GUI idle while "
1242 "programming pipes. Bad things might happen.\n");
1243 }
1244}
1245
771fe6b9
JG		 1246/*
1247 * CS functions
1248 */
0242f74d
AD		 1249int r100_reloc_pitch_offset(struct radeon_cs_parser *p,
1250 struct radeon_cs_packet *pkt,
1251 unsigned idx,
1252 unsigned reg)
1253{
1254 int r;
1255 u32 tile_flags = 0;
1256 u32 tmp;
1257 struct radeon_cs_reloc *reloc;
1258 u32 value;
1259
012e976d 1260 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
0242f74d
AD		 1261 if (r) {
1262 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1263 idx, reg);
c3ad63af 1264 radeon_cs_dump_packet(p, pkt);
0242f74d
AD		 1265 return r;
1266 }
1267
1268 value = radeon_get_ib_value(p, idx);
1269 tmp = value & 0x003fffff;
df0af440 1270 tmp += (((u32)reloc->gpu_offset) >> 10);
0242f74d
AD		 1271
1272 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
df0af440 1273 if (reloc->tiling_flags & RADEON_TILING_MACRO)
0242f74d 1274 tile_flags |= RADEON_DST_TILE_MACRO;
df0af440 1275 if (reloc->tiling_flags & RADEON_TILING_MICRO) {
0242f74d
AD		 1276 if (reg == RADEON_SRC_PITCH_OFFSET) {
1277 DRM_ERROR("Cannot src blit from microtiled surface\n");
c3ad63af 1278 radeon_cs_dump_packet(p, pkt);
0242f74d
AD		 1279 return -EINVAL;
1280 }
1281 tile_flags |= RADEON_DST_TILE_MICRO;
1282 }
1283
1284 tmp |= tile_flags;
1285 p->ib.ptr[idx] = (value & 0x3fc00000) | tmp;
1286 } else
1287 p->ib.ptr[idx] = (value & 0xffc00000) | tmp;
1288 return 0;
1289}
1290
1291int r100_packet3_load_vbpntr(struct radeon_cs_parser *p,
1292 struct radeon_cs_packet *pkt,
1293 int idx)
1294{
1295 unsigned c, i;
1296 struct radeon_cs_reloc *reloc;
1297 struct r100_cs_track *track;
1298 int r = 0;
1299 volatile uint32_t *ib;
1300 u32 idx_value;
1301
1302 ib = p->ib.ptr;
1303 track = (struct r100_cs_track *)p->track;
1304 c = radeon_get_ib_value(p, idx++) & 0x1F;
1305 if (c > 16) {
1306 DRM_ERROR("Only 16 vertex buffers are allowed %d\n",
1307 pkt->opcode);
c3ad63af 1308 radeon_cs_dump_packet(p, pkt);
0242f74d
AD		 1309 return -EINVAL;
1310 }
1311 track->num_arrays = c;
1312 for (i = 0; i < (c - 1); i+=2, idx+=3) {
012e976d 1313 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
0242f74d
AD		 1314 if (r) {
1315 DRM_ERROR("No reloc for packet3 %d\n",
1316 pkt->opcode);
c3ad63af 1317 radeon_cs_dump_packet(p, pkt);
0242f74d
AD		 1318 return r;
1319 }
1320 idx_value = radeon_get_ib_value(p, idx);
df0af440 1321 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset);
0242f74d
AD		 1322
1323 track->arrays[i + 0].esize = idx_value >> 8;
1324 track->arrays[i + 0].robj = reloc->robj;
1325 track->arrays[i + 0].esize &= 0x7F;
012e976d 1326 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
0242f74d
AD		 1327 if (r) {
1328 DRM_ERROR("No reloc for packet3 %d\n",
1329 pkt->opcode);
c3ad63af 1330 radeon_cs_dump_packet(p, pkt);
0242f74d
AD		 1331 return r;
1332 }
df0af440 1333 ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->gpu_offset);
0242f74d
AD		 1334 track->arrays[i + 1].robj = reloc->robj;
1335 track->arrays[i + 1].esize = idx_value >> 24;
1336 track->arrays[i + 1].esize &= 0x7F;
1337 }
1338 if (c & 1) {
012e976d 1339 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
0242f74d
AD		 1340 if (r) {
1341 DRM_ERROR("No reloc for packet3 %d\n",
1342 pkt->opcode);
c3ad63af 1343 radeon_cs_dump_packet(p, pkt);
0242f74d
AD		 1344 return r;
1345 }
1346 idx_value = radeon_get_ib_value(p, idx);
df0af440 1347 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset);
0242f74d
AD		 1348 track->arrays[i + 0].robj = reloc->robj;
1349 track->arrays[i + 0].esize = idx_value >> 8;
1350 track->arrays[i + 0].esize &= 0x7F;
1351 }
1352 return r;
1353}
1354
771fe6b9
JG		 1355int r100_cs_parse_packet0(struct radeon_cs_parser *p,
1356 struct radeon_cs_packet *pkt,
068a117c 1357 const unsigned *auth, unsigned n,
771fe6b9
JG		 1358 radeon_packet0_check_t check)
1359{
1360 unsigned reg;
1361 unsigned i, j, m;
1362 unsigned idx;
1363 int r;
1364
1365 idx = pkt->idx + 1;
1366 reg = pkt->reg;
068a117c
JG		 1367 /* Check that register fall into register range
1368 * determined by the number of entry (n) in the
1369 * safe register bitmap.
1370 */
771fe6b9
JG		 1371 if (pkt->one_reg_wr) {
1372 if ((reg >> 7) > n) {
1373 return -EINVAL;
1374 }
1375 } else {
1376 if (((reg + (pkt->count << 2)) >> 7) > n) {
1377 return -EINVAL;
1378 }
1379 }
1380 for (i = 0; i <= pkt->count; i++, idx++) {
1381 j = (reg >> 7);
1382 m = 1 << ((reg >> 2) & 31);
1383 if (auth[j] & m) {
1384 r = check(p, pkt, idx, reg);
1385 if (r) {
1386 return r;
1387 }
1388 }
1389 if (pkt->one_reg_wr) {
1390 if (!(auth[j] & m)) {
1391 break;
1392 }
1393 } else {
1394 reg += 4;
1395 }
1396 }
1397 return 0;
1398}
1399
531369e6
DA		 1400/**
1401 * r100_cs_packet_next_vline() - parse userspace VLINE packet
1402 * @parser: parser structure holding parsing context.
1403 *
1404 * Userspace sends a special sequence for VLINE waits.
1405 * PACKET0 - VLINE_START_END + value
1406 * PACKET0 - WAIT_UNTIL +_value
1407 * RELOC (P3) - crtc_id in reloc.
1408 *
1409 * This function parses this and relocates the VLINE START END
1410 * and WAIT UNTIL packets to the correct crtc.
1411 * It also detects a switched off crtc and nulls out the
1412 * wait in that case.
1413 */
1414int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
1415{
531369e6
DA		 1416 struct drm_crtc *crtc;
1417 struct radeon_crtc *radeon_crtc;
1418 struct radeon_cs_packet p3reloc, waitreloc;
1419 int crtc_id;
1420 int r;
1421 uint32_t header, h_idx, reg;
513bcb46 1422 volatile uint32_t *ib;
531369e6 1423
f2e39221 1424 ib = p->ib.ptr;
531369e6
DA		 1425
1426 /* parse the wait until */
c38f34b5 1427 r = radeon_cs_packet_parse(p, &waitreloc, p->idx);
531369e6
DA		 1428 if (r)
1429 return r;
1430
1431 /* check its a wait until and only 1 count */
1432 if (waitreloc.reg != RADEON_WAIT_UNTIL ||
1433 waitreloc.count != 0) {
1434 DRM_ERROR("vline wait had illegal wait until segment\n");
a3a88a66 1435 return -EINVAL;
531369e6
DA		 1436 }
1437
513bcb46 1438 if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) {
531369e6 1439 DRM_ERROR("vline wait had illegal wait until\n");
a3a88a66 1440 return -EINVAL;
531369e6
DA		 1441 }
1442
1443 /* jump over the NOP */
c38f34b5 1444 r = radeon_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2);
531369e6
DA		 1445 if (r)
1446 return r;
1447
1448 h_idx = p->idx - 2;
90ebd065
AD		 1449 p->idx += waitreloc.count + 2;
1450 p->idx += p3reloc.count + 2;
531369e6 1451
513bcb46
DA		 1452 header = radeon_get_ib_value(p, h_idx);
1453 crtc_id = radeon_get_ib_value(p, h_idx + 5);
4e872ae2 1454 reg = R100_CP_PACKET0_GET_REG(header);
b957f457
RC		 1455 crtc = drm_crtc_find(p->rdev->ddev, crtc_id);
1456 if (!crtc) {
531369e6 1457 DRM_ERROR("cannot find crtc %d\n", crtc_id);
10e10d34 1458 return -ENOENT;
531369e6 1459 }
531369e6
DA		 1460 radeon_crtc = to_radeon_crtc(crtc);
1461 crtc_id = radeon_crtc->crtc_id;
1462
1463 if (!crtc->enabled) {
1464 /* if the CRTC isn't enabled - we need to nop out the wait until */
513bcb46
DA		 1465 ib[h_idx + 2] = PACKET2(0);
1466 ib[h_idx + 3] = PACKET2(0);
531369e6
DA		 1467 } else if (crtc_id == 1) {
1468 switch (reg) {
1469 case AVIVO_D1MODE_VLINE_START_END:
90ebd065 1470 header &= ~R300_CP_PACKET0_REG_MASK;
531369e6
DA		 1471 header |= AVIVO_D2MODE_VLINE_START_END >> 2;
1472 break;
1473 case RADEON_CRTC_GUI_TRIG_VLINE:
90ebd065 1474 header &= ~R300_CP_PACKET0_REG_MASK;
531369e6
DA		 1475 header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2;
1476 break;
1477 default:
1478 DRM_ERROR("unknown crtc reloc\n");
a3a88a66 1479 return -EINVAL;
531369e6 1480 }
513bcb46
DA		 1481 ib[h_idx] = header;
1482 ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1;
531369e6 1483 }
a3a88a66
PB		 1484
1485 return 0;
531369e6
DA		 1486}
1487
551ebd83
DA		 1488static int r100_get_vtx_size(uint32_t vtx_fmt)
1489{
1490 int vtx_size;
1491 vtx_size = 2;
1492 /* ordered according to bits in spec */
1493 if (vtx_fmt & RADEON_SE_VTX_FMT_W0)
1494 vtx_size++;
1495 if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR)
1496 vtx_size += 3;
1497 if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA)
1498 vtx_size++;
1499 if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR)
1500 vtx_size++;
1501 if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC)
1502 vtx_size += 3;
1503 if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG)
1504 vtx_size++;
1505 if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC)
1506 vtx_size++;
1507 if (vtx_fmt & RADEON_SE_VTX_FMT_ST0)
1508 vtx_size += 2;
1509 if (vtx_fmt & RADEON_SE_VTX_FMT_ST1)
1510 vtx_size += 2;
1511 if (vtx_fmt & RADEON_SE_VTX_FMT_Q1)
1512 vtx_size++;
1513 if (vtx_fmt & RADEON_SE_VTX_FMT_ST2)
1514 vtx_size += 2;
1515 if (vtx_fmt & RADEON_SE_VTX_FMT_Q2)
1516 vtx_size++;
1517 if (vtx_fmt & RADEON_SE_VTX_FMT_ST3)
1518 vtx_size += 2;
1519 if (vtx_fmt & RADEON_SE_VTX_FMT_Q3)
1520 vtx_size++;
1521 if (vtx_fmt & RADEON_SE_VTX_FMT_Q0)
1522 vtx_size++;
1523 /* blend weight */
1524 if (vtx_fmt & (0x7 << 15))
1525 vtx_size += (vtx_fmt >> 15) & 0x7;
1526 if (vtx_fmt & RADEON_SE_VTX_FMT_N0)
1527 vtx_size += 3;
1528 if (vtx_fmt & RADEON_SE_VTX_FMT_XY1)
1529 vtx_size += 2;
1530 if (vtx_fmt & RADEON_SE_VTX_FMT_Z1)
1531 vtx_size++;
1532 if (vtx_fmt & RADEON_SE_VTX_FMT_W1)
1533 vtx_size++;
1534 if (vtx_fmt & RADEON_SE_VTX_FMT_N1)
1535 vtx_size++;
1536 if (vtx_fmt & RADEON_SE_VTX_FMT_Z)
1537 vtx_size++;
1538 return vtx_size;
1539}
1540
771fe6b9 1541static int r100_packet0_check(struct radeon_cs_parser *p,
551ebd83
DA		 1542 struct radeon_cs_packet *pkt,
1543 unsigned idx, unsigned reg)
771fe6b9 1544{
771fe6b9 1545 struct radeon_cs_reloc *reloc;
551ebd83 1546 struct r100_cs_track *track;
771fe6b9
JG		 1547 volatile uint32_t *ib;
1548 uint32_t tmp;
771fe6b9 1549 int r;
551ebd83 1550 int i, face;
e024e110 1551 u32 tile_flags = 0;
513bcb46 1552 u32 idx_value;
771fe6b9 1553
f2e39221 1554 ib = p->ib.ptr;
551ebd83
DA		 1555 track = (struct r100_cs_track *)p->track;
1556
513bcb46
DA		 1557 idx_value = radeon_get_ib_value(p, idx);
1558
551ebd83
DA		 1559 switch (reg) {
1560 case RADEON_CRTC_GUI_TRIG_VLINE:
1561 r = r100_cs_packet_parse_vline(p);
1562 if (r) {
1563 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1564 idx, reg);
c3ad63af 1565 radeon_cs_dump_packet(p, pkt);
551ebd83
DA		 1566 return r;
1567 }
1568 break;
771fe6b9
JG		 1569 /* FIXME: only allow PACKET3 blit? easier to check for out of
1570 * range access */
551ebd83
DA		 1571 case RADEON_DST_PITCH_OFFSET:
1572 case RADEON_SRC_PITCH_OFFSET:
1573 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
1574 if (r)
1575 return r;
1576 break;
1577 case RADEON_RB3D_DEPTHOFFSET:
012e976d 1578 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
551ebd83
DA		 1579 if (r) {
1580 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1581 idx, reg);
c3ad63af 1582 radeon_cs_dump_packet(p, pkt);
551ebd83
DA		 1583 return r;
1584 }
1585 track->zb.robj = reloc->robj;
513bcb46 1586 track->zb.offset = idx_value;
40b4a759 1587 track->zb_dirty = true;
df0af440 1588 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
551ebd83
DA		 1589 break;
1590 case RADEON_RB3D_COLOROFFSET:
012e976d 1591 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
551ebd83
DA		 1592 if (r) {
1593 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1594 idx, reg);
c3ad63af 1595 radeon_cs_dump_packet(p, pkt);
551ebd83
DA		 1596 return r;
1597 }
1598 track->cb[0].robj = reloc->robj;
513bcb46 1599 track->cb[0].offset = idx_value;
40b4a759 1600 track->cb_dirty = true;
df0af440 1601 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
551ebd83
DA		 1602 break;
1603 case RADEON_PP_TXOFFSET_0:
1604 case RADEON_PP_TXOFFSET_1:
1605 case RADEON_PP_TXOFFSET_2:
1606 i = (reg - RADEON_PP_TXOFFSET_0) / 24;
012e976d 1607 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
551ebd83
DA		 1608 if (r) {
1609 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1610 idx, reg);
c3ad63af 1611 radeon_cs_dump_packet(p, pkt);
551ebd83
DA		 1612 return r;
1613 }
f2746f83 1614 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
df0af440 1615 if (reloc->tiling_flags & RADEON_TILING_MACRO)
f2746f83 1616 tile_flags |= RADEON_TXO_MACRO_TILE;
df0af440 1617 if (reloc->tiling_flags & RADEON_TILING_MICRO)
f2746f83
AD		 1618 tile_flags |= RADEON_TXO_MICRO_TILE_X2;
1619
1620 tmp = idx_value & ~(0x7 << 2);
1621 tmp |= tile_flags;
df0af440 1622 ib[idx] = tmp + ((u32)reloc->gpu_offset);
f2746f83 1623 } else
df0af440 1624 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
551ebd83 1625 track->textures[i].robj = reloc->robj;
40b4a759 1626 track->tex_dirty = true;
551ebd83
DA		 1627 break;
1628 case RADEON_PP_CUBIC_OFFSET_T0_0:
1629 case RADEON_PP_CUBIC_OFFSET_T0_1:
1630 case RADEON_PP_CUBIC_OFFSET_T0_2:
1631 case RADEON_PP_CUBIC_OFFSET_T0_3:
1632 case RADEON_PP_CUBIC_OFFSET_T0_4:
1633 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
012e976d 1634 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
551ebd83
DA		 1635 if (r) {
1636 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1637 idx, reg);
c3ad63af 1638 radeon_cs_dump_packet(p, pkt);
551ebd83
DA		 1639 return r;
1640 }
513bcb46 1641 track->textures[0].cube_info[i].offset = idx_value;
df0af440 1642 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
551ebd83 1643 track->textures[0].cube_info[i].robj = reloc->robj;
40b4a759 1644 track->tex_dirty = true;
551ebd83
DA		 1645 break;
1646 case RADEON_PP_CUBIC_OFFSET_T1_0:
1647 case RADEON_PP_CUBIC_OFFSET_T1_1:
1648 case RADEON_PP_CUBIC_OFFSET_T1_2:
1649 case RADEON_PP_CUBIC_OFFSET_T1_3:
1650 case RADEON_PP_CUBIC_OFFSET_T1_4:
1651 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
012e976d 1652 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
551ebd83
DA		 1653 if (r) {
1654 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1655 idx, reg);
c3ad63af 1656 radeon_cs_dump_packet(p, pkt);
551ebd83
DA		 1657 return r;
1658 }
513bcb46 1659 track->textures[1].cube_info[i].offset = idx_value;
df0af440 1660 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
551ebd83 1661 track->textures[1].cube_info[i].robj = reloc->robj;
40b4a759 1662 track->tex_dirty = true;
551ebd83
DA		 1663 break;
1664 case RADEON_PP_CUBIC_OFFSET_T2_0:
1665 case RADEON_PP_CUBIC_OFFSET_T2_1:
1666 case RADEON_PP_CUBIC_OFFSET_T2_2:
1667 case RADEON_PP_CUBIC_OFFSET_T2_3:
1668 case RADEON_PP_CUBIC_OFFSET_T2_4:
1669 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
012e976d 1670 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
551ebd83
DA		 1671 if (r) {
1672 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1673 idx, reg);
c3ad63af 1674 radeon_cs_dump_packet(p, pkt);
551ebd83
DA		 1675 return r;
1676 }
513bcb46 1677 track->textures[2].cube_info[i].offset = idx_value;
df0af440 1678 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
551ebd83 1679 track->textures[2].cube_info[i].robj = reloc->robj;
40b4a759 1680 track->tex_dirty = true;
551ebd83
DA		 1681 break;
1682 case RADEON_RE_WIDTH_HEIGHT:
513bcb46 1683 track->maxy = ((idx_value >> 16) & 0x7FF);
40b4a759
MO		 1684 track->cb_dirty = true;
1685 track->zb_dirty = true;
551ebd83
DA		 1686 break;
1687 case RADEON_RB3D_COLORPITCH:
012e976d 1688 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
551ebd83
DA		 1689 if (r) {
1690 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1691 idx, reg);
c3ad63af 1692 radeon_cs_dump_packet(p, pkt);
551ebd83
DA		 1693 return r;
1694 }
c9068eb2 1695 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
df0af440 1696 if (reloc->tiling_flags & RADEON_TILING_MACRO)
c9068eb2 1697 tile_flags |= RADEON_COLOR_TILE_ENABLE;
df0af440 1698 if (reloc->tiling_flags & RADEON_TILING_MICRO)
c9068eb2
AD		 1699 tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
1700
1701 tmp = idx_value & ~(0x7 << 16);
1702 tmp |= tile_flags;
1703 ib[idx] = tmp;
1704 } else
1705 ib[idx] = idx_value;
e024e110 1706
513bcb46 1707 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
40b4a759 1708 track->cb_dirty = true;
551ebd83
DA		 1709 break;
1710 case RADEON_RB3D_DEPTHPITCH:
513bcb46 1711 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
40b4a759 1712 track->zb_dirty = true;
551ebd83
DA		 1713 break;
1714 case RADEON_RB3D_CNTL:
513bcb46 1715 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
551ebd83
DA		 1716 case 7:
1717 case 8:
1718 case 9:
1719 case 11:
1720 case 12:
1721 track->cb[0].cpp = 1;
e024e110 1722 break;
551ebd83
DA		 1723 case 3:
1724 case 4:
1725 case 15:
1726 track->cb[0].cpp = 2;
1727 break;
1728 case 6:
1729 track->cb[0].cpp = 4;
1730 break;
1731 default:
1732 DRM_ERROR("Invalid color buffer format (%d) !\n",
513bcb46 1733 ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
551ebd83
DA		 1734 return -EINVAL;
1735 }
513bcb46 1736 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
40b4a759
MO		 1737 track->cb_dirty = true;
1738 track->zb_dirty = true;
551ebd83
DA		 1739 break;
1740 case RADEON_RB3D_ZSTENCILCNTL:
513bcb46 1741 switch (idx_value & 0xf) {
551ebd83
DA		 1742 case 0:
1743 track->zb.cpp = 2;
1744 break;
1745 case 2:
1746 case 3:
1747 case 4:
1748 case 5:
1749 case 9:
1750 case 11:
1751 track->zb.cpp = 4;
17782d99 1752 break;
771fe6b9 1753 default:
771fe6b9
JG		 1754 break;
1755 }
40b4a759 1756 track->zb_dirty = true;
551ebd83
DA		 1757 break;
1758 case RADEON_RB3D_ZPASS_ADDR:
012e976d 1759 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
551ebd83
DA		 1760 if (r) {
1761 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1762 idx, reg);
c3ad63af 1763 radeon_cs_dump_packet(p, pkt);
551ebd83
DA		 1764 return r;
1765 }
df0af440 1766 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
551ebd83
DA		 1767 break;
1768 case RADEON_PP_CNTL:
1769 {
513bcb46 1770 uint32_t temp = idx_value >> 4;
551ebd83
DA		 1771 for (i = 0; i < track->num_texture; i++)
1772 track->textures[i].enabled = !!(temp & (1 << i));
40b4a759 1773 track->tex_dirty = true;
551ebd83
DA		 1774 }
1775 break;
1776 case RADEON_SE_VF_CNTL:
513bcb46 1777 track->vap_vf_cntl = idx_value;
551ebd83
DA		 1778 break;
1779 case RADEON_SE_VTX_FMT:
513bcb46 1780 track->vtx_size = r100_get_vtx_size(idx_value);
551ebd83
DA		 1781 break;
1782 case RADEON_PP_TEX_SIZE_0:
1783 case RADEON_PP_TEX_SIZE_1:
1784 case RADEON_PP_TEX_SIZE_2:
1785 i = (reg - RADEON_PP_TEX_SIZE_0) / 8;
513bcb46
DA		 1786 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
1787 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
40b4a759 1788 track->tex_dirty = true;
551ebd83
DA		 1789 break;
1790 case RADEON_PP_TEX_PITCH_0:
1791 case RADEON_PP_TEX_PITCH_1:
1792 case RADEON_PP_TEX_PITCH_2:
1793 i = (reg - RADEON_PP_TEX_PITCH_0) / 8;
513bcb46 1794 track->textures[i].pitch = idx_value + 32;
40b4a759 1795 track->tex_dirty = true;
551ebd83
DA		 1796 break;
1797 case RADEON_PP_TXFILTER_0:
1798 case RADEON_PP_TXFILTER_1:
1799 case RADEON_PP_TXFILTER_2:
1800 i = (reg - RADEON_PP_TXFILTER_0) / 24;
513bcb46 1801 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK)
551ebd83 1802 >> RADEON_MAX_MIP_LEVEL_SHIFT);
513bcb46 1803 tmp = (idx_value >> 23) & 0x7;
551ebd83
DA		 1804 if (tmp == 2 || tmp == 6)
1805 track->textures[i].roundup_w = false;
513bcb46 1806 tmp = (idx_value >> 27) & 0x7;
551ebd83
DA		 1807 if (tmp == 2 || tmp == 6)
1808 track->textures[i].roundup_h = false;
40b4a759 1809 track->tex_dirty = true;
551ebd83
DA		 1810 break;
1811 case RADEON_PP_TXFORMAT_0:
1812 case RADEON_PP_TXFORMAT_1:
1813 case RADEON_PP_TXFORMAT_2:
1814 i = (reg - RADEON_PP_TXFORMAT_0) / 24;
513bcb46 1815 if (idx_value & RADEON_TXFORMAT_NON_POWER2) {
551ebd83
DA		 1816 track->textures[i].use_pitch = 1;
1817 } else {
1818 track->textures[i].use_pitch = 0;
513bcb46
DA		 1819 track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
1820 track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
551ebd83 1821 }
513bcb46 1822 if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE)
551ebd83 1823 track->textures[i].tex_coord_type = 2;
513bcb46 1824 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
551ebd83
DA		 1825 case RADEON_TXFORMAT_I8:
1826 case RADEON_TXFORMAT_RGB332:
1827 case RADEON_TXFORMAT_Y8:
1828 track->textures[i].cpp = 1;
f9da52d5 1829 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
551ebd83
DA		 1830 break;
1831 case RADEON_TXFORMAT_AI88:
1832 case RADEON_TXFORMAT_ARGB1555:
1833 case RADEON_TXFORMAT_RGB565:
1834 case RADEON_TXFORMAT_ARGB4444:
1835 case RADEON_TXFORMAT_VYUY422:
1836 case RADEON_TXFORMAT_YVYU422:
551ebd83
DA		 1837 case RADEON_TXFORMAT_SHADOW16:
1838 case RADEON_TXFORMAT_LDUDV655:
1839 case RADEON_TXFORMAT_DUDV88:
1840 track->textures[i].cpp = 2;
f9da52d5 1841 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
771fe6b9 1842 break;
551ebd83
DA		 1843 case RADEON_TXFORMAT_ARGB8888:
1844 case RADEON_TXFORMAT_RGBA8888:
551ebd83
DA		 1845 case RADEON_TXFORMAT_SHADOW32:
1846 case RADEON_TXFORMAT_LDUDUV8888:
1847 track->textures[i].cpp = 4;
f9da52d5 1848 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
551ebd83 1849 break;
d785d78b
DA		 1850 case RADEON_TXFORMAT_DXT1:
1851 track->textures[i].cpp = 1;
1852 track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
1853 break;
1854 case RADEON_TXFORMAT_DXT23:
1855 case RADEON_TXFORMAT_DXT45:
1856 track->textures[i].cpp = 1;
1857 track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
1858 break;
551ebd83 1859 }
513bcb46
DA		 1860 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
1861 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
40b4a759 1862 track->tex_dirty = true;
551ebd83
DA		 1863 break;
1864 case RADEON_PP_CUBIC_FACES_0:
1865 case RADEON_PP_CUBIC_FACES_1:
1866 case RADEON_PP_CUBIC_FACES_2:
513bcb46 1867 tmp = idx_value;
551ebd83
DA		 1868 i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;
1869 for (face = 0; face < 4; face++) {
1870 track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
1871 track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
771fe6b9 1872 }
40b4a759 1873 track->tex_dirty = true;
551ebd83
DA		 1874 break;
1875 default:
1876 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1877 reg, idx);
1878 return -EINVAL;
771fe6b9
JG		 1879 }
1880 return 0;
1881}
1882
068a117c
JG		 1883int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1884 struct radeon_cs_packet *pkt,
4c788679 1885 struct radeon_bo *robj)
068a117c 1886{
068a117c 1887 unsigned idx;
513bcb46 1888 u32 value;
068a117c 1889 idx = pkt->idx + 1;
513bcb46 1890 value = radeon_get_ib_value(p, idx + 2);
4c788679 1891 if ((value + 1) > radeon_bo_size(robj)) {
068a117c
JG		 1892 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
1893 "(need %u have %lu) !\n",
513bcb46 1894 value + 1,
4c788679 1895 radeon_bo_size(robj));
068a117c
JG		 1896 return -EINVAL;
1897 }
1898 return 0;
1899}
1900
771fe6b9
JG		 1901static int r100_packet3_check(struct radeon_cs_parser *p,
1902 struct radeon_cs_packet *pkt)
1903{
771fe6b9 1904 struct radeon_cs_reloc *reloc;
551ebd83 1905 struct r100_cs_track *track;
771fe6b9 1906 unsigned idx;
771fe6b9
JG		 1907 volatile uint32_t *ib;
1908 int r;
1909
f2e39221 1910 ib = p->ib.ptr;
771fe6b9 1911 idx = pkt->idx + 1;
551ebd83 1912 track = (struct r100_cs_track *)p->track;
771fe6b9
JG		 1913 switch (pkt->opcode) {
1914 case PACKET3_3D_LOAD_VBPNTR:
513bcb46
DA		 1915 r = r100_packet3_load_vbpntr(p, pkt, idx);
1916 if (r)
1917 return r;
771fe6b9
JG		 1918 break;
1919 case PACKET3_INDX_BUFFER:
012e976d 1920 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
771fe6b9
JG		 1921 if (r) {
1922 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
c3ad63af 1923 radeon_cs_dump_packet(p, pkt);
771fe6b9
JG		 1924 return r;
1925 }
df0af440 1926 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->gpu_offset);
068a117c
JG		 1927 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1928 if (r) {
1929 return r;
1930 }
771fe6b9
JG		 1931 break;
1932 case 0x23:
771fe6b9 1933 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
012e976d 1934 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
771fe6b9
JG		 1935 if (r) {
1936 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
c3ad63af 1937 radeon_cs_dump_packet(p, pkt);
771fe6b9
JG		 1938 return r;
1939 }
df0af440 1940 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->gpu_offset);
551ebd83 1941 track->num_arrays = 1;
513bcb46 1942 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2));
551ebd83
DA		 1943
1944 track->arrays[0].robj = reloc->robj;
1945 track->arrays[0].esize = track->vtx_size;
1946
513bcb46 1947 track->max_indx = radeon_get_ib_value(p, idx+1);
551ebd83 1948
513bcb46 1949 track->vap_vf_cntl = radeon_get_ib_value(p, idx+3);
551ebd83
DA		 1950 track->immd_dwords = pkt->count - 1;
1951 r = r100_cs_track_check(p->rdev, track);
1952 if (r)
1953 return r;
771fe6b9
JG		 1954 break;
1955 case PACKET3_3D_DRAW_IMMD:
513bcb46 1956 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
551ebd83
DA		 1957 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1958 return -EINVAL;
1959 }
cf57fc7a 1960 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0));
513bcb46 1961 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
551ebd83
DA		 1962 track->immd_dwords = pkt->count - 1;
1963 r = r100_cs_track_check(p->rdev, track);
1964 if (r)
1965 return r;
1966 break;
771fe6b9
JG		 1967 /* triggers drawing using in-packet vertex data */
1968 case PACKET3_3D_DRAW_IMMD_2:
513bcb46 1969 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
551ebd83
DA		 1970 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1971 return -EINVAL;
1972 }
513bcb46 1973 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
551ebd83
DA		 1974 track->immd_dwords = pkt->count;
1975 r = r100_cs_track_check(p->rdev, track);
1976 if (r)
1977 return r;
1978 break;
771fe6b9
JG		 1979 /* triggers drawing using in-packet vertex data */
1980 case PACKET3_3D_DRAW_VBUF_2:
513bcb46 1981 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
551ebd83
DA		 1982 r = r100_cs_track_check(p->rdev, track);
1983 if (r)
1984 return r;
1985 break;
771fe6b9
JG		 1986 /* triggers drawing of vertex buffers setup elsewhere */
1987 case PACKET3_3D_DRAW_INDX_2:
513bcb46 1988 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
551ebd83
DA		 1989 r = r100_cs_track_check(p->rdev, track);
1990 if (r)
1991 return r;
1992 break;
771fe6b9
JG		 1993 /* triggers drawing using indices to vertex buffer */
1994 case PACKET3_3D_DRAW_VBUF:
513bcb46 1995 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
551ebd83
DA		 1996 r = r100_cs_track_check(p->rdev, track);
1997 if (r)
1998 return r;
1999 break;
771fe6b9
JG		 2000 /* triggers drawing of vertex buffers setup elsewhere */
2001 case PACKET3_3D_DRAW_INDX:
513bcb46 2002 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
551ebd83
DA		 2003 r = r100_cs_track_check(p->rdev, track);
2004 if (r)
2005 return r;
2006 break;
771fe6b9 2007 /* triggers drawing using indices to vertex buffer */
ab9e1f59
DA		 2008 case PACKET3_3D_CLEAR_HIZ:
2009 case PACKET3_3D_CLEAR_ZMASK:
2010 if (p->rdev->hyperz_filp != p->filp)
2011 return -EINVAL;
2012 break;
771fe6b9
JG		 2013 case PACKET3_NOP:
2014 break;
2015 default:
2016 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
2017 return -EINVAL;
2018 }
2019 return 0;
2020}
2021
2022int r100_cs_parse(struct radeon_cs_parser *p)
2023{
2024 struct radeon_cs_packet pkt;
9f022ddf 2025 struct r100_cs_track *track;
771fe6b9
JG		 2026 int r;
2027
9f022ddf 2028 track = kzalloc(sizeof(*track), GFP_KERNEL);
ce067913
DC		 2029 if (!track)
2030 return -ENOMEM;
9f022ddf
JG		 2031 r100_cs_track_clear(p->rdev, track);
2032 p->track = track;
771fe6b9 2033 do {
c38f34b5 2034 r = radeon_cs_packet_parse(p, &pkt, p->idx);
771fe6b9
JG		 2035 if (r) {
2036 return r;
2037 }
2038 p->idx += pkt.count + 2;
2039 switch (pkt.type) {
4e872ae2 2040 case RADEON_PACKET_TYPE0:
66b3543e
IH		 2041 if (p->rdev->family >= CHIP_R200)
2042 r = r100_cs_parse_packet0(p, &pkt,
2043 p->rdev->config.r100.reg_safe_bm,
2044 p->rdev->config.r100.reg_safe_bm_size,
2045 &r200_packet0_check);
2046 else
2047 r = r100_cs_parse_packet0(p, &pkt,
2048 p->rdev->config.r100.reg_safe_bm,
2049 p->rdev->config.r100.reg_safe_bm_size,
2050 &r100_packet0_check);
2051 break;
4e872ae2 2052 case RADEON_PACKET_TYPE2:
66b3543e 2053 break;
4e872ae2 2054 case RADEON_PACKET_TYPE3:
66b3543e
IH		 2055 r = r100_packet3_check(p, &pkt);
2056 break;
2057 default:
2058 DRM_ERROR("Unknown packet type %d !\n",
2059 pkt.type);
2060 return -EINVAL;
771fe6b9 2061 }
66b3543e 2062 if (r)
771fe6b9 2063 return r;
771fe6b9
JG		 2064 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
2065 return 0;
2066}
2067
0242f74d 2068static void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
771fe6b9 2069{
0242f74d
AD		 2070 DRM_ERROR("pitch %d\n", t->pitch);
2071 DRM_ERROR("use_pitch %d\n", t->use_pitch);
2072 DRM_ERROR("width %d\n", t->width);
2073 DRM_ERROR("width_11 %d\n", t->width_11);
2074 DRM_ERROR("height %d\n", t->height);
2075 DRM_ERROR("height_11 %d\n", t->height_11);
2076 DRM_ERROR("num levels %d\n", t->num_levels);
2077 DRM_ERROR("depth %d\n", t->txdepth);
2078 DRM_ERROR("bpp %d\n", t->cpp);
2079 DRM_ERROR("coordinate type %d\n", t->tex_coord_type);
2080 DRM_ERROR("width round to power of 2 %d\n", t->roundup_w);
2081 DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
2082 DRM_ERROR("compress format %d\n", t->compress_format);
771fe6b9
JG		 2083}
2084
0242f74d 2085static int r100_track_compress_size(int compress_format, int w, int h)
771fe6b9 2086{
0242f74d
AD		 2087 int block_width, block_height, block_bytes;
2088 int wblocks, hblocks;
2089 int min_wblocks;
2090 int sz;
771fe6b9 2091
0242f74d
AD		 2092 block_width = 4;
2093 block_height = 4;
2094
2095 switch (compress_format) {
2096 case R100_TRACK_COMP_DXT1:
2097 block_bytes = 8;
2098 min_wblocks = 4;
2099 break;
2100 default:
2101 case R100_TRACK_COMP_DXT35:
2102 block_bytes = 16;
2103 min_wblocks = 2;
2104 break;
771fe6b9 2105 }
0242f74d
AD		 2106
2107 hblocks = (h + block_height - 1) / block_height;
2108 wblocks = (w + block_width - 1) / block_width;
2109 if (wblocks < min_wblocks)
2110 wblocks = min_wblocks;
2111 sz = wblocks * hblocks * block_bytes;
2112 return sz;
771fe6b9
JG		 2113}
2114
0242f74d
AD		 2115static int r100_cs_track_cube(struct radeon_device *rdev,
2116 struct r100_cs_track *track, unsigned idx)
771fe6b9 2117{
0242f74d
AD		 2118 unsigned face, w, h;
2119 struct radeon_bo *cube_robj;
2120 unsigned long size;
2121 unsigned compress_format = track->textures[idx].compress_format;
771fe6b9 2122
0242f74d
AD		 2123 for (face = 0; face < 5; face++) {
2124 cube_robj = track->textures[idx].cube_info[face].robj;
2125 w = track->textures[idx].cube_info[face].width;
2126 h = track->textures[idx].cube_info[face].height;
771fe6b9 2127
0242f74d
AD		 2128 if (compress_format) {
2129 size = r100_track_compress_size(compress_format, w, h);
2130 } else
2131 size = w * h;
2132 size *= track->textures[idx].cpp;
2133
2134 size += track->textures[idx].cube_info[face].offset;
2135
2136 if (size > radeon_bo_size(cube_robj)) {
2137 DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
2138 size, radeon_bo_size(cube_robj));
2139 r100_cs_track_texture_print(&track->textures[idx]);
2140 return -1;
771fe6b9 2141 }
771fe6b9 2142 }
0242f74d 2143 return 0;
771fe6b9
JG		 2144}
2145
0242f74d
AD		 2146static int r100_cs_track_texture_check(struct radeon_device *rdev,
2147 struct r100_cs_track *track)
771fe6b9 2148{
0242f74d
AD		 2149 struct radeon_bo *robj;
2150 unsigned long size;
2151 unsigned u, i, w, h, d;
2152 int ret;
771fe6b9 2153
0242f74d
AD		 2154 for (u = 0; u < track->num_texture; u++) {
2155 if (!track->textures[u].enabled)
2156 continue;
2157 if (track->textures[u].lookup_disable)
2158 continue;
2159 robj = track->textures[u].robj;
2160 if (robj == NULL) {
2161 DRM_ERROR("No texture bound to unit %u\n", u);
2162 return -EINVAL;
771fe6b9 2163 }
0242f74d
AD		 2164 size = 0;
2165 for (i = 0; i <= track->textures[u].num_levels; i++) {
2166 if (track->textures[u].use_pitch) {
2167 if (rdev->family < CHIP_R300)
2168 w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i);
2169 else
2170 w = track->textures[u].pitch / (1 << i);
2171 } else {
2172 w = track->textures[u].width;
2173 if (rdev->family >= CHIP_RV515)
2174 w |= track->textures[u].width_11;
2175 w = w / (1 << i);
2176 if (track->textures[u].roundup_w)
2177 w = roundup_pow_of_two(w);
2178 }
2179 h = track->textures[u].height;
2180 if (rdev->family >= CHIP_RV515)
2181 h |= track->textures[u].height_11;
2182 h = h / (1 << i);
2183 if (track->textures[u].roundup_h)
2184 h = roundup_pow_of_two(h);
2185 if (track->textures[u].tex_coord_type == 1) {
2186 d = (1 << track->textures[u].txdepth) / (1 << i);
2187 if (!d)
2188 d = 1;
2189 } else {
2190 d = 1;
2191 }
2192 if (track->textures[u].compress_format) {
771fe6b9 2193
0242f74d
AD		 2194 size += r100_track_compress_size(track->textures[u].compress_format, w, h) * d;
2195 /* compressed textures are block based */
2196 } else
2197 size += w * h * d;
2198 }
2199 size *= track->textures[u].cpp;
771fe6b9 2200
0242f74d
AD		 2201 switch (track->textures[u].tex_coord_type) {
2202 case 0:
2203 case 1:
2204 break;
2205 case 2:
2206 if (track->separate_cube) {
2207 ret = r100_cs_track_cube(rdev, track, u);
2208 if (ret)
2209 return ret;
2210 } else
2211 size *= 6;
2212 break;
2213 default:
2214 DRM_ERROR("Invalid texture coordinate type %u for unit "
2215 "%u\n", track->textures[u].tex_coord_type, u);
2216 return -EINVAL;
2217 }
2218 if (size > radeon_bo_size(robj)) {
2219 DRM_ERROR("Texture of unit %u needs %lu bytes but is "
2220 "%lu\n", u, size, radeon_bo_size(robj));
2221 r100_cs_track_texture_print(&track->textures[u]);
2222 return -EINVAL;
771fe6b9 2223 }
771fe6b9 2224 }
0242f74d 2225 return 0;
771fe6b9
JG		 2226}
2227
0242f74d 2228int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
771fe6b9
JG		 2229{
2230 unsigned i;
0242f74d
AD		 2231 unsigned long size;
2232 unsigned prim_walk;
2233 unsigned nverts;
2234 unsigned num_cb = track->cb_dirty ? track->num_cb : 0;
771fe6b9 2235
0242f74d
AD		 2236 if (num_cb && !track->zb_cb_clear && !track->color_channel_mask &&
2237 !track->blend_read_enable)
2238 num_cb = 0;
2239
2240 for (i = 0; i < num_cb; i++) {
2241 if (track->cb[i].robj == NULL) {
2242 DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
2243 return -EINVAL;
2244 }
2245 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
2246 size += track->cb[i].offset;
2247 if (size > radeon_bo_size(track->cb[i].robj)) {
2248 DRM_ERROR("[drm] Buffer too small for color buffer %d "
2249 "(need %lu have %lu) !\n", i, size,
2250 radeon_bo_size(track->cb[i].robj));
2251 DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
2252 i, track->cb[i].pitch, track->cb[i].cpp,
2253 track->cb[i].offset, track->maxy);
2254 return -EINVAL;
771fe6b9 2255 }
771fe6b9 2256 }
0242f74d 2257 track->cb_dirty = false;
771fe6b9 2258
0242f74d
AD		 2259 if (track->zb_dirty && track->z_enabled) {
2260 if (track->zb.robj == NULL) {
2261 DRM_ERROR("[drm] No buffer for z buffer !\n");
2262 return -EINVAL;
2263 }
2264 size = track->zb.pitch * track->zb.cpp * track->maxy;
2265 size += track->zb.offset;
2266 if (size > radeon_bo_size(track->zb.robj)) {
2267 DRM_ERROR("[drm] Buffer too small for z buffer "
2268 "(need %lu have %lu) !\n", size,
2269 radeon_bo_size(track->zb.robj));
2270 DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
2271 track->zb.pitch, track->zb.cpp,
2272 track->zb.offset, track->maxy);
2273 return -EINVAL;
2274 }
225758d8 2275 }
0242f74d 2276 track->zb_dirty = false;
771fe6b9 2277
0242f74d
AD		 2278 if (track->aa_dirty && track->aaresolve) {
2279 if (track->aa.robj == NULL) {
2280 DRM_ERROR("[drm] No buffer for AA resolve buffer %d !\n", i);
2281 return -EINVAL;
2282 }
2283 /* I believe the format comes from colorbuffer0. */
2284 size = track->aa.pitch * track->cb[0].cpp * track->maxy;
2285 size += track->aa.offset;
2286 if (size > radeon_bo_size(track->aa.robj)) {
2287 DRM_ERROR("[drm] Buffer too small for AA resolve buffer %d "
2288 "(need %lu have %lu) !\n", i, size,
2289 radeon_bo_size(track->aa.robj));
2290 DRM_ERROR("[drm] AA resolve buffer %d (%u %u %u %u)\n",
2291 i, track->aa.pitch, track->cb[0].cpp,
2292 track->aa.offset, track->maxy);
2293 return -EINVAL;
2294 }
2295 }
2296 track->aa_dirty = false;
771fe6b9 2297
0242f74d
AD		 2298 prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
2299 if (track->vap_vf_cntl & (1 << 14)) {
2300 nverts = track->vap_alt_nverts;
2301 } else {
2302 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
2739d49c 2303 }
0242f74d
AD		 2304 switch (prim_walk) {
2305 case 1:
2306 for (i = 0; i < track->num_arrays; i++) {
2307 size = track->arrays[i].esize * track->max_indx * 4;
2308 if (track->arrays[i].robj == NULL) {
2309 DRM_ERROR("(PW %u) Vertex array %u no buffer "
2310 "bound\n", prim_walk, i);
2311 return -EINVAL;
2312 }
2313 if (size > radeon_bo_size(track->arrays[i].robj)) {
2314 dev_err(rdev->dev, "(PW %u) Vertex array %u "
2315 "need %lu dwords have %lu dwords\n",
2316 prim_walk, i, size >> 2,
2317 radeon_bo_size(track->arrays[i].robj)
2318 >> 2);
2319 DRM_ERROR("Max indices %u\n", track->max_indx);
2320 return -EINVAL;
2321 }
771fe6b9 2322 }
0242f74d
AD		 2323 break;
2324 case 2:
2325 for (i = 0; i < track->num_arrays; i++) {
2326 size = track->arrays[i].esize * (nverts - 1) * 4;
2327 if (track->arrays[i].robj == NULL) {
2328 DRM_ERROR("(PW %u) Vertex array %u no buffer "
2329 "bound\n", prim_walk, i);
2330 return -EINVAL;
2331 }
2332 if (size > radeon_bo_size(track->arrays[i].robj)) {
2333 dev_err(rdev->dev, "(PW %u) Vertex array %u "
2334 "need %lu dwords have %lu dwords\n",
2335 prim_walk, i, size >> 2,
2336 radeon_bo_size(track->arrays[i].robj)
2337 >> 2);
2338 return -EINVAL;
2339 }
771fe6b9 2340 }
0242f74d
AD		 2341 break;
2342 case 3:
2343 size = track->vtx_size * nverts;
2344 if (size != track->immd_dwords) {
2345 DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
2346 track->immd_dwords, size);
2347 DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
2348 nverts, track->vtx_size);
2349 return -EINVAL;
771fe6b9 2350 }
0242f74d
AD		 2351 break;
2352 default:
2353 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
2354 prim_walk);
2355 return -EINVAL;
2a0f8918
DA		 2356 }
2357
0242f74d
AD		 2358 if (track->tex_dirty) {
2359 track->tex_dirty = false;
2360 return r100_cs_track_texture_check(rdev, track);
2a0f8918 2361 }
0242f74d 2362 return 0;
2a0f8918
DA		 2363}
2364
0242f74d 2365void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track)
2a0f8918 2366{
0242f74d 2367 unsigned i, face;
2a0f8918 2368
0242f74d
AD		 2369 track->cb_dirty = true;
2370 track->zb_dirty = true;
2371 track->tex_dirty = true;
2372 track->aa_dirty = true;
b7d8cce5 2373
0242f74d
AD		 2374 if (rdev->family < CHIP_R300) {
2375 track->num_cb = 1;
2376 if (rdev->family <= CHIP_RS200)
2377 track->num_texture = 3;
7a50f01a 2378 else
0242f74d
AD		 2379 track->num_texture = 6;
2380 track->maxy = 2048;
2381 track->separate_cube = 1;
28d52043 2382 } else {
0242f74d
AD		 2383 track->num_cb = 4;
2384 track->num_texture = 16;
2385 track->maxy = 4096;
2386 track->separate_cube = 0;
2387 track->aaresolve = false;
2388 track->aa.robj = NULL;
28d52043 2389 }
2a0f8918 2390
0242f74d
AD		 2391 for (i = 0; i < track->num_cb; i++) {
2392 track->cb[i].robj = NULL;
2393 track->cb[i].pitch = 8192;
2394 track->cb[i].cpp = 16;
2395 track->cb[i].offset = 0;
771fe6b9 2396 }
0242f74d
AD		 2397 track->z_enabled = true;
2398 track->zb.robj = NULL;
2399 track->zb.pitch = 8192;
2400 track->zb.cpp = 4;
2401 track->zb.offset = 0;
2402 track->vtx_size = 0x7F;
2403 track->immd_dwords = 0xFFFFFFFFUL;
2404 track->num_arrays = 11;
2405 track->max_indx = 0x00FFFFFFUL;
2406 for (i = 0; i < track->num_arrays; i++) {
2407 track->arrays[i].robj = NULL;
2408 track->arrays[i].esize = 0x7F;
771fe6b9 2409 }
0242f74d
AD		 2410 for (i = 0; i < track->num_texture; i++) {
2411 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
2412 track->textures[i].pitch = 16536;
2413 track->textures[i].width = 16536;
2414 track->textures[i].height = 16536;
2415 track->textures[i].width_11 = 1 << 11;
2416 track->textures[i].height_11 = 1 << 11;
2417 track->textures[i].num_levels = 12;
2418 if (rdev->family <= CHIP_RS200) {
2419 track->textures[i].tex_coord_type = 0;
2420 track->textures[i].txdepth = 0;
2421 } else {
2422 track->textures[i].txdepth = 16;
2423 track->textures[i].tex_coord_type = 1;
2424 }
2425 track->textures[i].cpp = 64;
2426 track->textures[i].robj = NULL;
2427 /* CS IB emission code makes sure texture unit are disabled */
2428 track->textures[i].enabled = false;
2429 track->textures[i].lookup_disable = false;
2430 track->textures[i].roundup_w = true;
2431 track->textures[i].roundup_h = true;
2432 if (track->separate_cube)
2433 for (face = 0; face < 5; face++) {
2434 track->textures[i].cube_info[face].robj = NULL;
2435 track->textures[i].cube_info[face].width = 16536;
2436 track->textures[i].cube_info[face].height = 16536;
2437 track->textures[i].cube_info[face].offset = 0;
2438 }
771fe6b9
JG		 2439 }
2440}
2441
0242f74d
AD		 2442/*
2443 * Global GPU functions
2444 */
1109ca09 2445static void r100_errata(struct radeon_device *rdev)
771fe6b9 2446{
0242f74d 2447 rdev->pll_errata = 0;
771fe6b9 2448
0242f74d
AD		 2449 if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) {
2450 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS;
2451 }
771fe6b9 2452
0242f74d
AD		 2453 if (rdev->family == CHIP_RV100 ||
2454 rdev->family == CHIP_RS100 ||
2455 rdev->family == CHIP_RS200) {
2456 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY;
2457 }
771fe6b9
JG		 2458}
2459
1109ca09 2460static int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
771fe6b9 2461{
0242f74d
AD		 2462 unsigned i;
2463 uint32_t tmp;
771fe6b9 2464
0242f74d
AD		 2465 for (i = 0; i < rdev->usec_timeout; i++) {
2466 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
2467 if (tmp >= n) {
2468 return 0;
2469 }
2470 DRM_UDELAY(1);
771fe6b9 2471 }
0242f74d 2472 return -1;
771fe6b9
JG		 2473}
2474
0242f74d 2475int r100_gui_wait_for_idle(struct radeon_device *rdev)
771fe6b9 2476{
771fe6b9 2477 unsigned i;
0242f74d 2478 uint32_t tmp;
771fe6b9 2479
0242f74d
AD		 2480 if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
2481 printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !"
2482 " Bad things might happen.\n");
771fe6b9 2483 }
0242f74d
AD		 2484 for (i = 0; i < rdev->usec_timeout; i++) {
2485 tmp = RREG32(RADEON_RBBM_STATUS);
2486 if (!(tmp & RADEON_RBBM_ACTIVE)) {
2487 return 0;
2488 }
2489 DRM_UDELAY(1);
771fe6b9 2490 }
0242f74d 2491 return -1;
771fe6b9
JG		 2492}
2493
0242f74d 2494int r100_mc_wait_for_idle(struct radeon_device *rdev)
771fe6b9 2495{
0242f74d 2496 unsigned i;
771fe6b9
JG		 2497 uint32_t tmp;
2498
0242f74d
AD		 2499 for (i = 0; i < rdev->usec_timeout; i++) {
2500 /* read MC_STATUS */
2501 tmp = RREG32(RADEON_MC_STATUS);
2502 if (tmp & RADEON_MC_IDLE) {
2503 return 0;
2504 }
2505 DRM_UDELAY(1);
2506 }
2507 return -1;
771fe6b9
JG		 2508}
2509
0242f74d 2510bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
771fe6b9 2511{
0242f74d 2512 u32 rbbm_status;
771fe6b9 2513
0242f74d
AD		 2514 rbbm_status = RREG32(R_000E40_RBBM_STATUS);
2515 if (!G_000E40_GUI_ACTIVE(rbbm_status)) {
ff212f25 2516 radeon_ring_lockup_update(rdev, ring);
0242f74d
AD		 2517 return false;
2518 }
0242f74d 2519 return radeon_ring_test_lockup(rdev, ring);
771fe6b9
JG		 2520}
2521
74da01dc
AD		 2522/* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
2523void r100_enable_bm(struct radeon_device *rdev)
2524{
2525 uint32_t tmp;
2526 /* Enable bus mastering */
2527 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
2528 WREG32(RADEON_BUS_CNTL, tmp);
2529}
2530
0242f74d 2531void r100_bm_disable(struct radeon_device *rdev)
771fe6b9 2532{
0242f74d
AD		 2533 u32 tmp;
2534
2535 /* disable bus mastering */
2536 tmp = RREG32(R_000030_BUS_CNTL);
2537 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000044);
2538 mdelay(1);
2539 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000042);
2540 mdelay(1);
2541 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000040);
2542 tmp = RREG32(RADEON_BUS_CNTL);
2543 mdelay(1);
2544 pci_clear_master(rdev->pdev);
2545 mdelay(1);
771fe6b9 2546}
e024e110 2547
0242f74d 2548int r100_asic_reset(struct radeon_device *rdev)
e024e110 2549{
0242f74d
AD		 2550 struct r100_mc_save save;
2551 u32 status, tmp;
2552 int ret = 0;
e024e110 2553
0242f74d
AD		 2554 status = RREG32(R_000E40_RBBM_STATUS);
2555 if (!G_000E40_GUI_ACTIVE(status)) {
2556 return 0;
e024e110 2557 }
0242f74d
AD		 2558 r100_mc_stop(rdev, &save);
2559 status = RREG32(R_000E40_RBBM_STATUS);
2560 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2561 /* stop CP */
2562 WREG32(RADEON_CP_CSQ_CNTL, 0);
2563 tmp = RREG32(RADEON_CP_RB_CNTL);
2564 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
2565 WREG32(RADEON_CP_RB_RPTR_WR, 0);
2566 WREG32(RADEON_CP_RB_WPTR, 0);
2567 WREG32(RADEON_CP_RB_CNTL, tmp);
2568 /* save PCI state */
2569 pci_save_state(rdev->pdev);
2570 /* disable bus mastering */
2571 r100_bm_disable(rdev);
2572 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_SE(1) |
2573 S_0000F0_SOFT_RESET_RE(1) |
2574 S_0000F0_SOFT_RESET_PP(1) |
2575 S_0000F0_SOFT_RESET_RB(1));
2576 RREG32(R_0000F0_RBBM_SOFT_RESET);
2577 mdelay(500);
2578 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2579 mdelay(1);
2580 status = RREG32(R_000E40_RBBM_STATUS);
2581 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2582 /* reset CP */
2583 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
2584 RREG32(R_0000F0_RBBM_SOFT_RESET);
2585 mdelay(500);
2586 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2587 mdelay(1);
2588 status = RREG32(R_000E40_RBBM_STATUS);
2589 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2590 /* restore PCI & busmastering */
2591 pci_restore_state(rdev->pdev);
2592 r100_enable_bm(rdev);
2593 /* Check if GPU is idle */
2594 if (G_000E40_SE_BUSY(status) || G_000E40_RE_BUSY(status) ||
2595 G_000E40_TAM_BUSY(status) || G_000E40_PB_BUSY(status)) {
2596 dev_err(rdev->dev, "failed to reset GPU\n");
2597 ret = -1;
2598 } else
2599 dev_info(rdev->dev, "GPU reset succeed\n");
2600 r100_mc_resume(rdev, &save);
2601 return ret;
2602}
e024e110 2603
0242f74d
AD		 2604void r100_set_common_regs(struct radeon_device *rdev)
2605{
2606 struct drm_device *dev = rdev->ddev;
2607 bool force_dac2 = false;
2608 u32 tmp;
f5c5f040 2609
0242f74d
AD		 2610 /* set these so they don't interfere with anything */
2611 WREG32(RADEON_OV0_SCALE_CNTL, 0);
2612 WREG32(RADEON_SUBPIC_CNTL, 0);
2613 WREG32(RADEON_VIPH_CONTROL, 0);
2614 WREG32(RADEON_I2C_CNTL_1, 0);
2615 WREG32(RADEON_DVI_I2C_CNTL_1, 0);
2616 WREG32(RADEON_CAP0_TRIG_CNTL, 0);
2617 WREG32(RADEON_CAP1_TRIG_CNTL, 0);
f5c5f040 2618
0242f74d
AD		 2619 /* always set up dac2 on rn50 and some rv100 as lots
2620 * of servers seem to wire it up to a VGA port but
2621 * don't report it in the bios connector
2622 * table.
2623 */
2624 switch (dev->pdev->device) {
2625 /* RN50 */
2626 case 0x515e:
2627 case 0x5969:
2628 force_dac2 = true;
2629 break;
2630 /* RV100*/
2631 case 0x5159:
2632 case 0x515a:
2633 /* DELL triple head servers */
2634 if ((dev->pdev->subsystem_vendor == 0x1028 /* DELL */) &&
2635 ((dev->pdev->subsystem_device == 0x016c) ||
2636 (dev->pdev->subsystem_device == 0x016d) ||
2637 (dev->pdev->subsystem_device == 0x016e) ||
2638 (dev->pdev->subsystem_device == 0x016f) ||
2639 (dev->pdev->subsystem_device == 0x0170) ||
2640 (dev->pdev->subsystem_device == 0x017d) ||
2641 (dev->pdev->subsystem_device == 0x017e) ||
2642 (dev->pdev->subsystem_device == 0x0183) ||
2643 (dev->pdev->subsystem_device == 0x018a) ||
2644 (dev->pdev->subsystem_device == 0x019a)))
2645 force_dac2 = true;
2646 break;
2647 }
f5c5f040 2648
0242f74d
AD		 2649 if (force_dac2) {
2650 u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
2651 u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
2652 u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
e024e110 2653
0242f74d
AD		 2654 /* For CRT on DAC2, don't turn it on if BIOS didn't
2655 enable it, even it's detected.
2656 */
c93bb85b 2657
0242f74d
AD		 2658 /* force it to crtc0 */
2659 dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
2660 dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
2661 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
c93bb85b 2662
0242f74d
AD		 2663 /* set up the TV DAC */
2664 tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL |
2665 RADEON_TV_DAC_STD_MASK |
2666 RADEON_TV_DAC_RDACPD |
2667 RADEON_TV_DAC_GDACPD |
2668 RADEON_TV_DAC_BDACPD |
2669 RADEON_TV_DAC_BGADJ_MASK |
2670 RADEON_TV_DAC_DACADJ_MASK);
2671 tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
2672 RADEON_TV_DAC_NHOLD |
2673 RADEON_TV_DAC_STD_PS2 |
2674 (0x58 << 16));
f46c0120 2675
0242f74d
AD		 2676 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
2677 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
2678 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
c93bb85b 2679 }
0242f74d
AD		 2680
2681 /* switch PM block to ACPI mode */
2682 tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL);
2683 tmp &= ~RADEON_PM_MODE_SEL;
2684 WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);
2685
2686}
2687
2688/*
2689 * VRAM info
2690 */
2691static void r100_vram_get_type(struct radeon_device *rdev)
2692{
2693 uint32_t tmp;
2694
2695 rdev->mc.vram_is_ddr = false;
2696 if (rdev->flags & RADEON_IS_IGP)
2697 rdev->mc.vram_is_ddr = true;
2698 else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
2699 rdev->mc.vram_is_ddr = true;
2700 if ((rdev->family == CHIP_RV100) ||
2701 (rdev->family == CHIP_RS100) ||
2702 (rdev->family == CHIP_RS200)) {
2703 tmp = RREG32(RADEON_MEM_CNTL);
2704 if (tmp & RV100_HALF_MODE) {
2705 rdev->mc.vram_width = 32;
2706 } else {
2707 rdev->mc.vram_width = 64;
2708 }
2709 if (rdev->flags & RADEON_SINGLE_CRTC) {
2710 rdev->mc.vram_width /= 4;
2711 rdev->mc.vram_is_ddr = true;
dfee5614 2712 }
0242f74d
AD		 2713 } else if (rdev->family <= CHIP_RV280) {
2714 tmp = RREG32(RADEON_MEM_CNTL);
2715 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
2716 rdev->mc.vram_width = 128;
2717 } else {
2718 rdev->mc.vram_width = 64;
2719 }
2720 } else {
2721 /* newer IGPs */
2722 rdev->mc.vram_width = 128;
c93bb85b 2723 }
0242f74d 2724}
c93bb85b 2725
0242f74d
AD		 2726static u32 r100_get_accessible_vram(struct radeon_device *rdev)
2727{
2728 u32 aper_size;
2729 u8 byte;
2730
2731 aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2732
2733 /* Set HDP_APER_CNTL only on cards that are known not to be broken,
2734 * that is has the 2nd generation multifunction PCI interface
2735 */
2736 if (rdev->family == CHIP_RV280 ||
2737 rdev->family >= CHIP_RV350) {
2738 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
2739 ~RADEON_HDP_APER_CNTL);
2740 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
2741 return aper_size * 2;
c93bb85b
JG		 2742 }
2743
0242f74d
AD		 2744 /* Older cards have all sorts of funny issues to deal with. First
2745 * check if it's a multifunction card by reading the PCI config
2746 * header type... Limit those to one aperture size
c93bb85b 2747 */
0242f74d
AD		 2748 pci_read_config_byte(rdev->pdev, 0xe, &byte);
2749 if (byte & 0x80) {
2750 DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
2751 DRM_INFO("Limiting VRAM to one aperture\n");
2752 return aper_size;
2753 }
c93bb85b 2754
0242f74d
AD		 2755 /* Single function older card. We read HDP_APER_CNTL to see how the BIOS
2756 * have set it up. We don't write this as it's broken on some ASICs but
2757 * we expect the BIOS to have done the right thing (might be too optimistic...)
2758 */
2759 if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
2760 return aper_size * 2;
2761 return aper_size;
2762}
c93bb85b 2763
0242f74d
AD		 2764void r100_vram_init_sizes(struct radeon_device *rdev)
2765{
2766 u64 config_aper_size;
c93bb85b 2767
0242f74d
AD		 2768 /* work out accessible VRAM */
2769 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
2770 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
2771 rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev);
2772 /* FIXME we don't use the second aperture yet when we could use it */
2773 if (rdev->mc.visible_vram_size > rdev->mc.aper_size)
2774 rdev->mc.visible_vram_size = rdev->mc.aper_size;
2775 config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2776 if (rdev->flags & RADEON_IS_IGP) {
2777 uint32_t tom;
2778 /* read NB_TOM to get the amount of ram stolen for the GPU */
2779 tom = RREG32(RADEON_NB_TOM);
2780 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
2781 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2782 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2783 } else {
2784 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
2785 /* Some production boards of m6 will report 0
2786 * if it's 8 MB
2787 */
2788 if (rdev->mc.real_vram_size == 0) {
2789 rdev->mc.real_vram_size = 8192 * 1024;
2790 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2791 }
2792 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
2793 * Novell bug 204882 + along with lots of ubuntu ones
2794 */
2795 if (rdev->mc.aper_size > config_aper_size)
2796 config_aper_size = rdev->mc.aper_size;
2797
2798 if (config_aper_size > rdev->mc.real_vram_size)
2799 rdev->mc.mc_vram_size = config_aper_size;
2800 else
2801 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
c93bb85b 2802 }
0242f74d 2803}
c93bb85b 2804
0242f74d
AD		 2805void r100_vga_set_state(struct radeon_device *rdev, bool state)
2806{
2807 uint32_t temp;
2808
2809 temp = RREG32(RADEON_CONFIG_CNTL);
2810 if (state == false) {
2811 temp &= ~RADEON_CFG_VGA_RAM_EN;
2812 temp |= RADEON_CFG_VGA_IO_DIS;
2813 } else {
2814 temp &= ~RADEON_CFG_VGA_IO_DIS;
c93bb85b 2815 }
0242f74d
AD		 2816 WREG32(RADEON_CONFIG_CNTL, temp);
2817}
c93bb85b 2818
1109ca09 2819static void r100_mc_init(struct radeon_device *rdev)
0242f74d
AD		 2820{
2821 u64 base;
c93bb85b 2822
0242f74d
AD		 2823 r100_vram_get_type(rdev);
2824 r100_vram_init_sizes(rdev);
2825 base = rdev->mc.aper_base;
2826 if (rdev->flags & RADEON_IS_IGP)
2827 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
2828 radeon_vram_location(rdev, &rdev->mc, base);
2829 rdev->mc.gtt_base_align = 0;
2830 if (!(rdev->flags & RADEON_IS_AGP))
2831 radeon_gtt_location(rdev, &rdev->mc);
2832 radeon_update_bandwidth_info(rdev);
2833}
2834
2835
2836/*
2837 * Indirect registers accessor
2838 */
2839void r100_pll_errata_after_index(struct radeon_device *rdev)
2840{
2841 if (rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS) {
2842 (void)RREG32(RADEON_CLOCK_CNTL_DATA);
2843 (void)RREG32(RADEON_CRTC_GEN_CNTL);
c93bb85b 2844 }
0242f74d 2845}
c93bb85b 2846
0242f74d
AD		 2847static void r100_pll_errata_after_data(struct radeon_device *rdev)
2848{
2849 /* This workarounds is necessary on RV100, RS100 and RS200 chips
2850 * or the chip could hang on a subsequent access
2851 */
2852 if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
2853 mdelay(5);
c93bb85b
JG		 2854 }
2855
0242f74d
AD		 2856 /* This function is required to workaround a hardware bug in some (all?)
2857 * revisions of the R300. This workaround should be called after every
2858 * CLOCK_CNTL_INDEX register access. If not, register reads afterward
2859 * may not be correct.
2860 */
2861 if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
2862 uint32_t save, tmp;
c93bb85b 2863
0242f74d
AD		 2864 save = RREG32(RADEON_CLOCK_CNTL_INDEX);
2865 tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
2866 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
2867 tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
2868 WREG32(RADEON_CLOCK_CNTL_INDEX, save);
c93bb85b 2869 }
0242f74d 2870}
c93bb85b 2871
0242f74d
AD		 2872uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
2873{
0a5b7b0b 2874 unsigned long flags;
0242f74d 2875 uint32_t data;
c93bb85b 2876
0a5b7b0b 2877 spin_lock_irqsave(&rdev->pll_idx_lock, flags);
0242f74d
AD		 2878 WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
2879 r100_pll_errata_after_index(rdev);
2880 data = RREG32(RADEON_CLOCK_CNTL_DATA);
2881 r100_pll_errata_after_data(rdev);
0a5b7b0b 2882 spin_unlock_irqrestore(&rdev->pll_idx_lock, flags);
0242f74d
AD		 2883 return data;
2884}
c93bb85b 2885
0242f74d
AD		 2886void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2887{
0a5b7b0b
AD		 2888 unsigned long flags;
2889
2890 spin_lock_irqsave(&rdev->pll_idx_lock, flags);
0242f74d
AD		 2891 WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN));
2892 r100_pll_errata_after_index(rdev);
2893 WREG32(RADEON_CLOCK_CNTL_DATA, v);
2894 r100_pll_errata_after_data(rdev);
0a5b7b0b 2895 spin_unlock_irqrestore(&rdev->pll_idx_lock, flags);
0242f74d
AD		 2896}
2897
1109ca09 2898static void r100_set_safe_registers(struct radeon_device *rdev)
0242f74d
AD		 2899{
2900 if (ASIC_IS_RN50(rdev)) {
2901 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
2902 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
2903 } else if (rdev->family < CHIP_R200) {
2904 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
2905 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
c93bb85b 2906 } else {
0242f74d 2907 r200_set_safe_registers(rdev);
c93bb85b 2908 }
0242f74d 2909}
c93bb85b 2910
0242f74d
AD		 2911/*
2912 * Debugfs info
2913 */
2914#if defined(CONFIG_DEBUG_FS)
2915static int r100_debugfs_rbbm_info(struct seq_file *m, void *data)
2916{
2917 struct drm_info_node *node = (struct drm_info_node *) m->private;
2918 struct drm_device *dev = node->minor->dev;
2919 struct radeon_device *rdev = dev->dev_private;
2920 uint32_t reg, value;
2921 unsigned i;
c93bb85b 2922
0242f74d
AD		 2923 seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
2924 seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
2925 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2926 for (i = 0; i < 64; i++) {
2927 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100);
2928 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
2929 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
2930 value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
2931 seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
2932 }
2933 return 0;
2934}
c93bb85b 2935
0242f74d
AD		 2936static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data)
2937{
2938 struct drm_info_node *node = (struct drm_info_node *) m->private;
2939 struct drm_device *dev = node->minor->dev;
2940 struct radeon_device *rdev = dev->dev_private;
2941 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2942 uint32_t rdp, wdp;
2943 unsigned count, i, j;
c93bb85b 2944
0242f74d
AD		 2945 radeon_ring_free_size(rdev, ring);
2946 rdp = RREG32(RADEON_CP_RB_RPTR);
2947 wdp = RREG32(RADEON_CP_RB_WPTR);
2948 count = (rdp + ring->ring_size - wdp) & ring->ptr_mask;
2949 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2950 seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
2951 seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
2952 seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw);
2953 seq_printf(m, "%u dwords in ring\n", count);
0eb3448a
AI		 2954 if (ring->ready) {
2955 for (j = 0; j <= count; j++) {
2956 i = (rdp + j) & ring->ptr_mask;
2957 seq_printf(m, "r[%04d]=0x%08x\n", i, ring->ring[i]);
2958 }
0242f74d
AD		 2959 }
2960 return 0;
2961}
c93bb85b 2962
c93bb85b 2963
0242f74d
AD		 2964static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data)
2965{
2966 struct drm_info_node *node = (struct drm_info_node *) m->private;
2967 struct drm_device *dev = node->minor->dev;
2968 struct radeon_device *rdev = dev->dev_private;
2969 uint32_t csq_stat, csq2_stat, tmp;
2970 unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
2971 unsigned i;
c93bb85b 2972
0242f74d
AD		 2973 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2974 seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
2975 csq_stat = RREG32(RADEON_CP_CSQ_STAT);
2976 csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
2977 r_rptr = (csq_stat >> 0) & 0x3ff;
2978 r_wptr = (csq_stat >> 10) & 0x3ff;
2979 ib1_rptr = (csq_stat >> 20) & 0x3ff;
2980 ib1_wptr = (csq2_stat >> 0) & 0x3ff;
2981 ib2_rptr = (csq2_stat >> 10) & 0x3ff;
2982 ib2_wptr = (csq2_stat >> 20) & 0x3ff;
2983 seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
2984 seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
2985 seq_printf(m, "Ring rptr %u\n", r_rptr);
2986 seq_printf(m, "Ring wptr %u\n", r_wptr);
2987 seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
2988 seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
2989 seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
2990 seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
2991 /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
2992 * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
2993 seq_printf(m, "Ring fifo:\n");
2994 for (i = 0; i < 256; i++) {
2995 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2996 tmp = RREG32(RADEON_CP_CSQ_DATA);
2997 seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
2998 }
2999 seq_printf(m, "Indirect1 fifo:\n");
3000 for (i = 256; i <= 512; i++) {
3001 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
3002 tmp = RREG32(RADEON_CP_CSQ_DATA);
3003 seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
3004 }
3005 seq_printf(m, "Indirect2 fifo:\n");
3006 for (i = 640; i < ib1_wptr; i++) {
3007 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
3008 tmp = RREG32(RADEON_CP_CSQ_DATA);
3009 seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
3010 }
3011 return 0;
3012}
3013
3014static int r100_debugfs_mc_info(struct seq_file *m, void *data)
3015{
3016 struct drm_info_node *node = (struct drm_info_node *) m->private;
3017 struct drm_device *dev = node->minor->dev;
3018 struct radeon_device *rdev = dev->dev_private;
3019 uint32_t tmp;
c93bb85b 3020
0242f74d
AD		 3021 tmp = RREG32(RADEON_CONFIG_MEMSIZE);
3022 seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
3023 tmp = RREG32(RADEON_MC_FB_LOCATION);
3024 seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
3025 tmp = RREG32(RADEON_BUS_CNTL);
3026 seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
3027 tmp = RREG32(RADEON_MC_AGP_LOCATION);
3028 seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
3029 tmp = RREG32(RADEON_AGP_BASE);
3030 seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
3031 tmp = RREG32(RADEON_HOST_PATH_CNTL);
3032 seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
3033 tmp = RREG32(0x01D0);
3034 seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
3035 tmp = RREG32(RADEON_AIC_LO_ADDR);
3036 seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
3037 tmp = RREG32(RADEON_AIC_HI_ADDR);
3038 seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
3039 tmp = RREG32(0x01E4);
3040 seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
3041 return 0;
3042}
c93bb85b 3043
0242f74d
AD		 3044static struct drm_info_list r100_debugfs_rbbm_list[] = {
3045 {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL},
3046};
c93bb85b 3047
0242f74d
AD		 3048static struct drm_info_list r100_debugfs_cp_list[] = {
3049 {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL},
3050 {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL},
3051};
c93bb85b 3052
0242f74d
AD		 3053static struct drm_info_list r100_debugfs_mc_info_list[] = {
3054 {"r100_mc_info", r100_debugfs_mc_info, 0, NULL},
3055};
3056#endif
c93bb85b 3057
0242f74d
AD		 3058int r100_debugfs_rbbm_init(struct radeon_device *rdev)
3059{
3060#if defined(CONFIG_DEBUG_FS)
3061 return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1);
3062#else
3063 return 0;
3064#endif
3065}
c93bb85b 3066
0242f74d
AD		 3067int r100_debugfs_cp_init(struct radeon_device *rdev)
3068{
3069#if defined(CONFIG_DEBUG_FS)
3070 return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2);
3071#else
3072 return 0;
3073#endif
3074}
c93bb85b 3075
0242f74d
AD		 3076int r100_debugfs_mc_info_init(struct radeon_device *rdev)
3077{
3078#if defined(CONFIG_DEBUG_FS)
3079 return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1);
3080#else
3081 return 0;
3082#endif
3083}
c93bb85b 3084
0242f74d
AD		 3085int r100_set_surface_reg(struct radeon_device *rdev, int reg,
3086 uint32_t tiling_flags, uint32_t pitch,
3087 uint32_t offset, uint32_t obj_size)
3088{
3089 int surf_index = reg * 16;
3090 int flags = 0;
c93bb85b 3091
0242f74d
AD		 3092 if (rdev->family <= CHIP_RS200) {
3093 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
3094 == (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
3095 flags |= RADEON_SURF_TILE_COLOR_BOTH;
3096 if (tiling_flags & RADEON_TILING_MACRO)
3097 flags |= RADEON_SURF_TILE_COLOR_MACRO;
67d5ced5
AD		 3098 /* setting pitch to 0 disables tiling */
3099 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
3100 == 0)
3101 pitch = 0;
0242f74d
AD		 3102 } else if (rdev->family <= CHIP_RV280) {
3103 if (tiling_flags & (RADEON_TILING_MACRO))
3104 flags |= R200_SURF_TILE_COLOR_MACRO;
3105 if (tiling_flags & RADEON_TILING_MICRO)
3106 flags |= R200_SURF_TILE_COLOR_MICRO;
3107 } else {
3108 if (tiling_flags & RADEON_TILING_MACRO)
3109 flags |= R300_SURF_TILE_MACRO;
3110 if (tiling_flags & RADEON_TILING_MICRO)
3111 flags |= R300_SURF_TILE_MICRO;
3112 }
c93bb85b 3113
0242f74d
AD		 3114 if (tiling_flags & RADEON_TILING_SWAP_16BIT)
3115 flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP;
3116 if (tiling_flags & RADEON_TILING_SWAP_32BIT)
3117 flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP;
3118
0242f74d
AD		 3119 /* r100/r200 divide by 16 */
3120 if (rdev->family < CHIP_R300)
3121 flags |= pitch / 16;
3122 else
3123 flags |= pitch / 8;
c93bb85b 3124
c93bb85b 3125
0242f74d
AD		 3126 DRM_DEBUG_KMS("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
3127 WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
3128 WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
3129 WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);
3130 return 0;
3131}
c93bb85b 3132
0242f74d
AD		 3133void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
3134{
3135 int surf_index = reg * 16;
3136 WREG32(RADEON_SURFACE0_INFO + surf_index, 0);
3137}
c93bb85b 3138
0242f74d
AD		 3139void r100_bandwidth_update(struct radeon_device *rdev)
3140{
3141 fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff;
3142 fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff;
3143 fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff;
3144 uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
3145 fixed20_12 memtcas_ff[8] = {
3146 dfixed_init(1),
3147 dfixed_init(2),
3148 dfixed_init(3),
3149 dfixed_init(0),
3150 dfixed_init_half(1),
3151 dfixed_init_half(2),
3152 dfixed_init(0),
3153 };
3154 fixed20_12 memtcas_rs480_ff[8] = {
3155 dfixed_init(0),
3156 dfixed_init(1),
3157 dfixed_init(2),
3158 dfixed_init(3),
3159 dfixed_init(0),
3160 dfixed_init_half(1),
3161 dfixed_init_half(2),
3162 dfixed_init_half(3),
3163 };
3164 fixed20_12 memtcas2_ff[8] = {
3165 dfixed_init(0),
3166 dfixed_init(1),
3167 dfixed_init(2),
3168 dfixed_init(3),
3169 dfixed_init(4),
3170 dfixed_init(5),
3171 dfixed_init(6),
3172 dfixed_init(7),
3173 };
3174 fixed20_12 memtrbs[8] = {
3175 dfixed_init(1),
3176 dfixed_init_half(1),
3177 dfixed_init(2),
3178 dfixed_init_half(2),
3179 dfixed_init(3),
3180 dfixed_init_half(3),
3181 dfixed_init(4),
3182 dfixed_init_half(4)
3183 };
3184 fixed20_12 memtrbs_r4xx[8] = {
3185 dfixed_init(4),
3186 dfixed_init(5),
3187 dfixed_init(6),
3188 dfixed_init(7),
3189 dfixed_init(8),
3190 dfixed_init(9),
3191 dfixed_init(10),
3192 dfixed_init(11)
3193 };
3194 fixed20_12 min_mem_eff;
3195 fixed20_12 mc_latency_sclk, mc_latency_mclk, k1;
3196 fixed20_12 cur_latency_mclk, cur_latency_sclk;
3197 fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate,
3198 disp_drain_rate2, read_return_rate;
3199 fixed20_12 time_disp1_drop_priority;
3200 int c;
3201 int cur_size = 16; /* in octawords */
3202 int critical_point = 0, critical_point2;
3203/* uint32_t read_return_rate, time_disp1_drop_priority; */
3204 int stop_req, max_stop_req;
3205 struct drm_display_mode *mode1 = NULL;
3206 struct drm_display_mode *mode2 = NULL;
3207 uint32_t pixel_bytes1 = 0;
3208 uint32_t pixel_bytes2 = 0;
c93bb85b 3209
8efe82ca
AD		 3210 if (!rdev->mode_info.mode_config_initialized)
3211 return;
3212
0242f74d 3213 radeon_update_display_priority(rdev);
c93bb85b 3214
0242f74d
AD		 3215 if (rdev->mode_info.crtcs[0]->base.enabled) {
3216 mode1 = &rdev->mode_info.crtcs[0]->base.mode;
f4510a27 3217 pixel_bytes1 = rdev->mode_info.crtcs[0]->base.primary->fb->bits_per_pixel / 8;
0242f74d
AD		 3218 }
3219 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3220 if (rdev->mode_info.crtcs[1]->base.enabled) {
3221 mode2 = &rdev->mode_info.crtcs[1]->base.mode;
f4510a27 3222 pixel_bytes2 = rdev->mode_info.crtcs[1]->base.primary->fb->bits_per_pixel / 8;
0242f74d
AD		 3223 }
3224 }
c93bb85b 3225
0242f74d
AD		 3226 min_mem_eff.full = dfixed_const_8(0);
3227 /* get modes */
3228 if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
3229 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);
3230 mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT);
3231 mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT);
3232 /* check crtc enables */
3233 if (mode2)
3234 mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
3235 if (mode1)
3236 mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
3237 WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
3238 }
c93bb85b 3239
0242f74d
AD		 3240 /*
3241 * determine is there is enough bw for current mode
3242 */
3243 sclk_ff = rdev->pm.sclk;
3244 mclk_ff = rdev->pm.mclk;
c93bb85b 3245
0242f74d
AD		 3246 temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
3247 temp_ff.full = dfixed_const(temp);
3248 mem_bw.full = dfixed_mul(mclk_ff, temp_ff);
c93bb85b 3249
0242f74d
AD		 3250 pix_clk.full = 0;
3251 pix_clk2.full = 0;
3252 peak_disp_bw.full = 0;
3253 if (mode1) {
3254 temp_ff.full = dfixed_const(1000);
3255 pix_clk.full = dfixed_const(mode1->clock); /* convert to fixed point */
3256 pix_clk.full = dfixed_div(pix_clk, temp_ff);
3257 temp_ff.full = dfixed_const(pixel_bytes1);
3258 peak_disp_bw.full += dfixed_mul(pix_clk, temp_ff);
3259 }
3260 if (mode2) {
3261 temp_ff.full = dfixed_const(1000);
3262 pix_clk2.full = dfixed_const(mode2->clock); /* convert to fixed point */
3263 pix_clk2.full = dfixed_div(pix_clk2, temp_ff);
3264 temp_ff.full = dfixed_const(pixel_bytes2);
3265 peak_disp_bw.full += dfixed_mul(pix_clk2, temp_ff);
3266 }
c93bb85b 3267
0242f74d
AD		 3268 mem_bw.full = dfixed_mul(mem_bw, min_mem_eff);
3269 if (peak_disp_bw.full >= mem_bw.full) {
3270 DRM_ERROR("You may not have enough display bandwidth for current mode\n"
3271 "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
3272 }
c93bb85b 3273
0242f74d
AD		 3274 /* Get values from the EXT_MEM_CNTL register...converting its contents. */
3275 temp = RREG32(RADEON_MEM_TIMING_CNTL);
3276 if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
3277 mem_trcd = ((temp >> 2) & 0x3) + 1;
3278 mem_trp = ((temp & 0x3)) + 1;
3279 mem_tras = ((temp & 0x70) >> 4) + 1;
3280 } else if (rdev->family == CHIP_R300 ||
3281 rdev->family == CHIP_R350) { /* r300, r350 */
3282 mem_trcd = (temp & 0x7) + 1;
3283 mem_trp = ((temp >> 8) & 0x7) + 1;
3284 mem_tras = ((temp >> 11) & 0xf) + 4;
3285 } else if (rdev->family == CHIP_RV350 ||
3286 rdev->family <= CHIP_RV380) {
3287 /* rv3x0 */
3288 mem_trcd = (temp & 0x7) + 3;
3289 mem_trp = ((temp >> 8) & 0x7) + 3;
3290 mem_tras = ((temp >> 11) & 0xf) + 6;
3291 } else if (rdev->family == CHIP_R420 ||
3292 rdev->family == CHIP_R423 ||
3293 rdev->family == CHIP_RV410) {
3294 /* r4xx */
3295 mem_trcd = (temp & 0xf) + 3;
3296 if (mem_trcd > 15)
3297 mem_trcd = 15;
3298 mem_trp = ((temp >> 8) & 0xf) + 3;
3299 if (mem_trp > 15)
3300 mem_trp = 15;
3301 mem_tras = ((temp >> 12) & 0x1f) + 6;
3302 if (mem_tras > 31)
3303 mem_tras = 31;
3304 } else { /* RV200, R200 */
3305 mem_trcd = (temp & 0x7) + 1;
3306 mem_trp = ((temp >> 8) & 0x7) + 1;
3307 mem_tras = ((temp >> 12) & 0xf) + 4;
3308 }
3309 /* convert to FF */
3310 trcd_ff.full = dfixed_const(mem_trcd);
3311 trp_ff.full = dfixed_const(mem_trp);
3312 tras_ff.full = dfixed_const(mem_tras);
c93bb85b 3313
0242f74d
AD		 3314 /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
3315 temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
3316 data = (temp & (7 << 20)) >> 20;
3317 if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) {
3318 if (rdev->family == CHIP_RS480) /* don't think rs400 */
3319 tcas_ff = memtcas_rs480_ff[data];
3320 else
3321 tcas_ff = memtcas_ff[data];
3322 } else
3323 tcas_ff = memtcas2_ff[data];
c93bb85b 3324
0242f74d
AD		 3325 if (rdev->family == CHIP_RS400 ||
3326 rdev->family == CHIP_RS480) {
3327 /* extra cas latency stored in bits 23-25 0-4 clocks */
3328 data = (temp >> 23) & 0x7;
3329 if (data < 5)
3330 tcas_ff.full += dfixed_const(data);
c93bb85b 3331 }
551ebd83 3332
0242f74d
AD		 3333 if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
3334 /* on the R300, Tcas is included in Trbs.
3335 */
3336 temp = RREG32(RADEON_MEM_CNTL);
3337 data = (R300_MEM_NUM_CHANNELS_MASK & temp);
3338 if (data == 1) {
3339 if (R300_MEM_USE_CD_CH_ONLY & temp) {
3340 temp = RREG32(R300_MC_IND_INDEX);
3341 temp &= ~R300_MC_IND_ADDR_MASK;
3342 temp |= R300_MC_READ_CNTL_CD_mcind;
3343 WREG32(R300_MC_IND_INDEX, temp);
3344 temp = RREG32(R300_MC_IND_DATA);
3345 data = (R300_MEM_RBS_POSITION_C_MASK & temp);
3346 } else {
3347 temp = RREG32(R300_MC_READ_CNTL_AB);
3348 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
3349 }
3350 } else {
3351 temp = RREG32(R300_MC_READ_CNTL_AB);
3352 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
3353 }
3354 if (rdev->family == CHIP_RV410 ||
3355 rdev->family == CHIP_R420 ||
3356 rdev->family == CHIP_R423)
3357 trbs_ff = memtrbs_r4xx[data];
3358 else
3359 trbs_ff = memtrbs[data];
3360 tcas_ff.full += trbs_ff.full;
3361 }
551ebd83 3362
0242f74d 3363 sclk_eff_ff.full = sclk_ff.full;
d785d78b 3364
0242f74d
AD		 3365 if (rdev->flags & RADEON_IS_AGP) {
3366 fixed20_12 agpmode_ff;
3367 agpmode_ff.full = dfixed_const(radeon_agpmode);
3368 temp_ff.full = dfixed_const_666(16);
3369 sclk_eff_ff.full -= dfixed_mul(agpmode_ff, temp_ff);
3370 }
3371 /* TODO PCIE lanes may affect this - agpmode == 16?? */
d785d78b 3372
0242f74d
AD		 3373 if (ASIC_IS_R300(rdev)) {
3374 sclk_delay_ff.full = dfixed_const(250);
3375 } else {
3376 if ((rdev->family == CHIP_RV100) ||
3377 rdev->flags & RADEON_IS_IGP) {
3378 if (rdev->mc.vram_is_ddr)
3379 sclk_delay_ff.full = dfixed_const(41);
3380 else
3381 sclk_delay_ff.full = dfixed_const(33);
3382 } else {
3383 if (rdev->mc.vram_width == 128)
3384 sclk_delay_ff.full = dfixed_const(57);
3385 else
3386 sclk_delay_ff.full = dfixed_const(41);
3387 }
d785d78b
DA		 3388 }
3389
0242f74d 3390 mc_latency_sclk.full = dfixed_div(sclk_delay_ff, sclk_eff_ff);
d785d78b 3391
0242f74d
AD		 3392 if (rdev->mc.vram_is_ddr) {
3393 if (rdev->mc.vram_width == 32) {
3394 k1.full = dfixed_const(40);
3395 c = 3;
3396 } else {
3397 k1.full = dfixed_const(20);
3398 c = 1;
3399 }
3400 } else {
3401 k1.full = dfixed_const(40);
3402 c = 3;
3403 }
37cf6b03 3404
0242f74d
AD		 3405 temp_ff.full = dfixed_const(2);
3406 mc_latency_mclk.full = dfixed_mul(trcd_ff, temp_ff);
3407 temp_ff.full = dfixed_const(c);
3408 mc_latency_mclk.full += dfixed_mul(tcas_ff, temp_ff);
3409 temp_ff.full = dfixed_const(4);
3410 mc_latency_mclk.full += dfixed_mul(tras_ff, temp_ff);
3411 mc_latency_mclk.full += dfixed_mul(trp_ff, temp_ff);
3412 mc_latency_mclk.full += k1.full;
37cf6b03 3413
0242f74d
AD		 3414 mc_latency_mclk.full = dfixed_div(mc_latency_mclk, mclk_ff);
3415 mc_latency_mclk.full += dfixed_div(temp_ff, sclk_eff_ff);
37cf6b03 3416
0242f74d
AD		 3417 /*
3418 HW cursor time assuming worst case of full size colour cursor.
3419 */
3420 temp_ff.full = dfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
3421 temp_ff.full += trcd_ff.full;
3422 if (temp_ff.full < tras_ff.full)
3423 temp_ff.full = tras_ff.full;
3424 cur_latency_mclk.full = dfixed_div(temp_ff, mclk_ff);
37cf6b03 3425
0242f74d
AD		 3426 temp_ff.full = dfixed_const(cur_size);
3427 cur_latency_sclk.full = dfixed_div(temp_ff, sclk_eff_ff);
3428 /*
3429 Find the total latency for the display data.
3430 */
3431 disp_latency_overhead.full = dfixed_const(8);
3432 disp_latency_overhead.full = dfixed_div(disp_latency_overhead, sclk_ff);
3433 mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
3434 mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
37cf6b03 3435
0242f74d
AD		 3436 if (mc_latency_mclk.full > mc_latency_sclk.full)
3437 disp_latency.full = mc_latency_mclk.full;
3438 else
3439 disp_latency.full = mc_latency_sclk.full;
551ebd83 3440
0242f74d
AD		 3441 /* setup Max GRPH_STOP_REQ default value */
3442 if (ASIC_IS_RV100(rdev))
3443 max_stop_req = 0x5c;
3444 else
3445 max_stop_req = 0x7c;
d785d78b 3446
0242f74d
AD		 3447 if (mode1) {
3448 /* CRTC1
3449 Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
3450 GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
3451 */
3452 stop_req = mode1->hdisplay * pixel_bytes1 / 16;
d785d78b 3453
0242f74d
AD		 3454 if (stop_req > max_stop_req)
3455 stop_req = max_stop_req;
551ebd83 3456
0242f74d
AD		 3457 /*
3458 Find the drain rate of the display buffer.
3459 */
3460 temp_ff.full = dfixed_const((16/pixel_bytes1));
3461 disp_drain_rate.full = dfixed_div(pix_clk, temp_ff);
551ebd83 3462
0242f74d
AD		 3463 /*
3464 Find the critical point of the display buffer.
3465 */
3466 crit_point_ff.full = dfixed_mul(disp_drain_rate, disp_latency);
3467 crit_point_ff.full += dfixed_const_half(0);
a41ceb1c 3468
0242f74d
AD		 3469 critical_point = dfixed_trunc(crit_point_ff);
3470
3471 if (rdev->disp_priority == 2) {
3472 critical_point = 0;
551ebd83 3473 }
40b4a759 3474
0242f74d
AD		 3475 /*
3476 The critical point should never be above max_stop_req-4. Setting
3477 GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
3478 */
3479 if (max_stop_req - critical_point < 4)
3480 critical_point = 0;
3481
3482 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
3483 /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
3484 critical_point = 0x10;
551ebd83 3485 }
0242f74d
AD		 3486
3487 temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
3488 temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
3489 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3490 temp &= ~(RADEON_GRPH_START_REQ_MASK);
3491 if ((rdev->family == CHIP_R350) &&
3492 (stop_req > 0x15)) {
3493 stop_req -= 0x10;
551ebd83 3494 }
0242f74d
AD		 3495 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3496 temp |= RADEON_GRPH_BUFFER_SIZE;
3497 temp &= ~(RADEON_GRPH_CRITICAL_CNTL |
3498 RADEON_GRPH_CRITICAL_AT_SOF |
3499 RADEON_GRPH_STOP_CNTL);
3500 /*
3501 Write the result into the register.
3502 */
3503 WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3504 (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
40b4a759 3505
0242f74d
AD		 3506#if 0
3507 if ((rdev->family == CHIP_RS400) ||
3508 (rdev->family == CHIP_RS480)) {
3509 /* attempt to program RS400 disp regs correctly ??? */
3510 temp = RREG32(RS400_DISP1_REG_CNTL);
3511 temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK |
3512 RS400_DISP1_STOP_REQ_LEVEL_MASK);
3513 WREG32(RS400_DISP1_REQ_CNTL1, (temp |
3514 (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3515 (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3516 temp = RREG32(RS400_DMIF_MEM_CNTL1);
3517 temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK |
3518 RS400_DISP1_CRITICAL_POINT_STOP_MASK);
3519 WREG32(RS400_DMIF_MEM_CNTL1, (temp |
3520 (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) |
3521 (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
fff1ce4d 3522 }
0242f74d 3523#endif
fff1ce4d 3524
0242f74d
AD		 3525 DRM_DEBUG_KMS("GRPH_BUFFER_CNTL from to %x\n",
3526 /* (unsigned int)info->SavedReg->grph_buffer_cntl, */
3527 (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
cae94b0a 3528 }
0242f74d
AD		 3529
3530 if (mode2) {
3531 u32 grph2_cntl;
3532 stop_req = mode2->hdisplay * pixel_bytes2 / 16;
3533
3534 if (stop_req > max_stop_req)
3535 stop_req = max_stop_req;
3536
3537 /*
3538 Find the drain rate of the display buffer.
3539 */
3540 temp_ff.full = dfixed_const((16/pixel_bytes2));
3541 disp_drain_rate2.full = dfixed_div(pix_clk2, temp_ff);
3542
3543 grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL);
3544 grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK);
3545 grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3546 grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK);
3547 if ((rdev->family == CHIP_R350) &&
3548 (stop_req > 0x15)) {
3549 stop_req -= 0x10;
551ebd83 3550 }
0242f74d
AD		 3551 grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3552 grph2_cntl |= RADEON_GRPH_BUFFER_SIZE;
3553 grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL |
3554 RADEON_GRPH_CRITICAL_AT_SOF |
3555 RADEON_GRPH_STOP_CNTL);
3556
3557 if ((rdev->family == CHIP_RS100) ||
3558 (rdev->family == CHIP_RS200))
3559 critical_point2 = 0;
3560 else {
3561 temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
3562 temp_ff.full = dfixed_const(temp);
3563 temp_ff.full = dfixed_mul(mclk_ff, temp_ff);
3564 if (sclk_ff.full < temp_ff.full)
3565 temp_ff.full = sclk_ff.full;
3566
3567 read_return_rate.full = temp_ff.full;
3568
3569 if (mode1) {
3570 temp_ff.full = read_return_rate.full - disp_drain_rate.full;
3571 time_disp1_drop_priority.full = dfixed_div(crit_point_ff, temp_ff);
3572 } else {
3573 time_disp1_drop_priority.full = 0;
551ebd83 3574 }
0242f74d
AD		 3575 crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full;
3576 crit_point_ff.full = dfixed_mul(crit_point_ff, disp_drain_rate2);
3577 crit_point_ff.full += dfixed_const_half(0);
3578
3579 critical_point2 = dfixed_trunc(crit_point_ff);
3580
3581 if (rdev->disp_priority == 2) {
3582 critical_point2 = 0;
551ebd83 3583 }
40b4a759 3584
0242f74d
AD		 3585 if (max_stop_req - critical_point2 < 4)
3586 critical_point2 = 0;
551ebd83 3587
0242f74d 3588 }
551ebd83 3589
0242f74d
AD		 3590 if (critical_point2 == 0 && rdev->family == CHIP_R300) {
3591 /* some R300 cards have problem with this set to 0 */
3592 critical_point2 = 0x10;
3593 }
40b4a759 3594
0242f74d
AD		 3595 WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3596 (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
551ebd83 3597
0242f74d
AD		 3598 if ((rdev->family == CHIP_RS400) ||
3599 (rdev->family == CHIP_RS480)) {
3600#if 0
3601 /* attempt to program RS400 disp2 regs correctly ??? */
3602 temp = RREG32(RS400_DISP2_REQ_CNTL1);
3603 temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK |
3604 RS400_DISP2_STOP_REQ_LEVEL_MASK);
3605 WREG32(RS400_DISP2_REQ_CNTL1, (temp |
3606 (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3607 (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3608 temp = RREG32(RS400_DISP2_REQ_CNTL2);
3609 temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK |
3610 RS400_DISP2_CRITICAL_POINT_STOP_MASK);
3611 WREG32(RS400_DISP2_REQ_CNTL2, (temp |
3612 (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) |
3613 (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT)));
3614#endif
3615 WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);
3616 WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000);
3617 WREG32(RS400_DMIF_MEM_CNTL1, 0x29CA71DC);
3618 WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
551ebd83 3619 }
0242f74d
AD		 3620
3621 DRM_DEBUG_KMS("GRPH2_BUFFER_CNTL from to %x\n",
3622 (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
551ebd83
DA		 3623 }
3624}
3ce0a23d 3625
e32eb50d 3626int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
3ce0a23d
JG		 3627{
3628 uint32_t scratch;
3629 uint32_t tmp = 0;
3630 unsigned i;
3631 int r;
3632
3633 r = radeon_scratch_get(rdev, &scratch);
3634 if (r) {
3635 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
3636 return r;
3637 }
3638 WREG32(scratch, 0xCAFEDEAD);
e32eb50d 3639 r = radeon_ring_lock(rdev, ring, 2);
3ce0a23d
JG		 3640 if (r) {
3641 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
3642 radeon_scratch_free(rdev, scratch);
3643 return r;
3644 }
e32eb50d
CK		 3645 radeon_ring_write(ring, PACKET0(scratch, 0));
3646 radeon_ring_write(ring, 0xDEADBEEF);
1538a9e0 3647 radeon_ring_unlock_commit(rdev, ring, false);
3ce0a23d
JG		 3648 for (i = 0; i < rdev->usec_timeout; i++) {
3649 tmp = RREG32(scratch);
3650 if (tmp == 0xDEADBEEF) {
3651 break;
3652 }
3653 DRM_UDELAY(1);
3654 }
3655 if (i < rdev->usec_timeout) {
3656 DRM_INFO("ring test succeeded in %d usecs\n", i);
3657 } else {
369d7ec1 3658 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
3ce0a23d
JG		 3659 scratch, tmp);
3660 r = -EINVAL;
3661 }
3662 radeon_scratch_free(rdev, scratch);
3663 return r;
3664}
3665
3666void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3667{
e32eb50d 3668 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
7b1f2485 3669
c7eff978
AD		 3670 if (ring->rptr_save_reg) {
3671 u32 next_rptr = ring->wptr + 2 + 3;
3672 radeon_ring_write(ring, PACKET0(ring->rptr_save_reg, 0));
3673 radeon_ring_write(ring, next_rptr);
3674 }
3675
e32eb50d
CK		 3676 radeon_ring_write(ring, PACKET0(RADEON_CP_IB_BASE, 1));
3677 radeon_ring_write(ring, ib->gpu_addr);
3678 radeon_ring_write(ring, ib->length_dw);
3ce0a23d
JG		 3679}
3680
f712812e 3681int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
3ce0a23d 3682{
f2e39221 3683 struct radeon_ib ib;
3ce0a23d
JG		 3684 uint32_t scratch;
3685 uint32_t tmp = 0;
3686 unsigned i;
3687 int r;
3688
3689 r = radeon_scratch_get(rdev, &scratch);
3690 if (r) {
3691 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3692 return r;
3693 }
3694 WREG32(scratch, 0xCAFEDEAD);
4bf3dd92 3695 r = radeon_ib_get(rdev, RADEON_RING_TYPE_GFX_INDEX, &ib, NULL, 256);
3ce0a23d 3696 if (r) {
af026c5b
MD		 3697 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
3698 goto free_scratch;
3ce0a23d 3699 }
f2e39221
JG		 3700 ib.ptr[0] = PACKET0(scratch, 0);
3701 ib.ptr[1] = 0xDEADBEEF;
3702 ib.ptr[2] = PACKET2(0);
3703 ib.ptr[3] = PACKET2(0);
3704 ib.ptr[4] = PACKET2(0);
3705 ib.ptr[5] = PACKET2(0);
3706 ib.ptr[6] = PACKET2(0);
3707 ib.ptr[7] = PACKET2(0);
3708 ib.length_dw = 8;
1538a9e0 3709 r = radeon_ib_schedule(rdev, &ib, NULL, false);
3ce0a23d 3710 if (r) {
af026c5b
MD		 3711 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
3712 goto free_ib;
3ce0a23d 3713 }
f2e39221 3714 r = radeon_fence_wait(ib.fence, false);
3ce0a23d 3715 if (r) {
af026c5b
MD		 3716 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
3717 goto free_ib;
3ce0a23d
JG		 3718 }
3719 for (i = 0; i < rdev->usec_timeout; i++) {
3720 tmp = RREG32(scratch);
3721 if (tmp == 0xDEADBEEF) {
3722 break;
3723 }
3724 DRM_UDELAY(1);
3725 }
3726 if (i < rdev->usec_timeout) {
3727 DRM_INFO("ib test succeeded in %u usecs\n", i);
3728 } else {
62f288cf 3729 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
3ce0a23d
JG		 3730 scratch, tmp);
3731 r = -EINVAL;
3732 }
af026c5b 3733free_ib:
3ce0a23d 3734 radeon_ib_free(rdev, &ib);
af026c5b
MD		 3735free_scratch:
3736 radeon_scratch_free(rdev, scratch);
3ce0a23d
JG		 3737 return r;
3738}
9f022ddf 3739
9f022ddf
JG		 3740void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
3741{
3742 /* Shutdown CP we shouldn't need to do that but better be safe than
3743 * sorry
3744 */
e32eb50d 3745 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
9f022ddf
JG		 3746 WREG32(R_000740_CP_CSQ_CNTL, 0);
3747
3748 /* Save few CRTC registers */
ca6ffc64 3749 save->GENMO_WT = RREG8(R_0003C2_GENMO_WT);
9f022ddf
JG		 3750 save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
3751 save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
3752 save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
3753 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3754 save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL);
3755 save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET);
3756 }
3757
3758 /* Disable VGA aperture access */
ca6ffc64 3759 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT);
9f022ddf
JG		 3760 /* Disable cursor, overlay, crtc */
3761 WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1));
3762 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL |
3763 S_000054_CRTC_DISPLAY_DIS(1));
3764 WREG32(R_000050_CRTC_GEN_CNTL,
3765 (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) |
3766 S_000050_CRTC_DISP_REQ_EN_B(1));
3767 WREG32(R_000420_OV0_SCALE_CNTL,
3768 C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL));
3769 WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET);
3770 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3771 WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET |
3772 S_000360_CUR2_LOCK(1));
3773 WREG32(R_0003F8_CRTC2_GEN_CNTL,
3774 (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) |
3775 S_0003F8_CRTC2_DISPLAY_DIS(1) |
3776 S_0003F8_CRTC2_DISP_REQ_EN_B(1));
3777 WREG32(R_000360_CUR2_OFFSET,
3778 C_000360_CUR2_LOCK & save->CUR2_OFFSET);
3779 }
3780}
3781
3782void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save)
3783{
3784 /* Update base address for crtc */
d594e46a 3785 WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
9f022ddf 3786 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
d594e46a 3787 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
9f022ddf
JG		 3788 }
3789 /* Restore CRTC registers */
ca6ffc64 3790 WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);
9f022ddf
JG		 3791 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
3792 WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
3793 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3794 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
3795 }
3796}
ca6ffc64
JG		 3797
3798void r100_vga_render_disable(struct radeon_device *rdev)
3799{
d4550907 3800 u32 tmp;
ca6ffc64 3801
d4550907 3802 tmp = RREG8(R_0003C2_GENMO_WT);
ca6ffc64
JG		 3803 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);
3804}
d4550907
JG		 3805
3806static void r100_debugfs(struct radeon_device *rdev)
3807{
3808 int r;
3809
3810 r = r100_debugfs_mc_info_init(rdev);
3811 if (r)
3812 dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n");
3813}
3814
3815static void r100_mc_program(struct radeon_device *rdev)
3816{
3817 struct r100_mc_save save;
3818
3819 /* Stops all mc clients */
3820 r100_mc_stop(rdev, &save);
3821 if (rdev->flags & RADEON_IS_AGP) {
3822 WREG32(R_00014C_MC_AGP_LOCATION,
3823 S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
3824 S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
3825 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
3826 if (rdev->family > CHIP_RV200)
3827 WREG32(R_00015C_AGP_BASE_2,
3828 upper_32_bits(rdev->mc.agp_base) & 0xff);
3829 } else {
3830 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
3831 WREG32(R_000170_AGP_BASE, 0);
3832 if (rdev->family > CHIP_RV200)
3833 WREG32(R_00015C_AGP_BASE_2, 0);
3834 }
3835 /* Wait for mc idle */
3836 if (r100_mc_wait_for_idle(rdev))
3837 dev_warn(rdev->dev, "Wait for MC idle timeout.\n");
3838 /* Program MC, should be a 32bits limited address space */
3839 WREG32(R_000148_MC_FB_LOCATION,
3840 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
3841 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
3842 r100_mc_resume(rdev, &save);
3843}
3844
1109ca09 3845static void r100_clock_startup(struct radeon_device *rdev)
d4550907
JG		 3846{
3847 u32 tmp;
3848
3849 if (radeon_dynclks != -1 && radeon_dynclks)
3850 radeon_legacy_set_clock_gating(rdev, 1);
3851 /* We need to force on some of the block */
3852 tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
3853 tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
3854 if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280))
3855 tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1);
3856 WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
3857}
3858
3859static int r100_startup(struct radeon_device *rdev)
3860{
3861 int r;
3862
92cde00c
AD		 3863 /* set common regs */
3864 r100_set_common_regs(rdev);
3865 /* program mc */
d4550907
JG		 3866 r100_mc_program(rdev);
3867 /* Resume clock */
3868 r100_clock_startup(rdev);
d4550907
JG		 3869 /* Initialize GART (initialize after TTM so we can allocate
3870 * memory through TTM but finalize after TTM) */
17e15b0c 3871 r100_enable_bm(rdev);
d4550907
JG		 3872 if (rdev->flags & RADEON_IS_PCI) {
3873 r = r100_pci_gart_enable(rdev);
3874 if (r)
3875 return r;
3876 }
724c80e1
AD		 3877
3878 /* allocate wb buffer */
3879 r = radeon_wb_init(rdev);
3880 if (r)
3881 return r;
3882
30eb77f4
JG		 3883 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
3884 if (r) {
3885 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
3886 return r;
3887 }
3888
d4550907 3889 /* Enable IRQ */
e49f3959
AH		 3890 if (!rdev->irq.installed) {
3891 r = radeon_irq_kms_init(rdev);
3892 if (r)
3893 return r;
3894 }
3895
d4550907 3896 r100_irq_set(rdev);
cafe6609 3897 rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
d4550907
JG		 3898 /* 1M ring buffer */
3899 r = r100_cp_init(rdev, 1024 * 1024);
3900 if (r) {
ec4f2ac4 3901 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
d4550907
JG		 3902 return r;
3903 }
b15ba512 3904
2898c348
CK		 3905 r = radeon_ib_pool_init(rdev);
3906 if (r) {
3907 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
b15ba512 3908 return r;
2898c348 3909 }
b15ba512 3910
d4550907
JG		 3911 return 0;
3912}
3913
3914int r100_resume(struct radeon_device *rdev)
3915{
6b7746e8
JG		 3916 int r;
3917
d4550907
JG		 3918 /* Make sur GART are not working */
3919 if (rdev->flags & RADEON_IS_PCI)
3920 r100_pci_gart_disable(rdev);
3921 /* Resume clock before doing reset */
3922 r100_clock_startup(rdev);
3923 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
a2d07b74 3924 if (radeon_asic_reset(rdev)) {
d4550907
JG		 3925 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3926 RREG32(R_000E40_RBBM_STATUS),
3927 RREG32(R_0007C0_CP_STAT));
3928 }
3929 /* post */
3930 radeon_combios_asic_init(rdev->ddev);
3931 /* Resume clock after posting */
3932 r100_clock_startup(rdev);
550e2d92
DA		 3933 /* Initialize surface registers */
3934 radeon_surface_init(rdev);
b15ba512
JG		 3935
3936 rdev->accel_working = true;
6b7746e8
JG		 3937 r = r100_startup(rdev);
3938 if (r) {
3939 rdev->accel_working = false;
3940 }
3941 return r;
d4550907
JG		 3942}
3943
3944int r100_suspend(struct radeon_device *rdev)
3945{
6c7bccea 3946 radeon_pm_suspend(rdev);
d4550907 3947 r100_cp_disable(rdev);
724c80e1 3948 radeon_wb_disable(rdev);
d4550907
JG		 3949 r100_irq_disable(rdev);
3950 if (rdev->flags & RADEON_IS_PCI)
3951 r100_pci_gart_disable(rdev);
3952 return 0;
3953}
3954
3955void r100_fini(struct radeon_device *rdev)
3956{
6c7bccea 3957 radeon_pm_fini(rdev);
d4550907 3958 r100_cp_fini(rdev);
724c80e1 3959 radeon_wb_fini(rdev);
2898c348 3960 radeon_ib_pool_fini(rdev);
d4550907
JG		 3961 radeon_gem_fini(rdev);
3962 if (rdev->flags & RADEON_IS_PCI)
3963 r100_pci_gart_fini(rdev);
d0269ed8 3964 radeon_agp_fini(rdev);
d4550907
JG		 3965 radeon_irq_kms_fini(rdev);
3966 radeon_fence_driver_fini(rdev);
4c788679 3967 radeon_bo_fini(rdev);
d4550907
JG		 3968 radeon_atombios_fini(rdev);
3969 kfree(rdev->bios);
3970 rdev->bios = NULL;
3971}
3972
4c712e6c
DA		 3973/*
3974 * Due to how kexec works, it can leave the hw fully initialised when it
3975 * boots the new kernel. However doing our init sequence with the CP and
3976 * WB stuff setup causes GPU hangs on the RN50 at least. So at startup
3977 * do some quick sanity checks and restore sane values to avoid this
3978 * problem.
3979 */
3980void r100_restore_sanity(struct radeon_device *rdev)
3981{
3982 u32 tmp;
3983
3984 tmp = RREG32(RADEON_CP_CSQ_CNTL);
3985 if (tmp) {
3986 WREG32(RADEON_CP_CSQ_CNTL, 0);
3987 }
3988 tmp = RREG32(RADEON_CP_RB_CNTL);
3989 if (tmp) {
3990 WREG32(RADEON_CP_RB_CNTL, 0);
3991 }
3992 tmp = RREG32(RADEON_SCRATCH_UMSK);
3993 if (tmp) {
3994 WREG32(RADEON_SCRATCH_UMSK, 0);
3995 }
3996}
3997
d4550907
JG		 3998int r100_init(struct radeon_device *rdev)
3999{
4000 int r;
4001
d4550907
JG		 4002 /* Register debugfs file specific to this group of asics */
4003 r100_debugfs(rdev);
4004 /* Disable VGA */
4005 r100_vga_render_disable(rdev);
4006 /* Initialize scratch registers */
4007 radeon_scratch_init(rdev);
4008 /* Initialize surface registers */
4009 radeon_surface_init(rdev);
4c712e6c
DA		 4010 /* sanity check some register to avoid hangs like after kexec */
4011 r100_restore_sanity(rdev);
d4550907
JG		 4012 /* TODO: disable VGA need to use VGA request */
4013 /* BIOS*/
4014 if (!radeon_get_bios(rdev)) {
4015 if (ASIC_IS_AVIVO(rdev))
4016 return -EINVAL;
4017 }
4018 if (rdev->is_atom_bios) {
4019 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
4020 return -EINVAL;
4021 } else {
4022 r = radeon_combios_init(rdev);
4023 if (r)
4024 return r;
4025 }
4026 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
a2d07b74 4027 if (radeon_asic_reset(rdev)) {
d4550907
JG		 4028 dev_warn(rdev->dev,
4029 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
4030 RREG32(R_000E40_RBBM_STATUS),
4031 RREG32(R_0007C0_CP_STAT));
4032 }
4033 /* check if cards are posted or not */
72542d77
DA		 4034 if (radeon_boot_test_post_card(rdev) == false)
4035 return -EINVAL;
d4550907
JG		 4036 /* Set asic errata */
4037 r100_errata(rdev);
4038 /* Initialize clocks */
4039 radeon_get_clock_info(rdev->ddev);
d594e46a
JG		 4040 /* initialize AGP */
4041 if (rdev->flags & RADEON_IS_AGP) {
4042 r = radeon_agp_init(rdev);
4043 if (r) {
4044 radeon_agp_disable(rdev);
4045 }
4046 }
4047 /* initialize VRAM */
4048 r100_mc_init(rdev);
d4550907 4049 /* Fence driver */
30eb77f4 4050 r = radeon_fence_driver_init(rdev);
d4550907
JG		 4051 if (r)
4052 return r;
d4550907 4053 /* Memory manager */
4c788679 4054 r = radeon_bo_init(rdev);
d4550907
JG		 4055 if (r)
4056 return r;
4057 if (rdev->flags & RADEON_IS_PCI) {
4058 r = r100_pci_gart_init(rdev);
4059 if (r)
4060 return r;
4061 }
4062 r100_set_safe_registers(rdev);
b15ba512 4063
6c7bccea
AD		 4064 /* Initialize power management */
4065 radeon_pm_init(rdev);
4066
d4550907
JG		 4067 rdev->accel_working = true;
4068 r = r100_startup(rdev);
4069 if (r) {
4070 /* Somethings want wront with the accel init stop accel */
4071 dev_err(rdev->dev, "Disabling GPU acceleration\n");
d4550907 4072 r100_cp_fini(rdev);
724c80e1 4073 radeon_wb_fini(rdev);
2898c348 4074 radeon_ib_pool_fini(rdev);
655efd3d 4075 radeon_irq_kms_fini(rdev);
d4550907
JG		 4076 if (rdev->flags & RADEON_IS_PCI)
4077 r100_pci_gart_fini(rdev);
d4550907
JG		 4078 rdev->accel_working = false;
4079 }
4080 return 0;
4081}
6fcbef7a 4082
6fcbef7a
AK		 4083u32 r100_io_rreg(struct radeon_device *rdev, u32 reg)
4084{
4085 if (reg < rdev->rio_mem_size)
4086 return ioread32(rdev->rio_mem + reg);
4087 else {
4088 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
4089 return ioread32(rdev->rio_mem + RADEON_MM_DATA);
4090 }
4091}
4092
4093void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v)
4094{
4095 if (reg < rdev->rio_mem_size)
4096 iowrite32(v, rdev->rio_mem + reg);
4097 else {
4098 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
4099 iowrite32(v, rdev->rio_mem + RADEON_MM_DATA);
4100 }
4101}
Linux kernel - Deliverables
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