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gpu: add module.h to drivers/gpu files as required.
[deliverable/linux.git] / drivers / gpu / drm / radeon / r100.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#include <linux/seq_file.h>
5a0e3ad6 29#include <linux/slab.h>
771fe6b9
JG		 30#include "drmP.h"
31#include "drm.h"
32#include "radeon_drm.h"
771fe6b9
JG		 33#include "radeon_reg.h"
34#include "radeon.h"
e6990375 35#include "radeon_asic.h"
3ce0a23d 36#include "r100d.h"
d4550907
JG		 37#include "rs100d.h"
38#include "rv200d.h"
39#include "rv250d.h"
49e02b73 40#include "atom.h"
3ce0a23d 41
70967ab9
BH		 42#include <linux/firmware.h>
43#include <linux/platform_device.h>
e0cd3608 44#include <linux/module.h>
70967ab9 45
551ebd83
DA		 46#include "r100_reg_safe.h"
47#include "rn50_reg_safe.h"
48
70967ab9
BH		 49/* Firmware Names */
50#define FIRMWARE_R100 "radeon/R100_cp.bin"
51#define FIRMWARE_R200 "radeon/R200_cp.bin"
52#define FIRMWARE_R300 "radeon/R300_cp.bin"
53#define FIRMWARE_R420 "radeon/R420_cp.bin"
54#define FIRMWARE_RS690 "radeon/RS690_cp.bin"
55#define FIRMWARE_RS600 "radeon/RS600_cp.bin"
56#define FIRMWARE_R520 "radeon/R520_cp.bin"
57
58MODULE_FIRMWARE(FIRMWARE_R100);
59MODULE_FIRMWARE(FIRMWARE_R200);
60MODULE_FIRMWARE(FIRMWARE_R300);
61MODULE_FIRMWARE(FIRMWARE_R420);
62MODULE_FIRMWARE(FIRMWARE_RS690);
63MODULE_FIRMWARE(FIRMWARE_RS600);
64MODULE_FIRMWARE(FIRMWARE_R520);
771fe6b9 65
551ebd83
DA		 66#include "r100_track.h"
67
771fe6b9
JG		 68/* This files gather functions specifics to:
69 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
771fe6b9 70 */
771fe6b9 71
cbdd4501
AK		 72int r100_reloc_pitch_offset(struct radeon_cs_parser *p,
73 struct radeon_cs_packet *pkt,
74 unsigned idx,
75 unsigned reg)
76{
77 int r;
78 u32 tile_flags = 0;
79 u32 tmp;
80 struct radeon_cs_reloc *reloc;
81 u32 value;
82
83 r = r100_cs_packet_next_reloc(p, &reloc);
84 if (r) {
85 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
86 idx, reg);
87 r100_cs_dump_packet(p, pkt);
88 return r;
89 }
90 value = radeon_get_ib_value(p, idx);
91 tmp = value & 0x003fffff;
92 tmp += (((u32)reloc->lobj.gpu_offset) >> 10);
93
94 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
95 tile_flags |= RADEON_DST_TILE_MACRO;
96 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
97 if (reg == RADEON_SRC_PITCH_OFFSET) {
98 DRM_ERROR("Cannot src blit from microtiled surface\n");
99 r100_cs_dump_packet(p, pkt);
100 return -EINVAL;
101 }
102 tile_flags |= RADEON_DST_TILE_MICRO;
103 }
104
105 tmp |= tile_flags;
106 p->ib->ptr[idx] = (value & 0x3fc00000) | tmp;
107 return 0;
108}
109
110int r100_packet3_load_vbpntr(struct radeon_cs_parser *p,
111 struct radeon_cs_packet *pkt,
112 int idx)
113{
114 unsigned c, i;
115 struct radeon_cs_reloc *reloc;
116 struct r100_cs_track *track;
117 int r = 0;
118 volatile uint32_t *ib;
119 u32 idx_value;
120
121 ib = p->ib->ptr;
122 track = (struct r100_cs_track *)p->track;
123 c = radeon_get_ib_value(p, idx++) & 0x1F;
124 if (c > 16) {
125 DRM_ERROR("Only 16 vertex buffers are allowed %d\n",
126 pkt->opcode);
127 r100_cs_dump_packet(p, pkt);
128 return -EINVAL;
129 }
130 track->num_arrays = c;
131 for (i = 0; i < (c - 1); i+=2, idx+=3) {
132 r = r100_cs_packet_next_reloc(p, &reloc);
133 if (r) {
134 DRM_ERROR("No reloc for packet3 %d\n",
135 pkt->opcode);
136 r100_cs_dump_packet(p, pkt);
137 return r;
138 }
139 idx_value = radeon_get_ib_value(p, idx);
140 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
141
142 track->arrays[i + 0].esize = idx_value >> 8;
143 track->arrays[i + 0].robj = reloc->robj;
144 track->arrays[i + 0].esize &= 0x7F;
145 r = r100_cs_packet_next_reloc(p, &reloc);
146 if (r) {
147 DRM_ERROR("No reloc for packet3 %d\n",
148 pkt->opcode);
149 r100_cs_dump_packet(p, pkt);
150 return r;
151 }
152 ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->lobj.gpu_offset);
153 track->arrays[i + 1].robj = reloc->robj;
154 track->arrays[i + 1].esize = idx_value >> 24;
155 track->arrays[i + 1].esize &= 0x7F;
156 }
157 if (c & 1) {
158 r = r100_cs_packet_next_reloc(p, &reloc);
159 if (r) {
160 DRM_ERROR("No reloc for packet3 %d\n",
161 pkt->opcode);
162 r100_cs_dump_packet(p, pkt);
163 return r;
164 }
165 idx_value = radeon_get_ib_value(p, idx);
166 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
167 track->arrays[i + 0].robj = reloc->robj;
168 track->arrays[i + 0].esize = idx_value >> 8;
169 track->arrays[i + 0].esize &= 0x7F;
170 }
171 return r;
172}
173
6f34be50
AD		 174void r100_pre_page_flip(struct radeon_device *rdev, int crtc)
175{
6f34be50
AD		 176 /* enable the pflip int */
177 radeon_irq_kms_pflip_irq_get(rdev, crtc);
178}
179
180void r100_post_page_flip(struct radeon_device *rdev, int crtc)
181{
182 /* disable the pflip int */
183 radeon_irq_kms_pflip_irq_put(rdev, crtc);
184}
185
186u32 r100_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
187{
188 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
189 u32 tmp = ((u32)crtc_base) | RADEON_CRTC_OFFSET__OFFSET_LOCK;
190
191 /* Lock the graphics update lock */
192 /* update the scanout addresses */
193 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
194
acb32506
AD		 195 /* Wait for update_pending to go high. */
196 while (!(RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET));
197 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
6f34be50
AD		 198
199 /* Unlock the lock, so double-buffering can take place inside vblank */
200 tmp &= ~RADEON_CRTC_OFFSET__OFFSET_LOCK;
201 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
202
203 /* Return current update_pending status: */
204 return RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET;
205}
206
ce8f5370 207void r100_pm_get_dynpm_state(struct radeon_device *rdev)
a48b9b4e
AD		 208{
209 int i;
ce8f5370
AD		 210 rdev->pm.dynpm_can_upclock = true;
211 rdev->pm.dynpm_can_downclock = true;
a48b9b4e 212
ce8f5370
AD		 213 switch (rdev->pm.dynpm_planned_action) {
214 case DYNPM_ACTION_MINIMUM:
a48b9b4e 215 rdev->pm.requested_power_state_index = 0;
ce8f5370 216 rdev->pm.dynpm_can_downclock = false;
a48b9b4e 217 break;
ce8f5370 218 case DYNPM_ACTION_DOWNCLOCK:
a48b9b4e
AD		 219 if (rdev->pm.current_power_state_index == 0) {
220 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
ce8f5370 221 rdev->pm.dynpm_can_downclock = false;
a48b9b4e
AD		 222 } else {
223 if (rdev->pm.active_crtc_count > 1) {
224 for (i = 0; i < rdev->pm.num_power_states; i++) {
d7311171 225 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
a48b9b4e
AD		 226 continue;
227 else if (i >= rdev->pm.current_power_state_index) {
228 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
229 break;
230 } else {
231 rdev->pm.requested_power_state_index = i;
232 break;
233 }
234 }
235 } else
236 rdev->pm.requested_power_state_index =
237 rdev->pm.current_power_state_index - 1;
238 }
d7311171
AD		 239 /* don't use the power state if crtcs are active and no display flag is set */
240 if ((rdev->pm.active_crtc_count > 0) &&
241 (rdev->pm.power_state[rdev->pm.requested_power_state_index].clock_info[0].flags &
242 RADEON_PM_MODE_NO_DISPLAY)) {
243 rdev->pm.requested_power_state_index++;
244 }
a48b9b4e 245 break;
ce8f5370 246 case DYNPM_ACTION_UPCLOCK:
a48b9b4e
AD		 247 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
248 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
ce8f5370 249 rdev->pm.dynpm_can_upclock = false;
a48b9b4e
AD		 250 } else {
251 if (rdev->pm.active_crtc_count > 1) {
252 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
d7311171 253 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
a48b9b4e
AD		 254 continue;
255 else if (i <= rdev->pm.current_power_state_index) {
256 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
257 break;
258 } else {
259 rdev->pm.requested_power_state_index = i;
260 break;
261 }
262 }
263 } else
264 rdev->pm.requested_power_state_index =
265 rdev->pm.current_power_state_index + 1;
266 }
267 break;
ce8f5370 268 case DYNPM_ACTION_DEFAULT:
58e21dff 269 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
ce8f5370 270 rdev->pm.dynpm_can_upclock = false;
58e21dff 271 break;
ce8f5370 272 case DYNPM_ACTION_NONE:
a48b9b4e
AD		 273 default:
274 DRM_ERROR("Requested mode for not defined action\n");
275 return;
276 }
277 /* only one clock mode per power state */
278 rdev->pm.requested_clock_mode_index = 0;
279
d9fdaafb 280 DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
ce8a3eb2
AD		 281 rdev->pm.power_state[rdev->pm.requested_power_state_index].
282 clock_info[rdev->pm.requested_clock_mode_index].sclk,
283 rdev->pm.power_state[rdev->pm.requested_power_state_index].
284 clock_info[rdev->pm.requested_clock_mode_index].mclk,
285 rdev->pm.power_state[rdev->pm.requested_power_state_index].
286 pcie_lanes);
a48b9b4e
AD		 287}
288
ce8f5370
AD		 289void r100_pm_init_profile(struct radeon_device *rdev)
290{
291 /* default */
292 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
293 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
294 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
295 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
296 /* low sh */
297 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
298 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
299 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
300 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 301 /* mid sh */
302 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
303 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
304 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
305 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 306 /* high sh */
307 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
308 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
309 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
310 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
311 /* low mh */
312 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
313 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
314 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
315 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 316 /* mid mh */
317 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
318 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
319 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
320 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 321 /* high mh */
322 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
323 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
324 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
325 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
bae6b562
AD		 326}
327
49e02b73
AD		 328void r100_pm_misc(struct radeon_device *rdev)
329{
49e02b73
AD		 330 int requested_index = rdev->pm.requested_power_state_index;
331 struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
332 struct radeon_voltage *voltage = &ps->clock_info[0].voltage;
333 u32 tmp, sclk_cntl, sclk_cntl2, sclk_more_cntl;
334
335 if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) {
336 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
337 tmp = RREG32(voltage->gpio.reg);
338 if (voltage->active_high)
339 tmp |= voltage->gpio.mask;
340 else
341 tmp &= ~(voltage->gpio.mask);
342 WREG32(voltage->gpio.reg, tmp);
343 if (voltage->delay)
344 udelay(voltage->delay);
345 } else {
346 tmp = RREG32(voltage->gpio.reg);
347 if (voltage->active_high)
348 tmp &= ~voltage->gpio.mask;
349 else
350 tmp |= voltage->gpio.mask;
351 WREG32(voltage->gpio.reg, tmp);
352 if (voltage->delay)
353 udelay(voltage->delay);
354 }
355 }
356
357 sclk_cntl = RREG32_PLL(SCLK_CNTL);
358 sclk_cntl2 = RREG32_PLL(SCLK_CNTL2);
359 sclk_cntl2 &= ~REDUCED_SPEED_SCLK_SEL(3);
360 sclk_more_cntl = RREG32_PLL(SCLK_MORE_CNTL);
361 sclk_more_cntl &= ~VOLTAGE_DELAY_SEL(3);
362 if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) {
363 sclk_more_cntl |= REDUCED_SPEED_SCLK_EN;
364 if (ps->misc & ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE)
365 sclk_cntl2 |= REDUCED_SPEED_SCLK_MODE;
366 else
367 sclk_cntl2 &= ~REDUCED_SPEED_SCLK_MODE;
368 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2)
369 sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(0);
370 else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4)
371 sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(2);
372 } else
373 sclk_more_cntl &= ~REDUCED_SPEED_SCLK_EN;
374
375 if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) {
376 sclk_more_cntl |= IO_CG_VOLTAGE_DROP;
377 if (voltage->delay) {
378 sclk_more_cntl |= VOLTAGE_DROP_SYNC;
379 switch (voltage->delay) {
380 case 33:
381 sclk_more_cntl |= VOLTAGE_DELAY_SEL(0);
382 break;
383 case 66:
384 sclk_more_cntl |= VOLTAGE_DELAY_SEL(1);
385 break;
386 case 99:
387 sclk_more_cntl |= VOLTAGE_DELAY_SEL(2);
388 break;
389 case 132:
390 sclk_more_cntl |= VOLTAGE_DELAY_SEL(3);
391 break;
392 }
393 } else
394 sclk_more_cntl &= ~VOLTAGE_DROP_SYNC;
395 } else
396 sclk_more_cntl &= ~IO_CG_VOLTAGE_DROP;
397
398 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN)
399 sclk_cntl &= ~FORCE_HDP;
400 else
401 sclk_cntl |= FORCE_HDP;
402
403 WREG32_PLL(SCLK_CNTL, sclk_cntl);
404 WREG32_PLL(SCLK_CNTL2, sclk_cntl2);
405 WREG32_PLL(SCLK_MORE_CNTL, sclk_more_cntl);
406
407 /* set pcie lanes */
408 if ((rdev->flags & RADEON_IS_PCIE) &&
409 !(rdev->flags & RADEON_IS_IGP) &&
410 rdev->asic->set_pcie_lanes &&
411 (ps->pcie_lanes !=
412 rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {
413 radeon_set_pcie_lanes(rdev,
414 ps->pcie_lanes);
d9fdaafb 415 DRM_DEBUG_DRIVER("Setting: p: %d\n", ps->pcie_lanes);
49e02b73 416 }
49e02b73
AD		 417}
418
419void r100_pm_prepare(struct radeon_device *rdev)
420{
421 struct drm_device *ddev = rdev->ddev;
422 struct drm_crtc *crtc;
423 struct radeon_crtc *radeon_crtc;
424 u32 tmp;
425
426 /* disable any active CRTCs */
427 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
428 radeon_crtc = to_radeon_crtc(crtc);
429 if (radeon_crtc->enabled) {
430 if (radeon_crtc->crtc_id) {
431 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
432 tmp |= RADEON_CRTC2_DISP_REQ_EN_B;
433 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
434 } else {
435 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
436 tmp |= RADEON_CRTC_DISP_REQ_EN_B;
437 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
438 }
439 }
440 }
441}
442
443void r100_pm_finish(struct radeon_device *rdev)
444{
445 struct drm_device *ddev = rdev->ddev;
446 struct drm_crtc *crtc;
447 struct radeon_crtc *radeon_crtc;
448 u32 tmp;
449
450 /* enable any active CRTCs */
451 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
452 radeon_crtc = to_radeon_crtc(crtc);
453 if (radeon_crtc->enabled) {
454 if (radeon_crtc->crtc_id) {
455 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
456 tmp &= ~RADEON_CRTC2_DISP_REQ_EN_B;
457 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
458 } else {
459 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
460 tmp &= ~RADEON_CRTC_DISP_REQ_EN_B;
461 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
462 }
463 }
464 }
465}
466
def9ba9c
AD		 467bool r100_gui_idle(struct radeon_device *rdev)
468{
469 if (RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE)
470 return false;
471 else
472 return true;
473}
474
05a05c50
AD		 475/* hpd for digital panel detect/disconnect */
476bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
477{
478 bool connected = false;
479
480 switch (hpd) {
481 case RADEON_HPD_1:
482 if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE)
483 connected = true;
484 break;
485 case RADEON_HPD_2:
486 if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE)
487 connected = true;
488 break;
489 default:
490 break;
491 }
492 return connected;
493}
494
495void r100_hpd_set_polarity(struct radeon_device *rdev,
496 enum radeon_hpd_id hpd)
497{
498 u32 tmp;
499 bool connected = r100_hpd_sense(rdev, hpd);
500
501 switch (hpd) {
502 case RADEON_HPD_1:
503 tmp = RREG32(RADEON_FP_GEN_CNTL);
504 if (connected)
505 tmp &= ~RADEON_FP_DETECT_INT_POL;
506 else
507 tmp |= RADEON_FP_DETECT_INT_POL;
508 WREG32(RADEON_FP_GEN_CNTL, tmp);
509 break;
510 case RADEON_HPD_2:
511 tmp = RREG32(RADEON_FP2_GEN_CNTL);
512 if (connected)
513 tmp &= ~RADEON_FP2_DETECT_INT_POL;
514 else
515 tmp |= RADEON_FP2_DETECT_INT_POL;
516 WREG32(RADEON_FP2_GEN_CNTL, tmp);
517 break;
518 default:
519 break;
520 }
521}
522
523void r100_hpd_init(struct radeon_device *rdev)
524{
525 struct drm_device *dev = rdev->ddev;
526 struct drm_connector *connector;
527
528 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
529 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
530 switch (radeon_connector->hpd.hpd) {
531 case RADEON_HPD_1:
532 rdev->irq.hpd[0] = true;
533 break;
534 case RADEON_HPD_2:
535 rdev->irq.hpd[1] = true;
536 break;
537 default:
538 break;
539 }
540 }
003e69f9
JG		 541 if (rdev->irq.installed)
542 r100_irq_set(rdev);
05a05c50
AD		 543}
544
545void r100_hpd_fini(struct radeon_device *rdev)
546{
547 struct drm_device *dev = rdev->ddev;
548 struct drm_connector *connector;
549
550 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
551 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
552 switch (radeon_connector->hpd.hpd) {
553 case RADEON_HPD_1:
554 rdev->irq.hpd[0] = false;
555 break;
556 case RADEON_HPD_2:
557 rdev->irq.hpd[1] = false;
558 break;
559 default:
560 break;
561 }
562 }
563}
564
771fe6b9
JG		 565/*
566 * PCI GART
567 */
568void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
569{
570 /* TODO: can we do somethings here ? */
571 /* It seems hw only cache one entry so we should discard this
572 * entry otherwise if first GPU GART read hit this entry it
573 * could end up in wrong address. */
574}
575
4aac0473 576int r100_pci_gart_init(struct radeon_device *rdev)
771fe6b9 577{
771fe6b9
JG		 578 int r;
579
4aac0473 580 if (rdev->gart.table.ram.ptr) {
fce7d61b 581 WARN(1, "R100 PCI GART already initialized\n");
4aac0473
JG		 582 return 0;
583 }
771fe6b9
JG		 584 /* Initialize common gart structure */
585 r = radeon_gart_init(rdev);
4aac0473 586 if (r)
771fe6b9 587 return r;
4aac0473
JG		 588 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
589 rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
590 rdev->asic->gart_set_page = &r100_pci_gart_set_page;
591 return radeon_gart_table_ram_alloc(rdev);
592}
593
17e15b0c
DA		 594/* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
595void r100_enable_bm(struct radeon_device *rdev)
596{
597 uint32_t tmp;
598 /* Enable bus mastering */
599 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
600 WREG32(RADEON_BUS_CNTL, tmp);
601}
602
4aac0473
JG		 603int r100_pci_gart_enable(struct radeon_device *rdev)
604{
605 uint32_t tmp;
606
82568565 607 radeon_gart_restore(rdev);
771fe6b9
JG		 608 /* discard memory request outside of configured range */
609 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
610 WREG32(RADEON_AIC_CNTL, tmp);
611 /* set address range for PCI address translate */
d594e46a
JG		 612 WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start);
613 WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end);
771fe6b9
JG		 614 /* set PCI GART page-table base address */
615 WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
616 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
617 WREG32(RADEON_AIC_CNTL, tmp);
618 r100_pci_gart_tlb_flush(rdev);
fcf4de5a
TV		 619 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
620 (unsigned)(rdev->mc.gtt_size >> 20),
621 (unsigned long long)rdev->gart.table_addr);
771fe6b9
JG		 622 rdev->gart.ready = true;
623 return 0;
624}
625
626void r100_pci_gart_disable(struct radeon_device *rdev)
627{
628 uint32_t tmp;
629
630 /* discard memory request outside of configured range */
631 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
632 WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
633 WREG32(RADEON_AIC_LO_ADDR, 0);
634 WREG32(RADEON_AIC_HI_ADDR, 0);
635}
636
637int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
638{
639 if (i < 0 || i > rdev->gart.num_gpu_pages) {
640 return -EINVAL;
641 }
ed10f95d 642 rdev->gart.table.ram.ptr[i] = cpu_to_le32(lower_32_bits(addr));
771fe6b9
JG		 643 return 0;
644}
645
4aac0473 646void r100_pci_gart_fini(struct radeon_device *rdev)
771fe6b9 647{
f9274562 648 radeon_gart_fini(rdev);
4aac0473
JG		 649 r100_pci_gart_disable(rdev);
650 radeon_gart_table_ram_free(rdev);
771fe6b9
JG		 651}
652
7ed220d7
MD		 653int r100_irq_set(struct radeon_device *rdev)
654{
655 uint32_t tmp = 0;
656
003e69f9 657 if (!rdev->irq.installed) {
fce7d61b 658 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
003e69f9
JG		 659 WREG32(R_000040_GEN_INT_CNTL, 0);
660 return -EINVAL;
661 }
7ed220d7
MD		 662 if (rdev->irq.sw_int) {
663 tmp |= RADEON_SW_INT_ENABLE;
664 }
2031f77c
AD		 665 if (rdev->irq.gui_idle) {
666 tmp |= RADEON_GUI_IDLE_MASK;
667 }
6f34be50
AD		 668 if (rdev->irq.crtc_vblank_int[0] ||
669 rdev->irq.pflip[0]) {
7ed220d7
MD		 670 tmp |= RADEON_CRTC_VBLANK_MASK;
671 }
6f34be50
AD		 672 if (rdev->irq.crtc_vblank_int[1] ||
673 rdev->irq.pflip[1]) {
7ed220d7
MD		 674 tmp |= RADEON_CRTC2_VBLANK_MASK;
675 }
05a05c50
AD		 676 if (rdev->irq.hpd[0]) {
677 tmp |= RADEON_FP_DETECT_MASK;
678 }
679 if (rdev->irq.hpd[1]) {
680 tmp |= RADEON_FP2_DETECT_MASK;
681 }
7ed220d7
MD		 682 WREG32(RADEON_GEN_INT_CNTL, tmp);
683 return 0;
684}
685
9f022ddf
JG		 686void r100_irq_disable(struct radeon_device *rdev)
687{
688 u32 tmp;
689
690 WREG32(R_000040_GEN_INT_CNTL, 0);
691 /* Wait and acknowledge irq */
692 mdelay(1);
693 tmp = RREG32(R_000044_GEN_INT_STATUS);
694 WREG32(R_000044_GEN_INT_STATUS, tmp);
695}
696
cbdd4501 697static uint32_t r100_irq_ack(struct radeon_device *rdev)
7ed220d7
MD		 698{
699 uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
05a05c50
AD		 700 uint32_t irq_mask = RADEON_SW_INT_TEST |
701 RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT |
702 RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT;
7ed220d7 703
2031f77c
AD		 704 /* the interrupt works, but the status bit is permanently asserted */
705 if (rdev->irq.gui_idle && radeon_gui_idle(rdev)) {
706 if (!rdev->irq.gui_idle_acked)
707 irq_mask |= RADEON_GUI_IDLE_STAT;
708 }
709
7ed220d7
MD		 710 if (irqs) {
711 WREG32(RADEON_GEN_INT_STATUS, irqs);
712 }
713 return irqs & irq_mask;
714}
715
716int r100_irq_process(struct radeon_device *rdev)
717{
3e5cb98d 718 uint32_t status, msi_rearm;
d4877cf2 719 bool queue_hotplug = false;
7ed220d7 720
2031f77c
AD		 721 /* reset gui idle ack. the status bit is broken */
722 rdev->irq.gui_idle_acked = false;
723
7ed220d7
MD		 724 status = r100_irq_ack(rdev);
725 if (!status) {
726 return IRQ_NONE;
727 }
a513c184
JG		 728 if (rdev->shutdown) {
729 return IRQ_NONE;
730 }
7ed220d7
MD		 731 while (status) {
732 /* SW interrupt */
733 if (status & RADEON_SW_INT_TEST) {
734 radeon_fence_process(rdev);
735 }
2031f77c
AD		 736 /* gui idle interrupt */
737 if (status & RADEON_GUI_IDLE_STAT) {
738 rdev->irq.gui_idle_acked = true;
739 rdev->pm.gui_idle = true;
740 wake_up(&rdev->irq.idle_queue);
741 }
7ed220d7
MD		 742 /* Vertical blank interrupts */
743 if (status & RADEON_CRTC_VBLANK_STAT) {
6f34be50
AD		 744 if (rdev->irq.crtc_vblank_int[0]) {
745 drm_handle_vblank(rdev->ddev, 0);
746 rdev->pm.vblank_sync = true;
747 wake_up(&rdev->irq.vblank_queue);
748 }
3e4ea742
MK		 749 if (rdev->irq.pflip[0])
750 radeon_crtc_handle_flip(rdev, 0);
7ed220d7
MD		 751 }
752 if (status & RADEON_CRTC2_VBLANK_STAT) {
6f34be50
AD		 753 if (rdev->irq.crtc_vblank_int[1]) {
754 drm_handle_vblank(rdev->ddev, 1);
755 rdev->pm.vblank_sync = true;
756 wake_up(&rdev->irq.vblank_queue);
757 }
3e4ea742
MK		 758 if (rdev->irq.pflip[1])
759 radeon_crtc_handle_flip(rdev, 1);
7ed220d7 760 }
05a05c50 761 if (status & RADEON_FP_DETECT_STAT) {
d4877cf2
AD		 762 queue_hotplug = true;
763 DRM_DEBUG("HPD1\n");
05a05c50
AD		 764 }
765 if (status & RADEON_FP2_DETECT_STAT) {
d4877cf2
AD		 766 queue_hotplug = true;
767 DRM_DEBUG("HPD2\n");
05a05c50 768 }
7ed220d7
MD		 769 status = r100_irq_ack(rdev);
770 }
2031f77c
AD		 771 /* reset gui idle ack. the status bit is broken */
772 rdev->irq.gui_idle_acked = false;
d4877cf2 773 if (queue_hotplug)
32c87fca 774 schedule_work(&rdev->hotplug_work);
3e5cb98d
AD		 775 if (rdev->msi_enabled) {
776 switch (rdev->family) {
777 case CHIP_RS400:
778 case CHIP_RS480:
779 msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM;
780 WREG32(RADEON_AIC_CNTL, msi_rearm);
781 WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM);
782 break;
783 default:
784 msi_rearm = RREG32(RADEON_MSI_REARM_EN) & ~RV370_MSI_REARM_EN;
785 WREG32(RADEON_MSI_REARM_EN, msi_rearm);
786 WREG32(RADEON_MSI_REARM_EN, msi_rearm | RV370_MSI_REARM_EN);
787 break;
788 }
789 }
7ed220d7
MD		 790 return IRQ_HANDLED;
791}
792
793u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
794{
795 if (crtc == 0)
796 return RREG32(RADEON_CRTC_CRNT_FRAME);
797 else
798 return RREG32(RADEON_CRTC2_CRNT_FRAME);
799}
800
9e5b2af7
PN		 801/* Who ever call radeon_fence_emit should call ring_lock and ask
802 * for enough space (today caller are ib schedule and buffer move) */
771fe6b9
JG		 803void r100_fence_ring_emit(struct radeon_device *rdev,
804 struct radeon_fence *fence)
805{
9e5b2af7
PN		 806 /* We have to make sure that caches are flushed before
807 * CPU might read something from VRAM. */
808 radeon_ring_write(rdev, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));
809 radeon_ring_write(rdev, RADEON_RB3D_DC_FLUSH_ALL);
810 radeon_ring_write(rdev, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));
811 radeon_ring_write(rdev, RADEON_RB3D_ZC_FLUSH_ALL);
771fe6b9 812 /* Wait until IDLE & CLEAN */
4612dc97
AD		 813 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
814 radeon_ring_write(rdev, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
cafe6609
JG		 815 radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
816 radeon_ring_write(rdev, rdev->config.r100.hdp_cntl |
817 RADEON_HDP_READ_BUFFER_INVALIDATE);
818 radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
819 radeon_ring_write(rdev, rdev->config.r100.hdp_cntl);
771fe6b9
JG		 820 /* Emit fence sequence & fire IRQ */
821 radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
822 radeon_ring_write(rdev, fence->seq);
823 radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0));
824 radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
825}
826
771fe6b9
JG		 827int r100_copy_blit(struct radeon_device *rdev,
828 uint64_t src_offset,
829 uint64_t dst_offset,
003cefe0 830 unsigned num_gpu_pages,
771fe6b9
JG		 831 struct radeon_fence *fence)
832{
833 uint32_t cur_pages;
003cefe0 834 uint32_t stride_bytes = RADEON_GPU_PAGE_SIZE;
771fe6b9
JG		 835 uint32_t pitch;
836 uint32_t stride_pixels;
837 unsigned ndw;
838 int num_loops;
839 int r = 0;
840
841 /* radeon limited to 16k stride */
842 stride_bytes &= 0x3fff;
843 /* radeon pitch is /64 */
844 pitch = stride_bytes / 64;
845 stride_pixels = stride_bytes / 4;
003cefe0 846 num_loops = DIV_ROUND_UP(num_gpu_pages, 8191);
771fe6b9
JG		 847
848 /* Ask for enough room for blit + flush + fence */
849 ndw = 64 + (10 * num_loops);
850 r = radeon_ring_lock(rdev, ndw);
851 if (r) {
852 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
853 return -EINVAL;
854 }
003cefe0
AD		 855 while (num_gpu_pages > 0) {
856 cur_pages = num_gpu_pages;
771fe6b9
JG		 857 if (cur_pages > 8191) {
858 cur_pages = 8191;
859 }
003cefe0 860 num_gpu_pages -= cur_pages;
771fe6b9
JG		 861
862 /* pages are in Y direction - height
863 page width in X direction - width */
864 radeon_ring_write(rdev, PACKET3(PACKET3_BITBLT_MULTI, 8));
865 radeon_ring_write(rdev,
866 RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
867 RADEON_GMC_DST_PITCH_OFFSET_CNTL |
868 RADEON_GMC_SRC_CLIPPING |
869 RADEON_GMC_DST_CLIPPING |
870 RADEON_GMC_BRUSH_NONE |
871 (RADEON_COLOR_FORMAT_ARGB8888 << 8) |
872 RADEON_GMC_SRC_DATATYPE_COLOR |
873 RADEON_ROP3_S |
874 RADEON_DP_SRC_SOURCE_MEMORY |
875 RADEON_GMC_CLR_CMP_CNTL_DIS |
876 RADEON_GMC_WR_MSK_DIS);
877 radeon_ring_write(rdev, (pitch << 22) | (src_offset >> 10));
878 radeon_ring_write(rdev, (pitch << 22) | (dst_offset >> 10));
879 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
880 radeon_ring_write(rdev, 0);
881 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
d9ad77eb
DA		 882 radeon_ring_write(rdev, num_gpu_pages);
883 radeon_ring_write(rdev, num_gpu_pages);
771fe6b9
JG		 884 radeon_ring_write(rdev, cur_pages | (stride_pixels << 16));
885 }
886 radeon_ring_write(rdev, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
887 radeon_ring_write(rdev, RADEON_RB2D_DC_FLUSH_ALL);
888 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
889 radeon_ring_write(rdev,
890 RADEON_WAIT_2D_IDLECLEAN |
891 RADEON_WAIT_HOST_IDLECLEAN |
892 RADEON_WAIT_DMA_GUI_IDLE);
893 if (fence) {
894 r = radeon_fence_emit(rdev, fence);
895 }
896 radeon_ring_unlock_commit(rdev);
897 return r;
898}
899
45600232
JG		 900static int r100_cp_wait_for_idle(struct radeon_device *rdev)
901{
902 unsigned i;
903 u32 tmp;
904
905 for (i = 0; i < rdev->usec_timeout; i++) {
906 tmp = RREG32(R_000E40_RBBM_STATUS);
907 if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) {
908 return 0;
909 }
910 udelay(1);
911 }
912 return -1;
913}
914
771fe6b9
JG		 915void r100_ring_start(struct radeon_device *rdev)
916{
917 int r;
918
919 r = radeon_ring_lock(rdev, 2);
920 if (r) {
921 return;
922 }
923 radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
924 radeon_ring_write(rdev,
925 RADEON_ISYNC_ANY2D_IDLE3D |
926 RADEON_ISYNC_ANY3D_IDLE2D |
927 RADEON_ISYNC_WAIT_IDLEGUI |
928 RADEON_ISYNC_CPSCRATCH_IDLEGUI);
929 radeon_ring_unlock_commit(rdev);
930}
931
70967ab9
BH		 932
933/* Load the microcode for the CP */
934static int r100_cp_init_microcode(struct radeon_device *rdev)
771fe6b9 935{
70967ab9
BH		 936 struct platform_device *pdev;
937 const char *fw_name = NULL;
938 int err;
771fe6b9 939
d9fdaafb 940 DRM_DEBUG_KMS("\n");
771fe6b9 941
70967ab9
BH		 942 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
943 err = IS_ERR(pdev);
944 if (err) {
945 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
946 return -EINVAL;
947 }
771fe6b9
JG		 948 if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) ||
949 (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) ||
950 (rdev->family == CHIP_RS200)) {
951 DRM_INFO("Loading R100 Microcode\n");
70967ab9 952 fw_name = FIRMWARE_R100;
771fe6b9
JG		 953 } else if ((rdev->family == CHIP_R200) ||
954 (rdev->family == CHIP_RV250) ||
955 (rdev->family == CHIP_RV280) ||
956 (rdev->family == CHIP_RS300)) {
957 DRM_INFO("Loading R200 Microcode\n");
70967ab9 958 fw_name = FIRMWARE_R200;
771fe6b9
JG		 959 } else if ((rdev->family == CHIP_R300) ||
960 (rdev->family == CHIP_R350) ||
961 (rdev->family == CHIP_RV350) ||
962 (rdev->family == CHIP_RV380) ||
963 (rdev->family == CHIP_RS400) ||
964 (rdev->family == CHIP_RS480)) {
965 DRM_INFO("Loading R300 Microcode\n");
70967ab9 966 fw_name = FIRMWARE_R300;
771fe6b9
JG		 967 } else if ((rdev->family == CHIP_R420) ||
968 (rdev->family == CHIP_R423) ||
969 (rdev->family == CHIP_RV410)) {
970 DRM_INFO("Loading R400 Microcode\n");
70967ab9 971 fw_name = FIRMWARE_R420;
771fe6b9
JG		 972 } else if ((rdev->family == CHIP_RS690) ||
973 (rdev->family == CHIP_RS740)) {
974 DRM_INFO("Loading RS690/RS740 Microcode\n");
70967ab9 975 fw_name = FIRMWARE_RS690;
771fe6b9
JG		 976 } else if (rdev->family == CHIP_RS600) {
977 DRM_INFO("Loading RS600 Microcode\n");
70967ab9 978 fw_name = FIRMWARE_RS600;
771fe6b9
JG		 979 } else if ((rdev->family == CHIP_RV515) ||
980 (rdev->family == CHIP_R520) ||
981 (rdev->family == CHIP_RV530) ||
982 (rdev->family == CHIP_R580) ||
983 (rdev->family == CHIP_RV560) ||
984 (rdev->family == CHIP_RV570)) {
985 DRM_INFO("Loading R500 Microcode\n");
70967ab9
BH		 986 fw_name = FIRMWARE_R520;
987 }
988
3ce0a23d 989 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
70967ab9
BH		 990 platform_device_unregister(pdev);
991 if (err) {
992 printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
993 fw_name);
3ce0a23d 994 } else if (rdev->me_fw->size % 8) {
70967ab9
BH		 995 printk(KERN_ERR
996 "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
3ce0a23d 997 rdev->me_fw->size, fw_name);
70967ab9 998 err = -EINVAL;
3ce0a23d
JG		 999 release_firmware(rdev->me_fw);
1000 rdev->me_fw = NULL;
70967ab9
BH		 1001 }
1002 return err;
1003}
d4550907 1004
70967ab9
BH		 1005static void r100_cp_load_microcode(struct radeon_device *rdev)
1006{
1007 const __be32 *fw_data;
1008 int i, size;
1009
1010 if (r100_gui_wait_for_idle(rdev)) {
1011 printk(KERN_WARNING "Failed to wait GUI idle while "
1012 "programming pipes. Bad things might happen.\n");
1013 }
1014
3ce0a23d
JG		 1015 if (rdev->me_fw) {
1016 size = rdev->me_fw->size / 4;
1017 fw_data = (const __be32 *)&rdev->me_fw->data[0];
70967ab9
BH		 1018 WREG32(RADEON_CP_ME_RAM_ADDR, 0);
1019 for (i = 0; i < size; i += 2) {
1020 WREG32(RADEON_CP_ME_RAM_DATAH,
1021 be32_to_cpup(&fw_data[i]));
1022 WREG32(RADEON_CP_ME_RAM_DATAL,
1023 be32_to_cpup(&fw_data[i + 1]));
771fe6b9
JG		 1024 }
1025 }
1026}
1027
1028int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
1029{
1030 unsigned rb_bufsz;
1031 unsigned rb_blksz;
1032 unsigned max_fetch;
1033 unsigned pre_write_timer;
1034 unsigned pre_write_limit;
1035 unsigned indirect2_start;
1036 unsigned indirect1_start;
1037 uint32_t tmp;
1038 int r;
1039
1040 if (r100_debugfs_cp_init(rdev)) {
1041 DRM_ERROR("Failed to register debugfs file for CP !\n");
1042 }
3ce0a23d 1043 if (!rdev->me_fw) {
70967ab9
BH		 1044 r = r100_cp_init_microcode(rdev);
1045 if (r) {
1046 DRM_ERROR("Failed to load firmware!\n");
1047 return r;
1048 }
1049 }
1050
771fe6b9
JG		 1051 /* Align ring size */
1052 rb_bufsz = drm_order(ring_size / 8);
1053 ring_size = (1 << (rb_bufsz + 1)) * 4;
1054 r100_cp_load_microcode(rdev);
1055 r = radeon_ring_init(rdev, ring_size);
1056 if (r) {
1057 return r;
1058 }
1059 /* Each time the cp read 1024 bytes (16 dword/quadword) update
1060 * the rptr copy in system ram */
1061 rb_blksz = 9;
1062 /* cp will read 128bytes at a time (4 dwords) */
1063 max_fetch = 1;
1064 rdev->cp.align_mask = 16 - 1;
1065 /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
1066 pre_write_timer = 64;
1067 /* Force CP_RB_WPTR write if written more than one time before the
1068 * delay expire
1069 */
1070 pre_write_limit = 0;
1071 /* Setup the cp cache like this (cache size is 96 dwords) :
1072 * RING 0 to 15
1073 * INDIRECT1 16 to 79
1074 * INDIRECT2 80 to 95
1075 * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
1076 * indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
1077 * indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
1078 * Idea being that most of the gpu cmd will be through indirect1 buffer
1079 * so it gets the bigger cache.
1080 */
1081 indirect2_start = 80;
1082 indirect1_start = 16;
1083 /* cp setup */
1084 WREG32(0x718, pre_write_timer | (pre_write_limit << 28));
d6f28938 1085 tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
771fe6b9 1086 REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
724c80e1 1087 REG_SET(RADEON_MAX_FETCH, max_fetch));
d6f28938
AD		 1088#ifdef __BIG_ENDIAN
1089 tmp |= RADEON_BUF_SWAP_32BIT;
1090#endif
724c80e1 1091 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_NO_UPDATE);
d6f28938 1092
771fe6b9
JG		 1093 /* Set ring address */
1094 DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)rdev->cp.gpu_addr);
1095 WREG32(RADEON_CP_RB_BASE, rdev->cp.gpu_addr);
1096 /* Force read & write ptr to 0 */
724c80e1 1097 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA | RADEON_RB_NO_UPDATE);
771fe6b9 1098 WREG32(RADEON_CP_RB_RPTR_WR, 0);
87463ff8
MD		 1099 rdev->cp.wptr = 0;
1100 WREG32(RADEON_CP_RB_WPTR, rdev->cp.wptr);
724c80e1
AD		 1101
1102 /* set the wb address whether it's enabled or not */
1103 WREG32(R_00070C_CP_RB_RPTR_ADDR,
1104 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) >> 2));
1105 WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET);
1106
1107 if (rdev->wb.enabled)
1108 WREG32(R_000770_SCRATCH_UMSK, 0xff);
1109 else {
1110 tmp |= RADEON_RB_NO_UPDATE;
1111 WREG32(R_000770_SCRATCH_UMSK, 0);
1112 }
1113
771fe6b9
JG		 1114 WREG32(RADEON_CP_RB_CNTL, tmp);
1115 udelay(10);
1116 rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
771fe6b9
JG		 1117 /* Set cp mode to bus mastering & enable cp*/
1118 WREG32(RADEON_CP_CSQ_MODE,
1119 REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
1120 REG_SET(RADEON_INDIRECT1_START, indirect1_start));
d75ee3be
AD		 1121 WREG32(RADEON_CP_RB_WPTR_DELAY, 0);
1122 WREG32(RADEON_CP_CSQ_MODE, 0x00004D4D);
771fe6b9
JG		 1123 WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
1124 radeon_ring_start(rdev);
1125 r = radeon_ring_test(rdev);
1126 if (r) {
1127 DRM_ERROR("radeon: cp isn't working (%d).\n", r);
1128 return r;
1129 }
1130 rdev->cp.ready = true;
53595338 1131 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
771fe6b9
JG		 1132 return 0;
1133}
1134
1135void r100_cp_fini(struct radeon_device *rdev)
1136{
45600232
JG		 1137 if (r100_cp_wait_for_idle(rdev)) {
1138 DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
1139 }
771fe6b9 1140 /* Disable ring */
a18d7ea1 1141 r100_cp_disable(rdev);
771fe6b9
JG		 1142 radeon_ring_fini(rdev);
1143 DRM_INFO("radeon: cp finalized\n");
1144}
1145
1146void r100_cp_disable(struct radeon_device *rdev)
1147{
1148 /* Disable ring */
53595338 1149 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
771fe6b9
JG		 1150 rdev->cp.ready = false;
1151 WREG32(RADEON_CP_CSQ_MODE, 0);
1152 WREG32(RADEON_CP_CSQ_CNTL, 0);
724c80e1 1153 WREG32(R_000770_SCRATCH_UMSK, 0);
771fe6b9
JG		 1154 if (r100_gui_wait_for_idle(rdev)) {
1155 printk(KERN_WARNING "Failed to wait GUI idle while "
1156 "programming pipes. Bad things might happen.\n");
1157 }
1158}
1159
3ce0a23d
JG		 1160void r100_cp_commit(struct radeon_device *rdev)
1161{
1162 WREG32(RADEON_CP_RB_WPTR, rdev->cp.wptr);
1163 (void)RREG32(RADEON_CP_RB_WPTR);
1164}
1165
771fe6b9
JG		 1166
1167/*
1168 * CS functions
1169 */
1170int r100_cs_parse_packet0(struct radeon_cs_parser *p,
1171 struct radeon_cs_packet *pkt,
068a117c 1172 const unsigned *auth, unsigned n,
771fe6b9
JG		 1173 radeon_packet0_check_t check)
1174{
1175 unsigned reg;
1176 unsigned i, j, m;
1177 unsigned idx;
1178 int r;
1179
1180 idx = pkt->idx + 1;
1181 reg = pkt->reg;
068a117c
JG		 1182 /* Check that register fall into register range
1183 * determined by the number of entry (n) in the
1184 * safe register bitmap.
1185 */
771fe6b9
JG		 1186 if (pkt->one_reg_wr) {
1187 if ((reg >> 7) > n) {
1188 return -EINVAL;
1189 }
1190 } else {
1191 if (((reg + (pkt->count << 2)) >> 7) > n) {
1192 return -EINVAL;
1193 }
1194 }
1195 for (i = 0; i <= pkt->count; i++, idx++) {
1196 j = (reg >> 7);
1197 m = 1 << ((reg >> 2) & 31);
1198 if (auth[j] & m) {
1199 r = check(p, pkt, idx, reg);
1200 if (r) {
1201 return r;
1202 }
1203 }
1204 if (pkt->one_reg_wr) {
1205 if (!(auth[j] & m)) {
1206 break;
1207 }
1208 } else {
1209 reg += 4;
1210 }
1211 }
1212 return 0;
1213}
1214
771fe6b9
JG		 1215void r100_cs_dump_packet(struct radeon_cs_parser *p,
1216 struct radeon_cs_packet *pkt)
1217{
771fe6b9
JG		 1218 volatile uint32_t *ib;
1219 unsigned i;
1220 unsigned idx;
1221
1222 ib = p->ib->ptr;
771fe6b9
JG		 1223 idx = pkt->idx;
1224 for (i = 0; i <= (pkt->count + 1); i++, idx++) {
1225 DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]);
1226 }
1227}
1228
1229/**
1230 * r100_cs_packet_parse() - parse cp packet and point ib index to next packet
1231 * @parser: parser structure holding parsing context.
1232 * @pkt: where to store packet informations
1233 *
1234 * Assume that chunk_ib_index is properly set. Will return -EINVAL
1235 * if packet is bigger than remaining ib size. or if packets is unknown.
1236 **/
1237int r100_cs_packet_parse(struct radeon_cs_parser *p,
1238 struct radeon_cs_packet *pkt,
1239 unsigned idx)
1240{
1241 struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
fa99239c 1242 uint32_t header;
771fe6b9
JG		 1243
1244 if (idx >= ib_chunk->length_dw) {
1245 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
1246 idx, ib_chunk->length_dw);
1247 return -EINVAL;
1248 }
513bcb46 1249 header = radeon_get_ib_value(p, idx);
771fe6b9
JG		 1250 pkt->idx = idx;
1251 pkt->type = CP_PACKET_GET_TYPE(header);
1252 pkt->count = CP_PACKET_GET_COUNT(header);
1253 switch (pkt->type) {
1254 case PACKET_TYPE0:
1255 pkt->reg = CP_PACKET0_GET_REG(header);
1256 pkt->one_reg_wr = CP_PACKET0_GET_ONE_REG_WR(header);
1257 break;
1258 case PACKET_TYPE3:
1259 pkt->opcode = CP_PACKET3_GET_OPCODE(header);
1260 break;
1261 case PACKET_TYPE2:
1262 pkt->count = -1;
1263 break;
1264 default:
1265 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
1266 return -EINVAL;
1267 }
1268 if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
1269 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
1270 pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
1271 return -EINVAL;
1272 }
1273 return 0;
1274}
1275
531369e6
DA		 1276/**
1277 * r100_cs_packet_next_vline() - parse userspace VLINE packet
1278 * @parser: parser structure holding parsing context.
1279 *
1280 * Userspace sends a special sequence for VLINE waits.
1281 * PACKET0 - VLINE_START_END + value
1282 * PACKET0 - WAIT_UNTIL +_value
1283 * RELOC (P3) - crtc_id in reloc.
1284 *
1285 * This function parses this and relocates the VLINE START END
1286 * and WAIT UNTIL packets to the correct crtc.
1287 * It also detects a switched off crtc and nulls out the
1288 * wait in that case.
1289 */
1290int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
1291{
531369e6
DA		 1292 struct drm_mode_object *obj;
1293 struct drm_crtc *crtc;
1294 struct radeon_crtc *radeon_crtc;
1295 struct radeon_cs_packet p3reloc, waitreloc;
1296 int crtc_id;
1297 int r;
1298 uint32_t header, h_idx, reg;
513bcb46 1299 volatile uint32_t *ib;
531369e6 1300
513bcb46 1301 ib = p->ib->ptr;
531369e6
DA		 1302
1303 /* parse the wait until */
1304 r = r100_cs_packet_parse(p, &waitreloc, p->idx);
1305 if (r)
1306 return r;
1307
1308 /* check its a wait until and only 1 count */
1309 if (waitreloc.reg != RADEON_WAIT_UNTIL ||
1310 waitreloc.count != 0) {
1311 DRM_ERROR("vline wait had illegal wait until segment\n");
a3a88a66 1312 return -EINVAL;
531369e6
DA		 1313 }
1314
513bcb46 1315 if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) {
531369e6 1316 DRM_ERROR("vline wait had illegal wait until\n");
a3a88a66 1317 return -EINVAL;
531369e6
DA		 1318 }
1319
1320 /* jump over the NOP */
90ebd065 1321 r = r100_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2);
531369e6
DA		 1322 if (r)
1323 return r;
1324
1325 h_idx = p->idx - 2;
90ebd065
AD		 1326 p->idx += waitreloc.count + 2;
1327 p->idx += p3reloc.count + 2;
531369e6 1328
513bcb46
DA		 1329 header = radeon_get_ib_value(p, h_idx);
1330 crtc_id = radeon_get_ib_value(p, h_idx + 5);
d4ac6a05 1331 reg = CP_PACKET0_GET_REG(header);
531369e6
DA		 1332 obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
1333 if (!obj) {
1334 DRM_ERROR("cannot find crtc %d\n", crtc_id);
a3a88a66 1335 return -EINVAL;
531369e6
DA		 1336 }
1337 crtc = obj_to_crtc(obj);
1338 radeon_crtc = to_radeon_crtc(crtc);
1339 crtc_id = radeon_crtc->crtc_id;
1340
1341 if (!crtc->enabled) {
1342 /* if the CRTC isn't enabled - we need to nop out the wait until */
513bcb46
DA		 1343 ib[h_idx + 2] = PACKET2(0);
1344 ib[h_idx + 3] = PACKET2(0);
531369e6
DA		 1345 } else if (crtc_id == 1) {
1346 switch (reg) {
1347 case AVIVO_D1MODE_VLINE_START_END:
90ebd065 1348 header &= ~R300_CP_PACKET0_REG_MASK;
531369e6
DA		 1349 header |= AVIVO_D2MODE_VLINE_START_END >> 2;
1350 break;
1351 case RADEON_CRTC_GUI_TRIG_VLINE:
90ebd065 1352 header &= ~R300_CP_PACKET0_REG_MASK;
531369e6
DA		 1353 header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2;
1354 break;
1355 default:
1356 DRM_ERROR("unknown crtc reloc\n");
a3a88a66 1357 return -EINVAL;
531369e6 1358 }
513bcb46
DA		 1359 ib[h_idx] = header;
1360 ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1;
531369e6 1361 }
a3a88a66
PB		 1362
1363 return 0;
531369e6
DA		 1364}
1365
771fe6b9
JG		 1366/**
1367 * r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3
1368 * @parser: parser structure holding parsing context.
1369 * @data: pointer to relocation data
1370 * @offset_start: starting offset
1371 * @offset_mask: offset mask (to align start offset on)
1372 * @reloc: reloc informations
1373 *
1374 * Check next packet is relocation packet3, do bo validation and compute
1375 * GPU offset using the provided start.
1376 **/
1377int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
1378 struct radeon_cs_reloc **cs_reloc)
1379{
771fe6b9
JG		 1380 struct radeon_cs_chunk *relocs_chunk;
1381 struct radeon_cs_packet p3reloc;
1382 unsigned idx;
1383 int r;
1384
1385 if (p->chunk_relocs_idx == -1) {
1386 DRM_ERROR("No relocation chunk !\n");
1387 return -EINVAL;
1388 }
1389 *cs_reloc = NULL;
771fe6b9
JG		 1390 relocs_chunk = &p->chunks[p->chunk_relocs_idx];
1391 r = r100_cs_packet_parse(p, &p3reloc, p->idx);
1392 if (r) {
1393 return r;
1394 }
1395 p->idx += p3reloc.count + 2;
1396 if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
1397 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
1398 p3reloc.idx);
1399 r100_cs_dump_packet(p, &p3reloc);
1400 return -EINVAL;
1401 }
513bcb46 1402 idx = radeon_get_ib_value(p, p3reloc.idx + 1);
771fe6b9
JG		 1403 if (idx >= relocs_chunk->length_dw) {
1404 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
1405 idx, relocs_chunk->length_dw);
1406 r100_cs_dump_packet(p, &p3reloc);
1407 return -EINVAL;
1408 }
1409 /* FIXME: we assume reloc size is 4 dwords */
1410 *cs_reloc = p->relocs_ptr[(idx / 4)];
1411 return 0;
1412}
1413
551ebd83
DA		 1414static int r100_get_vtx_size(uint32_t vtx_fmt)
1415{
1416 int vtx_size;
1417 vtx_size = 2;
1418 /* ordered according to bits in spec */
1419 if (vtx_fmt & RADEON_SE_VTX_FMT_W0)
1420 vtx_size++;
1421 if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR)
1422 vtx_size += 3;
1423 if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA)
1424 vtx_size++;
1425 if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR)
1426 vtx_size++;
1427 if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC)
1428 vtx_size += 3;
1429 if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG)
1430 vtx_size++;
1431 if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC)
1432 vtx_size++;
1433 if (vtx_fmt & RADEON_SE_VTX_FMT_ST0)
1434 vtx_size += 2;
1435 if (vtx_fmt & RADEON_SE_VTX_FMT_ST1)
1436 vtx_size += 2;
1437 if (vtx_fmt & RADEON_SE_VTX_FMT_Q1)
1438 vtx_size++;
1439 if (vtx_fmt & RADEON_SE_VTX_FMT_ST2)
1440 vtx_size += 2;
1441 if (vtx_fmt & RADEON_SE_VTX_FMT_Q2)
1442 vtx_size++;
1443 if (vtx_fmt & RADEON_SE_VTX_FMT_ST3)
1444 vtx_size += 2;
1445 if (vtx_fmt & RADEON_SE_VTX_FMT_Q3)
1446 vtx_size++;
1447 if (vtx_fmt & RADEON_SE_VTX_FMT_Q0)
1448 vtx_size++;
1449 /* blend weight */
1450 if (vtx_fmt & (0x7 << 15))
1451 vtx_size += (vtx_fmt >> 15) & 0x7;
1452 if (vtx_fmt & RADEON_SE_VTX_FMT_N0)
1453 vtx_size += 3;
1454 if (vtx_fmt & RADEON_SE_VTX_FMT_XY1)
1455 vtx_size += 2;
1456 if (vtx_fmt & RADEON_SE_VTX_FMT_Z1)
1457 vtx_size++;
1458 if (vtx_fmt & RADEON_SE_VTX_FMT_W1)
1459 vtx_size++;
1460 if (vtx_fmt & RADEON_SE_VTX_FMT_N1)
1461 vtx_size++;
1462 if (vtx_fmt & RADEON_SE_VTX_FMT_Z)
1463 vtx_size++;
1464 return vtx_size;
1465}
1466
771fe6b9 1467static int r100_packet0_check(struct radeon_cs_parser *p,
551ebd83
DA		 1468 struct radeon_cs_packet *pkt,
1469 unsigned idx, unsigned reg)
771fe6b9 1470{
771fe6b9 1471 struct radeon_cs_reloc *reloc;
551ebd83 1472 struct r100_cs_track *track;
771fe6b9
JG		 1473 volatile uint32_t *ib;
1474 uint32_t tmp;
771fe6b9 1475 int r;
551ebd83 1476 int i, face;
e024e110 1477 u32 tile_flags = 0;
513bcb46 1478 u32 idx_value;
771fe6b9
JG		 1479
1480 ib = p->ib->ptr;
551ebd83
DA		 1481 track = (struct r100_cs_track *)p->track;
1482
513bcb46
DA		 1483 idx_value = radeon_get_ib_value(p, idx);
1484
551ebd83
DA		 1485 switch (reg) {
1486 case RADEON_CRTC_GUI_TRIG_VLINE:
1487 r = r100_cs_packet_parse_vline(p);
1488 if (r) {
1489 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1490 idx, reg);
1491 r100_cs_dump_packet(p, pkt);
1492 return r;
1493 }
1494 break;
771fe6b9
JG		 1495 /* FIXME: only allow PACKET3 blit? easier to check for out of
1496 * range access */
551ebd83
DA		 1497 case RADEON_DST_PITCH_OFFSET:
1498 case RADEON_SRC_PITCH_OFFSET:
1499 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
1500 if (r)
1501 return r;
1502 break;
1503 case RADEON_RB3D_DEPTHOFFSET:
1504 r = r100_cs_packet_next_reloc(p, &reloc);
1505 if (r) {
1506 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1507 idx, reg);
1508 r100_cs_dump_packet(p, pkt);
1509 return r;
1510 }
1511 track->zb.robj = reloc->robj;
513bcb46 1512 track->zb.offset = idx_value;
40b4a759 1513 track->zb_dirty = true;
513bcb46 1514 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83
DA		 1515 break;
1516 case RADEON_RB3D_COLOROFFSET:
1517 r = r100_cs_packet_next_reloc(p, &reloc);
1518 if (r) {
1519 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1520 idx, reg);
1521 r100_cs_dump_packet(p, pkt);
1522 return r;
1523 }
1524 track->cb[0].robj = reloc->robj;
513bcb46 1525 track->cb[0].offset = idx_value;
40b4a759 1526 track->cb_dirty = true;
513bcb46 1527 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83
DA		 1528 break;
1529 case RADEON_PP_TXOFFSET_0:
1530 case RADEON_PP_TXOFFSET_1:
1531 case RADEON_PP_TXOFFSET_2:
1532 i = (reg - RADEON_PP_TXOFFSET_0) / 24;
1533 r = r100_cs_packet_next_reloc(p, &reloc);
1534 if (r) {
1535 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1536 idx, reg);
1537 r100_cs_dump_packet(p, pkt);
1538 return r;
1539 }
513bcb46 1540 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83 1541 track->textures[i].robj = reloc->robj;
40b4a759 1542 track->tex_dirty = true;
551ebd83
DA		 1543 break;
1544 case RADEON_PP_CUBIC_OFFSET_T0_0:
1545 case RADEON_PP_CUBIC_OFFSET_T0_1:
1546 case RADEON_PP_CUBIC_OFFSET_T0_2:
1547 case RADEON_PP_CUBIC_OFFSET_T0_3:
1548 case RADEON_PP_CUBIC_OFFSET_T0_4:
1549 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
1550 r = r100_cs_packet_next_reloc(p, &reloc);
1551 if (r) {
1552 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1553 idx, reg);
1554 r100_cs_dump_packet(p, pkt);
1555 return r;
1556 }
513bcb46
DA		 1557 track->textures[0].cube_info[i].offset = idx_value;
1558 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83 1559 track->textures[0].cube_info[i].robj = reloc->robj;
40b4a759 1560 track->tex_dirty = true;
551ebd83
DA		 1561 break;
1562 case RADEON_PP_CUBIC_OFFSET_T1_0:
1563 case RADEON_PP_CUBIC_OFFSET_T1_1:
1564 case RADEON_PP_CUBIC_OFFSET_T1_2:
1565 case RADEON_PP_CUBIC_OFFSET_T1_3:
1566 case RADEON_PP_CUBIC_OFFSET_T1_4:
1567 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
1568 r = r100_cs_packet_next_reloc(p, &reloc);
1569 if (r) {
1570 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1571 idx, reg);
1572 r100_cs_dump_packet(p, pkt);
1573 return r;
1574 }
513bcb46
DA		 1575 track->textures[1].cube_info[i].offset = idx_value;
1576 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83 1577 track->textures[1].cube_info[i].robj = reloc->robj;
40b4a759 1578 track->tex_dirty = true;
551ebd83
DA		 1579 break;
1580 case RADEON_PP_CUBIC_OFFSET_T2_0:
1581 case RADEON_PP_CUBIC_OFFSET_T2_1:
1582 case RADEON_PP_CUBIC_OFFSET_T2_2:
1583 case RADEON_PP_CUBIC_OFFSET_T2_3:
1584 case RADEON_PP_CUBIC_OFFSET_T2_4:
1585 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
1586 r = r100_cs_packet_next_reloc(p, &reloc);
1587 if (r) {
1588 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1589 idx, reg);
1590 r100_cs_dump_packet(p, pkt);
1591 return r;
1592 }
513bcb46
DA		 1593 track->textures[2].cube_info[i].offset = idx_value;
1594 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83 1595 track->textures[2].cube_info[i].robj = reloc->robj;
40b4a759 1596 track->tex_dirty = true;
551ebd83
DA		 1597 break;
1598 case RADEON_RE_WIDTH_HEIGHT:
513bcb46 1599 track->maxy = ((idx_value >> 16) & 0x7FF);
40b4a759
MO		 1600 track->cb_dirty = true;
1601 track->zb_dirty = true;
551ebd83
DA		 1602 break;
1603 case RADEON_RB3D_COLORPITCH:
1604 r = r100_cs_packet_next_reloc(p, &reloc);
1605 if (r) {
1606 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1607 idx, reg);
1608 r100_cs_dump_packet(p, pkt);
1609 return r;
1610 }
e024e110 1611
551ebd83
DA		 1612 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1613 tile_flags |= RADEON_COLOR_TILE_ENABLE;
1614 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1615 tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
e024e110 1616
513bcb46 1617 tmp = idx_value & ~(0x7 << 16);
551ebd83
DA		 1618 tmp |= tile_flags;
1619 ib[idx] = tmp;
e024e110 1620
513bcb46 1621 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
40b4a759 1622 track->cb_dirty = true;
551ebd83
DA		 1623 break;
1624 case RADEON_RB3D_DEPTHPITCH:
513bcb46 1625 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
40b4a759 1626 track->zb_dirty = true;
551ebd83
DA		 1627 break;
1628 case RADEON_RB3D_CNTL:
513bcb46 1629 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
551ebd83
DA		 1630 case 7:
1631 case 8:
1632 case 9:
1633 case 11:
1634 case 12:
1635 track->cb[0].cpp = 1;
e024e110 1636 break;
551ebd83
DA		 1637 case 3:
1638 case 4:
1639 case 15:
1640 track->cb[0].cpp = 2;
1641 break;
1642 case 6:
1643 track->cb[0].cpp = 4;
1644 break;
1645 default:
1646 DRM_ERROR("Invalid color buffer format (%d) !\n",
513bcb46 1647 ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
551ebd83
DA		 1648 return -EINVAL;
1649 }
513bcb46 1650 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
40b4a759
MO		 1651 track->cb_dirty = true;
1652 track->zb_dirty = true;
551ebd83
DA		 1653 break;
1654 case RADEON_RB3D_ZSTENCILCNTL:
513bcb46 1655 switch (idx_value & 0xf) {
551ebd83
DA		 1656 case 0:
1657 track->zb.cpp = 2;
1658 break;
1659 case 2:
1660 case 3:
1661 case 4:
1662 case 5:
1663 case 9:
1664 case 11:
1665 track->zb.cpp = 4;
17782d99 1666 break;
771fe6b9 1667 default:
771fe6b9
JG		 1668 break;
1669 }
40b4a759 1670 track->zb_dirty = true;
551ebd83
DA		 1671 break;
1672 case RADEON_RB3D_ZPASS_ADDR:
1673 r = r100_cs_packet_next_reloc(p, &reloc);
1674 if (r) {
1675 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1676 idx, reg);
1677 r100_cs_dump_packet(p, pkt);
1678 return r;
1679 }
513bcb46 1680 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83
DA		 1681 break;
1682 case RADEON_PP_CNTL:
1683 {
513bcb46 1684 uint32_t temp = idx_value >> 4;
551ebd83
DA		 1685 for (i = 0; i < track->num_texture; i++)
1686 track->textures[i].enabled = !!(temp & (1 << i));
40b4a759 1687 track->tex_dirty = true;
551ebd83
DA		 1688 }
1689 break;
1690 case RADEON_SE_VF_CNTL:
513bcb46 1691 track->vap_vf_cntl = idx_value;
551ebd83
DA		 1692 break;
1693 case RADEON_SE_VTX_FMT:
513bcb46 1694 track->vtx_size = r100_get_vtx_size(idx_value);
551ebd83
DA		 1695 break;
1696 case RADEON_PP_TEX_SIZE_0:
1697 case RADEON_PP_TEX_SIZE_1:
1698 case RADEON_PP_TEX_SIZE_2:
1699 i = (reg - RADEON_PP_TEX_SIZE_0) / 8;
513bcb46
DA		 1700 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
1701 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
40b4a759 1702 track->tex_dirty = true;
551ebd83
DA		 1703 break;
1704 case RADEON_PP_TEX_PITCH_0:
1705 case RADEON_PP_TEX_PITCH_1:
1706 case RADEON_PP_TEX_PITCH_2:
1707 i = (reg - RADEON_PP_TEX_PITCH_0) / 8;
513bcb46 1708 track->textures[i].pitch = idx_value + 32;
40b4a759 1709 track->tex_dirty = true;
551ebd83
DA		 1710 break;
1711 case RADEON_PP_TXFILTER_0:
1712 case RADEON_PP_TXFILTER_1:
1713 case RADEON_PP_TXFILTER_2:
1714 i = (reg - RADEON_PP_TXFILTER_0) / 24;
513bcb46 1715 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK)
551ebd83 1716 >> RADEON_MAX_MIP_LEVEL_SHIFT);
513bcb46 1717 tmp = (idx_value >> 23) & 0x7;
551ebd83
DA		 1718 if (tmp == 2 || tmp == 6)
1719 track->textures[i].roundup_w = false;
513bcb46 1720 tmp = (idx_value >> 27) & 0x7;
551ebd83
DA		 1721 if (tmp == 2 || tmp == 6)
1722 track->textures[i].roundup_h = false;
40b4a759 1723 track->tex_dirty = true;
551ebd83
DA		 1724 break;
1725 case RADEON_PP_TXFORMAT_0:
1726 case RADEON_PP_TXFORMAT_1:
1727 case RADEON_PP_TXFORMAT_2:
1728 i = (reg - RADEON_PP_TXFORMAT_0) / 24;
513bcb46 1729 if (idx_value & RADEON_TXFORMAT_NON_POWER2) {
551ebd83
DA		 1730 track->textures[i].use_pitch = 1;
1731 } else {
1732 track->textures[i].use_pitch = 0;
513bcb46
DA		 1733 track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
1734 track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
551ebd83 1735 }
513bcb46 1736 if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE)
551ebd83 1737 track->textures[i].tex_coord_type = 2;
513bcb46 1738 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
551ebd83
DA		 1739 case RADEON_TXFORMAT_I8:
1740 case RADEON_TXFORMAT_RGB332:
1741 case RADEON_TXFORMAT_Y8:
1742 track->textures[i].cpp = 1;
f9da52d5 1743 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
551ebd83
DA		 1744 break;
1745 case RADEON_TXFORMAT_AI88:
1746 case RADEON_TXFORMAT_ARGB1555:
1747 case RADEON_TXFORMAT_RGB565:
1748 case RADEON_TXFORMAT_ARGB4444:
1749 case RADEON_TXFORMAT_VYUY422:
1750 case RADEON_TXFORMAT_YVYU422:
551ebd83
DA		 1751 case RADEON_TXFORMAT_SHADOW16:
1752 case RADEON_TXFORMAT_LDUDV655:
1753 case RADEON_TXFORMAT_DUDV88:
1754 track->textures[i].cpp = 2;
f9da52d5 1755 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
771fe6b9 1756 break;
551ebd83
DA		 1757 case RADEON_TXFORMAT_ARGB8888:
1758 case RADEON_TXFORMAT_RGBA8888:
551ebd83
DA		 1759 case RADEON_TXFORMAT_SHADOW32:
1760 case RADEON_TXFORMAT_LDUDUV8888:
1761 track->textures[i].cpp = 4;
f9da52d5 1762 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
551ebd83 1763 break;
d785d78b
DA		 1764 case RADEON_TXFORMAT_DXT1:
1765 track->textures[i].cpp = 1;
1766 track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
1767 break;
1768 case RADEON_TXFORMAT_DXT23:
1769 case RADEON_TXFORMAT_DXT45:
1770 track->textures[i].cpp = 1;
1771 track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
1772 break;
551ebd83 1773 }
513bcb46
DA		 1774 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
1775 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
40b4a759 1776 track->tex_dirty = true;
551ebd83
DA		 1777 break;
1778 case RADEON_PP_CUBIC_FACES_0:
1779 case RADEON_PP_CUBIC_FACES_1:
1780 case RADEON_PP_CUBIC_FACES_2:
513bcb46 1781 tmp = idx_value;
551ebd83
DA		 1782 i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;
1783 for (face = 0; face < 4; face++) {
1784 track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
1785 track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
771fe6b9 1786 }
40b4a759 1787 track->tex_dirty = true;
551ebd83
DA		 1788 break;
1789 default:
1790 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1791 reg, idx);
1792 return -EINVAL;
771fe6b9
JG		 1793 }
1794 return 0;
1795}
1796
068a117c
JG		 1797int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1798 struct radeon_cs_packet *pkt,
4c788679 1799 struct radeon_bo *robj)
068a117c 1800{
068a117c 1801 unsigned idx;
513bcb46 1802 u32 value;
068a117c 1803 idx = pkt->idx + 1;
513bcb46 1804 value = radeon_get_ib_value(p, idx + 2);
4c788679 1805 if ((value + 1) > radeon_bo_size(robj)) {
068a117c
JG		 1806 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
1807 "(need %u have %lu) !\n",
513bcb46 1808 value + 1,
4c788679 1809 radeon_bo_size(robj));
068a117c
JG		 1810 return -EINVAL;
1811 }
1812 return 0;
1813}
1814
771fe6b9
JG		 1815static int r100_packet3_check(struct radeon_cs_parser *p,
1816 struct radeon_cs_packet *pkt)
1817{
771fe6b9 1818 struct radeon_cs_reloc *reloc;
551ebd83 1819 struct r100_cs_track *track;
771fe6b9 1820 unsigned idx;
771fe6b9
JG		 1821 volatile uint32_t *ib;
1822 int r;
1823
1824 ib = p->ib->ptr;
771fe6b9 1825 idx = pkt->idx + 1;
551ebd83 1826 track = (struct r100_cs_track *)p->track;
771fe6b9
JG		 1827 switch (pkt->opcode) {
1828 case PACKET3_3D_LOAD_VBPNTR:
513bcb46
DA		 1829 r = r100_packet3_load_vbpntr(p, pkt, idx);
1830 if (r)
1831 return r;
771fe6b9
JG		 1832 break;
1833 case PACKET3_INDX_BUFFER:
1834 r = r100_cs_packet_next_reloc(p, &reloc);
1835 if (r) {
1836 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1837 r100_cs_dump_packet(p, pkt);
1838 return r;
1839 }
513bcb46 1840 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset);
068a117c
JG		 1841 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1842 if (r) {
1843 return r;
1844 }
771fe6b9
JG		 1845 break;
1846 case 0x23:
771fe6b9
JG		 1847 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
1848 r = r100_cs_packet_next_reloc(p, &reloc);
1849 if (r) {
1850 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1851 r100_cs_dump_packet(p, pkt);
1852 return r;
1853 }
513bcb46 1854 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset);
551ebd83 1855 track->num_arrays = 1;
513bcb46 1856 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2));
551ebd83
DA		 1857
1858 track->arrays[0].robj = reloc->robj;
1859 track->arrays[0].esize = track->vtx_size;
1860
513bcb46 1861 track->max_indx = radeon_get_ib_value(p, idx+1);
551ebd83 1862
513bcb46 1863 track->vap_vf_cntl = radeon_get_ib_value(p, idx+3);
551ebd83
DA		 1864 track->immd_dwords = pkt->count - 1;
1865 r = r100_cs_track_check(p->rdev, track);
1866 if (r)
1867 return r;
771fe6b9
JG		 1868 break;
1869 case PACKET3_3D_DRAW_IMMD:
513bcb46 1870 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
551ebd83
DA		 1871 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1872 return -EINVAL;
1873 }
cf57fc7a 1874 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0));
513bcb46 1875 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
551ebd83
DA		 1876 track->immd_dwords = pkt->count - 1;
1877 r = r100_cs_track_check(p->rdev, track);
1878 if (r)
1879 return r;
1880 break;
771fe6b9
JG		 1881 /* triggers drawing using in-packet vertex data */
1882 case PACKET3_3D_DRAW_IMMD_2:
513bcb46 1883 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
551ebd83
DA		 1884 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1885 return -EINVAL;
1886 }
513bcb46 1887 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
551ebd83
DA		 1888 track->immd_dwords = pkt->count;
1889 r = r100_cs_track_check(p->rdev, track);
1890 if (r)
1891 return r;
1892 break;
771fe6b9
JG		 1893 /* triggers drawing using in-packet vertex data */
1894 case PACKET3_3D_DRAW_VBUF_2:
513bcb46 1895 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
551ebd83
DA		 1896 r = r100_cs_track_check(p->rdev, track);
1897 if (r)
1898 return r;
1899 break;
771fe6b9
JG		 1900 /* triggers drawing of vertex buffers setup elsewhere */
1901 case PACKET3_3D_DRAW_INDX_2:
513bcb46 1902 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
551ebd83
DA		 1903 r = r100_cs_track_check(p->rdev, track);
1904 if (r)
1905 return r;
1906 break;
771fe6b9
JG		 1907 /* triggers drawing using indices to vertex buffer */
1908 case PACKET3_3D_DRAW_VBUF:
513bcb46 1909 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
551ebd83
DA		 1910 r = r100_cs_track_check(p->rdev, track);
1911 if (r)
1912 return r;
1913 break;
771fe6b9
JG		 1914 /* triggers drawing of vertex buffers setup elsewhere */
1915 case PACKET3_3D_DRAW_INDX:
513bcb46 1916 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
551ebd83
DA		 1917 r = r100_cs_track_check(p->rdev, track);
1918 if (r)
1919 return r;
1920 break;
771fe6b9 1921 /* triggers drawing using indices to vertex buffer */
ab9e1f59
DA		 1922 case PACKET3_3D_CLEAR_HIZ:
1923 case PACKET3_3D_CLEAR_ZMASK:
1924 if (p->rdev->hyperz_filp != p->filp)
1925 return -EINVAL;
1926 break;
771fe6b9
JG		 1927 case PACKET3_NOP:
1928 break;
1929 default:
1930 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1931 return -EINVAL;
1932 }
1933 return 0;
1934}
1935
1936int r100_cs_parse(struct radeon_cs_parser *p)
1937{
1938 struct radeon_cs_packet pkt;
9f022ddf 1939 struct r100_cs_track *track;
771fe6b9
JG		 1940 int r;
1941
9f022ddf
JG		 1942 track = kzalloc(sizeof(*track), GFP_KERNEL);
1943 r100_cs_track_clear(p->rdev, track);
1944 p->track = track;
771fe6b9
JG		 1945 do {
1946 r = r100_cs_packet_parse(p, &pkt, p->idx);
1947 if (r) {
1948 return r;
1949 }
1950 p->idx += pkt.count + 2;
1951 switch (pkt.type) {
068a117c 1952 case PACKET_TYPE0:
551ebd83
DA		 1953 if (p->rdev->family >= CHIP_R200)
1954 r = r100_cs_parse_packet0(p, &pkt,
1955 p->rdev->config.r100.reg_safe_bm,
1956 p->rdev->config.r100.reg_safe_bm_size,
1957 &r200_packet0_check);
1958 else
1959 r = r100_cs_parse_packet0(p, &pkt,
1960 p->rdev->config.r100.reg_safe_bm,
1961 p->rdev->config.r100.reg_safe_bm_size,
1962 &r100_packet0_check);
068a117c
JG		 1963 break;
1964 case PACKET_TYPE2:
1965 break;
1966 case PACKET_TYPE3:
1967 r = r100_packet3_check(p, &pkt);
1968 break;
1969 default:
1970 DRM_ERROR("Unknown packet type %d !\n",
1971 pkt.type);
1972 return -EINVAL;
771fe6b9
JG		 1973 }
1974 if (r) {
1975 return r;
1976 }
1977 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
1978 return 0;
1979}
1980
1981
1982/*
1983 * Global GPU functions
1984 */
1985void r100_errata(struct radeon_device *rdev)
1986{
1987 rdev->pll_errata = 0;
1988
1989 if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) {
1990 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS;
1991 }
1992
1993 if (rdev->family == CHIP_RV100 ||
1994 rdev->family == CHIP_RS100 ||
1995 rdev->family == CHIP_RS200) {
1996 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY;
1997 }
1998}
1999
2000/* Wait for vertical sync on primary CRTC */
2001void r100_gpu_wait_for_vsync(struct radeon_device *rdev)
2002{
2003 uint32_t crtc_gen_cntl, tmp;
2004 int i;
2005
2006 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
2007 if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) ||
2008 !(crtc_gen_cntl & RADEON_CRTC_EN)) {
2009 return;
2010 }
2011 /* Clear the CRTC_VBLANK_SAVE bit */
2012 WREG32(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR);
2013 for (i = 0; i < rdev->usec_timeout; i++) {
2014 tmp = RREG32(RADEON_CRTC_STATUS);
2015 if (tmp & RADEON_CRTC_VBLANK_SAVE) {
2016 return;
2017 }
2018 DRM_UDELAY(1);
2019 }
2020}
2021
2022/* Wait for vertical sync on secondary CRTC */
2023void r100_gpu_wait_for_vsync2(struct radeon_device *rdev)
2024{
2025 uint32_t crtc2_gen_cntl, tmp;
2026 int i;
2027
2028 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
2029 if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) ||
2030 !(crtc2_gen_cntl & RADEON_CRTC2_EN))
2031 return;
2032
2033 /* Clear the CRTC_VBLANK_SAVE bit */
2034 WREG32(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR);
2035 for (i = 0; i < rdev->usec_timeout; i++) {
2036 tmp = RREG32(RADEON_CRTC2_STATUS);
2037 if (tmp & RADEON_CRTC2_VBLANK_SAVE) {
2038 return;
2039 }
2040 DRM_UDELAY(1);
2041 }
2042}
2043
2044int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
2045{
2046 unsigned i;
2047 uint32_t tmp;
2048
2049 for (i = 0; i < rdev->usec_timeout; i++) {
2050 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
2051 if (tmp >= n) {
2052 return 0;
2053 }
2054 DRM_UDELAY(1);
2055 }
2056 return -1;
2057}
2058
2059int r100_gui_wait_for_idle(struct radeon_device *rdev)
2060{
2061 unsigned i;
2062 uint32_t tmp;
2063
2064 if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
2065 printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !"
2066 " Bad things might happen.\n");
2067 }
2068 for (i = 0; i < rdev->usec_timeout; i++) {
2069 tmp = RREG32(RADEON_RBBM_STATUS);
4612dc97 2070 if (!(tmp & RADEON_RBBM_ACTIVE)) {
771fe6b9
JG		 2071 return 0;
2072 }
2073 DRM_UDELAY(1);
2074 }
2075 return -1;
2076}
2077
2078int r100_mc_wait_for_idle(struct radeon_device *rdev)
2079{
2080 unsigned i;
2081 uint32_t tmp;
2082
2083 for (i = 0; i < rdev->usec_timeout; i++) {
2084 /* read MC_STATUS */
4612dc97
AD		 2085 tmp = RREG32(RADEON_MC_STATUS);
2086 if (tmp & RADEON_MC_IDLE) {
771fe6b9
JG		 2087 return 0;
2088 }
2089 DRM_UDELAY(1);
2090 }
2091 return -1;
2092}
2093
225758d8 2094void r100_gpu_lockup_update(struct r100_gpu_lockup *lockup, struct radeon_cp *cp)
771fe6b9 2095{
225758d8
JG		 2096 lockup->last_cp_rptr = cp->rptr;
2097 lockup->last_jiffies = jiffies;
2098}
2099
2100/**
2101 * r100_gpu_cp_is_lockup() - check if CP is lockup by recording information
2102 * @rdev: radeon device structure
2103 * @lockup: r100_gpu_lockup structure holding CP lockup tracking informations
2104 * @cp: radeon_cp structure holding CP information
2105 *
2106 * We don't need to initialize the lockup tracking information as we will either
2107 * have CP rptr to a different value of jiffies wrap around which will force
2108 * initialization of the lockup tracking informations.
2109 *
2110 * A possible false positivie is if we get call after while and last_cp_rptr ==
2111 * the current CP rptr, even if it's unlikely it might happen. To avoid this
2112 * if the elapsed time since last call is bigger than 2 second than we return
2113 * false and update the tracking information. Due to this the caller must call
2114 * r100_gpu_cp_is_lockup several time in less than 2sec for lockup to be reported
2115 * the fencing code should be cautious about that.
2116 *
2117 * Caller should write to the ring to force CP to do something so we don't get
2118 * false positive when CP is just gived nothing to do.
2119 *
2120 **/
2121bool r100_gpu_cp_is_lockup(struct radeon_device *rdev, struct r100_gpu_lockup *lockup, struct radeon_cp *cp)
2122{
2123 unsigned long cjiffies, elapsed;
2124
2125 cjiffies = jiffies;
2126 if (!time_after(cjiffies, lockup->last_jiffies)) {
2127 /* likely a wrap around */
2128 lockup->last_cp_rptr = cp->rptr;
2129 lockup->last_jiffies = jiffies;
2130 return false;
2131 }
2132 if (cp->rptr != lockup->last_cp_rptr) {
2133 /* CP is still working no lockup */
2134 lockup->last_cp_rptr = cp->rptr;
2135 lockup->last_jiffies = jiffies;
2136 return false;
2137 }
2138 elapsed = jiffies_to_msecs(cjiffies - lockup->last_jiffies);
ec00efb7 2139 if (elapsed >= 10000) {
225758d8
JG		 2140 dev_err(rdev->dev, "GPU lockup CP stall for more than %lumsec\n", elapsed);
2141 return true;
2142 }
2143 /* give a chance to the GPU ... */
2144 return false;
771fe6b9
JG		 2145}
2146
225758d8 2147bool r100_gpu_is_lockup(struct radeon_device *rdev)
771fe6b9 2148{
225758d8
JG		 2149 u32 rbbm_status;
2150 int r;
771fe6b9 2151
225758d8
JG		 2152 rbbm_status = RREG32(R_000E40_RBBM_STATUS);
2153 if (!G_000E40_GUI_ACTIVE(rbbm_status)) {
2154 r100_gpu_lockup_update(&rdev->config.r100.lockup, &rdev->cp);
2155 return false;
2156 }
2157 /* force CP activities */
2158 r = radeon_ring_lock(rdev, 2);
2159 if (!r) {
2160 /* PACKET2 NOP */
2161 radeon_ring_write(rdev, 0x80000000);
2162 radeon_ring_write(rdev, 0x80000000);
2163 radeon_ring_unlock_commit(rdev);
2164 }
2165 rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
2166 return r100_gpu_cp_is_lockup(rdev, &rdev->config.r100.lockup, &rdev->cp);
771fe6b9
JG		 2167}
2168
90aca4d2 2169void r100_bm_disable(struct radeon_device *rdev)
771fe6b9 2170{
90aca4d2 2171 u32 tmp;
771fe6b9 2172
90aca4d2
JG		 2173 /* disable bus mastering */
2174 tmp = RREG32(R_000030_BUS_CNTL);
2175 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000044);
2176 mdelay(1);
2177 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000042);
2178 mdelay(1);
2179 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000040);
2180 tmp = RREG32(RADEON_BUS_CNTL);
2181 mdelay(1);
2182 pci_read_config_word(rdev->pdev, 0x4, (u16*)&tmp);
2183 pci_write_config_word(rdev->pdev, 0x4, tmp & 0xFFFB);
771fe6b9 2184 mdelay(1);
771fe6b9
JG		 2185}
2186
a2d07b74 2187int r100_asic_reset(struct radeon_device *rdev)
771fe6b9 2188{
90aca4d2
JG		 2189 struct r100_mc_save save;
2190 u32 status, tmp;
25b2ec5b 2191 int ret = 0;
771fe6b9 2192
90aca4d2
JG		 2193 status = RREG32(R_000E40_RBBM_STATUS);
2194 if (!G_000E40_GUI_ACTIVE(status)) {
2195 return 0;
771fe6b9 2196 }
25b2ec5b 2197 r100_mc_stop(rdev, &save);
90aca4d2
JG		 2198 status = RREG32(R_000E40_RBBM_STATUS);
2199 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2200 /* stop CP */
2201 WREG32(RADEON_CP_CSQ_CNTL, 0);
2202 tmp = RREG32(RADEON_CP_RB_CNTL);
2203 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
2204 WREG32(RADEON_CP_RB_RPTR_WR, 0);
2205 WREG32(RADEON_CP_RB_WPTR, 0);
2206 WREG32(RADEON_CP_RB_CNTL, tmp);
2207 /* save PCI state */
2208 pci_save_state(rdev->pdev);
2209 /* disable bus mastering */
2210 r100_bm_disable(rdev);
2211 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_SE(1) |
2212 S_0000F0_SOFT_RESET_RE(1) |
2213 S_0000F0_SOFT_RESET_PP(1) |
2214 S_0000F0_SOFT_RESET_RB(1));
2215 RREG32(R_0000F0_RBBM_SOFT_RESET);
2216 mdelay(500);
2217 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2218 mdelay(1);
2219 status = RREG32(R_000E40_RBBM_STATUS);
2220 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
771fe6b9 2221 /* reset CP */
90aca4d2
JG		 2222 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
2223 RREG32(R_0000F0_RBBM_SOFT_RESET);
2224 mdelay(500);
2225 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2226 mdelay(1);
2227 status = RREG32(R_000E40_RBBM_STATUS);
2228 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2229 /* restore PCI & busmastering */
2230 pci_restore_state(rdev->pdev);
2231 r100_enable_bm(rdev);
771fe6b9 2232 /* Check if GPU is idle */
90aca4d2
JG		 2233 if (G_000E40_SE_BUSY(status) || G_000E40_RE_BUSY(status) ||
2234 G_000E40_TAM_BUSY(status) || G_000E40_PB_BUSY(status)) {
2235 dev_err(rdev->dev, "failed to reset GPU\n");
2236 rdev->gpu_lockup = true;
25b2ec5b
AD		 2237 ret = -1;
2238 } else
2239 dev_info(rdev->dev, "GPU reset succeed\n");
90aca4d2 2240 r100_mc_resume(rdev, &save);
25b2ec5b 2241 return ret;
771fe6b9
JG		 2242}
2243
92cde00c
AD		 2244void r100_set_common_regs(struct radeon_device *rdev)
2245{
2739d49c
AD		 2246 struct drm_device *dev = rdev->ddev;
2247 bool force_dac2 = false;
d668046c 2248 u32 tmp;
2739d49c 2249
92cde00c
AD		 2250 /* set these so they don't interfere with anything */
2251 WREG32(RADEON_OV0_SCALE_CNTL, 0);
2252 WREG32(RADEON_SUBPIC_CNTL, 0);
2253 WREG32(RADEON_VIPH_CONTROL, 0);
2254 WREG32(RADEON_I2C_CNTL_1, 0);
2255 WREG32(RADEON_DVI_I2C_CNTL_1, 0);
2256 WREG32(RADEON_CAP0_TRIG_CNTL, 0);
2257 WREG32(RADEON_CAP1_TRIG_CNTL, 0);
2739d49c
AD		 2258
2259 /* always set up dac2 on rn50 and some rv100 as lots
2260 * of servers seem to wire it up to a VGA port but
2261 * don't report it in the bios connector
2262 * table.
2263 */
2264 switch (dev->pdev->device) {
2265 /* RN50 */
2266 case 0x515e:
2267 case 0x5969:
2268 force_dac2 = true;
2269 break;
2270 /* RV100*/
2271 case 0x5159:
2272 case 0x515a:
2273 /* DELL triple head servers */
2274 if ((dev->pdev->subsystem_vendor == 0x1028 /* DELL */) &&
2275 ((dev->pdev->subsystem_device == 0x016c) ||
2276 (dev->pdev->subsystem_device == 0x016d) ||
2277 (dev->pdev->subsystem_device == 0x016e) ||
2278 (dev->pdev->subsystem_device == 0x016f) ||
2279 (dev->pdev->subsystem_device == 0x0170) ||
2280 (dev->pdev->subsystem_device == 0x017d) ||
2281 (dev->pdev->subsystem_device == 0x017e) ||
2282 (dev->pdev->subsystem_device == 0x0183) ||
2283 (dev->pdev->subsystem_device == 0x018a) ||
2284 (dev->pdev->subsystem_device == 0x019a)))
2285 force_dac2 = true;
2286 break;
2287 }
2288
2289 if (force_dac2) {
2290 u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
2291 u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
2292 u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
2293
2294 /* For CRT on DAC2, don't turn it on if BIOS didn't
2295 enable it, even it's detected.
2296 */
2297
2298 /* force it to crtc0 */
2299 dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
2300 dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
2301 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
2302
2303 /* set up the TV DAC */
2304 tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL |
2305 RADEON_TV_DAC_STD_MASK |
2306 RADEON_TV_DAC_RDACPD |
2307 RADEON_TV_DAC_GDACPD |
2308 RADEON_TV_DAC_BDACPD |
2309 RADEON_TV_DAC_BGADJ_MASK |
2310 RADEON_TV_DAC_DACADJ_MASK);
2311 tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
2312 RADEON_TV_DAC_NHOLD |
2313 RADEON_TV_DAC_STD_PS2 |
2314 (0x58 << 16));
2315
2316 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
2317 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
2318 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
2319 }
d668046c
DA		 2320
2321 /* switch PM block to ACPI mode */
2322 tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL);
2323 tmp &= ~RADEON_PM_MODE_SEL;
2324 WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);
2325
92cde00c 2326}
771fe6b9
JG		 2327
2328/*
2329 * VRAM info
2330 */
2331static void r100_vram_get_type(struct radeon_device *rdev)
2332{
2333 uint32_t tmp;
2334
2335 rdev->mc.vram_is_ddr = false;
2336 if (rdev->flags & RADEON_IS_IGP)
2337 rdev->mc.vram_is_ddr = true;
2338 else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
2339 rdev->mc.vram_is_ddr = true;
2340 if ((rdev->family == CHIP_RV100) ||
2341 (rdev->family == CHIP_RS100) ||
2342 (rdev->family == CHIP_RS200)) {
2343 tmp = RREG32(RADEON_MEM_CNTL);
2344 if (tmp & RV100_HALF_MODE) {
2345 rdev->mc.vram_width = 32;
2346 } else {
2347 rdev->mc.vram_width = 64;
2348 }
2349 if (rdev->flags & RADEON_SINGLE_CRTC) {
2350 rdev->mc.vram_width /= 4;
2351 rdev->mc.vram_is_ddr = true;
2352 }
2353 } else if (rdev->family <= CHIP_RV280) {
2354 tmp = RREG32(RADEON_MEM_CNTL);
2355 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
2356 rdev->mc.vram_width = 128;
2357 } else {
2358 rdev->mc.vram_width = 64;
2359 }
2360 } else {
2361 /* newer IGPs */
2362 rdev->mc.vram_width = 128;
2363 }
2364}
2365
2a0f8918 2366static u32 r100_get_accessible_vram(struct radeon_device *rdev)
771fe6b9 2367{
2a0f8918
DA		 2368 u32 aper_size;
2369 u8 byte;
2370
2371 aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2372
2373 /* Set HDP_APER_CNTL only on cards that are known not to be broken,
2374 * that is has the 2nd generation multifunction PCI interface
2375 */
2376 if (rdev->family == CHIP_RV280 ||
2377 rdev->family >= CHIP_RV350) {
2378 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
2379 ~RADEON_HDP_APER_CNTL);
2380 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
2381 return aper_size * 2;
2382 }
2383
2384 /* Older cards have all sorts of funny issues to deal with. First
2385 * check if it's a multifunction card by reading the PCI config
2386 * header type... Limit those to one aperture size
2387 */
2388 pci_read_config_byte(rdev->pdev, 0xe, &byte);
2389 if (byte & 0x80) {
2390 DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
2391 DRM_INFO("Limiting VRAM to one aperture\n");
2392 return aper_size;
2393 }
2394
2395 /* Single function older card. We read HDP_APER_CNTL to see how the BIOS
2396 * have set it up. We don't write this as it's broken on some ASICs but
2397 * we expect the BIOS to have done the right thing (might be too optimistic...)
2398 */
2399 if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
2400 return aper_size * 2;
2401 return aper_size;
2402}
2403
2404void r100_vram_init_sizes(struct radeon_device *rdev)
2405{
2406 u64 config_aper_size;
2a0f8918 2407
d594e46a 2408 /* work out accessible VRAM */
01d73a69
JC		 2409 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
2410 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
51e5fcd3
JG		 2411 rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev);
2412 /* FIXME we don't use the second aperture yet when we could use it */
2413 if (rdev->mc.visible_vram_size > rdev->mc.aper_size)
2414 rdev->mc.visible_vram_size = rdev->mc.aper_size;
2a0f8918 2415 config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
771fe6b9
JG		 2416 if (rdev->flags & RADEON_IS_IGP) {
2417 uint32_t tom;
2418 /* read NB_TOM to get the amount of ram stolen for the GPU */
2419 tom = RREG32(RADEON_NB_TOM);
7a50f01a 2420 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
7a50f01a
DA		 2421 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2422 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
771fe6b9 2423 } else {
7a50f01a 2424 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
771fe6b9
JG		 2425 /* Some production boards of m6 will report 0
2426 * if it's 8 MB
2427 */
7a50f01a
DA		 2428 if (rdev->mc.real_vram_size == 0) {
2429 rdev->mc.real_vram_size = 8192 * 1024;
2430 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
771fe6b9 2431 }
d594e46a
JG		 2432 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
2433 * Novell bug 204882 + along with lots of ubuntu ones
2434 */
b7d8cce5
AD		 2435 if (rdev->mc.aper_size > config_aper_size)
2436 config_aper_size = rdev->mc.aper_size;
2437
7a50f01a
DA		 2438 if (config_aper_size > rdev->mc.real_vram_size)
2439 rdev->mc.mc_vram_size = config_aper_size;
2440 else
2441 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
771fe6b9 2442 }
2a0f8918
DA		 2443}
2444
28d52043
DA		 2445void r100_vga_set_state(struct radeon_device *rdev, bool state)
2446{
2447 uint32_t temp;
2448
2449 temp = RREG32(RADEON_CONFIG_CNTL);
2450 if (state == false) {
d75ee3be
AD		 2451 temp &= ~RADEON_CFG_VGA_RAM_EN;
2452 temp |= RADEON_CFG_VGA_IO_DIS;
28d52043 2453 } else {
d75ee3be 2454 temp &= ~RADEON_CFG_VGA_IO_DIS;
28d52043
DA		 2455 }
2456 WREG32(RADEON_CONFIG_CNTL, temp);
2457}
2458
d594e46a 2459void r100_mc_init(struct radeon_device *rdev)
2a0f8918 2460{
d594e46a 2461 u64 base;
2a0f8918 2462
d594e46a 2463 r100_vram_get_type(rdev);
2a0f8918 2464 r100_vram_init_sizes(rdev);
d594e46a
JG		 2465 base = rdev->mc.aper_base;
2466 if (rdev->flags & RADEON_IS_IGP)
2467 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
2468 radeon_vram_location(rdev, &rdev->mc, base);
8d369bb1 2469 rdev->mc.gtt_base_align = 0;
d594e46a
JG		 2470 if (!(rdev->flags & RADEON_IS_AGP))
2471 radeon_gtt_location(rdev, &rdev->mc);
f47299c5 2472 radeon_update_bandwidth_info(rdev);
771fe6b9
JG		 2473}
2474
2475
2476/*
2477 * Indirect registers accessor
2478 */
2479void r100_pll_errata_after_index(struct radeon_device *rdev)
2480{
4ce9198e
AD		 2481 if (rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS) {
2482 (void)RREG32(RADEON_CLOCK_CNTL_DATA);
2483 (void)RREG32(RADEON_CRTC_GEN_CNTL);
771fe6b9 2484 }
771fe6b9
JG		 2485}
2486
2487static void r100_pll_errata_after_data(struct radeon_device *rdev)
2488{
2489 /* This workarounds is necessary on RV100, RS100 and RS200 chips
2490 * or the chip could hang on a subsequent access
2491 */
2492 if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
2493 udelay(5000);
2494 }
2495
2496 /* This function is required to workaround a hardware bug in some (all?)
2497 * revisions of the R300. This workaround should be called after every
2498 * CLOCK_CNTL_INDEX register access. If not, register reads afterward
2499 * may not be correct.
2500 */
2501 if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
2502 uint32_t save, tmp;
2503
2504 save = RREG32(RADEON_CLOCK_CNTL_INDEX);
2505 tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
2506 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
2507 tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
2508 WREG32(RADEON_CLOCK_CNTL_INDEX, save);
2509 }
2510}
2511
2512uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
2513{
2514 uint32_t data;
2515
2516 WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
2517 r100_pll_errata_after_index(rdev);
2518 data = RREG32(RADEON_CLOCK_CNTL_DATA);
2519 r100_pll_errata_after_data(rdev);
2520 return data;
2521}
2522
2523void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2524{
2525 WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN));
2526 r100_pll_errata_after_index(rdev);
2527 WREG32(RADEON_CLOCK_CNTL_DATA, v);
2528 r100_pll_errata_after_data(rdev);
2529}
2530
d4550907 2531void r100_set_safe_registers(struct radeon_device *rdev)
068a117c 2532{
551ebd83
DA		 2533 if (ASIC_IS_RN50(rdev)) {
2534 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
2535 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
2536 } else if (rdev->family < CHIP_R200) {
2537 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
2538 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
2539 } else {
d4550907 2540 r200_set_safe_registers(rdev);
551ebd83 2541 }
068a117c
JG		 2542}
2543
771fe6b9
JG		 2544/*
2545 * Debugfs info
2546 */
2547#if defined(CONFIG_DEBUG_FS)
2548static int r100_debugfs_rbbm_info(struct seq_file *m, void *data)
2549{
2550 struct drm_info_node *node = (struct drm_info_node *) m->private;
2551 struct drm_device *dev = node->minor->dev;
2552 struct radeon_device *rdev = dev->dev_private;
2553 uint32_t reg, value;
2554 unsigned i;
2555
2556 seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
2557 seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
2558 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2559 for (i = 0; i < 64; i++) {
2560 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100);
2561 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
2562 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
2563 value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
2564 seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
2565 }
2566 return 0;
2567}
2568
2569static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data)
2570{
2571 struct drm_info_node *node = (struct drm_info_node *) m->private;
2572 struct drm_device *dev = node->minor->dev;
2573 struct radeon_device *rdev = dev->dev_private;
2574 uint32_t rdp, wdp;
2575 unsigned count, i, j;
2576
2577 radeon_ring_free_size(rdev);
2578 rdp = RREG32(RADEON_CP_RB_RPTR);
2579 wdp = RREG32(RADEON_CP_RB_WPTR);
2580 count = (rdp + rdev->cp.ring_size - wdp) & rdev->cp.ptr_mask;
2581 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2582 seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
2583 seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
2584 seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
2585 seq_printf(m, "%u dwords in ring\n", count);
2586 for (j = 0; j <= count; j++) {
2587 i = (rdp + j) & rdev->cp.ptr_mask;
2588 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
2589 }
2590 return 0;
2591}
2592
2593
2594static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data)
2595{
2596 struct drm_info_node *node = (struct drm_info_node *) m->private;
2597 struct drm_device *dev = node->minor->dev;
2598 struct radeon_device *rdev = dev->dev_private;
2599 uint32_t csq_stat, csq2_stat, tmp;
2600 unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
2601 unsigned i;
2602
2603 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2604 seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
2605 csq_stat = RREG32(RADEON_CP_CSQ_STAT);
2606 csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
2607 r_rptr = (csq_stat >> 0) & 0x3ff;
2608 r_wptr = (csq_stat >> 10) & 0x3ff;
2609 ib1_rptr = (csq_stat >> 20) & 0x3ff;
2610 ib1_wptr = (csq2_stat >> 0) & 0x3ff;
2611 ib2_rptr = (csq2_stat >> 10) & 0x3ff;
2612 ib2_wptr = (csq2_stat >> 20) & 0x3ff;
2613 seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
2614 seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
2615 seq_printf(m, "Ring rptr %u\n", r_rptr);
2616 seq_printf(m, "Ring wptr %u\n", r_wptr);
2617 seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
2618 seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
2619 seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
2620 seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
2621 /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
2622 * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
2623 seq_printf(m, "Ring fifo:\n");
2624 for (i = 0; i < 256; i++) {
2625 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2626 tmp = RREG32(RADEON_CP_CSQ_DATA);
2627 seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
2628 }
2629 seq_printf(m, "Indirect1 fifo:\n");
2630 for (i = 256; i <= 512; i++) {
2631 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2632 tmp = RREG32(RADEON_CP_CSQ_DATA);
2633 seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
2634 }
2635 seq_printf(m, "Indirect2 fifo:\n");
2636 for (i = 640; i < ib1_wptr; i++) {
2637 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2638 tmp = RREG32(RADEON_CP_CSQ_DATA);
2639 seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
2640 }
2641 return 0;
2642}
2643
2644static int r100_debugfs_mc_info(struct seq_file *m, void *data)
2645{
2646 struct drm_info_node *node = (struct drm_info_node *) m->private;
2647 struct drm_device *dev = node->minor->dev;
2648 struct radeon_device *rdev = dev->dev_private;
2649 uint32_t tmp;
2650
2651 tmp = RREG32(RADEON_CONFIG_MEMSIZE);
2652 seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
2653 tmp = RREG32(RADEON_MC_FB_LOCATION);
2654 seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
2655 tmp = RREG32(RADEON_BUS_CNTL);
2656 seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
2657 tmp = RREG32(RADEON_MC_AGP_LOCATION);
2658 seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
2659 tmp = RREG32(RADEON_AGP_BASE);
2660 seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
2661 tmp = RREG32(RADEON_HOST_PATH_CNTL);
2662 seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
2663 tmp = RREG32(0x01D0);
2664 seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
2665 tmp = RREG32(RADEON_AIC_LO_ADDR);
2666 seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
2667 tmp = RREG32(RADEON_AIC_HI_ADDR);
2668 seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
2669 tmp = RREG32(0x01E4);
2670 seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
2671 return 0;
2672}
2673
2674static struct drm_info_list r100_debugfs_rbbm_list[] = {
2675 {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL},
2676};
2677
2678static struct drm_info_list r100_debugfs_cp_list[] = {
2679 {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL},
2680 {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL},
2681};
2682
2683static struct drm_info_list r100_debugfs_mc_info_list[] = {
2684 {"r100_mc_info", r100_debugfs_mc_info, 0, NULL},
2685};
2686#endif
2687
2688int r100_debugfs_rbbm_init(struct radeon_device *rdev)
2689{
2690#if defined(CONFIG_DEBUG_FS)
2691 return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1);
2692#else
2693 return 0;
2694#endif
2695}
2696
2697int r100_debugfs_cp_init(struct radeon_device *rdev)
2698{
2699#if defined(CONFIG_DEBUG_FS)
2700 return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2);
2701#else
2702 return 0;
2703#endif
2704}
2705
2706int r100_debugfs_mc_info_init(struct radeon_device *rdev)
2707{
2708#if defined(CONFIG_DEBUG_FS)
2709 return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1);
2710#else
2711 return 0;
2712#endif
2713}
e024e110
DA		 2714
2715int r100_set_surface_reg(struct radeon_device *rdev, int reg,
2716 uint32_t tiling_flags, uint32_t pitch,
2717 uint32_t offset, uint32_t obj_size)
2718{
2719 int surf_index = reg * 16;
2720 int flags = 0;
2721
e024e110
DA		 2722 if (rdev->family <= CHIP_RS200) {
2723 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2724 == (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2725 flags |= RADEON_SURF_TILE_COLOR_BOTH;
2726 if (tiling_flags & RADEON_TILING_MACRO)
2727 flags |= RADEON_SURF_TILE_COLOR_MACRO;
2728 } else if (rdev->family <= CHIP_RV280) {
2729 if (tiling_flags & (RADEON_TILING_MACRO))
2730 flags |= R200_SURF_TILE_COLOR_MACRO;
2731 if (tiling_flags & RADEON_TILING_MICRO)
2732 flags |= R200_SURF_TILE_COLOR_MICRO;
2733 } else {
2734 if (tiling_flags & RADEON_TILING_MACRO)
2735 flags |= R300_SURF_TILE_MACRO;
2736 if (tiling_flags & RADEON_TILING_MICRO)
2737 flags |= R300_SURF_TILE_MICRO;
2738 }
2739
c88f9f0c
MD		 2740 if (tiling_flags & RADEON_TILING_SWAP_16BIT)
2741 flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP;
2742 if (tiling_flags & RADEON_TILING_SWAP_32BIT)
2743 flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP;
2744
f5c5f040
DA		 2745 /* when we aren't tiling the pitch seems to needs to be furtherdivided down. - tested on power5 + rn50 server */
2746 if (tiling_flags & (RADEON_TILING_SWAP_16BIT | RADEON_TILING_SWAP_32BIT)) {
2747 if (!(tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO)))
2748 if (ASIC_IS_RN50(rdev))
2749 pitch /= 16;
2750 }
2751
2752 /* r100/r200 divide by 16 */
2753 if (rdev->family < CHIP_R300)
2754 flags |= pitch / 16;
2755 else
2756 flags |= pitch / 8;
2757
2758
d9fdaafb 2759 DRM_DEBUG_KMS("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
e024e110
DA		 2760 WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
2761 WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
2762 WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);
2763 return 0;
2764}
2765
2766void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
2767{
2768 int surf_index = reg * 16;
2769 WREG32(RADEON_SURFACE0_INFO + surf_index, 0);
2770}
c93bb85b
JG		 2771
2772void r100_bandwidth_update(struct radeon_device *rdev)
2773{
2774 fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff;
2775 fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff;
2776 fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff;
2777 uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
2778 fixed20_12 memtcas_ff[8] = {
68adac5e
BS		 2779 dfixed_init(1),
2780 dfixed_init(2),
2781 dfixed_init(3),
2782 dfixed_init(0),
2783 dfixed_init_half(1),
2784 dfixed_init_half(2),
2785 dfixed_init(0),
c93bb85b
JG		 2786 };
2787 fixed20_12 memtcas_rs480_ff[8] = {
68adac5e
BS		 2788 dfixed_init(0),
2789 dfixed_init(1),
2790 dfixed_init(2),
2791 dfixed_init(3),
2792 dfixed_init(0),
2793 dfixed_init_half(1),
2794 dfixed_init_half(2),
2795 dfixed_init_half(3),
c93bb85b
JG		 2796 };
2797 fixed20_12 memtcas2_ff[8] = {
68adac5e
BS		 2798 dfixed_init(0),
2799 dfixed_init(1),
2800 dfixed_init(2),
2801 dfixed_init(3),
2802 dfixed_init(4),
2803 dfixed_init(5),
2804 dfixed_init(6),
2805 dfixed_init(7),
c93bb85b
JG		 2806 };
2807 fixed20_12 memtrbs[8] = {
68adac5e
BS		 2808 dfixed_init(1),
2809 dfixed_init_half(1),
2810 dfixed_init(2),
2811 dfixed_init_half(2),
2812 dfixed_init(3),
2813 dfixed_init_half(3),
2814 dfixed_init(4),
2815 dfixed_init_half(4)
c93bb85b
JG		 2816 };
2817 fixed20_12 memtrbs_r4xx[8] = {
68adac5e
BS		 2818 dfixed_init(4),
2819 dfixed_init(5),
2820 dfixed_init(6),
2821 dfixed_init(7),
2822 dfixed_init(8),
2823 dfixed_init(9),
2824 dfixed_init(10),
2825 dfixed_init(11)
c93bb85b
JG		 2826 };
2827 fixed20_12 min_mem_eff;
2828 fixed20_12 mc_latency_sclk, mc_latency_mclk, k1;
2829 fixed20_12 cur_latency_mclk, cur_latency_sclk;
2830 fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate,
2831 disp_drain_rate2, read_return_rate;
2832 fixed20_12 time_disp1_drop_priority;
2833 int c;
2834 int cur_size = 16; /* in octawords */
2835 int critical_point = 0, critical_point2;
2836/* uint32_t read_return_rate, time_disp1_drop_priority; */
2837 int stop_req, max_stop_req;
2838 struct drm_display_mode *mode1 = NULL;
2839 struct drm_display_mode *mode2 = NULL;
2840 uint32_t pixel_bytes1 = 0;
2841 uint32_t pixel_bytes2 = 0;
2842
f46c0120
AD		 2843 radeon_update_display_priority(rdev);
2844
c93bb85b
JG		 2845 if (rdev->mode_info.crtcs[0]->base.enabled) {
2846 mode1 = &rdev->mode_info.crtcs[0]->base.mode;
2847 pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8;
2848 }
dfee5614
DA		 2849 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
2850 if (rdev->mode_info.crtcs[1]->base.enabled) {
2851 mode2 = &rdev->mode_info.crtcs[1]->base.mode;
2852 pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8;
2853 }
c93bb85b
JG		 2854 }
2855
68adac5e 2856 min_mem_eff.full = dfixed_const_8(0);
c93bb85b
JG		 2857 /* get modes */
2858 if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
2859 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);
2860 mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT);
2861 mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT);
2862 /* check crtc enables */
2863 if (mode2)
2864 mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
2865 if (mode1)
2866 mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
2867 WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
2868 }
2869
2870 /*
2871 * determine is there is enough bw for current mode
2872 */
f47299c5
AD		 2873 sclk_ff = rdev->pm.sclk;
2874 mclk_ff = rdev->pm.mclk;
c93bb85b
JG		 2875
2876 temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
68adac5e
BS		 2877 temp_ff.full = dfixed_const(temp);
2878 mem_bw.full = dfixed_mul(mclk_ff, temp_ff);
c93bb85b
JG		 2879
2880 pix_clk.full = 0;
2881 pix_clk2.full = 0;
2882 peak_disp_bw.full = 0;
2883 if (mode1) {
68adac5e
BS		 2884 temp_ff.full = dfixed_const(1000);
2885 pix_clk.full = dfixed_const(mode1->clock); /* convert to fixed point */
2886 pix_clk.full = dfixed_div(pix_clk, temp_ff);
2887 temp_ff.full = dfixed_const(pixel_bytes1);
2888 peak_disp_bw.full += dfixed_mul(pix_clk, temp_ff);
c93bb85b
JG		 2889 }
2890 if (mode2) {
68adac5e
BS		 2891 temp_ff.full = dfixed_const(1000);
2892 pix_clk2.full = dfixed_const(mode2->clock); /* convert to fixed point */
2893 pix_clk2.full = dfixed_div(pix_clk2, temp_ff);
2894 temp_ff.full = dfixed_const(pixel_bytes2);
2895 peak_disp_bw.full += dfixed_mul(pix_clk2, temp_ff);
c93bb85b
JG		 2896 }
2897
68adac5e 2898 mem_bw.full = dfixed_mul(mem_bw, min_mem_eff);
c93bb85b
JG		 2899 if (peak_disp_bw.full >= mem_bw.full) {
2900 DRM_ERROR("You may not have enough display bandwidth for current mode\n"
2901 "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
2902 }
2903
2904 /* Get values from the EXT_MEM_CNTL register...converting its contents. */
2905 temp = RREG32(RADEON_MEM_TIMING_CNTL);
2906 if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
2907 mem_trcd = ((temp >> 2) & 0x3) + 1;
2908 mem_trp = ((temp & 0x3)) + 1;
2909 mem_tras = ((temp & 0x70) >> 4) + 1;
2910 } else if (rdev->family == CHIP_R300 ||
2911 rdev->family == CHIP_R350) { /* r300, r350 */
2912 mem_trcd = (temp & 0x7) + 1;
2913 mem_trp = ((temp >> 8) & 0x7) + 1;
2914 mem_tras = ((temp >> 11) & 0xf) + 4;
2915 } else if (rdev->family == CHIP_RV350 ||
2916 rdev->family <= CHIP_RV380) {
2917 /* rv3x0 */
2918 mem_trcd = (temp & 0x7) + 3;
2919 mem_trp = ((temp >> 8) & 0x7) + 3;
2920 mem_tras = ((temp >> 11) & 0xf) + 6;
2921 } else if (rdev->family == CHIP_R420 ||
2922 rdev->family == CHIP_R423 ||
2923 rdev->family == CHIP_RV410) {
2924 /* r4xx */
2925 mem_trcd = (temp & 0xf) + 3;
2926 if (mem_trcd > 15)
2927 mem_trcd = 15;
2928 mem_trp = ((temp >> 8) & 0xf) + 3;
2929 if (mem_trp > 15)
2930 mem_trp = 15;
2931 mem_tras = ((temp >> 12) & 0x1f) + 6;
2932 if (mem_tras > 31)
2933 mem_tras = 31;
2934 } else { /* RV200, R200 */
2935 mem_trcd = (temp & 0x7) + 1;
2936 mem_trp = ((temp >> 8) & 0x7) + 1;
2937 mem_tras = ((temp >> 12) & 0xf) + 4;
2938 }
2939 /* convert to FF */
68adac5e
BS		 2940 trcd_ff.full = dfixed_const(mem_trcd);
2941 trp_ff.full = dfixed_const(mem_trp);
2942 tras_ff.full = dfixed_const(mem_tras);
c93bb85b
JG		 2943
2944 /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
2945 temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2946 data = (temp & (7 << 20)) >> 20;
2947 if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) {
2948 if (rdev->family == CHIP_RS480) /* don't think rs400 */
2949 tcas_ff = memtcas_rs480_ff[data];
2950 else
2951 tcas_ff = memtcas_ff[data];
2952 } else
2953 tcas_ff = memtcas2_ff[data];
2954
2955 if (rdev->family == CHIP_RS400 ||
2956 rdev->family == CHIP_RS480) {
2957 /* extra cas latency stored in bits 23-25 0-4 clocks */
2958 data = (temp >> 23) & 0x7;
2959 if (data < 5)
68adac5e 2960 tcas_ff.full += dfixed_const(data);
c93bb85b
JG		 2961 }
2962
2963 if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
2964 /* on the R300, Tcas is included in Trbs.
2965 */
2966 temp = RREG32(RADEON_MEM_CNTL);
2967 data = (R300_MEM_NUM_CHANNELS_MASK & temp);
2968 if (data == 1) {
2969 if (R300_MEM_USE_CD_CH_ONLY & temp) {
2970 temp = RREG32(R300_MC_IND_INDEX);
2971 temp &= ~R300_MC_IND_ADDR_MASK;
2972 temp |= R300_MC_READ_CNTL_CD_mcind;
2973 WREG32(R300_MC_IND_INDEX, temp);
2974 temp = RREG32(R300_MC_IND_DATA);
2975 data = (R300_MEM_RBS_POSITION_C_MASK & temp);
2976 } else {
2977 temp = RREG32(R300_MC_READ_CNTL_AB);
2978 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2979 }
2980 } else {
2981 temp = RREG32(R300_MC_READ_CNTL_AB);
2982 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2983 }
2984 if (rdev->family == CHIP_RV410 ||
2985 rdev->family == CHIP_R420 ||
2986 rdev->family == CHIP_R423)
2987 trbs_ff = memtrbs_r4xx[data];
2988 else
2989 trbs_ff = memtrbs[data];
2990 tcas_ff.full += trbs_ff.full;
2991 }
2992
2993 sclk_eff_ff.full = sclk_ff.full;
2994
2995 if (rdev->flags & RADEON_IS_AGP) {
2996 fixed20_12 agpmode_ff;
68adac5e
BS		 2997 agpmode_ff.full = dfixed_const(radeon_agpmode);
2998 temp_ff.full = dfixed_const_666(16);
2999 sclk_eff_ff.full -= dfixed_mul(agpmode_ff, temp_ff);
c93bb85b
JG		 3000 }
3001 /* TODO PCIE lanes may affect this - agpmode == 16?? */
3002
3003 if (ASIC_IS_R300(rdev)) {
68adac5e 3004 sclk_delay_ff.full = dfixed_const(250);
c93bb85b
JG		 3005 } else {
3006 if ((rdev->family == CHIP_RV100) ||
3007 rdev->flags & RADEON_IS_IGP) {
3008 if (rdev->mc.vram_is_ddr)
68adac5e 3009 sclk_delay_ff.full = dfixed_const(41);
c93bb85b 3010 else
68adac5e 3011 sclk_delay_ff.full = dfixed_const(33);
c93bb85b
JG		 3012 } else {
3013 if (rdev->mc.vram_width == 128)
68adac5e 3014 sclk_delay_ff.full = dfixed_const(57);
c93bb85b 3015 else
68adac5e 3016 sclk_delay_ff.full = dfixed_const(41);
c93bb85b
JG		 3017 }
3018 }
3019
68adac5e 3020 mc_latency_sclk.full = dfixed_div(sclk_delay_ff, sclk_eff_ff);
c93bb85b
JG		 3021
3022 if (rdev->mc.vram_is_ddr) {
3023 if (rdev->mc.vram_width == 32) {
68adac5e 3024 k1.full = dfixed_const(40);
c93bb85b
JG		 3025 c = 3;
3026 } else {
68adac5e 3027 k1.full = dfixed_const(20);
c93bb85b
JG		 3028 c = 1;
3029 }
3030 } else {
68adac5e 3031 k1.full = dfixed_const(40);
c93bb85b
JG		 3032 c = 3;
3033 }
3034
68adac5e
BS		 3035 temp_ff.full = dfixed_const(2);
3036 mc_latency_mclk.full = dfixed_mul(trcd_ff, temp_ff);
3037 temp_ff.full = dfixed_const(c);
3038 mc_latency_mclk.full += dfixed_mul(tcas_ff, temp_ff);
3039 temp_ff.full = dfixed_const(4);
3040 mc_latency_mclk.full += dfixed_mul(tras_ff, temp_ff);
3041 mc_latency_mclk.full += dfixed_mul(trp_ff, temp_ff);
c93bb85b
JG		 3042 mc_latency_mclk.full += k1.full;
3043
68adac5e
BS		 3044 mc_latency_mclk.full = dfixed_div(mc_latency_mclk, mclk_ff);
3045 mc_latency_mclk.full += dfixed_div(temp_ff, sclk_eff_ff);
c93bb85b
JG		 3046
3047 /*
3048 HW cursor time assuming worst case of full size colour cursor.
3049 */
68adac5e 3050 temp_ff.full = dfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
c93bb85b
JG		 3051 temp_ff.full += trcd_ff.full;
3052 if (temp_ff.full < tras_ff.full)
3053 temp_ff.full = tras_ff.full;
68adac5e 3054 cur_latency_mclk.full = dfixed_div(temp_ff, mclk_ff);
c93bb85b 3055
68adac5e
BS		 3056 temp_ff.full = dfixed_const(cur_size);
3057 cur_latency_sclk.full = dfixed_div(temp_ff, sclk_eff_ff);
c93bb85b
JG		 3058 /*
3059 Find the total latency for the display data.
3060 */
68adac5e
BS		 3061 disp_latency_overhead.full = dfixed_const(8);
3062 disp_latency_overhead.full = dfixed_div(disp_latency_overhead, sclk_ff);
c93bb85b
JG		 3063 mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
3064 mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
3065
3066 if (mc_latency_mclk.full > mc_latency_sclk.full)
3067 disp_latency.full = mc_latency_mclk.full;
3068 else
3069 disp_latency.full = mc_latency_sclk.full;
3070
3071 /* setup Max GRPH_STOP_REQ default value */
3072 if (ASIC_IS_RV100(rdev))
3073 max_stop_req = 0x5c;
3074 else
3075 max_stop_req = 0x7c;
3076
3077 if (mode1) {
3078 /* CRTC1
3079 Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
3080 GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
3081 */
3082 stop_req = mode1->hdisplay * pixel_bytes1 / 16;
3083
3084 if (stop_req > max_stop_req)
3085 stop_req = max_stop_req;
3086
3087 /*
3088 Find the drain rate of the display buffer.
3089 */
68adac5e
BS		 3090 temp_ff.full = dfixed_const((16/pixel_bytes1));
3091 disp_drain_rate.full = dfixed_div(pix_clk, temp_ff);
c93bb85b
JG		 3092
3093 /*
3094 Find the critical point of the display buffer.
3095 */
68adac5e
BS		 3096 crit_point_ff.full = dfixed_mul(disp_drain_rate, disp_latency);
3097 crit_point_ff.full += dfixed_const_half(0);
c93bb85b 3098
68adac5e 3099 critical_point = dfixed_trunc(crit_point_ff);
c93bb85b
JG		 3100
3101 if (rdev->disp_priority == 2) {
3102 critical_point = 0;
3103 }
3104
3105 /*
3106 The critical point should never be above max_stop_req-4. Setting
3107 GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
3108 */
3109 if (max_stop_req - critical_point < 4)
3110 critical_point = 0;
3111
3112 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
3113 /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
3114 critical_point = 0x10;
3115 }
3116
3117 temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
3118 temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
3119 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3120 temp &= ~(RADEON_GRPH_START_REQ_MASK);
3121 if ((rdev->family == CHIP_R350) &&
3122 (stop_req > 0x15)) {
3123 stop_req -= 0x10;
3124 }
3125 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3126 temp |= RADEON_GRPH_BUFFER_SIZE;
3127 temp &= ~(RADEON_GRPH_CRITICAL_CNTL |
3128 RADEON_GRPH_CRITICAL_AT_SOF |
3129 RADEON_GRPH_STOP_CNTL);
3130 /*
3131 Write the result into the register.
3132 */
3133 WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3134 (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
3135
3136#if 0
3137 if ((rdev->family == CHIP_RS400) ||
3138 (rdev->family == CHIP_RS480)) {
3139 /* attempt to program RS400 disp regs correctly ??? */
3140 temp = RREG32(RS400_DISP1_REG_CNTL);
3141 temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK |
3142 RS400_DISP1_STOP_REQ_LEVEL_MASK);
3143 WREG32(RS400_DISP1_REQ_CNTL1, (temp |
3144 (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3145 (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3146 temp = RREG32(RS400_DMIF_MEM_CNTL1);
3147 temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK |
3148 RS400_DISP1_CRITICAL_POINT_STOP_MASK);
3149 WREG32(RS400_DMIF_MEM_CNTL1, (temp |
3150 (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) |
3151 (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
3152 }
3153#endif
3154
d9fdaafb 3155 DRM_DEBUG_KMS("GRPH_BUFFER_CNTL from to %x\n",
c93bb85b
JG		 3156 /* (unsigned int)info->SavedReg->grph_buffer_cntl, */
3157 (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
3158 }
3159
3160 if (mode2) {
3161 u32 grph2_cntl;
3162 stop_req = mode2->hdisplay * pixel_bytes2 / 16;
3163
3164 if (stop_req > max_stop_req)
3165 stop_req = max_stop_req;
3166
3167 /*
3168 Find the drain rate of the display buffer.
3169 */
68adac5e
BS		 3170 temp_ff.full = dfixed_const((16/pixel_bytes2));
3171 disp_drain_rate2.full = dfixed_div(pix_clk2, temp_ff);
c93bb85b
JG		 3172
3173 grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL);
3174 grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK);
3175 grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3176 grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK);
3177 if ((rdev->family == CHIP_R350) &&
3178 (stop_req > 0x15)) {
3179 stop_req -= 0x10;
3180 }
3181 grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3182 grph2_cntl |= RADEON_GRPH_BUFFER_SIZE;
3183 grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL |
3184 RADEON_GRPH_CRITICAL_AT_SOF |
3185 RADEON_GRPH_STOP_CNTL);
3186
3187 if ((rdev->family == CHIP_RS100) ||
3188 (rdev->family == CHIP_RS200))
3189 critical_point2 = 0;
3190 else {
3191 temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
68adac5e
BS		 3192 temp_ff.full = dfixed_const(temp);
3193 temp_ff.full = dfixed_mul(mclk_ff, temp_ff);
c93bb85b
JG		 3194 if (sclk_ff.full < temp_ff.full)
3195 temp_ff.full = sclk_ff.full;
3196
3197 read_return_rate.full = temp_ff.full;
3198
3199 if (mode1) {
3200 temp_ff.full = read_return_rate.full - disp_drain_rate.full;
68adac5e 3201 time_disp1_drop_priority.full = dfixed_div(crit_point_ff, temp_ff);
c93bb85b
JG		 3202 } else {
3203 time_disp1_drop_priority.full = 0;
3204 }
3205 crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full;
68adac5e
BS		 3206 crit_point_ff.full = dfixed_mul(crit_point_ff, disp_drain_rate2);
3207 crit_point_ff.full += dfixed_const_half(0);
c93bb85b 3208
68adac5e 3209 critical_point2 = dfixed_trunc(crit_point_ff);
c93bb85b
JG		 3210
3211 if (rdev->disp_priority == 2) {
3212 critical_point2 = 0;
3213 }
3214
3215 if (max_stop_req - critical_point2 < 4)
3216 critical_point2 = 0;
3217
3218 }
3219
3220 if (critical_point2 == 0 && rdev->family == CHIP_R300) {
3221 /* some R300 cards have problem with this set to 0 */
3222 critical_point2 = 0x10;
3223 }
3224
3225 WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3226 (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
3227
3228 if ((rdev->family == CHIP_RS400) ||
3229 (rdev->family == CHIP_RS480)) {
3230#if 0
3231 /* attempt to program RS400 disp2 regs correctly ??? */
3232 temp = RREG32(RS400_DISP2_REQ_CNTL1);
3233 temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK |
3234 RS400_DISP2_STOP_REQ_LEVEL_MASK);
3235 WREG32(RS400_DISP2_REQ_CNTL1, (temp |
3236 (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3237 (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3238 temp = RREG32(RS400_DISP2_REQ_CNTL2);
3239 temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK |
3240 RS400_DISP2_CRITICAL_POINT_STOP_MASK);
3241 WREG32(RS400_DISP2_REQ_CNTL2, (temp |
3242 (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) |
3243 (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT)));
3244#endif
3245 WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);
3246 WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000);
3247 WREG32(RS400_DMIF_MEM_CNTL1, 0x29CA71DC);
3248 WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
3249 }
3250
d9fdaafb 3251 DRM_DEBUG_KMS("GRPH2_BUFFER_CNTL from to %x\n",
c93bb85b
JG		 3252 (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
3253 }
3254}
551ebd83 3255
cbdd4501 3256static void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
551ebd83
DA		 3257{
3258 DRM_ERROR("pitch %d\n", t->pitch);
ceb776bc 3259 DRM_ERROR("use_pitch %d\n", t->use_pitch);
551ebd83 3260 DRM_ERROR("width %d\n", t->width);
ceb776bc 3261 DRM_ERROR("width_11 %d\n", t->width_11);
551ebd83 3262 DRM_ERROR("height %d\n", t->height);
ceb776bc 3263 DRM_ERROR("height_11 %d\n", t->height_11);
551ebd83
DA		 3264 DRM_ERROR("num levels %d\n", t->num_levels);
3265 DRM_ERROR("depth %d\n", t->txdepth);
3266 DRM_ERROR("bpp %d\n", t->cpp);
3267 DRM_ERROR("coordinate type %d\n", t->tex_coord_type);
3268 DRM_ERROR("width round to power of 2 %d\n", t->roundup_w);
3269 DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
d785d78b 3270 DRM_ERROR("compress format %d\n", t->compress_format);
551ebd83
DA		 3271}
3272
d785d78b
DA		 3273static int r100_track_compress_size(int compress_format, int w, int h)
3274{
3275 int block_width, block_height, block_bytes;
3276 int wblocks, hblocks;
3277 int min_wblocks;
3278 int sz;
3279
3280 block_width = 4;
3281 block_height = 4;
3282
3283 switch (compress_format) {
3284 case R100_TRACK_COMP_DXT1:
3285 block_bytes = 8;
3286 min_wblocks = 4;
3287 break;
3288 default:
3289 case R100_TRACK_COMP_DXT35:
3290 block_bytes = 16;
3291 min_wblocks = 2;
3292 break;
3293 }
3294
3295 hblocks = (h + block_height - 1) / block_height;
3296 wblocks = (w + block_width - 1) / block_width;
3297 if (wblocks < min_wblocks)
3298 wblocks = min_wblocks;
3299 sz = wblocks * hblocks * block_bytes;
3300 return sz;
3301}
3302
37cf6b03
RS		 3303static int r100_cs_track_cube(struct radeon_device *rdev,
3304 struct r100_cs_track *track, unsigned idx)
3305{
3306 unsigned face, w, h;
3307 struct radeon_bo *cube_robj;
3308 unsigned long size;
3309 unsigned compress_format = track->textures[idx].compress_format;
3310
3311 for (face = 0; face < 5; face++) {
3312 cube_robj = track->textures[idx].cube_info[face].robj;
3313 w = track->textures[idx].cube_info[face].width;
3314 h = track->textures[idx].cube_info[face].height;
3315
3316 if (compress_format) {
3317 size = r100_track_compress_size(compress_format, w, h);
3318 } else
3319 size = w * h;
3320 size *= track->textures[idx].cpp;
3321
3322 size += track->textures[idx].cube_info[face].offset;
3323
3324 if (size > radeon_bo_size(cube_robj)) {
3325 DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
3326 size, radeon_bo_size(cube_robj));
3327 r100_cs_track_texture_print(&track->textures[idx]);
3328 return -1;
3329 }
3330 }
3331 return 0;
3332}
3333
551ebd83
DA		 3334static int r100_cs_track_texture_check(struct radeon_device *rdev,
3335 struct r100_cs_track *track)
3336{
4c788679 3337 struct radeon_bo *robj;
551ebd83 3338 unsigned long size;
b73c5f8b 3339 unsigned u, i, w, h, d;
551ebd83
DA		 3340 int ret;
3341
3342 for (u = 0; u < track->num_texture; u++) {
3343 if (!track->textures[u].enabled)
3344 continue;
43b93fbf
AD		 3345 if (track->textures[u].lookup_disable)
3346 continue;
551ebd83
DA		 3347 robj = track->textures[u].robj;
3348 if (robj == NULL) {
3349 DRM_ERROR("No texture bound to unit %u\n", u);
3350 return -EINVAL;
3351 }
3352 size = 0;
3353 for (i = 0; i <= track->textures[u].num_levels; i++) {
3354 if (track->textures[u].use_pitch) {
3355 if (rdev->family < CHIP_R300)
3356 w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i);
3357 else
3358 w = track->textures[u].pitch / (1 << i);
3359 } else {
ceb776bc 3360 w = track->textures[u].width;
551ebd83
DA		 3361 if (rdev->family >= CHIP_RV515)
3362 w |= track->textures[u].width_11;
ceb776bc 3363 w = w / (1 << i);
551ebd83
DA		 3364 if (track->textures[u].roundup_w)
3365 w = roundup_pow_of_two(w);
3366 }
ceb776bc 3367 h = track->textures[u].height;
551ebd83
DA		 3368 if (rdev->family >= CHIP_RV515)
3369 h |= track->textures[u].height_11;
ceb776bc 3370 h = h / (1 << i);
551ebd83
DA		 3371 if (track->textures[u].roundup_h)
3372 h = roundup_pow_of_two(h);
b73c5f8b
MO		 3373 if (track->textures[u].tex_coord_type == 1) {
3374 d = (1 << track->textures[u].txdepth) / (1 << i);
3375 if (!d)
3376 d = 1;
3377 } else {
3378 d = 1;
3379 }
d785d78b
DA		 3380 if (track->textures[u].compress_format) {
3381
b73c5f8b 3382 size += r100_track_compress_size(track->textures[u].compress_format, w, h) * d;
d785d78b
DA		 3383 /* compressed textures are block based */
3384 } else
b73c5f8b 3385 size += w * h * d;
551ebd83
DA		 3386 }
3387 size *= track->textures[u].cpp;
d785d78b 3388
551ebd83
DA		 3389 switch (track->textures[u].tex_coord_type) {
3390 case 0:
551ebd83 3391 case 1:
551ebd83
DA		 3392 break;
3393 case 2:
3394 if (track->separate_cube) {
3395 ret = r100_cs_track_cube(rdev, track, u);
3396 if (ret)
3397 return ret;
3398 } else
3399 size *= 6;
3400 break;
3401 default:
3402 DRM_ERROR("Invalid texture coordinate type %u for unit "
3403 "%u\n", track->textures[u].tex_coord_type, u);
3404 return -EINVAL;
3405 }
4c788679 3406 if (size > radeon_bo_size(robj)) {
551ebd83 3407 DRM_ERROR("Texture of unit %u needs %lu bytes but is "
4c788679 3408 "%lu\n", u, size, radeon_bo_size(robj));
551ebd83
DA		 3409 r100_cs_track_texture_print(&track->textures[u]);
3410 return -EINVAL;
3411 }
3412 }
3413 return 0;
3414}
3415
3416int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
3417{
3418 unsigned i;
3419 unsigned long size;
3420 unsigned prim_walk;
3421 unsigned nverts;
40b4a759 3422 unsigned num_cb = track->cb_dirty ? track->num_cb : 0;
551ebd83 3423
40b4a759 3424 if (num_cb && !track->zb_cb_clear && !track->color_channel_mask &&
a41ceb1c
MO		 3425 !track->blend_read_enable)
3426 num_cb = 0;
3427
3428 for (i = 0; i < num_cb; i++) {
551ebd83
DA		 3429 if (track->cb[i].robj == NULL) {
3430 DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
3431 return -EINVAL;
3432 }
3433 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
3434 size += track->cb[i].offset;
4c788679 3435 if (size > radeon_bo_size(track->cb[i].robj)) {
551ebd83
DA		 3436 DRM_ERROR("[drm] Buffer too small for color buffer %d "
3437 "(need %lu have %lu) !\n", i, size,
4c788679 3438 radeon_bo_size(track->cb[i].robj));
551ebd83
DA		 3439 DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
3440 i, track->cb[i].pitch, track->cb[i].cpp,
3441 track->cb[i].offset, track->maxy);
3442 return -EINVAL;
3443 }
3444 }
40b4a759
MO		 3445 track->cb_dirty = false;
3446
3447 if (track->zb_dirty && track->z_enabled) {
551ebd83
DA		 3448 if (track->zb.robj == NULL) {
3449 DRM_ERROR("[drm] No buffer for z buffer !\n");
3450 return -EINVAL;
3451 }
3452 size = track->zb.pitch * track->zb.cpp * track->maxy;
3453 size += track->zb.offset;
4c788679 3454 if (size > radeon_bo_size(track->zb.robj)) {
551ebd83
DA		 3455 DRM_ERROR("[drm] Buffer too small for z buffer "
3456 "(need %lu have %lu) !\n", size,
4c788679 3457 radeon_bo_size(track->zb.robj));
551ebd83
DA		 3458 DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
3459 track->zb.pitch, track->zb.cpp,
3460 track->zb.offset, track->maxy);
3461 return -EINVAL;
3462 }
3463 }
40b4a759
MO		 3464 track->zb_dirty = false;
3465
fff1ce4d
MO		 3466 if (track->aa_dirty && track->aaresolve) {
3467 if (track->aa.robj == NULL) {
3468 DRM_ERROR("[drm] No buffer for AA resolve buffer %d !\n", i);
3469 return -EINVAL;
3470 }
3471 /* I believe the format comes from colorbuffer0. */
3472 size = track->aa.pitch * track->cb[0].cpp * track->maxy;
3473 size += track->aa.offset;
3474 if (size > radeon_bo_size(track->aa.robj)) {
3475 DRM_ERROR("[drm] Buffer too small for AA resolve buffer %d "
3476 "(need %lu have %lu) !\n", i, size,
3477 radeon_bo_size(track->aa.robj));
3478 DRM_ERROR("[drm] AA resolve buffer %d (%u %u %u %u)\n",
3479 i, track->aa.pitch, track->cb[0].cpp,
3480 track->aa.offset, track->maxy);
3481 return -EINVAL;
3482 }
3483 }
3484 track->aa_dirty = false;
3485
551ebd83 3486 prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
cae94b0a
MO		 3487 if (track->vap_vf_cntl & (1 << 14)) {
3488 nverts = track->vap_alt_nverts;
3489 } else {
3490 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
3491 }
551ebd83
DA		 3492 switch (prim_walk) {
3493 case 1:
3494 for (i = 0; i < track->num_arrays; i++) {
3495 size = track->arrays[i].esize * track->max_indx * 4;
3496 if (track->arrays[i].robj == NULL) {
3497 DRM_ERROR("(PW %u) Vertex array %u no buffer "
3498 "bound\n", prim_walk, i);
3499 return -EINVAL;
3500 }
4c788679
JG		 3501 if (size > radeon_bo_size(track->arrays[i].robj)) {
3502 dev_err(rdev->dev, "(PW %u) Vertex array %u "
3503 "need %lu dwords have %lu dwords\n",
3504 prim_walk, i, size >> 2,
3505 radeon_bo_size(track->arrays[i].robj)
3506 >> 2);
551ebd83
DA		 3507 DRM_ERROR("Max indices %u\n", track->max_indx);
3508 return -EINVAL;
3509 }
3510 }
3511 break;
3512 case 2:
3513 for (i = 0; i < track->num_arrays; i++) {
3514 size = track->arrays[i].esize * (nverts - 1) * 4;
3515 if (track->arrays[i].robj == NULL) {
3516 DRM_ERROR("(PW %u) Vertex array %u no buffer "
3517 "bound\n", prim_walk, i);
3518 return -EINVAL;
3519 }
4c788679
JG		 3520 if (size > radeon_bo_size(track->arrays[i].robj)) {
3521 dev_err(rdev->dev, "(PW %u) Vertex array %u "
3522 "need %lu dwords have %lu dwords\n",
3523 prim_walk, i, size >> 2,
3524 radeon_bo_size(track->arrays[i].robj)
3525 >> 2);
551ebd83
DA		 3526 return -EINVAL;
3527 }
3528 }
3529 break;
3530 case 3:
3531 size = track->vtx_size * nverts;
3532 if (size != track->immd_dwords) {
3533 DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
3534 track->immd_dwords, size);
3535 DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
3536 nverts, track->vtx_size);
3537 return -EINVAL;
3538 }
3539 break;
3540 default:
3541 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
3542 prim_walk);
3543 return -EINVAL;
3544 }
40b4a759
MO		 3545
3546 if (track->tex_dirty) {
3547 track->tex_dirty = false;
3548 return r100_cs_track_texture_check(rdev, track);
3549 }
3550 return 0;
551ebd83
DA		 3551}
3552
3553void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track)
3554{
3555 unsigned i, face;
3556
40b4a759
MO		 3557 track->cb_dirty = true;
3558 track->zb_dirty = true;
3559 track->tex_dirty = true;
fff1ce4d 3560 track->aa_dirty = true;
40b4a759 3561
551ebd83
DA		 3562 if (rdev->family < CHIP_R300) {
3563 track->num_cb = 1;
3564 if (rdev->family <= CHIP_RS200)
3565 track->num_texture = 3;
3566 else
3567 track->num_texture = 6;
3568 track->maxy = 2048;
3569 track->separate_cube = 1;
3570 } else {
3571 track->num_cb = 4;
3572 track->num_texture = 16;
3573 track->maxy = 4096;
3574 track->separate_cube = 0;
45e4039c 3575 track->aaresolve = false;
fff1ce4d 3576 track->aa.robj = NULL;
551ebd83
DA		 3577 }
3578
3579 for (i = 0; i < track->num_cb; i++) {
3580 track->cb[i].robj = NULL;
3581 track->cb[i].pitch = 8192;
3582 track->cb[i].cpp = 16;
3583 track->cb[i].offset = 0;
3584 }
3585 track->z_enabled = true;
3586 track->zb.robj = NULL;
3587 track->zb.pitch = 8192;
3588 track->zb.cpp = 4;
3589 track->zb.offset = 0;
3590 track->vtx_size = 0x7F;
3591 track->immd_dwords = 0xFFFFFFFFUL;
3592 track->num_arrays = 11;
3593 track->max_indx = 0x00FFFFFFUL;
3594 for (i = 0; i < track->num_arrays; i++) {
3595 track->arrays[i].robj = NULL;
3596 track->arrays[i].esize = 0x7F;
3597 }
3598 for (i = 0; i < track->num_texture; i++) {
d785d78b 3599 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
551ebd83
DA		 3600 track->textures[i].pitch = 16536;
3601 track->textures[i].width = 16536;
3602 track->textures[i].height = 16536;
3603 track->textures[i].width_11 = 1 << 11;
3604 track->textures[i].height_11 = 1 << 11;
3605 track->textures[i].num_levels = 12;
3606 if (rdev->family <= CHIP_RS200) {
3607 track->textures[i].tex_coord_type = 0;
3608 track->textures[i].txdepth = 0;
3609 } else {
3610 track->textures[i].txdepth = 16;
3611 track->textures[i].tex_coord_type = 1;
3612 }
3613 track->textures[i].cpp = 64;
3614 track->textures[i].robj = NULL;
3615 /* CS IB emission code makes sure texture unit are disabled */
3616 track->textures[i].enabled = false;
43b93fbf 3617 track->textures[i].lookup_disable = false;
551ebd83
DA		 3618 track->textures[i].roundup_w = true;
3619 track->textures[i].roundup_h = true;
3620 if (track->separate_cube)
3621 for (face = 0; face < 5; face++) {
3622 track->textures[i].cube_info[face].robj = NULL;
3623 track->textures[i].cube_info[face].width = 16536;
3624 track->textures[i].cube_info[face].height = 16536;
3625 track->textures[i].cube_info[face].offset = 0;
3626 }
3627 }
3628}
3ce0a23d
JG		 3629
3630int r100_ring_test(struct radeon_device *rdev)
3631{
3632 uint32_t scratch;
3633 uint32_t tmp = 0;
3634 unsigned i;
3635 int r;
3636
3637 r = radeon_scratch_get(rdev, &scratch);
3638 if (r) {
3639 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
3640 return r;
3641 }
3642 WREG32(scratch, 0xCAFEDEAD);
3643 r = radeon_ring_lock(rdev, 2);
3644 if (r) {
3645 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
3646 radeon_scratch_free(rdev, scratch);
3647 return r;
3648 }
3649 radeon_ring_write(rdev, PACKET0(scratch, 0));
3650 radeon_ring_write(rdev, 0xDEADBEEF);
3651 radeon_ring_unlock_commit(rdev);
3652 for (i = 0; i < rdev->usec_timeout; i++) {
3653 tmp = RREG32(scratch);
3654 if (tmp == 0xDEADBEEF) {
3655 break;
3656 }
3657 DRM_UDELAY(1);
3658 }
3659 if (i < rdev->usec_timeout) {
3660 DRM_INFO("ring test succeeded in %d usecs\n", i);
3661 } else {
369d7ec1 3662 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
3ce0a23d
JG		 3663 scratch, tmp);
3664 r = -EINVAL;
3665 }
3666 radeon_scratch_free(rdev, scratch);
3667 return r;
3668}
3669
3670void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3671{
3672 radeon_ring_write(rdev, PACKET0(RADEON_CP_IB_BASE, 1));
3673 radeon_ring_write(rdev, ib->gpu_addr);
3674 radeon_ring_write(rdev, ib->length_dw);
3675}
3676
3677int r100_ib_test(struct radeon_device *rdev)
3678{
3679 struct radeon_ib *ib;
3680 uint32_t scratch;
3681 uint32_t tmp = 0;
3682 unsigned i;
3683 int r;
3684
3685 r = radeon_scratch_get(rdev, &scratch);
3686 if (r) {
3687 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3688 return r;
3689 }
3690 WREG32(scratch, 0xCAFEDEAD);
3691 r = radeon_ib_get(rdev, &ib);
3692 if (r) {
3693 return r;
3694 }
3695 ib->ptr[0] = PACKET0(scratch, 0);
3696 ib->ptr[1] = 0xDEADBEEF;
3697 ib->ptr[2] = PACKET2(0);
3698 ib->ptr[3] = PACKET2(0);
3699 ib->ptr[4] = PACKET2(0);
3700 ib->ptr[5] = PACKET2(0);
3701 ib->ptr[6] = PACKET2(0);
3702 ib->ptr[7] = PACKET2(0);
3703 ib->length_dw = 8;
3704 r = radeon_ib_schedule(rdev, ib);
3705 if (r) {
3706 radeon_scratch_free(rdev, scratch);
3707 radeon_ib_free(rdev, &ib);
3708 return r;
3709 }
3710 r = radeon_fence_wait(ib->fence, false);
3711 if (r) {
3712 return r;
3713 }
3714 for (i = 0; i < rdev->usec_timeout; i++) {
3715 tmp = RREG32(scratch);
3716 if (tmp == 0xDEADBEEF) {
3717 break;
3718 }
3719 DRM_UDELAY(1);
3720 }
3721 if (i < rdev->usec_timeout) {
3722 DRM_INFO("ib test succeeded in %u usecs\n", i);
3723 } else {
62f288cf 3724 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
3ce0a23d
JG		 3725 scratch, tmp);
3726 r = -EINVAL;
3727 }
3728 radeon_scratch_free(rdev, scratch);
3729 radeon_ib_free(rdev, &ib);
3730 return r;
3731}
9f022ddf
JG		 3732
3733void r100_ib_fini(struct radeon_device *rdev)
3734{
3735 radeon_ib_pool_fini(rdev);
3736}
3737
3738int r100_ib_init(struct radeon_device *rdev)
3739{
3740 int r;
3741
3742 r = radeon_ib_pool_init(rdev);
3743 if (r) {
ec4f2ac4 3744 dev_err(rdev->dev, "failed initializing IB pool (%d).\n", r);
9f022ddf
JG		 3745 r100_ib_fini(rdev);
3746 return r;
3747 }
3748 r = r100_ib_test(rdev);
3749 if (r) {
ec4f2ac4 3750 dev_err(rdev->dev, "failed testing IB (%d).\n", r);
9f022ddf
JG		 3751 r100_ib_fini(rdev);
3752 return r;
3753 }
3754 return 0;
3755}
3756
3757void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
3758{
3759 /* Shutdown CP we shouldn't need to do that but better be safe than
3760 * sorry
3761 */
3762 rdev->cp.ready = false;
3763 WREG32(R_000740_CP_CSQ_CNTL, 0);
3764
3765 /* Save few CRTC registers */
ca6ffc64 3766 save->GENMO_WT = RREG8(R_0003C2_GENMO_WT);
9f022ddf
JG		 3767 save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
3768 save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
3769 save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
3770 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3771 save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL);
3772 save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET);
3773 }
3774
3775 /* Disable VGA aperture access */
ca6ffc64 3776 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT);
9f022ddf
JG		 3777 /* Disable cursor, overlay, crtc */
3778 WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1));
3779 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL |
3780 S_000054_CRTC_DISPLAY_DIS(1));
3781 WREG32(R_000050_CRTC_GEN_CNTL,
3782 (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) |
3783 S_000050_CRTC_DISP_REQ_EN_B(1));
3784 WREG32(R_000420_OV0_SCALE_CNTL,
3785 C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL));
3786 WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET);
3787 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3788 WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET |
3789 S_000360_CUR2_LOCK(1));
3790 WREG32(R_0003F8_CRTC2_GEN_CNTL,
3791 (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) |
3792 S_0003F8_CRTC2_DISPLAY_DIS(1) |
3793 S_0003F8_CRTC2_DISP_REQ_EN_B(1));
3794 WREG32(R_000360_CUR2_OFFSET,
3795 C_000360_CUR2_LOCK & save->CUR2_OFFSET);
3796 }
3797}
3798
3799void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save)
3800{
3801 /* Update base address for crtc */
d594e46a 3802 WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
9f022ddf 3803 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
d594e46a 3804 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
9f022ddf
JG		 3805 }
3806 /* Restore CRTC registers */
ca6ffc64 3807 WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);
9f022ddf
JG		 3808 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
3809 WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
3810 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3811 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
3812 }
3813}
ca6ffc64
JG		 3814
3815void r100_vga_render_disable(struct radeon_device *rdev)
3816{
d4550907 3817 u32 tmp;
ca6ffc64 3818
d4550907 3819 tmp = RREG8(R_0003C2_GENMO_WT);
ca6ffc64
JG		 3820 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);
3821}
d4550907
JG		 3822
3823static void r100_debugfs(struct radeon_device *rdev)
3824{
3825 int r;
3826
3827 r = r100_debugfs_mc_info_init(rdev);
3828 if (r)
3829 dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n");
3830}
3831
3832static void r100_mc_program(struct radeon_device *rdev)
3833{
3834 struct r100_mc_save save;
3835
3836 /* Stops all mc clients */
3837 r100_mc_stop(rdev, &save);
3838 if (rdev->flags & RADEON_IS_AGP) {
3839 WREG32(R_00014C_MC_AGP_LOCATION,
3840 S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
3841 S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
3842 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
3843 if (rdev->family > CHIP_RV200)
3844 WREG32(R_00015C_AGP_BASE_2,
3845 upper_32_bits(rdev->mc.agp_base) & 0xff);
3846 } else {
3847 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
3848 WREG32(R_000170_AGP_BASE, 0);
3849 if (rdev->family > CHIP_RV200)
3850 WREG32(R_00015C_AGP_BASE_2, 0);
3851 }
3852 /* Wait for mc idle */
3853 if (r100_mc_wait_for_idle(rdev))
3854 dev_warn(rdev->dev, "Wait for MC idle timeout.\n");
3855 /* Program MC, should be a 32bits limited address space */
3856 WREG32(R_000148_MC_FB_LOCATION,
3857 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
3858 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
3859 r100_mc_resume(rdev, &save);
3860}
3861
3862void r100_clock_startup(struct radeon_device *rdev)
3863{
3864 u32 tmp;
3865
3866 if (radeon_dynclks != -1 && radeon_dynclks)
3867 radeon_legacy_set_clock_gating(rdev, 1);
3868 /* We need to force on some of the block */
3869 tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
3870 tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
3871 if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280))
3872 tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1);
3873 WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
3874}
3875
3876static int r100_startup(struct radeon_device *rdev)
3877{
3878 int r;
3879
92cde00c
AD		 3880 /* set common regs */
3881 r100_set_common_regs(rdev);
3882 /* program mc */
d4550907
JG		 3883 r100_mc_program(rdev);
3884 /* Resume clock */
3885 r100_clock_startup(rdev);
d4550907
JG		 3886 /* Initialize GART (initialize after TTM so we can allocate
3887 * memory through TTM but finalize after TTM) */
17e15b0c 3888 r100_enable_bm(rdev);
d4550907
JG		 3889 if (rdev->flags & RADEON_IS_PCI) {
3890 r = r100_pci_gart_enable(rdev);
3891 if (r)
3892 return r;
3893 }
724c80e1
AD		 3894
3895 /* allocate wb buffer */
3896 r = radeon_wb_init(rdev);
3897 if (r)
3898 return r;
3899
d4550907 3900 /* Enable IRQ */
d4550907 3901 r100_irq_set(rdev);
cafe6609 3902 rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
d4550907
JG		 3903 /* 1M ring buffer */
3904 r = r100_cp_init(rdev, 1024 * 1024);
3905 if (r) {
ec4f2ac4 3906 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
d4550907
JG		 3907 return r;
3908 }
d4550907
JG		 3909 r = r100_ib_init(rdev);
3910 if (r) {
ec4f2ac4 3911 dev_err(rdev->dev, "failed initializing IB (%d).\n", r);
d4550907
JG		 3912 return r;
3913 }
3914 return 0;
3915}
3916
3917int r100_resume(struct radeon_device *rdev)
3918{
3919 /* Make sur GART are not working */
3920 if (rdev->flags & RADEON_IS_PCI)
3921 r100_pci_gart_disable(rdev);
3922 /* Resume clock before doing reset */
3923 r100_clock_startup(rdev);
3924 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
a2d07b74 3925 if (radeon_asic_reset(rdev)) {
d4550907
JG		 3926 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3927 RREG32(R_000E40_RBBM_STATUS),
3928 RREG32(R_0007C0_CP_STAT));
3929 }
3930 /* post */
3931 radeon_combios_asic_init(rdev->ddev);
3932 /* Resume clock after posting */
3933 r100_clock_startup(rdev);
550e2d92
DA		 3934 /* Initialize surface registers */
3935 radeon_surface_init(rdev);
d4550907
JG		 3936 return r100_startup(rdev);
3937}
3938
3939int r100_suspend(struct radeon_device *rdev)
3940{
3941 r100_cp_disable(rdev);
724c80e1 3942 radeon_wb_disable(rdev);
d4550907
JG		 3943 r100_irq_disable(rdev);
3944 if (rdev->flags & RADEON_IS_PCI)
3945 r100_pci_gart_disable(rdev);
3946 return 0;
3947}
3948
3949void r100_fini(struct radeon_device *rdev)
3950{
d4550907 3951 r100_cp_fini(rdev);
724c80e1 3952 radeon_wb_fini(rdev);
d4550907
JG		 3953 r100_ib_fini(rdev);
3954 radeon_gem_fini(rdev);
3955 if (rdev->flags & RADEON_IS_PCI)
3956 r100_pci_gart_fini(rdev);
d0269ed8 3957 radeon_agp_fini(rdev);
d4550907
JG		 3958 radeon_irq_kms_fini(rdev);
3959 radeon_fence_driver_fini(rdev);
4c788679 3960 radeon_bo_fini(rdev);
d4550907
JG		 3961 radeon_atombios_fini(rdev);
3962 kfree(rdev->bios);
3963 rdev->bios = NULL;
3964}
3965
4c712e6c
DA		 3966/*
3967 * Due to how kexec works, it can leave the hw fully initialised when it
3968 * boots the new kernel. However doing our init sequence with the CP and
3969 * WB stuff setup causes GPU hangs on the RN50 at least. So at startup
3970 * do some quick sanity checks and restore sane values to avoid this
3971 * problem.
3972 */
3973void r100_restore_sanity(struct radeon_device *rdev)
3974{
3975 u32 tmp;
3976
3977 tmp = RREG32(RADEON_CP_CSQ_CNTL);
3978 if (tmp) {
3979 WREG32(RADEON_CP_CSQ_CNTL, 0);
3980 }
3981 tmp = RREG32(RADEON_CP_RB_CNTL);
3982 if (tmp) {
3983 WREG32(RADEON_CP_RB_CNTL, 0);
3984 }
3985 tmp = RREG32(RADEON_SCRATCH_UMSK);
3986 if (tmp) {
3987 WREG32(RADEON_SCRATCH_UMSK, 0);
3988 }
3989}
3990
d4550907
JG		 3991int r100_init(struct radeon_device *rdev)
3992{
3993 int r;
3994
d4550907
JG		 3995 /* Register debugfs file specific to this group of asics */
3996 r100_debugfs(rdev);
3997 /* Disable VGA */
3998 r100_vga_render_disable(rdev);
3999 /* Initialize scratch registers */
4000 radeon_scratch_init(rdev);
4001 /* Initialize surface registers */
4002 radeon_surface_init(rdev);
4c712e6c
DA		 4003 /* sanity check some register to avoid hangs like after kexec */
4004 r100_restore_sanity(rdev);
d4550907
JG		 4005 /* TODO: disable VGA need to use VGA request */
4006 /* BIOS*/
4007 if (!radeon_get_bios(rdev)) {
4008 if (ASIC_IS_AVIVO(rdev))
4009 return -EINVAL;
4010 }
4011 if (rdev->is_atom_bios) {
4012 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
4013 return -EINVAL;
4014 } else {
4015 r = radeon_combios_init(rdev);
4016 if (r)
4017 return r;
4018 }
4019 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
a2d07b74 4020 if (radeon_asic_reset(rdev)) {
d4550907
JG		 4021 dev_warn(rdev->dev,
4022 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
4023 RREG32(R_000E40_RBBM_STATUS),
4024 RREG32(R_0007C0_CP_STAT));
4025 }
4026 /* check if cards are posted or not */
72542d77
DA		 4027 if (radeon_boot_test_post_card(rdev) == false)
4028 return -EINVAL;
d4550907
JG		 4029 /* Set asic errata */
4030 r100_errata(rdev);
4031 /* Initialize clocks */
4032 radeon_get_clock_info(rdev->ddev);
d594e46a
JG		 4033 /* initialize AGP */
4034 if (rdev->flags & RADEON_IS_AGP) {
4035 r = radeon_agp_init(rdev);
4036 if (r) {
4037 radeon_agp_disable(rdev);
4038 }
4039 }
4040 /* initialize VRAM */
4041 r100_mc_init(rdev);
d4550907
JG		 4042 /* Fence driver */
4043 r = radeon_fence_driver_init(rdev);
4044 if (r)
4045 return r;
4046 r = radeon_irq_kms_init(rdev);
4047 if (r)
4048 return r;
4049 /* Memory manager */
4c788679 4050 r = radeon_bo_init(rdev);
d4550907
JG		 4051 if (r)
4052 return r;
4053 if (rdev->flags & RADEON_IS_PCI) {
4054 r = r100_pci_gart_init(rdev);
4055 if (r)
4056 return r;
4057 }
4058 r100_set_safe_registers(rdev);
4059 rdev->accel_working = true;
4060 r = r100_startup(rdev);
4061 if (r) {
4062 /* Somethings want wront with the accel init stop accel */
4063 dev_err(rdev->dev, "Disabling GPU acceleration\n");
d4550907 4064 r100_cp_fini(rdev);
724c80e1 4065 radeon_wb_fini(rdev);
d4550907 4066 r100_ib_fini(rdev);
655efd3d 4067 radeon_irq_kms_fini(rdev);
d4550907
JG		 4068 if (rdev->flags & RADEON_IS_PCI)
4069 r100_pci_gart_fini(rdev);
d4550907
JG		 4070 rdev->accel_working = false;
4071 }
4072 return 0;
4073}
6fcbef7a
AK		 4074
4075uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
4076{
4077 if (reg < rdev->rmmio_size)
4078 return readl(((void __iomem *)rdev->rmmio) + reg);
4079 else {
4080 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
4081 return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
4082 }
4083}
4084
4085void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
4086{
4087 if (reg < rdev->rmmio_size)
4088 writel(v, ((void __iomem *)rdev->rmmio) + reg);
4089 else {
4090 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
4091 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
4092 }
4093}
4094
4095u32 r100_io_rreg(struct radeon_device *rdev, u32 reg)
4096{
4097 if (reg < rdev->rio_mem_size)
4098 return ioread32(rdev->rio_mem + reg);
4099 else {
4100 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
4101 return ioread32(rdev->rio_mem + RADEON_MM_DATA);
4102 }
4103}
4104
4105void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v)
4106{
4107 if (reg < rdev->rio_mem_size)
4108 iowrite32(v, rdev->rio_mem + reg);
4109 else {
4110 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
4111 iowrite32(v, rdev->rio_mem + RADEON_MM_DATA);
4112 }
4113}
Linux kernel - Deliverables
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