[deliverable/linux.git] / drivers / gpu / drm / radeon / r100_track.h


#define R100_TRACK_MAX_TEXTURE 3
#define R200_TRACK_MAX_TEXTURE 6
#define R300_TRACK_MAX_TEXTURE 16

#define R100_MAX_CB 1
#define R300_MAX_CB 4

/*
 * CS functions
 */
struct r100_cs_track_cb {
	struct radeon_bo	*robj;
	unsigned		pitch;
	unsigned		cpp;
	unsigned		offset;
};

struct r100_cs_track_array {
	struct radeon_bo	*robj;
	unsigned		esize;
};

struct r100_cs_cube_info {
	struct radeon_bo	*robj;
	unsigned		offset;
	unsigned		width;
	unsigned		height;
};

#define R100_TRACK_COMP_NONE   0
#define R100_TRACK_COMP_DXT1   1
#define R100_TRACK_COMP_DXT35  2

struct r100_cs_track_texture {
	struct radeon_bo	*robj;
	struct r100_cs_cube_info cube_info[5]; /* info for 5 non-primary faces */
	unsigned		pitch;
	unsigned		width;
	unsigned		height;
	unsigned		num_levels;
	unsigned		cpp;
	unsigned		tex_coord_type;
	unsigned		txdepth;
	unsigned		width_11;
	unsigned		height_11;
	bool			use_pitch;
	bool			enabled;
	bool                    lookup_disable;
	bool			roundup_w;
	bool			roundup_h;
	unsigned                compress_format;
};

struct r100_cs_track {
	unsigned			num_cb;
	unsigned                        num_texture;
	unsigned			maxy;
	unsigned			vtx_size;
	unsigned			vap_vf_cntl;
	unsigned			vap_alt_nverts;
	unsigned			immd_dwords;
	unsigned			num_arrays;
	unsigned			max_indx;
	unsigned			color_channel_mask;
	struct r100_cs_track_array	arrays[11];
	struct r100_cs_track_cb 	cb[R300_MAX_CB];
	struct r100_cs_track_cb 	zb;
	struct r100_cs_track_texture	textures[R300_TRACK_MAX_TEXTURE];
	bool				z_enabled;
	bool                            separate_cube;
	bool				zb_cb_clear;
	bool				blend_read_enable;

	bool				cb_dirty;
	bool				zb_dirty;
	bool				tex_dirty;
};

int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track);
void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track);
int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
			      struct radeon_cs_reloc **cs_reloc);
void r100_cs_dump_packet(struct radeon_cs_parser *p,
			 struct radeon_cs_packet *pkt);

int r100_cs_packet_parse_vline(struct radeon_cs_parser *p);

int r200_packet0_check(struct radeon_cs_parser *p,
		       struct radeon_cs_packet *pkt,
		       unsigned idx, unsigned reg);


static inline int r100_reloc_pitch_offset(struct radeon_cs_parser *p,
					  struct radeon_cs_packet *pkt,
					  unsigned idx,
					  unsigned reg)
{
	int r;
	u32 tile_flags = 0;
	u32 tmp;
	struct radeon_cs_reloc *reloc;
	u32 value;

	r = r100_cs_packet_next_reloc(p, &reloc);
	if (r) {
		DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
			  idx, reg);
		r100_cs_dump_packet(p, pkt);
		return r;
	}
	value = radeon_get_ib_value(p, idx);
	tmp = value & 0x003fffff;
	tmp += (((u32)reloc->lobj.gpu_offset) >> 10);

	if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
		tile_flags |= RADEON_DST_TILE_MACRO;
	if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
		if (reg == RADEON_SRC_PITCH_OFFSET) {
			DRM_ERROR("Cannot src blit from microtiled surface\n");
			r100_cs_dump_packet(p, pkt);
			return -EINVAL;
		}
		tile_flags |= RADEON_DST_TILE_MICRO;
	}

	tmp |= tile_flags;
	p->ib->ptr[idx] = (value & 0x3fc00000) | tmp;
	return 0;
}

static inline int r100_packet3_load_vbpntr(struct radeon_cs_parser *p,
					   struct radeon_cs_packet *pkt,
					   int idx)
{
	unsigned c, i;
	struct radeon_cs_reloc *reloc;
	struct r100_cs_track *track;
	int r = 0;
	volatile uint32_t *ib;
	u32 idx_value;

	ib = p->ib->ptr;
	track = (struct r100_cs_track *)p->track;
	c = radeon_get_ib_value(p, idx++) & 0x1F;
	track->num_arrays = c;
	for (i = 0; i < (c - 1); i+=2, idx+=3) {
		r = r100_cs_packet_next_reloc(p, &reloc);
		if (r) {
			DRM_ERROR("No reloc for packet3 %d\n",
				  pkt->opcode);
			r100_cs_dump_packet(p, pkt);
			return r;
		}
		idx_value = radeon_get_ib_value(p, idx);
		ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);

		track->arrays[i + 0].esize = idx_value >> 8;
		track->arrays[i + 0].robj = reloc->robj;
		track->arrays[i + 0].esize &= 0x7F;
		r = r100_cs_packet_next_reloc(p, &reloc);
		if (r) {
			DRM_ERROR("No reloc for packet3 %d\n",
				  pkt->opcode);
			r100_cs_dump_packet(p, pkt);
			return r;
		}
		ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->lobj.gpu_offset);
		track->arrays[i + 1].robj = reloc->robj;
		track->arrays[i + 1].esize = idx_value >> 24;
		track->arrays[i + 1].esize &= 0x7F;
	}
	if (c & 1) {
		r = r100_cs_packet_next_reloc(p, &reloc);
		if (r) {
			DRM_ERROR("No reloc for packet3 %d\n",
					  pkt->opcode);
			r100_cs_dump_packet(p, pkt);
			return r;
		}
		idx_value = radeon_get_ib_value(p, idx);
		ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
		track->arrays[i + 0].robj = reloc->robj;
		track->arrays[i + 0].esize = idx_value >> 8;
		track->arrays[i + 0].esize &= 0x7F;
	}
	return r;
}
Commit	Line	Data
551ebd83 DA	1
	2	#define R100_TRACK_MAX_TEXTURE 3
	3	#define R200_TRACK_MAX_TEXTURE 6
	4	#define R300_TRACK_MAX_TEXTURE 16
	5
	6	#define R100_MAX_CB 1
	7	#define R300_MAX_CB 4
	8
	9	/*
	10	* CS functions
	11	*/
	12	struct r100_cs_track_cb {
4c788679	13	struct radeon_bo *robj;
551ebd83 DA	14	unsigned pitch;
	15	unsigned cpp;
	16	unsigned offset;
	17	};
	18
	19	struct r100_cs_track_array {
4c788679	20	struct radeon_bo *robj;
551ebd83 DA	21	unsigned esize;
	22	};
	23
	24	struct r100_cs_cube_info {
4c788679 JG	25	struct radeon_bo *robj;
4c788679 JG	26	unsigned offset;
551ebd83 DA	27	unsigned width;
	28	unsigned height;
	29	};
	30
d785d78b DA	31	#define R100_TRACK_COMP_NONE 0
	32	#define R100_TRACK_COMP_DXT1 1
	33	#define R100_TRACK_COMP_DXT35 2
	34
551ebd83	35	struct r100_cs_track_texture {
4c788679	36	struct radeon_bo *robj;
551ebd83 DA	37	struct r100_cs_cube_info cube_info[5]; /* info for 5 non-primary faces */
	38	unsigned pitch;
	39	unsigned width;
	40	unsigned height;
	41	unsigned num_levels;
	42	unsigned cpp;
	43	unsigned tex_coord_type;
	44	unsigned txdepth;
	45	unsigned width_11;
	46	unsigned height_11;
	47	bool use_pitch;
	48	bool enabled;
43b93fbf	49	bool lookup_disable;
551ebd83 DA	50	bool roundup_w;
551ebd83 DA	51	bool roundup_h;
d785d78b	52	unsigned compress_format;
551ebd83 DA	53	};
551ebd83 DA	54
551ebd83	55	struct r100_cs_track {
551ebd83 DA	56	unsigned num_cb;
	57	unsigned num_texture;
	58	unsigned maxy;
	59	unsigned vtx_size;
	60	unsigned vap_vf_cntl;
cae94b0a	61	unsigned vap_alt_nverts;
551ebd83 DA	62	unsigned immd_dwords;
	63	unsigned num_arrays;
	64	unsigned max_indx;
46c64d4b	65	unsigned color_channel_mask;
551ebd83 DA	66	struct r100_cs_track_array arrays[11];
	67	struct r100_cs_track_cb cb[R300_MAX_CB];
	68	struct r100_cs_track_cb zb;
	69	struct r100_cs_track_texture textures[R300_TRACK_MAX_TEXTURE];
	70	bool z_enabled;
	71	bool separate_cube;
797fd5b9	72	bool zb_cb_clear;
46c64d4b	73	bool blend_read_enable;
40b4a759 MO	74
	75	bool cb_dirty;
	76	bool zb_dirty;
	77	bool tex_dirty;
551ebd83 DA	78	};
	79
	80	int r100_cs_track_check(struct radeon_device rdev, struct r100_cs_track track);
	81	void r100_cs_track_clear(struct radeon_device rdev, struct r100_cs_track track);
	82	int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
	83	struct radeon_cs_reloc **cs_reloc);
	84	void r100_cs_dump_packet(struct radeon_cs_parser *p,
	85	struct radeon_cs_packet *pkt);
	86
	87	int r100_cs_packet_parse_vline(struct radeon_cs_parser *p);
	88
	89	int r200_packet0_check(struct radeon_cs_parser *p,
	90	struct radeon_cs_packet *pkt,
	91	unsigned idx, unsigned reg);
	92
513bcb46 DA	93
513bcb46 DA	94
551ebd83 DA	95	static inline int r100_reloc_pitch_offset(struct radeon_cs_parser *p,
	96	struct radeon_cs_packet *pkt,
	97	unsigned idx,
	98	unsigned reg)
	99	{
	100	int r;
	101	u32 tile_flags = 0;
	102	u32 tmp;
	103	struct radeon_cs_reloc *reloc;
513bcb46	104	u32 value;
551ebd83 DA	105
	106	r = r100_cs_packet_next_reloc(p, &reloc);
	107	if (r) {
	108	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
	109	idx, reg);
	110	r100_cs_dump_packet(p, pkt);
	111	return r;
	112	}
513bcb46 DA	113	value = radeon_get_ib_value(p, idx);
513bcb46 DA	114	tmp = value & 0x003fffff;
551ebd83 DA	115	tmp += (((u32)reloc->lobj.gpu_offset) >> 10);
	116
	117	if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
	118	tile_flags \|= RADEON_DST_TILE_MACRO;
	119	if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
	120	if (reg == RADEON_SRC_PITCH_OFFSET) {
	121	DRM_ERROR("Cannot src blit from microtiled surface\n");
	122	r100_cs_dump_packet(p, pkt);
	123	return -EINVAL;
	124	}
	125	tile_flags \|= RADEON_DST_TILE_MICRO;
	126	}
	127
	128	tmp \|= tile_flags;
513bcb46	129	p->ib->ptr[idx] = (value & 0x3fc00000) \| tmp;
551ebd83 DA	130	return 0;
551ebd83 DA	131	}
513bcb46 DA	132
	133	static inline int r100_packet3_load_vbpntr(struct radeon_cs_parser *p,
	134	struct radeon_cs_packet *pkt,
	135	int idx)
	136	{
	137	unsigned c, i;
	138	struct radeon_cs_reloc *reloc;
	139	struct r100_cs_track *track;
	140	int r = 0;
	141	volatile uint32_t *ib;
	142	u32 idx_value;
	143
	144	ib = p->ib->ptr;
	145	track = (struct r100_cs_track *)p->track;
	146	c = radeon_get_ib_value(p, idx++) & 0x1F;
	147	track->num_arrays = c;
	148	for (i = 0; i < (c - 1); i+=2, idx+=3) {
	149	r = r100_cs_packet_next_reloc(p, &reloc);
	150	if (r) {
	151	DRM_ERROR("No reloc for packet3 %d\n",
	152	pkt->opcode);
	153	r100_cs_dump_packet(p, pkt);
	154	return r;
	155	}
	156	idx_value = radeon_get_ib_value(p, idx);
	157	ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
	158
	159	track->arrays[i + 0].esize = idx_value >> 8;
	160	track->arrays[i + 0].robj = reloc->robj;
	161	track->arrays[i + 0].esize &= 0x7F;
	162	r = r100_cs_packet_next_reloc(p, &reloc);
	163	if (r) {
	164	DRM_ERROR("No reloc for packet3 %d\n",
	165	pkt->opcode);
	166	r100_cs_dump_packet(p, pkt);
	167	return r;
	168	}
	169	ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->lobj.gpu_offset);
	170	track->arrays[i + 1].robj = reloc->robj;
	171	track->arrays[i + 1].esize = idx_value >> 24;
	172	track->arrays[i + 1].esize &= 0x7F;
	173	}
	174	if (c & 1) {
	175	r = r100_cs_packet_next_reloc(p, &reloc);
	176	if (r) {
	177	DRM_ERROR("No reloc for packet3 %d\n",
	178	pkt->opcode);
	179	r100_cs_dump_packet(p, pkt);
	180	return r;
	181	}
	182	idx_value = radeon_get_ib_value(p, idx);
	183	ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
	184	track->arrays[i + 0].robj = reloc->robj;
	185	track->arrays[i + 0].esize = idx_value >> 8;
	186	track->arrays[i + 0].esize &= 0x7F;
	187	}
	188	return r;
	189	}