projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 3ce0a23d JG |
1 | /* |
| 2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
| 3 | * Copyright 2008 Red Hat Inc. | |
| 4 | * Copyright 2009 Jerome Glisse. | |
| 5 | * | |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
| 7 | * copy of this software and associated documentation files (the "Software"), | |
| 8 | * to deal in the Software without restriction, including without limitation | |
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 10 | * and/or sell copies of the Software, and to permit persons to whom the | |
| 11 | * Software is furnished to do so, subject to the following conditions: | |
| 12 | * | |
| 13 | * The above copyright notice and this permission notice shall be included in | |
| 14 | * all copies or substantial portions of the Software. | |
| 15 | * | |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 22 | * OTHER DEALINGS IN THE SOFTWARE. | |
| 23 | * | |
| 24 | * Authors: Dave Airlie | |
| 25 | * Alex Deucher | |
| 26 | * Jerome Glisse | |
| 27 | */ | |
| 28 | #ifndef __R100D_H__ | |
| 29 | #define __R100D_H__ | |
| 30 | ||
| 31 | #define CP_PACKET0 0x00000000 | |
| 32 | #define PACKET0_BASE_INDEX_SHIFT 0 | |
| 33 | #define PACKET0_BASE_INDEX_MASK (0x1ffff << 0) | |
| 34 | #define PACKET0_COUNT_SHIFT 16 | |
| 35 | #define PACKET0_COUNT_MASK (0x3fff << 16) | |
| 36 | #define CP_PACKET1 0x40000000 | |
| 37 | #define CP_PACKET2 0x80000000 | |
| 38 | #define PACKET2_PAD_SHIFT 0 | |
| 39 | #define PACKET2_PAD_MASK (0x3fffffff << 0) | |
| 40 | #define CP_PACKET3 0xC0000000 | |
| 41 | #define PACKET3_IT_OPCODE_SHIFT 8 | |
| 42 | #define PACKET3_IT_OPCODE_MASK (0xff << 8) | |
| 43 | #define PACKET3_COUNT_SHIFT 16 | |
| 44 | #define PACKET3_COUNT_MASK (0x3fff << 16) | |
| 45 | /* PACKET3 op code */ | |
| 46 | #define PACKET3_NOP 0x10 | |
| 47 | #define PACKET3_3D_DRAW_VBUF 0x28 | |
| 48 | #define PACKET3_3D_DRAW_IMMD 0x29 | |
| 49 | #define PACKET3_3D_DRAW_INDX 0x2A | |
| 50 | #define PACKET3_3D_LOAD_VBPNTR 0x2F | |
| 51 | #define PACKET3_INDX_BUFFER 0x33 | |
| 52 | #define PACKET3_3D_DRAW_VBUF_2 0x34 | |
| 53 | #define PACKET3_3D_DRAW_IMMD_2 0x35 | |
| 54 | #define PACKET3_3D_DRAW_INDX_2 0x36 | |
| 55 | #define PACKET3_BITBLT_MULTI 0x9B | |
| 56 | ||
| 57 | #define PACKET0(reg, n) (CP_PACKET0 | \ | |
| 58 | REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) | \ | |
| 59 | REG_SET(PACKET0_COUNT, (n))) | |
| 60 | #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) | |
| 61 | #define PACKET3(op, n) (CP_PACKET3 | \ | |
| 62 | REG_SET(PACKET3_IT_OPCODE, (op)) | \ | |
| 63 | REG_SET(PACKET3_COUNT, (n))) | |
| 64 | ||
| 65 | #define PACKET_TYPE0 0 | |
| 66 | #define PACKET_TYPE1 1 | |
| 67 | #define PACKET_TYPE2 2 | |
| 68 | #define PACKET_TYPE3 3 | |
| 69 | ||
| 70 | #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) | |
| 71 | #define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) | |
| 72 | #define CP_PACKET0_GET_REG(h) (((h) & 0x1FFF) << 2) | |
| 73 | #define CP_PACKET0_GET_ONE_REG_WR(h) (((h) >> 15) & 1) | |
| 74 | #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) | |
| 75 | ||
| 45600232 | 76 | /* Registers */ |
| 9f022ddf JG |
77 | #define R_000040_GEN_INT_CNTL 0x000040 |
| 78 | #define S_000040_CRTC_VBLANK(x) (((x) & 0x1) << 0) | |
| 79 | #define G_000040_CRTC_VBLANK(x) (((x) >> 0) & 0x1) | |
| 80 | #define C_000040_CRTC_VBLANK 0xFFFFFFFE | |
| 81 | #define S_000040_CRTC_VLINE(x) (((x) & 0x1) << 1) | |
| 82 | #define G_000040_CRTC_VLINE(x) (((x) >> 1) & 0x1) | |
| 83 | #define C_000040_CRTC_VLINE 0xFFFFFFFD | |
| 84 | #define S_000040_CRTC_VSYNC(x) (((x) & 0x1) << 2) | |
| 85 | #define G_000040_CRTC_VSYNC(x) (((x) >> 2) & 0x1) | |
| 86 | #define C_000040_CRTC_VSYNC 0xFFFFFFFB | |
| 87 | #define S_000040_SNAPSHOT(x) (((x) & 0x1) << 3) | |
| 88 | #define G_000040_SNAPSHOT(x) (((x) >> 3) & 0x1) | |
| 89 | #define C_000040_SNAPSHOT 0xFFFFFFF7 | |
| 90 | #define S_000040_FP_DETECT(x) (((x) & 0x1) << 4) | |
| 91 | #define G_000040_FP_DETECT(x) (((x) >> 4) & 0x1) | |
| 92 | #define C_000040_FP_DETECT 0xFFFFFFEF | |
| 93 | #define S_000040_CRTC2_VLINE(x) (((x) & 0x1) << 5) | |
| 94 | #define G_000040_CRTC2_VLINE(x) (((x) >> 5) & 0x1) | |
| 95 | #define C_000040_CRTC2_VLINE 0xFFFFFFDF | |
| 96 | #define S_000040_DMA_VIPH0_INT_EN(x) (((x) & 0x1) << 12) | |
| 97 | #define G_000040_DMA_VIPH0_INT_EN(x) (((x) >> 12) & 0x1) | |
| 98 | #define C_000040_DMA_VIPH0_INT_EN 0xFFFFEFFF | |
| 99 | #define S_000040_CRTC2_VSYNC(x) (((x) & 0x1) << 6) | |
| 100 | #define G_000040_CRTC2_VSYNC(x) (((x) >> 6) & 0x1) | |
| 101 | #define C_000040_CRTC2_VSYNC 0xFFFFFFBF | |
| 102 | #define S_000040_SNAPSHOT2(x) (((x) & 0x1) << 7) | |
| 103 | #define G_000040_SNAPSHOT2(x) (((x) >> 7) & 0x1) | |
| 104 | #define C_000040_SNAPSHOT2 0xFFFFFF7F | |
| 105 | #define S_000040_CRTC2_VBLANK(x) (((x) & 0x1) << 9) | |
| 106 | #define G_000040_CRTC2_VBLANK(x) (((x) >> 9) & 0x1) | |
| 107 | #define C_000040_CRTC2_VBLANK 0xFFFFFDFF | |
| 108 | #define S_000040_FP2_DETECT(x) (((x) & 0x1) << 10) | |
| 109 | #define G_000040_FP2_DETECT(x) (((x) >> 10) & 0x1) | |
| 110 | #define C_000040_FP2_DETECT 0xFFFFFBFF | |
| 111 | #define S_000040_VSYNC_DIFF_OVER_LIMIT(x) (((x) & 0x1) << 11) | |
| 112 | #define G_000040_VSYNC_DIFF_OVER_LIMIT(x) (((x) >> 11) & 0x1) | |
| 113 | #define C_000040_VSYNC_DIFF_OVER_LIMIT 0xFFFFF7FF | |
| 114 | #define S_000040_DMA_VIPH1_INT_EN(x) (((x) & 0x1) << 13) | |
| 115 | #define G_000040_DMA_VIPH1_INT_EN(x) (((x) >> 13) & 0x1) | |
| 116 | #define C_000040_DMA_VIPH1_INT_EN 0xFFFFDFFF | |
| 117 | #define S_000040_DMA_VIPH2_INT_EN(x) (((x) & 0x1) << 14) | |
| 118 | #define G_000040_DMA_VIPH2_INT_EN(x) (((x) >> 14) & 0x1) | |
| 119 | #define C_000040_DMA_VIPH2_INT_EN 0xFFFFBFFF | |
| 120 | #define S_000040_DMA_VIPH3_INT_EN(x) (((x) & 0x1) << 15) | |
| 121 | #define G_000040_DMA_VIPH3_INT_EN(x) (((x) >> 15) & 0x1) | |
| 122 | #define C_000040_DMA_VIPH3_INT_EN 0xFFFF7FFF | |
| 123 | #define S_000040_I2C_INT_EN(x) (((x) & 0x1) << 17) | |
| 124 | #define G_000040_I2C_INT_EN(x) (((x) >> 17) & 0x1) | |
| 125 | #define C_000040_I2C_INT_EN 0xFFFDFFFF | |
| 126 | #define S_000040_GUI_IDLE(x) (((x) & 0x1) << 19) | |
| 127 | #define G_000040_GUI_IDLE(x) (((x) >> 19) & 0x1) | |
| 128 | #define C_000040_GUI_IDLE 0xFFF7FFFF | |
| 129 | #define S_000040_VIPH_INT_EN(x) (((x) & 0x1) << 24) | |
| 130 | #define G_000040_VIPH_INT_EN(x) (((x) >> 24) & 0x1) | |
| 131 | #define C_000040_VIPH_INT_EN 0xFEFFFFFF | |
| 132 | #define S_000040_SW_INT_EN(x) (((x) & 0x1) << 25) | |
| 133 | #define G_000040_SW_INT_EN(x) (((x) >> 25) & 0x1) | |
| 134 | #define C_000040_SW_INT_EN 0xFDFFFFFF | |
| 135 | #define S_000040_GEYSERVILLE(x) (((x) & 0x1) << 27) | |
| 136 | #define G_000040_GEYSERVILLE(x) (((x) >> 27) & 0x1) | |
| 137 | #define C_000040_GEYSERVILLE 0xF7FFFFFF | |
| 138 | #define S_000040_HDCP_AUTHORIZED_INT(x) (((x) & 0x1) << 28) | |
| 139 | #define G_000040_HDCP_AUTHORIZED_INT(x) (((x) >> 28) & 0x1) | |
| 140 | #define C_000040_HDCP_AUTHORIZED_INT 0xEFFFFFFF | |
| 141 | #define S_000040_DVI_I2C_INT(x) (((x) & 0x1) << 29) | |
| 142 | #define G_000040_DVI_I2C_INT(x) (((x) >> 29) & 0x1) | |
| 143 | #define C_000040_DVI_I2C_INT 0xDFFFFFFF | |
| 144 | #define S_000040_GUIDMA(x) (((x) & 0x1) << 30) | |
| 145 | #define G_000040_GUIDMA(x) (((x) >> 30) & 0x1) | |
| 146 | #define C_000040_GUIDMA 0xBFFFFFFF | |
| 147 | #define S_000040_VIDDMA(x) (((x) & 0x1) << 31) | |
| 148 | #define G_000040_VIDDMA(x) (((x) >> 31) & 0x1) | |
| 149 | #define C_000040_VIDDMA 0x7FFFFFFF | |
| 150 | #define R_000044_GEN_INT_STATUS 0x000044 | |
| 151 | #define S_000044_CRTC_VBLANK_STAT(x) (((x) & 0x1) << 0) | |
| 152 | #define G_000044_CRTC_VBLANK_STAT(x) (((x) >> 0) & 0x1) | |
| 153 | #define C_000044_CRTC_VBLANK_STAT 0xFFFFFFFE | |
| 154 | #define S_000044_CRTC_VBLANK_STAT_AK(x) (((x) & 0x1) << 0) | |
| 155 | #define G_000044_CRTC_VBLANK_STAT_AK(x) (((x) >> 0) & 0x1) | |
| 156 | #define C_000044_CRTC_VBLANK_STAT_AK 0xFFFFFFFE | |
| 157 | #define S_000044_CRTC_VLINE_STAT(x) (((x) & 0x1) << 1) | |
| 158 | #define G_000044_CRTC_VLINE_STAT(x) (((x) >> 1) & 0x1) | |
| 159 | #define C_000044_CRTC_VLINE_STAT 0xFFFFFFFD | |
| 160 | #define S_000044_CRTC_VLINE_STAT_AK(x) (((x) & 0x1) << 1) | |
| 161 | #define G_000044_CRTC_VLINE_STAT_AK(x) (((x) >> 1) & 0x1) | |
| 162 | #define C_000044_CRTC_VLINE_STAT_AK 0xFFFFFFFD | |
| 163 | #define S_000044_CRTC_VSYNC_STAT(x) (((x) & 0x1) << 2) | |
| 164 | #define G_000044_CRTC_VSYNC_STAT(x) (((x) >> 2) & 0x1) | |
| 165 | #define C_000044_CRTC_VSYNC_STAT 0xFFFFFFFB | |
| 166 | #define S_000044_CRTC_VSYNC_STAT_AK(x) (((x) & 0x1) << 2) | |
| 167 | #define G_000044_CRTC_VSYNC_STAT_AK(x) (((x) >> 2) & 0x1) | |
| 168 | #define C_000044_CRTC_VSYNC_STAT_AK 0xFFFFFFFB | |
| 169 | #define S_000044_SNAPSHOT_STAT(x) (((x) & 0x1) << 3) | |
| 170 | #define G_000044_SNAPSHOT_STAT(x) (((x) >> 3) & 0x1) | |
| 171 | #define C_000044_SNAPSHOT_STAT 0xFFFFFFF7 | |
| 172 | #define S_000044_SNAPSHOT_STAT_AK(x) (((x) & 0x1) << 3) | |
| 173 | #define G_000044_SNAPSHOT_STAT_AK(x) (((x) >> 3) & 0x1) | |
| 174 | #define C_000044_SNAPSHOT_STAT_AK 0xFFFFFFF7 | |
| 175 | #define S_000044_FP_DETECT_STAT(x) (((x) & 0x1) << 4) | |
| 176 | #define G_000044_FP_DETECT_STAT(x) (((x) >> 4) & 0x1) | |
| 177 | #define C_000044_FP_DETECT_STAT 0xFFFFFFEF | |
| 178 | #define S_000044_FP_DETECT_STAT_AK(x) (((x) & 0x1) << 4) | |
| 179 | #define G_000044_FP_DETECT_STAT_AK(x) (((x) >> 4) & 0x1) | |
| 180 | #define C_000044_FP_DETECT_STAT_AK 0xFFFFFFEF | |
| 181 | #define S_000044_CRTC2_VLINE_STAT(x) (((x) & 0x1) << 5) | |
| 182 | #define G_000044_CRTC2_VLINE_STAT(x) (((x) >> 5) & 0x1) | |
| 183 | #define C_000044_CRTC2_VLINE_STAT 0xFFFFFFDF | |
| 184 | #define S_000044_CRTC2_VLINE_STAT_AK(x) (((x) & 0x1) << 5) | |
| 185 | #define G_000044_CRTC2_VLINE_STAT_AK(x) (((x) >> 5) & 0x1) | |
| 186 | #define C_000044_CRTC2_VLINE_STAT_AK 0xFFFFFFDF | |
| 187 | #define S_000044_CRTC2_VSYNC_STAT(x) (((x) & 0x1) << 6) | |
| 188 | #define G_000044_CRTC2_VSYNC_STAT(x) (((x) >> 6) & 0x1) | |
| 189 | #define C_000044_CRTC2_VSYNC_STAT 0xFFFFFFBF | |
| 190 | #define S_000044_CRTC2_VSYNC_STAT_AK(x) (((x) & 0x1) << 6) | |
| 191 | #define G_000044_CRTC2_VSYNC_STAT_AK(x) (((x) >> 6) & 0x1) | |
| 192 | #define C_000044_CRTC2_VSYNC_STAT_AK 0xFFFFFFBF | |
| 193 | #define S_000044_SNAPSHOT2_STAT(x) (((x) & 0x1) << 7) | |
| 194 | #define G_000044_SNAPSHOT2_STAT(x) (((x) >> 7) & 0x1) | |
| 195 | #define C_000044_SNAPSHOT2_STAT 0xFFFFFF7F | |
| 196 | #define S_000044_SNAPSHOT2_STAT_AK(x) (((x) & 0x1) << 7) | |
| 197 | #define G_000044_SNAPSHOT2_STAT_AK(x) (((x) >> 7) & 0x1) | |
| 198 | #define C_000044_SNAPSHOT2_STAT_AK 0xFFFFFF7F | |
| 199 | #define S_000044_CAP0_INT_ACTIVE(x) (((x) & 0x1) << 8) | |
| 200 | #define G_000044_CAP0_INT_ACTIVE(x) (((x) >> 8) & 0x1) | |
| 201 | #define C_000044_CAP0_INT_ACTIVE 0xFFFFFEFF | |
| 202 | #define S_000044_CRTC2_VBLANK_STAT(x) (((x) & 0x1) << 9) | |
| 203 | #define G_000044_CRTC2_VBLANK_STAT(x) (((x) >> 9) & 0x1) | |
| 204 | #define C_000044_CRTC2_VBLANK_STAT 0xFFFFFDFF | |
| 205 | #define S_000044_CRTC2_VBLANK_STAT_AK(x) (((x) & 0x1) << 9) | |
| 206 | #define G_000044_CRTC2_VBLANK_STAT_AK(x) (((x) >> 9) & 0x1) | |
| 207 | #define C_000044_CRTC2_VBLANK_STAT_AK 0xFFFFFDFF | |
| 208 | #define S_000044_FP2_DETECT_STAT(x) (((x) & 0x1) << 10) | |
| 209 | #define G_000044_FP2_DETECT_STAT(x) (((x) >> 10) & 0x1) | |
| 210 | #define C_000044_FP2_DETECT_STAT 0xFFFFFBFF | |
| 211 | #define S_000044_FP2_DETECT_STAT_AK(x) (((x) & 0x1) << 10) | |
| 212 | #define G_000044_FP2_DETECT_STAT_AK(x) (((x) >> 10) & 0x1) | |
| 213 | #define C_000044_FP2_DETECT_STAT_AK 0xFFFFFBFF | |
| 214 | #define S_000044_VSYNC_DIFF_OVER_LIMIT_STAT(x) (((x) & 0x1) << 11) | |
| 215 | #define G_000044_VSYNC_DIFF_OVER_LIMIT_STAT(x) (((x) >> 11) & 0x1) | |
| 216 | #define C_000044_VSYNC_DIFF_OVER_LIMIT_STAT 0xFFFFF7FF | |
| 217 | #define S_000044_VSYNC_DIFF_OVER_LIMIT_STAT_AK(x) (((x) & 0x1) << 11) | |
| 218 | #define G_000044_VSYNC_DIFF_OVER_LIMIT_STAT_AK(x) (((x) >> 11) & 0x1) | |
| 219 | #define C_000044_VSYNC_DIFF_OVER_LIMIT_STAT_AK 0xFFFFF7FF | |
| 220 | #define S_000044_DMA_VIPH0_INT(x) (((x) & 0x1) << 12) | |
| 221 | #define G_000044_DMA_VIPH0_INT(x) (((x) >> 12) & 0x1) | |
| 222 | #define C_000044_DMA_VIPH0_INT 0xFFFFEFFF | |
| 223 | #define S_000044_DMA_VIPH0_INT_AK(x) (((x) & 0x1) << 12) | |
| 224 | #define G_000044_DMA_VIPH0_INT_AK(x) (((x) >> 12) & 0x1) | |
| 225 | #define C_000044_DMA_VIPH0_INT_AK 0xFFFFEFFF | |
| 226 | #define S_000044_DMA_VIPH1_INT(x) (((x) & 0x1) << 13) | |
| 227 | #define G_000044_DMA_VIPH1_INT(x) (((x) >> 13) & 0x1) | |
| 228 | #define C_000044_DMA_VIPH1_INT 0xFFFFDFFF | |
| 229 | #define S_000044_DMA_VIPH1_INT_AK(x) (((x) & 0x1) << 13) | |
| 230 | #define G_000044_DMA_VIPH1_INT_AK(x) (((x) >> 13) & 0x1) | |
| 231 | #define C_000044_DMA_VIPH1_INT_AK 0xFFFFDFFF | |
| 232 | #define S_000044_DMA_VIPH2_INT(x) (((x) & 0x1) << 14) | |
| 233 | #define G_000044_DMA_VIPH2_INT(x) (((x) >> 14) & 0x1) | |
| 234 | #define C_000044_DMA_VIPH2_INT 0xFFFFBFFF | |
| 235 | #define S_000044_DMA_VIPH2_INT_AK(x) (((x) & 0x1) << 14) | |
| 236 | #define G_000044_DMA_VIPH2_INT_AK(x) (((x) >> 14) & 0x1) | |
| 237 | #define C_000044_DMA_VIPH2_INT_AK 0xFFFFBFFF | |
| 238 | #define S_000044_DMA_VIPH3_INT(x) (((x) & 0x1) << 15) | |
| 239 | #define G_000044_DMA_VIPH3_INT(x) (((x) >> 15) & 0x1) | |
| 240 | #define C_000044_DMA_VIPH3_INT 0xFFFF7FFF | |
| 241 | #define S_000044_DMA_VIPH3_INT_AK(x) (((x) & 0x1) << 15) | |
| 242 | #define G_000044_DMA_VIPH3_INT_AK(x) (((x) >> 15) & 0x1) | |
| 243 | #define C_000044_DMA_VIPH3_INT_AK 0xFFFF7FFF | |
| 244 | #define S_000044_I2C_INT(x) (((x) & 0x1) << 17) | |
| 245 | #define G_000044_I2C_INT(x) (((x) >> 17) & 0x1) | |
| 246 | #define C_000044_I2C_INT 0xFFFDFFFF | |
| 247 | #define S_000044_I2C_INT_AK(x) (((x) & 0x1) << 17) | |
| 248 | #define G_000044_I2C_INT_AK(x) (((x) >> 17) & 0x1) | |
| 249 | #define C_000044_I2C_INT_AK 0xFFFDFFFF | |
| 250 | #define S_000044_GUI_IDLE_STAT(x) (((x) & 0x1) << 19) | |
| 251 | #define G_000044_GUI_IDLE_STAT(x) (((x) >> 19) & 0x1) | |
| 252 | #define C_000044_GUI_IDLE_STAT 0xFFF7FFFF | |
| 253 | #define S_000044_GUI_IDLE_STAT_AK(x) (((x) & 0x1) << 19) | |
| 254 | #define G_000044_GUI_IDLE_STAT_AK(x) (((x) >> 19) & 0x1) | |
| 255 | #define C_000044_GUI_IDLE_STAT_AK 0xFFF7FFFF | |
| 256 | #define S_000044_VIPH_INT(x) (((x) & 0x1) << 24) | |
| 257 | #define G_000044_VIPH_INT(x) (((x) >> 24) & 0x1) | |
| 258 | #define C_000044_VIPH_INT 0xFEFFFFFF | |
| 259 | #define S_000044_SW_INT(x) (((x) & 0x1) << 25) | |
| 260 | #define G_000044_SW_INT(x) (((x) >> 25) & 0x1) | |
| 261 | #define C_000044_SW_INT 0xFDFFFFFF | |
| 262 | #define S_000044_SW_INT_AK(x) (((x) & 0x1) << 25) | |
| 263 | #define G_000044_SW_INT_AK(x) (((x) >> 25) & 0x1) | |
| 264 | #define C_000044_SW_INT_AK 0xFDFFFFFF | |
| 265 | #define S_000044_SW_INT_SET(x) (((x) & 0x1) << 26) | |
| 266 | #define G_000044_SW_INT_SET(x) (((x) >> 26) & 0x1) | |
| 267 | #define C_000044_SW_INT_SET 0xFBFFFFFF | |
| 268 | #define S_000044_GEYSERVILLE_STAT(x) (((x) & 0x1) << 27) | |
| 269 | #define G_000044_GEYSERVILLE_STAT(x) (((x) >> 27) & 0x1) | |
| 270 | #define C_000044_GEYSERVILLE_STAT 0xF7FFFFFF | |
| 271 | #define S_000044_GEYSERVILLE_STAT_AK(x) (((x) & 0x1) << 27) | |
| 272 | #define G_000044_GEYSERVILLE_STAT_AK(x) (((x) >> 27) & 0x1) | |
| 273 | #define C_000044_GEYSERVILLE_STAT_AK 0xF7FFFFFF | |
| 274 | #define S_000044_HDCP_AUTHORIZED_INT_STAT(x) (((x) & 0x1) << 28) | |
| 275 | #define G_000044_HDCP_AUTHORIZED_INT_STAT(x) (((x) >> 28) & 0x1) | |
| 276 | #define C_000044_HDCP_AUTHORIZED_INT_STAT 0xEFFFFFFF | |
| 277 | #define S_000044_HDCP_AUTHORIZED_INT_AK(x) (((x) & 0x1) << 28) | |
| 278 | #define G_000044_HDCP_AUTHORIZED_INT_AK(x) (((x) >> 28) & 0x1) | |
| 279 | #define C_000044_HDCP_AUTHORIZED_INT_AK 0xEFFFFFFF | |
| 280 | #define S_000044_DVI_I2C_INT_STAT(x) (((x) & 0x1) << 29) | |
| 281 | #define G_000044_DVI_I2C_INT_STAT(x) (((x) >> 29) & 0x1) | |
| 282 | #define C_000044_DVI_I2C_INT_STAT 0xDFFFFFFF | |
| 283 | #define S_000044_DVI_I2C_INT_AK(x) (((x) & 0x1) << 29) | |
| 284 | #define G_000044_DVI_I2C_INT_AK(x) (((x) >> 29) & 0x1) | |
| 285 | #define C_000044_DVI_I2C_INT_AK 0xDFFFFFFF | |
| 286 | #define S_000044_GUIDMA_STAT(x) (((x) & 0x1) << 30) | |
| 287 | #define G_000044_GUIDMA_STAT(x) (((x) >> 30) & 0x1) | |
| 288 | #define C_000044_GUIDMA_STAT 0xBFFFFFFF | |
| 289 | #define S_000044_GUIDMA_AK(x) (((x) & 0x1) << 30) | |
| 290 | #define G_000044_GUIDMA_AK(x) (((x) >> 30) & 0x1) | |
| 291 | #define C_000044_GUIDMA_AK 0xBFFFFFFF | |
| 292 | #define S_000044_VIDDMA_STAT(x) (((x) & 0x1) << 31) | |
| 293 | #define G_000044_VIDDMA_STAT(x) (((x) >> 31) & 0x1) | |
| 294 | #define C_000044_VIDDMA_STAT 0x7FFFFFFF | |
| 295 | #define S_000044_VIDDMA_AK(x) (((x) & 0x1) << 31) | |
| 296 | #define G_000044_VIDDMA_AK(x) (((x) >> 31) & 0x1) | |
| 297 | #define C_000044_VIDDMA_AK 0x7FFFFFFF | |
| 298 | #define R_000050_CRTC_GEN_CNTL 0x000050 | |
| 299 | #define S_000050_CRTC_DBL_SCAN_EN(x) (((x) & 0x1) << 0) | |
| 300 | #define G_000050_CRTC_DBL_SCAN_EN(x) (((x) >> 0) & 0x1) | |
| 301 | #define C_000050_CRTC_DBL_SCAN_EN 0xFFFFFFFE | |
| 302 | #define S_000050_CRTC_INTERLACE_EN(x) (((x) & 0x1) << 1) | |
| 303 | #define G_000050_CRTC_INTERLACE_EN(x) (((x) >> 1) & 0x1) | |
| 304 | #define C_000050_CRTC_INTERLACE_EN 0xFFFFFFFD | |
| 305 | #define S_000050_CRTC_C_SYNC_EN(x) (((x) & 0x1) << 4) | |
| 306 | #define G_000050_CRTC_C_SYNC_EN(x) (((x) >> 4) & 0x1) | |
| 307 | #define C_000050_CRTC_C_SYNC_EN 0xFFFFFFEF | |
| 308 | #define S_000050_CRTC_PIX_WIDTH(x) (((x) & 0xF) << 8) | |
| 309 | #define G_000050_CRTC_PIX_WIDTH(x) (((x) >> 8) & 0xF) | |
| 310 | #define C_000050_CRTC_PIX_WIDTH 0xFFFFF0FF | |
| 311 | #define S_000050_CRTC_ICON_EN(x) (((x) & 0x1) << 15) | |
| 312 | #define G_000050_CRTC_ICON_EN(x) (((x) >> 15) & 0x1) | |
| 313 | #define C_000050_CRTC_ICON_EN 0xFFFF7FFF | |
| 314 | #define S_000050_CRTC_CUR_EN(x) (((x) & 0x1) << 16) | |
| 315 | #define G_000050_CRTC_CUR_EN(x) (((x) >> 16) & 0x1) | |
| 316 | #define C_000050_CRTC_CUR_EN 0xFFFEFFFF | |
| 317 | #define S_000050_CRTC_VSTAT_MODE(x) (((x) & 0x3) << 17) | |
| 318 | #define G_000050_CRTC_VSTAT_MODE(x) (((x) >> 17) & 0x3) | |
| 319 | #define C_000050_CRTC_VSTAT_MODE 0xFFF9FFFF | |
| 320 | #define S_000050_CRTC_CUR_MODE(x) (((x) & 0x7) << 20) | |
| 321 | #define G_000050_CRTC_CUR_MODE(x) (((x) >> 20) & 0x7) | |
| 322 | #define C_000050_CRTC_CUR_MODE 0xFF8FFFFF | |
| 323 | #define S_000050_CRTC_EXT_DISP_EN(x) (((x) & 0x1) << 24) | |
| 324 | #define G_000050_CRTC_EXT_DISP_EN(x) (((x) >> 24) & 0x1) | |
| 325 | #define C_000050_CRTC_EXT_DISP_EN 0xFEFFFFFF | |
| 326 | #define S_000050_CRTC_EN(x) (((x) & 0x1) << 25) | |
| 327 | #define G_000050_CRTC_EN(x) (((x) >> 25) & 0x1) | |
| 328 | #define C_000050_CRTC_EN 0xFDFFFFFF | |
| 329 | #define S_000050_CRTC_DISP_REQ_EN_B(x) (((x) & 0x1) << 26) | |
| 330 | #define G_000050_CRTC_DISP_REQ_EN_B(x) (((x) >> 26) & 0x1) | |
| 331 | #define C_000050_CRTC_DISP_REQ_EN_B 0xFBFFFFFF | |
| 332 | #define R_000054_CRTC_EXT_CNTL 0x000054 | |
| 333 | #define S_000054_CRTC_VGA_XOVERSCAN(x) (((x) & 0x1) << 0) | |
| 334 | #define G_000054_CRTC_VGA_XOVERSCAN(x) (((x) >> 0) & 0x1) | |
| 335 | #define C_000054_CRTC_VGA_XOVERSCAN 0xFFFFFFFE | |
| 336 | #define S_000054_VGA_BLINK_RATE(x) (((x) & 0x3) << 1) | |
| 337 | #define G_000054_VGA_BLINK_RATE(x) (((x) >> 1) & 0x3) | |
| 338 | #define C_000054_VGA_BLINK_RATE 0xFFFFFFF9 | |
| 339 | #define S_000054_VGA_ATI_LINEAR(x) (((x) & 0x1) << 3) | |
| 340 | #define G_000054_VGA_ATI_LINEAR(x) (((x) >> 3) & 0x1) | |
| 341 | #define C_000054_VGA_ATI_LINEAR 0xFFFFFFF7 | |
| 342 | #define S_000054_VGA_128KAP_PAGING(x) (((x) & 0x1) << 4) | |
| 343 | #define G_000054_VGA_128KAP_PAGING(x) (((x) >> 4) & 0x1) | |
| 344 | #define C_000054_VGA_128KAP_PAGING 0xFFFFFFEF | |
| 345 | #define S_000054_VGA_TEXT_132(x) (((x) & 0x1) << 5) | |
| 346 | #define G_000054_VGA_TEXT_132(x) (((x) >> 5) & 0x1) | |
| 347 | #define C_000054_VGA_TEXT_132 0xFFFFFFDF | |
| 348 | #define S_000054_VGA_XCRT_CNT_EN(x) (((x) & 0x1) << 6) | |
| 349 | #define G_000054_VGA_XCRT_CNT_EN(x) (((x) >> 6) & 0x1) | |
| 350 | #define C_000054_VGA_XCRT_CNT_EN 0xFFFFFFBF | |
| 351 | #define S_000054_CRTC_HSYNC_DIS(x) (((x) & 0x1) << 8) | |
| 352 | #define G_000054_CRTC_HSYNC_DIS(x) (((x) >> 8) & 0x1) | |
| 353 | #define C_000054_CRTC_HSYNC_DIS 0xFFFFFEFF | |
| 354 | #define S_000054_CRTC_VSYNC_DIS(x) (((x) & 0x1) << 9) | |
| 355 | #define G_000054_CRTC_VSYNC_DIS(x) (((x) >> 9) & 0x1) | |
| 356 | #define C_000054_CRTC_VSYNC_DIS 0xFFFFFDFF | |
| 357 | #define S_000054_CRTC_DISPLAY_DIS(x) (((x) & 0x1) << 10) | |
| 358 | #define G_000054_CRTC_DISPLAY_DIS(x) (((x) >> 10) & 0x1) | |
| 359 | #define C_000054_CRTC_DISPLAY_DIS 0xFFFFFBFF | |
| 360 | #define S_000054_CRTC_SYNC_TRISTATE(x) (((x) & 0x1) << 11) | |
| 361 | #define G_000054_CRTC_SYNC_TRISTATE(x) (((x) >> 11) & 0x1) | |
| 362 | #define C_000054_CRTC_SYNC_TRISTATE 0xFFFFF7FF | |
| 363 | #define S_000054_CRTC_HSYNC_TRISTATE(x) (((x) & 0x1) << 12) | |
| 364 | #define G_000054_CRTC_HSYNC_TRISTATE(x) (((x) >> 12) & 0x1) | |
| 365 | #define C_000054_CRTC_HSYNC_TRISTATE 0xFFFFEFFF | |
| 366 | #define S_000054_CRTC_VSYNC_TRISTATE(x) (((x) & 0x1) << 13) | |
| 367 | #define G_000054_CRTC_VSYNC_TRISTATE(x) (((x) >> 13) & 0x1) | |
| 368 | #define C_000054_CRTC_VSYNC_TRISTATE 0xFFFFDFFF | |
| 369 | #define S_000054_CRT_ON(x) (((x) & 0x1) << 15) | |
| 370 | #define G_000054_CRT_ON(x) (((x) >> 15) & 0x1) | |
| 371 | #define C_000054_CRT_ON 0xFFFF7FFF | |
| 372 | #define S_000054_VGA_CUR_B_TEST(x) (((x) & 0x1) << 17) | |
| 373 | #define G_000054_VGA_CUR_B_TEST(x) (((x) >> 17) & 0x1) | |
| 374 | #define C_000054_VGA_CUR_B_TEST 0xFFFDFFFF | |
| 375 | #define S_000054_VGA_PACK_DIS(x) (((x) & 0x1) << 18) | |
| 376 | #define G_000054_VGA_PACK_DIS(x) (((x) >> 18) & 0x1) | |
| 377 | #define C_000054_VGA_PACK_DIS 0xFFFBFFFF | |
| 378 | #define S_000054_VGA_MEM_PS_EN(x) (((x) & 0x1) << 19) | |
| 379 | #define G_000054_VGA_MEM_PS_EN(x) (((x) >> 19) & 0x1) | |
| 380 | #define C_000054_VGA_MEM_PS_EN 0xFFF7FFFF | |
| 381 | #define S_000054_VCRTC_IDX_MASTER(x) (((x) & 0x7F) << 24) | |
| 382 | #define G_000054_VCRTC_IDX_MASTER(x) (((x) >> 24) & 0x7F) | |
| 383 | #define C_000054_VCRTC_IDX_MASTER 0x80FFFFFF | |
| 384 | #define R_00023C_DISPLAY_BASE_ADDR 0x00023C | |
| 385 | #define S_00023C_DISPLAY_BASE_ADDR(x) (((x) & 0xFFFFFFFF) << 0) | |
| 386 | #define G_00023C_DISPLAY_BASE_ADDR(x) (((x) >> 0) & 0xFFFFFFFF) | |
| 387 | #define C_00023C_DISPLAY_BASE_ADDR 0x00000000 | |
| 388 | #define R_000260_CUR_OFFSET 0x000260 | |
| 389 | #define S_000260_CUR_OFFSET(x) (((x) & 0x7FFFFFF) << 0) | |
| 390 | #define G_000260_CUR_OFFSET(x) (((x) >> 0) & 0x7FFFFFF) | |
| 391 | #define C_000260_CUR_OFFSET 0xF8000000 | |
| 392 | #define S_000260_CUR_LOCK(x) (((x) & 0x1) << 31) | |
| 393 | #define G_000260_CUR_LOCK(x) (((x) >> 31) & 0x1) | |
| 394 | #define C_000260_CUR_LOCK 0x7FFFFFFF | |
| 395 | #define R_00033C_CRTC2_DISPLAY_BASE_ADDR 0x00033C | |
| 396 | #define S_00033C_CRTC2_DISPLAY_BASE_ADDR(x) (((x) & 0xFFFFFFFF) << 0) | |
| 397 | #define G_00033C_CRTC2_DISPLAY_BASE_ADDR(x) (((x) >> 0) & 0xFFFFFFFF) | |
| 398 | #define C_00033C_CRTC2_DISPLAY_BASE_ADDR 0x00000000 | |
| 399 | #define R_000360_CUR2_OFFSET 0x000360 | |
| 400 | #define S_000360_CUR2_OFFSET(x) (((x) & 0x7FFFFFF) << 0) | |
| 401 | #define G_000360_CUR2_OFFSET(x) (((x) >> 0) & 0x7FFFFFF) | |
| 402 | #define C_000360_CUR2_OFFSET 0xF8000000 | |
| 403 | #define S_000360_CUR2_LOCK(x) (((x) & 0x1) << 31) | |
| 404 | #define G_000360_CUR2_LOCK(x) (((x) >> 31) & 0x1) | |
| 405 | #define C_000360_CUR2_LOCK 0x7FFFFFFF | |
| 406 | #define R_0003C0_GENMO_WT 0x0003C0 | |
| 407 | #define S_0003C0_GENMO_MONO_ADDRESS_B(x) (((x) & 0x1) << 0) | |
| 408 | #define G_0003C0_GENMO_MONO_ADDRESS_B(x) (((x) >> 0) & 0x1) | |
| 409 | #define C_0003C0_GENMO_MONO_ADDRESS_B 0xFFFFFFFE | |
| 410 | #define S_0003C0_VGA_RAM_EN(x) (((x) & 0x1) << 1) | |
| 411 | #define G_0003C0_VGA_RAM_EN(x) (((x) >> 1) & 0x1) | |
| 412 | #define C_0003C0_VGA_RAM_EN 0xFFFFFFFD | |
| 413 | #define S_0003C0_VGA_CKSEL(x) (((x) & 0x3) << 2) | |
| 414 | #define G_0003C0_VGA_CKSEL(x) (((x) >> 2) & 0x3) | |
| 415 | #define C_0003C0_VGA_CKSEL 0xFFFFFFF3 | |
| 416 | #define S_0003C0_ODD_EVEN_MD_PGSEL(x) (((x) & 0x1) << 5) | |
| 417 | #define G_0003C0_ODD_EVEN_MD_PGSEL(x) (((x) >> 5) & 0x1) | |
| 418 | #define C_0003C0_ODD_EVEN_MD_PGSEL 0xFFFFFFDF | |
| 419 | #define S_0003C0_VGA_HSYNC_POL(x) (((x) & 0x1) << 6) | |
| 420 | #define G_0003C0_VGA_HSYNC_POL(x) (((x) >> 6) & 0x1) | |
| 421 | #define C_0003C0_VGA_HSYNC_POL 0xFFFFFFBF | |
| 422 | #define S_0003C0_VGA_VSYNC_POL(x) (((x) & 0x1) << 7) | |
| 423 | #define G_0003C0_VGA_VSYNC_POL(x) (((x) >> 7) & 0x1) | |
| 424 | #define C_0003C0_VGA_VSYNC_POL 0xFFFFFF7F | |
| 425 | #define R_0003F8_CRTC2_GEN_CNTL 0x0003F8 | |
| 426 | #define S_0003F8_CRTC2_DBL_SCAN_EN(x) (((x) & 0x1) << 0) | |
| 427 | #define G_0003F8_CRTC2_DBL_SCAN_EN(x) (((x) >> 0) & 0x1) | |
| 428 | #define C_0003F8_CRTC2_DBL_SCAN_EN 0xFFFFFFFE | |
| 429 | #define S_0003F8_CRTC2_INTERLACE_EN(x) (((x) & 0x1) << 1) | |
| 430 | #define G_0003F8_CRTC2_INTERLACE_EN(x) (((x) >> 1) & 0x1) | |
| 431 | #define C_0003F8_CRTC2_INTERLACE_EN 0xFFFFFFFD | |
| 432 | #define S_0003F8_CRTC2_SYNC_TRISTATE(x) (((x) & 0x1) << 4) | |
| 433 | #define G_0003F8_CRTC2_SYNC_TRISTATE(x) (((x) >> 4) & 0x1) | |
| 434 | #define C_0003F8_CRTC2_SYNC_TRISTATE 0xFFFFFFEF | |
| 435 | #define S_0003F8_CRTC2_HSYNC_TRISTATE(x) (((x) & 0x1) << 5) | |
| 436 | #define G_0003F8_CRTC2_HSYNC_TRISTATE(x) (((x) >> 5) & 0x1) | |
| 437 | #define C_0003F8_CRTC2_HSYNC_TRISTATE 0xFFFFFFDF | |
| 438 | #define S_0003F8_CRTC2_VSYNC_TRISTATE(x) (((x) & 0x1) << 6) | |
| 439 | #define G_0003F8_CRTC2_VSYNC_TRISTATE(x) (((x) >> 6) & 0x1) | |
| 440 | #define C_0003F8_CRTC2_VSYNC_TRISTATE 0xFFFFFFBF | |
| 441 | #define S_0003F8_CRT2_ON(x) (((x) & 0x1) << 7) | |
| 442 | #define G_0003F8_CRT2_ON(x) (((x) >> 7) & 0x1) | |
| 443 | #define C_0003F8_CRT2_ON 0xFFFFFF7F | |
| 444 | #define S_0003F8_CRTC2_PIX_WIDTH(x) (((x) & 0xF) << 8) | |
| 445 | #define G_0003F8_CRTC2_PIX_WIDTH(x) (((x) >> 8) & 0xF) | |
| 446 | #define C_0003F8_CRTC2_PIX_WIDTH 0xFFFFF0FF | |
| 447 | #define S_0003F8_CRTC2_ICON_EN(x) (((x) & 0x1) << 15) | |
| 448 | #define G_0003F8_CRTC2_ICON_EN(x) (((x) >> 15) & 0x1) | |
| 449 | #define C_0003F8_CRTC2_ICON_EN 0xFFFF7FFF | |
| 450 | #define S_0003F8_CRTC2_CUR_EN(x) (((x) & 0x1) << 16) | |
| 451 | #define G_0003F8_CRTC2_CUR_EN(x) (((x) >> 16) & 0x1) | |
| 452 | #define C_0003F8_CRTC2_CUR_EN 0xFFFEFFFF | |
| 453 | #define S_0003F8_CRTC2_CUR_MODE(x) (((x) & 0x7) << 20) | |
| 454 | #define G_0003F8_CRTC2_CUR_MODE(x) (((x) >> 20) & 0x7) | |
| 455 | #define C_0003F8_CRTC2_CUR_MODE 0xFF8FFFFF | |
| 456 | #define S_0003F8_CRTC2_DISPLAY_DIS(x) (((x) & 0x1) << 23) | |
| 457 | #define G_0003F8_CRTC2_DISPLAY_DIS(x) (((x) >> 23) & 0x1) | |
| 458 | #define C_0003F8_CRTC2_DISPLAY_DIS 0xFF7FFFFF | |
| 459 | #define S_0003F8_CRTC2_EN(x) (((x) & 0x1) << 25) | |
| 460 | #define G_0003F8_CRTC2_EN(x) (((x) >> 25) & 0x1) | |
| 461 | #define C_0003F8_CRTC2_EN 0xFDFFFFFF | |
| 462 | #define S_0003F8_CRTC2_DISP_REQ_EN_B(x) (((x) & 0x1) << 26) | |
| 463 | #define G_0003F8_CRTC2_DISP_REQ_EN_B(x) (((x) >> 26) & 0x1) | |
| 464 | #define C_0003F8_CRTC2_DISP_REQ_EN_B 0xFBFFFFFF | |
| 465 | #define S_0003F8_CRTC2_C_SYNC_EN(x) (((x) & 0x1) << 27) | |
| 466 | #define G_0003F8_CRTC2_C_SYNC_EN(x) (((x) >> 27) & 0x1) | |
| 467 | #define C_0003F8_CRTC2_C_SYNC_EN 0xF7FFFFFF | |
| 468 | #define S_0003F8_CRTC2_HSYNC_DIS(x) (((x) & 0x1) << 28) | |
| 469 | #define G_0003F8_CRTC2_HSYNC_DIS(x) (((x) >> 28) & 0x1) | |
| 470 | #define C_0003F8_CRTC2_HSYNC_DIS 0xEFFFFFFF | |
| 471 | #define S_0003F8_CRTC2_VSYNC_DIS(x) (((x) & 0x1) << 29) | |
| 472 | #define G_0003F8_CRTC2_VSYNC_DIS(x) (((x) >> 29) & 0x1) | |
| 473 | #define C_0003F8_CRTC2_VSYNC_DIS 0xDFFFFFFF | |
| 474 | #define R_000420_OV0_SCALE_CNTL 0x000420 | |
| 475 | #define S_000420_OV0_NO_READ_BEHIND_SCAN(x) (((x) & 0x1) << 1) | |
| 476 | #define G_000420_OV0_NO_READ_BEHIND_SCAN(x) (((x) >> 1) & 0x1) | |
| 477 | #define C_000420_OV0_NO_READ_BEHIND_SCAN 0xFFFFFFFD | |
| 478 | #define S_000420_OV0_HORZ_PICK_NEAREST(x) (((x) & 0x1) << 2) | |
| 479 | #define G_000420_OV0_HORZ_PICK_NEAREST(x) (((x) >> 2) & 0x1) | |
| 480 | #define C_000420_OV0_HORZ_PICK_NEAREST 0xFFFFFFFB | |
| 481 | #define S_000420_OV0_VERT_PICK_NEAREST(x) (((x) & 0x1) << 3) | |
| 482 | #define G_000420_OV0_VERT_PICK_NEAREST(x) (((x) >> 3) & 0x1) | |
| 483 | #define C_000420_OV0_VERT_PICK_NEAREST 0xFFFFFFF7 | |
| 484 | #define S_000420_OV0_SIGNED_UV(x) (((x) & 0x1) << 4) | |
| 485 | #define G_000420_OV0_SIGNED_UV(x) (((x) >> 4) & 0x1) | |
| 486 | #define C_000420_OV0_SIGNED_UV 0xFFFFFFEF | |
| 487 | #define S_000420_OV0_GAMMA_SEL(x) (((x) & 0x7) << 5) | |
| 488 | #define G_000420_OV0_GAMMA_SEL(x) (((x) >> 5) & 0x7) | |
| 489 | #define C_000420_OV0_GAMMA_SEL 0xFFFFFF1F | |
| 490 | #define S_000420_OV0_SURFACE_FORMAT(x) (((x) & 0xF) << 8) | |
| 491 | #define G_000420_OV0_SURFACE_FORMAT(x) (((x) >> 8) & 0xF) | |
| 492 | #define C_000420_OV0_SURFACE_FORMAT 0xFFFFF0FF | |
| 493 | #define S_000420_OV0_ADAPTIVE_DEINT(x) (((x) & 0x1) << 12) | |
| 494 | #define G_000420_OV0_ADAPTIVE_DEINT(x) (((x) >> 12) & 0x1) | |
| 495 | #define C_000420_OV0_ADAPTIVE_DEINT 0xFFFFEFFF | |
| 496 | #define S_000420_OV0_CRTC_SEL(x) (((x) & 0x1) << 14) | |
| 497 | #define G_000420_OV0_CRTC_SEL(x) (((x) >> 14) & 0x1) | |
| 498 | #define C_000420_OV0_CRTC_SEL 0xFFFFBFFF | |
| 499 | #define S_000420_OV0_BURST_PER_PLANE(x) (((x) & 0x7F) << 16) | |
| 500 | #define G_000420_OV0_BURST_PER_PLANE(x) (((x) >> 16) & 0x7F) | |
| 501 | #define C_000420_OV0_BURST_PER_PLANE 0xFF80FFFF | |
| 502 | #define S_000420_OV0_DOUBLE_BUFFER_REGS(x) (((x) & 0x1) << 24) | |
| 503 | #define G_000420_OV0_DOUBLE_BUFFER_REGS(x) (((x) >> 24) & 0x1) | |
| 504 | #define C_000420_OV0_DOUBLE_BUFFER_REGS 0xFEFFFFFF | |
| 505 | #define S_000420_OV0_BANDWIDTH(x) (((x) & 0x1) << 26) | |
| 506 | #define G_000420_OV0_BANDWIDTH(x) (((x) >> 26) & 0x1) | |
| 507 | #define C_000420_OV0_BANDWIDTH 0xFBFFFFFF | |
| 508 | #define S_000420_OV0_LIN_TRANS_BYPASS(x) (((x) & 0x1) << 28) | |
| 509 | #define G_000420_OV0_LIN_TRANS_BYPASS(x) (((x) >> 28) & 0x1) | |
| 510 | #define C_000420_OV0_LIN_TRANS_BYPASS 0xEFFFFFFF | |
| 511 | #define S_000420_OV0_INT_EMU(x) (((x) & 0x1) << 29) | |
| 512 | #define G_000420_OV0_INT_EMU(x) (((x) >> 29) & 0x1) | |
| 513 | #define C_000420_OV0_INT_EMU 0xDFFFFFFF | |
| 514 | #define S_000420_OV0_OVERLAY_EN(x) (((x) & 0x1) << 30) | |
| 515 | #define G_000420_OV0_OVERLAY_EN(x) (((x) >> 30) & 0x1) | |
| 516 | #define C_000420_OV0_OVERLAY_EN 0xBFFFFFFF | |
| 517 | #define S_000420_OV0_SOFT_RESET(x) (((x) & 0x1) << 31) | |
| 518 | #define G_000420_OV0_SOFT_RESET(x) (((x) >> 31) & 0x1) | |
| 519 | #define C_000420_OV0_SOFT_RESET 0x7FFFFFFF | |
| 520 | #define R_00070C_CP_RB_RPTR_ADDR 0x00070C | |
| 521 | #define S_00070C_RB_RPTR_SWAP(x) (((x) & 0x3) << 0) | |
| 522 | #define G_00070C_RB_RPTR_SWAP(x) (((x) >> 0) & 0x3) | |
| 523 | #define C_00070C_RB_RPTR_SWAP 0xFFFFFFFC | |
| 524 | #define S_00070C_RB_RPTR_ADDR(x) (((x) & 0x3FFFFFFF) << 2) | |
| 525 | #define G_00070C_RB_RPTR_ADDR(x) (((x) >> 2) & 0x3FFFFFFF) | |
| 526 | #define C_00070C_RB_RPTR_ADDR 0x00000003 | |
| 527 | #define R_000740_CP_CSQ_CNTL 0x000740 | |
| 528 | #define S_000740_CSQ_CNT_PRIMARY(x) (((x) & 0xFF) << 0) | |
| 529 | #define G_000740_CSQ_CNT_PRIMARY(x) (((x) >> 0) & 0xFF) | |
| 530 | #define C_000740_CSQ_CNT_PRIMARY 0xFFFFFF00 | |
| 531 | #define S_000740_CSQ_CNT_INDIRECT(x) (((x) & 0xFF) << 8) | |
| 532 | #define G_000740_CSQ_CNT_INDIRECT(x) (((x) >> 8) & 0xFF) | |
| 533 | #define C_000740_CSQ_CNT_INDIRECT 0xFFFF00FF | |
| 534 | #define S_000740_CSQ_MODE(x) (((x) & 0xF) << 28) | |
| 535 | #define G_000740_CSQ_MODE(x) (((x) >> 28) & 0xF) | |
| 536 | #define C_000740_CSQ_MODE 0x0FFFFFFF | |
| 537 | #define R_000770_SCRATCH_UMSK 0x000770 | |
| 538 | #define S_000770_SCRATCH_UMSK(x) (((x) & 0x3F) << 0) | |
| 539 | #define G_000770_SCRATCH_UMSK(x) (((x) >> 0) & 0x3F) | |
| 540 | #define C_000770_SCRATCH_UMSK 0xFFFFFFC0 | |
| 541 | #define S_000770_SCRATCH_SWAP(x) (((x) & 0x3) << 16) | |
| 542 | #define G_000770_SCRATCH_SWAP(x) (((x) >> 16) & 0x3) | |
| 543 | #define C_000770_SCRATCH_SWAP 0xFFFCFFFF | |
| 544 | #define R_000774_SCRATCH_ADDR 0x000774 | |
| 545 | #define S_000774_SCRATCH_ADDR(x) (((x) & 0x7FFFFFF) << 5) | |
| 546 | #define G_000774_SCRATCH_ADDR(x) (((x) >> 5) & 0x7FFFFFF) | |
| 547 | #define C_000774_SCRATCH_ADDR 0x0000001F | |
| 45600232 JG |
548 | #define R_000E40_RBBM_STATUS 0x000E40 |
| 549 | #define S_000E40_CMDFIFO_AVAIL(x) (((x) & 0x7F) << 0) | |
| 550 | #define G_000E40_CMDFIFO_AVAIL(x) (((x) >> 0) & 0x7F) | |
| 551 | #define C_000E40_CMDFIFO_AVAIL 0xFFFFFF80 | |
| 552 | #define S_000E40_HIRQ_ON_RBB(x) (((x) & 0x1) << 8) | |
| 553 | #define G_000E40_HIRQ_ON_RBB(x) (((x) >> 8) & 0x1) | |
| 554 | #define C_000E40_HIRQ_ON_RBB 0xFFFFFEFF | |
| 555 | #define S_000E40_CPRQ_ON_RBB(x) (((x) & 0x1) << 9) | |
| 556 | #define G_000E40_CPRQ_ON_RBB(x) (((x) >> 9) & 0x1) | |
| 557 | #define C_000E40_CPRQ_ON_RBB 0xFFFFFDFF | |
| 558 | #define S_000E40_CFRQ_ON_RBB(x) (((x) & 0x1) << 10) | |
| 559 | #define G_000E40_CFRQ_ON_RBB(x) (((x) >> 10) & 0x1) | |
| 560 | #define C_000E40_CFRQ_ON_RBB 0xFFFFFBFF | |
| 561 | #define S_000E40_HIRQ_IN_RTBUF(x) (((x) & 0x1) << 11) | |
| 562 | #define G_000E40_HIRQ_IN_RTBUF(x) (((x) >> 11) & 0x1) | |
| 563 | #define C_000E40_HIRQ_IN_RTBUF 0xFFFFF7FF | |
| 564 | #define S_000E40_CPRQ_IN_RTBUF(x) (((x) & 0x1) << 12) | |
| 565 | #define G_000E40_CPRQ_IN_RTBUF(x) (((x) >> 12) & 0x1) | |
| 566 | #define C_000E40_CPRQ_IN_RTBUF 0xFFFFEFFF | |
| 567 | #define S_000E40_CFRQ_IN_RTBUF(x) (((x) & 0x1) << 13) | |
| 568 | #define G_000E40_CFRQ_IN_RTBUF(x) (((x) >> 13) & 0x1) | |
| 569 | #define C_000E40_CFRQ_IN_RTBUF 0xFFFFDFFF | |
| 570 | #define S_000E40_CF_PIPE_BUSY(x) (((x) & 0x1) << 14) | |
| 571 | #define G_000E40_CF_PIPE_BUSY(x) (((x) >> 14) & 0x1) | |
| 572 | #define C_000E40_CF_PIPE_BUSY 0xFFFFBFFF | |
| 573 | #define S_000E40_ENG_EV_BUSY(x) (((x) & 0x1) << 15) | |
| 574 | #define G_000E40_ENG_EV_BUSY(x) (((x) >> 15) & 0x1) | |
| 575 | #define C_000E40_ENG_EV_BUSY 0xFFFF7FFF | |
| 576 | #define S_000E40_CP_CMDSTRM_BUSY(x) (((x) & 0x1) << 16) | |
| 577 | #define G_000E40_CP_CMDSTRM_BUSY(x) (((x) >> 16) & 0x1) | |
| 578 | #define C_000E40_CP_CMDSTRM_BUSY 0xFFFEFFFF | |
| 579 | #define S_000E40_E2_BUSY(x) (((x) & 0x1) << 17) | |
| 580 | #define G_000E40_E2_BUSY(x) (((x) >> 17) & 0x1) | |
| 581 | #define C_000E40_E2_BUSY 0xFFFDFFFF | |
| 582 | #define S_000E40_RB2D_BUSY(x) (((x) & 0x1) << 18) | |
| 583 | #define G_000E40_RB2D_BUSY(x) (((x) >> 18) & 0x1) | |
| 584 | #define C_000E40_RB2D_BUSY 0xFFFBFFFF | |
| 585 | #define S_000E40_RB3D_BUSY(x) (((x) & 0x1) << 19) | |
| 586 | #define G_000E40_RB3D_BUSY(x) (((x) >> 19) & 0x1) | |
| 587 | #define C_000E40_RB3D_BUSY 0xFFF7FFFF | |
| 588 | #define S_000E40_SE_BUSY(x) (((x) & 0x1) << 20) | |
| 589 | #define G_000E40_SE_BUSY(x) (((x) >> 20) & 0x1) | |
| 590 | #define C_000E40_SE_BUSY 0xFFEFFFFF | |
| 591 | #define S_000E40_RE_BUSY(x) (((x) & 0x1) << 21) | |
| 592 | #define G_000E40_RE_BUSY(x) (((x) >> 21) & 0x1) | |
| 593 | #define C_000E40_RE_BUSY 0xFFDFFFFF | |
| 594 | #define S_000E40_TAM_BUSY(x) (((x) & 0x1) << 22) | |
| 595 | #define G_000E40_TAM_BUSY(x) (((x) >> 22) & 0x1) | |
| 596 | #define C_000E40_TAM_BUSY 0xFFBFFFFF | |
| 597 | #define S_000E40_TDM_BUSY(x) (((x) & 0x1) << 23) | |
| 598 | #define G_000E40_TDM_BUSY(x) (((x) >> 23) & 0x1) | |
| 599 | #define C_000E40_TDM_BUSY 0xFF7FFFFF | |
| 600 | #define S_000E40_PB_BUSY(x) (((x) & 0x1) << 24) | |
| 601 | #define G_000E40_PB_BUSY(x) (((x) >> 24) & 0x1) | |
| 602 | #define C_000E40_PB_BUSY 0xFEFFFFFF | |
| 603 | #define S_000E40_GUI_ACTIVE(x) (((x) & 0x1) << 31) | |
| 604 | #define G_000E40_GUI_ACTIVE(x) (((x) >> 31) & 0x1) | |
| 605 | #define C_000E40_GUI_ACTIVE 0x7FFFFFFF | |
| 606 | ||
| 3ce0a23d | 607 | #endif |