[deliverable/linux.git] / drivers / gpu / drm / radeon / r200.c

/*
 * Copyright 2008 Advanced Micro Devices, Inc.
 * Copyright 2008 Red Hat Inc.
 * Copyright 2009 Jerome Glisse.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Dave Airlie
 *          Alex Deucher
 *          Jerome Glisse
 */
#include "drmP.h"
#include "drm.h"
#include "radeon_drm.h"
#include "radeon_reg.h"
#include "radeon.h"

#include "r100d.h"
#include "r200_reg_safe.h"

#include "r100_track.h"

static int r200_get_vtx_size_0(uint32_t vtx_fmt_0)
{
	int vtx_size, i;
	vtx_size = 2;

	if (vtx_fmt_0 & R200_VTX_Z0)
		vtx_size++;
	if (vtx_fmt_0 & R200_VTX_W0)
		vtx_size++;
	/* blend weight */
	if (vtx_fmt_0 & (0x7 << R200_VTX_WEIGHT_COUNT_SHIFT))
		vtx_size += (vtx_fmt_0 >> R200_VTX_WEIGHT_COUNT_SHIFT) & 0x7;
	if (vtx_fmt_0 & R200_VTX_PV_MATRIX_SEL)
		vtx_size++;
	if (vtx_fmt_0 & R200_VTX_N0)
		vtx_size += 3;
	if (vtx_fmt_0 & R200_VTX_POINT_SIZE)
		vtx_size++;
	if (vtx_fmt_0 & R200_VTX_DISCRETE_FOG)
		vtx_size++;
	if (vtx_fmt_0 & R200_VTX_SHININESS_0)
		vtx_size++;
	if (vtx_fmt_0 & R200_VTX_SHININESS_1)
		vtx_size++;
	for (i = 0; i < 8; i++) {
		int color_size = (vtx_fmt_0 >> (11 + 2*i)) & 0x3;
		switch (color_size) {
		case 0: break;
		case 1: vtx_size++; break;
		case 2: vtx_size += 3; break;
		case 3: vtx_size += 4; break;
		}
	}
	if (vtx_fmt_0 & R200_VTX_XY1)
		vtx_size += 2;
	if (vtx_fmt_0 & R200_VTX_Z1)
		vtx_size++;
	if (vtx_fmt_0 & R200_VTX_W1)
		vtx_size++;
	if (vtx_fmt_0 & R200_VTX_N1)
		vtx_size += 3;
	return vtx_size;
}

int r200_copy_dma(struct radeon_device *rdev,
		  uint64_t src_offset,
		  uint64_t dst_offset,
		  unsigned num_pages,
		  struct radeon_fence *fence)
{
	uint32_t size;
	uint32_t cur_size;
	int i, num_loops;
	int r = 0;

	/* radeon pitch is /64 */
	size = num_pages << PAGE_SHIFT;
	num_loops = DIV_ROUND_UP(size, 0x1FFFFF);
	r = radeon_ring_lock(rdev, num_loops * 4 + 64);
	if (r) {
		DRM_ERROR("radeon: moving bo (%d).\n", r);
		return r;
	}
	/* Must wait for 2D idle & clean before DMA or hangs might happen */
	radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
	radeon_ring_write(rdev, (1 << 16));
	for (i = 0; i < num_loops; i++) {
		cur_size = size;
		if (cur_size > 0x1FFFFF) {
			cur_size = 0x1FFFFF;
		}
		size -= cur_size;
		radeon_ring_write(rdev, PACKET0(0x720, 2));
		radeon_ring_write(rdev, src_offset);
		radeon_ring_write(rdev, dst_offset);
		radeon_ring_write(rdev, cur_size | (1 << 31) | (1 << 30));
		src_offset += cur_size;
		dst_offset += cur_size;
	}
	radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
	radeon_ring_write(rdev, RADEON_WAIT_DMA_GUI_IDLE);
	if (fence) {
		r = radeon_fence_emit(rdev, fence);
	}
	radeon_ring_unlock_commit(rdev);
	return r;
}


static int r200_get_vtx_size_1(uint32_t vtx_fmt_1)
{
	int vtx_size, i, tex_size;
	vtx_size = 0;
	for (i = 0; i < 6; i++) {
		tex_size = (vtx_fmt_1 >> (i * 3)) & 0x7;
		if (tex_size > 4)
			continue;
		vtx_size += tex_size;
	}
	return vtx_size;
}

int r200_packet0_check(struct radeon_cs_parser *p,
		       struct radeon_cs_packet *pkt,
		       unsigned idx, unsigned reg)
{
	struct radeon_cs_reloc *reloc;
	struct r100_cs_track *track;
	volatile uint32_t *ib;
	uint32_t tmp;
	int r;
	int i;
	int face;
	u32 tile_flags = 0;
	u32 idx_value;

	ib = p->ib->ptr;
	track = (struct r100_cs_track *)p->track;
	idx_value = radeon_get_ib_value(p, idx);
	switch (reg) {
	case RADEON_CRTC_GUI_TRIG_VLINE:
		r = r100_cs_packet_parse_vline(p);
		if (r) {
			DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
				  idx, reg);
			r100_cs_dump_packet(p, pkt);
			return r;
		}
		break;
		/* FIXME: only allow PACKET3 blit? easier to check for out of
		 * range access */
	case RADEON_DST_PITCH_OFFSET:
	case RADEON_SRC_PITCH_OFFSET:
		r = r100_reloc_pitch_offset(p, pkt, idx, reg);
		if (r)
			return r;
		break;
	case RADEON_RB3D_DEPTHOFFSET:
		r = r100_cs_packet_next_reloc(p, &reloc);
		if (r) {
			DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
				  idx, reg);
			r100_cs_dump_packet(p, pkt);
			return r;
		}
		track->zb.robj = reloc->robj;
		track->zb.offset = idx_value;
		ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
		break;
	case RADEON_RB3D_COLOROFFSET:
		r = r100_cs_packet_next_reloc(p, &reloc);
		if (r) {
			DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
				  idx, reg);
			r100_cs_dump_packet(p, pkt);
			return r;
		}
		track->cb[0].robj = reloc->robj;
		track->cb[0].offset = idx_value;
		ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
		break;
	case R200_PP_TXOFFSET_0:
	case R200_PP_TXOFFSET_1:
	case R200_PP_TXOFFSET_2:
	case R200_PP_TXOFFSET_3:
	case R200_PP_TXOFFSET_4:
	case R200_PP_TXOFFSET_5:
		i = (reg - R200_PP_TXOFFSET_0) / 24;
		r = r100_cs_packet_next_reloc(p, &reloc);
		if (r) {
			DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
				  idx, reg);
			r100_cs_dump_packet(p, pkt);
			return r;
		}
		ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
		track->textures[i].robj = reloc->robj;
		break;
	case R200_PP_CUBIC_OFFSET_F1_0:
	case R200_PP_CUBIC_OFFSET_F2_0:
	case R200_PP_CUBIC_OFFSET_F3_0:
	case R200_PP_CUBIC_OFFSET_F4_0:
	case R200_PP_CUBIC_OFFSET_F5_0:
	case R200_PP_CUBIC_OFFSET_F1_1:
	case R200_PP_CUBIC_OFFSET_F2_1:
	case R200_PP_CUBIC_OFFSET_F3_1:
	case R200_PP_CUBIC_OFFSET_F4_1:
	case R200_PP_CUBIC_OFFSET_F5_1:
	case R200_PP_CUBIC_OFFSET_F1_2:
	case R200_PP_CUBIC_OFFSET_F2_2:
	case R200_PP_CUBIC_OFFSET_F3_2:
	case R200_PP_CUBIC_OFFSET_F4_2:
	case R200_PP_CUBIC_OFFSET_F5_2:
	case R200_PP_CUBIC_OFFSET_F1_3:
	case R200_PP_CUBIC_OFFSET_F2_3:
	case R200_PP_CUBIC_OFFSET_F3_3:
	case R200_PP_CUBIC_OFFSET_F4_3:
	case R200_PP_CUBIC_OFFSET_F5_3:
	case R200_PP_CUBIC_OFFSET_F1_4:
	case R200_PP_CUBIC_OFFSET_F2_4:
	case R200_PP_CUBIC_OFFSET_F3_4:
	case R200_PP_CUBIC_OFFSET_F4_4:
	case R200_PP_CUBIC_OFFSET_F5_4:
	case R200_PP_CUBIC_OFFSET_F1_5:
	case R200_PP_CUBIC_OFFSET_F2_5:
	case R200_PP_CUBIC_OFFSET_F3_5:
	case R200_PP_CUBIC_OFFSET_F4_5:
	case R200_PP_CUBIC_OFFSET_F5_5:
		i = (reg - R200_PP_TXOFFSET_0) / 24;
		face = (reg - ((i * 24) + R200_PP_TXOFFSET_0)) / 4;
		r = r100_cs_packet_next_reloc(p, &reloc);
		if (r) {
			DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
				  idx, reg);
			r100_cs_dump_packet(p, pkt);
			return r;
		}
		track->textures[i].cube_info[face - 1].offset = idx_value;
		ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
		track->textures[i].cube_info[face - 1].robj = reloc->robj;
		break;
	case RADEON_RE_WIDTH_HEIGHT:
		track->maxy = ((idx_value >> 16) & 0x7FF);
		break;
	case RADEON_RB3D_COLORPITCH:
		r = r100_cs_packet_next_reloc(p, &reloc);
		if (r) {
			DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
				  idx, reg);
			r100_cs_dump_packet(p, pkt);
			return r;
		}

		if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
			tile_flags |= RADEON_COLOR_TILE_ENABLE;
		if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
			tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;

		tmp = idx_value & ~(0x7 << 16);
		tmp |= tile_flags;
		ib[idx] = tmp;

		track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
		break;
	case RADEON_RB3D_DEPTHPITCH:
		track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
		break;
	case RADEON_RB3D_CNTL:
		switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
		case 7:
		case 8:
		case 9:
		case 11:
		case 12:
			track->cb[0].cpp = 1;
			break;
		case 3:
		case 4:
		case 15:
			track->cb[0].cpp = 2;
			break;
		case 6:
			track->cb[0].cpp = 4;
			break;
		default:
			DRM_ERROR("Invalid color buffer format (%d) !\n",
				  ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
			return -EINVAL;
		}
		if (idx_value & RADEON_DEPTHXY_OFFSET_ENABLE) {
			DRM_ERROR("No support for depth xy offset in kms\n");
			return -EINVAL;
		}

		track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
		break;
	case RADEON_RB3D_ZSTENCILCNTL:
		switch (idx_value & 0xf) {
		case 0:
			track->zb.cpp = 2;
			break;
		case 2:
		case 3:
		case 4:
		case 5:
		case 9:
		case 11:
			track->zb.cpp = 4;
			break;
		default:
			break;
		}
		break;
	case RADEON_RB3D_ZPASS_ADDR:
		r = r100_cs_packet_next_reloc(p, &reloc);
		if (r) {
			DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
				  idx, reg);
			r100_cs_dump_packet(p, pkt);
			return r;
		}
		ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
		break;
	case RADEON_PP_CNTL:
		{
			uint32_t temp = idx_value >> 4;
			for (i = 0; i < track->num_texture; i++)
				track->textures[i].enabled = !!(temp & (1 << i));
		}
		break;
	case RADEON_SE_VF_CNTL:
		track->vap_vf_cntl = idx_value;
		break;
	case 0x210c:
		/* VAP_VF_MAX_VTX_INDX */
		track->max_indx = idx_value & 0x00FFFFFFUL;
		break;
	case R200_SE_VTX_FMT_0:
		track->vtx_size = r200_get_vtx_size_0(idx_value);
		break;
	case R200_SE_VTX_FMT_1:
		track->vtx_size += r200_get_vtx_size_1(idx_value);
		break;
	case R200_PP_TXSIZE_0:
	case R200_PP_TXSIZE_1:
	case R200_PP_TXSIZE_2:
	case R200_PP_TXSIZE_3:
	case R200_PP_TXSIZE_4:
	case R200_PP_TXSIZE_5:
		i = (reg - R200_PP_TXSIZE_0) / 32;
		track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
		track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
		break;
	case R200_PP_TXPITCH_0:
	case R200_PP_TXPITCH_1:
	case R200_PP_TXPITCH_2:
	case R200_PP_TXPITCH_3:
	case R200_PP_TXPITCH_4:
	case R200_PP_TXPITCH_5:
		i = (reg - R200_PP_TXPITCH_0) / 32;
		track->textures[i].pitch = idx_value + 32;
		break;
	case R200_PP_TXFILTER_0:
	case R200_PP_TXFILTER_1:
	case R200_PP_TXFILTER_2:
	case R200_PP_TXFILTER_3:
	case R200_PP_TXFILTER_4:
	case R200_PP_TXFILTER_5:
		i = (reg - R200_PP_TXFILTER_0) / 32;
		track->textures[i].num_levels = ((idx_value & R200_MAX_MIP_LEVEL_MASK)
						 >> R200_MAX_MIP_LEVEL_SHIFT);
		tmp = (idx_value >> 23) & 0x7;
		if (tmp == 2 || tmp == 6)
			track->textures[i].roundup_w = false;
		tmp = (idx_value >> 27) & 0x7;
		if (tmp == 2 || tmp == 6)
			track->textures[i].roundup_h = false;
		break;
	case R200_PP_TXMULTI_CTL_0:
	case R200_PP_TXMULTI_CTL_1:
	case R200_PP_TXMULTI_CTL_2:
	case R200_PP_TXMULTI_CTL_3:
	case R200_PP_TXMULTI_CTL_4:
	case R200_PP_TXMULTI_CTL_5:
		i = (reg - R200_PP_TXMULTI_CTL_0) / 32;
		break;
	case R200_PP_TXFORMAT_X_0:
	case R200_PP_TXFORMAT_X_1:
	case R200_PP_TXFORMAT_X_2:
	case R200_PP_TXFORMAT_X_3:
	case R200_PP_TXFORMAT_X_4:
	case R200_PP_TXFORMAT_X_5:
		i = (reg - R200_PP_TXFORMAT_X_0) / 32;
		track->textures[i].txdepth = idx_value & 0x7;
		tmp = (idx_value >> 16) & 0x3;
		/* 2D, 3D, CUBE */
		switch (tmp) {
		case 0:
		case 5:
		case 6:
		case 7:
			/* 1D/2D */
			track->textures[i].tex_coord_type = 0;
			break;
		case 1:
			/* CUBE */
			track->textures[i].tex_coord_type = 2;
			break;
		case 2:
			/* 3D */
			track->textures[i].tex_coord_type = 1;
			break;
		}
		break;
	case R200_PP_TXFORMAT_0:
	case R200_PP_TXFORMAT_1:
	case R200_PP_TXFORMAT_2:
	case R200_PP_TXFORMAT_3:
	case R200_PP_TXFORMAT_4:
	case R200_PP_TXFORMAT_5:
		i = (reg - R200_PP_TXFORMAT_0) / 32;
		if (idx_value & R200_TXFORMAT_NON_POWER2) {
			track->textures[i].use_pitch = 1;
		} else {
			track->textures[i].use_pitch = 0;
			track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
			track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
		}
		switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
		case R200_TXFORMAT_I8:
		case R200_TXFORMAT_RGB332:
		case R200_TXFORMAT_Y8:
			track->textures[i].cpp = 1;
			break;
		case R200_TXFORMAT_AI88:
		case R200_TXFORMAT_ARGB1555:
		case R200_TXFORMAT_RGB565:
		case R200_TXFORMAT_ARGB4444:
		case R200_TXFORMAT_VYUY422:
		case R200_TXFORMAT_YVYU422:
		case R200_TXFORMAT_LDVDU655:
		case R200_TXFORMAT_DVDU88:
		case R200_TXFORMAT_AVYU4444:
			track->textures[i].cpp = 2;
			break;
		case R200_TXFORMAT_ARGB8888:
		case R200_TXFORMAT_RGBA8888:
		case R200_TXFORMAT_ABGR8888:
		case R200_TXFORMAT_BGR111110:
		case R200_TXFORMAT_LDVDU8888:
			track->textures[i].cpp = 4;
			break;
		case R200_TXFORMAT_DXT1:
			track->textures[i].cpp = 1;
			track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
			break;
		case R200_TXFORMAT_DXT23:
		case R200_TXFORMAT_DXT45:
			track->textures[i].cpp = 1;
			track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
			break;
		}
		track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
		track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
		break;
	case R200_PP_CUBIC_FACES_0:
	case R200_PP_CUBIC_FACES_1:
	case R200_PP_CUBIC_FACES_2:
	case R200_PP_CUBIC_FACES_3:
	case R200_PP_CUBIC_FACES_4:
	case R200_PP_CUBIC_FACES_5:
		tmp = idx_value;
		i = (reg - R200_PP_CUBIC_FACES_0) / 32;
		for (face = 0; face < 4; face++) {
			track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
			track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
		}
		break;
	default:
		printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
		       reg, idx);
		return -EINVAL;
	}
	return 0;
}

void r200_set_safe_registers(struct radeon_device *rdev)
{
	rdev->config.r100.reg_safe_bm = r200_reg_safe_bm;
	rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r200_reg_safe_bm);
}
Commit	Line	Data
551ebd83 DA	1	/*
	2	* Copyright 2008 Advanced Micro Devices, Inc.
	3	* Copyright 2008 Red Hat Inc.
	4	* Copyright 2009 Jerome Glisse.
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a
	7	* copy of this software and associated documentation files (the "Software"),
	8	* to deal in the Software without restriction, including without limitation
	9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	10	* and/or sell copies of the Software, and to permit persons to whom the
	11	* Software is furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	22	* OTHER DEALINGS IN THE SOFTWARE.
	23	*
	24	* Authors: Dave Airlie
	25	* Alex Deucher
	26	* Jerome Glisse
	27	*/
	28	#include "drmP.h"
	29	#include "drm.h"
	30	#include "radeon_drm.h"
	31	#include "radeon_reg.h"
	32	#include "radeon.h"
	33
44ca7478	34	#include "r100d.h"
551ebd83 DA	35	#include "r200_reg_safe.h"
	36
	37	#include "r100_track.h"
	38
	39	static int r200_get_vtx_size_0(uint32_t vtx_fmt_0)
	40	{
	41	int vtx_size, i;
	42	vtx_size = 2;
	43
	44	if (vtx_fmt_0 & R200_VTX_Z0)
	45	vtx_size++;
	46	if (vtx_fmt_0 & R200_VTX_W0)
	47	vtx_size++;
	48	/* blend weight */
	49	if (vtx_fmt_0 & (0x7 << R200_VTX_WEIGHT_COUNT_SHIFT))
	50	vtx_size += (vtx_fmt_0 >> R200_VTX_WEIGHT_COUNT_SHIFT) & 0x7;
	51	if (vtx_fmt_0 & R200_VTX_PV_MATRIX_SEL)
	52	vtx_size++;
	53	if (vtx_fmt_0 & R200_VTX_N0)
	54	vtx_size += 3;
	55	if (vtx_fmt_0 & R200_VTX_POINT_SIZE)
	56	vtx_size++;
	57	if (vtx_fmt_0 & R200_VTX_DISCRETE_FOG)
	58	vtx_size++;
	59	if (vtx_fmt_0 & R200_VTX_SHININESS_0)
	60	vtx_size++;
	61	if (vtx_fmt_0 & R200_VTX_SHININESS_1)
	62	vtx_size++;
	63	for (i = 0; i < 8; i++) {
	64	int color_size = (vtx_fmt_0 >> (11 + 2*i)) & 0x3;
	65	switch (color_size) {
	66	case 0: break;
	67	case 1: vtx_size++; break;
	68	case 2: vtx_size += 3; break;
	69	case 3: vtx_size += 4; break;
	70	}
	71	}
	72	if (vtx_fmt_0 & R200_VTX_XY1)
	73	vtx_size += 2;
	74	if (vtx_fmt_0 & R200_VTX_Z1)
	75	vtx_size++;
	76	if (vtx_fmt_0 & R200_VTX_W1)
	77	vtx_size++;
	78	if (vtx_fmt_0 & R200_VTX_N1)
	79	vtx_size += 3;
	80	return vtx_size;
	81	}
	82
44ca7478 PN	83	int r200_copy_dma(struct radeon_device *rdev,
	84	uint64_t src_offset,
	85	uint64_t dst_offset,
	86	unsigned num_pages,
	87	struct radeon_fence *fence)
	88	{
	89	uint32_t size;
	90	uint32_t cur_size;
	91	int i, num_loops;
	92	int r = 0;
	93
	94	/* radeon pitch is /64 */
	95	size = num_pages << PAGE_SHIFT;
	96	num_loops = DIV_ROUND_UP(size, 0x1FFFFF);
	97	r = radeon_ring_lock(rdev, num_loops * 4 + 64);
	98	if (r) {
	99	DRM_ERROR("radeon: moving bo (%d).\n", r);
	100	return r;
	101	}
	102	/* Must wait for 2D idle & clean before DMA or hangs might happen */
	103	radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
	104	radeon_ring_write(rdev, (1 << 16));
	105	for (i = 0; i < num_loops; i++) {
	106	cur_size = size;
	107	if (cur_size > 0x1FFFFF) {
	108	cur_size = 0x1FFFFF;
	109	}
	110	size -= cur_size;
	111	radeon_ring_write(rdev, PACKET0(0x720, 2));
	112	radeon_ring_write(rdev, src_offset);
	113	radeon_ring_write(rdev, dst_offset);
	114	radeon_ring_write(rdev, cur_size \| (1 << 31) \| (1 << 30));
	115	src_offset += cur_size;
	116	dst_offset += cur_size;
	117	}
	118	radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
	119	radeon_ring_write(rdev, RADEON_WAIT_DMA_GUI_IDLE);
	120	if (fence) {
	121	r = radeon_fence_emit(rdev, fence);
	122	}
	123	radeon_ring_unlock_commit(rdev);
	124	return r;
	125	}
	126
	127
551ebd83 DA	128	static int r200_get_vtx_size_1(uint32_t vtx_fmt_1)
	129	{
	130	int vtx_size, i, tex_size;
	131	vtx_size = 0;
	132	for (i = 0; i < 6; i++) {
	133	tex_size = (vtx_fmt_1 >> (i * 3)) & 0x7;
	134	if (tex_size > 4)
	135	continue;
	136	vtx_size += tex_size;
	137	}
	138	return vtx_size;
	139	}
	140
	141	int r200_packet0_check(struct radeon_cs_parser *p,
	142	struct radeon_cs_packet *pkt,
	143	unsigned idx, unsigned reg)
	144	{
551ebd83 DA	145	struct radeon_cs_reloc *reloc;
	146	struct r100_cs_track *track;
	147	volatile uint32_t *ib;
	148	uint32_t tmp;
	149	int r;
	150	int i;
	151	int face;
	152	u32 tile_flags = 0;
513bcb46	153	u32 idx_value;
551ebd83 DA	154
551ebd83 DA	155	ib = p->ib->ptr;
551ebd83	156	track = (struct r100_cs_track *)p->track;
513bcb46	157	idx_value = radeon_get_ib_value(p, idx);
551ebd83 DA	158	switch (reg) {
	159	case RADEON_CRTC_GUI_TRIG_VLINE:
	160	r = r100_cs_packet_parse_vline(p);
	161	if (r) {
	162	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
	163	idx, reg);
	164	r100_cs_dump_packet(p, pkt);
	165	return r;
	166	}
	167	break;
	168	/* FIXME: only allow PACKET3 blit? easier to check for out of
	169	* range access */
	170	case RADEON_DST_PITCH_OFFSET:
	171	case RADEON_SRC_PITCH_OFFSET:
	172	r = r100_reloc_pitch_offset(p, pkt, idx, reg);
	173	if (r)
	174	return r;
	175	break;
	176	case RADEON_RB3D_DEPTHOFFSET:
	177	r = r100_cs_packet_next_reloc(p, &reloc);
	178	if (r) {
	179	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
	180	idx, reg);
	181	r100_cs_dump_packet(p, pkt);
	182	return r;
	183	}
	184	track->zb.robj = reloc->robj;
513bcb46 DA	185	track->zb.offset = idx_value;
513bcb46 DA	186	ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83 DA	187	break;
	188	case RADEON_RB3D_COLOROFFSET:
	189	r = r100_cs_packet_next_reloc(p, &reloc);
	190	if (r) {
	191	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
	192	idx, reg);
	193	r100_cs_dump_packet(p, pkt);
	194	return r;
	195	}
	196	track->cb[0].robj = reloc->robj;
513bcb46 DA	197	track->cb[0].offset = idx_value;
513bcb46 DA	198	ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83 DA	199	break;
	200	case R200_PP_TXOFFSET_0:
	201	case R200_PP_TXOFFSET_1:
	202	case R200_PP_TXOFFSET_2:
	203	case R200_PP_TXOFFSET_3:
	204	case R200_PP_TXOFFSET_4:
	205	case R200_PP_TXOFFSET_5:
	206	i = (reg - R200_PP_TXOFFSET_0) / 24;
	207	r = r100_cs_packet_next_reloc(p, &reloc);
	208	if (r) {
	209	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
	210	idx, reg);
	211	r100_cs_dump_packet(p, pkt);
	212	return r;
	213	}
513bcb46	214	ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83 DA	215	track->textures[i].robj = reloc->robj;
	216	break;
	217	case R200_PP_CUBIC_OFFSET_F1_0:
	218	case R200_PP_CUBIC_OFFSET_F2_0:
	219	case R200_PP_CUBIC_OFFSET_F3_0:
	220	case R200_PP_CUBIC_OFFSET_F4_0:
	221	case R200_PP_CUBIC_OFFSET_F5_0:
	222	case R200_PP_CUBIC_OFFSET_F1_1:
	223	case R200_PP_CUBIC_OFFSET_F2_1:
	224	case R200_PP_CUBIC_OFFSET_F3_1:
	225	case R200_PP_CUBIC_OFFSET_F4_1:
	226	case R200_PP_CUBIC_OFFSET_F5_1:
	227	case R200_PP_CUBIC_OFFSET_F1_2:
	228	case R200_PP_CUBIC_OFFSET_F2_2:
	229	case R200_PP_CUBIC_OFFSET_F3_2:
	230	case R200_PP_CUBIC_OFFSET_F4_2:
	231	case R200_PP_CUBIC_OFFSET_F5_2:
	232	case R200_PP_CUBIC_OFFSET_F1_3:
	233	case R200_PP_CUBIC_OFFSET_F2_3:
	234	case R200_PP_CUBIC_OFFSET_F3_3:
	235	case R200_PP_CUBIC_OFFSET_F4_3:
	236	case R200_PP_CUBIC_OFFSET_F5_3:
	237	case R200_PP_CUBIC_OFFSET_F1_4:
	238	case R200_PP_CUBIC_OFFSET_F2_4:
	239	case R200_PP_CUBIC_OFFSET_F3_4:
	240	case R200_PP_CUBIC_OFFSET_F4_4:
	241	case R200_PP_CUBIC_OFFSET_F5_4:
	242	case R200_PP_CUBIC_OFFSET_F1_5:
	243	case R200_PP_CUBIC_OFFSET_F2_5:
	244	case R200_PP_CUBIC_OFFSET_F3_5:
	245	case R200_PP_CUBIC_OFFSET_F4_5:
	246	case R200_PP_CUBIC_OFFSET_F5_5:
	247	i = (reg - R200_PP_TXOFFSET_0) / 24;
	248	face = (reg - ((i * 24) + R200_PP_TXOFFSET_0)) / 4;
	249	r = r100_cs_packet_next_reloc(p, &reloc);
	250	if (r) {
	251	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
	252	idx, reg);
	253	r100_cs_dump_packet(p, pkt);
	254	return r;
	255	}
513bcb46 DA	256	track->textures[i].cube_info[face - 1].offset = idx_value;
513bcb46 DA	257	ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83 DA	258	track->textures[i].cube_info[face - 1].robj = reloc->robj;
	259	break;
	260	case RADEON_RE_WIDTH_HEIGHT:
513bcb46	261	track->maxy = ((idx_value >> 16) & 0x7FF);
551ebd83 DA	262	break;
	263	case RADEON_RB3D_COLORPITCH:
	264	r = r100_cs_packet_next_reloc(p, &reloc);
	265	if (r) {
	266	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
	267	idx, reg);
	268	r100_cs_dump_packet(p, pkt);
	269	return r;
	270	}
	271
	272	if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
	273	tile_flags \|= RADEON_COLOR_TILE_ENABLE;
	274	if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
	275	tile_flags \|= RADEON_COLOR_MICROTILE_ENABLE;
	276
513bcb46	277	tmp = idx_value & ~(0x7 << 16);
551ebd83 DA	278	tmp \|= tile_flags;
	279	ib[idx] = tmp;
	280
513bcb46	281	track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
551ebd83 DA	282	break;
551ebd83 DA	283	case RADEON_RB3D_DEPTHPITCH:
513bcb46	284	track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
551ebd83 DA	285	break;
551ebd83 DA	286	case RADEON_RB3D_CNTL:
513bcb46	287	switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
551ebd83 DA	288	case 7:
	289	case 8:
	290	case 9:
	291	case 11:
	292	case 12:
	293	track->cb[0].cpp = 1;
	294	break;
	295	case 3:
	296	case 4:
	297	case 15:
	298	track->cb[0].cpp = 2;
	299	break;
	300	case 6:
	301	track->cb[0].cpp = 4;
	302	break;
	303	default:
	304	DRM_ERROR("Invalid color buffer format (%d) !\n",
513bcb46	305	((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
551ebd83 DA	306	return -EINVAL;
551ebd83 DA	307	}
513bcb46	308	if (idx_value & RADEON_DEPTHXY_OFFSET_ENABLE) {
551ebd83 DA	309	DRM_ERROR("No support for depth xy offset in kms\n");
	310	return -EINVAL;
	311	}
	312
513bcb46	313	track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
551ebd83 DA	314	break;
551ebd83 DA	315	case RADEON_RB3D_ZSTENCILCNTL:
513bcb46	316	switch (idx_value & 0xf) {
551ebd83 DA	317	case 0:
	318	track->zb.cpp = 2;
	319	break;
	320	case 2:
	321	case 3:
	322	case 4:
	323	case 5:
	324	case 9:
	325	case 11:
	326	track->zb.cpp = 4;
	327	break;
	328	default:
	329	break;
	330	}
	331	break;
	332	case RADEON_RB3D_ZPASS_ADDR:
	333	r = r100_cs_packet_next_reloc(p, &reloc);
	334	if (r) {
	335	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
	336	idx, reg);
	337	r100_cs_dump_packet(p, pkt);
	338	return r;
	339	}
513bcb46	340	ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83 DA	341	break;
	342	case RADEON_PP_CNTL:
	343	{
513bcb46	344	uint32_t temp = idx_value >> 4;
551ebd83 DA	345	for (i = 0; i < track->num_texture; i++)
	346	track->textures[i].enabled = !!(temp & (1 << i));
	347	}
	348	break;
	349	case RADEON_SE_VF_CNTL:
513bcb46	350	track->vap_vf_cntl = idx_value;
551ebd83 DA	351	break;
	352	case 0x210c:
	353	/* VAP_VF_MAX_VTX_INDX */
513bcb46	354	track->max_indx = idx_value & 0x00FFFFFFUL;
551ebd83 DA	355	break;
551ebd83 DA	356	case R200_SE_VTX_FMT_0:
513bcb46	357	track->vtx_size = r200_get_vtx_size_0(idx_value);
551ebd83 DA	358	break;
551ebd83 DA	359	case R200_SE_VTX_FMT_1:
513bcb46	360	track->vtx_size += r200_get_vtx_size_1(idx_value);
551ebd83 DA	361	break;
	362	case R200_PP_TXSIZE_0:
	363	case R200_PP_TXSIZE_1:
	364	case R200_PP_TXSIZE_2:
	365	case R200_PP_TXSIZE_3:
	366	case R200_PP_TXSIZE_4:
	367	case R200_PP_TXSIZE_5:
	368	i = (reg - R200_PP_TXSIZE_0) / 32;
513bcb46 DA	369	track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
513bcb46 DA	370	track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
551ebd83 DA	371	break;
	372	case R200_PP_TXPITCH_0:
	373	case R200_PP_TXPITCH_1:
	374	case R200_PP_TXPITCH_2:
	375	case R200_PP_TXPITCH_3:
	376	case R200_PP_TXPITCH_4:
	377	case R200_PP_TXPITCH_5:
	378	i = (reg - R200_PP_TXPITCH_0) / 32;
513bcb46	379	track->textures[i].pitch = idx_value + 32;
551ebd83 DA	380	break;
	381	case R200_PP_TXFILTER_0:
	382	case R200_PP_TXFILTER_1:
	383	case R200_PP_TXFILTER_2:
	384	case R200_PP_TXFILTER_3:
	385	case R200_PP_TXFILTER_4:
	386	case R200_PP_TXFILTER_5:
	387	i = (reg - R200_PP_TXFILTER_0) / 32;
513bcb46	388	track->textures[i].num_levels = ((idx_value & R200_MAX_MIP_LEVEL_MASK)
551ebd83	389	>> R200_MAX_MIP_LEVEL_SHIFT);
513bcb46	390	tmp = (idx_value >> 23) & 0x7;
551ebd83 DA	391	if (tmp == 2 \|\| tmp == 6)
551ebd83 DA	392	track->textures[i].roundup_w = false;
513bcb46	393	tmp = (idx_value >> 27) & 0x7;
551ebd83 DA	394	if (tmp == 2 \|\| tmp == 6)
	395	track->textures[i].roundup_h = false;
	396	break;
	397	case R200_PP_TXMULTI_CTL_0:
	398	case R200_PP_TXMULTI_CTL_1:
	399	case R200_PP_TXMULTI_CTL_2:
	400	case R200_PP_TXMULTI_CTL_3:
	401	case R200_PP_TXMULTI_CTL_4:
	402	case R200_PP_TXMULTI_CTL_5:
	403	i = (reg - R200_PP_TXMULTI_CTL_0) / 32;
	404	break;
	405	case R200_PP_TXFORMAT_X_0:
	406	case R200_PP_TXFORMAT_X_1:
	407	case R200_PP_TXFORMAT_X_2:
	408	case R200_PP_TXFORMAT_X_3:
	409	case R200_PP_TXFORMAT_X_4:
	410	case R200_PP_TXFORMAT_X_5:
	411	i = (reg - R200_PP_TXFORMAT_X_0) / 32;
513bcb46 DA	412	track->textures[i].txdepth = idx_value & 0x7;
513bcb46 DA	413	tmp = (idx_value >> 16) & 0x3;
551ebd83 DA	414	/* 2D, 3D, CUBE */
	415	switch (tmp) {
	416	case 0:
	417	case 5:
	418	case 6:
	419	case 7:
f3d1ccc1	420	/* 1D/2D */
551ebd83 DA	421	track->textures[i].tex_coord_type = 0;
	422	break;
	423	case 1:
f3d1ccc1 AR	424	/* CUBE */
f3d1ccc1 AR	425	track->textures[i].tex_coord_type = 2;
551ebd83 DA	426	break;
551ebd83 DA	427	case 2:
f3d1ccc1 AR	428	/* 3D */
f3d1ccc1 AR	429	track->textures[i].tex_coord_type = 1;
551ebd83 DA	430	break;
	431	}
	432	break;
	433	case R200_PP_TXFORMAT_0:
	434	case R200_PP_TXFORMAT_1:
	435	case R200_PP_TXFORMAT_2:
	436	case R200_PP_TXFORMAT_3:
	437	case R200_PP_TXFORMAT_4:
	438	case R200_PP_TXFORMAT_5:
	439	i = (reg - R200_PP_TXFORMAT_0) / 32;
513bcb46	440	if (idx_value & R200_TXFORMAT_NON_POWER2) {
551ebd83 DA	441	track->textures[i].use_pitch = 1;
	442	} else {
	443	track->textures[i].use_pitch = 0;
513bcb46 DA	444	track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
513bcb46 DA	445	track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
551ebd83	446	}
513bcb46	447	switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
551ebd83 DA	448	case R200_TXFORMAT_I8:
	449	case R200_TXFORMAT_RGB332:
	450	case R200_TXFORMAT_Y8:
	451	track->textures[i].cpp = 1;
	452	break;
551ebd83 DA	453	case R200_TXFORMAT_AI88:
	454	case R200_TXFORMAT_ARGB1555:
	455	case R200_TXFORMAT_RGB565:
	456	case R200_TXFORMAT_ARGB4444:
	457	case R200_TXFORMAT_VYUY422:
	458	case R200_TXFORMAT_YVYU422:
	459	case R200_TXFORMAT_LDVDU655:
	460	case R200_TXFORMAT_DVDU88:
	461	case R200_TXFORMAT_AVYU4444:
	462	track->textures[i].cpp = 2;
	463	break;
	464	case R200_TXFORMAT_ARGB8888:
	465	case R200_TXFORMAT_RGBA8888:
	466	case R200_TXFORMAT_ABGR8888:
	467	case R200_TXFORMAT_BGR111110:
	468	case R200_TXFORMAT_LDVDU8888:
d785d78b DA	469	track->textures[i].cpp = 4;
	470	break;
	471	case R200_TXFORMAT_DXT1:
	472	track->textures[i].cpp = 1;
	473	track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
	474	break;
551ebd83 DA	475	case R200_TXFORMAT_DXT23:
551ebd83 DA	476	case R200_TXFORMAT_DXT45:
d785d78b DA	477	track->textures[i].cpp = 1;
d785d78b DA	478	track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
551ebd83 DA	479	break;
551ebd83 DA	480	}
513bcb46 DA	481	track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
513bcb46 DA	482	track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
551ebd83 DA	483	break;
	484	case R200_PP_CUBIC_FACES_0:
	485	case R200_PP_CUBIC_FACES_1:
	486	case R200_PP_CUBIC_FACES_2:
	487	case R200_PP_CUBIC_FACES_3:
	488	case R200_PP_CUBIC_FACES_4:
	489	case R200_PP_CUBIC_FACES_5:
513bcb46	490	tmp = idx_value;
551ebd83 DA	491	i = (reg - R200_PP_CUBIC_FACES_0) / 32;
	492	for (face = 0; face < 4; face++) {
	493	track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
	494	track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
	495	}
	496	break;
	497	default:
	498	printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
	499	reg, idx);
	500	return -EINVAL;
	501	}
	502	return 0;
	503	}
	504
d4550907	505	void r200_set_safe_registers(struct radeon_device *rdev)
551ebd83 DA	506	{
	507	rdev->config.r100.reg_safe_bm = r200_reg_safe_bm;
	508	rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r200_reg_safe_bm);
551ebd83	509	}