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Merge branch 'drm-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied...
[deliverable/linux.git] / drivers / gpu / drm / radeon / r300.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#include <linux/seq_file.h>
29#include "drmP.h"
30#include "drm.h"
31#include "radeon_reg.h"
32#include "radeon.h"
e024e110 33#include "radeon_drm.h"
551ebd83 34#include "r100_track.h"
3ce0a23d 35#include "r300d.h"
ca6ffc64 36#include "rv350d.h"
50f15303
DA		 37#include "r300_reg_safe.h"
38
cafe6609
JG		 39/* This files gather functions specifics to: r300,r350,rv350,rv370,rv380
40 *
41 * GPU Errata:
42 * - HOST_PATH_CNTL: r300 family seems to dislike write to HOST_PATH_CNTL
43 * using MMIO to flush host path read cache, this lead to HARDLOCKUP.
44 * However, scheduling such write to the ring seems harmless, i suspect
45 * the CP read collide with the flush somehow, or maybe the MC, hard to
46 * tell. (Jerome Glisse)
47 */
771fe6b9
JG		 48
49/*
50 * rv370,rv380 PCIE GART
51 */
207bf9e9
JG		 52static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev);
53
771fe6b9
JG		 54void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev)
55{
56 uint32_t tmp;
57 int i;
58
59 /* Workaround HW bug do flush 2 times */
60 for (i = 0; i < 2; i++) {
61 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
62 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp | RADEON_PCIE_TX_GART_INVALIDATE_TLB);
63 (void)RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
64 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
771fe6b9 65 }
de1b2898 66 mb();
771fe6b9
JG		 67}
68
4aac0473
JG		 69int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
70{
71 void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
72
73 if (i < 0 || i > rdev->gart.num_gpu_pages) {
74 return -EINVAL;
75 }
76 addr = (lower_32_bits(addr) >> 8) |
77 ((upper_32_bits(addr) & 0xff) << 24) |
78 0xc;
79 /* on x86 we want this to be CPU endian, on powerpc
80 * on powerpc without HW swappers, it'll get swapped on way
81 * into VRAM - so no need for cpu_to_le32 on VRAM tables */
82 writel(addr, ((void __iomem *)ptr) + (i * 4));
83 return 0;
84}
85
86int rv370_pcie_gart_init(struct radeon_device *rdev)
771fe6b9 87{
771fe6b9
JG		 88 int r;
89
4aac0473
JG		 90 if (rdev->gart.table.vram.robj) {
91 WARN(1, "RV370 PCIE GART already initialized.\n");
92 return 0;
93 }
771fe6b9
JG		 94 /* Initialize common gart structure */
95 r = radeon_gart_init(rdev);
4aac0473 96 if (r)
771fe6b9 97 return r;
771fe6b9 98 r = rv370_debugfs_pcie_gart_info_init(rdev);
4aac0473 99 if (r)
771fe6b9 100 DRM_ERROR("Failed to register debugfs file for PCIE gart !\n");
771fe6b9 101 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
4aac0473
JG		 102 rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
103 rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
104 return radeon_gart_table_vram_alloc(rdev);
105}
106
107int rv370_pcie_gart_enable(struct radeon_device *rdev)
108{
109 uint32_t table_addr;
110 uint32_t tmp;
111 int r;
112
113 if (rdev->gart.table.vram.robj == NULL) {
114 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
115 return -EINVAL;
771fe6b9 116 }
4aac0473
JG		 117 r = radeon_gart_table_vram_pin(rdev);
118 if (r)
119 return r;
82568565 120 radeon_gart_restore(rdev);
771fe6b9
JG		 121 /* discard memory request outside of configured range */
122 tmp = RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
123 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
d594e46a
JG		 124 WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, rdev->mc.gtt_start);
125 tmp = rdev->mc.gtt_end & ~RADEON_GPU_PAGE_MASK;
771fe6b9
JG		 126 WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, tmp);
127 WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0);
128 WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0);
129 table_addr = rdev->gart.table_addr;
130 WREG32_PCIE(RADEON_PCIE_TX_GART_BASE, table_addr);
131 /* FIXME: setup default page */
d594e46a 132 WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, rdev->mc.vram_start);
771fe6b9
JG		 133 WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_HI, 0);
134 /* Clear error */
135 WREG32_PCIE(0x18, 0);
136 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
137 tmp |= RADEON_PCIE_TX_GART_EN;
138 tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
139 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
140 rv370_pcie_gart_tlb_flush(rdev);
141 DRM_INFO("PCIE GART of %uM enabled (table at 0x%08X).\n",
3ce0a23d 142 (unsigned)(rdev->mc.gtt_size >> 20), table_addr);
771fe6b9
JG		 143 rdev->gart.ready = true;
144 return 0;
145}
146
147void rv370_pcie_gart_disable(struct radeon_device *rdev)
148{
4c788679
JG		 149 u32 tmp;
150 int r;
771fe6b9
JG		 151
152 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
153 tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
154 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp & ~RADEON_PCIE_TX_GART_EN);
155 if (rdev->gart.table.vram.robj) {
4c788679
JG		 156 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
157 if (likely(r == 0)) {
158 radeon_bo_kunmap(rdev->gart.table.vram.robj);
159 radeon_bo_unpin(rdev->gart.table.vram.robj);
160 radeon_bo_unreserve(rdev->gart.table.vram.robj);
161 }
771fe6b9
JG		 162 }
163}
164
4aac0473 165void rv370_pcie_gart_fini(struct radeon_device *rdev)
771fe6b9 166{
4aac0473
JG		 167 rv370_pcie_gart_disable(rdev);
168 radeon_gart_table_vram_free(rdev);
169 radeon_gart_fini(rdev);
771fe6b9
JG		 170}
171
771fe6b9
JG		 172void r300_fence_ring_emit(struct radeon_device *rdev,
173 struct radeon_fence *fence)
174{
175 /* Who ever call radeon_fence_emit should call ring_lock and ask
176 * for enough space (today caller are ib schedule and buffer move) */
177 /* Write SC register so SC & US assert idle */
4612dc97 178 radeon_ring_write(rdev, PACKET0(R300_RE_SCISSORS_TL, 0));
771fe6b9 179 radeon_ring_write(rdev, 0);
4612dc97 180 radeon_ring_write(rdev, PACKET0(R300_RE_SCISSORS_BR, 0));
771fe6b9
JG		 181 radeon_ring_write(rdev, 0);
182 /* Flush 3D cache */
4612dc97
AD		 183 radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
184 radeon_ring_write(rdev, R300_RB3D_DC_FLUSH);
185 radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
186 radeon_ring_write(rdev, R300_ZC_FLUSH);
771fe6b9 187 /* Wait until IDLE & CLEAN */
4612dc97
AD		 188 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
189 radeon_ring_write(rdev, (RADEON_WAIT_3D_IDLECLEAN |
190 RADEON_WAIT_2D_IDLECLEAN |
191 RADEON_WAIT_DMA_GUI_IDLE));
cafe6609
JG		 192 radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
193 radeon_ring_write(rdev, rdev->config.r300.hdp_cntl |
194 RADEON_HDP_READ_BUFFER_INVALIDATE);
195 radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
196 radeon_ring_write(rdev, rdev->config.r300.hdp_cntl);
771fe6b9
JG		 197 /* Emit fence sequence & fire IRQ */
198 radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
199 radeon_ring_write(rdev, fence->seq);
200 radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0));
201 radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
202}
203
771fe6b9
JG		 204void r300_ring_start(struct radeon_device *rdev)
205{
206 unsigned gb_tile_config;
207 int r;
208
209 /* Sub pixel 1/12 so we can have 4K rendering according to doc */
210 gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16);
068a117c 211 switch(rdev->num_gb_pipes) {
771fe6b9
JG		 212 case 2:
213 gb_tile_config |= R300_PIPE_COUNT_R300;
214 break;
215 case 3:
216 gb_tile_config |= R300_PIPE_COUNT_R420_3P;
217 break;
218 case 4:
219 gb_tile_config |= R300_PIPE_COUNT_R420;
220 break;
221 case 1:
222 default:
223 gb_tile_config |= R300_PIPE_COUNT_RV350;
224 break;
225 }
226
227 r = radeon_ring_lock(rdev, 64);
228 if (r) {
229 return;
230 }
231 radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
232 radeon_ring_write(rdev,
233 RADEON_ISYNC_ANY2D_IDLE3D |
234 RADEON_ISYNC_ANY3D_IDLE2D |
235 RADEON_ISYNC_WAIT_IDLEGUI |
236 RADEON_ISYNC_CPSCRATCH_IDLEGUI);
237 radeon_ring_write(rdev, PACKET0(R300_GB_TILE_CONFIG, 0));
238 radeon_ring_write(rdev, gb_tile_config);
239 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
240 radeon_ring_write(rdev,
241 RADEON_WAIT_2D_IDLECLEAN |
242 RADEON_WAIT_3D_IDLECLEAN);
4612dc97
AD		 243 radeon_ring_write(rdev, PACKET0(R300_DST_PIPE_CONFIG, 0));
244 radeon_ring_write(rdev, R300_PIPE_AUTO_CONFIG);
771fe6b9
JG		 245 radeon_ring_write(rdev, PACKET0(R300_GB_SELECT, 0));
246 radeon_ring_write(rdev, 0);
247 radeon_ring_write(rdev, PACKET0(R300_GB_ENABLE, 0));
248 radeon_ring_write(rdev, 0);
249 radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
250 radeon_ring_write(rdev, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE);
251 radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
252 radeon_ring_write(rdev, R300_ZC_FLUSH | R300_ZC_FREE);
253 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
254 radeon_ring_write(rdev,
255 RADEON_WAIT_2D_IDLECLEAN |
256 RADEON_WAIT_3D_IDLECLEAN);
257 radeon_ring_write(rdev, PACKET0(R300_GB_AA_CONFIG, 0));
258 radeon_ring_write(rdev, 0);
259 radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
260 radeon_ring_write(rdev, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE);
261 radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
262 radeon_ring_write(rdev, R300_ZC_FLUSH | R300_ZC_FREE);
263 radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS0, 0));
264 radeon_ring_write(rdev,
265 ((6 << R300_MS_X0_SHIFT) |
266 (6 << R300_MS_Y0_SHIFT) |
267 (6 << R300_MS_X1_SHIFT) |
268 (6 << R300_MS_Y1_SHIFT) |
269 (6 << R300_MS_X2_SHIFT) |
270 (6 << R300_MS_Y2_SHIFT) |
271 (6 << R300_MSBD0_Y_SHIFT) |
272 (6 << R300_MSBD0_X_SHIFT)));
273 radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS1, 0));
274 radeon_ring_write(rdev,
275 ((6 << R300_MS_X3_SHIFT) |
276 (6 << R300_MS_Y3_SHIFT) |
277 (6 << R300_MS_X4_SHIFT) |
278 (6 << R300_MS_Y4_SHIFT) |
279 (6 << R300_MS_X5_SHIFT) |
280 (6 << R300_MS_Y5_SHIFT) |
281 (6 << R300_MSBD1_SHIFT)));
282 radeon_ring_write(rdev, PACKET0(R300_GA_ENHANCE, 0));
283 radeon_ring_write(rdev, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL);
284 radeon_ring_write(rdev, PACKET0(R300_GA_POLY_MODE, 0));
285 radeon_ring_write(rdev,
286 R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE);
287 radeon_ring_write(rdev, PACKET0(R300_GA_ROUND_MODE, 0));
288 radeon_ring_write(rdev,
289 R300_GEOMETRY_ROUND_NEAREST |
290 R300_COLOR_ROUND_NEAREST);
291 radeon_ring_unlock_commit(rdev);
292}
293
294void r300_errata(struct radeon_device *rdev)
295{
296 rdev->pll_errata = 0;
297
298 if (rdev->family == CHIP_R300 &&
299 (RREG32(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) == RADEON_CFG_ATI_REV_A11) {
300 rdev->pll_errata |= CHIP_ERRATA_R300_CG;
301 }
302}
303
304int r300_mc_wait_for_idle(struct radeon_device *rdev)
305{
306 unsigned i;
307 uint32_t tmp;
308
309 for (i = 0; i < rdev->usec_timeout; i++) {
310 /* read MC_STATUS */
4612dc97
AD		 311 tmp = RREG32(RADEON_MC_STATUS);
312 if (tmp & R300_MC_IDLE) {
771fe6b9
JG		 313 return 0;
314 }
315 DRM_UDELAY(1);
316 }
317 return -1;
318}
319
320void r300_gpu_init(struct radeon_device *rdev)
321{
322 uint32_t gb_tile_config, tmp;
323
324 r100_hdp_reset(rdev);
325 /* FIXME: rv380 one pipes ? */
326 if ((rdev->family == CHIP_R300) || (rdev->family == CHIP_R350)) {
327 /* r300,r350 */
328 rdev->num_gb_pipes = 2;
329 } else {
330 /* rv350,rv370,rv380 */
331 rdev->num_gb_pipes = 1;
332 }
f779b3e5 333 rdev->num_z_pipes = 1;
771fe6b9
JG		 334 gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16);
335 switch (rdev->num_gb_pipes) {
336 case 2:
337 gb_tile_config |= R300_PIPE_COUNT_R300;
338 break;
339 case 3:
340 gb_tile_config |= R300_PIPE_COUNT_R420_3P;
341 break;
342 case 4:
343 gb_tile_config |= R300_PIPE_COUNT_R420;
344 break;
771fe6b9 345 default:
068a117c 346 case 1:
771fe6b9
JG		 347 gb_tile_config |= R300_PIPE_COUNT_RV350;
348 break;
349 }
350 WREG32(R300_GB_TILE_CONFIG, gb_tile_config);
351
352 if (r100_gui_wait_for_idle(rdev)) {
353 printk(KERN_WARNING "Failed to wait GUI idle while "
354 "programming pipes. Bad things might happen.\n");
355 }
356
4612dc97
AD		 357 tmp = RREG32(R300_DST_PIPE_CONFIG);
358 WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG);
771fe6b9
JG		 359
360 WREG32(R300_RB2D_DSTCACHE_MODE,
361 R300_DC_AUTOFLUSH_ENABLE |
362 R300_DC_DC_DISABLE_IGNORE_PE);
363
364 if (r100_gui_wait_for_idle(rdev)) {
365 printk(KERN_WARNING "Failed to wait GUI idle while "
366 "programming pipes. Bad things might happen.\n");
367 }
368 if (r300_mc_wait_for_idle(rdev)) {
369 printk(KERN_WARNING "Failed to wait MC idle while "
370 "programming pipes. Bad things might happen.\n");
371 }
f779b3e5
AD		 372 DRM_INFO("radeon: %d quad pipes, %d Z pipes initialized.\n",
373 rdev->num_gb_pipes, rdev->num_z_pipes);
771fe6b9
JG		 374}
375
376int r300_ga_reset(struct radeon_device *rdev)
377{
378 uint32_t tmp;
379 bool reinit_cp;
380 int i;
381
382 reinit_cp = rdev->cp.ready;
383 rdev->cp.ready = false;
384 for (i = 0; i < rdev->usec_timeout; i++) {
385 WREG32(RADEON_CP_CSQ_MODE, 0);
386 WREG32(RADEON_CP_CSQ_CNTL, 0);
387 WREG32(RADEON_RBBM_SOFT_RESET, 0x32005);
388 (void)RREG32(RADEON_RBBM_SOFT_RESET);
389 udelay(200);
390 WREG32(RADEON_RBBM_SOFT_RESET, 0);
391 /* Wait to prevent race in RBBM_STATUS */
392 mdelay(1);
393 tmp = RREG32(RADEON_RBBM_STATUS);
394 if (tmp & ((1 << 20) | (1 << 26))) {
395 DRM_ERROR("VAP & CP still busy (RBBM_STATUS=0x%08X)", tmp);
396 /* GA still busy soft reset it */
397 WREG32(0x429C, 0x200);
398 WREG32(R300_VAP_PVS_STATE_FLUSH_REG, 0);
4612dc97
AD		 399 WREG32(R300_RE_SCISSORS_TL, 0);
400 WREG32(R300_RE_SCISSORS_BR, 0);
771fe6b9
JG		 401 WREG32(0x24AC, 0);
402 }
403 /* Wait to prevent race in RBBM_STATUS */
404 mdelay(1);
405 tmp = RREG32(RADEON_RBBM_STATUS);
406 if (!(tmp & ((1 << 20) | (1 << 26)))) {
407 break;
408 }
409 }
410 for (i = 0; i < rdev->usec_timeout; i++) {
411 tmp = RREG32(RADEON_RBBM_STATUS);
412 if (!(tmp & ((1 << 20) | (1 << 26)))) {
413 DRM_INFO("GA reset succeed (RBBM_STATUS=0x%08X)\n",
414 tmp);
415 if (reinit_cp) {
416 return r100_cp_init(rdev, rdev->cp.ring_size);
417 }
418 return 0;
419 }
420 DRM_UDELAY(1);
421 }
422 tmp = RREG32(RADEON_RBBM_STATUS);
423 DRM_ERROR("Failed to reset GA ! (RBBM_STATUS=0x%08X)\n", tmp);
424 return -1;
425}
426
427int r300_gpu_reset(struct radeon_device *rdev)
428{
429 uint32_t status;
430
431 /* reset order likely matter */
432 status = RREG32(RADEON_RBBM_STATUS);
433 /* reset HDP */
434 r100_hdp_reset(rdev);
435 /* reset rb2d */
436 if (status & ((1 << 17) | (1 << 18) | (1 << 27))) {
437 r100_rb2d_reset(rdev);
438 }
439 /* reset GA */
440 if (status & ((1 << 20) | (1 << 26))) {
441 r300_ga_reset(rdev);
442 }
443 /* reset CP */
444 status = RREG32(RADEON_RBBM_STATUS);
445 if (status & (1 << 16)) {
446 r100_cp_reset(rdev);
447 }
448 /* Check if GPU is idle */
449 status = RREG32(RADEON_RBBM_STATUS);
4612dc97 450 if (status & RADEON_RBBM_ACTIVE) {
771fe6b9
JG		 451 DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status);
452 return -1;
453 }
454 DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status);
455 return 0;
456}
457
458
459/*
460 * r300,r350,rv350,rv380 VRAM info
461 */
d594e46a 462void r300_mc_init(struct radeon_device *rdev)
771fe6b9 463{
8e361130
JG		 464 u64 base;
465 u32 tmp;
771fe6b9
JG		 466
467 /* DDR for all card after R300 & IGP */
468 rdev->mc.vram_is_ddr = true;
469 tmp = RREG32(RADEON_MEM_CNTL);
5ff55717
DA		 470 tmp &= R300_MEM_NUM_CHANNELS_MASK;
471 switch (tmp) {
472 case 0: rdev->mc.vram_width = 64; break;
473 case 1: rdev->mc.vram_width = 128; break;
474 case 2: rdev->mc.vram_width = 256; break;
475 default: rdev->mc.vram_width = 128; break;
771fe6b9 476 }
2a0f8918 477 r100_vram_init_sizes(rdev);
8e361130
JG		 478 base = rdev->mc.aper_base;
479 if (rdev->flags & RADEON_IS_IGP)
480 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
481 radeon_vram_location(rdev, &rdev->mc, base);
d594e46a
JG		 482 if (!(rdev->flags & RADEON_IS_AGP))
483 radeon_gtt_location(rdev, &rdev->mc);
771fe6b9
JG		 484}
485
771fe6b9
JG		 486void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes)
487{
488 uint32_t link_width_cntl, mask;
489
490 if (rdev->flags & RADEON_IS_IGP)
491 return;
492
493 if (!(rdev->flags & RADEON_IS_PCIE))
494 return;
495
496 /* FIXME wait for idle */
497
498 switch (lanes) {
499 case 0:
500 mask = RADEON_PCIE_LC_LINK_WIDTH_X0;
501 break;
502 case 1:
503 mask = RADEON_PCIE_LC_LINK_WIDTH_X1;
504 break;
505 case 2:
506 mask = RADEON_PCIE_LC_LINK_WIDTH_X2;
507 break;
508 case 4:
509 mask = RADEON_PCIE_LC_LINK_WIDTH_X4;
510 break;
511 case 8:
512 mask = RADEON_PCIE_LC_LINK_WIDTH_X8;
513 break;
514 case 12:
515 mask = RADEON_PCIE_LC_LINK_WIDTH_X12;
516 break;
517 case 16:
518 default:
519 mask = RADEON_PCIE_LC_LINK_WIDTH_X16;
520 break;
521 }
522
523 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
524
525 if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) ==
526 (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT))
527 return;
528
529 link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK |
530 RADEON_PCIE_LC_RECONFIG_NOW |
531 RADEON_PCIE_LC_RECONFIG_LATER |
532 RADEON_PCIE_LC_SHORT_RECONFIG_EN);
533 link_width_cntl |= mask;
534 WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
535 WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl |
536 RADEON_PCIE_LC_RECONFIG_NOW));
537
538 /* wait for lane set to complete */
539 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
540 while (link_width_cntl == 0xffffffff)
541 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
542
543}
544
c836a412
AD		 545int rv370_get_pcie_lanes(struct radeon_device *rdev)
546{
547 u32 link_width_cntl;
548
549 if (rdev->flags & RADEON_IS_IGP)
550 return 0;
551
552 if (!(rdev->flags & RADEON_IS_PCIE))
553 return 0;
554
555 /* FIXME wait for idle */
556
aa5120d2
RM		 557 if (rdev->family < CHIP_R600)
558 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
559 else
560 link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
c836a412
AD		 561
562 switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) {
563 case RADEON_PCIE_LC_LINK_WIDTH_X0:
564 return 0;
565 case RADEON_PCIE_LC_LINK_WIDTH_X1:
566 return 1;
567 case RADEON_PCIE_LC_LINK_WIDTH_X2:
568 return 2;
569 case RADEON_PCIE_LC_LINK_WIDTH_X4:
570 return 4;
571 case RADEON_PCIE_LC_LINK_WIDTH_X8:
572 return 8;
573 case RADEON_PCIE_LC_LINK_WIDTH_X16:
574 default:
575 return 16;
576 }
577}
578
771fe6b9
JG		 579#if defined(CONFIG_DEBUG_FS)
580static int rv370_debugfs_pcie_gart_info(struct seq_file *m, void *data)
581{
582 struct drm_info_node *node = (struct drm_info_node *) m->private;
583 struct drm_device *dev = node->minor->dev;
584 struct radeon_device *rdev = dev->dev_private;
585 uint32_t tmp;
586
587 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
588 seq_printf(m, "PCIE_TX_GART_CNTL 0x%08x\n", tmp);
589 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_BASE);
590 seq_printf(m, "PCIE_TX_GART_BASE 0x%08x\n", tmp);
591 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_LO);
592 seq_printf(m, "PCIE_TX_GART_START_LO 0x%08x\n", tmp);
593 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_HI);
594 seq_printf(m, "PCIE_TX_GART_START_HI 0x%08x\n", tmp);
595 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_LO);
596 seq_printf(m, "PCIE_TX_GART_END_LO 0x%08x\n", tmp);
597 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_HI);
598 seq_printf(m, "PCIE_TX_GART_END_HI 0x%08x\n", tmp);
599 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_ERROR);
600 seq_printf(m, "PCIE_TX_GART_ERROR 0x%08x\n", tmp);
601 return 0;
602}
603
604static struct drm_info_list rv370_pcie_gart_info_list[] = {
605 {"rv370_pcie_gart_info", rv370_debugfs_pcie_gart_info, 0, NULL},
606};
607#endif
608
207bf9e9 609static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev)
771fe6b9
JG		 610{
611#if defined(CONFIG_DEBUG_FS)
612 return radeon_debugfs_add_files(rdev, rv370_pcie_gart_info_list, 1);
613#else
614 return 0;
615#endif
616}
617
771fe6b9
JG		 618static int r300_packet0_check(struct radeon_cs_parser *p,
619 struct radeon_cs_packet *pkt,
620 unsigned idx, unsigned reg)
621{
771fe6b9 622 struct radeon_cs_reloc *reloc;
551ebd83 623 struct r100_cs_track *track;
771fe6b9 624 volatile uint32_t *ib;
e024e110 625 uint32_t tmp, tile_flags = 0;
771fe6b9
JG		 626 unsigned i;
627 int r;
513bcb46 628 u32 idx_value;
771fe6b9
JG		 629
630 ib = p->ib->ptr;
551ebd83 631 track = (struct r100_cs_track *)p->track;
513bcb46
DA		 632 idx_value = radeon_get_ib_value(p, idx);
633
068a117c 634 switch(reg) {
531369e6
DA		 635 case AVIVO_D1MODE_VLINE_START_END:
636 case RADEON_CRTC_GUI_TRIG_VLINE:
637 r = r100_cs_packet_parse_vline(p);
638 if (r) {
639 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
640 idx, reg);
641 r100_cs_dump_packet(p, pkt);
642 return r;
643 }
644 break;
771fe6b9
JG		 645 case RADEON_DST_PITCH_OFFSET:
646 case RADEON_SRC_PITCH_OFFSET:
551ebd83
DA		 647 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
648 if (r)
771fe6b9 649 return r;
771fe6b9
JG		 650 break;
651 case R300_RB3D_COLOROFFSET0:
652 case R300_RB3D_COLOROFFSET1:
653 case R300_RB3D_COLOROFFSET2:
654 case R300_RB3D_COLOROFFSET3:
655 i = (reg - R300_RB3D_COLOROFFSET0) >> 2;
656 r = r100_cs_packet_next_reloc(p, &reloc);
657 if (r) {
658 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
659 idx, reg);
660 r100_cs_dump_packet(p, pkt);
661 return r;
662 }
663 track->cb[i].robj = reloc->robj;
513bcb46
DA		 664 track->cb[i].offset = idx_value;
665 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
771fe6b9
JG		 666 break;
667 case R300_ZB_DEPTHOFFSET:
668 r = r100_cs_packet_next_reloc(p, &reloc);
669 if (r) {
670 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
671 idx, reg);
672 r100_cs_dump_packet(p, pkt);
673 return r;
674 }
675 track->zb.robj = reloc->robj;
513bcb46
DA		 676 track->zb.offset = idx_value;
677 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
771fe6b9
JG		 678 break;
679 case R300_TX_OFFSET_0:
680 case R300_TX_OFFSET_0+4:
681 case R300_TX_OFFSET_0+8:
682 case R300_TX_OFFSET_0+12:
683 case R300_TX_OFFSET_0+16:
684 case R300_TX_OFFSET_0+20:
685 case R300_TX_OFFSET_0+24:
686 case R300_TX_OFFSET_0+28:
687 case R300_TX_OFFSET_0+32:
688 case R300_TX_OFFSET_0+36:
689 case R300_TX_OFFSET_0+40:
690 case R300_TX_OFFSET_0+44:
691 case R300_TX_OFFSET_0+48:
692 case R300_TX_OFFSET_0+52:
693 case R300_TX_OFFSET_0+56:
694 case R300_TX_OFFSET_0+60:
068a117c 695 i = (reg - R300_TX_OFFSET_0) >> 2;
771fe6b9
JG		 696 r = r100_cs_packet_next_reloc(p, &reloc);
697 if (r) {
698 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
699 idx, reg);
700 r100_cs_dump_packet(p, pkt);
701 return r;
702 }
6e726772
MC		 703
704 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
705 tile_flags |= R300_TXO_MACRO_TILE;
706 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
707 tile_flags |= R300_TXO_MICRO_TILE;
939461d5
MO		 708 else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE)
709 tile_flags |= R300_TXO_MICRO_TILE_SQUARE;
6e726772
MC		 710
711 tmp = idx_value + ((u32)reloc->lobj.gpu_offset);
712 tmp |= tile_flags;
713 ib[idx] = tmp;
068a117c 714 track->textures[i].robj = reloc->robj;
771fe6b9
JG		 715 break;
716 /* Tracked registers */
068a117c
JG		 717 case 0x2084:
718 /* VAP_VF_CNTL */
513bcb46 719 track->vap_vf_cntl = idx_value;
068a117c
JG		 720 break;
721 case 0x20B4:
722 /* VAP_VTX_SIZE */
513bcb46 723 track->vtx_size = idx_value & 0x7F;
068a117c
JG		 724 break;
725 case 0x2134:
726 /* VAP_VF_MAX_VTX_INDX */
513bcb46 727 track->max_indx = idx_value & 0x00FFFFFFUL;
068a117c 728 break;
771fe6b9
JG		 729 case 0x43E4:
730 /* SC_SCISSOR1 */
513bcb46 731 track->maxy = ((idx_value >> 13) & 0x1FFF) + 1;
771fe6b9
JG		 732 if (p->rdev->family < CHIP_RV515) {
733 track->maxy -= 1440;
734 }
735 break;
736 case 0x4E00:
737 /* RB3D_CCTL */
513bcb46 738 track->num_cb = ((idx_value >> 5) & 0x3) + 1;
771fe6b9
JG		 739 break;
740 case 0x4E38:
741 case 0x4E3C:
742 case 0x4E40:
743 case 0x4E44:
744 /* RB3D_COLORPITCH0 */
745 /* RB3D_COLORPITCH1 */
746 /* RB3D_COLORPITCH2 */
747 /* RB3D_COLORPITCH3 */
e024e110
DA		 748 r = r100_cs_packet_next_reloc(p, &reloc);
749 if (r) {
750 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
751 idx, reg);
752 r100_cs_dump_packet(p, pkt);
753 return r;
754 }
755
756 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
757 tile_flags |= R300_COLOR_TILE_ENABLE;
758 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
759 tile_flags |= R300_COLOR_MICROTILE_ENABLE;
939461d5
MO		 760 else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE)
761 tile_flags |= R300_COLOR_MICROTILE_SQUARE_ENABLE;
e024e110 762
513bcb46 763 tmp = idx_value & ~(0x7 << 16);
e024e110
DA		 764 tmp |= tile_flags;
765 ib[idx] = tmp;
766
771fe6b9 767 i = (reg - 0x4E38) >> 2;
513bcb46
DA		 768 track->cb[i].pitch = idx_value & 0x3FFE;
769 switch (((idx_value >> 21) & 0xF)) {
771fe6b9
JG		 770 case 9:
771 case 11:
772 case 12:
773 track->cb[i].cpp = 1;
774 break;
775 case 3:
776 case 4:
777 case 13:
778 case 15:
779 track->cb[i].cpp = 2;
780 break;
781 case 6:
782 track->cb[i].cpp = 4;
783 break;
784 case 10:
785 track->cb[i].cpp = 8;
786 break;
787 case 7:
788 track->cb[i].cpp = 16;
789 break;
790 default:
791 DRM_ERROR("Invalid color buffer format (%d) !\n",
513bcb46 792 ((idx_value >> 21) & 0xF));
771fe6b9
JG		 793 return -EINVAL;
794 }
795 break;
796 case 0x4F00:
797 /* ZB_CNTL */
513bcb46 798 if (idx_value & 2) {
771fe6b9
JG		 799 track->z_enabled = true;
800 } else {
801 track->z_enabled = false;
802 }
803 break;
804 case 0x4F10:
805 /* ZB_FORMAT */
513bcb46 806 switch ((idx_value & 0xF)) {
771fe6b9
JG		 807 case 0:
808 case 1:
809 track->zb.cpp = 2;
810 break;
811 case 2:
812 track->zb.cpp = 4;
813 break;
814 default:
815 DRM_ERROR("Invalid z buffer format (%d) !\n",
513bcb46 816 (idx_value & 0xF));
771fe6b9
JG		 817 return -EINVAL;
818 }
819 break;
820 case 0x4F24:
821 /* ZB_DEPTHPITCH */
e024e110
DA		 822 r = r100_cs_packet_next_reloc(p, &reloc);
823 if (r) {
824 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
825 idx, reg);
826 r100_cs_dump_packet(p, pkt);
827 return r;
828 }
829
830 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
831 tile_flags |= R300_DEPTHMACROTILE_ENABLE;
832 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
939461d5
MO		 833 tile_flags |= R300_DEPTHMICROTILE_TILED;
834 else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE)
835 tile_flags |= R300_DEPTHMICROTILE_TILED_SQUARE;
e024e110 836
513bcb46 837 tmp = idx_value & ~(0x7 << 16);
e024e110
DA		 838 tmp |= tile_flags;
839 ib[idx] = tmp;
840
513bcb46 841 track->zb.pitch = idx_value & 0x3FFC;
771fe6b9 842 break;
068a117c
JG		 843 case 0x4104:
844 for (i = 0; i < 16; i++) {
845 bool enabled;
846
513bcb46 847 enabled = !!(idx_value & (1 << i));
068a117c
JG		 848 track->textures[i].enabled = enabled;
849 }
850 break;
851 case 0x44C0:
852 case 0x44C4:
853 case 0x44C8:
854 case 0x44CC:
855 case 0x44D0:
856 case 0x44D4:
857 case 0x44D8:
858 case 0x44DC:
859 case 0x44E0:
860 case 0x44E4:
861 case 0x44E8:
862 case 0x44EC:
863 case 0x44F0:
864 case 0x44F4:
865 case 0x44F8:
866 case 0x44FC:
867 /* TX_FORMAT1_[0-15] */
868 i = (reg - 0x44C0) >> 2;
513bcb46 869 tmp = (idx_value >> 25) & 0x3;
068a117c 870 track->textures[i].tex_coord_type = tmp;
513bcb46 871 switch ((idx_value & 0x1F)) {
551ebd83
DA		 872 case R300_TX_FORMAT_X8:
873 case R300_TX_FORMAT_Y4X4:
874 case R300_TX_FORMAT_Z3Y3X2:
068a117c
JG		 875 track->textures[i].cpp = 1;
876 break;
551ebd83
DA		 877 case R300_TX_FORMAT_X16:
878 case R300_TX_FORMAT_Y8X8:
879 case R300_TX_FORMAT_Z5Y6X5:
880 case R300_TX_FORMAT_Z6Y5X5:
881 case R300_TX_FORMAT_W4Z4Y4X4:
882 case R300_TX_FORMAT_W1Z5Y5X5:
551ebd83
DA		 883 case R300_TX_FORMAT_D3DMFT_CxV8U8:
884 case R300_TX_FORMAT_B8G8_B8G8:
885 case R300_TX_FORMAT_G8R8_G8B8:
068a117c
JG		 886 track->textures[i].cpp = 2;
887 break;
551ebd83
DA		 888 case R300_TX_FORMAT_Y16X16:
889 case R300_TX_FORMAT_Z11Y11X10:
890 case R300_TX_FORMAT_Z10Y11X11:
891 case R300_TX_FORMAT_W8Z8Y8X8:
892 case R300_TX_FORMAT_W2Z10Y10X10:
893 case 0x17:
894 case R300_TX_FORMAT_FL_I32:
895 case 0x1e:
068a117c
JG		 896 track->textures[i].cpp = 4;
897 break;
551ebd83
DA		 898 case R300_TX_FORMAT_W16Z16Y16X16:
899 case R300_TX_FORMAT_FL_R16G16B16A16:
900 case R300_TX_FORMAT_FL_I32A32:
068a117c
JG		 901 track->textures[i].cpp = 8;
902 break;
551ebd83 903 case R300_TX_FORMAT_FL_R32G32B32A32:
068a117c
JG		 904 track->textures[i].cpp = 16;
905 break;
d785d78b
DA		 906 case R300_TX_FORMAT_DXT1:
907 track->textures[i].cpp = 1;
908 track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
909 break;
512889f4
MO		 910 case R300_TX_FORMAT_ATI2N:
911 if (p->rdev->family < CHIP_R420) {
912 DRM_ERROR("Invalid texture format %u\n",
913 (idx_value & 0x1F));
914 return -EINVAL;
915 }
916 /* The same rules apply as for DXT3/5. */
917 /* Pass through. */
d785d78b
DA		 918 case R300_TX_FORMAT_DXT3:
919 case R300_TX_FORMAT_DXT5:
920 track->textures[i].cpp = 1;
921 track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
922 break;
068a117c
JG		 923 default:
924 DRM_ERROR("Invalid texture format %u\n",
513bcb46 925 (idx_value & 0x1F));
068a117c
JG		 926 return -EINVAL;
927 break;
928 }
929 break;
930 case 0x4400:
931 case 0x4404:
932 case 0x4408:
933 case 0x440C:
934 case 0x4410:
935 case 0x4414:
936 case 0x4418:
937 case 0x441C:
938 case 0x4420:
939 case 0x4424:
940 case 0x4428:
941 case 0x442C:
942 case 0x4430:
943 case 0x4434:
944 case 0x4438:
945 case 0x443C:
946 /* TX_FILTER0_[0-15] */
947 i = (reg - 0x4400) >> 2;
513bcb46 948 tmp = idx_value & 0x7;
068a117c
JG		 949 if (tmp == 2 || tmp == 4 || tmp == 6) {
950 track->textures[i].roundup_w = false;
951 }
513bcb46 952 tmp = (idx_value >> 3) & 0x7;
068a117c
JG		 953 if (tmp == 2 || tmp == 4 || tmp == 6) {
954 track->textures[i].roundup_h = false;
955 }
956 break;
957 case 0x4500:
958 case 0x4504:
959 case 0x4508:
960 case 0x450C:
961 case 0x4510:
962 case 0x4514:
963 case 0x4518:
964 case 0x451C:
965 case 0x4520:
966 case 0x4524:
967 case 0x4528:
968 case 0x452C:
969 case 0x4530:
970 case 0x4534:
971 case 0x4538:
972 case 0x453C:
973 /* TX_FORMAT2_[0-15] */
974 i = (reg - 0x4500) >> 2;
513bcb46 975 tmp = idx_value & 0x3FFF;
068a117c
JG		 976 track->textures[i].pitch = tmp + 1;
977 if (p->rdev->family >= CHIP_RV515) {
513bcb46 978 tmp = ((idx_value >> 15) & 1) << 11;
068a117c 979 track->textures[i].width_11 = tmp;
513bcb46 980 tmp = ((idx_value >> 16) & 1) << 11;
068a117c 981 track->textures[i].height_11 = tmp;
512889f4
MO		 982
983 /* ATI1N */
984 if (idx_value & (1 << 14)) {
985 /* The same rules apply as for DXT1. */
986 track->textures[i].compress_format =
987 R100_TRACK_COMP_DXT1;
988 }
989 } else if (idx_value & (1 << 14)) {
990 DRM_ERROR("Forbidden bit TXFORMAT_MSB\n");
991 return -EINVAL;
068a117c
JG		 992 }
993 break;
994 case 0x4480:
995 case 0x4484:
996 case 0x4488:
997 case 0x448C:
998 case 0x4490:
999 case 0x4494:
1000 case 0x4498:
1001 case 0x449C:
1002 case 0x44A0:
1003 case 0x44A4:
1004 case 0x44A8:
1005 case 0x44AC:
1006 case 0x44B0:
1007 case 0x44B4:
1008 case 0x44B8:
1009 case 0x44BC:
1010 /* TX_FORMAT0_[0-15] */
1011 i = (reg - 0x4480) >> 2;
513bcb46 1012 tmp = idx_value & 0x7FF;
068a117c 1013 track->textures[i].width = tmp + 1;
513bcb46 1014 tmp = (idx_value >> 11) & 0x7FF;
068a117c 1015 track->textures[i].height = tmp + 1;
513bcb46 1016 tmp = (idx_value >> 26) & 0xF;
068a117c 1017 track->textures[i].num_levels = tmp;
513bcb46 1018 tmp = idx_value & (1 << 31);
068a117c 1019 track->textures[i].use_pitch = !!tmp;
513bcb46 1020 tmp = (idx_value >> 22) & 0xF;
068a117c
JG		 1021 track->textures[i].txdepth = tmp;
1022 break;
3f8befec
DA		 1023 case R300_ZB_ZPASS_ADDR:
1024 r = r100_cs_packet_next_reloc(p, &reloc);
1025 if (r) {
1026 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1027 idx, reg);
1028 r100_cs_dump_packet(p, pkt);
1029 return r;
1030 }
513bcb46 1031 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
3f8befec 1032 break;
46c64d4b
MO		 1033 case 0x4e0c:
1034 /* RB3D_COLOR_CHANNEL_MASK */
1035 track->color_channel_mask = idx_value;
1036 break;
1037 case 0x4d1c:
1038 /* ZB_BW_CNTL */
1039 track->fastfill = !!(idx_value & (1 << 2));
1040 break;
1041 case 0x4e04:
1042 /* RB3D_BLENDCNTL */
1043 track->blend_read_enable = !!(idx_value & (1 << 2));
1044 break;
3f8befec
DA		 1045 case 0x4be8:
1046 /* valid register only on RV530 */
1047 if (p->rdev->family == CHIP_RV530)
1048 break;
1049 /* fallthrough do not move */
771fe6b9 1050 default:
068a117c
JG		 1051 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1052 reg, idx);
771fe6b9
JG		 1053 return -EINVAL;
1054 }
1055 return 0;
1056}
1057
1058static int r300_packet3_check(struct radeon_cs_parser *p,
1059 struct radeon_cs_packet *pkt)
1060{
771fe6b9 1061 struct radeon_cs_reloc *reloc;
551ebd83 1062 struct r100_cs_track *track;
771fe6b9
JG		 1063 volatile uint32_t *ib;
1064 unsigned idx;
771fe6b9
JG		 1065 int r;
1066
1067 ib = p->ib->ptr;
771fe6b9 1068 idx = pkt->idx + 1;
551ebd83 1069 track = (struct r100_cs_track *)p->track;
068a117c 1070 switch(pkt->opcode) {
771fe6b9 1071 case PACKET3_3D_LOAD_VBPNTR:
513bcb46
DA		 1072 r = r100_packet3_load_vbpntr(p, pkt, idx);
1073 if (r)
1074 return r;
771fe6b9
JG		 1075 break;
1076 case PACKET3_INDX_BUFFER:
1077 r = r100_cs_packet_next_reloc(p, &reloc);
1078 if (r) {
1079 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1080 r100_cs_dump_packet(p, pkt);
1081 return r;
1082 }
513bcb46 1083 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
068a117c
JG		 1084 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1085 if (r) {
1086 return r;
1087 }
771fe6b9
JG		 1088 break;
1089 /* Draw packet */
771fe6b9 1090 case PACKET3_3D_DRAW_IMMD:
068a117c
JG		 1091 /* Number of dwords is vtx_size * (num_vertices - 1)
1092 * PRIM_WALK must be equal to 3 vertex data in embedded
1093 * in cmd stream */
513bcb46 1094 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
068a117c
JG		 1095 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1096 return -EINVAL;
1097 }
513bcb46 1098 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
068a117c 1099 track->immd_dwords = pkt->count - 1;
551ebd83 1100 r = r100_cs_track_check(p->rdev, track);
068a117c
JG		 1101 if (r) {
1102 return r;
1103 }
1104 break;
771fe6b9 1105 case PACKET3_3D_DRAW_IMMD_2:
068a117c
JG		 1106 /* Number of dwords is vtx_size * (num_vertices - 1)
1107 * PRIM_WALK must be equal to 3 vertex data in embedded
1108 * in cmd stream */
513bcb46 1109 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
068a117c
JG		 1110 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1111 return -EINVAL;
1112 }
513bcb46 1113 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
068a117c 1114 track->immd_dwords = pkt->count;
551ebd83 1115 r = r100_cs_track_check(p->rdev, track);
068a117c
JG		 1116 if (r) {
1117 return r;
1118 }
1119 break;
1120 case PACKET3_3D_DRAW_VBUF:
513bcb46 1121 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
551ebd83 1122 r = r100_cs_track_check(p->rdev, track);
068a117c
JG		 1123 if (r) {
1124 return r;
1125 }
1126 break;
1127 case PACKET3_3D_DRAW_VBUF_2:
513bcb46 1128 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
551ebd83 1129 r = r100_cs_track_check(p->rdev, track);
068a117c
JG		 1130 if (r) {
1131 return r;
1132 }
1133 break;
1134 case PACKET3_3D_DRAW_INDX:
513bcb46 1135 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
551ebd83 1136 r = r100_cs_track_check(p->rdev, track);
068a117c
JG		 1137 if (r) {
1138 return r;
1139 }
1140 break;
771fe6b9 1141 case PACKET3_3D_DRAW_INDX_2:
513bcb46 1142 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
551ebd83 1143 r = r100_cs_track_check(p->rdev, track);
771fe6b9
JG		 1144 if (r) {
1145 return r;
1146 }
1147 break;
1148 case PACKET3_NOP:
1149 break;
1150 default:
1151 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1152 return -EINVAL;
1153 }
1154 return 0;
1155}
1156
1157int r300_cs_parse(struct radeon_cs_parser *p)
1158{
1159 struct radeon_cs_packet pkt;
9f022ddf 1160 struct r100_cs_track *track;
771fe6b9
JG		 1161 int r;
1162
9f022ddf
JG		 1163 track = kzalloc(sizeof(*track), GFP_KERNEL);
1164 r100_cs_track_clear(p->rdev, track);
1165 p->track = track;
771fe6b9
JG		 1166 do {
1167 r = r100_cs_packet_parse(p, &pkt, p->idx);
1168 if (r) {
1169 return r;
1170 }
1171 p->idx += pkt.count + 2;
1172 switch (pkt.type) {
1173 case PACKET_TYPE0:
1174 r = r100_cs_parse_packet0(p, &pkt,
068a117c
JG		 1175 p->rdev->config.r300.reg_safe_bm,
1176 p->rdev->config.r300.reg_safe_bm_size,
771fe6b9
JG		 1177 &r300_packet0_check);
1178 break;
1179 case PACKET_TYPE2:
1180 break;
1181 case PACKET_TYPE3:
1182 r = r300_packet3_check(p, &pkt);
1183 break;
1184 default:
1185 DRM_ERROR("Unknown packet type %d !\n", pkt.type);
1186 return -EINVAL;
1187 }
1188 if (r) {
1189 return r;
1190 }
1191 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
1192 return 0;
1193}
068a117c 1194
9f022ddf 1195void r300_set_reg_safe(struct radeon_device *rdev)
068a117c
JG		 1196{
1197 rdev->config.r300.reg_safe_bm = r300_reg_safe_bm;
1198 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r300_reg_safe_bm);
9f022ddf
JG		 1199}
1200
9f022ddf
JG		 1201void r300_mc_program(struct radeon_device *rdev)
1202{
1203 struct r100_mc_save save;
1204 int r;
1205
1206 r = r100_debugfs_mc_info_init(rdev);
1207 if (r) {
1208 dev_err(rdev->dev, "Failed to create r100_mc debugfs file.\n");
1209 }
1210
1211 /* Stops all mc clients */
1212 r100_mc_stop(rdev, &save);
9f022ddf
JG		 1213 if (rdev->flags & RADEON_IS_AGP) {
1214 WREG32(R_00014C_MC_AGP_LOCATION,
1215 S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
1216 S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
1217 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
1218 WREG32(R_00015C_AGP_BASE_2,
1219 upper_32_bits(rdev->mc.agp_base) & 0xff);
1220 } else {
1221 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
1222 WREG32(R_000170_AGP_BASE, 0);
1223 WREG32(R_00015C_AGP_BASE_2, 0);
1224 }
1225 /* Wait for mc idle */
1226 if (r300_mc_wait_for_idle(rdev))
1227 DRM_INFO("Failed to wait MC idle before programming MC.\n");
1228 /* Program MC, should be a 32bits limited address space */
1229 WREG32(R_000148_MC_FB_LOCATION,
1230 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
1231 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
1232 r100_mc_resume(rdev, &save);
1233}
ca6ffc64
JG		 1234
1235void r300_clock_startup(struct radeon_device *rdev)
1236{
1237 u32 tmp;
1238
1239 if (radeon_dynclks != -1 && radeon_dynclks)
1240 radeon_legacy_set_clock_gating(rdev, 1);
1241 /* We need to force on some of the block */
1242 tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
1243 tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
1244 if ((rdev->family == CHIP_RV350) || (rdev->family == CHIP_RV380))
1245 tmp |= S_00000D_FORCE_VAP(1);
1246 WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
1247}
207bf9e9
JG		 1248
1249static int r300_startup(struct radeon_device *rdev)
1250{
1251 int r;
1252
92cde00c
AD		 1253 /* set common regs */
1254 r100_set_common_regs(rdev);
1255 /* program mc */
207bf9e9
JG		 1256 r300_mc_program(rdev);
1257 /* Resume clock */
1258 r300_clock_startup(rdev);
1259 /* Initialize GPU configuration (# pipes, ...) */
1260 r300_gpu_init(rdev);
1261 /* Initialize GART (initialize after TTM so we can allocate
1262 * memory through TTM but finalize after TTM) */
1263 if (rdev->flags & RADEON_IS_PCIE) {
1264 r = rv370_pcie_gart_enable(rdev);
1265 if (r)
1266 return r;
1267 }
17e15b0c
DA		 1268
1269 if (rdev->family == CHIP_R300 ||
1270 rdev->family == CHIP_R350 ||
1271 rdev->family == CHIP_RV350)
1272 r100_enable_bm(rdev);
1273
207bf9e9
JG		 1274 if (rdev->flags & RADEON_IS_PCI) {
1275 r = r100_pci_gart_enable(rdev);
1276 if (r)
1277 return r;
1278 }
1279 /* Enable IRQ */
207bf9e9 1280 r100_irq_set(rdev);
cafe6609 1281 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
207bf9e9
JG		 1282 /* 1M ring buffer */
1283 r = r100_cp_init(rdev, 1024 * 1024);
1284 if (r) {
1285 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
1286 return r;
1287 }
1288 r = r100_wb_init(rdev);
1289 if (r)
1290 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
1291 r = r100_ib_init(rdev);
1292 if (r) {
1293 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
1294 return r;
1295 }
1296 return 0;
1297}
1298
1299int r300_resume(struct radeon_device *rdev)
1300{
1301 /* Make sur GART are not working */
1302 if (rdev->flags & RADEON_IS_PCIE)
1303 rv370_pcie_gart_disable(rdev);
1304 if (rdev->flags & RADEON_IS_PCI)
1305 r100_pci_gart_disable(rdev);
1306 /* Resume clock before doing reset */
1307 r300_clock_startup(rdev);
1308 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
1309 if (radeon_gpu_reset(rdev)) {
1310 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
1311 RREG32(R_000E40_RBBM_STATUS),
1312 RREG32(R_0007C0_CP_STAT));
1313 }
1314 /* post */
1315 radeon_combios_asic_init(rdev->ddev);
1316 /* Resume clock after posting */
1317 r300_clock_startup(rdev);
550e2d92
DA		 1318 /* Initialize surface registers */
1319 radeon_surface_init(rdev);
207bf9e9
JG		 1320 return r300_startup(rdev);
1321}
1322
1323int r300_suspend(struct radeon_device *rdev)
1324{
1325 r100_cp_disable(rdev);
1326 r100_wb_disable(rdev);
1327 r100_irq_disable(rdev);
1328 if (rdev->flags & RADEON_IS_PCIE)
1329 rv370_pcie_gart_disable(rdev);
1330 if (rdev->flags & RADEON_IS_PCI)
1331 r100_pci_gart_disable(rdev);
1332 return 0;
1333}
1334
1335void r300_fini(struct radeon_device *rdev)
1336{
207bf9e9
JG		 1337 r100_cp_fini(rdev);
1338 r100_wb_fini(rdev);
1339 r100_ib_fini(rdev);
1340 radeon_gem_fini(rdev);
1341 if (rdev->flags & RADEON_IS_PCIE)
1342 rv370_pcie_gart_fini(rdev);
1343 if (rdev->flags & RADEON_IS_PCI)
1344 r100_pci_gart_fini(rdev);
d0269ed8 1345 radeon_agp_fini(rdev);
207bf9e9
JG		 1346 radeon_irq_kms_fini(rdev);
1347 radeon_fence_driver_fini(rdev);
4c788679 1348 radeon_bo_fini(rdev);
207bf9e9
JG		 1349 radeon_atombios_fini(rdev);
1350 kfree(rdev->bios);
1351 rdev->bios = NULL;
1352}
1353
1354int r300_init(struct radeon_device *rdev)
1355{
1356 int r;
1357
207bf9e9
JG		 1358 /* Disable VGA */
1359 r100_vga_render_disable(rdev);
1360 /* Initialize scratch registers */
1361 radeon_scratch_init(rdev);
1362 /* Initialize surface registers */
1363 radeon_surface_init(rdev);
1364 /* TODO: disable VGA need to use VGA request */
1365 /* BIOS*/
1366 if (!radeon_get_bios(rdev)) {
1367 if (ASIC_IS_AVIVO(rdev))
1368 return -EINVAL;
1369 }
1370 if (rdev->is_atom_bios) {
1371 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
1372 return -EINVAL;
1373 } else {
1374 r = radeon_combios_init(rdev);
1375 if (r)
1376 return r;
1377 }
1378 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
1379 if (radeon_gpu_reset(rdev)) {
1380 dev_warn(rdev->dev,
1381 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
1382 RREG32(R_000E40_RBBM_STATUS),
1383 RREG32(R_0007C0_CP_STAT));
1384 }
1385 /* check if cards are posted or not */
72542d77
DA		 1386 if (radeon_boot_test_post_card(rdev) == false)
1387 return -EINVAL;
207bf9e9
JG		 1388 /* Set asic errata */
1389 r300_errata(rdev);
1390 /* Initialize clocks */
1391 radeon_get_clock_info(rdev->ddev);
6234077d
RM		 1392 /* Initialize power management */
1393 radeon_pm_init(rdev);
d594e46a
JG		 1394 /* initialize AGP */
1395 if (rdev->flags & RADEON_IS_AGP) {
1396 r = radeon_agp_init(rdev);
1397 if (r) {
1398 radeon_agp_disable(rdev);
1399 }
1400 }
1401 /* initialize memory controller */
1402 r300_mc_init(rdev);
207bf9e9
JG		 1403 /* Fence driver */
1404 r = radeon_fence_driver_init(rdev);
1405 if (r)
1406 return r;
1407 r = radeon_irq_kms_init(rdev);
1408 if (r)
1409 return r;
1410 /* Memory manager */
4c788679 1411 r = radeon_bo_init(rdev);
207bf9e9
JG		 1412 if (r)
1413 return r;
1414 if (rdev->flags & RADEON_IS_PCIE) {
1415 r = rv370_pcie_gart_init(rdev);
1416 if (r)
1417 return r;
1418 }
1419 if (rdev->flags & RADEON_IS_PCI) {
1420 r = r100_pci_gart_init(rdev);
1421 if (r)
1422 return r;
1423 }
1424 r300_set_reg_safe(rdev);
1425 rdev->accel_working = true;
1426 r = r300_startup(rdev);
1427 if (r) {
1428 /* Somethings want wront with the accel init stop accel */
1429 dev_err(rdev->dev, "Disabling GPU acceleration\n");
207bf9e9
JG		 1430 r100_cp_fini(rdev);
1431 r100_wb_fini(rdev);
1432 r100_ib_fini(rdev);
655efd3d 1433 radeon_irq_kms_fini(rdev);
207bf9e9
JG		 1434 if (rdev->flags & RADEON_IS_PCIE)
1435 rv370_pcie_gart_fini(rdev);
1436 if (rdev->flags & RADEON_IS_PCI)
1437 r100_pci_gart_fini(rdev);
655efd3d 1438 radeon_agp_fini(rdev);
207bf9e9
JG		 1439 rdev->accel_working = false;
1440 }
1441 return 0;
1442}
Linux kernel - Deliverables
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