[deliverable/linux.git] / drivers / gpu / drm / radeon / r420.c

/*
 * Copyright 2008 Advanced Micro Devices, Inc.
 * Copyright 2008 Red Hat Inc.
 * Copyright 2009 Jerome Glisse.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Dave Airlie
 *          Alex Deucher
 *          Jerome Glisse
 */
#include <linux/seq_file.h>
#include "drmP.h"
#include "radeon_reg.h"
#include "radeon.h"
#include "atom.h"
#include "r420d.h"

int r420_mc_init(struct radeon_device *rdev)
{
	int r;

	/* Setup GPU memory space */
	rdev->mc.vram_location = 0xFFFFFFFFUL;
	rdev->mc.gtt_location = 0xFFFFFFFFUL;
	if (rdev->flags & RADEON_IS_AGP) {
		r = radeon_agp_init(rdev);
		if (r) {
			printk(KERN_WARNING "[drm] Disabling AGP\n");
			rdev->flags &= ~RADEON_IS_AGP;
			rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
		} else {
			rdev->mc.gtt_location = rdev->mc.agp_base;
		}
	}
	r = radeon_mc_setup(rdev);
	if (r) {
		return r;
	}
	return 0;
}

void r420_pipes_init(struct radeon_device *rdev)
{
	unsigned tmp;
	unsigned gb_pipe_select;
	unsigned num_pipes;

	/* GA_ENHANCE workaround TCL deadlock issue */
	WREG32(0x4274, (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3));
	/* get max number of pipes */
	gb_pipe_select = RREG32(0x402C);
	num_pipes = ((gb_pipe_select >> 12) & 3) + 1;
	rdev->num_gb_pipes = num_pipes;
	tmp = 0;
	switch (num_pipes) {
	default:
		/* force to 1 pipe */
		num_pipes = 1;
	case 1:
		tmp = (0 << 1);
		break;
	case 2:
		tmp = (3 << 1);
		break;
	case 3:
		tmp = (6 << 1);
		break;
	case 4:
		tmp = (7 << 1);
		break;
	}
	WREG32(0x42C8, (1 << num_pipes) - 1);
	/* Sub pixel 1/12 so we can have 4K rendering according to doc */
	tmp |= (1 << 4) | (1 << 0);
	WREG32(0x4018, tmp);
	if (r100_gui_wait_for_idle(rdev)) {
		printk(KERN_WARNING "Failed to wait GUI idle while "
		       "programming pipes. Bad things might happen.\n");
	}

	tmp = RREG32(0x170C);
	WREG32(0x170C, tmp | (1 << 31));

	WREG32(R300_RB2D_DSTCACHE_MODE,
	       RREG32(R300_RB2D_DSTCACHE_MODE) |
	       R300_DC_AUTOFLUSH_ENABLE |
	       R300_DC_DC_DISABLE_IGNORE_PE);

	if (r100_gui_wait_for_idle(rdev)) {
		printk(KERN_WARNING "Failed to wait GUI idle while "
		       "programming pipes. Bad things might happen.\n");
	}

	if (rdev->family == CHIP_RV530) {
		tmp = RREG32(RV530_GB_PIPE_SELECT2);
		if ((tmp & 3) == 3)
			rdev->num_z_pipes = 2;
		else
			rdev->num_z_pipes = 1;
	} else
		rdev->num_z_pipes = 1;

	DRM_INFO("radeon: %d quad pipes, %d z pipes initialized.\n",
		 rdev->num_gb_pipes, rdev->num_z_pipes);
}

u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg)
{
	u32 r;

	WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg));
	r = RREG32(R_0001FC_MC_IND_DATA);
	return r;
}

void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
{
	WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg) |
		S_0001F8_MC_IND_WR_EN(1));
	WREG32(R_0001FC_MC_IND_DATA, v);
}

static void r420_debugfs(struct radeon_device *rdev)
{
	if (r100_debugfs_rbbm_init(rdev)) {
		DRM_ERROR("Failed to register debugfs file for RBBM !\n");
	}
	if (r420_debugfs_pipes_info_init(rdev)) {
		DRM_ERROR("Failed to register debugfs file for pipes !\n");
	}
}

static void r420_clock_resume(struct radeon_device *rdev)
{
	u32 sclk_cntl;
	sclk_cntl = RREG32_PLL(R_00000D_SCLK_CNTL);
	sclk_cntl |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
	if (rdev->family == CHIP_R420)
		sclk_cntl |= S_00000D_FORCE_PX(1) | S_00000D_FORCE_TX(1);
	WREG32_PLL(R_00000D_SCLK_CNTL, sclk_cntl);
}

static int r420_startup(struct radeon_device *rdev)
{
	int r;

	r300_mc_program(rdev);
	/* Initialize GART (initialize after TTM so we can allocate
	 * memory through TTM but finalize after TTM) */
	if (rdev->flags & RADEON_IS_PCIE) {
		r = rv370_pcie_gart_enable(rdev);
		if (r)
			return r;
	}
	if (rdev->flags & RADEON_IS_PCI) {
		r = r100_pci_gart_enable(rdev);
		if (r)
			return r;
	}
	r420_pipes_init(rdev);
	/* Enable IRQ */
	rdev->irq.sw_int = true;
	r100_irq_set(rdev);
	/* 1M ring buffer */
	r = r100_cp_init(rdev, 1024 * 1024);
	if (r) {
		dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
		return r;
	}
	r = r100_wb_init(rdev);
	if (r) {
		dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
	}
	r = r100_ib_init(rdev);
	if (r) {
		dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
		return r;
	}
	return 0;
}

int r420_resume(struct radeon_device *rdev)
{
	/* Make sur GART are not working */
	if (rdev->flags & RADEON_IS_PCIE)
		rv370_pcie_gart_disable(rdev);
	if (rdev->flags & RADEON_IS_PCI)
		r100_pci_gart_disable(rdev);
	/* Resume clock before doing reset */
	r420_clock_resume(rdev);
	/* Reset gpu before posting otherwise ATOM will enter infinite loop */
	if (radeon_gpu_reset(rdev)) {
		dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
			RREG32(R_000E40_RBBM_STATUS),
			RREG32(R_0007C0_CP_STAT));
	}
	/* check if cards are posted or not */
	if (rdev->is_atom_bios) {
		atom_asic_init(rdev->mode_info.atom_context);
	} else {
		radeon_combios_asic_init(rdev->ddev);
	}
	/* Resume clock after posting */
	r420_clock_resume(rdev);

	return r420_startup(rdev);
}

int r420_suspend(struct radeon_device *rdev)
{
	r100_cp_disable(rdev);
	r100_wb_disable(rdev);
	r100_irq_disable(rdev);
	if (rdev->flags & RADEON_IS_PCIE)
		rv370_pcie_gart_disable(rdev);
	if (rdev->flags & RADEON_IS_PCI)
		r100_pci_gart_disable(rdev);
	return 0;
}

void r420_fini(struct radeon_device *rdev)
{
	r100_cp_fini(rdev);
	r100_wb_fini(rdev);
	r100_ib_fini(rdev);
	radeon_gem_fini(rdev);
	if (rdev->flags & RADEON_IS_PCIE)
		rv370_pcie_gart_fini(rdev);
	if (rdev->flags & RADEON_IS_PCI)
		r100_pci_gart_fini(rdev);
	radeon_agp_fini(rdev);
	radeon_irq_kms_fini(rdev);
	radeon_fence_driver_fini(rdev);
	radeon_object_fini(rdev);
	if (rdev->is_atom_bios) {
		radeon_atombios_fini(rdev);
	} else {
		radeon_combios_fini(rdev);
	}
	kfree(rdev->bios);
	rdev->bios = NULL;
}

int r420_init(struct radeon_device *rdev)
{
	int r;

	rdev->new_init_path = true;
	/* Initialize scratch registers */
	radeon_scratch_init(rdev);
	/* Initialize surface registers */
	radeon_surface_init(rdev);
	/* TODO: disable VGA need to use VGA request */
	/* BIOS*/
	if (!radeon_get_bios(rdev)) {
		if (ASIC_IS_AVIVO(rdev))
			return -EINVAL;
	}
	if (rdev->is_atom_bios) {
		r = radeon_atombios_init(rdev);
		if (r) {
			return r;
		}
	} else {
		r = radeon_combios_init(rdev);
		if (r) {
			return r;
		}
	}
	/* Reset gpu before posting otherwise ATOM will enter infinite loop */
	if (radeon_gpu_reset(rdev)) {
		dev_warn(rdev->dev,
			"GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
			RREG32(R_000E40_RBBM_STATUS),
			RREG32(R_0007C0_CP_STAT));
	}
	/* check if cards are posted or not */
	if (!radeon_card_posted(rdev) && rdev->bios) {
		DRM_INFO("GPU not posted. posting now...\n");
		if (rdev->is_atom_bios) {
			atom_asic_init(rdev->mode_info.atom_context);
		} else {
			radeon_combios_asic_init(rdev->ddev);
		}
	}
	/* Initialize clocks */
	radeon_get_clock_info(rdev->ddev);
	/* Get vram informations */
	r300_vram_info(rdev);
	/* Initialize memory controller (also test AGP) */
	r = r420_mc_init(rdev);
	if (r) {
		return r;
	}
	r420_debugfs(rdev);
	/* Fence driver */
	r = radeon_fence_driver_init(rdev);
	if (r) {
		return r;
	}
	r = radeon_irq_kms_init(rdev);
	if (r) {
		return r;
	}
	/* Memory manager */
	r = radeon_object_init(rdev);
	if (r) {
		return r;
	}
	if (rdev->flags & RADEON_IS_PCIE) {
		r = rv370_pcie_gart_init(rdev);
		if (r)
			return r;
	}
	if (rdev->flags & RADEON_IS_PCI) {
		r = r100_pci_gart_init(rdev);
		if (r)
			return r;
	}
	r300_set_reg_safe(rdev);
	rdev->accel_working = true;
	r = r420_startup(rdev);
	if (r) {
		/* Somethings want wront with the accel init stop accel */
		dev_err(rdev->dev, "Disabling GPU acceleration\n");
		r420_suspend(rdev);
		r100_cp_fini(rdev);
		r100_wb_fini(rdev);
		r100_ib_fini(rdev);
		if (rdev->flags & RADEON_IS_PCIE)
			rv370_pcie_gart_fini(rdev);
		if (rdev->flags & RADEON_IS_PCI)
			r100_pci_gart_fini(rdev);
		radeon_agp_fini(rdev);
		radeon_irq_kms_fini(rdev);
		rdev->accel_working = false;
	}
	return 0;
}

/*
 * Debugfs info
 */
#if defined(CONFIG_DEBUG_FS)
static int r420_debugfs_pipes_info(struct seq_file *m, void *data)
{
	struct drm_info_node *node = (struct drm_info_node *) m->private;
	struct drm_device *dev = node->minor->dev;
	struct radeon_device *rdev = dev->dev_private;
	uint32_t tmp;

	tmp = RREG32(R400_GB_PIPE_SELECT);
	seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp);
	tmp = RREG32(R300_GB_TILE_CONFIG);
	seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp);
	tmp = RREG32(R300_DST_PIPE_CONFIG);
	seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp);
	return 0;
}

static struct drm_info_list r420_pipes_info_list[] = {
	{"r420_pipes_info", r420_debugfs_pipes_info, 0, NULL},
};
#endif

int r420_debugfs_pipes_info_init(struct radeon_device *rdev)
{
#if defined(CONFIG_DEBUG_FS)
	return radeon_debugfs_add_files(rdev, r420_pipes_info_list, 1);
#else
	return 0;
#endif
}
Commit	Line	Data
771fe6b9 JG	1	/*
	2	* Copyright 2008 Advanced Micro Devices, Inc.
	3	* Copyright 2008 Red Hat Inc.
	4	* Copyright 2009 Jerome Glisse.
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a
	7	* copy of this software and associated documentation files (the "Software"),
	8	* to deal in the Software without restriction, including without limitation
	9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	10	* and/or sell copies of the Software, and to permit persons to whom the
	11	* Software is furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	22	* OTHER DEALINGS IN THE SOFTWARE.
	23	*
	24	* Authors: Dave Airlie
	25	* Alex Deucher
	26	* Jerome Glisse
	27	*/
	28	#include <linux/seq_file.h>
	29	#include "drmP.h"
	30	#include "radeon_reg.h"
	31	#include "radeon.h"
9f022ddf	32	#include "atom.h"
905b6822	33	#include "r420d.h"
771fe6b9	34
771fe6b9 JG	35	int r420_mc_init(struct radeon_device *rdev)
	36	{
	37	int r;
	38
771fe6b9 JG	39	/* Setup GPU memory space */
	40	rdev->mc.vram_location = 0xFFFFFFFFUL;
	41	rdev->mc.gtt_location = 0xFFFFFFFFUL;
	42	if (rdev->flags & RADEON_IS_AGP) {
	43	r = radeon_agp_init(rdev);
	44	if (r) {
	45	printk(KERN_WARNING "[drm] Disabling AGP\n");
	46	rdev->flags &= ~RADEON_IS_AGP;
	47	rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
	48	} else {
	49	rdev->mc.gtt_location = rdev->mc.agp_base;
	50	}
	51	}
	52	r = radeon_mc_setup(rdev);
	53	if (r) {
	54	return r;
	55	}
771fe6b9 JG	56	return 0;
	57	}
	58
771fe6b9 JG	59	void r420_pipes_init(struct radeon_device *rdev)
	60	{
	61	unsigned tmp;
	62	unsigned gb_pipe_select;
	63	unsigned num_pipes;
	64
	65	/* GA_ENHANCE workaround TCL deadlock issue */
	66	WREG32(0x4274, (1 << 0) \| (1 << 1) \| (1 << 2) \| (1 << 3));
	67	/* get max number of pipes */
	68	gb_pipe_select = RREG32(0x402C);
	69	num_pipes = ((gb_pipe_select >> 12) & 3) + 1;
	70	rdev->num_gb_pipes = num_pipes;
	71	tmp = 0;
	72	switch (num_pipes) {
	73	default:
	74	/* force to 1 pipe */
	75	num_pipes = 1;
	76	case 1:
	77	tmp = (0 << 1);
	78	break;
	79	case 2:
	80	tmp = (3 << 1);
	81	break;
	82	case 3:
	83	tmp = (6 << 1);
	84	break;
	85	case 4:
	86	tmp = (7 << 1);
	87	break;
	88	}
	89	WREG32(0x42C8, (1 << num_pipes) - 1);
	90	/* Sub pixel 1/12 so we can have 4K rendering according to doc */
	91	tmp \|= (1 << 4) \| (1 << 0);
	92	WREG32(0x4018, tmp);
	93	if (r100_gui_wait_for_idle(rdev)) {
	94	printk(KERN_WARNING "Failed to wait GUI idle while "
	95	"programming pipes. Bad things might happen.\n");
	96	}
	97
	98	tmp = RREG32(0x170C);
	99	WREG32(0x170C, tmp \| (1 << 31));
	100
	101	WREG32(R300_RB2D_DSTCACHE_MODE,
	102	RREG32(R300_RB2D_DSTCACHE_MODE) \|
	103	R300_DC_AUTOFLUSH_ENABLE \|
	104	R300_DC_DC_DISABLE_IGNORE_PE);
	105
	106	if (r100_gui_wait_for_idle(rdev)) {
	107	printk(KERN_WARNING "Failed to wait GUI idle while "
	108	"programming pipes. Bad things might happen.\n");
	109	}
f779b3e5 AD	110
	111	if (rdev->family == CHIP_RV530) {
	112	tmp = RREG32(RV530_GB_PIPE_SELECT2);
	113	if ((tmp & 3) == 3)
	114	rdev->num_z_pipes = 2;
	115	else
	116	rdev->num_z_pipes = 1;
	117	} else
	118	rdev->num_z_pipes = 1;
	119
	120	DRM_INFO("radeon: %d quad pipes, %d z pipes initialized.\n",
	121	rdev->num_gb_pipes, rdev->num_z_pipes);
771fe6b9 JG	122	}
771fe6b9 JG	123
9f022ddf	124	u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg)
771fe6b9	125	{
9f022ddf JG	126	u32 r;
	127
	128	WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg));
	129	r = RREG32(R_0001FC_MC_IND_DATA);
	130	return r;
	131	}
	132
	133	void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
	134	{
	135	WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg) \|
	136	S_0001F8_MC_IND_WR_EN(1));
	137	WREG32(R_0001FC_MC_IND_DATA, v);
	138	}
	139
	140	static void r420_debugfs(struct radeon_device *rdev)
	141	{
	142	if (r100_debugfs_rbbm_init(rdev)) {
	143	DRM_ERROR("Failed to register debugfs file for RBBM !\n");
	144	}
	145	if (r420_debugfs_pipes_info_init(rdev)) {
	146	DRM_ERROR("Failed to register debugfs file for pipes !\n");
	147	}
	148	}
	149
	150	static void r420_clock_resume(struct radeon_device *rdev)
	151	{
	152	u32 sclk_cntl;
	153	sclk_cntl = RREG32_PLL(R_00000D_SCLK_CNTL);
	154	sclk_cntl \|= S_00000D_FORCE_CP(1) \| S_00000D_FORCE_VIP(1);
	155	if (rdev->family == CHIP_R420)
	156	sclk_cntl \|= S_00000D_FORCE_PX(1) \| S_00000D_FORCE_TX(1);
	157	WREG32_PLL(R_00000D_SCLK_CNTL, sclk_cntl);
	158	}
	159
fc30b8ef	160	static int r420_startup(struct radeon_device *rdev)
9f022ddf JG	161	{
	162	int r;
	163
9f022ddf JG	164	r300_mc_program(rdev);
	165	/* Initialize GART (initialize after TTM so we can allocate
	166	* memory through TTM but finalize after TTM) */
4aac0473 JG	167	if (rdev->flags & RADEON_IS_PCIE) {
	168	r = rv370_pcie_gart_enable(rdev);
	169	if (r)
	170	return r;
	171	}
	172	if (rdev->flags & RADEON_IS_PCI) {
	173	r = r100_pci_gart_enable(rdev);
	174	if (r)
	175	return r;
9f022ddf	176	}
771fe6b9	177	r420_pipes_init(rdev);
9f022ddf JG	178	/* Enable IRQ */
	179	rdev->irq.sw_int = true;
	180	r100_irq_set(rdev);
	181	/* 1M ring buffer */
	182	r = r100_cp_init(rdev, 1024 * 1024);
	183	if (r) {
	184	dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
	185	return r;
	186	}
	187	r = r100_wb_init(rdev);
	188	if (r) {
	189	dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
771fe6b9	190	}
9f022ddf JG	191	r = r100_ib_init(rdev);
	192	if (r) {
	193	dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
	194	return r;
	195	}
	196	return 0;
771fe6b9 JG	197	}
771fe6b9 JG	198
fc30b8ef DA	199	int r420_resume(struct radeon_device *rdev)
	200	{
	201	/* Make sur GART are not working */
	202	if (rdev->flags & RADEON_IS_PCIE)
	203	rv370_pcie_gart_disable(rdev);
	204	if (rdev->flags & RADEON_IS_PCI)
	205	r100_pci_gart_disable(rdev);
	206	/* Resume clock before doing reset */
	207	r420_clock_resume(rdev);
	208	/* Reset gpu before posting otherwise ATOM will enter infinite loop */
	209	if (radeon_gpu_reset(rdev)) {
	210	dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
	211	RREG32(R_000E40_RBBM_STATUS),
	212	RREG32(R_0007C0_CP_STAT));
	213	}
	214	/* check if cards are posted or not */
	215	if (rdev->is_atom_bios) {
	216	atom_asic_init(rdev->mode_info.atom_context);
	217	} else {
	218	radeon_combios_asic_init(rdev->ddev);
	219	}
	220	/* Resume clock after posting */
	221	r420_clock_resume(rdev);
	222
	223	return r420_startup(rdev);
	224	}
	225
9f022ddf JG	226	int r420_suspend(struct radeon_device *rdev)
	227	{
	228	r100_cp_disable(rdev);
	229	r100_wb_disable(rdev);
	230	r100_irq_disable(rdev);
4aac0473 JG	231	if (rdev->flags & RADEON_IS_PCIE)
	232	rv370_pcie_gart_disable(rdev);
	233	if (rdev->flags & RADEON_IS_PCI)
	234	r100_pci_gart_disable(rdev);
9f022ddf JG	235	return 0;
9f022ddf JG	236	}
771fe6b9	237
9f022ddf	238	void r420_fini(struct radeon_device *rdev)
771fe6b9	239	{
9f022ddf JG	240	r100_cp_fini(rdev);
	241	r100_wb_fini(rdev);
	242	r100_ib_fini(rdev);
	243	radeon_gem_fini(rdev);
4aac0473 JG	244	if (rdev->flags & RADEON_IS_PCIE)
	245	rv370_pcie_gart_fini(rdev);
	246	if (rdev->flags & RADEON_IS_PCI)
	247	r100_pci_gart_fini(rdev);
9f022ddf JG	248	radeon_agp_fini(rdev);
	249	radeon_irq_kms_fini(rdev);
	250	radeon_fence_driver_fini(rdev);
	251	radeon_object_fini(rdev);
	252	if (rdev->is_atom_bios) {
	253	radeon_atombios_fini(rdev);
	254	} else {
	255	radeon_combios_fini(rdev);
	256	}
	257	kfree(rdev->bios);
	258	rdev->bios = NULL;
771fe6b9 JG	259	}
771fe6b9 JG	260
9f022ddf JG	261	int r420_init(struct radeon_device *rdev)
	262	{
	263	int r;
	264
	265	rdev->new_init_path = true;
	266	/* Initialize scratch registers */
	267	radeon_scratch_init(rdev);
	268	/* Initialize surface registers */
	269	radeon_surface_init(rdev);
	270	/* TODO: disable VGA need to use VGA request */
	271	/* BIOS*/
	272	if (!radeon_get_bios(rdev)) {
	273	if (ASIC_IS_AVIVO(rdev))
	274	return -EINVAL;
	275	}
	276	if (rdev->is_atom_bios) {
	277	r = radeon_atombios_init(rdev);
	278	if (r) {
	279	return r;
	280	}
	281	} else {
	282	r = radeon_combios_init(rdev);
	283	if (r) {
	284	return r;
	285	}
	286	}
	287	/* Reset gpu before posting otherwise ATOM will enter infinite loop */
	288	if (radeon_gpu_reset(rdev)) {
	289	dev_warn(rdev->dev,
	290	"GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
	291	RREG32(R_000E40_RBBM_STATUS),
	292	RREG32(R_0007C0_CP_STAT));
	293	}
	294	/* check if cards are posted or not */
	295	if (!radeon_card_posted(rdev) && rdev->bios) {
	296	DRM_INFO("GPU not posted. posting now...\n");
	297	if (rdev->is_atom_bios) {
	298	atom_asic_init(rdev->mode_info.atom_context);
	299	} else {
	300	radeon_combios_asic_init(rdev->ddev);
	301	}
	302	}
	303	/* Initialize clocks */
	304	radeon_get_clock_info(rdev->ddev);
	305	/* Get vram informations */
	306	r300_vram_info(rdev);
	307	/* Initialize memory controller (also test AGP) */
	308	r = r420_mc_init(rdev);
	309	if (r) {
	310	return r;
	311	}
	312	r420_debugfs(rdev);
	313	/* Fence driver */
	314	r = radeon_fence_driver_init(rdev);
	315	if (r) {
	316	return r;
	317	}
	318	r = radeon_irq_kms_init(rdev);
	319	if (r) {
	320	return r;
	321	}
	322	/* Memory manager */
	323	r = radeon_object_init(rdev);
	324	if (r) {
325	return r;
326	}
4aac0473 JG	327	if (rdev->flags & RADEON_IS_PCIE) {
	328	r = rv370_pcie_gart_init(rdev);
	329	if (r)
	330	return r;
	331	}
	332	if (rdev->flags & RADEON_IS_PCI) {
	333	r = r100_pci_gart_init(rdev);
	334	if (r)
	335	return r;
	336	}
9f022ddf	337	r300_set_reg_safe(rdev);
733289c2	338	rdev->accel_working = true;
fc30b8ef	339	r = r420_startup(rdev);
9f022ddf JG	340	if (r) {
	341	/* Somethings want wront with the accel init stop accel */
	342	dev_err(rdev->dev, "Disabling GPU acceleration\n");
	343	r420_suspend(rdev);
	344	r100_cp_fini(rdev);
	345	r100_wb_fini(rdev);
	346	r100_ib_fini(rdev);
4aac0473 JG	347	if (rdev->flags & RADEON_IS_PCIE)
	348	rv370_pcie_gart_fini(rdev);
	349	if (rdev->flags & RADEON_IS_PCI)
	350	r100_pci_gart_fini(rdev);
9f022ddf JG	351	radeon_agp_fini(rdev);
9f022ddf JG	352	radeon_irq_kms_fini(rdev);
733289c2	353	rdev->accel_working = false;
9f022ddf JG	354	}
	355	return 0;
	356	}
771fe6b9 JG	357
	358	/*
	359	* Debugfs info
	360	*/
	361	#if defined(CONFIG_DEBUG_FS)
	362	static int r420_debugfs_pipes_info(struct seq_file m, void data)
	363	{
	364	struct drm_info_node node = (struct drm_info_node ) m->private;
	365	struct drm_device *dev = node->minor->dev;
	366	struct radeon_device *rdev = dev->dev_private;
	367	uint32_t tmp;
	368
	369	tmp = RREG32(R400_GB_PIPE_SELECT);
	370	seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp);
	371	tmp = RREG32(R300_GB_TILE_CONFIG);
	372	seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp);
	373	tmp = RREG32(R300_DST_PIPE_CONFIG);
	374	seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp);
	375	return 0;
	376	}
	377
	378	static struct drm_info_list r420_pipes_info_list[] = {
	379	{"r420_pipes_info", r420_debugfs_pipes_info, 0, NULL},
	380	};
	381	#endif
	382
	383	int r420_debugfs_pipes_info_init(struct radeon_device *rdev)
	384	{
	385	#if defined(CONFIG_DEBUG_FS)
	386	return radeon_debugfs_add_files(rdev, r420_pipes_info_list, 1);
	387	#else
	388	return 0;
	389	#endif
	390	}