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771fe6b9 JG |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
28 | #include "drmP.h" | |
771fe6b9 | 29 | #include "radeon.h" |
f0ed1f65 JG |
30 | #include "atom.h" |
31 | #include "r520d.h" | |
771fe6b9 | 32 | |
f0ed1f65 | 33 | /* This files gather functions specifics to: r520,rv530,rv560,rv570,r580 */ |
771fe6b9 | 34 | |
f0ed1f65 | 35 | static int r520_mc_wait_for_idle(struct radeon_device *rdev) |
771fe6b9 JG |
36 | { |
37 | unsigned i; | |
38 | uint32_t tmp; | |
39 | ||
40 | for (i = 0; i < rdev->usec_timeout; i++) { | |
41 | /* read MC_STATUS */ | |
42 | tmp = RREG32_MC(R520_MC_STATUS); | |
43 | if (tmp & R520_MC_STATUS_IDLE) { | |
44 | return 0; | |
45 | } | |
46 | DRM_UDELAY(1); | |
47 | } | |
48 | return -1; | |
49 | } | |
50 | ||
f0ed1f65 | 51 | static void r520_gpu_init(struct radeon_device *rdev) |
771fe6b9 JG |
52 | { |
53 | unsigned pipe_select_current, gb_pipe_select, tmp; | |
54 | ||
55 | r100_hdp_reset(rdev); | |
d39c3b89 | 56 | rv515_vga_render_disable(rdev); |
771fe6b9 JG |
57 | /* |
58 | * DST_PIPE_CONFIG 0x170C | |
59 | * GB_TILE_CONFIG 0x4018 | |
60 | * GB_FIFO_SIZE 0x4024 | |
61 | * GB_PIPE_SELECT 0x402C | |
62 | * GB_PIPE_SELECT2 0x4124 | |
63 | * Z_PIPE_SHIFT 0 | |
64 | * Z_PIPE_MASK 0x000000003 | |
65 | * GB_FIFO_SIZE2 0x4128 | |
66 | * SC_SFIFO_SIZE_SHIFT 0 | |
67 | * SC_SFIFO_SIZE_MASK 0x000000003 | |
68 | * SC_MFIFO_SIZE_SHIFT 2 | |
69 | * SC_MFIFO_SIZE_MASK 0x00000000C | |
70 | * FG_SFIFO_SIZE_SHIFT 4 | |
71 | * FG_SFIFO_SIZE_MASK 0x000000030 | |
72 | * ZB_MFIFO_SIZE_SHIFT 6 | |
73 | * ZB_MFIFO_SIZE_MASK 0x0000000C0 | |
74 | * GA_ENHANCE 0x4274 | |
75 | * SU_REG_DEST 0x42C8 | |
76 | */ | |
77 | /* workaround for RV530 */ | |
78 | if (rdev->family == CHIP_RV530) { | |
771fe6b9 JG |
79 | WREG32(0x4128, 0xFF); |
80 | } | |
81 | r420_pipes_init(rdev); | |
82 | gb_pipe_select = RREG32(0x402C); | |
83 | tmp = RREG32(0x170C); | |
84 | pipe_select_current = (tmp >> 2) & 3; | |
85 | tmp = (1 << pipe_select_current) | | |
86 | (((gb_pipe_select >> 8) & 0xF) << 4); | |
87 | WREG32_PLL(0x000D, tmp); | |
88 | if (r520_mc_wait_for_idle(rdev)) { | |
89 | printk(KERN_WARNING "Failed to wait MC idle while " | |
90 | "programming pipes. Bad things might happen.\n"); | |
91 | } | |
92 | } | |
93 | ||
771fe6b9 JG |
94 | static void r520_vram_get_type(struct radeon_device *rdev) |
95 | { | |
96 | uint32_t tmp; | |
97 | ||
98 | rdev->mc.vram_width = 128; | |
99 | rdev->mc.vram_is_ddr = true; | |
100 | tmp = RREG32_MC(R520_MC_CNTL0); | |
101 | switch ((tmp & R520_MEM_NUM_CHANNELS_MASK) >> R520_MEM_NUM_CHANNELS_SHIFT) { | |
102 | case 0: | |
103 | rdev->mc.vram_width = 32; | |
104 | break; | |
105 | case 1: | |
106 | rdev->mc.vram_width = 64; | |
107 | break; | |
108 | case 2: | |
109 | rdev->mc.vram_width = 128; | |
110 | break; | |
111 | case 3: | |
112 | rdev->mc.vram_width = 256; | |
113 | break; | |
114 | default: | |
115 | rdev->mc.vram_width = 128; | |
116 | break; | |
117 | } | |
118 | if (tmp & R520_MC_CHANNEL_SIZE) | |
119 | rdev->mc.vram_width *= 2; | |
120 | } | |
121 | ||
122 | void r520_vram_info(struct radeon_device *rdev) | |
123 | { | |
c93bb85b JG |
124 | fixed20_12 a; |
125 | ||
771fe6b9 | 126 | r520_vram_get_type(rdev); |
771fe6b9 | 127 | |
2a0f8918 | 128 | r100_vram_init_sizes(rdev); |
c93bb85b JG |
129 | /* FIXME: we should enforce default clock in case GPU is not in |
130 | * default setup | |
131 | */ | |
132 | a.full = rfixed_const(100); | |
133 | rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk); | |
134 | rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a); | |
135 | } | |
136 | ||
f0ed1f65 JG |
137 | void r520_mc_program(struct radeon_device *rdev) |
138 | { | |
139 | struct rv515_mc_save save; | |
140 | ||
141 | /* Stops all mc clients */ | |
142 | rv515_mc_stop(rdev, &save); | |
143 | ||
144 | /* Wait for mc idle */ | |
145 | if (r520_mc_wait_for_idle(rdev)) | |
146 | dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); | |
147 | /* Write VRAM size in case we are limiting it */ | |
148 | WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size); | |
149 | /* Program MC, should be a 32bits limited address space */ | |
150 | WREG32_MC(R_000004_MC_FB_LOCATION, | |
151 | S_000004_MC_FB_START(rdev->mc.vram_start >> 16) | | |
152 | S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16)); | |
153 | WREG32(R_000134_HDP_FB_LOCATION, | |
154 | S_000134_HDP_FB_START(rdev->mc.vram_start >> 16)); | |
155 | if (rdev->flags & RADEON_IS_AGP) { | |
156 | WREG32_MC(R_000005_MC_AGP_LOCATION, | |
157 | S_000005_MC_AGP_START(rdev->mc.gtt_start >> 16) | | |
158 | S_000005_MC_AGP_TOP(rdev->mc.gtt_end >> 16)); | |
159 | WREG32_MC(R_000006_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); | |
160 | WREG32_MC(R_000007_AGP_BASE_2, | |
161 | S_000007_AGP_BASE_ADDR_2(upper_32_bits(rdev->mc.agp_base))); | |
162 | } else { | |
163 | WREG32_MC(R_000005_MC_AGP_LOCATION, 0xFFFFFFFF); | |
164 | WREG32_MC(R_000006_AGP_BASE, 0); | |
165 | WREG32_MC(R_000007_AGP_BASE_2, 0); | |
166 | } | |
167 | ||
168 | rv515_mc_resume(rdev, &save); | |
169 | } | |
170 | ||
171 | static int r520_startup(struct radeon_device *rdev) | |
172 | { | |
173 | int r; | |
174 | ||
175 | r520_mc_program(rdev); | |
176 | /* Resume clock */ | |
177 | rv515_clock_startup(rdev); | |
178 | /* Initialize GPU configuration (# pipes, ...) */ | |
179 | r520_gpu_init(rdev); | |
180 | /* Initialize GART (initialize after TTM so we can allocate | |
181 | * memory through TTM but finalize after TTM) */ | |
182 | if (rdev->flags & RADEON_IS_PCIE) { | |
183 | r = rv370_pcie_gart_enable(rdev); | |
184 | if (r) | |
185 | return r; | |
186 | } | |
187 | /* Enable IRQ */ | |
ac447df4 | 188 | rs600_irq_set(rdev); |
f0ed1f65 JG |
189 | /* 1M ring buffer */ |
190 | r = r100_cp_init(rdev, 1024 * 1024); | |
191 | if (r) { | |
192 | dev_err(rdev->dev, "failled initializing CP (%d).\n", r); | |
193 | return r; | |
194 | } | |
195 | r = r100_wb_init(rdev); | |
196 | if (r) | |
197 | dev_err(rdev->dev, "failled initializing WB (%d).\n", r); | |
198 | r = r100_ib_init(rdev); | |
199 | if (r) { | |
200 | dev_err(rdev->dev, "failled initializing IB (%d).\n", r); | |
201 | return r; | |
202 | } | |
203 | return 0; | |
204 | } | |
205 | ||
206 | int r520_resume(struct radeon_device *rdev) | |
c93bb85b | 207 | { |
f0ed1f65 JG |
208 | /* Make sur GART are not working */ |
209 | if (rdev->flags & RADEON_IS_PCIE) | |
210 | rv370_pcie_gart_disable(rdev); | |
211 | /* Resume clock before doing reset */ | |
212 | rv515_clock_startup(rdev); | |
213 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ | |
214 | if (radeon_gpu_reset(rdev)) { | |
215 | dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", | |
216 | RREG32(R_000E40_RBBM_STATUS), | |
217 | RREG32(R_0007C0_CP_STAT)); | |
218 | } | |
219 | /* post */ | |
220 | atom_asic_init(rdev->mode_info.atom_context); | |
221 | /* Resume clock after posting */ | |
222 | rv515_clock_startup(rdev); | |
223 | return r520_startup(rdev); | |
771fe6b9 | 224 | } |
d39c3b89 JG |
225 | |
226 | int r520_init(struct radeon_device *rdev) | |
227 | { | |
f0ed1f65 JG |
228 | int r; |
229 | ||
f0ed1f65 JG |
230 | /* Initialize scratch registers */ |
231 | radeon_scratch_init(rdev); | |
232 | /* Initialize surface registers */ | |
233 | radeon_surface_init(rdev); | |
234 | /* TODO: disable VGA need to use VGA request */ | |
235 | /* BIOS*/ | |
236 | if (!radeon_get_bios(rdev)) { | |
237 | if (ASIC_IS_AVIVO(rdev)) | |
238 | return -EINVAL; | |
239 | } | |
240 | if (rdev->is_atom_bios) { | |
241 | r = radeon_atombios_init(rdev); | |
242 | if (r) | |
243 | return r; | |
244 | } else { | |
245 | dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n"); | |
246 | return -EINVAL; | |
247 | } | |
248 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ | |
249 | if (radeon_gpu_reset(rdev)) { | |
250 | dev_warn(rdev->dev, | |
251 | "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", | |
252 | RREG32(R_000E40_RBBM_STATUS), | |
253 | RREG32(R_0007C0_CP_STAT)); | |
254 | } | |
255 | /* check if cards are posted or not */ | |
72542d77 DA |
256 | if (radeon_boot_test_post_card(rdev) == false) |
257 | return -EINVAL; | |
258 | ||
f0ed1f65 JG |
259 | if (!radeon_card_posted(rdev) && rdev->bios) { |
260 | DRM_INFO("GPU not posted. posting now...\n"); | |
261 | atom_asic_init(rdev->mode_info.atom_context); | |
262 | } | |
263 | /* Initialize clocks */ | |
264 | radeon_get_clock_info(rdev->ddev); | |
7433874e RM |
265 | /* Initialize power management */ |
266 | radeon_pm_init(rdev); | |
f0ed1f65 JG |
267 | /* Get vram informations */ |
268 | r520_vram_info(rdev); | |
269 | /* Initialize memory controller (also test AGP) */ | |
270 | r = r420_mc_init(rdev); | |
271 | if (r) | |
272 | return r; | |
273 | rv515_debugfs(rdev); | |
274 | /* Fence driver */ | |
275 | r = radeon_fence_driver_init(rdev); | |
276 | if (r) | |
277 | return r; | |
278 | r = radeon_irq_kms_init(rdev); | |
279 | if (r) | |
280 | return r; | |
281 | /* Memory manager */ | |
4c788679 | 282 | r = radeon_bo_init(rdev); |
f0ed1f65 JG |
283 | if (r) |
284 | return r; | |
285 | r = rv370_pcie_gart_init(rdev); | |
286 | if (r) | |
287 | return r; | |
d39c3b89 | 288 | rv515_set_safe_registers(rdev); |
f0ed1f65 JG |
289 | rdev->accel_working = true; |
290 | r = r520_startup(rdev); | |
291 | if (r) { | |
292 | /* Somethings want wront with the accel init stop accel */ | |
293 | dev_err(rdev->dev, "Disabling GPU acceleration\n"); | |
294 | rv515_suspend(rdev); | |
295 | r100_cp_fini(rdev); | |
296 | r100_wb_fini(rdev); | |
297 | r100_ib_fini(rdev); | |
298 | rv370_pcie_gart_fini(rdev); | |
299 | radeon_agp_fini(rdev); | |
300 | radeon_irq_kms_fini(rdev); | |
301 | rdev->accel_working = false; | |
302 | } | |
d39c3b89 JG |
303 | return 0; |
304 | } |