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771fe6b9 JG |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
5a0e3ad6 | 28 | #include <linux/slab.h> |
3ce0a23d JG |
29 | #include <linux/seq_file.h> |
30 | #include <linux/firmware.h> | |
31 | #include <linux/platform_device.h> | |
771fe6b9 | 32 | #include "drmP.h" |
3ce0a23d | 33 | #include "radeon_drm.h" |
771fe6b9 | 34 | #include "radeon.h" |
e6990375 | 35 | #include "radeon_asic.h" |
3ce0a23d | 36 | #include "radeon_mode.h" |
3ce0a23d | 37 | #include "r600d.h" |
3ce0a23d | 38 | #include "atom.h" |
d39c3b89 | 39 | #include "avivod.h" |
771fe6b9 | 40 | |
3ce0a23d JG |
41 | #define PFP_UCODE_SIZE 576 |
42 | #define PM4_UCODE_SIZE 1792 | |
d8f60cfc | 43 | #define RLC_UCODE_SIZE 768 |
3ce0a23d JG |
44 | #define R700_PFP_UCODE_SIZE 848 |
45 | #define R700_PM4_UCODE_SIZE 1360 | |
d8f60cfc | 46 | #define R700_RLC_UCODE_SIZE 1024 |
fe251e2f AD |
47 | #define EVERGREEN_PFP_UCODE_SIZE 1120 |
48 | #define EVERGREEN_PM4_UCODE_SIZE 1376 | |
45f9a39b | 49 | #define EVERGREEN_RLC_UCODE_SIZE 768 |
3ce0a23d JG |
50 | |
51 | /* Firmware Names */ | |
52 | MODULE_FIRMWARE("radeon/R600_pfp.bin"); | |
53 | MODULE_FIRMWARE("radeon/R600_me.bin"); | |
54 | MODULE_FIRMWARE("radeon/RV610_pfp.bin"); | |
55 | MODULE_FIRMWARE("radeon/RV610_me.bin"); | |
56 | MODULE_FIRMWARE("radeon/RV630_pfp.bin"); | |
57 | MODULE_FIRMWARE("radeon/RV630_me.bin"); | |
58 | MODULE_FIRMWARE("radeon/RV620_pfp.bin"); | |
59 | MODULE_FIRMWARE("radeon/RV620_me.bin"); | |
60 | MODULE_FIRMWARE("radeon/RV635_pfp.bin"); | |
61 | MODULE_FIRMWARE("radeon/RV635_me.bin"); | |
62 | MODULE_FIRMWARE("radeon/RV670_pfp.bin"); | |
63 | MODULE_FIRMWARE("radeon/RV670_me.bin"); | |
64 | MODULE_FIRMWARE("radeon/RS780_pfp.bin"); | |
65 | MODULE_FIRMWARE("radeon/RS780_me.bin"); | |
66 | MODULE_FIRMWARE("radeon/RV770_pfp.bin"); | |
67 | MODULE_FIRMWARE("radeon/RV770_me.bin"); | |
68 | MODULE_FIRMWARE("radeon/RV730_pfp.bin"); | |
69 | MODULE_FIRMWARE("radeon/RV730_me.bin"); | |
70 | MODULE_FIRMWARE("radeon/RV710_pfp.bin"); | |
71 | MODULE_FIRMWARE("radeon/RV710_me.bin"); | |
d8f60cfc AD |
72 | MODULE_FIRMWARE("radeon/R600_rlc.bin"); |
73 | MODULE_FIRMWARE("radeon/R700_rlc.bin"); | |
fe251e2f AD |
74 | MODULE_FIRMWARE("radeon/CEDAR_pfp.bin"); |
75 | MODULE_FIRMWARE("radeon/CEDAR_me.bin"); | |
45f9a39b | 76 | MODULE_FIRMWARE("radeon/CEDAR_rlc.bin"); |
fe251e2f AD |
77 | MODULE_FIRMWARE("radeon/REDWOOD_pfp.bin"); |
78 | MODULE_FIRMWARE("radeon/REDWOOD_me.bin"); | |
45f9a39b | 79 | MODULE_FIRMWARE("radeon/REDWOOD_rlc.bin"); |
fe251e2f AD |
80 | MODULE_FIRMWARE("radeon/JUNIPER_pfp.bin"); |
81 | MODULE_FIRMWARE("radeon/JUNIPER_me.bin"); | |
45f9a39b | 82 | MODULE_FIRMWARE("radeon/JUNIPER_rlc.bin"); |
a7433742 | 83 | MODULE_FIRMWARE("radeon/CYPRESS_pfp.bin"); |
fe251e2f | 84 | MODULE_FIRMWARE("radeon/CYPRESS_me.bin"); |
45f9a39b | 85 | MODULE_FIRMWARE("radeon/CYPRESS_rlc.bin"); |
3ce0a23d JG |
86 | |
87 | int r600_debugfs_mc_info_init(struct radeon_device *rdev); | |
771fe6b9 | 88 | |
1a029b76 | 89 | /* r600,rv610,rv630,rv620,rv635,rv670 */ |
771fe6b9 JG |
90 | int r600_mc_wait_for_idle(struct radeon_device *rdev); |
91 | void r600_gpu_init(struct radeon_device *rdev); | |
3ce0a23d | 92 | void r600_fini(struct radeon_device *rdev); |
45f9a39b | 93 | void r600_irq_disable(struct radeon_device *rdev); |
771fe6b9 | 94 | |
def9ba9c AD |
95 | bool r600_gui_idle(struct radeon_device *rdev) |
96 | { | |
97 | if (RREG32(GRBM_STATUS) & GUI_ACTIVE) | |
98 | return false; | |
99 | else | |
100 | return true; | |
101 | } | |
102 | ||
e0df1ac5 AD |
103 | /* hpd for digital panel detect/disconnect */ |
104 | bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) | |
105 | { | |
106 | bool connected = false; | |
107 | ||
108 | if (ASIC_IS_DCE3(rdev)) { | |
109 | switch (hpd) { | |
110 | case RADEON_HPD_1: | |
111 | if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE) | |
112 | connected = true; | |
113 | break; | |
114 | case RADEON_HPD_2: | |
115 | if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE) | |
116 | connected = true; | |
117 | break; | |
118 | case RADEON_HPD_3: | |
119 | if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE) | |
120 | connected = true; | |
121 | break; | |
122 | case RADEON_HPD_4: | |
123 | if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE) | |
124 | connected = true; | |
125 | break; | |
126 | /* DCE 3.2 */ | |
127 | case RADEON_HPD_5: | |
128 | if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE) | |
129 | connected = true; | |
130 | break; | |
131 | case RADEON_HPD_6: | |
132 | if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE) | |
133 | connected = true; | |
134 | break; | |
135 | default: | |
136 | break; | |
137 | } | |
138 | } else { | |
139 | switch (hpd) { | |
140 | case RADEON_HPD_1: | |
141 | if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE) | |
142 | connected = true; | |
143 | break; | |
144 | case RADEON_HPD_2: | |
145 | if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE) | |
146 | connected = true; | |
147 | break; | |
148 | case RADEON_HPD_3: | |
149 | if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE) | |
150 | connected = true; | |
151 | break; | |
152 | default: | |
153 | break; | |
154 | } | |
155 | } | |
156 | return connected; | |
157 | } | |
158 | ||
159 | void r600_hpd_set_polarity(struct radeon_device *rdev, | |
429770b3 | 160 | enum radeon_hpd_id hpd) |
e0df1ac5 AD |
161 | { |
162 | u32 tmp; | |
163 | bool connected = r600_hpd_sense(rdev, hpd); | |
164 | ||
165 | if (ASIC_IS_DCE3(rdev)) { | |
166 | switch (hpd) { | |
167 | case RADEON_HPD_1: | |
168 | tmp = RREG32(DC_HPD1_INT_CONTROL); | |
169 | if (connected) | |
170 | tmp &= ~DC_HPDx_INT_POLARITY; | |
171 | else | |
172 | tmp |= DC_HPDx_INT_POLARITY; | |
173 | WREG32(DC_HPD1_INT_CONTROL, tmp); | |
174 | break; | |
175 | case RADEON_HPD_2: | |
176 | tmp = RREG32(DC_HPD2_INT_CONTROL); | |
177 | if (connected) | |
178 | tmp &= ~DC_HPDx_INT_POLARITY; | |
179 | else | |
180 | tmp |= DC_HPDx_INT_POLARITY; | |
181 | WREG32(DC_HPD2_INT_CONTROL, tmp); | |
182 | break; | |
183 | case RADEON_HPD_3: | |
184 | tmp = RREG32(DC_HPD3_INT_CONTROL); | |
185 | if (connected) | |
186 | tmp &= ~DC_HPDx_INT_POLARITY; | |
187 | else | |
188 | tmp |= DC_HPDx_INT_POLARITY; | |
189 | WREG32(DC_HPD3_INT_CONTROL, tmp); | |
190 | break; | |
191 | case RADEON_HPD_4: | |
192 | tmp = RREG32(DC_HPD4_INT_CONTROL); | |
193 | if (connected) | |
194 | tmp &= ~DC_HPDx_INT_POLARITY; | |
195 | else | |
196 | tmp |= DC_HPDx_INT_POLARITY; | |
197 | WREG32(DC_HPD4_INT_CONTROL, tmp); | |
198 | break; | |
199 | case RADEON_HPD_5: | |
200 | tmp = RREG32(DC_HPD5_INT_CONTROL); | |
201 | if (connected) | |
202 | tmp &= ~DC_HPDx_INT_POLARITY; | |
203 | else | |
204 | tmp |= DC_HPDx_INT_POLARITY; | |
205 | WREG32(DC_HPD5_INT_CONTROL, tmp); | |
206 | break; | |
207 | /* DCE 3.2 */ | |
208 | case RADEON_HPD_6: | |
209 | tmp = RREG32(DC_HPD6_INT_CONTROL); | |
210 | if (connected) | |
211 | tmp &= ~DC_HPDx_INT_POLARITY; | |
212 | else | |
213 | tmp |= DC_HPDx_INT_POLARITY; | |
214 | WREG32(DC_HPD6_INT_CONTROL, tmp); | |
215 | break; | |
216 | default: | |
217 | break; | |
218 | } | |
219 | } else { | |
220 | switch (hpd) { | |
221 | case RADEON_HPD_1: | |
222 | tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL); | |
223 | if (connected) | |
224 | tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY; | |
225 | else | |
226 | tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY; | |
227 | WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); | |
228 | break; | |
229 | case RADEON_HPD_2: | |
230 | tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL); | |
231 | if (connected) | |
232 | tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY; | |
233 | else | |
234 | tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY; | |
235 | WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); | |
236 | break; | |
237 | case RADEON_HPD_3: | |
238 | tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL); | |
239 | if (connected) | |
240 | tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY; | |
241 | else | |
242 | tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY; | |
243 | WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); | |
244 | break; | |
245 | default: | |
246 | break; | |
247 | } | |
248 | } | |
249 | } | |
250 | ||
251 | void r600_hpd_init(struct radeon_device *rdev) | |
252 | { | |
253 | struct drm_device *dev = rdev->ddev; | |
254 | struct drm_connector *connector; | |
255 | ||
256 | if (ASIC_IS_DCE3(rdev)) { | |
257 | u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa); | |
258 | if (ASIC_IS_DCE32(rdev)) | |
259 | tmp |= DC_HPDx_EN; | |
260 | ||
261 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
262 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
263 | switch (radeon_connector->hpd.hpd) { | |
264 | case RADEON_HPD_1: | |
265 | WREG32(DC_HPD1_CONTROL, tmp); | |
266 | rdev->irq.hpd[0] = true; | |
267 | break; | |
268 | case RADEON_HPD_2: | |
269 | WREG32(DC_HPD2_CONTROL, tmp); | |
270 | rdev->irq.hpd[1] = true; | |
271 | break; | |
272 | case RADEON_HPD_3: | |
273 | WREG32(DC_HPD3_CONTROL, tmp); | |
274 | rdev->irq.hpd[2] = true; | |
275 | break; | |
276 | case RADEON_HPD_4: | |
277 | WREG32(DC_HPD4_CONTROL, tmp); | |
278 | rdev->irq.hpd[3] = true; | |
279 | break; | |
280 | /* DCE 3.2 */ | |
281 | case RADEON_HPD_5: | |
282 | WREG32(DC_HPD5_CONTROL, tmp); | |
283 | rdev->irq.hpd[4] = true; | |
284 | break; | |
285 | case RADEON_HPD_6: | |
286 | WREG32(DC_HPD6_CONTROL, tmp); | |
287 | rdev->irq.hpd[5] = true; | |
288 | break; | |
289 | default: | |
290 | break; | |
291 | } | |
292 | } | |
293 | } else { | |
294 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
295 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
296 | switch (radeon_connector->hpd.hpd) { | |
297 | case RADEON_HPD_1: | |
298 | WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN); | |
299 | rdev->irq.hpd[0] = true; | |
300 | break; | |
301 | case RADEON_HPD_2: | |
302 | WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN); | |
303 | rdev->irq.hpd[1] = true; | |
304 | break; | |
305 | case RADEON_HPD_3: | |
306 | WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN); | |
307 | rdev->irq.hpd[2] = true; | |
308 | break; | |
309 | default: | |
310 | break; | |
311 | } | |
312 | } | |
313 | } | |
003e69f9 JG |
314 | if (rdev->irq.installed) |
315 | r600_irq_set(rdev); | |
e0df1ac5 AD |
316 | } |
317 | ||
318 | void r600_hpd_fini(struct radeon_device *rdev) | |
319 | { | |
320 | struct drm_device *dev = rdev->ddev; | |
321 | struct drm_connector *connector; | |
322 | ||
323 | if (ASIC_IS_DCE3(rdev)) { | |
324 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
325 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
326 | switch (radeon_connector->hpd.hpd) { | |
327 | case RADEON_HPD_1: | |
328 | WREG32(DC_HPD1_CONTROL, 0); | |
329 | rdev->irq.hpd[0] = false; | |
330 | break; | |
331 | case RADEON_HPD_2: | |
332 | WREG32(DC_HPD2_CONTROL, 0); | |
333 | rdev->irq.hpd[1] = false; | |
334 | break; | |
335 | case RADEON_HPD_3: | |
336 | WREG32(DC_HPD3_CONTROL, 0); | |
337 | rdev->irq.hpd[2] = false; | |
338 | break; | |
339 | case RADEON_HPD_4: | |
340 | WREG32(DC_HPD4_CONTROL, 0); | |
341 | rdev->irq.hpd[3] = false; | |
342 | break; | |
343 | /* DCE 3.2 */ | |
344 | case RADEON_HPD_5: | |
345 | WREG32(DC_HPD5_CONTROL, 0); | |
346 | rdev->irq.hpd[4] = false; | |
347 | break; | |
348 | case RADEON_HPD_6: | |
349 | WREG32(DC_HPD6_CONTROL, 0); | |
350 | rdev->irq.hpd[5] = false; | |
351 | break; | |
352 | default: | |
353 | break; | |
354 | } | |
355 | } | |
356 | } else { | |
357 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
358 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
359 | switch (radeon_connector->hpd.hpd) { | |
360 | case RADEON_HPD_1: | |
361 | WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0); | |
362 | rdev->irq.hpd[0] = false; | |
363 | break; | |
364 | case RADEON_HPD_2: | |
365 | WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0); | |
366 | rdev->irq.hpd[1] = false; | |
367 | break; | |
368 | case RADEON_HPD_3: | |
369 | WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0); | |
370 | rdev->irq.hpd[2] = false; | |
371 | break; | |
372 | default: | |
373 | break; | |
374 | } | |
375 | } | |
376 | } | |
377 | } | |
378 | ||
771fe6b9 | 379 | /* |
3ce0a23d | 380 | * R600 PCIE GART |
771fe6b9 | 381 | */ |
3ce0a23d JG |
382 | void r600_pcie_gart_tlb_flush(struct radeon_device *rdev) |
383 | { | |
384 | unsigned i; | |
385 | u32 tmp; | |
386 | ||
2e98f10a DA |
387 | /* flush hdp cache so updates hit vram */ |
388 | WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); | |
389 | ||
3ce0a23d JG |
390 | WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12); |
391 | WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12); | |
392 | WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1)); | |
393 | for (i = 0; i < rdev->usec_timeout; i++) { | |
394 | /* read MC_STATUS */ | |
395 | tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE); | |
396 | tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT; | |
397 | if (tmp == 2) { | |
398 | printk(KERN_WARNING "[drm] r600 flush TLB failed\n"); | |
399 | return; | |
400 | } | |
401 | if (tmp) { | |
402 | return; | |
403 | } | |
404 | udelay(1); | |
405 | } | |
406 | } | |
407 | ||
4aac0473 | 408 | int r600_pcie_gart_init(struct radeon_device *rdev) |
3ce0a23d | 409 | { |
4aac0473 | 410 | int r; |
3ce0a23d | 411 | |
4aac0473 JG |
412 | if (rdev->gart.table.vram.robj) { |
413 | WARN(1, "R600 PCIE GART already initialized.\n"); | |
414 | return 0; | |
415 | } | |
3ce0a23d JG |
416 | /* Initialize common gart structure */ |
417 | r = radeon_gart_init(rdev); | |
4aac0473 | 418 | if (r) |
3ce0a23d | 419 | return r; |
3ce0a23d | 420 | rdev->gart.table_size = rdev->gart.num_gpu_pages * 8; |
4aac0473 JG |
421 | return radeon_gart_table_vram_alloc(rdev); |
422 | } | |
423 | ||
424 | int r600_pcie_gart_enable(struct radeon_device *rdev) | |
425 | { | |
426 | u32 tmp; | |
427 | int r, i; | |
428 | ||
429 | if (rdev->gart.table.vram.robj == NULL) { | |
430 | dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); | |
431 | return -EINVAL; | |
771fe6b9 | 432 | } |
4aac0473 JG |
433 | r = radeon_gart_table_vram_pin(rdev); |
434 | if (r) | |
435 | return r; | |
82568565 | 436 | radeon_gart_restore(rdev); |
bc1a631e | 437 | |
3ce0a23d JG |
438 | /* Setup L2 cache */ |
439 | WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | | |
440 | ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | | |
441 | EFFECTIVE_L2_QUEUE_SIZE(7)); | |
442 | WREG32(VM_L2_CNTL2, 0); | |
443 | WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); | |
444 | /* Setup TLB control */ | |
445 | tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | | |
446 | SYSTEM_ACCESS_MODE_NOT_IN_SYS | | |
447 | EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) | | |
448 | ENABLE_WAIT_L2_QUERY; | |
449 | WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); | |
450 | WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); | |
451 | WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING); | |
452 | WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); | |
453 | WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); | |
454 | WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); | |
455 | WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); | |
456 | WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); | |
457 | WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); | |
458 | WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); | |
459 | WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); | |
460 | WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); | |
461 | WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); | |
462 | WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); | |
463 | WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); | |
1a029b76 | 464 | WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); |
3ce0a23d JG |
465 | WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); |
466 | WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | | |
467 | RANGE_PROTECTION_FAULT_ENABLE_DEFAULT); | |
468 | WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, | |
469 | (u32)(rdev->dummy_page.addr >> 12)); | |
470 | for (i = 1; i < 7; i++) | |
471 | WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); | |
771fe6b9 | 472 | |
3ce0a23d JG |
473 | r600_pcie_gart_tlb_flush(rdev); |
474 | rdev->gart.ready = true; | |
771fe6b9 JG |
475 | return 0; |
476 | } | |
477 | ||
3ce0a23d | 478 | void r600_pcie_gart_disable(struct radeon_device *rdev) |
771fe6b9 | 479 | { |
3ce0a23d | 480 | u32 tmp; |
4c788679 | 481 | int i, r; |
771fe6b9 | 482 | |
3ce0a23d JG |
483 | /* Disable all tables */ |
484 | for (i = 0; i < 7; i++) | |
485 | WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); | |
771fe6b9 | 486 | |
3ce0a23d JG |
487 | /* Disable L2 cache */ |
488 | WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING | | |
489 | EFFECTIVE_L2_QUEUE_SIZE(7)); | |
490 | WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); | |
491 | /* Setup L1 TLB control */ | |
492 | tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) | | |
493 | ENABLE_WAIT_L2_QUERY; | |
494 | WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); | |
495 | WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); | |
496 | WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); | |
497 | WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); | |
498 | WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); | |
499 | WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); | |
500 | WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); | |
501 | WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); | |
502 | WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp); | |
503 | WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp); | |
504 | WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); | |
505 | WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); | |
506 | WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp); | |
507 | WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); | |
4aac0473 | 508 | if (rdev->gart.table.vram.robj) { |
4c788679 JG |
509 | r = radeon_bo_reserve(rdev->gart.table.vram.robj, false); |
510 | if (likely(r == 0)) { | |
511 | radeon_bo_kunmap(rdev->gart.table.vram.robj); | |
512 | radeon_bo_unpin(rdev->gart.table.vram.robj); | |
513 | radeon_bo_unreserve(rdev->gart.table.vram.robj); | |
514 | } | |
4aac0473 JG |
515 | } |
516 | } | |
517 | ||
518 | void r600_pcie_gart_fini(struct radeon_device *rdev) | |
519 | { | |
f9274562 | 520 | radeon_gart_fini(rdev); |
4aac0473 JG |
521 | r600_pcie_gart_disable(rdev); |
522 | radeon_gart_table_vram_free(rdev); | |
771fe6b9 JG |
523 | } |
524 | ||
1a029b76 JG |
525 | void r600_agp_enable(struct radeon_device *rdev) |
526 | { | |
527 | u32 tmp; | |
528 | int i; | |
529 | ||
530 | /* Setup L2 cache */ | |
531 | WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | | |
532 | ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | | |
533 | EFFECTIVE_L2_QUEUE_SIZE(7)); | |
534 | WREG32(VM_L2_CNTL2, 0); | |
535 | WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); | |
536 | /* Setup TLB control */ | |
537 | tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | | |
538 | SYSTEM_ACCESS_MODE_NOT_IN_SYS | | |
539 | EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) | | |
540 | ENABLE_WAIT_L2_QUERY; | |
541 | WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); | |
542 | WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); | |
543 | WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING); | |
544 | WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); | |
545 | WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); | |
546 | WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); | |
547 | WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); | |
548 | WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); | |
549 | WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); | |
550 | WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); | |
551 | WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); | |
552 | WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); | |
553 | WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); | |
554 | WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); | |
555 | for (i = 0; i < 7; i++) | |
556 | WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); | |
557 | } | |
558 | ||
771fe6b9 JG |
559 | int r600_mc_wait_for_idle(struct radeon_device *rdev) |
560 | { | |
3ce0a23d JG |
561 | unsigned i; |
562 | u32 tmp; | |
563 | ||
564 | for (i = 0; i < rdev->usec_timeout; i++) { | |
565 | /* read MC_STATUS */ | |
566 | tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00; | |
567 | if (!tmp) | |
568 | return 0; | |
569 | udelay(1); | |
570 | } | |
571 | return -1; | |
771fe6b9 JG |
572 | } |
573 | ||
a3c1945a | 574 | static void r600_mc_program(struct radeon_device *rdev) |
771fe6b9 | 575 | { |
a3c1945a | 576 | struct rv515_mc_save save; |
3ce0a23d JG |
577 | u32 tmp; |
578 | int i, j; | |
771fe6b9 | 579 | |
3ce0a23d JG |
580 | /* Initialize HDP */ |
581 | for (i = 0, j = 0; i < 32; i++, j += 0x18) { | |
582 | WREG32((0x2c14 + j), 0x00000000); | |
583 | WREG32((0x2c18 + j), 0x00000000); | |
584 | WREG32((0x2c1c + j), 0x00000000); | |
585 | WREG32((0x2c20 + j), 0x00000000); | |
586 | WREG32((0x2c24 + j), 0x00000000); | |
587 | } | |
588 | WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0); | |
771fe6b9 | 589 | |
a3c1945a | 590 | rv515_mc_stop(rdev, &save); |
3ce0a23d | 591 | if (r600_mc_wait_for_idle(rdev)) { |
a3c1945a | 592 | dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); |
3ce0a23d | 593 | } |
a3c1945a | 594 | /* Lockout access through VGA aperture (doesn't exist before R600) */ |
3ce0a23d | 595 | WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE); |
3ce0a23d | 596 | /* Update configuration */ |
1a029b76 JG |
597 | if (rdev->flags & RADEON_IS_AGP) { |
598 | if (rdev->mc.vram_start < rdev->mc.gtt_start) { | |
599 | /* VRAM before AGP */ | |
600 | WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, | |
601 | rdev->mc.vram_start >> 12); | |
602 | WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, | |
603 | rdev->mc.gtt_end >> 12); | |
604 | } else { | |
605 | /* VRAM after AGP */ | |
606 | WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, | |
607 | rdev->mc.gtt_start >> 12); | |
608 | WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, | |
609 | rdev->mc.vram_end >> 12); | |
610 | } | |
611 | } else { | |
612 | WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12); | |
613 | WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12); | |
614 | } | |
3ce0a23d | 615 | WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0); |
1a029b76 | 616 | tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16; |
3ce0a23d JG |
617 | tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF); |
618 | WREG32(MC_VM_FB_LOCATION, tmp); | |
619 | WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); | |
620 | WREG32(HDP_NONSURFACE_INFO, (2 << 7)); | |
1a029b76 | 621 | WREG32(HDP_NONSURFACE_SIZE, rdev->mc.mc_vram_size | 0x3FF); |
3ce0a23d | 622 | if (rdev->flags & RADEON_IS_AGP) { |
1a029b76 JG |
623 | WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22); |
624 | WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22); | |
3ce0a23d JG |
625 | WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22); |
626 | } else { | |
627 | WREG32(MC_VM_AGP_BASE, 0); | |
628 | WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF); | |
629 | WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF); | |
630 | } | |
3ce0a23d | 631 | if (r600_mc_wait_for_idle(rdev)) { |
a3c1945a | 632 | dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); |
3ce0a23d | 633 | } |
a3c1945a | 634 | rv515_mc_resume(rdev, &save); |
698443d9 DA |
635 | /* we need to own VRAM, so turn off the VGA renderer here |
636 | * to stop it overwriting our objects */ | |
d39c3b89 | 637 | rv515_vga_render_disable(rdev); |
3ce0a23d JG |
638 | } |
639 | ||
d594e46a JG |
640 | /** |
641 | * r600_vram_gtt_location - try to find VRAM & GTT location | |
642 | * @rdev: radeon device structure holding all necessary informations | |
643 | * @mc: memory controller structure holding memory informations | |
644 | * | |
645 | * Function will place try to place VRAM at same place as in CPU (PCI) | |
646 | * address space as some GPU seems to have issue when we reprogram at | |
647 | * different address space. | |
648 | * | |
649 | * If there is not enough space to fit the unvisible VRAM after the | |
650 | * aperture then we limit the VRAM size to the aperture. | |
651 | * | |
652 | * If we are using AGP then place VRAM adjacent to AGP aperture are we need | |
653 | * them to be in one from GPU point of view so that we can program GPU to | |
654 | * catch access outside them (weird GPU policy see ??). | |
655 | * | |
656 | * This function will never fails, worst case are limiting VRAM or GTT. | |
657 | * | |
658 | * Note: GTT start, end, size should be initialized before calling this | |
659 | * function on AGP platform. | |
660 | */ | |
661 | void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc) | |
662 | { | |
663 | u64 size_bf, size_af; | |
664 | ||
665 | if (mc->mc_vram_size > 0xE0000000) { | |
666 | /* leave room for at least 512M GTT */ | |
667 | dev_warn(rdev->dev, "limiting VRAM\n"); | |
668 | mc->real_vram_size = 0xE0000000; | |
669 | mc->mc_vram_size = 0xE0000000; | |
670 | } | |
671 | if (rdev->flags & RADEON_IS_AGP) { | |
672 | size_bf = mc->gtt_start; | |
673 | size_af = 0xFFFFFFFF - mc->gtt_end + 1; | |
674 | if (size_bf > size_af) { | |
675 | if (mc->mc_vram_size > size_bf) { | |
676 | dev_warn(rdev->dev, "limiting VRAM\n"); | |
677 | mc->real_vram_size = size_bf; | |
678 | mc->mc_vram_size = size_bf; | |
679 | } | |
680 | mc->vram_start = mc->gtt_start - mc->mc_vram_size; | |
681 | } else { | |
682 | if (mc->mc_vram_size > size_af) { | |
683 | dev_warn(rdev->dev, "limiting VRAM\n"); | |
684 | mc->real_vram_size = size_af; | |
685 | mc->mc_vram_size = size_af; | |
686 | } | |
687 | mc->vram_start = mc->gtt_end; | |
688 | } | |
689 | mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; | |
690 | dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n", | |
691 | mc->mc_vram_size >> 20, mc->vram_start, | |
692 | mc->vram_end, mc->real_vram_size >> 20); | |
693 | } else { | |
694 | u64 base = 0; | |
695 | if (rdev->flags & RADEON_IS_IGP) | |
696 | base = (RREG32(MC_VM_FB_LOCATION) & 0xFFFF) << 24; | |
697 | radeon_vram_location(rdev, &rdev->mc, base); | |
698 | radeon_gtt_location(rdev, mc); | |
699 | } | |
700 | } | |
701 | ||
3ce0a23d | 702 | int r600_mc_init(struct radeon_device *rdev) |
771fe6b9 | 703 | { |
3ce0a23d | 704 | u32 tmp; |
5885b7a9 | 705 | int chansize, numchan; |
771fe6b9 | 706 | |
3ce0a23d | 707 | /* Get VRAM informations */ |
771fe6b9 | 708 | rdev->mc.vram_is_ddr = true; |
3ce0a23d JG |
709 | tmp = RREG32(RAMCFG); |
710 | if (tmp & CHANSIZE_OVERRIDE) { | |
771fe6b9 | 711 | chansize = 16; |
3ce0a23d | 712 | } else if (tmp & CHANSIZE_MASK) { |
771fe6b9 JG |
713 | chansize = 64; |
714 | } else { | |
715 | chansize = 32; | |
716 | } | |
5885b7a9 AD |
717 | tmp = RREG32(CHMAP); |
718 | switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) { | |
719 | case 0: | |
720 | default: | |
721 | numchan = 1; | |
722 | break; | |
723 | case 1: | |
724 | numchan = 2; | |
725 | break; | |
726 | case 2: | |
727 | numchan = 4; | |
728 | break; | |
729 | case 3: | |
730 | numchan = 8; | |
731 | break; | |
771fe6b9 | 732 | } |
5885b7a9 | 733 | rdev->mc.vram_width = numchan * chansize; |
3ce0a23d JG |
734 | /* Could aper size report 0 ? */ |
735 | rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); | |
736 | rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); | |
737 | /* Setup GPU memory space */ | |
738 | rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); | |
739 | rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); | |
51e5fcd3 | 740 | rdev->mc.visible_vram_size = rdev->mc.aper_size; |
d594e46a | 741 | r600_vram_gtt_location(rdev, &rdev->mc); |
f47299c5 | 742 | |
06b6476d AD |
743 | if (rdev->flags & RADEON_IS_IGP) |
744 | rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); | |
f47299c5 | 745 | radeon_update_bandwidth_info(rdev); |
3ce0a23d | 746 | return 0; |
771fe6b9 JG |
747 | } |
748 | ||
3ce0a23d JG |
749 | /* We doesn't check that the GPU really needs a reset we simply do the |
750 | * reset, it's up to the caller to determine if the GPU needs one. We | |
751 | * might add an helper function to check that. | |
752 | */ | |
753 | int r600_gpu_soft_reset(struct radeon_device *rdev) | |
771fe6b9 | 754 | { |
a3c1945a | 755 | struct rv515_mc_save save; |
3ce0a23d JG |
756 | u32 grbm_busy_mask = S_008010_VC_BUSY(1) | S_008010_VGT_BUSY_NO_DMA(1) | |
757 | S_008010_VGT_BUSY(1) | S_008010_TA03_BUSY(1) | | |
758 | S_008010_TC_BUSY(1) | S_008010_SX_BUSY(1) | | |
759 | S_008010_SH_BUSY(1) | S_008010_SPI03_BUSY(1) | | |
760 | S_008010_SMX_BUSY(1) | S_008010_SC_BUSY(1) | | |
761 | S_008010_PA_BUSY(1) | S_008010_DB03_BUSY(1) | | |
762 | S_008010_CR_BUSY(1) | S_008010_CB03_BUSY(1) | | |
763 | S_008010_GUI_ACTIVE(1); | |
764 | u32 grbm2_busy_mask = S_008014_SPI0_BUSY(1) | S_008014_SPI1_BUSY(1) | | |
765 | S_008014_SPI2_BUSY(1) | S_008014_SPI3_BUSY(1) | | |
766 | S_008014_TA0_BUSY(1) | S_008014_TA1_BUSY(1) | | |
767 | S_008014_TA2_BUSY(1) | S_008014_TA3_BUSY(1) | | |
768 | S_008014_DB0_BUSY(1) | S_008014_DB1_BUSY(1) | | |
769 | S_008014_DB2_BUSY(1) | S_008014_DB3_BUSY(1) | | |
770 | S_008014_CB0_BUSY(1) | S_008014_CB1_BUSY(1) | | |
771 | S_008014_CB2_BUSY(1) | S_008014_CB3_BUSY(1); | |
a3c1945a | 772 | u32 tmp; |
771fe6b9 | 773 | |
1a029b76 JG |
774 | dev_info(rdev->dev, "GPU softreset \n"); |
775 | dev_info(rdev->dev, " R_008010_GRBM_STATUS=0x%08X\n", | |
776 | RREG32(R_008010_GRBM_STATUS)); | |
777 | dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n", | |
a3c1945a | 778 | RREG32(R_008014_GRBM_STATUS2)); |
1a029b76 JG |
779 | dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n", |
780 | RREG32(R_000E50_SRBM_STATUS)); | |
a3c1945a JG |
781 | rv515_mc_stop(rdev, &save); |
782 | if (r600_mc_wait_for_idle(rdev)) { | |
783 | dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); | |
784 | } | |
3ce0a23d | 785 | /* Disable CP parsing/prefetching */ |
90aca4d2 | 786 | WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1)); |
3ce0a23d JG |
787 | /* Check if any of the rendering block is busy and reset it */ |
788 | if ((RREG32(R_008010_GRBM_STATUS) & grbm_busy_mask) || | |
789 | (RREG32(R_008014_GRBM_STATUS2) & grbm2_busy_mask)) { | |
a3c1945a | 790 | tmp = S_008020_SOFT_RESET_CR(1) | |
3ce0a23d JG |
791 | S_008020_SOFT_RESET_DB(1) | |
792 | S_008020_SOFT_RESET_CB(1) | | |
793 | S_008020_SOFT_RESET_PA(1) | | |
794 | S_008020_SOFT_RESET_SC(1) | | |
795 | S_008020_SOFT_RESET_SMX(1) | | |
796 | S_008020_SOFT_RESET_SPI(1) | | |
797 | S_008020_SOFT_RESET_SX(1) | | |
798 | S_008020_SOFT_RESET_SH(1) | | |
799 | S_008020_SOFT_RESET_TC(1) | | |
800 | S_008020_SOFT_RESET_TA(1) | | |
801 | S_008020_SOFT_RESET_VC(1) | | |
a3c1945a | 802 | S_008020_SOFT_RESET_VGT(1); |
1a029b76 | 803 | dev_info(rdev->dev, " R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp); |
a3c1945a | 804 | WREG32(R_008020_GRBM_SOFT_RESET, tmp); |
90aca4d2 JG |
805 | RREG32(R_008020_GRBM_SOFT_RESET); |
806 | mdelay(15); | |
3ce0a23d | 807 | WREG32(R_008020_GRBM_SOFT_RESET, 0); |
3ce0a23d JG |
808 | } |
809 | /* Reset CP (we always reset CP) */ | |
a3c1945a JG |
810 | tmp = S_008020_SOFT_RESET_CP(1); |
811 | dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp); | |
812 | WREG32(R_008020_GRBM_SOFT_RESET, tmp); | |
90aca4d2 JG |
813 | RREG32(R_008020_GRBM_SOFT_RESET); |
814 | mdelay(15); | |
3ce0a23d | 815 | WREG32(R_008020_GRBM_SOFT_RESET, 0); |
3ce0a23d | 816 | /* Wait a little for things to settle down */ |
225758d8 | 817 | mdelay(1); |
1a029b76 JG |
818 | dev_info(rdev->dev, " R_008010_GRBM_STATUS=0x%08X\n", |
819 | RREG32(R_008010_GRBM_STATUS)); | |
820 | dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n", | |
821 | RREG32(R_008014_GRBM_STATUS2)); | |
822 | dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n", | |
823 | RREG32(R_000E50_SRBM_STATUS)); | |
a3c1945a | 824 | rv515_mc_resume(rdev, &save); |
3ce0a23d JG |
825 | return 0; |
826 | } | |
827 | ||
225758d8 JG |
828 | bool r600_gpu_is_lockup(struct radeon_device *rdev) |
829 | { | |
830 | u32 srbm_status; | |
831 | u32 grbm_status; | |
832 | u32 grbm_status2; | |
833 | int r; | |
834 | ||
835 | srbm_status = RREG32(R_000E50_SRBM_STATUS); | |
836 | grbm_status = RREG32(R_008010_GRBM_STATUS); | |
837 | grbm_status2 = RREG32(R_008014_GRBM_STATUS2); | |
838 | if (!G_008010_GUI_ACTIVE(grbm_status)) { | |
839 | r100_gpu_lockup_update(&rdev->config.r300.lockup, &rdev->cp); | |
840 | return false; | |
841 | } | |
842 | /* force CP activities */ | |
843 | r = radeon_ring_lock(rdev, 2); | |
844 | if (!r) { | |
845 | /* PACKET2 NOP */ | |
846 | radeon_ring_write(rdev, 0x80000000); | |
847 | radeon_ring_write(rdev, 0x80000000); | |
848 | radeon_ring_unlock_commit(rdev); | |
849 | } | |
850 | rdev->cp.rptr = RREG32(R600_CP_RB_RPTR); | |
851 | return r100_gpu_cp_is_lockup(rdev, &rdev->config.r300.lockup, &rdev->cp); | |
852 | } | |
853 | ||
a2d07b74 | 854 | int r600_asic_reset(struct radeon_device *rdev) |
3ce0a23d JG |
855 | { |
856 | return r600_gpu_soft_reset(rdev); | |
857 | } | |
858 | ||
859 | static u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes, | |
860 | u32 num_backends, | |
861 | u32 backend_disable_mask) | |
862 | { | |
863 | u32 backend_map = 0; | |
864 | u32 enabled_backends_mask; | |
865 | u32 enabled_backends_count; | |
866 | u32 cur_pipe; | |
867 | u32 swizzle_pipe[R6XX_MAX_PIPES]; | |
868 | u32 cur_backend; | |
869 | u32 i; | |
870 | ||
871 | if (num_tile_pipes > R6XX_MAX_PIPES) | |
872 | num_tile_pipes = R6XX_MAX_PIPES; | |
873 | if (num_tile_pipes < 1) | |
874 | num_tile_pipes = 1; | |
875 | if (num_backends > R6XX_MAX_BACKENDS) | |
876 | num_backends = R6XX_MAX_BACKENDS; | |
877 | if (num_backends < 1) | |
878 | num_backends = 1; | |
879 | ||
880 | enabled_backends_mask = 0; | |
881 | enabled_backends_count = 0; | |
882 | for (i = 0; i < R6XX_MAX_BACKENDS; ++i) { | |
883 | if (((backend_disable_mask >> i) & 1) == 0) { | |
884 | enabled_backends_mask |= (1 << i); | |
885 | ++enabled_backends_count; | |
886 | } | |
887 | if (enabled_backends_count == num_backends) | |
888 | break; | |
889 | } | |
890 | ||
891 | if (enabled_backends_count == 0) { | |
892 | enabled_backends_mask = 1; | |
893 | enabled_backends_count = 1; | |
894 | } | |
895 | ||
896 | if (enabled_backends_count != num_backends) | |
897 | num_backends = enabled_backends_count; | |
898 | ||
899 | memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES); | |
900 | switch (num_tile_pipes) { | |
901 | case 1: | |
902 | swizzle_pipe[0] = 0; | |
903 | break; | |
904 | case 2: | |
905 | swizzle_pipe[0] = 0; | |
906 | swizzle_pipe[1] = 1; | |
907 | break; | |
908 | case 3: | |
909 | swizzle_pipe[0] = 0; | |
910 | swizzle_pipe[1] = 1; | |
911 | swizzle_pipe[2] = 2; | |
912 | break; | |
913 | case 4: | |
914 | swizzle_pipe[0] = 0; | |
915 | swizzle_pipe[1] = 1; | |
916 | swizzle_pipe[2] = 2; | |
917 | swizzle_pipe[3] = 3; | |
918 | break; | |
919 | case 5: | |
920 | swizzle_pipe[0] = 0; | |
921 | swizzle_pipe[1] = 1; | |
922 | swizzle_pipe[2] = 2; | |
923 | swizzle_pipe[3] = 3; | |
924 | swizzle_pipe[4] = 4; | |
925 | break; | |
926 | case 6: | |
927 | swizzle_pipe[0] = 0; | |
928 | swizzle_pipe[1] = 2; | |
929 | swizzle_pipe[2] = 4; | |
930 | swizzle_pipe[3] = 5; | |
931 | swizzle_pipe[4] = 1; | |
932 | swizzle_pipe[5] = 3; | |
933 | break; | |
934 | case 7: | |
935 | swizzle_pipe[0] = 0; | |
936 | swizzle_pipe[1] = 2; | |
937 | swizzle_pipe[2] = 4; | |
938 | swizzle_pipe[3] = 6; | |
939 | swizzle_pipe[4] = 1; | |
940 | swizzle_pipe[5] = 3; | |
941 | swizzle_pipe[6] = 5; | |
942 | break; | |
943 | case 8: | |
944 | swizzle_pipe[0] = 0; | |
945 | swizzle_pipe[1] = 2; | |
946 | swizzle_pipe[2] = 4; | |
947 | swizzle_pipe[3] = 6; | |
948 | swizzle_pipe[4] = 1; | |
949 | swizzle_pipe[5] = 3; | |
950 | swizzle_pipe[6] = 5; | |
951 | swizzle_pipe[7] = 7; | |
952 | break; | |
953 | } | |
954 | ||
955 | cur_backend = 0; | |
956 | for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) { | |
957 | while (((1 << cur_backend) & enabled_backends_mask) == 0) | |
958 | cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS; | |
959 | ||
960 | backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2))); | |
961 | ||
962 | cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS; | |
963 | } | |
964 | ||
965 | return backend_map; | |
966 | } | |
967 | ||
968 | int r600_count_pipe_bits(uint32_t val) | |
969 | { | |
970 | int i, ret = 0; | |
971 | ||
972 | for (i = 0; i < 32; i++) { | |
973 | ret += val & 1; | |
974 | val >>= 1; | |
975 | } | |
976 | return ret; | |
771fe6b9 JG |
977 | } |
978 | ||
3ce0a23d JG |
979 | void r600_gpu_init(struct radeon_device *rdev) |
980 | { | |
981 | u32 tiling_config; | |
982 | u32 ramcfg; | |
d03f5d59 AD |
983 | u32 backend_map; |
984 | u32 cc_rb_backend_disable; | |
985 | u32 cc_gc_shader_pipe_config; | |
3ce0a23d JG |
986 | u32 tmp; |
987 | int i, j; | |
988 | u32 sq_config; | |
989 | u32 sq_gpr_resource_mgmt_1 = 0; | |
990 | u32 sq_gpr_resource_mgmt_2 = 0; | |
991 | u32 sq_thread_resource_mgmt = 0; | |
992 | u32 sq_stack_resource_mgmt_1 = 0; | |
993 | u32 sq_stack_resource_mgmt_2 = 0; | |
994 | ||
995 | /* FIXME: implement */ | |
996 | switch (rdev->family) { | |
997 | case CHIP_R600: | |
998 | rdev->config.r600.max_pipes = 4; | |
999 | rdev->config.r600.max_tile_pipes = 8; | |
1000 | rdev->config.r600.max_simds = 4; | |
1001 | rdev->config.r600.max_backends = 4; | |
1002 | rdev->config.r600.max_gprs = 256; | |
1003 | rdev->config.r600.max_threads = 192; | |
1004 | rdev->config.r600.max_stack_entries = 256; | |
1005 | rdev->config.r600.max_hw_contexts = 8; | |
1006 | rdev->config.r600.max_gs_threads = 16; | |
1007 | rdev->config.r600.sx_max_export_size = 128; | |
1008 | rdev->config.r600.sx_max_export_pos_size = 16; | |
1009 | rdev->config.r600.sx_max_export_smx_size = 128; | |
1010 | rdev->config.r600.sq_num_cf_insts = 2; | |
1011 | break; | |
1012 | case CHIP_RV630: | |
1013 | case CHIP_RV635: | |
1014 | rdev->config.r600.max_pipes = 2; | |
1015 | rdev->config.r600.max_tile_pipes = 2; | |
1016 | rdev->config.r600.max_simds = 3; | |
1017 | rdev->config.r600.max_backends = 1; | |
1018 | rdev->config.r600.max_gprs = 128; | |
1019 | rdev->config.r600.max_threads = 192; | |
1020 | rdev->config.r600.max_stack_entries = 128; | |
1021 | rdev->config.r600.max_hw_contexts = 8; | |
1022 | rdev->config.r600.max_gs_threads = 4; | |
1023 | rdev->config.r600.sx_max_export_size = 128; | |
1024 | rdev->config.r600.sx_max_export_pos_size = 16; | |
1025 | rdev->config.r600.sx_max_export_smx_size = 128; | |
1026 | rdev->config.r600.sq_num_cf_insts = 2; | |
1027 | break; | |
1028 | case CHIP_RV610: | |
1029 | case CHIP_RV620: | |
1030 | case CHIP_RS780: | |
1031 | case CHIP_RS880: | |
1032 | rdev->config.r600.max_pipes = 1; | |
1033 | rdev->config.r600.max_tile_pipes = 1; | |
1034 | rdev->config.r600.max_simds = 2; | |
1035 | rdev->config.r600.max_backends = 1; | |
1036 | rdev->config.r600.max_gprs = 128; | |
1037 | rdev->config.r600.max_threads = 192; | |
1038 | rdev->config.r600.max_stack_entries = 128; | |
1039 | rdev->config.r600.max_hw_contexts = 4; | |
1040 | rdev->config.r600.max_gs_threads = 4; | |
1041 | rdev->config.r600.sx_max_export_size = 128; | |
1042 | rdev->config.r600.sx_max_export_pos_size = 16; | |
1043 | rdev->config.r600.sx_max_export_smx_size = 128; | |
1044 | rdev->config.r600.sq_num_cf_insts = 1; | |
1045 | break; | |
1046 | case CHIP_RV670: | |
1047 | rdev->config.r600.max_pipes = 4; | |
1048 | rdev->config.r600.max_tile_pipes = 4; | |
1049 | rdev->config.r600.max_simds = 4; | |
1050 | rdev->config.r600.max_backends = 4; | |
1051 | rdev->config.r600.max_gprs = 192; | |
1052 | rdev->config.r600.max_threads = 192; | |
1053 | rdev->config.r600.max_stack_entries = 256; | |
1054 | rdev->config.r600.max_hw_contexts = 8; | |
1055 | rdev->config.r600.max_gs_threads = 16; | |
1056 | rdev->config.r600.sx_max_export_size = 128; | |
1057 | rdev->config.r600.sx_max_export_pos_size = 16; | |
1058 | rdev->config.r600.sx_max_export_smx_size = 128; | |
1059 | rdev->config.r600.sq_num_cf_insts = 2; | |
1060 | break; | |
1061 | default: | |
1062 | break; | |
1063 | } | |
1064 | ||
1065 | /* Initialize HDP */ | |
1066 | for (i = 0, j = 0; i < 32; i++, j += 0x18) { | |
1067 | WREG32((0x2c14 + j), 0x00000000); | |
1068 | WREG32((0x2c18 + j), 0x00000000); | |
1069 | WREG32((0x2c1c + j), 0x00000000); | |
1070 | WREG32((0x2c20 + j), 0x00000000); | |
1071 | WREG32((0x2c24 + j), 0x00000000); | |
1072 | } | |
1073 | ||
1074 | WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); | |
1075 | ||
1076 | /* Setup tiling */ | |
1077 | tiling_config = 0; | |
1078 | ramcfg = RREG32(RAMCFG); | |
1079 | switch (rdev->config.r600.max_tile_pipes) { | |
1080 | case 1: | |
1081 | tiling_config |= PIPE_TILING(0); | |
1082 | break; | |
1083 | case 2: | |
1084 | tiling_config |= PIPE_TILING(1); | |
1085 | break; | |
1086 | case 4: | |
1087 | tiling_config |= PIPE_TILING(2); | |
1088 | break; | |
1089 | case 8: | |
1090 | tiling_config |= PIPE_TILING(3); | |
1091 | break; | |
1092 | default: | |
1093 | break; | |
1094 | } | |
d03f5d59 | 1095 | rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes; |
961fb597 | 1096 | rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT); |
3ce0a23d JG |
1097 | tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT); |
1098 | tiling_config |= GROUP_SIZE(0); | |
961fb597 | 1099 | rdev->config.r600.tiling_group_size = 256; |
3ce0a23d JG |
1100 | tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT; |
1101 | if (tmp > 3) { | |
1102 | tiling_config |= ROW_TILING(3); | |
1103 | tiling_config |= SAMPLE_SPLIT(3); | |
1104 | } else { | |
1105 | tiling_config |= ROW_TILING(tmp); | |
1106 | tiling_config |= SAMPLE_SPLIT(tmp); | |
1107 | } | |
1108 | tiling_config |= BANK_SWAPS(1); | |
d03f5d59 AD |
1109 | |
1110 | cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000; | |
1111 | cc_rb_backend_disable |= | |
1112 | BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << rdev->config.r600.max_backends) & R6XX_MAX_BACKENDS_MASK); | |
1113 | ||
1114 | cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00; | |
1115 | cc_gc_shader_pipe_config |= | |
1116 | INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << rdev->config.r600.max_pipes) & R6XX_MAX_PIPES_MASK); | |
1117 | cc_gc_shader_pipe_config |= | |
1118 | INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << rdev->config.r600.max_simds) & R6XX_MAX_SIMDS_MASK); | |
1119 | ||
1120 | backend_map = r600_get_tile_pipe_to_backend_map(rdev->config.r600.max_tile_pipes, | |
1121 | (R6XX_MAX_BACKENDS - | |
1122 | r600_count_pipe_bits((cc_rb_backend_disable & | |
1123 | R6XX_MAX_BACKENDS_MASK) >> 16)), | |
1124 | (cc_rb_backend_disable >> 16)); | |
1125 | ||
1126 | tiling_config |= BACKEND_MAP(backend_map); | |
3ce0a23d JG |
1127 | WREG32(GB_TILING_CONFIG, tiling_config); |
1128 | WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff); | |
1129 | WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff); | |
1130 | ||
3ce0a23d | 1131 | /* Setup pipes */ |
d03f5d59 AD |
1132 | WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable); |
1133 | WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); | |
f867c60d | 1134 | WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); |
3ce0a23d | 1135 | |
d03f5d59 | 1136 | tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8); |
3ce0a23d JG |
1137 | WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK); |
1138 | WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK); | |
1139 | ||
1140 | /* Setup some CP states */ | |
1141 | WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b))); | |
1142 | WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40))); | |
1143 | ||
1144 | WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT | | |
1145 | SYNC_WALKER | SYNC_ALIGNER)); | |
1146 | /* Setup various GPU states */ | |
1147 | if (rdev->family == CHIP_RV670) | |
1148 | WREG32(ARB_GDEC_RD_CNTL, 0x00000021); | |
1149 | ||
1150 | tmp = RREG32(SX_DEBUG_1); | |
1151 | tmp |= SMX_EVENT_RELEASE; | |
1152 | if ((rdev->family > CHIP_R600)) | |
1153 | tmp |= ENABLE_NEW_SMX_ADDRESS; | |
1154 | WREG32(SX_DEBUG_1, tmp); | |
1155 | ||
1156 | if (((rdev->family) == CHIP_R600) || | |
1157 | ((rdev->family) == CHIP_RV630) || | |
1158 | ((rdev->family) == CHIP_RV610) || | |
1159 | ((rdev->family) == CHIP_RV620) || | |
ee59f2b4 AD |
1160 | ((rdev->family) == CHIP_RS780) || |
1161 | ((rdev->family) == CHIP_RS880)) { | |
3ce0a23d JG |
1162 | WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE); |
1163 | } else { | |
1164 | WREG32(DB_DEBUG, 0); | |
1165 | } | |
1166 | WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) | | |
1167 | DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4))); | |
1168 | ||
1169 | WREG32(PA_SC_MULTI_CHIP_CNTL, 0); | |
1170 | WREG32(VGT_NUM_INSTANCES, 0); | |
1171 | ||
1172 | WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0)); | |
1173 | WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0)); | |
1174 | ||
1175 | tmp = RREG32(SQ_MS_FIFO_SIZES); | |
1176 | if (((rdev->family) == CHIP_RV610) || | |
1177 | ((rdev->family) == CHIP_RV620) || | |
ee59f2b4 AD |
1178 | ((rdev->family) == CHIP_RS780) || |
1179 | ((rdev->family) == CHIP_RS880)) { | |
3ce0a23d JG |
1180 | tmp = (CACHE_FIFO_SIZE(0xa) | |
1181 | FETCH_FIFO_HIWATER(0xa) | | |
1182 | DONE_FIFO_HIWATER(0xe0) | | |
1183 | ALU_UPDATE_FIFO_HIWATER(0x8)); | |
1184 | } else if (((rdev->family) == CHIP_R600) || | |
1185 | ((rdev->family) == CHIP_RV630)) { | |
1186 | tmp &= ~DONE_FIFO_HIWATER(0xff); | |
1187 | tmp |= DONE_FIFO_HIWATER(0x4); | |
1188 | } | |
1189 | WREG32(SQ_MS_FIFO_SIZES, tmp); | |
1190 | ||
1191 | /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT | |
1192 | * should be adjusted as needed by the 2D/3D drivers. This just sets default values | |
1193 | */ | |
1194 | sq_config = RREG32(SQ_CONFIG); | |
1195 | sq_config &= ~(PS_PRIO(3) | | |
1196 | VS_PRIO(3) | | |
1197 | GS_PRIO(3) | | |
1198 | ES_PRIO(3)); | |
1199 | sq_config |= (DX9_CONSTS | | |
1200 | VC_ENABLE | | |
1201 | PS_PRIO(0) | | |
1202 | VS_PRIO(1) | | |
1203 | GS_PRIO(2) | | |
1204 | ES_PRIO(3)); | |
1205 | ||
1206 | if ((rdev->family) == CHIP_R600) { | |
1207 | sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) | | |
1208 | NUM_VS_GPRS(124) | | |
1209 | NUM_CLAUSE_TEMP_GPRS(4)); | |
1210 | sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) | | |
1211 | NUM_ES_GPRS(0)); | |
1212 | sq_thread_resource_mgmt = (NUM_PS_THREADS(136) | | |
1213 | NUM_VS_THREADS(48) | | |
1214 | NUM_GS_THREADS(4) | | |
1215 | NUM_ES_THREADS(4)); | |
1216 | sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) | | |
1217 | NUM_VS_STACK_ENTRIES(128)); | |
1218 | sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) | | |
1219 | NUM_ES_STACK_ENTRIES(0)); | |
1220 | } else if (((rdev->family) == CHIP_RV610) || | |
1221 | ((rdev->family) == CHIP_RV620) || | |
ee59f2b4 AD |
1222 | ((rdev->family) == CHIP_RS780) || |
1223 | ((rdev->family) == CHIP_RS880)) { | |
3ce0a23d JG |
1224 | /* no vertex cache */ |
1225 | sq_config &= ~VC_ENABLE; | |
1226 | ||
1227 | sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) | | |
1228 | NUM_VS_GPRS(44) | | |
1229 | NUM_CLAUSE_TEMP_GPRS(2)); | |
1230 | sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) | | |
1231 | NUM_ES_GPRS(17)); | |
1232 | sq_thread_resource_mgmt = (NUM_PS_THREADS(79) | | |
1233 | NUM_VS_THREADS(78) | | |
1234 | NUM_GS_THREADS(4) | | |
1235 | NUM_ES_THREADS(31)); | |
1236 | sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) | | |
1237 | NUM_VS_STACK_ENTRIES(40)); | |
1238 | sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) | | |
1239 | NUM_ES_STACK_ENTRIES(16)); | |
1240 | } else if (((rdev->family) == CHIP_RV630) || | |
1241 | ((rdev->family) == CHIP_RV635)) { | |
1242 | sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) | | |
1243 | NUM_VS_GPRS(44) | | |
1244 | NUM_CLAUSE_TEMP_GPRS(2)); | |
1245 | sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) | | |
1246 | NUM_ES_GPRS(18)); | |
1247 | sq_thread_resource_mgmt = (NUM_PS_THREADS(79) | | |
1248 | NUM_VS_THREADS(78) | | |
1249 | NUM_GS_THREADS(4) | | |
1250 | NUM_ES_THREADS(31)); | |
1251 | sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) | | |
1252 | NUM_VS_STACK_ENTRIES(40)); | |
1253 | sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) | | |
1254 | NUM_ES_STACK_ENTRIES(16)); | |
1255 | } else if ((rdev->family) == CHIP_RV670) { | |
1256 | sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) | | |
1257 | NUM_VS_GPRS(44) | | |
1258 | NUM_CLAUSE_TEMP_GPRS(2)); | |
1259 | sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) | | |
1260 | NUM_ES_GPRS(17)); | |
1261 | sq_thread_resource_mgmt = (NUM_PS_THREADS(79) | | |
1262 | NUM_VS_THREADS(78) | | |
1263 | NUM_GS_THREADS(4) | | |
1264 | NUM_ES_THREADS(31)); | |
1265 | sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) | | |
1266 | NUM_VS_STACK_ENTRIES(64)); | |
1267 | sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) | | |
1268 | NUM_ES_STACK_ENTRIES(64)); | |
1269 | } | |
1270 | ||
1271 | WREG32(SQ_CONFIG, sq_config); | |
1272 | WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1); | |
1273 | WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2); | |
1274 | WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt); | |
1275 | WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1); | |
1276 | WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2); | |
1277 | ||
1278 | if (((rdev->family) == CHIP_RV610) || | |
1279 | ((rdev->family) == CHIP_RV620) || | |
ee59f2b4 AD |
1280 | ((rdev->family) == CHIP_RS780) || |
1281 | ((rdev->family) == CHIP_RS880)) { | |
3ce0a23d JG |
1282 | WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY)); |
1283 | } else { | |
1284 | WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC)); | |
1285 | } | |
1286 | ||
1287 | /* More default values. 2D/3D driver should adjust as needed */ | |
1288 | WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) | | |
1289 | S1_X(0x4) | S1_Y(0xc))); | |
1290 | WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) | | |
1291 | S1_X(0x2) | S1_Y(0x2) | | |
1292 | S2_X(0xa) | S2_Y(0x6) | | |
1293 | S3_X(0x6) | S3_Y(0xa))); | |
1294 | WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) | | |
1295 | S1_X(0x4) | S1_Y(0xc) | | |
1296 | S2_X(0x1) | S2_Y(0x6) | | |
1297 | S3_X(0xa) | S3_Y(0xe))); | |
1298 | WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) | | |
1299 | S5_X(0x0) | S5_Y(0x0) | | |
1300 | S6_X(0xb) | S6_Y(0x4) | | |
1301 | S7_X(0x7) | S7_Y(0x8))); | |
1302 | ||
1303 | WREG32(VGT_STRMOUT_EN, 0); | |
1304 | tmp = rdev->config.r600.max_pipes * 16; | |
1305 | switch (rdev->family) { | |
1306 | case CHIP_RV610: | |
3ce0a23d | 1307 | case CHIP_RV620: |
ee59f2b4 AD |
1308 | case CHIP_RS780: |
1309 | case CHIP_RS880: | |
3ce0a23d JG |
1310 | tmp += 32; |
1311 | break; | |
1312 | case CHIP_RV670: | |
1313 | tmp += 128; | |
1314 | break; | |
1315 | default: | |
1316 | break; | |
1317 | } | |
1318 | if (tmp > 256) { | |
1319 | tmp = 256; | |
1320 | } | |
1321 | WREG32(VGT_ES_PER_GS, 128); | |
1322 | WREG32(VGT_GS_PER_ES, tmp); | |
1323 | WREG32(VGT_GS_PER_VS, 2); | |
1324 | WREG32(VGT_GS_VERTEX_REUSE, 16); | |
1325 | ||
1326 | /* more default values. 2D/3D driver should adjust as needed */ | |
1327 | WREG32(PA_SC_LINE_STIPPLE_STATE, 0); | |
1328 | WREG32(VGT_STRMOUT_EN, 0); | |
1329 | WREG32(SX_MISC, 0); | |
1330 | WREG32(PA_SC_MODE_CNTL, 0); | |
1331 | WREG32(PA_SC_AA_CONFIG, 0); | |
1332 | WREG32(PA_SC_LINE_STIPPLE, 0); | |
1333 | WREG32(SPI_INPUT_Z, 0); | |
1334 | WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2)); | |
1335 | WREG32(CB_COLOR7_FRAG, 0); | |
1336 | ||
1337 | /* Clear render buffer base addresses */ | |
1338 | WREG32(CB_COLOR0_BASE, 0); | |
1339 | WREG32(CB_COLOR1_BASE, 0); | |
1340 | WREG32(CB_COLOR2_BASE, 0); | |
1341 | WREG32(CB_COLOR3_BASE, 0); | |
1342 | WREG32(CB_COLOR4_BASE, 0); | |
1343 | WREG32(CB_COLOR5_BASE, 0); | |
1344 | WREG32(CB_COLOR6_BASE, 0); | |
1345 | WREG32(CB_COLOR7_BASE, 0); | |
1346 | WREG32(CB_COLOR7_FRAG, 0); | |
1347 | ||
1348 | switch (rdev->family) { | |
1349 | case CHIP_RV610: | |
3ce0a23d | 1350 | case CHIP_RV620: |
ee59f2b4 AD |
1351 | case CHIP_RS780: |
1352 | case CHIP_RS880: | |
3ce0a23d JG |
1353 | tmp = TC_L2_SIZE(8); |
1354 | break; | |
1355 | case CHIP_RV630: | |
1356 | case CHIP_RV635: | |
1357 | tmp = TC_L2_SIZE(4); | |
1358 | break; | |
1359 | case CHIP_R600: | |
1360 | tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT; | |
1361 | break; | |
1362 | default: | |
1363 | tmp = TC_L2_SIZE(0); | |
1364 | break; | |
1365 | } | |
1366 | WREG32(TC_CNTL, tmp); | |
1367 | ||
1368 | tmp = RREG32(HDP_HOST_PATH_CNTL); | |
1369 | WREG32(HDP_HOST_PATH_CNTL, tmp); | |
1370 | ||
1371 | tmp = RREG32(ARB_POP); | |
1372 | tmp |= ENABLE_TC128; | |
1373 | WREG32(ARB_POP, tmp); | |
1374 | ||
1375 | WREG32(PA_SC_MULTI_CHIP_CNTL, 0); | |
1376 | WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA | | |
1377 | NUM_CLIP_SEQ(3))); | |
1378 | WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095)); | |
1379 | } | |
1380 | ||
1381 | ||
771fe6b9 JG |
1382 | /* |
1383 | * Indirect registers accessor | |
1384 | */ | |
3ce0a23d JG |
1385 | u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg) |
1386 | { | |
1387 | u32 r; | |
1388 | ||
1389 | WREG32(PCIE_PORT_INDEX, ((reg) & 0xff)); | |
1390 | (void)RREG32(PCIE_PORT_INDEX); | |
1391 | r = RREG32(PCIE_PORT_DATA); | |
1392 | return r; | |
1393 | } | |
1394 | ||
1395 | void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v) | |
1396 | { | |
1397 | WREG32(PCIE_PORT_INDEX, ((reg) & 0xff)); | |
1398 | (void)RREG32(PCIE_PORT_INDEX); | |
1399 | WREG32(PCIE_PORT_DATA, (v)); | |
1400 | (void)RREG32(PCIE_PORT_DATA); | |
1401 | } | |
1402 | ||
3ce0a23d JG |
1403 | /* |
1404 | * CP & Ring | |
1405 | */ | |
1406 | void r600_cp_stop(struct radeon_device *rdev) | |
1407 | { | |
1408 | WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1)); | |
1409 | } | |
1410 | ||
d8f60cfc | 1411 | int r600_init_microcode(struct radeon_device *rdev) |
3ce0a23d JG |
1412 | { |
1413 | struct platform_device *pdev; | |
1414 | const char *chip_name; | |
d8f60cfc AD |
1415 | const char *rlc_chip_name; |
1416 | size_t pfp_req_size, me_req_size, rlc_req_size; | |
3ce0a23d JG |
1417 | char fw_name[30]; |
1418 | int err; | |
1419 | ||
1420 | DRM_DEBUG("\n"); | |
1421 | ||
1422 | pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0); | |
1423 | err = IS_ERR(pdev); | |
1424 | if (err) { | |
1425 | printk(KERN_ERR "radeon_cp: Failed to register firmware\n"); | |
1426 | return -EINVAL; | |
1427 | } | |
1428 | ||
1429 | switch (rdev->family) { | |
d8f60cfc AD |
1430 | case CHIP_R600: |
1431 | chip_name = "R600"; | |
1432 | rlc_chip_name = "R600"; | |
1433 | break; | |
1434 | case CHIP_RV610: | |
1435 | chip_name = "RV610"; | |
1436 | rlc_chip_name = "R600"; | |
1437 | break; | |
1438 | case CHIP_RV630: | |
1439 | chip_name = "RV630"; | |
1440 | rlc_chip_name = "R600"; | |
1441 | break; | |
1442 | case CHIP_RV620: | |
1443 | chip_name = "RV620"; | |
1444 | rlc_chip_name = "R600"; | |
1445 | break; | |
1446 | case CHIP_RV635: | |
1447 | chip_name = "RV635"; | |
1448 | rlc_chip_name = "R600"; | |
1449 | break; | |
1450 | case CHIP_RV670: | |
1451 | chip_name = "RV670"; | |
1452 | rlc_chip_name = "R600"; | |
1453 | break; | |
3ce0a23d | 1454 | case CHIP_RS780: |
d8f60cfc AD |
1455 | case CHIP_RS880: |
1456 | chip_name = "RS780"; | |
1457 | rlc_chip_name = "R600"; | |
1458 | break; | |
1459 | case CHIP_RV770: | |
1460 | chip_name = "RV770"; | |
1461 | rlc_chip_name = "R700"; | |
1462 | break; | |
3ce0a23d | 1463 | case CHIP_RV730: |
d8f60cfc AD |
1464 | case CHIP_RV740: |
1465 | chip_name = "RV730"; | |
1466 | rlc_chip_name = "R700"; | |
1467 | break; | |
1468 | case CHIP_RV710: | |
1469 | chip_name = "RV710"; | |
1470 | rlc_chip_name = "R700"; | |
1471 | break; | |
fe251e2f AD |
1472 | case CHIP_CEDAR: |
1473 | chip_name = "CEDAR"; | |
45f9a39b | 1474 | rlc_chip_name = "CEDAR"; |
fe251e2f AD |
1475 | break; |
1476 | case CHIP_REDWOOD: | |
1477 | chip_name = "REDWOOD"; | |
45f9a39b | 1478 | rlc_chip_name = "REDWOOD"; |
fe251e2f AD |
1479 | break; |
1480 | case CHIP_JUNIPER: | |
1481 | chip_name = "JUNIPER"; | |
45f9a39b | 1482 | rlc_chip_name = "JUNIPER"; |
fe251e2f AD |
1483 | break; |
1484 | case CHIP_CYPRESS: | |
1485 | case CHIP_HEMLOCK: | |
1486 | chip_name = "CYPRESS"; | |
45f9a39b | 1487 | rlc_chip_name = "CYPRESS"; |
fe251e2f | 1488 | break; |
3ce0a23d JG |
1489 | default: BUG(); |
1490 | } | |
1491 | ||
fe251e2f AD |
1492 | if (rdev->family >= CHIP_CEDAR) { |
1493 | pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4; | |
1494 | me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4; | |
45f9a39b | 1495 | rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4; |
fe251e2f | 1496 | } else if (rdev->family >= CHIP_RV770) { |
3ce0a23d JG |
1497 | pfp_req_size = R700_PFP_UCODE_SIZE * 4; |
1498 | me_req_size = R700_PM4_UCODE_SIZE * 4; | |
d8f60cfc | 1499 | rlc_req_size = R700_RLC_UCODE_SIZE * 4; |
3ce0a23d JG |
1500 | } else { |
1501 | pfp_req_size = PFP_UCODE_SIZE * 4; | |
1502 | me_req_size = PM4_UCODE_SIZE * 12; | |
d8f60cfc | 1503 | rlc_req_size = RLC_UCODE_SIZE * 4; |
3ce0a23d JG |
1504 | } |
1505 | ||
d8f60cfc | 1506 | DRM_INFO("Loading %s Microcode\n", chip_name); |
3ce0a23d JG |
1507 | |
1508 | snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name); | |
1509 | err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev); | |
1510 | if (err) | |
1511 | goto out; | |
1512 | if (rdev->pfp_fw->size != pfp_req_size) { | |
1513 | printk(KERN_ERR | |
1514 | "r600_cp: Bogus length %zu in firmware \"%s\"\n", | |
1515 | rdev->pfp_fw->size, fw_name); | |
1516 | err = -EINVAL; | |
1517 | goto out; | |
1518 | } | |
1519 | ||
1520 | snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name); | |
1521 | err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev); | |
1522 | if (err) | |
1523 | goto out; | |
1524 | if (rdev->me_fw->size != me_req_size) { | |
1525 | printk(KERN_ERR | |
1526 | "r600_cp: Bogus length %zu in firmware \"%s\"\n", | |
1527 | rdev->me_fw->size, fw_name); | |
1528 | err = -EINVAL; | |
1529 | } | |
d8f60cfc AD |
1530 | |
1531 | snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name); | |
1532 | err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev); | |
1533 | if (err) | |
1534 | goto out; | |
1535 | if (rdev->rlc_fw->size != rlc_req_size) { | |
1536 | printk(KERN_ERR | |
1537 | "r600_rlc: Bogus length %zu in firmware \"%s\"\n", | |
1538 | rdev->rlc_fw->size, fw_name); | |
1539 | err = -EINVAL; | |
1540 | } | |
1541 | ||
3ce0a23d JG |
1542 | out: |
1543 | platform_device_unregister(pdev); | |
1544 | ||
1545 | if (err) { | |
1546 | if (err != -EINVAL) | |
1547 | printk(KERN_ERR | |
1548 | "r600_cp: Failed to load firmware \"%s\"\n", | |
1549 | fw_name); | |
1550 | release_firmware(rdev->pfp_fw); | |
1551 | rdev->pfp_fw = NULL; | |
1552 | release_firmware(rdev->me_fw); | |
1553 | rdev->me_fw = NULL; | |
d8f60cfc AD |
1554 | release_firmware(rdev->rlc_fw); |
1555 | rdev->rlc_fw = NULL; | |
3ce0a23d JG |
1556 | } |
1557 | return err; | |
1558 | } | |
1559 | ||
1560 | static int r600_cp_load_microcode(struct radeon_device *rdev) | |
1561 | { | |
1562 | const __be32 *fw_data; | |
1563 | int i; | |
1564 | ||
1565 | if (!rdev->me_fw || !rdev->pfp_fw) | |
1566 | return -EINVAL; | |
1567 | ||
1568 | r600_cp_stop(rdev); | |
1569 | ||
1570 | WREG32(CP_RB_CNTL, RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3)); | |
1571 | ||
1572 | /* Reset cp */ | |
1573 | WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); | |
1574 | RREG32(GRBM_SOFT_RESET); | |
1575 | mdelay(15); | |
1576 | WREG32(GRBM_SOFT_RESET, 0); | |
1577 | ||
1578 | WREG32(CP_ME_RAM_WADDR, 0); | |
1579 | ||
1580 | fw_data = (const __be32 *)rdev->me_fw->data; | |
1581 | WREG32(CP_ME_RAM_WADDR, 0); | |
1582 | for (i = 0; i < PM4_UCODE_SIZE * 3; i++) | |
1583 | WREG32(CP_ME_RAM_DATA, | |
1584 | be32_to_cpup(fw_data++)); | |
1585 | ||
1586 | fw_data = (const __be32 *)rdev->pfp_fw->data; | |
1587 | WREG32(CP_PFP_UCODE_ADDR, 0); | |
1588 | for (i = 0; i < PFP_UCODE_SIZE; i++) | |
1589 | WREG32(CP_PFP_UCODE_DATA, | |
1590 | be32_to_cpup(fw_data++)); | |
1591 | ||
1592 | WREG32(CP_PFP_UCODE_ADDR, 0); | |
1593 | WREG32(CP_ME_RAM_WADDR, 0); | |
1594 | WREG32(CP_ME_RAM_RADDR, 0); | |
1595 | return 0; | |
1596 | } | |
1597 | ||
1598 | int r600_cp_start(struct radeon_device *rdev) | |
1599 | { | |
1600 | int r; | |
1601 | uint32_t cp_me; | |
1602 | ||
1603 | r = radeon_ring_lock(rdev, 7); | |
1604 | if (r) { | |
1605 | DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); | |
1606 | return r; | |
1607 | } | |
1608 | radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5)); | |
1609 | radeon_ring_write(rdev, 0x1); | |
fe251e2f AD |
1610 | if (rdev->family >= CHIP_CEDAR) { |
1611 | radeon_ring_write(rdev, 0x0); | |
1612 | radeon_ring_write(rdev, rdev->config.evergreen.max_hw_contexts - 1); | |
1613 | } else if (rdev->family >= CHIP_RV770) { | |
3ce0a23d JG |
1614 | radeon_ring_write(rdev, 0x0); |
1615 | radeon_ring_write(rdev, rdev->config.rv770.max_hw_contexts - 1); | |
fe251e2f AD |
1616 | } else { |
1617 | radeon_ring_write(rdev, 0x3); | |
1618 | radeon_ring_write(rdev, rdev->config.r600.max_hw_contexts - 1); | |
3ce0a23d JG |
1619 | } |
1620 | radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1)); | |
1621 | radeon_ring_write(rdev, 0); | |
1622 | radeon_ring_write(rdev, 0); | |
1623 | radeon_ring_unlock_commit(rdev); | |
1624 | ||
1625 | cp_me = 0xff; | |
1626 | WREG32(R_0086D8_CP_ME_CNTL, cp_me); | |
1627 | return 0; | |
1628 | } | |
1629 | ||
1630 | int r600_cp_resume(struct radeon_device *rdev) | |
1631 | { | |
1632 | u32 tmp; | |
1633 | u32 rb_bufsz; | |
1634 | int r; | |
1635 | ||
1636 | /* Reset cp */ | |
1637 | WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); | |
1638 | RREG32(GRBM_SOFT_RESET); | |
1639 | mdelay(15); | |
1640 | WREG32(GRBM_SOFT_RESET, 0); | |
1641 | ||
1642 | /* Set ring buffer size */ | |
1643 | rb_bufsz = drm_order(rdev->cp.ring_size / 8); | |
d6f28938 | 1644 | tmp = RB_NO_UPDATE | (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; |
3ce0a23d | 1645 | #ifdef __BIG_ENDIAN |
d6f28938 | 1646 | tmp |= BUF_SWAP_32BIT; |
3ce0a23d | 1647 | #endif |
d6f28938 | 1648 | WREG32(CP_RB_CNTL, tmp); |
3ce0a23d JG |
1649 | WREG32(CP_SEM_WAIT_TIMER, 0x4); |
1650 | ||
1651 | /* Set the write pointer delay */ | |
1652 | WREG32(CP_RB_WPTR_DELAY, 0); | |
1653 | ||
1654 | /* Initialize the ring buffer's read and write pointers */ | |
3ce0a23d JG |
1655 | WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA); |
1656 | WREG32(CP_RB_RPTR_WR, 0); | |
1657 | WREG32(CP_RB_WPTR, 0); | |
1658 | WREG32(CP_RB_RPTR_ADDR, rdev->cp.gpu_addr & 0xFFFFFFFF); | |
1659 | WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->cp.gpu_addr)); | |
1660 | mdelay(1); | |
1661 | WREG32(CP_RB_CNTL, tmp); | |
1662 | ||
1663 | WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8); | |
1664 | WREG32(CP_DEBUG, (1 << 27) | (1 << 28)); | |
1665 | ||
1666 | rdev->cp.rptr = RREG32(CP_RB_RPTR); | |
1667 | rdev->cp.wptr = RREG32(CP_RB_WPTR); | |
1668 | ||
1669 | r600_cp_start(rdev); | |
1670 | rdev->cp.ready = true; | |
1671 | r = radeon_ring_test(rdev); | |
1672 | if (r) { | |
1673 | rdev->cp.ready = false; | |
1674 | return r; | |
1675 | } | |
1676 | return 0; | |
1677 | } | |
1678 | ||
1679 | void r600_cp_commit(struct radeon_device *rdev) | |
1680 | { | |
1681 | WREG32(CP_RB_WPTR, rdev->cp.wptr); | |
1682 | (void)RREG32(CP_RB_WPTR); | |
1683 | } | |
1684 | ||
1685 | void r600_ring_init(struct radeon_device *rdev, unsigned ring_size) | |
1686 | { | |
1687 | u32 rb_bufsz; | |
1688 | ||
1689 | /* Align ring size */ | |
1690 | rb_bufsz = drm_order(ring_size / 8); | |
1691 | ring_size = (1 << (rb_bufsz + 1)) * 4; | |
1692 | rdev->cp.ring_size = ring_size; | |
1693 | rdev->cp.align_mask = 16 - 1; | |
1694 | } | |
1695 | ||
655efd3d JG |
1696 | void r600_cp_fini(struct radeon_device *rdev) |
1697 | { | |
1698 | r600_cp_stop(rdev); | |
1699 | radeon_ring_fini(rdev); | |
1700 | } | |
1701 | ||
3ce0a23d JG |
1702 | |
1703 | /* | |
1704 | * GPU scratch registers helpers function. | |
1705 | */ | |
1706 | void r600_scratch_init(struct radeon_device *rdev) | |
1707 | { | |
1708 | int i; | |
1709 | ||
1710 | rdev->scratch.num_reg = 7; | |
1711 | for (i = 0; i < rdev->scratch.num_reg; i++) { | |
1712 | rdev->scratch.free[i] = true; | |
1713 | rdev->scratch.reg[i] = SCRATCH_REG0 + (i * 4); | |
1714 | } | |
1715 | } | |
1716 | ||
1717 | int r600_ring_test(struct radeon_device *rdev) | |
1718 | { | |
1719 | uint32_t scratch; | |
1720 | uint32_t tmp = 0; | |
1721 | unsigned i; | |
1722 | int r; | |
1723 | ||
1724 | r = radeon_scratch_get(rdev, &scratch); | |
1725 | if (r) { | |
1726 | DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r); | |
1727 | return r; | |
1728 | } | |
1729 | WREG32(scratch, 0xCAFEDEAD); | |
1730 | r = radeon_ring_lock(rdev, 3); | |
1731 | if (r) { | |
1732 | DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); | |
1733 | radeon_scratch_free(rdev, scratch); | |
1734 | return r; | |
1735 | } | |
1736 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1)); | |
1737 | radeon_ring_write(rdev, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); | |
1738 | radeon_ring_write(rdev, 0xDEADBEEF); | |
1739 | radeon_ring_unlock_commit(rdev); | |
1740 | for (i = 0; i < rdev->usec_timeout; i++) { | |
1741 | tmp = RREG32(scratch); | |
1742 | if (tmp == 0xDEADBEEF) | |
1743 | break; | |
1744 | DRM_UDELAY(1); | |
1745 | } | |
1746 | if (i < rdev->usec_timeout) { | |
1747 | DRM_INFO("ring test succeeded in %d usecs\n", i); | |
1748 | } else { | |
1749 | DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n", | |
1750 | scratch, tmp); | |
1751 | r = -EINVAL; | |
1752 | } | |
1753 | radeon_scratch_free(rdev, scratch); | |
1754 | return r; | |
1755 | } | |
1756 | ||
81cc35bf JG |
1757 | void r600_wb_disable(struct radeon_device *rdev) |
1758 | { | |
4c788679 JG |
1759 | int r; |
1760 | ||
81cc35bf JG |
1761 | WREG32(SCRATCH_UMSK, 0); |
1762 | if (rdev->wb.wb_obj) { | |
4c788679 JG |
1763 | r = radeon_bo_reserve(rdev->wb.wb_obj, false); |
1764 | if (unlikely(r != 0)) | |
1765 | return; | |
1766 | radeon_bo_kunmap(rdev->wb.wb_obj); | |
1767 | radeon_bo_unpin(rdev->wb.wb_obj); | |
1768 | radeon_bo_unreserve(rdev->wb.wb_obj); | |
81cc35bf JG |
1769 | } |
1770 | } | |
1771 | ||
1772 | void r600_wb_fini(struct radeon_device *rdev) | |
1773 | { | |
1774 | r600_wb_disable(rdev); | |
1775 | if (rdev->wb.wb_obj) { | |
4c788679 | 1776 | radeon_bo_unref(&rdev->wb.wb_obj); |
81cc35bf JG |
1777 | rdev->wb.wb = NULL; |
1778 | rdev->wb.wb_obj = NULL; | |
1779 | } | |
1780 | } | |
1781 | ||
1782 | int r600_wb_enable(struct radeon_device *rdev) | |
3ce0a23d JG |
1783 | { |
1784 | int r; | |
1785 | ||
1786 | if (rdev->wb.wb_obj == NULL) { | |
4c788679 JG |
1787 | r = radeon_bo_create(rdev, NULL, RADEON_GPU_PAGE_SIZE, true, |
1788 | RADEON_GEM_DOMAIN_GTT, &rdev->wb.wb_obj); | |
3ce0a23d | 1789 | if (r) { |
4c788679 | 1790 | dev_warn(rdev->dev, "(%d) create WB bo failed\n", r); |
3ce0a23d JG |
1791 | return r; |
1792 | } | |
4c788679 JG |
1793 | r = radeon_bo_reserve(rdev->wb.wb_obj, false); |
1794 | if (unlikely(r != 0)) { | |
1795 | r600_wb_fini(rdev); | |
3ce0a23d JG |
1796 | return r; |
1797 | } | |
4c788679 | 1798 | r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT, |
81cc35bf | 1799 | &rdev->wb.gpu_addr); |
3ce0a23d | 1800 | if (r) { |
4c788679 JG |
1801 | radeon_bo_unreserve(rdev->wb.wb_obj); |
1802 | dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r); | |
81cc35bf | 1803 | r600_wb_fini(rdev); |
3ce0a23d JG |
1804 | return r; |
1805 | } | |
4c788679 JG |
1806 | r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb); |
1807 | radeon_bo_unreserve(rdev->wb.wb_obj); | |
3ce0a23d | 1808 | if (r) { |
4c788679 | 1809 | dev_warn(rdev->dev, "(%d) map WB bo failed\n", r); |
81cc35bf | 1810 | r600_wb_fini(rdev); |
3ce0a23d JG |
1811 | return r; |
1812 | } | |
1813 | } | |
1814 | WREG32(SCRATCH_ADDR, (rdev->wb.gpu_addr >> 8) & 0xFFFFFFFF); | |
1815 | WREG32(CP_RB_RPTR_ADDR, (rdev->wb.gpu_addr + 1024) & 0xFFFFFFFC); | |
1816 | WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + 1024) & 0xFF); | |
1817 | WREG32(SCRATCH_UMSK, 0xff); | |
1818 | return 0; | |
1819 | } | |
1820 | ||
3ce0a23d JG |
1821 | void r600_fence_ring_emit(struct radeon_device *rdev, |
1822 | struct radeon_fence *fence) | |
1823 | { | |
d8f60cfc | 1824 | /* Also consider EVENT_WRITE_EOP. it handles the interrupts + timestamps + events */ |
44224c3f AD |
1825 | |
1826 | radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE, 0)); | |
1827 | radeon_ring_write(rdev, CACHE_FLUSH_AND_INV_EVENT); | |
1828 | /* wait for 3D idle clean */ | |
1829 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1)); | |
1830 | radeon_ring_write(rdev, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); | |
1831 | radeon_ring_write(rdev, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit); | |
3ce0a23d JG |
1832 | /* Emit fence sequence & fire IRQ */ |
1833 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1)); | |
1834 | radeon_ring_write(rdev, ((rdev->fence_drv.scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); | |
1835 | radeon_ring_write(rdev, fence->seq); | |
d8f60cfc AD |
1836 | /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */ |
1837 | radeon_ring_write(rdev, PACKET0(CP_INT_STATUS, 0)); | |
1838 | radeon_ring_write(rdev, RB_INT_STAT); | |
3ce0a23d JG |
1839 | } |
1840 | ||
3ce0a23d JG |
1841 | int r600_copy_blit(struct radeon_device *rdev, |
1842 | uint64_t src_offset, uint64_t dst_offset, | |
1843 | unsigned num_pages, struct radeon_fence *fence) | |
1844 | { | |
ff82f052 JG |
1845 | int r; |
1846 | ||
1847 | mutex_lock(&rdev->r600_blit.mutex); | |
1848 | rdev->r600_blit.vb_ib = NULL; | |
1849 | r = r600_blit_prepare_copy(rdev, num_pages * RADEON_GPU_PAGE_SIZE); | |
1850 | if (r) { | |
1851 | if (rdev->r600_blit.vb_ib) | |
1852 | radeon_ib_free(rdev, &rdev->r600_blit.vb_ib); | |
1853 | mutex_unlock(&rdev->r600_blit.mutex); | |
1854 | return r; | |
1855 | } | |
a77f1718 | 1856 | r600_kms_blit_copy(rdev, src_offset, dst_offset, num_pages * RADEON_GPU_PAGE_SIZE); |
3ce0a23d | 1857 | r600_blit_done_copy(rdev, fence); |
ff82f052 | 1858 | mutex_unlock(&rdev->r600_blit.mutex); |
3ce0a23d JG |
1859 | return 0; |
1860 | } | |
1861 | ||
3ce0a23d JG |
1862 | int r600_set_surface_reg(struct radeon_device *rdev, int reg, |
1863 | uint32_t tiling_flags, uint32_t pitch, | |
1864 | uint32_t offset, uint32_t obj_size) | |
1865 | { | |
1866 | /* FIXME: implement */ | |
1867 | return 0; | |
1868 | } | |
1869 | ||
1870 | void r600_clear_surface_reg(struct radeon_device *rdev, int reg) | |
1871 | { | |
1872 | /* FIXME: implement */ | |
1873 | } | |
1874 | ||
1875 | ||
1876 | bool r600_card_posted(struct radeon_device *rdev) | |
1877 | { | |
1878 | uint32_t reg; | |
1879 | ||
1880 | /* first check CRTCs */ | |
1881 | reg = RREG32(D1CRTC_CONTROL) | | |
1882 | RREG32(D2CRTC_CONTROL); | |
1883 | if (reg & CRTC_EN) | |
1884 | return true; | |
1885 | ||
1886 | /* then check MEM_SIZE, in case the crtcs are off */ | |
1887 | if (RREG32(CONFIG_MEMSIZE)) | |
1888 | return true; | |
1889 | ||
1890 | return false; | |
1891 | } | |
1892 | ||
fc30b8ef | 1893 | int r600_startup(struct radeon_device *rdev) |
3ce0a23d JG |
1894 | { |
1895 | int r; | |
1896 | ||
779720a3 AD |
1897 | if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) { |
1898 | r = r600_init_microcode(rdev); | |
1899 | if (r) { | |
1900 | DRM_ERROR("Failed to load firmware!\n"); | |
1901 | return r; | |
1902 | } | |
1903 | } | |
1904 | ||
a3c1945a | 1905 | r600_mc_program(rdev); |
1a029b76 JG |
1906 | if (rdev->flags & RADEON_IS_AGP) { |
1907 | r600_agp_enable(rdev); | |
1908 | } else { | |
1909 | r = r600_pcie_gart_enable(rdev); | |
1910 | if (r) | |
1911 | return r; | |
1912 | } | |
3ce0a23d | 1913 | r600_gpu_init(rdev); |
c38c7b64 JG |
1914 | r = r600_blit_init(rdev); |
1915 | if (r) { | |
1916 | r600_blit_fini(rdev); | |
1917 | rdev->asic->copy = NULL; | |
1918 | dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r); | |
1919 | } | |
ff82f052 JG |
1920 | /* pin copy shader into vram */ |
1921 | if (rdev->r600_blit.shader_obj) { | |
1922 | r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false); | |
1923 | if (unlikely(r != 0)) | |
1924 | return r; | |
1925 | r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM, | |
1926 | &rdev->r600_blit.shader_gpu_addr); | |
1927 | radeon_bo_unreserve(rdev->r600_blit.shader_obj); | |
7923c615 | 1928 | if (r) { |
ff82f052 | 1929 | dev_err(rdev->dev, "(%d) pin blit object failed\n", r); |
7923c615 AD |
1930 | return r; |
1931 | } | |
1932 | } | |
d8f60cfc | 1933 | /* Enable IRQ */ |
d8f60cfc AD |
1934 | r = r600_irq_init(rdev); |
1935 | if (r) { | |
1936 | DRM_ERROR("radeon: IH init failed (%d).\n", r); | |
1937 | radeon_irq_kms_fini(rdev); | |
1938 | return r; | |
1939 | } | |
1940 | r600_irq_set(rdev); | |
1941 | ||
3ce0a23d JG |
1942 | r = radeon_ring_init(rdev, rdev->cp.ring_size); |
1943 | if (r) | |
1944 | return r; | |
1945 | r = r600_cp_load_microcode(rdev); | |
1946 | if (r) | |
1947 | return r; | |
1948 | r = r600_cp_resume(rdev); | |
1949 | if (r) | |
1950 | return r; | |
81cc35bf JG |
1951 | /* write back buffer are not vital so don't worry about failure */ |
1952 | r600_wb_enable(rdev); | |
3ce0a23d JG |
1953 | return 0; |
1954 | } | |
1955 | ||
28d52043 DA |
1956 | void r600_vga_set_state(struct radeon_device *rdev, bool state) |
1957 | { | |
1958 | uint32_t temp; | |
1959 | ||
1960 | temp = RREG32(CONFIG_CNTL); | |
1961 | if (state == false) { | |
1962 | temp &= ~(1<<0); | |
1963 | temp |= (1<<1); | |
1964 | } else { | |
1965 | temp &= ~(1<<1); | |
1966 | } | |
1967 | WREG32(CONFIG_CNTL, temp); | |
1968 | } | |
1969 | ||
fc30b8ef DA |
1970 | int r600_resume(struct radeon_device *rdev) |
1971 | { | |
1972 | int r; | |
1973 | ||
1a029b76 JG |
1974 | /* Do not reset GPU before posting, on r600 hw unlike on r500 hw, |
1975 | * posting will perform necessary task to bring back GPU into good | |
1976 | * shape. | |
1977 | */ | |
fc30b8ef | 1978 | /* post card */ |
e7d40b9a | 1979 | atom_asic_init(rdev->mode_info.atom_context); |
fc30b8ef DA |
1980 | /* Initialize clocks */ |
1981 | r = radeon_clocks_init(rdev); | |
1982 | if (r) { | |
1983 | return r; | |
1984 | } | |
1985 | ||
1986 | r = r600_startup(rdev); | |
1987 | if (r) { | |
1988 | DRM_ERROR("r600 startup failed on resume\n"); | |
1989 | return r; | |
1990 | } | |
1991 | ||
62a8ea3f | 1992 | r = r600_ib_test(rdev); |
fc30b8ef DA |
1993 | if (r) { |
1994 | DRM_ERROR("radeon: failled testing IB (%d).\n", r); | |
1995 | return r; | |
1996 | } | |
38fd2c6f RM |
1997 | |
1998 | r = r600_audio_init(rdev); | |
1999 | if (r) { | |
2000 | DRM_ERROR("radeon: audio resume failed\n"); | |
2001 | return r; | |
2002 | } | |
2003 | ||
fc30b8ef DA |
2004 | return r; |
2005 | } | |
2006 | ||
3ce0a23d JG |
2007 | int r600_suspend(struct radeon_device *rdev) |
2008 | { | |
4c788679 JG |
2009 | int r; |
2010 | ||
38fd2c6f | 2011 | r600_audio_fini(rdev); |
3ce0a23d JG |
2012 | /* FIXME: we should wait for ring to be empty */ |
2013 | r600_cp_stop(rdev); | |
bc1a631e | 2014 | rdev->cp.ready = false; |
0c45249f | 2015 | r600_irq_suspend(rdev); |
81cc35bf | 2016 | r600_wb_disable(rdev); |
4aac0473 | 2017 | r600_pcie_gart_disable(rdev); |
bc1a631e | 2018 | /* unpin shaders bo */ |
30d2d9a5 JG |
2019 | if (rdev->r600_blit.shader_obj) { |
2020 | r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false); | |
2021 | if (!r) { | |
2022 | radeon_bo_unpin(rdev->r600_blit.shader_obj); | |
2023 | radeon_bo_unreserve(rdev->r600_blit.shader_obj); | |
2024 | } | |
2025 | } | |
3ce0a23d JG |
2026 | return 0; |
2027 | } | |
2028 | ||
2029 | /* Plan is to move initialization in that function and use | |
2030 | * helper function so that radeon_device_init pretty much | |
2031 | * do nothing more than calling asic specific function. This | |
2032 | * should also allow to remove a bunch of callback function | |
2033 | * like vram_info. | |
2034 | */ | |
2035 | int r600_init(struct radeon_device *rdev) | |
771fe6b9 | 2036 | { |
3ce0a23d | 2037 | int r; |
771fe6b9 | 2038 | |
3ce0a23d JG |
2039 | r = radeon_dummy_page_init(rdev); |
2040 | if (r) | |
2041 | return r; | |
2042 | if (r600_debugfs_mc_info_init(rdev)) { | |
2043 | DRM_ERROR("Failed to register debugfs file for mc !\n"); | |
2044 | } | |
2045 | /* This don't do much */ | |
2046 | r = radeon_gem_init(rdev); | |
2047 | if (r) | |
2048 | return r; | |
2049 | /* Read BIOS */ | |
2050 | if (!radeon_get_bios(rdev)) { | |
2051 | if (ASIC_IS_AVIVO(rdev)) | |
2052 | return -EINVAL; | |
2053 | } | |
2054 | /* Must be an ATOMBIOS */ | |
e7d40b9a JG |
2055 | if (!rdev->is_atom_bios) { |
2056 | dev_err(rdev->dev, "Expecting atombios for R600 GPU\n"); | |
3ce0a23d | 2057 | return -EINVAL; |
e7d40b9a | 2058 | } |
3ce0a23d JG |
2059 | r = radeon_atombios_init(rdev); |
2060 | if (r) | |
2061 | return r; | |
2062 | /* Post card if necessary */ | |
72542d77 DA |
2063 | if (!r600_card_posted(rdev)) { |
2064 | if (!rdev->bios) { | |
2065 | dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); | |
2066 | return -EINVAL; | |
2067 | } | |
3ce0a23d JG |
2068 | DRM_INFO("GPU not posted. posting now...\n"); |
2069 | atom_asic_init(rdev->mode_info.atom_context); | |
2070 | } | |
2071 | /* Initialize scratch registers */ | |
2072 | r600_scratch_init(rdev); | |
2073 | /* Initialize surface registers */ | |
2074 | radeon_surface_init(rdev); | |
7433874e | 2075 | /* Initialize clocks */ |
5e6dde7e | 2076 | radeon_get_clock_info(rdev->ddev); |
3ce0a23d JG |
2077 | r = radeon_clocks_init(rdev); |
2078 | if (r) | |
2079 | return r; | |
7433874e RM |
2080 | /* Initialize power management */ |
2081 | radeon_pm_init(rdev); | |
3ce0a23d JG |
2082 | /* Fence driver */ |
2083 | r = radeon_fence_driver_init(rdev); | |
2084 | if (r) | |
2085 | return r; | |
700a0cc0 JG |
2086 | if (rdev->flags & RADEON_IS_AGP) { |
2087 | r = radeon_agp_init(rdev); | |
2088 | if (r) | |
2089 | radeon_agp_disable(rdev); | |
2090 | } | |
3ce0a23d | 2091 | r = r600_mc_init(rdev); |
b574f251 | 2092 | if (r) |
3ce0a23d | 2093 | return r; |
3ce0a23d | 2094 | /* Memory manager */ |
4c788679 | 2095 | r = radeon_bo_init(rdev); |
3ce0a23d JG |
2096 | if (r) |
2097 | return r; | |
d8f60cfc AD |
2098 | |
2099 | r = radeon_irq_kms_init(rdev); | |
2100 | if (r) | |
2101 | return r; | |
2102 | ||
3ce0a23d JG |
2103 | rdev->cp.ring_obj = NULL; |
2104 | r600_ring_init(rdev, 1024 * 1024); | |
2105 | ||
d8f60cfc AD |
2106 | rdev->ih.ring_obj = NULL; |
2107 | r600_ih_ring_init(rdev, 64 * 1024); | |
3ce0a23d | 2108 | |
4aac0473 JG |
2109 | r = r600_pcie_gart_init(rdev); |
2110 | if (r) | |
2111 | return r; | |
2112 | ||
779720a3 | 2113 | rdev->accel_working = true; |
fc30b8ef | 2114 | r = r600_startup(rdev); |
3ce0a23d | 2115 | if (r) { |
655efd3d JG |
2116 | dev_err(rdev->dev, "disabling GPU acceleration\n"); |
2117 | r600_cp_fini(rdev); | |
75c81298 | 2118 | r600_wb_fini(rdev); |
655efd3d JG |
2119 | r600_irq_fini(rdev); |
2120 | radeon_irq_kms_fini(rdev); | |
75c81298 | 2121 | r600_pcie_gart_fini(rdev); |
733289c2 | 2122 | rdev->accel_working = false; |
3ce0a23d | 2123 | } |
733289c2 JG |
2124 | if (rdev->accel_working) { |
2125 | r = radeon_ib_pool_init(rdev); | |
2126 | if (r) { | |
db96380e | 2127 | dev_err(rdev->dev, "IB initialization failed (%d).\n", r); |
733289c2 | 2128 | rdev->accel_working = false; |
db96380e JG |
2129 | } else { |
2130 | r = r600_ib_test(rdev); | |
2131 | if (r) { | |
2132 | dev_err(rdev->dev, "IB test failed (%d).\n", r); | |
2133 | rdev->accel_working = false; | |
2134 | } | |
733289c2 | 2135 | } |
3ce0a23d | 2136 | } |
dafc3bd5 CK |
2137 | |
2138 | r = r600_audio_init(rdev); | |
2139 | if (r) | |
2140 | return r; /* TODO error handling */ | |
3ce0a23d JG |
2141 | return 0; |
2142 | } | |
2143 | ||
2144 | void r600_fini(struct radeon_device *rdev) | |
2145 | { | |
29fb52ca | 2146 | radeon_pm_fini(rdev); |
dafc3bd5 | 2147 | r600_audio_fini(rdev); |
3ce0a23d | 2148 | r600_blit_fini(rdev); |
655efd3d JG |
2149 | r600_cp_fini(rdev); |
2150 | r600_wb_fini(rdev); | |
d8f60cfc AD |
2151 | r600_irq_fini(rdev); |
2152 | radeon_irq_kms_fini(rdev); | |
4aac0473 | 2153 | r600_pcie_gart_fini(rdev); |
655efd3d | 2154 | radeon_agp_fini(rdev); |
3ce0a23d JG |
2155 | radeon_gem_fini(rdev); |
2156 | radeon_fence_driver_fini(rdev); | |
2157 | radeon_clocks_fini(rdev); | |
4c788679 | 2158 | radeon_bo_fini(rdev); |
e7d40b9a | 2159 | radeon_atombios_fini(rdev); |
3ce0a23d JG |
2160 | kfree(rdev->bios); |
2161 | rdev->bios = NULL; | |
2162 | radeon_dummy_page_fini(rdev); | |
2163 | } | |
2164 | ||
2165 | ||
2166 | /* | |
2167 | * CS stuff | |
2168 | */ | |
2169 | void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) | |
2170 | { | |
2171 | /* FIXME: implement */ | |
2172 | radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); | |
2173 | radeon_ring_write(rdev, ib->gpu_addr & 0xFFFFFFFC); | |
2174 | radeon_ring_write(rdev, upper_32_bits(ib->gpu_addr) & 0xFF); | |
2175 | radeon_ring_write(rdev, ib->length_dw); | |
2176 | } | |
2177 | ||
2178 | int r600_ib_test(struct radeon_device *rdev) | |
2179 | { | |
2180 | struct radeon_ib *ib; | |
2181 | uint32_t scratch; | |
2182 | uint32_t tmp = 0; | |
2183 | unsigned i; | |
2184 | int r; | |
2185 | ||
2186 | r = radeon_scratch_get(rdev, &scratch); | |
2187 | if (r) { | |
2188 | DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r); | |
2189 | return r; | |
2190 | } | |
2191 | WREG32(scratch, 0xCAFEDEAD); | |
2192 | r = radeon_ib_get(rdev, &ib); | |
2193 | if (r) { | |
2194 | DRM_ERROR("radeon: failed to get ib (%d).\n", r); | |
2195 | return r; | |
2196 | } | |
2197 | ib->ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1); | |
2198 | ib->ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); | |
2199 | ib->ptr[2] = 0xDEADBEEF; | |
2200 | ib->ptr[3] = PACKET2(0); | |
2201 | ib->ptr[4] = PACKET2(0); | |
2202 | ib->ptr[5] = PACKET2(0); | |
2203 | ib->ptr[6] = PACKET2(0); | |
2204 | ib->ptr[7] = PACKET2(0); | |
2205 | ib->ptr[8] = PACKET2(0); | |
2206 | ib->ptr[9] = PACKET2(0); | |
2207 | ib->ptr[10] = PACKET2(0); | |
2208 | ib->ptr[11] = PACKET2(0); | |
2209 | ib->ptr[12] = PACKET2(0); | |
2210 | ib->ptr[13] = PACKET2(0); | |
2211 | ib->ptr[14] = PACKET2(0); | |
2212 | ib->ptr[15] = PACKET2(0); | |
2213 | ib->length_dw = 16; | |
2214 | r = radeon_ib_schedule(rdev, ib); | |
2215 | if (r) { | |
2216 | radeon_scratch_free(rdev, scratch); | |
2217 | radeon_ib_free(rdev, &ib); | |
2218 | DRM_ERROR("radeon: failed to schedule ib (%d).\n", r); | |
2219 | return r; | |
2220 | } | |
2221 | r = radeon_fence_wait(ib->fence, false); | |
2222 | if (r) { | |
2223 | DRM_ERROR("radeon: fence wait failed (%d).\n", r); | |
2224 | return r; | |
2225 | } | |
2226 | for (i = 0; i < rdev->usec_timeout; i++) { | |
2227 | tmp = RREG32(scratch); | |
2228 | if (tmp == 0xDEADBEEF) | |
2229 | break; | |
2230 | DRM_UDELAY(1); | |
2231 | } | |
2232 | if (i < rdev->usec_timeout) { | |
2233 | DRM_INFO("ib test succeeded in %u usecs\n", i); | |
2234 | } else { | |
2235 | DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n", | |
2236 | scratch, tmp); | |
2237 | r = -EINVAL; | |
2238 | } | |
2239 | radeon_scratch_free(rdev, scratch); | |
2240 | radeon_ib_free(rdev, &ib); | |
771fe6b9 JG |
2241 | return r; |
2242 | } | |
2243 | ||
d8f60cfc AD |
2244 | /* |
2245 | * Interrupts | |
2246 | * | |
2247 | * Interrupts use a ring buffer on r6xx/r7xx hardware. It works pretty | |
2248 | * the same as the CP ring buffer, but in reverse. Rather than the CPU | |
2249 | * writing to the ring and the GPU consuming, the GPU writes to the ring | |
2250 | * and host consumes. As the host irq handler processes interrupts, it | |
2251 | * increments the rptr. When the rptr catches up with the wptr, all the | |
2252 | * current interrupts have been processed. | |
2253 | */ | |
2254 | ||
2255 | void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size) | |
2256 | { | |
2257 | u32 rb_bufsz; | |
2258 | ||
2259 | /* Align ring size */ | |
2260 | rb_bufsz = drm_order(ring_size / 4); | |
2261 | ring_size = (1 << rb_bufsz) * 4; | |
2262 | rdev->ih.ring_size = ring_size; | |
0c45249f JG |
2263 | rdev->ih.ptr_mask = rdev->ih.ring_size - 1; |
2264 | rdev->ih.rptr = 0; | |
d8f60cfc AD |
2265 | } |
2266 | ||
0c45249f | 2267 | static int r600_ih_ring_alloc(struct radeon_device *rdev) |
d8f60cfc AD |
2268 | { |
2269 | int r; | |
2270 | ||
d8f60cfc AD |
2271 | /* Allocate ring buffer */ |
2272 | if (rdev->ih.ring_obj == NULL) { | |
4c788679 JG |
2273 | r = radeon_bo_create(rdev, NULL, rdev->ih.ring_size, |
2274 | true, | |
2275 | RADEON_GEM_DOMAIN_GTT, | |
2276 | &rdev->ih.ring_obj); | |
d8f60cfc AD |
2277 | if (r) { |
2278 | DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r); | |
2279 | return r; | |
2280 | } | |
4c788679 JG |
2281 | r = radeon_bo_reserve(rdev->ih.ring_obj, false); |
2282 | if (unlikely(r != 0)) | |
2283 | return r; | |
2284 | r = radeon_bo_pin(rdev->ih.ring_obj, | |
2285 | RADEON_GEM_DOMAIN_GTT, | |
2286 | &rdev->ih.gpu_addr); | |
d8f60cfc | 2287 | if (r) { |
4c788679 | 2288 | radeon_bo_unreserve(rdev->ih.ring_obj); |
d8f60cfc AD |
2289 | DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r); |
2290 | return r; | |
2291 | } | |
4c788679 JG |
2292 | r = radeon_bo_kmap(rdev->ih.ring_obj, |
2293 | (void **)&rdev->ih.ring); | |
2294 | radeon_bo_unreserve(rdev->ih.ring_obj); | |
d8f60cfc AD |
2295 | if (r) { |
2296 | DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r); | |
2297 | return r; | |
2298 | } | |
2299 | } | |
d8f60cfc AD |
2300 | return 0; |
2301 | } | |
2302 | ||
2303 | static void r600_ih_ring_fini(struct radeon_device *rdev) | |
2304 | { | |
4c788679 | 2305 | int r; |
d8f60cfc | 2306 | if (rdev->ih.ring_obj) { |
4c788679 JG |
2307 | r = radeon_bo_reserve(rdev->ih.ring_obj, false); |
2308 | if (likely(r == 0)) { | |
2309 | radeon_bo_kunmap(rdev->ih.ring_obj); | |
2310 | radeon_bo_unpin(rdev->ih.ring_obj); | |
2311 | radeon_bo_unreserve(rdev->ih.ring_obj); | |
2312 | } | |
2313 | radeon_bo_unref(&rdev->ih.ring_obj); | |
d8f60cfc AD |
2314 | rdev->ih.ring = NULL; |
2315 | rdev->ih.ring_obj = NULL; | |
2316 | } | |
2317 | } | |
2318 | ||
45f9a39b | 2319 | void r600_rlc_stop(struct radeon_device *rdev) |
d8f60cfc AD |
2320 | { |
2321 | ||
45f9a39b AD |
2322 | if ((rdev->family >= CHIP_RV770) && |
2323 | (rdev->family <= CHIP_RV740)) { | |
d8f60cfc AD |
2324 | /* r7xx asics need to soft reset RLC before halting */ |
2325 | WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC); | |
2326 | RREG32(SRBM_SOFT_RESET); | |
2327 | udelay(15000); | |
2328 | WREG32(SRBM_SOFT_RESET, 0); | |
2329 | RREG32(SRBM_SOFT_RESET); | |
2330 | } | |
2331 | ||
2332 | WREG32(RLC_CNTL, 0); | |
2333 | } | |
2334 | ||
2335 | static void r600_rlc_start(struct radeon_device *rdev) | |
2336 | { | |
2337 | WREG32(RLC_CNTL, RLC_ENABLE); | |
2338 | } | |
2339 | ||
2340 | static int r600_rlc_init(struct radeon_device *rdev) | |
2341 | { | |
2342 | u32 i; | |
2343 | const __be32 *fw_data; | |
2344 | ||
2345 | if (!rdev->rlc_fw) | |
2346 | return -EINVAL; | |
2347 | ||
2348 | r600_rlc_stop(rdev); | |
2349 | ||
2350 | WREG32(RLC_HB_BASE, 0); | |
2351 | WREG32(RLC_HB_CNTL, 0); | |
2352 | WREG32(RLC_HB_RPTR, 0); | |
2353 | WREG32(RLC_HB_WPTR, 0); | |
2354 | WREG32(RLC_HB_WPTR_LSB_ADDR, 0); | |
2355 | WREG32(RLC_HB_WPTR_MSB_ADDR, 0); | |
2356 | WREG32(RLC_MC_CNTL, 0); | |
2357 | WREG32(RLC_UCODE_CNTL, 0); | |
2358 | ||
2359 | fw_data = (const __be32 *)rdev->rlc_fw->data; | |
45f9a39b AD |
2360 | if (rdev->family >= CHIP_CEDAR) { |
2361 | for (i = 0; i < EVERGREEN_RLC_UCODE_SIZE; i++) { | |
2362 | WREG32(RLC_UCODE_ADDR, i); | |
2363 | WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); | |
2364 | } | |
2365 | } else if (rdev->family >= CHIP_RV770) { | |
d8f60cfc AD |
2366 | for (i = 0; i < R700_RLC_UCODE_SIZE; i++) { |
2367 | WREG32(RLC_UCODE_ADDR, i); | |
2368 | WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); | |
2369 | } | |
2370 | } else { | |
2371 | for (i = 0; i < RLC_UCODE_SIZE; i++) { | |
2372 | WREG32(RLC_UCODE_ADDR, i); | |
2373 | WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); | |
2374 | } | |
2375 | } | |
2376 | WREG32(RLC_UCODE_ADDR, 0); | |
2377 | ||
2378 | r600_rlc_start(rdev); | |
2379 | ||
2380 | return 0; | |
2381 | } | |
2382 | ||
2383 | static void r600_enable_interrupts(struct radeon_device *rdev) | |
2384 | { | |
2385 | u32 ih_cntl = RREG32(IH_CNTL); | |
2386 | u32 ih_rb_cntl = RREG32(IH_RB_CNTL); | |
2387 | ||
2388 | ih_cntl |= ENABLE_INTR; | |
2389 | ih_rb_cntl |= IH_RB_ENABLE; | |
2390 | WREG32(IH_CNTL, ih_cntl); | |
2391 | WREG32(IH_RB_CNTL, ih_rb_cntl); | |
2392 | rdev->ih.enabled = true; | |
2393 | } | |
2394 | ||
45f9a39b | 2395 | void r600_disable_interrupts(struct radeon_device *rdev) |
d8f60cfc AD |
2396 | { |
2397 | u32 ih_rb_cntl = RREG32(IH_RB_CNTL); | |
2398 | u32 ih_cntl = RREG32(IH_CNTL); | |
2399 | ||
2400 | ih_rb_cntl &= ~IH_RB_ENABLE; | |
2401 | ih_cntl &= ~ENABLE_INTR; | |
2402 | WREG32(IH_RB_CNTL, ih_rb_cntl); | |
2403 | WREG32(IH_CNTL, ih_cntl); | |
2404 | /* set rptr, wptr to 0 */ | |
2405 | WREG32(IH_RB_RPTR, 0); | |
2406 | WREG32(IH_RB_WPTR, 0); | |
2407 | rdev->ih.enabled = false; | |
2408 | rdev->ih.wptr = 0; | |
2409 | rdev->ih.rptr = 0; | |
2410 | } | |
2411 | ||
e0df1ac5 AD |
2412 | static void r600_disable_interrupt_state(struct radeon_device *rdev) |
2413 | { | |
2414 | u32 tmp; | |
2415 | ||
2416 | WREG32(CP_INT_CNTL, 0); | |
2417 | WREG32(GRBM_INT_CNTL, 0); | |
2418 | WREG32(DxMODE_INT_MASK, 0); | |
2419 | if (ASIC_IS_DCE3(rdev)) { | |
2420 | WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0); | |
2421 | WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0); | |
2422 | tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY; | |
2423 | WREG32(DC_HPD1_INT_CONTROL, tmp); | |
2424 | tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY; | |
2425 | WREG32(DC_HPD2_INT_CONTROL, tmp); | |
2426 | tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY; | |
2427 | WREG32(DC_HPD3_INT_CONTROL, tmp); | |
2428 | tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY; | |
2429 | WREG32(DC_HPD4_INT_CONTROL, tmp); | |
2430 | if (ASIC_IS_DCE32(rdev)) { | |
2431 | tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY; | |
5898b1f3 | 2432 | WREG32(DC_HPD5_INT_CONTROL, tmp); |
e0df1ac5 | 2433 | tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY; |
5898b1f3 | 2434 | WREG32(DC_HPD6_INT_CONTROL, tmp); |
e0df1ac5 AD |
2435 | } |
2436 | } else { | |
2437 | WREG32(DACA_AUTODETECT_INT_CONTROL, 0); | |
2438 | WREG32(DACB_AUTODETECT_INT_CONTROL, 0); | |
2439 | tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; | |
5898b1f3 | 2440 | WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); |
e0df1ac5 | 2441 | tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; |
5898b1f3 | 2442 | WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); |
e0df1ac5 | 2443 | tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; |
5898b1f3 | 2444 | WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); |
e0df1ac5 AD |
2445 | } |
2446 | } | |
2447 | ||
d8f60cfc AD |
2448 | int r600_irq_init(struct radeon_device *rdev) |
2449 | { | |
2450 | int ret = 0; | |
2451 | int rb_bufsz; | |
2452 | u32 interrupt_cntl, ih_cntl, ih_rb_cntl; | |
2453 | ||
2454 | /* allocate ring */ | |
0c45249f | 2455 | ret = r600_ih_ring_alloc(rdev); |
d8f60cfc AD |
2456 | if (ret) |
2457 | return ret; | |
2458 | ||
2459 | /* disable irqs */ | |
2460 | r600_disable_interrupts(rdev); | |
2461 | ||
2462 | /* init rlc */ | |
2463 | ret = r600_rlc_init(rdev); | |
2464 | if (ret) { | |
2465 | r600_ih_ring_fini(rdev); | |
2466 | return ret; | |
2467 | } | |
2468 | ||
2469 | /* setup interrupt control */ | |
2470 | /* set dummy read address to ring address */ | |
2471 | WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8); | |
2472 | interrupt_cntl = RREG32(INTERRUPT_CNTL); | |
2473 | /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi | |
2474 | * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN | |
2475 | */ | |
2476 | interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE; | |
2477 | /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */ | |
2478 | interrupt_cntl &= ~IH_REQ_NONSNOOP_EN; | |
2479 | WREG32(INTERRUPT_CNTL, interrupt_cntl); | |
2480 | ||
2481 | WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8); | |
2482 | rb_bufsz = drm_order(rdev->ih.ring_size / 4); | |
2483 | ||
2484 | ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE | | |
2485 | IH_WPTR_OVERFLOW_CLEAR | | |
2486 | (rb_bufsz << 1)); | |
2487 | /* WPTR writeback, not yet */ | |
2488 | /*ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;*/ | |
2489 | WREG32(IH_RB_WPTR_ADDR_LO, 0); | |
2490 | WREG32(IH_RB_WPTR_ADDR_HI, 0); | |
2491 | ||
2492 | WREG32(IH_RB_CNTL, ih_rb_cntl); | |
2493 | ||
2494 | /* set rptr, wptr to 0 */ | |
2495 | WREG32(IH_RB_RPTR, 0); | |
2496 | WREG32(IH_RB_WPTR, 0); | |
2497 | ||
2498 | /* Default settings for IH_CNTL (disabled at first) */ | |
2499 | ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10); | |
2500 | /* RPTR_REARM only works if msi's are enabled */ | |
2501 | if (rdev->msi_enabled) | |
2502 | ih_cntl |= RPTR_REARM; | |
2503 | ||
2504 | #ifdef __BIG_ENDIAN | |
2505 | ih_cntl |= IH_MC_SWAP(IH_MC_SWAP_32BIT); | |
2506 | #endif | |
2507 | WREG32(IH_CNTL, ih_cntl); | |
2508 | ||
2509 | /* force the active interrupt state to all disabled */ | |
45f9a39b AD |
2510 | if (rdev->family >= CHIP_CEDAR) |
2511 | evergreen_disable_interrupt_state(rdev); | |
2512 | else | |
2513 | r600_disable_interrupt_state(rdev); | |
d8f60cfc AD |
2514 | |
2515 | /* enable irqs */ | |
2516 | r600_enable_interrupts(rdev); | |
2517 | ||
2518 | return ret; | |
2519 | } | |
2520 | ||
0c45249f | 2521 | void r600_irq_suspend(struct radeon_device *rdev) |
d8f60cfc | 2522 | { |
45f9a39b | 2523 | r600_irq_disable(rdev); |
d8f60cfc | 2524 | r600_rlc_stop(rdev); |
0c45249f JG |
2525 | } |
2526 | ||
2527 | void r600_irq_fini(struct radeon_device *rdev) | |
2528 | { | |
2529 | r600_irq_suspend(rdev); | |
d8f60cfc AD |
2530 | r600_ih_ring_fini(rdev); |
2531 | } | |
2532 | ||
2533 | int r600_irq_set(struct radeon_device *rdev) | |
2534 | { | |
e0df1ac5 AD |
2535 | u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE; |
2536 | u32 mode_int = 0; | |
2537 | u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0; | |
2031f77c | 2538 | u32 grbm_int_cntl = 0; |
f2594933 | 2539 | u32 hdmi1, hdmi2; |
d8f60cfc | 2540 | |
003e69f9 JG |
2541 | if (!rdev->irq.installed) { |
2542 | WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n"); | |
2543 | return -EINVAL; | |
2544 | } | |
d8f60cfc | 2545 | /* don't enable anything if the ih is disabled */ |
79c2bbc5 JG |
2546 | if (!rdev->ih.enabled) { |
2547 | r600_disable_interrupts(rdev); | |
2548 | /* force the active interrupt state to all disabled */ | |
2549 | r600_disable_interrupt_state(rdev); | |
d8f60cfc | 2550 | return 0; |
79c2bbc5 | 2551 | } |
d8f60cfc | 2552 | |
f2594933 | 2553 | hdmi1 = RREG32(R600_HDMI_BLOCK1 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN; |
e0df1ac5 | 2554 | if (ASIC_IS_DCE3(rdev)) { |
f2594933 | 2555 | hdmi2 = RREG32(R600_HDMI_BLOCK3 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN; |
e0df1ac5 AD |
2556 | hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN; |
2557 | hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN; | |
2558 | hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN; | |
2559 | hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN; | |
2560 | if (ASIC_IS_DCE32(rdev)) { | |
2561 | hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN; | |
2562 | hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN; | |
2563 | } | |
2564 | } else { | |
f2594933 | 2565 | hdmi2 = RREG32(R600_HDMI_BLOCK2 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN; |
e0df1ac5 AD |
2566 | hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN; |
2567 | hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN; | |
2568 | hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN; | |
2569 | } | |
2570 | ||
d8f60cfc AD |
2571 | if (rdev->irq.sw_int) { |
2572 | DRM_DEBUG("r600_irq_set: sw int\n"); | |
2573 | cp_int_cntl |= RB_INT_ENABLE; | |
2574 | } | |
2575 | if (rdev->irq.crtc_vblank_int[0]) { | |
2576 | DRM_DEBUG("r600_irq_set: vblank 0\n"); | |
2577 | mode_int |= D1MODE_VBLANK_INT_MASK; | |
2578 | } | |
2579 | if (rdev->irq.crtc_vblank_int[1]) { | |
2580 | DRM_DEBUG("r600_irq_set: vblank 1\n"); | |
2581 | mode_int |= D2MODE_VBLANK_INT_MASK; | |
2582 | } | |
e0df1ac5 AD |
2583 | if (rdev->irq.hpd[0]) { |
2584 | DRM_DEBUG("r600_irq_set: hpd 1\n"); | |
2585 | hpd1 |= DC_HPDx_INT_EN; | |
2586 | } | |
2587 | if (rdev->irq.hpd[1]) { | |
2588 | DRM_DEBUG("r600_irq_set: hpd 2\n"); | |
2589 | hpd2 |= DC_HPDx_INT_EN; | |
2590 | } | |
2591 | if (rdev->irq.hpd[2]) { | |
2592 | DRM_DEBUG("r600_irq_set: hpd 3\n"); | |
2593 | hpd3 |= DC_HPDx_INT_EN; | |
2594 | } | |
2595 | if (rdev->irq.hpd[3]) { | |
2596 | DRM_DEBUG("r600_irq_set: hpd 4\n"); | |
2597 | hpd4 |= DC_HPDx_INT_EN; | |
2598 | } | |
2599 | if (rdev->irq.hpd[4]) { | |
2600 | DRM_DEBUG("r600_irq_set: hpd 5\n"); | |
2601 | hpd5 |= DC_HPDx_INT_EN; | |
2602 | } | |
2603 | if (rdev->irq.hpd[5]) { | |
2604 | DRM_DEBUG("r600_irq_set: hpd 6\n"); | |
2605 | hpd6 |= DC_HPDx_INT_EN; | |
2606 | } | |
f2594933 CK |
2607 | if (rdev->irq.hdmi[0]) { |
2608 | DRM_DEBUG("r600_irq_set: hdmi 1\n"); | |
2609 | hdmi1 |= R600_HDMI_INT_EN; | |
2610 | } | |
2611 | if (rdev->irq.hdmi[1]) { | |
2612 | DRM_DEBUG("r600_irq_set: hdmi 2\n"); | |
2613 | hdmi2 |= R600_HDMI_INT_EN; | |
2614 | } | |
2031f77c AD |
2615 | if (rdev->irq.gui_idle) { |
2616 | DRM_DEBUG("gui idle\n"); | |
2617 | grbm_int_cntl |= GUI_IDLE_INT_ENABLE; | |
2618 | } | |
d8f60cfc AD |
2619 | |
2620 | WREG32(CP_INT_CNTL, cp_int_cntl); | |
2621 | WREG32(DxMODE_INT_MASK, mode_int); | |
2031f77c | 2622 | WREG32(GRBM_INT_CNTL, grbm_int_cntl); |
f2594933 | 2623 | WREG32(R600_HDMI_BLOCK1 + R600_HDMI_CNTL, hdmi1); |
e0df1ac5 | 2624 | if (ASIC_IS_DCE3(rdev)) { |
f2594933 | 2625 | WREG32(R600_HDMI_BLOCK3 + R600_HDMI_CNTL, hdmi2); |
e0df1ac5 AD |
2626 | WREG32(DC_HPD1_INT_CONTROL, hpd1); |
2627 | WREG32(DC_HPD2_INT_CONTROL, hpd2); | |
2628 | WREG32(DC_HPD3_INT_CONTROL, hpd3); | |
2629 | WREG32(DC_HPD4_INT_CONTROL, hpd4); | |
2630 | if (ASIC_IS_DCE32(rdev)) { | |
2631 | WREG32(DC_HPD5_INT_CONTROL, hpd5); | |
2632 | WREG32(DC_HPD6_INT_CONTROL, hpd6); | |
2633 | } | |
2634 | } else { | |
f2594933 | 2635 | WREG32(R600_HDMI_BLOCK2 + R600_HDMI_CNTL, hdmi2); |
e0df1ac5 AD |
2636 | WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1); |
2637 | WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2); | |
2638 | WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3); | |
2639 | } | |
d8f60cfc AD |
2640 | |
2641 | return 0; | |
2642 | } | |
2643 | ||
e0df1ac5 AD |
2644 | static inline void r600_irq_ack(struct radeon_device *rdev, |
2645 | u32 *disp_int, | |
2646 | u32 *disp_int_cont, | |
2647 | u32 *disp_int_cont2) | |
d8f60cfc | 2648 | { |
e0df1ac5 AD |
2649 | u32 tmp; |
2650 | ||
2651 | if (ASIC_IS_DCE3(rdev)) { | |
2652 | *disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS); | |
2653 | *disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE); | |
2654 | *disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2); | |
2655 | } else { | |
2656 | *disp_int = RREG32(DISP_INTERRUPT_STATUS); | |
2657 | *disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE); | |
2658 | *disp_int_cont2 = 0; | |
2659 | } | |
d8f60cfc | 2660 | |
e0df1ac5 | 2661 | if (*disp_int & LB_D1_VBLANK_INTERRUPT) |
d8f60cfc | 2662 | WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK); |
e0df1ac5 | 2663 | if (*disp_int & LB_D1_VLINE_INTERRUPT) |
d8f60cfc | 2664 | WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK); |
e0df1ac5 | 2665 | if (*disp_int & LB_D2_VBLANK_INTERRUPT) |
d8f60cfc | 2666 | WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK); |
e0df1ac5 | 2667 | if (*disp_int & LB_D2_VLINE_INTERRUPT) |
d8f60cfc | 2668 | WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK); |
e0df1ac5 AD |
2669 | if (*disp_int & DC_HPD1_INTERRUPT) { |
2670 | if (ASIC_IS_DCE3(rdev)) { | |
2671 | tmp = RREG32(DC_HPD1_INT_CONTROL); | |
2672 | tmp |= DC_HPDx_INT_ACK; | |
2673 | WREG32(DC_HPD1_INT_CONTROL, tmp); | |
2674 | } else { | |
2675 | tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL); | |
2676 | tmp |= DC_HPDx_INT_ACK; | |
2677 | WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); | |
2678 | } | |
2679 | } | |
2680 | if (*disp_int & DC_HPD2_INTERRUPT) { | |
2681 | if (ASIC_IS_DCE3(rdev)) { | |
2682 | tmp = RREG32(DC_HPD2_INT_CONTROL); | |
2683 | tmp |= DC_HPDx_INT_ACK; | |
2684 | WREG32(DC_HPD2_INT_CONTROL, tmp); | |
2685 | } else { | |
2686 | tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL); | |
2687 | tmp |= DC_HPDx_INT_ACK; | |
2688 | WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); | |
2689 | } | |
2690 | } | |
2691 | if (*disp_int_cont & DC_HPD3_INTERRUPT) { | |
2692 | if (ASIC_IS_DCE3(rdev)) { | |
2693 | tmp = RREG32(DC_HPD3_INT_CONTROL); | |
2694 | tmp |= DC_HPDx_INT_ACK; | |
2695 | WREG32(DC_HPD3_INT_CONTROL, tmp); | |
2696 | } else { | |
2697 | tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL); | |
2698 | tmp |= DC_HPDx_INT_ACK; | |
2699 | WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); | |
2700 | } | |
2701 | } | |
2702 | if (*disp_int_cont & DC_HPD4_INTERRUPT) { | |
2703 | tmp = RREG32(DC_HPD4_INT_CONTROL); | |
2704 | tmp |= DC_HPDx_INT_ACK; | |
2705 | WREG32(DC_HPD4_INT_CONTROL, tmp); | |
2706 | } | |
2707 | if (ASIC_IS_DCE32(rdev)) { | |
2708 | if (*disp_int_cont2 & DC_HPD5_INTERRUPT) { | |
2709 | tmp = RREG32(DC_HPD5_INT_CONTROL); | |
2710 | tmp |= DC_HPDx_INT_ACK; | |
2711 | WREG32(DC_HPD5_INT_CONTROL, tmp); | |
2712 | } | |
2713 | if (*disp_int_cont2 & DC_HPD6_INTERRUPT) { | |
2714 | tmp = RREG32(DC_HPD5_INT_CONTROL); | |
2715 | tmp |= DC_HPDx_INT_ACK; | |
2716 | WREG32(DC_HPD6_INT_CONTROL, tmp); | |
2717 | } | |
2718 | } | |
f2594933 CK |
2719 | if (RREG32(R600_HDMI_BLOCK1 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) { |
2720 | WREG32_P(R600_HDMI_BLOCK1 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK); | |
2721 | } | |
2722 | if (ASIC_IS_DCE3(rdev)) { | |
2723 | if (RREG32(R600_HDMI_BLOCK3 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) { | |
2724 | WREG32_P(R600_HDMI_BLOCK3 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK); | |
2725 | } | |
2726 | } else { | |
2727 | if (RREG32(R600_HDMI_BLOCK2 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) { | |
2728 | WREG32_P(R600_HDMI_BLOCK2 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK); | |
2729 | } | |
2730 | } | |
d8f60cfc AD |
2731 | } |
2732 | ||
2733 | void r600_irq_disable(struct radeon_device *rdev) | |
2734 | { | |
e0df1ac5 | 2735 | u32 disp_int, disp_int_cont, disp_int_cont2; |
d8f60cfc AD |
2736 | |
2737 | r600_disable_interrupts(rdev); | |
2738 | /* Wait and acknowledge irq */ | |
2739 | mdelay(1); | |
e0df1ac5 AD |
2740 | r600_irq_ack(rdev, &disp_int, &disp_int_cont, &disp_int_cont2); |
2741 | r600_disable_interrupt_state(rdev); | |
d8f60cfc AD |
2742 | } |
2743 | ||
2744 | static inline u32 r600_get_ih_wptr(struct radeon_device *rdev) | |
2745 | { | |
2746 | u32 wptr, tmp; | |
3ce0a23d | 2747 | |
d8f60cfc AD |
2748 | /* XXX use writeback */ |
2749 | wptr = RREG32(IH_RB_WPTR); | |
3ce0a23d | 2750 | |
d8f60cfc | 2751 | if (wptr & RB_OVERFLOW) { |
7924e5eb JG |
2752 | /* When a ring buffer overflow happen start parsing interrupt |
2753 | * from the last not overwritten vector (wptr + 16). Hopefully | |
2754 | * this should allow us to catchup. | |
2755 | */ | |
2756 | dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n", | |
2757 | wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask); | |
2758 | rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask; | |
d8f60cfc AD |
2759 | tmp = RREG32(IH_RB_CNTL); |
2760 | tmp |= IH_WPTR_OVERFLOW_CLEAR; | |
2761 | WREG32(IH_RB_CNTL, tmp); | |
2762 | } | |
0c45249f | 2763 | return (wptr & rdev->ih.ptr_mask); |
d8f60cfc | 2764 | } |
3ce0a23d | 2765 | |
d8f60cfc AD |
2766 | /* r600 IV Ring |
2767 | * Each IV ring entry is 128 bits: | |
2768 | * [7:0] - interrupt source id | |
2769 | * [31:8] - reserved | |
2770 | * [59:32] - interrupt source data | |
2771 | * [127:60] - reserved | |
2772 | * | |
2773 | * The basic interrupt vector entries | |
2774 | * are decoded as follows: | |
2775 | * src_id src_data description | |
2776 | * 1 0 D1 Vblank | |
2777 | * 1 1 D1 Vline | |
2778 | * 5 0 D2 Vblank | |
2779 | * 5 1 D2 Vline | |
2780 | * 19 0 FP Hot plug detection A | |
2781 | * 19 1 FP Hot plug detection B | |
2782 | * 19 2 DAC A auto-detection | |
2783 | * 19 3 DAC B auto-detection | |
f2594933 CK |
2784 | * 21 4 HDMI block A |
2785 | * 21 5 HDMI block B | |
d8f60cfc AD |
2786 | * 176 - CP_INT RB |
2787 | * 177 - CP_INT IB1 | |
2788 | * 178 - CP_INT IB2 | |
2789 | * 181 - EOP Interrupt | |
2790 | * 233 - GUI Idle | |
2791 | * | |
2792 | * Note, these are based on r600 and may need to be | |
2793 | * adjusted or added to on newer asics | |
2794 | */ | |
2795 | ||
2796 | int r600_irq_process(struct radeon_device *rdev) | |
2797 | { | |
2798 | u32 wptr = r600_get_ih_wptr(rdev); | |
2799 | u32 rptr = rdev->ih.rptr; | |
2800 | u32 src_id, src_data; | |
e0df1ac5 | 2801 | u32 ring_index, disp_int, disp_int_cont, disp_int_cont2; |
d8f60cfc | 2802 | unsigned long flags; |
d4877cf2 | 2803 | bool queue_hotplug = false; |
d8f60cfc AD |
2804 | |
2805 | DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr); | |
79c2bbc5 JG |
2806 | if (!rdev->ih.enabled) |
2807 | return IRQ_NONE; | |
d8f60cfc AD |
2808 | |
2809 | spin_lock_irqsave(&rdev->ih.lock, flags); | |
2810 | ||
2811 | if (rptr == wptr) { | |
2812 | spin_unlock_irqrestore(&rdev->ih.lock, flags); | |
2813 | return IRQ_NONE; | |
2814 | } | |
2815 | if (rdev->shutdown) { | |
2816 | spin_unlock_irqrestore(&rdev->ih.lock, flags); | |
2817 | return IRQ_NONE; | |
2818 | } | |
2819 | ||
2820 | restart_ih: | |
2821 | /* display interrupts */ | |
e0df1ac5 | 2822 | r600_irq_ack(rdev, &disp_int, &disp_int_cont, &disp_int_cont2); |
d8f60cfc AD |
2823 | |
2824 | rdev->ih.wptr = wptr; | |
2825 | while (rptr != wptr) { | |
2826 | /* wptr/rptr are in bytes! */ | |
2827 | ring_index = rptr / 4; | |
2828 | src_id = rdev->ih.ring[ring_index] & 0xff; | |
2829 | src_data = rdev->ih.ring[ring_index + 1] & 0xfffffff; | |
2830 | ||
2831 | switch (src_id) { | |
2832 | case 1: /* D1 vblank/vline */ | |
2833 | switch (src_data) { | |
2834 | case 0: /* D1 vblank */ | |
2835 | if (disp_int & LB_D1_VBLANK_INTERRUPT) { | |
2836 | drm_handle_vblank(rdev->ddev, 0); | |
839461d3 | 2837 | rdev->pm.vblank_sync = true; |
73a6d3fc | 2838 | wake_up(&rdev->irq.vblank_queue); |
d8f60cfc AD |
2839 | disp_int &= ~LB_D1_VBLANK_INTERRUPT; |
2840 | DRM_DEBUG("IH: D1 vblank\n"); | |
2841 | } | |
2842 | break; | |
2843 | case 1: /* D1 vline */ | |
2844 | if (disp_int & LB_D1_VLINE_INTERRUPT) { | |
2845 | disp_int &= ~LB_D1_VLINE_INTERRUPT; | |
2846 | DRM_DEBUG("IH: D1 vline\n"); | |
2847 | } | |
2848 | break; | |
2849 | default: | |
b042589c | 2850 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); |
d8f60cfc AD |
2851 | break; |
2852 | } | |
2853 | break; | |
2854 | case 5: /* D2 vblank/vline */ | |
2855 | switch (src_data) { | |
2856 | case 0: /* D2 vblank */ | |
2857 | if (disp_int & LB_D2_VBLANK_INTERRUPT) { | |
2858 | drm_handle_vblank(rdev->ddev, 1); | |
839461d3 | 2859 | rdev->pm.vblank_sync = true; |
73a6d3fc | 2860 | wake_up(&rdev->irq.vblank_queue); |
d8f60cfc AD |
2861 | disp_int &= ~LB_D2_VBLANK_INTERRUPT; |
2862 | DRM_DEBUG("IH: D2 vblank\n"); | |
2863 | } | |
2864 | break; | |
2865 | case 1: /* D1 vline */ | |
2866 | if (disp_int & LB_D2_VLINE_INTERRUPT) { | |
2867 | disp_int &= ~LB_D2_VLINE_INTERRUPT; | |
2868 | DRM_DEBUG("IH: D2 vline\n"); | |
2869 | } | |
2870 | break; | |
2871 | default: | |
b042589c | 2872 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); |
d8f60cfc AD |
2873 | break; |
2874 | } | |
2875 | break; | |
e0df1ac5 AD |
2876 | case 19: /* HPD/DAC hotplug */ |
2877 | switch (src_data) { | |
2878 | case 0: | |
2879 | if (disp_int & DC_HPD1_INTERRUPT) { | |
2880 | disp_int &= ~DC_HPD1_INTERRUPT; | |
d4877cf2 AD |
2881 | queue_hotplug = true; |
2882 | DRM_DEBUG("IH: HPD1\n"); | |
e0df1ac5 AD |
2883 | } |
2884 | break; | |
2885 | case 1: | |
2886 | if (disp_int & DC_HPD2_INTERRUPT) { | |
2887 | disp_int &= ~DC_HPD2_INTERRUPT; | |
d4877cf2 AD |
2888 | queue_hotplug = true; |
2889 | DRM_DEBUG("IH: HPD2\n"); | |
e0df1ac5 AD |
2890 | } |
2891 | break; | |
2892 | case 4: | |
2893 | if (disp_int_cont & DC_HPD3_INTERRUPT) { | |
2894 | disp_int_cont &= ~DC_HPD3_INTERRUPT; | |
d4877cf2 AD |
2895 | queue_hotplug = true; |
2896 | DRM_DEBUG("IH: HPD3\n"); | |
e0df1ac5 AD |
2897 | } |
2898 | break; | |
2899 | case 5: | |
2900 | if (disp_int_cont & DC_HPD4_INTERRUPT) { | |
2901 | disp_int_cont &= ~DC_HPD4_INTERRUPT; | |
d4877cf2 AD |
2902 | queue_hotplug = true; |
2903 | DRM_DEBUG("IH: HPD4\n"); | |
e0df1ac5 AD |
2904 | } |
2905 | break; | |
2906 | case 10: | |
2907 | if (disp_int_cont2 & DC_HPD5_INTERRUPT) { | |
5898b1f3 | 2908 | disp_int_cont2 &= ~DC_HPD5_INTERRUPT; |
d4877cf2 AD |
2909 | queue_hotplug = true; |
2910 | DRM_DEBUG("IH: HPD5\n"); | |
e0df1ac5 AD |
2911 | } |
2912 | break; | |
2913 | case 12: | |
2914 | if (disp_int_cont2 & DC_HPD6_INTERRUPT) { | |
5898b1f3 | 2915 | disp_int_cont2 &= ~DC_HPD6_INTERRUPT; |
d4877cf2 AD |
2916 | queue_hotplug = true; |
2917 | DRM_DEBUG("IH: HPD6\n"); | |
e0df1ac5 AD |
2918 | } |
2919 | break; | |
2920 | default: | |
b042589c | 2921 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); |
e0df1ac5 AD |
2922 | break; |
2923 | } | |
2924 | break; | |
f2594933 CK |
2925 | case 21: /* HDMI */ |
2926 | DRM_DEBUG("IH: HDMI: 0x%x\n", src_data); | |
2927 | r600_audio_schedule_polling(rdev); | |
2928 | break; | |
d8f60cfc AD |
2929 | case 176: /* CP_INT in ring buffer */ |
2930 | case 177: /* CP_INT in IB1 */ | |
2931 | case 178: /* CP_INT in IB2 */ | |
2932 | DRM_DEBUG("IH: CP int: 0x%08x\n", src_data); | |
2933 | radeon_fence_process(rdev); | |
2934 | break; | |
2935 | case 181: /* CP EOP event */ | |
2936 | DRM_DEBUG("IH: CP EOP\n"); | |
2937 | break; | |
2031f77c AD |
2938 | case 233: /* GUI IDLE */ |
2939 | DRM_DEBUG("IH: CP EOP\n"); | |
2940 | rdev->pm.gui_idle = true; | |
2941 | wake_up(&rdev->irq.idle_queue); | |
2942 | break; | |
d8f60cfc | 2943 | default: |
b042589c | 2944 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); |
d8f60cfc AD |
2945 | break; |
2946 | } | |
2947 | ||
2948 | /* wptr/rptr are in bytes! */ | |
0c45249f JG |
2949 | rptr += 16; |
2950 | rptr &= rdev->ih.ptr_mask; | |
d8f60cfc AD |
2951 | } |
2952 | /* make sure wptr hasn't changed while processing */ | |
2953 | wptr = r600_get_ih_wptr(rdev); | |
2954 | if (wptr != rdev->ih.wptr) | |
2955 | goto restart_ih; | |
d4877cf2 AD |
2956 | if (queue_hotplug) |
2957 | queue_work(rdev->wq, &rdev->hotplug_work); | |
d8f60cfc AD |
2958 | rdev->ih.rptr = rptr; |
2959 | WREG32(IH_RB_RPTR, rdev->ih.rptr); | |
2960 | spin_unlock_irqrestore(&rdev->ih.lock, flags); | |
2961 | return IRQ_HANDLED; | |
2962 | } | |
3ce0a23d JG |
2963 | |
2964 | /* | |
2965 | * Debugfs info | |
2966 | */ | |
2967 | #if defined(CONFIG_DEBUG_FS) | |
2968 | ||
2969 | static int r600_debugfs_cp_ring_info(struct seq_file *m, void *data) | |
771fe6b9 | 2970 | { |
3ce0a23d JG |
2971 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
2972 | struct drm_device *dev = node->minor->dev; | |
2973 | struct radeon_device *rdev = dev->dev_private; | |
3ce0a23d JG |
2974 | unsigned count, i, j; |
2975 | ||
2976 | radeon_ring_free_size(rdev); | |
d6840766 | 2977 | count = (rdev->cp.ring_size / 4) - rdev->cp.ring_free_dw; |
3ce0a23d | 2978 | seq_printf(m, "CP_STAT 0x%08x\n", RREG32(CP_STAT)); |
d6840766 RM |
2979 | seq_printf(m, "CP_RB_WPTR 0x%08x\n", RREG32(CP_RB_WPTR)); |
2980 | seq_printf(m, "CP_RB_RPTR 0x%08x\n", RREG32(CP_RB_RPTR)); | |
2981 | seq_printf(m, "driver's copy of the CP_RB_WPTR 0x%08x\n", rdev->cp.wptr); | |
2982 | seq_printf(m, "driver's copy of the CP_RB_RPTR 0x%08x\n", rdev->cp.rptr); | |
3ce0a23d JG |
2983 | seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw); |
2984 | seq_printf(m, "%u dwords in ring\n", count); | |
d6840766 | 2985 | i = rdev->cp.rptr; |
3ce0a23d | 2986 | for (j = 0; j <= count; j++) { |
3ce0a23d | 2987 | seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]); |
d6840766 | 2988 | i = (i + 1) & rdev->cp.ptr_mask; |
3ce0a23d JG |
2989 | } |
2990 | return 0; | |
2991 | } | |
2992 | ||
2993 | static int r600_debugfs_mc_info(struct seq_file *m, void *data) | |
2994 | { | |
2995 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
2996 | struct drm_device *dev = node->minor->dev; | |
2997 | struct radeon_device *rdev = dev->dev_private; | |
2998 | ||
2999 | DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS); | |
3000 | DREG32_SYS(m, rdev, VM_L2_STATUS); | |
3001 | return 0; | |
3002 | } | |
3003 | ||
3004 | static struct drm_info_list r600_mc_info_list[] = { | |
3005 | {"r600_mc_info", r600_debugfs_mc_info, 0, NULL}, | |
3006 | {"r600_ring_info", r600_debugfs_cp_ring_info, 0, NULL}, | |
3007 | }; | |
3008 | #endif | |
3009 | ||
3010 | int r600_debugfs_mc_info_init(struct radeon_device *rdev) | |
3011 | { | |
3012 | #if defined(CONFIG_DEBUG_FS) | |
3013 | return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list)); | |
3014 | #else | |
3015 | return 0; | |
3016 | #endif | |
771fe6b9 | 3017 | } |
062b389c JG |
3018 | |
3019 | /** | |
3020 | * r600_ioctl_wait_idle - flush host path cache on wait idle ioctl | |
3021 | * rdev: radeon device structure | |
3022 | * bo: buffer object struct which userspace is waiting for idle | |
3023 | * | |
3024 | * Some R6XX/R7XX doesn't seems to take into account HDP flush performed | |
3025 | * through ring buffer, this leads to corruption in rendering, see | |
3026 | * http://bugzilla.kernel.org/show_bug.cgi?id=15186 to avoid this we | |
3027 | * directly perform HDP flush by writing register through MMIO. | |
3028 | */ | |
3029 | void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo) | |
3030 | { | |
3031 | WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); | |
3032 | } |