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drm/radeon: add a bios scratch asic hung helper
[deliverable/linux.git] / drivers / gpu / drm / radeon / r600.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
5a0e3ad6 28#include <linux/slab.h>
3ce0a23d
JG		 29#include <linux/seq_file.h>
30#include <linux/firmware.h>
31#include <linux/platform_device.h>
e0cd3608 32#include <linux/module.h>
760285e7
DH		 33#include <drm/drmP.h>
34#include <drm/radeon_drm.h>
771fe6b9 35#include "radeon.h"
e6990375 36#include "radeon_asic.h"
3ce0a23d 37#include "radeon_mode.h"
3ce0a23d 38#include "r600d.h"
3ce0a23d 39#include "atom.h"
d39c3b89 40#include "avivod.h"
771fe6b9 41
3ce0a23d
JG		 42#define PFP_UCODE_SIZE 576
43#define PM4_UCODE_SIZE 1792
d8f60cfc 44#define RLC_UCODE_SIZE 768
3ce0a23d
JG		 45#define R700_PFP_UCODE_SIZE 848
46#define R700_PM4_UCODE_SIZE 1360
d8f60cfc 47#define R700_RLC_UCODE_SIZE 1024
fe251e2f
AD		 48#define EVERGREEN_PFP_UCODE_SIZE 1120
49#define EVERGREEN_PM4_UCODE_SIZE 1376
45f9a39b 50#define EVERGREEN_RLC_UCODE_SIZE 768
12727809 51#define CAYMAN_RLC_UCODE_SIZE 1024
c420c745 52#define ARUBA_RLC_UCODE_SIZE 1536
3ce0a23d
JG		 53
54/* Firmware Names */
55MODULE_FIRMWARE("radeon/R600_pfp.bin");
56MODULE_FIRMWARE("radeon/R600_me.bin");
57MODULE_FIRMWARE("radeon/RV610_pfp.bin");
58MODULE_FIRMWARE("radeon/RV610_me.bin");
59MODULE_FIRMWARE("radeon/RV630_pfp.bin");
60MODULE_FIRMWARE("radeon/RV630_me.bin");
61MODULE_FIRMWARE("radeon/RV620_pfp.bin");
62MODULE_FIRMWARE("radeon/RV620_me.bin");
63MODULE_FIRMWARE("radeon/RV635_pfp.bin");
64MODULE_FIRMWARE("radeon/RV635_me.bin");
65MODULE_FIRMWARE("radeon/RV670_pfp.bin");
66MODULE_FIRMWARE("radeon/RV670_me.bin");
67MODULE_FIRMWARE("radeon/RS780_pfp.bin");
68MODULE_FIRMWARE("radeon/RS780_me.bin");
69MODULE_FIRMWARE("radeon/RV770_pfp.bin");
70MODULE_FIRMWARE("radeon/RV770_me.bin");
71MODULE_FIRMWARE("radeon/RV730_pfp.bin");
72MODULE_FIRMWARE("radeon/RV730_me.bin");
73MODULE_FIRMWARE("radeon/RV710_pfp.bin");
74MODULE_FIRMWARE("radeon/RV710_me.bin");
d8f60cfc
AD		 75MODULE_FIRMWARE("radeon/R600_rlc.bin");
76MODULE_FIRMWARE("radeon/R700_rlc.bin");
fe251e2f
AD		 77MODULE_FIRMWARE("radeon/CEDAR_pfp.bin");
78MODULE_FIRMWARE("radeon/CEDAR_me.bin");
45f9a39b 79MODULE_FIRMWARE("radeon/CEDAR_rlc.bin");
fe251e2f
AD		 80MODULE_FIRMWARE("radeon/REDWOOD_pfp.bin");
81MODULE_FIRMWARE("radeon/REDWOOD_me.bin");
45f9a39b 82MODULE_FIRMWARE("radeon/REDWOOD_rlc.bin");
fe251e2f
AD		 83MODULE_FIRMWARE("radeon/JUNIPER_pfp.bin");
84MODULE_FIRMWARE("radeon/JUNIPER_me.bin");
45f9a39b 85MODULE_FIRMWARE("radeon/JUNIPER_rlc.bin");
a7433742 86MODULE_FIRMWARE("radeon/CYPRESS_pfp.bin");
fe251e2f 87MODULE_FIRMWARE("radeon/CYPRESS_me.bin");
45f9a39b 88MODULE_FIRMWARE("radeon/CYPRESS_rlc.bin");
439bd6cd
AD		 89MODULE_FIRMWARE("radeon/PALM_pfp.bin");
90MODULE_FIRMWARE("radeon/PALM_me.bin");
91MODULE_FIRMWARE("radeon/SUMO_rlc.bin");
d5c5a72f
AD		 92MODULE_FIRMWARE("radeon/SUMO_pfp.bin");
93MODULE_FIRMWARE("radeon/SUMO_me.bin");
94MODULE_FIRMWARE("radeon/SUMO2_pfp.bin");
95MODULE_FIRMWARE("radeon/SUMO2_me.bin");
3ce0a23d
JG		 96
97int r600_debugfs_mc_info_init(struct radeon_device *rdev);
771fe6b9 98
1a029b76 99/* r600,rv610,rv630,rv620,rv635,rv670 */
771fe6b9 100int r600_mc_wait_for_idle(struct radeon_device *rdev);
1109ca09 101static void r600_gpu_init(struct radeon_device *rdev);
3ce0a23d 102void r600_fini(struct radeon_device *rdev);
45f9a39b 103void r600_irq_disable(struct radeon_device *rdev);
9e46a48d 104static void r600_pcie_gen2_enable(struct radeon_device *rdev);
771fe6b9 105
21a8122a 106/* get temperature in millidegrees */
20d391d7 107int rv6xx_get_temp(struct radeon_device *rdev)
21a8122a
AD		 108{
109 u32 temp = (RREG32(CG_THERMAL_STATUS) & ASIC_T_MASK) >>
110 ASIC_T_SHIFT;
20d391d7 111 int actual_temp = temp & 0xff;
21a8122a 112
20d391d7
AD		 113 if (temp & 0x100)
114 actual_temp -= 256;
115
116 return actual_temp * 1000;
21a8122a
AD		 117}
118
ce8f5370 119void r600_pm_get_dynpm_state(struct radeon_device *rdev)
a48b9b4e
AD		 120{
121 int i;
122
ce8f5370
AD		 123 rdev->pm.dynpm_can_upclock = true;
124 rdev->pm.dynpm_can_downclock = true;
a48b9b4e
AD		 125
126 /* power state array is low to high, default is first */
127 if ((rdev->flags & RADEON_IS_IGP) || (rdev->family == CHIP_R600)) {
128 int min_power_state_index = 0;
129
130 if (rdev->pm.num_power_states > 2)
131 min_power_state_index = 1;
132
ce8f5370
AD		 133 switch (rdev->pm.dynpm_planned_action) {
134 case DYNPM_ACTION_MINIMUM:
a48b9b4e
AD		 135 rdev->pm.requested_power_state_index = min_power_state_index;
136 rdev->pm.requested_clock_mode_index = 0;
ce8f5370 137 rdev->pm.dynpm_can_downclock = false;
a48b9b4e 138 break;
ce8f5370 139 case DYNPM_ACTION_DOWNCLOCK:
a48b9b4e
AD		 140 if (rdev->pm.current_power_state_index == min_power_state_index) {
141 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
ce8f5370 142 rdev->pm.dynpm_can_downclock = false;
a48b9b4e
AD		 143 } else {
144 if (rdev->pm.active_crtc_count > 1) {
145 for (i = 0; i < rdev->pm.num_power_states; i++) {
d7311171 146 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
a48b9b4e
AD		 147 continue;
148 else if (i >= rdev->pm.current_power_state_index) {
149 rdev->pm.requested_power_state_index =
150 rdev->pm.current_power_state_index;
151 break;
152 } else {
153 rdev->pm.requested_power_state_index = i;
154 break;
155 }
156 }
773c3fa3
AD		 157 } else {
158 if (rdev->pm.current_power_state_index == 0)
159 rdev->pm.requested_power_state_index =
160 rdev->pm.num_power_states - 1;
161 else
162 rdev->pm.requested_power_state_index =
163 rdev->pm.current_power_state_index - 1;
164 }
a48b9b4e
AD		 165 }
166 rdev->pm.requested_clock_mode_index = 0;
d7311171
AD		 167 /* don't use the power state if crtcs are active and no display flag is set */
168 if ((rdev->pm.active_crtc_count > 0) &&
169 (rdev->pm.power_state[rdev->pm.requested_power_state_index].
170 clock_info[rdev->pm.requested_clock_mode_index].flags &
171 RADEON_PM_MODE_NO_DISPLAY)) {
172 rdev->pm.requested_power_state_index++;
173 }
a48b9b4e 174 break;
ce8f5370 175 case DYNPM_ACTION_UPCLOCK:
a48b9b4e
AD		 176 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
177 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
ce8f5370 178 rdev->pm.dynpm_can_upclock = false;
a48b9b4e
AD		 179 } else {
180 if (rdev->pm.active_crtc_count > 1) {
181 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
d7311171 182 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
a48b9b4e
AD		 183 continue;
184 else if (i <= rdev->pm.current_power_state_index) {
185 rdev->pm.requested_power_state_index =
186 rdev->pm.current_power_state_index;
187 break;
188 } else {
189 rdev->pm.requested_power_state_index = i;
190 break;
191 }
192 }
193 } else
194 rdev->pm.requested_power_state_index =
195 rdev->pm.current_power_state_index + 1;
196 }
197 rdev->pm.requested_clock_mode_index = 0;
198 break;
ce8f5370 199 case DYNPM_ACTION_DEFAULT:
58e21dff
AD		 200 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
201 rdev->pm.requested_clock_mode_index = 0;
ce8f5370 202 rdev->pm.dynpm_can_upclock = false;
58e21dff 203 break;
ce8f5370 204 case DYNPM_ACTION_NONE:
a48b9b4e
AD		 205 default:
206 DRM_ERROR("Requested mode for not defined action\n");
207 return;
208 }
209 } else {
210 /* XXX select a power state based on AC/DC, single/dualhead, etc. */
211 /* for now just select the first power state and switch between clock modes */
212 /* power state array is low to high, default is first (0) */
213 if (rdev->pm.active_crtc_count > 1) {
214 rdev->pm.requested_power_state_index = -1;
215 /* start at 1 as we don't want the default mode */
216 for (i = 1; i < rdev->pm.num_power_states; i++) {
d7311171 217 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
a48b9b4e
AD		 218 continue;
219 else if ((rdev->pm.power_state[i].type == POWER_STATE_TYPE_PERFORMANCE) ||
220 (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY)) {
221 rdev->pm.requested_power_state_index = i;
222 break;
223 }
224 }
225 /* if nothing selected, grab the default state. */
226 if (rdev->pm.requested_power_state_index == -1)
227 rdev->pm.requested_power_state_index = 0;
228 } else
229 rdev->pm.requested_power_state_index = 1;
230
ce8f5370
AD		 231 switch (rdev->pm.dynpm_planned_action) {
232 case DYNPM_ACTION_MINIMUM:
a48b9b4e 233 rdev->pm.requested_clock_mode_index = 0;
ce8f5370 234 rdev->pm.dynpm_can_downclock = false;
a48b9b4e 235 break;
ce8f5370 236 case DYNPM_ACTION_DOWNCLOCK:
a48b9b4e
AD		 237 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
238 if (rdev->pm.current_clock_mode_index == 0) {
239 rdev->pm.requested_clock_mode_index = 0;
ce8f5370 240 rdev->pm.dynpm_can_downclock = false;
a48b9b4e
AD		 241 } else
242 rdev->pm.requested_clock_mode_index =
243 rdev->pm.current_clock_mode_index - 1;
244 } else {
245 rdev->pm.requested_clock_mode_index = 0;
ce8f5370 246 rdev->pm.dynpm_can_downclock = false;
a48b9b4e 247 }
d7311171
AD		 248 /* don't use the power state if crtcs are active and no display flag is set */
249 if ((rdev->pm.active_crtc_count > 0) &&
250 (rdev->pm.power_state[rdev->pm.requested_power_state_index].
251 clock_info[rdev->pm.requested_clock_mode_index].flags &
252 RADEON_PM_MODE_NO_DISPLAY)) {
253 rdev->pm.requested_clock_mode_index++;
254 }
a48b9b4e 255 break;
ce8f5370 256 case DYNPM_ACTION_UPCLOCK:
a48b9b4e
AD		 257 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
258 if (rdev->pm.current_clock_mode_index ==
259 (rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1)) {
260 rdev->pm.requested_clock_mode_index = rdev->pm.current_clock_mode_index;
ce8f5370 261 rdev->pm.dynpm_can_upclock = false;
a48b9b4e
AD		 262 } else
263 rdev->pm.requested_clock_mode_index =
264 rdev->pm.current_clock_mode_index + 1;
265 } else {
266 rdev->pm.requested_clock_mode_index =
267 rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1;
ce8f5370 268 rdev->pm.dynpm_can_upclock = false;
a48b9b4e
AD		 269 }
270 break;
ce8f5370 271 case DYNPM_ACTION_DEFAULT:
58e21dff
AD		 272 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
273 rdev->pm.requested_clock_mode_index = 0;
ce8f5370 274 rdev->pm.dynpm_can_upclock = false;
58e21dff 275 break;
ce8f5370 276 case DYNPM_ACTION_NONE:
a48b9b4e
AD		 277 default:
278 DRM_ERROR("Requested mode for not defined action\n");
279 return;
280 }
281 }
282
d9fdaafb 283 DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
ce8a3eb2
AD		 284 rdev->pm.power_state[rdev->pm.requested_power_state_index].
285 clock_info[rdev->pm.requested_clock_mode_index].sclk,
286 rdev->pm.power_state[rdev->pm.requested_power_state_index].
287 clock_info[rdev->pm.requested_clock_mode_index].mclk,
288 rdev->pm.power_state[rdev->pm.requested_power_state_index].
289 pcie_lanes);
a48b9b4e
AD		 290}
291
ce8f5370
AD		 292void rs780_pm_init_profile(struct radeon_device *rdev)
293{
294 if (rdev->pm.num_power_states == 2) {
295 /* default */
296 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
297 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
298 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
299 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
300 /* low sh */
301 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
302 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
303 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
304 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 305 /* mid sh */
306 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
307 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
308 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
309 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 310 /* high sh */
311 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
312 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
313 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
314 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
315 /* low mh */
316 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
317 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
318 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
319 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 320 /* mid mh */
321 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
322 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
323 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
324 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 325 /* high mh */
326 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
327 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 1;
328 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
329 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
330 } else if (rdev->pm.num_power_states == 3) {
331 /* default */
332 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
333 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
334 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
335 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
336 /* low sh */
337 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
338 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
339 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
340 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 341 /* mid sh */
342 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
343 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
344 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
345 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 346 /* high sh */
347 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
348 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 2;
349 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
350 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
351 /* low mh */
352 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 1;
353 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 1;
354 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
355 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 356 /* mid mh */
357 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 1;
358 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 1;
359 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
360 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 361 /* high mh */
362 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 1;
363 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
364 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
365 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
366 } else {
367 /* default */
368 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
369 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
370 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
371 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
372 /* low sh */
373 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 2;
374 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 2;
375 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
376 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 377 /* mid sh */
378 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 2;
379 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 2;
380 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
381 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 382 /* high sh */
383 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 2;
384 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 3;
385 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
386 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
387 /* low mh */
388 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
389 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
390 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
391 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 392 /* mid mh */
393 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
394 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
395 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
396 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 397 /* high mh */
398 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
399 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 3;
400 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
401 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
402 }
403}
bae6b562 404
ce8f5370
AD		 405void r600_pm_init_profile(struct radeon_device *rdev)
406{
bbe26ffe
AD		 407 int idx;
408
ce8f5370
AD		 409 if (rdev->family == CHIP_R600) {
410 /* XXX */
411 /* default */
412 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
413 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
414 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
4bff5171 415 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 416 /* low sh */
417 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
418 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
419 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
4bff5171 420 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 421 /* mid sh */
422 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
423 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
424 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
425 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 426 /* high sh */
427 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
428 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
429 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
4bff5171 430 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 431 /* low mh */
432 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
433 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
434 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
4bff5171 435 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 436 /* mid mh */
437 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
438 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
439 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
440 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 441 /* high mh */
442 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
443 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
444 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
4bff5171 445 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 446 } else {
447 if (rdev->pm.num_power_states < 4) {
448 /* default */
449 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
450 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
451 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
452 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
453 /* low sh */
4bff5171
AD		 454 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
455 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
ce8f5370 456 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
c9e75b21
AD		 457 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
458 /* mid sh */
459 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
460 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
461 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
462 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
ce8f5370 463 /* high sh */
4bff5171
AD		 464 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
465 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
ce8f5370
AD		 466 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
467 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
468 /* low mh */
4bff5171
AD		 469 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
470 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 2;
ce8f5370 471 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
c9e75b21
AD		 472 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
473 /* low mh */
474 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
475 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 2;
476 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
477 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
ce8f5370 478 /* high mh */
4bff5171
AD		 479 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
480 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
ce8f5370
AD		 481 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
482 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
483 } else {
484 /* default */
485 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
486 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
487 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
488 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
489 /* low sh */
bbe26ffe
AD		 490 if (rdev->flags & RADEON_IS_MOBILITY)
491 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
492 else
493 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
494 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx;
495 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx;
496 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
497 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
c9e75b21 498 /* mid sh */
bbe26ffe
AD		 499 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx;
500 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx;
501 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
502 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
ce8f5370 503 /* high sh */
bbe26ffe
AD		 504 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
505 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx;
506 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx;
ce8f5370
AD		 507 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
508 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
509 /* low mh */
bbe26ffe
AD		 510 if (rdev->flags & RADEON_IS_MOBILITY)
511 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
512 else
513 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
514 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx;
515 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx;
516 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
517 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
c9e75b21 518 /* mid mh */
bbe26ffe
AD		 519 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx;
520 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx;
521 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
522 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
ce8f5370 523 /* high mh */
bbe26ffe
AD		 524 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
525 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx;
526 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx;
ce8f5370
AD		 527 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
528 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
529 }
530 }
bae6b562
AD		 531}
532
49e02b73
AD		 533void r600_pm_misc(struct radeon_device *rdev)
534{
a081a9d6
RM		 535 int req_ps_idx = rdev->pm.requested_power_state_index;
536 int req_cm_idx = rdev->pm.requested_clock_mode_index;
537 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
538 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
7ac9aa5a 539
4d60173f 540 if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
a377e187
AD		 541 /* 0xff01 is a flag rather then an actual voltage */
542 if (voltage->voltage == 0xff01)
543 return;
4d60173f 544 if (voltage->voltage != rdev->pm.current_vddc) {
8a83ec5e 545 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
4d60173f 546 rdev->pm.current_vddc = voltage->voltage;
d9fdaafb 547 DRM_DEBUG_DRIVER("Setting: v: %d\n", voltage->voltage);
4d60173f
AD		 548 }
549 }
49e02b73
AD		 550}
551
def9ba9c
AD		 552bool r600_gui_idle(struct radeon_device *rdev)
553{
554 if (RREG32(GRBM_STATUS) & GUI_ACTIVE)
555 return false;
556 else
557 return true;
558}
559
e0df1ac5
AD		 560/* hpd for digital panel detect/disconnect */
561bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
562{
563 bool connected = false;
564
565 if (ASIC_IS_DCE3(rdev)) {
566 switch (hpd) {
567 case RADEON_HPD_1:
568 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
569 connected = true;
570 break;
571 case RADEON_HPD_2:
572 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
573 connected = true;
574 break;
575 case RADEON_HPD_3:
576 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
577 connected = true;
578 break;
579 case RADEON_HPD_4:
580 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
581 connected = true;
582 break;
583 /* DCE 3.2 */
584 case RADEON_HPD_5:
585 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
586 connected = true;
587 break;
588 case RADEON_HPD_6:
589 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
590 connected = true;
591 break;
592 default:
593 break;
594 }
595 } else {
596 switch (hpd) {
597 case RADEON_HPD_1:
598 if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
599 connected = true;
600 break;
601 case RADEON_HPD_2:
602 if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
603 connected = true;
604 break;
605 case RADEON_HPD_3:
606 if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
607 connected = true;
608 break;
609 default:
610 break;
611 }
612 }
613 return connected;
614}
615
616void r600_hpd_set_polarity(struct radeon_device *rdev,
429770b3 617 enum radeon_hpd_id hpd)
e0df1ac5
AD		 618{
619 u32 tmp;
620 bool connected = r600_hpd_sense(rdev, hpd);
621
622 if (ASIC_IS_DCE3(rdev)) {
623 switch (hpd) {
624 case RADEON_HPD_1:
625 tmp = RREG32(DC_HPD1_INT_CONTROL);
626 if (connected)
627 tmp &= ~DC_HPDx_INT_POLARITY;
628 else
629 tmp |= DC_HPDx_INT_POLARITY;
630 WREG32(DC_HPD1_INT_CONTROL, tmp);
631 break;
632 case RADEON_HPD_2:
633 tmp = RREG32(DC_HPD2_INT_CONTROL);
634 if (connected)
635 tmp &= ~DC_HPDx_INT_POLARITY;
636 else
637 tmp |= DC_HPDx_INT_POLARITY;
638 WREG32(DC_HPD2_INT_CONTROL, tmp);
639 break;
640 case RADEON_HPD_3:
641 tmp = RREG32(DC_HPD3_INT_CONTROL);
642 if (connected)
643 tmp &= ~DC_HPDx_INT_POLARITY;
644 else
645 tmp |= DC_HPDx_INT_POLARITY;
646 WREG32(DC_HPD3_INT_CONTROL, tmp);
647 break;
648 case RADEON_HPD_4:
649 tmp = RREG32(DC_HPD4_INT_CONTROL);
650 if (connected)
651 tmp &= ~DC_HPDx_INT_POLARITY;
652 else
653 tmp |= DC_HPDx_INT_POLARITY;
654 WREG32(DC_HPD4_INT_CONTROL, tmp);
655 break;
656 case RADEON_HPD_5:
657 tmp = RREG32(DC_HPD5_INT_CONTROL);
658 if (connected)
659 tmp &= ~DC_HPDx_INT_POLARITY;
660 else
661 tmp |= DC_HPDx_INT_POLARITY;
662 WREG32(DC_HPD5_INT_CONTROL, tmp);
663 break;
664 /* DCE 3.2 */
665 case RADEON_HPD_6:
666 tmp = RREG32(DC_HPD6_INT_CONTROL);
667 if (connected)
668 tmp &= ~DC_HPDx_INT_POLARITY;
669 else
670 tmp |= DC_HPDx_INT_POLARITY;
671 WREG32(DC_HPD6_INT_CONTROL, tmp);
672 break;
673 default:
674 break;
675 }
676 } else {
677 switch (hpd) {
678 case RADEON_HPD_1:
679 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
680 if (connected)
681 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
682 else
683 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
684 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
685 break;
686 case RADEON_HPD_2:
687 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
688 if (connected)
689 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
690 else
691 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
692 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
693 break;
694 case RADEON_HPD_3:
695 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
696 if (connected)
697 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
698 else
699 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
700 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
701 break;
702 default:
703 break;
704 }
705 }
706}
707
708void r600_hpd_init(struct radeon_device *rdev)
709{
710 struct drm_device *dev = rdev->ddev;
711 struct drm_connector *connector;
fb98257a 712 unsigned enable = 0;
e0df1ac5 713
64912e99
AD		 714 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
715 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
716
455c89b9
JG		 717 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
718 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
719 /* don't try to enable hpd on eDP or LVDS avoid breaking the
720 * aux dp channel on imac and help (but not completely fix)
721 * https://bugzilla.redhat.com/show_bug.cgi?id=726143
722 */
723 continue;
724 }
64912e99
AD		 725 if (ASIC_IS_DCE3(rdev)) {
726 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa);
727 if (ASIC_IS_DCE32(rdev))
728 tmp |= DC_HPDx_EN;
e0df1ac5 729
e0df1ac5
AD		 730 switch (radeon_connector->hpd.hpd) {
731 case RADEON_HPD_1:
732 WREG32(DC_HPD1_CONTROL, tmp);
e0df1ac5
AD		 733 break;
734 case RADEON_HPD_2:
735 WREG32(DC_HPD2_CONTROL, tmp);
e0df1ac5
AD		 736 break;
737 case RADEON_HPD_3:
738 WREG32(DC_HPD3_CONTROL, tmp);
e0df1ac5
AD		 739 break;
740 case RADEON_HPD_4:
741 WREG32(DC_HPD4_CONTROL, tmp);
e0df1ac5
AD		 742 break;
743 /* DCE 3.2 */
744 case RADEON_HPD_5:
745 WREG32(DC_HPD5_CONTROL, tmp);
e0df1ac5
AD		 746 break;
747 case RADEON_HPD_6:
748 WREG32(DC_HPD6_CONTROL, tmp);
e0df1ac5
AD		 749 break;
750 default:
751 break;
752 }
64912e99 753 } else {
e0df1ac5
AD		 754 switch (radeon_connector->hpd.hpd) {
755 case RADEON_HPD_1:
756 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN);
e0df1ac5
AD		 757 break;
758 case RADEON_HPD_2:
759 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN);
e0df1ac5
AD		 760 break;
761 case RADEON_HPD_3:
762 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN);
e0df1ac5
AD		 763 break;
764 default:
765 break;
766 }
767 }
fb98257a 768 enable |= 1 << radeon_connector->hpd.hpd;
64912e99 769 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
e0df1ac5 770 }
fb98257a 771 radeon_irq_kms_enable_hpd(rdev, enable);
e0df1ac5
AD		 772}
773
774void r600_hpd_fini(struct radeon_device *rdev)
775{
776 struct drm_device *dev = rdev->ddev;
777 struct drm_connector *connector;
fb98257a 778 unsigned disable = 0;
e0df1ac5 779
fb98257a
CK		 780 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
781 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
782 if (ASIC_IS_DCE3(rdev)) {
e0df1ac5
AD		 783 switch (radeon_connector->hpd.hpd) {
784 case RADEON_HPD_1:
785 WREG32(DC_HPD1_CONTROL, 0);
e0df1ac5
AD		 786 break;
787 case RADEON_HPD_2:
788 WREG32(DC_HPD2_CONTROL, 0);
e0df1ac5
AD		 789 break;
790 case RADEON_HPD_3:
791 WREG32(DC_HPD3_CONTROL, 0);
e0df1ac5
AD		 792 break;
793 case RADEON_HPD_4:
794 WREG32(DC_HPD4_CONTROL, 0);
e0df1ac5
AD		 795 break;
796 /* DCE 3.2 */
797 case RADEON_HPD_5:
798 WREG32(DC_HPD5_CONTROL, 0);
e0df1ac5
AD		 799 break;
800 case RADEON_HPD_6:
801 WREG32(DC_HPD6_CONTROL, 0);
e0df1ac5
AD		 802 break;
803 default:
804 break;
805 }
fb98257a 806 } else {
e0df1ac5
AD		 807 switch (radeon_connector->hpd.hpd) {
808 case RADEON_HPD_1:
809 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0);
e0df1ac5
AD		 810 break;
811 case RADEON_HPD_2:
812 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0);
e0df1ac5
AD		 813 break;
814 case RADEON_HPD_3:
815 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0);
e0df1ac5
AD		 816 break;
817 default:
818 break;
819 }
820 }
fb98257a 821 disable |= 1 << radeon_connector->hpd.hpd;
e0df1ac5 822 }
fb98257a 823 radeon_irq_kms_disable_hpd(rdev, disable);
e0df1ac5
AD		 824}
825
771fe6b9 826/*
3ce0a23d 827 * R600 PCIE GART
771fe6b9 828 */
3ce0a23d
JG		 829void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
830{
831 unsigned i;
832 u32 tmp;
833
2e98f10a 834 /* flush hdp cache so updates hit vram */
f3886f85
AD		 835 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
836 !(rdev->flags & RADEON_IS_AGP)) {
c9a1be96 837 void __iomem *ptr = (void *)rdev->gart.ptr;
812d0469
AD		 838 u32 tmp;
839
840 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read
841 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL
f3886f85
AD		 842 * This seems to cause problems on some AGP cards. Just use the old
843 * method for them.
812d0469
AD		 844 */
845 WREG32(HDP_DEBUG1, 0);
846 tmp = readl((void __iomem *)ptr);
847 } else
848 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
2e98f10a 849
3ce0a23d
JG		 850 WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
851 WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
852 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
853 for (i = 0; i < rdev->usec_timeout; i++) {
854 /* read MC_STATUS */
855 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
856 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
857 if (tmp == 2) {
858 printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
859 return;
860 }
861 if (tmp) {
862 return;
863 }
864 udelay(1);
865 }
866}
867
4aac0473 868int r600_pcie_gart_init(struct radeon_device *rdev)
3ce0a23d 869{
4aac0473 870 int r;
3ce0a23d 871
c9a1be96 872 if (rdev->gart.robj) {
fce7d61b 873 WARN(1, "R600 PCIE GART already initialized\n");
4aac0473
JG		 874 return 0;
875 }
3ce0a23d
JG		 876 /* Initialize common gart structure */
877 r = radeon_gart_init(rdev);
4aac0473 878 if (r)
3ce0a23d 879 return r;
3ce0a23d 880 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
4aac0473
JG		 881 return radeon_gart_table_vram_alloc(rdev);
882}
883
1109ca09 884static int r600_pcie_gart_enable(struct radeon_device *rdev)
4aac0473
JG		 885{
886 u32 tmp;
887 int r, i;
888
c9a1be96 889 if (rdev->gart.robj == NULL) {
4aac0473
JG		 890 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
891 return -EINVAL;
771fe6b9 892 }
4aac0473
JG		 893 r = radeon_gart_table_vram_pin(rdev);
894 if (r)
895 return r;
82568565 896 radeon_gart_restore(rdev);
bc1a631e 897
3ce0a23d
JG		 898 /* Setup L2 cache */
899 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
900 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
901 EFFECTIVE_L2_QUEUE_SIZE(7));
902 WREG32(VM_L2_CNTL2, 0);
903 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
904 /* Setup TLB control */
905 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
906 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
907 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
908 ENABLE_WAIT_L2_QUERY;
909 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
910 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
911 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
912 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
913 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
914 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
915 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
916 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
917 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
918 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
919 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
920 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
921 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
922 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
923 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
1a029b76 924 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
3ce0a23d
JG		 925 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
926 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
927 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
928 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
929 (u32)(rdev->dummy_page.addr >> 12));
930 for (i = 1; i < 7; i++)
931 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
771fe6b9 932
3ce0a23d 933 r600_pcie_gart_tlb_flush(rdev);
fcf4de5a
TV		 934 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
935 (unsigned)(rdev->mc.gtt_size >> 20),
936 (unsigned long long)rdev->gart.table_addr);
3ce0a23d 937 rdev->gart.ready = true;
771fe6b9
JG		 938 return 0;
939}
940
1109ca09 941static void r600_pcie_gart_disable(struct radeon_device *rdev)
771fe6b9 942{
3ce0a23d 943 u32 tmp;
c9a1be96 944 int i;
771fe6b9 945
3ce0a23d
JG		 946 /* Disable all tables */
947 for (i = 0; i < 7; i++)
948 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
771fe6b9 949
3ce0a23d
JG		 950 /* Disable L2 cache */
951 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
952 EFFECTIVE_L2_QUEUE_SIZE(7));
953 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
954 /* Setup L1 TLB control */
955 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
956 ENABLE_WAIT_L2_QUERY;
957 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
958 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
959 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
960 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
961 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
962 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
963 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
964 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
965 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp);
966 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp);
967 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
968 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
969 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
970 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
c9a1be96 971 radeon_gart_table_vram_unpin(rdev);
4aac0473
JG		 972}
973
1109ca09 974static void r600_pcie_gart_fini(struct radeon_device *rdev)
4aac0473 975{
f9274562 976 radeon_gart_fini(rdev);
4aac0473
JG		 977 r600_pcie_gart_disable(rdev);
978 radeon_gart_table_vram_free(rdev);
771fe6b9
JG		 979}
980
1109ca09 981static void r600_agp_enable(struct radeon_device *rdev)
1a029b76
JG		 982{
983 u32 tmp;
984 int i;
985
986 /* Setup L2 cache */
987 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
988 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
989 EFFECTIVE_L2_QUEUE_SIZE(7));
990 WREG32(VM_L2_CNTL2, 0);
991 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
992 /* Setup TLB control */
993 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
994 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
995 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
996 ENABLE_WAIT_L2_QUERY;
997 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
998 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
999 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
1000 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
1001 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
1002 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
1003 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
1004 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
1005 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
1006 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
1007 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
1008 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
1009 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1010 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1011 for (i = 0; i < 7; i++)
1012 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
1013}
1014
771fe6b9
JG		 1015int r600_mc_wait_for_idle(struct radeon_device *rdev)
1016{
3ce0a23d
JG		 1017 unsigned i;
1018 u32 tmp;
1019
1020 for (i = 0; i < rdev->usec_timeout; i++) {
1021 /* read MC_STATUS */
1022 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00;
1023 if (!tmp)
1024 return 0;
1025 udelay(1);
1026 }
1027 return -1;
771fe6b9
JG		 1028}
1029
a3c1945a 1030static void r600_mc_program(struct radeon_device *rdev)
771fe6b9 1031{
a3c1945a 1032 struct rv515_mc_save save;
3ce0a23d
JG		 1033 u32 tmp;
1034 int i, j;
771fe6b9 1035
3ce0a23d
JG		 1036 /* Initialize HDP */
1037 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1038 WREG32((0x2c14 + j), 0x00000000);
1039 WREG32((0x2c18 + j), 0x00000000);
1040 WREG32((0x2c1c + j), 0x00000000);
1041 WREG32((0x2c20 + j), 0x00000000);
1042 WREG32((0x2c24 + j), 0x00000000);
1043 }
1044 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
771fe6b9 1045
a3c1945a 1046 rv515_mc_stop(rdev, &save);
3ce0a23d 1047 if (r600_mc_wait_for_idle(rdev)) {
a3c1945a 1048 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
3ce0a23d 1049 }
a3c1945a 1050 /* Lockout access through VGA aperture (doesn't exist before R600) */
3ce0a23d 1051 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
3ce0a23d 1052 /* Update configuration */
1a029b76
JG		 1053 if (rdev->flags & RADEON_IS_AGP) {
1054 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1055 /* VRAM before AGP */
1056 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1057 rdev->mc.vram_start >> 12);
1058 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1059 rdev->mc.gtt_end >> 12);
1060 } else {
1061 /* VRAM after AGP */
1062 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1063 rdev->mc.gtt_start >> 12);
1064 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1065 rdev->mc.vram_end >> 12);
1066 }
1067 } else {
1068 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
1069 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12);
1070 }
16cdf04d 1071 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12);
1a029b76 1072 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
3ce0a23d
JG		 1073 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1074 WREG32(MC_VM_FB_LOCATION, tmp);
1075 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1076 WREG32(HDP_NONSURFACE_INFO, (2 << 7));
46fcd2b3 1077 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
3ce0a23d 1078 if (rdev->flags & RADEON_IS_AGP) {
1a029b76
JG		 1079 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22);
1080 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22);
3ce0a23d
JG		 1081 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1082 } else {
1083 WREG32(MC_VM_AGP_BASE, 0);
1084 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1085 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1086 }
3ce0a23d 1087 if (r600_mc_wait_for_idle(rdev)) {
a3c1945a 1088 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
3ce0a23d 1089 }
a3c1945a 1090 rv515_mc_resume(rdev, &save);
698443d9
DA		 1091 /* we need to own VRAM, so turn off the VGA renderer here
1092 * to stop it overwriting our objects */
d39c3b89 1093 rv515_vga_render_disable(rdev);
3ce0a23d
JG		 1094}
1095
d594e46a
JG		 1096/**
1097 * r600_vram_gtt_location - try to find VRAM & GTT location
1098 * @rdev: radeon device structure holding all necessary informations
1099 * @mc: memory controller structure holding memory informations
1100 *
1101 * Function will place try to place VRAM at same place as in CPU (PCI)
1102 * address space as some GPU seems to have issue when we reprogram at
1103 * different address space.
1104 *
1105 * If there is not enough space to fit the unvisible VRAM after the
1106 * aperture then we limit the VRAM size to the aperture.
1107 *
1108 * If we are using AGP then place VRAM adjacent to AGP aperture are we need
1109 * them to be in one from GPU point of view so that we can program GPU to
1110 * catch access outside them (weird GPU policy see ??).
1111 *
1112 * This function will never fails, worst case are limiting VRAM or GTT.
1113 *
1114 * Note: GTT start, end, size should be initialized before calling this
1115 * function on AGP platform.
1116 */
0ef0c1f7 1117static void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
d594e46a
JG		 1118{
1119 u64 size_bf, size_af;
1120
1121 if (mc->mc_vram_size > 0xE0000000) {
1122 /* leave room for at least 512M GTT */
1123 dev_warn(rdev->dev, "limiting VRAM\n");
1124 mc->real_vram_size = 0xE0000000;
1125 mc->mc_vram_size = 0xE0000000;
1126 }
1127 if (rdev->flags & RADEON_IS_AGP) {
1128 size_bf = mc->gtt_start;
dfc6ae5b 1129 size_af = 0xFFFFFFFF - mc->gtt_end;
d594e46a
JG		 1130 if (size_bf > size_af) {
1131 if (mc->mc_vram_size > size_bf) {
1132 dev_warn(rdev->dev, "limiting VRAM\n");
1133 mc->real_vram_size = size_bf;
1134 mc->mc_vram_size = size_bf;
1135 }
1136 mc->vram_start = mc->gtt_start - mc->mc_vram_size;
1137 } else {
1138 if (mc->mc_vram_size > size_af) {
1139 dev_warn(rdev->dev, "limiting VRAM\n");
1140 mc->real_vram_size = size_af;
1141 mc->mc_vram_size = size_af;
1142 }
dfc6ae5b 1143 mc->vram_start = mc->gtt_end + 1;
d594e46a
JG		 1144 }
1145 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
1146 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
1147 mc->mc_vram_size >> 20, mc->vram_start,
1148 mc->vram_end, mc->real_vram_size >> 20);
1149 } else {
1150 u64 base = 0;
8961d52d
AD		 1151 if (rdev->flags & RADEON_IS_IGP) {
1152 base = RREG32(MC_VM_FB_LOCATION) & 0xFFFF;
1153 base <<= 24;
1154 }
d594e46a 1155 radeon_vram_location(rdev, &rdev->mc, base);
8d369bb1 1156 rdev->mc.gtt_base_align = 0;
d594e46a
JG		 1157 radeon_gtt_location(rdev, mc);
1158 }
1159}
1160
1109ca09 1161static int r600_mc_init(struct radeon_device *rdev)
771fe6b9 1162{
3ce0a23d 1163 u32 tmp;
5885b7a9 1164 int chansize, numchan;
771fe6b9 1165
3ce0a23d 1166 /* Get VRAM informations */
771fe6b9 1167 rdev->mc.vram_is_ddr = true;
3ce0a23d
JG		 1168 tmp = RREG32(RAMCFG);
1169 if (tmp & CHANSIZE_OVERRIDE) {
771fe6b9 1170 chansize = 16;
3ce0a23d 1171 } else if (tmp & CHANSIZE_MASK) {
771fe6b9
JG		 1172 chansize = 64;
1173 } else {
1174 chansize = 32;
1175 }
5885b7a9
AD		 1176 tmp = RREG32(CHMAP);
1177 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1178 case 0:
1179 default:
1180 numchan = 1;
1181 break;
1182 case 1:
1183 numchan = 2;
1184 break;
1185 case 2:
1186 numchan = 4;
1187 break;
1188 case 3:
1189 numchan = 8;
1190 break;
771fe6b9 1191 }
5885b7a9 1192 rdev->mc.vram_width = numchan * chansize;
3ce0a23d 1193 /* Could aper size report 0 ? */
01d73a69
JC		 1194 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
1195 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
3ce0a23d
JG		 1196 /* Setup GPU memory space */
1197 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
1198 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
51e5fcd3 1199 rdev->mc.visible_vram_size = rdev->mc.aper_size;
d594e46a 1200 r600_vram_gtt_location(rdev, &rdev->mc);
f47299c5 1201
f892034a
AD		 1202 if (rdev->flags & RADEON_IS_IGP) {
1203 rs690_pm_info(rdev);
06b6476d 1204 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
f892034a 1205 }
f47299c5 1206 radeon_update_bandwidth_info(rdev);
3ce0a23d 1207 return 0;
771fe6b9
JG		 1208}
1209
16cdf04d
AD		 1210int r600_vram_scratch_init(struct radeon_device *rdev)
1211{
1212 int r;
1213
1214 if (rdev->vram_scratch.robj == NULL) {
1215 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE,
1216 PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
40f5cf99 1217 NULL, &rdev->vram_scratch.robj);
16cdf04d
AD		 1218 if (r) {
1219 return r;
1220 }
1221 }
1222
1223 r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
1224 if (unlikely(r != 0))
1225 return r;
1226 r = radeon_bo_pin(rdev->vram_scratch.robj,
1227 RADEON_GEM_DOMAIN_VRAM, &rdev->vram_scratch.gpu_addr);
1228 if (r) {
1229 radeon_bo_unreserve(rdev->vram_scratch.robj);
1230 return r;
1231 }
1232 r = radeon_bo_kmap(rdev->vram_scratch.robj,
1233 (void **)&rdev->vram_scratch.ptr);
1234 if (r)
1235 radeon_bo_unpin(rdev->vram_scratch.robj);
1236 radeon_bo_unreserve(rdev->vram_scratch.robj);
1237
1238 return r;
1239}
1240
1241void r600_vram_scratch_fini(struct radeon_device *rdev)
1242{
1243 int r;
1244
1245 if (rdev->vram_scratch.robj == NULL) {
1246 return;
1247 }
1248 r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
1249 if (likely(r == 0)) {
1250 radeon_bo_kunmap(rdev->vram_scratch.robj);
1251 radeon_bo_unpin(rdev->vram_scratch.robj);
1252 radeon_bo_unreserve(rdev->vram_scratch.robj);
1253 }
1254 radeon_bo_unref(&rdev->vram_scratch.robj);
1255}
1256
410a3418
AD		 1257void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung)
1258{
1259 u32 tmp = RREG32(R600_BIOS_3_SCRATCH);
1260
1261 if (hung)
1262 tmp |= ATOM_S3_ASIC_GUI_ENGINE_HUNG;
1263 else
1264 tmp &= ~ATOM_S3_ASIC_GUI_ENGINE_HUNG;
1265
1266 WREG32(R600_BIOS_3_SCRATCH, tmp);
1267}
1268
3ce0a23d
JG		 1269/* We doesn't check that the GPU really needs a reset we simply do the
1270 * reset, it's up to the caller to determine if the GPU needs one. We
1271 * might add an helper function to check that.
1272 */
71e3d157 1273static void r600_gpu_soft_reset_gfx(struct radeon_device *rdev)
771fe6b9 1274{
3ce0a23d
JG		 1275 u32 grbm_busy_mask = S_008010_VC_BUSY(1) | S_008010_VGT_BUSY_NO_DMA(1) |
1276 S_008010_VGT_BUSY(1) | S_008010_TA03_BUSY(1) |
1277 S_008010_TC_BUSY(1) | S_008010_SX_BUSY(1) |
1278 S_008010_SH_BUSY(1) | S_008010_SPI03_BUSY(1) |
1279 S_008010_SMX_BUSY(1) | S_008010_SC_BUSY(1) |
1280 S_008010_PA_BUSY(1) | S_008010_DB03_BUSY(1) |
1281 S_008010_CR_BUSY(1) | S_008010_CB03_BUSY(1) |
1282 S_008010_GUI_ACTIVE(1);
1283 u32 grbm2_busy_mask = S_008014_SPI0_BUSY(1) | S_008014_SPI1_BUSY(1) |
1284 S_008014_SPI2_BUSY(1) | S_008014_SPI3_BUSY(1) |
1285 S_008014_TA0_BUSY(1) | S_008014_TA1_BUSY(1) |
1286 S_008014_TA2_BUSY(1) | S_008014_TA3_BUSY(1) |
1287 S_008014_DB0_BUSY(1) | S_008014_DB1_BUSY(1) |
1288 S_008014_DB2_BUSY(1) | S_008014_DB3_BUSY(1) |
1289 S_008014_CB0_BUSY(1) | S_008014_CB1_BUSY(1) |
1290 S_008014_CB2_BUSY(1) | S_008014_CB3_BUSY(1);
a3c1945a 1291 u32 tmp;
771fe6b9 1292
8d96fe93 1293 if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
71e3d157 1294 return;
8d96fe93 1295
64c56e8c 1296 dev_info(rdev->dev, " R_008010_GRBM_STATUS = 0x%08X\n",
1a029b76 1297 RREG32(R_008010_GRBM_STATUS));
64c56e8c 1298 dev_info(rdev->dev, " R_008014_GRBM_STATUS2 = 0x%08X\n",
a3c1945a 1299 RREG32(R_008014_GRBM_STATUS2));
64c56e8c 1300 dev_info(rdev->dev, " R_000E50_SRBM_STATUS = 0x%08X\n",
1a029b76 1301 RREG32(R_000E50_SRBM_STATUS));
440a7cd8
JG		 1302 dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n",
1303 RREG32(CP_STALLED_STAT1));
1304 dev_info(rdev->dev, " R_008678_CP_STALLED_STAT2 = 0x%08X\n",
1305 RREG32(CP_STALLED_STAT2));
1306 dev_info(rdev->dev, " R_00867C_CP_BUSY_STAT = 0x%08X\n",
1307 RREG32(CP_BUSY_STAT));
1308 dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n",
1309 RREG32(CP_STAT));
64c56e8c 1310
3ce0a23d 1311 /* Disable CP parsing/prefetching */
90aca4d2 1312 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
64c56e8c 1313
3ce0a23d
JG		 1314 /* Check if any of the rendering block is busy and reset it */
1315 if ((RREG32(R_008010_GRBM_STATUS) & grbm_busy_mask) ||
1316 (RREG32(R_008014_GRBM_STATUS2) & grbm2_busy_mask)) {
a3c1945a 1317 tmp = S_008020_SOFT_RESET_CR(1) |
3ce0a23d
JG		 1318 S_008020_SOFT_RESET_DB(1) |
1319 S_008020_SOFT_RESET_CB(1) |
1320 S_008020_SOFT_RESET_PA(1) |
1321 S_008020_SOFT_RESET_SC(1) |
1322 S_008020_SOFT_RESET_SMX(1) |
1323 S_008020_SOFT_RESET_SPI(1) |
1324 S_008020_SOFT_RESET_SX(1) |
1325 S_008020_SOFT_RESET_SH(1) |
1326 S_008020_SOFT_RESET_TC(1) |
1327 S_008020_SOFT_RESET_TA(1) |
1328 S_008020_SOFT_RESET_VC(1) |
a3c1945a 1329 S_008020_SOFT_RESET_VGT(1);
1a029b76 1330 dev_info(rdev->dev, " R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
a3c1945a 1331 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
90aca4d2
JG		 1332 RREG32(R_008020_GRBM_SOFT_RESET);
1333 mdelay(15);
3ce0a23d 1334 WREG32(R_008020_GRBM_SOFT_RESET, 0);
3ce0a23d
JG		 1335 }
1336 /* Reset CP (we always reset CP) */
a3c1945a
JG		 1337 tmp = S_008020_SOFT_RESET_CP(1);
1338 dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
1339 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
90aca4d2
JG		 1340 RREG32(R_008020_GRBM_SOFT_RESET);
1341 mdelay(15);
3ce0a23d 1342 WREG32(R_008020_GRBM_SOFT_RESET, 0);
71e3d157 1343
64c56e8c 1344 dev_info(rdev->dev, " R_008010_GRBM_STATUS = 0x%08X\n",
1a029b76 1345 RREG32(R_008010_GRBM_STATUS));
64c56e8c 1346 dev_info(rdev->dev, " R_008014_GRBM_STATUS2 = 0x%08X\n",
1a029b76 1347 RREG32(R_008014_GRBM_STATUS2));
64c56e8c 1348 dev_info(rdev->dev, " R_000E50_SRBM_STATUS = 0x%08X\n",
1a029b76 1349 RREG32(R_000E50_SRBM_STATUS));
440a7cd8
JG		 1350 dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n",
1351 RREG32(CP_STALLED_STAT1));
1352 dev_info(rdev->dev, " R_008678_CP_STALLED_STAT2 = 0x%08X\n",
1353 RREG32(CP_STALLED_STAT2));
1354 dev_info(rdev->dev, " R_00867C_CP_BUSY_STAT = 0x%08X\n",
1355 RREG32(CP_BUSY_STAT));
1356 dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n",
1357 RREG32(CP_STAT));
71e3d157
AD		 1358
1359}
1360
1361static void r600_gpu_soft_reset_dma(struct radeon_device *rdev)
1362{
1363 u32 tmp;
1364
1365 if (RREG32(DMA_STATUS_REG) & DMA_IDLE)
1366 return;
1367
eaaa6983
JG		 1368 dev_info(rdev->dev, " R_00D034_DMA_STATUS_REG = 0x%08X\n",
1369 RREG32(DMA_STATUS_REG));
71e3d157
AD		 1370
1371 /* Disable DMA */
1372 tmp = RREG32(DMA_RB_CNTL);
1373 tmp &= ~DMA_RB_ENABLE;
1374 WREG32(DMA_RB_CNTL, tmp);
1375
1376 /* Reset dma */
1377 if (rdev->family >= CHIP_RV770)
1378 WREG32(SRBM_SOFT_RESET, RV770_SOFT_RESET_DMA);
1379 else
1380 WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA);
1381 RREG32(SRBM_SOFT_RESET);
1382 udelay(50);
1383 WREG32(SRBM_SOFT_RESET, 0);
1384
1385 dev_info(rdev->dev, " R_00D034_DMA_STATUS_REG = 0x%08X\n",
1386 RREG32(DMA_STATUS_REG));
1387}
1388
1389static int r600_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
1390{
1391 struct rv515_mc_save save;
1392
19fc42ed
AD		 1393 if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
1394 reset_mask &= ~(RADEON_RESET_GFX | RADEON_RESET_COMPUTE);
1395
1396 if (RREG32(DMA_STATUS_REG) & DMA_IDLE)
1397 reset_mask &= ~RADEON_RESET_DMA;
1398
71e3d157
AD		 1399 if (reset_mask == 0)
1400 return 0;
1401
1402 dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);
1403
410a3418
AD		 1404 r600_set_bios_scratch_engine_hung(rdev, true);
1405
71e3d157
AD		 1406 rv515_mc_stop(rdev, &save);
1407 if (r600_mc_wait_for_idle(rdev)) {
1408 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1409 }
1410
1411 if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE))
1412 r600_gpu_soft_reset_gfx(rdev);
1413
1414 if (reset_mask & RADEON_RESET_DMA)
1415 r600_gpu_soft_reset_dma(rdev);
1416
1417 /* Wait a little for things to settle down */
1418 mdelay(1);
1419
a3c1945a 1420 rv515_mc_resume(rdev, &save);
410a3418
AD		 1421
1422 r600_set_bios_scratch_engine_hung(rdev, false);
1423
3ce0a23d
JG		 1424 return 0;
1425}
1426
e32eb50d 1427bool r600_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
225758d8
JG		 1428{
1429 u32 srbm_status;
1430 u32 grbm_status;
1431 u32 grbm_status2;
225758d8
JG		 1432
1433 srbm_status = RREG32(R_000E50_SRBM_STATUS);
1434 grbm_status = RREG32(R_008010_GRBM_STATUS);
1435 grbm_status2 = RREG32(R_008014_GRBM_STATUS2);
1436 if (!G_008010_GUI_ACTIVE(grbm_status)) {
069211e5 1437 radeon_ring_lockup_update(ring);
225758d8
JG		 1438 return false;
1439 }
1440 /* force CP activities */
7b9ef16b 1441 radeon_ring_force_activity(rdev, ring);
069211e5 1442 return radeon_ring_test_lockup(rdev, ring);
225758d8
JG		 1443}
1444
4d75658b
AD		 1445/**
1446 * r600_dma_is_lockup - Check if the DMA engine is locked up
1447 *
1448 * @rdev: radeon_device pointer
1449 * @ring: radeon_ring structure holding ring information
1450 *
1451 * Check if the async DMA engine is locked up (r6xx-evergreen).
1452 * Returns true if the engine appears to be locked up, false if not.
1453 */
1454bool r600_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
1455{
1456 u32 dma_status_reg;
1457
1458 dma_status_reg = RREG32(DMA_STATUS_REG);
1459 if (dma_status_reg & DMA_IDLE) {
1460 radeon_ring_lockup_update(ring);
1461 return false;
1462 }
1463 /* force ring activities */
1464 radeon_ring_force_activity(rdev, ring);
1465 return radeon_ring_test_lockup(rdev, ring);
1466}
1467
a2d07b74 1468int r600_asic_reset(struct radeon_device *rdev)
3ce0a23d 1469{
71e3d157
AD		 1470 return r600_gpu_soft_reset(rdev, (RADEON_RESET_GFX |
1471 RADEON_RESET_COMPUTE |
1472 RADEON_RESET_DMA));
3ce0a23d
JG		 1473}
1474
416a2bd2
AD		 1475u32 r6xx_remap_render_backend(struct radeon_device *rdev,
1476 u32 tiling_pipe_num,
1477 u32 max_rb_num,
1478 u32 total_max_rb_num,
1479 u32 disabled_rb_mask)
3ce0a23d 1480{
416a2bd2 1481 u32 rendering_pipe_num, rb_num_width, req_rb_num;
f689e3ac 1482 u32 pipe_rb_ratio, pipe_rb_remain, tmp;
416a2bd2
AD		 1483 u32 data = 0, mask = 1 << (max_rb_num - 1);
1484 unsigned i, j;
3ce0a23d 1485
416a2bd2 1486 /* mask out the RBs that don't exist on that asic */
f689e3ac
MT		 1487 tmp = disabled_rb_mask | ((0xff << max_rb_num) & 0xff);
1488 /* make sure at least one RB is available */
1489 if ((tmp & 0xff) != 0xff)
1490 disabled_rb_mask = tmp;
3ce0a23d 1491
416a2bd2
AD		 1492 rendering_pipe_num = 1 << tiling_pipe_num;
1493 req_rb_num = total_max_rb_num - r600_count_pipe_bits(disabled_rb_mask);
1494 BUG_ON(rendering_pipe_num < req_rb_num);
3ce0a23d 1495
416a2bd2
AD		 1496 pipe_rb_ratio = rendering_pipe_num / req_rb_num;
1497 pipe_rb_remain = rendering_pipe_num - pipe_rb_ratio * req_rb_num;
3ce0a23d 1498
416a2bd2
AD		 1499 if (rdev->family <= CHIP_RV740) {
1500 /* r6xx/r7xx */
1501 rb_num_width = 2;
1502 } else {
1503 /* eg+ */
1504 rb_num_width = 4;
1505 }
3ce0a23d 1506
416a2bd2
AD		 1507 for (i = 0; i < max_rb_num; i++) {
1508 if (!(mask & disabled_rb_mask)) {
1509 for (j = 0; j < pipe_rb_ratio; j++) {
1510 data <<= rb_num_width;
1511 data |= max_rb_num - i - 1;
1512 }
1513 if (pipe_rb_remain) {
1514 data <<= rb_num_width;
1515 data |= max_rb_num - i - 1;
1516 pipe_rb_remain--;
1517 }
1518 }
1519 mask >>= 1;
3ce0a23d
JG		 1520 }
1521
416a2bd2 1522 return data;
3ce0a23d
JG		 1523}
1524
1525int r600_count_pipe_bits(uint32_t val)
1526{
ef8cf3a1 1527 return hweight32(val);
771fe6b9
JG		 1528}
1529
1109ca09 1530static void r600_gpu_init(struct radeon_device *rdev)
3ce0a23d
JG		 1531{
1532 u32 tiling_config;
1533 u32 ramcfg;
d03f5d59
AD		 1534 u32 cc_rb_backend_disable;
1535 u32 cc_gc_shader_pipe_config;
3ce0a23d
JG		 1536 u32 tmp;
1537 int i, j;
1538 u32 sq_config;
1539 u32 sq_gpr_resource_mgmt_1 = 0;
1540 u32 sq_gpr_resource_mgmt_2 = 0;
1541 u32 sq_thread_resource_mgmt = 0;
1542 u32 sq_stack_resource_mgmt_1 = 0;
1543 u32 sq_stack_resource_mgmt_2 = 0;
416a2bd2 1544 u32 disabled_rb_mask;
3ce0a23d 1545
416a2bd2 1546 rdev->config.r600.tiling_group_size = 256;
3ce0a23d
JG		 1547 switch (rdev->family) {
1548 case CHIP_R600:
1549 rdev->config.r600.max_pipes = 4;
1550 rdev->config.r600.max_tile_pipes = 8;
1551 rdev->config.r600.max_simds = 4;
1552 rdev->config.r600.max_backends = 4;
1553 rdev->config.r600.max_gprs = 256;
1554 rdev->config.r600.max_threads = 192;
1555 rdev->config.r600.max_stack_entries = 256;
1556 rdev->config.r600.max_hw_contexts = 8;
1557 rdev->config.r600.max_gs_threads = 16;
1558 rdev->config.r600.sx_max_export_size = 128;
1559 rdev->config.r600.sx_max_export_pos_size = 16;
1560 rdev->config.r600.sx_max_export_smx_size = 128;
1561 rdev->config.r600.sq_num_cf_insts = 2;
1562 break;
1563 case CHIP_RV630:
1564 case CHIP_RV635:
1565 rdev->config.r600.max_pipes = 2;
1566 rdev->config.r600.max_tile_pipes = 2;
1567 rdev->config.r600.max_simds = 3;
1568 rdev->config.r600.max_backends = 1;
1569 rdev->config.r600.max_gprs = 128;
1570 rdev->config.r600.max_threads = 192;
1571 rdev->config.r600.max_stack_entries = 128;
1572 rdev->config.r600.max_hw_contexts = 8;
1573 rdev->config.r600.max_gs_threads = 4;
1574 rdev->config.r600.sx_max_export_size = 128;
1575 rdev->config.r600.sx_max_export_pos_size = 16;
1576 rdev->config.r600.sx_max_export_smx_size = 128;
1577 rdev->config.r600.sq_num_cf_insts = 2;
1578 break;
1579 case CHIP_RV610:
1580 case CHIP_RV620:
1581 case CHIP_RS780:
1582 case CHIP_RS880:
1583 rdev->config.r600.max_pipes = 1;
1584 rdev->config.r600.max_tile_pipes = 1;
1585 rdev->config.r600.max_simds = 2;
1586 rdev->config.r600.max_backends = 1;
1587 rdev->config.r600.max_gprs = 128;
1588 rdev->config.r600.max_threads = 192;
1589 rdev->config.r600.max_stack_entries = 128;
1590 rdev->config.r600.max_hw_contexts = 4;
1591 rdev->config.r600.max_gs_threads = 4;
1592 rdev->config.r600.sx_max_export_size = 128;
1593 rdev->config.r600.sx_max_export_pos_size = 16;
1594 rdev->config.r600.sx_max_export_smx_size = 128;
1595 rdev->config.r600.sq_num_cf_insts = 1;
1596 break;
1597 case CHIP_RV670:
1598 rdev->config.r600.max_pipes = 4;
1599 rdev->config.r600.max_tile_pipes = 4;
1600 rdev->config.r600.max_simds = 4;
1601 rdev->config.r600.max_backends = 4;
1602 rdev->config.r600.max_gprs = 192;
1603 rdev->config.r600.max_threads = 192;
1604 rdev->config.r600.max_stack_entries = 256;
1605 rdev->config.r600.max_hw_contexts = 8;
1606 rdev->config.r600.max_gs_threads = 16;
1607 rdev->config.r600.sx_max_export_size = 128;
1608 rdev->config.r600.sx_max_export_pos_size = 16;
1609 rdev->config.r600.sx_max_export_smx_size = 128;
1610 rdev->config.r600.sq_num_cf_insts = 2;
1611 break;
1612 default:
1613 break;
1614 }
1615
1616 /* Initialize HDP */
1617 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1618 WREG32((0x2c14 + j), 0x00000000);
1619 WREG32((0x2c18 + j), 0x00000000);
1620 WREG32((0x2c1c + j), 0x00000000);
1621 WREG32((0x2c20 + j), 0x00000000);
1622 WREG32((0x2c24 + j), 0x00000000);
1623 }
1624
1625 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1626
1627 /* Setup tiling */
1628 tiling_config = 0;
1629 ramcfg = RREG32(RAMCFG);
1630 switch (rdev->config.r600.max_tile_pipes) {
1631 case 1:
1632 tiling_config |= PIPE_TILING(0);
1633 break;
1634 case 2:
1635 tiling_config |= PIPE_TILING(1);
1636 break;
1637 case 4:
1638 tiling_config |= PIPE_TILING(2);
1639 break;
1640 case 8:
1641 tiling_config |= PIPE_TILING(3);
1642 break;
1643 default:
1644 break;
1645 }
d03f5d59 1646 rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes;
961fb597 1647 rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
3ce0a23d 1648 tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
881fe6c1 1649 tiling_config |= GROUP_SIZE((ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
416a2bd2 1650
3ce0a23d
JG		 1651 tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
1652 if (tmp > 3) {
1653 tiling_config |= ROW_TILING(3);
1654 tiling_config |= SAMPLE_SPLIT(3);
1655 } else {
1656 tiling_config |= ROW_TILING(tmp);
1657 tiling_config |= SAMPLE_SPLIT(tmp);
1658 }
1659 tiling_config |= BANK_SWAPS(1);
d03f5d59
AD		 1660
1661 cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000;
416a2bd2
AD		 1662 tmp = R6XX_MAX_BACKENDS -
1663 r600_count_pipe_bits((cc_rb_backend_disable >> 16) & R6XX_MAX_BACKENDS_MASK);
1664 if (tmp < rdev->config.r600.max_backends) {
1665 rdev->config.r600.max_backends = tmp;
1666 }
1667
1668 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0x00ffff00;
1669 tmp = R6XX_MAX_PIPES -
1670 r600_count_pipe_bits((cc_gc_shader_pipe_config >> 8) & R6XX_MAX_PIPES_MASK);
1671 if (tmp < rdev->config.r600.max_pipes) {
1672 rdev->config.r600.max_pipes = tmp;
1673 }
1674 tmp = R6XX_MAX_SIMDS -
1675 r600_count_pipe_bits((cc_gc_shader_pipe_config >> 16) & R6XX_MAX_SIMDS_MASK);
1676 if (tmp < rdev->config.r600.max_simds) {
1677 rdev->config.r600.max_simds = tmp;
1678 }
1679
1680 disabled_rb_mask = (RREG32(CC_RB_BACKEND_DISABLE) >> 16) & R6XX_MAX_BACKENDS_MASK;
1681 tmp = (tiling_config & PIPE_TILING__MASK) >> PIPE_TILING__SHIFT;
1682 tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.r600.max_backends,
1683 R6XX_MAX_BACKENDS, disabled_rb_mask);
1684 tiling_config |= tmp << 16;
1685 rdev->config.r600.backend_map = tmp;
1686
e7aeeba6 1687 rdev->config.r600.tile_config = tiling_config;
3ce0a23d
JG		 1688 WREG32(GB_TILING_CONFIG, tiling_config);
1689 WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff);
1690 WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff);
4d75658b 1691 WREG32(DMA_TILING_CONFIG, tiling_config & 0xffff);
3ce0a23d 1692
d03f5d59 1693 tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
3ce0a23d
JG		 1694 WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);
1695 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK);
1696
1697 /* Setup some CP states */
1698 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b)));
1699 WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40)));
1700
1701 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT |
1702 SYNC_WALKER | SYNC_ALIGNER));
1703 /* Setup various GPU states */
1704 if (rdev->family == CHIP_RV670)
1705 WREG32(ARB_GDEC_RD_CNTL, 0x00000021);
1706
1707 tmp = RREG32(SX_DEBUG_1);
1708 tmp |= SMX_EVENT_RELEASE;
1709 if ((rdev->family > CHIP_R600))
1710 tmp |= ENABLE_NEW_SMX_ADDRESS;
1711 WREG32(SX_DEBUG_1, tmp);
1712
1713 if (((rdev->family) == CHIP_R600) ||
1714 ((rdev->family) == CHIP_RV630) ||
1715 ((rdev->family) == CHIP_RV610) ||
1716 ((rdev->family) == CHIP_RV620) ||
ee59f2b4
AD		 1717 ((rdev->family) == CHIP_RS780) ||
1718 ((rdev->family) == CHIP_RS880)) {
3ce0a23d
JG		 1719 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE);
1720 } else {
1721 WREG32(DB_DEBUG, 0);
1722 }
1723 WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) |
1724 DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4)));
1725
1726 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1727 WREG32(VGT_NUM_INSTANCES, 0);
1728
1729 WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
1730 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0));
1731
1732 tmp = RREG32(SQ_MS_FIFO_SIZES);
1733 if (((rdev->family) == CHIP_RV610) ||
1734 ((rdev->family) == CHIP_RV620) ||
ee59f2b4
AD		 1735 ((rdev->family) == CHIP_RS780) ||
1736 ((rdev->family) == CHIP_RS880)) {
3ce0a23d
JG		 1737 tmp = (CACHE_FIFO_SIZE(0xa) |
1738 FETCH_FIFO_HIWATER(0xa) |
1739 DONE_FIFO_HIWATER(0xe0) |
1740 ALU_UPDATE_FIFO_HIWATER(0x8));
1741 } else if (((rdev->family) == CHIP_R600) ||
1742 ((rdev->family) == CHIP_RV630)) {
1743 tmp &= ~DONE_FIFO_HIWATER(0xff);
1744 tmp |= DONE_FIFO_HIWATER(0x4);
1745 }
1746 WREG32(SQ_MS_FIFO_SIZES, tmp);
1747
1748 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
1749 * should be adjusted as needed by the 2D/3D drivers. This just sets default values
1750 */
1751 sq_config = RREG32(SQ_CONFIG);
1752 sq_config &= ~(PS_PRIO(3) |
1753 VS_PRIO(3) |
1754 GS_PRIO(3) |
1755 ES_PRIO(3));
1756 sq_config |= (DX9_CONSTS |
1757 VC_ENABLE |
1758 PS_PRIO(0) |
1759 VS_PRIO(1) |
1760 GS_PRIO(2) |
1761 ES_PRIO(3));
1762
1763 if ((rdev->family) == CHIP_R600) {
1764 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) |
1765 NUM_VS_GPRS(124) |
1766 NUM_CLAUSE_TEMP_GPRS(4));
1767 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) |
1768 NUM_ES_GPRS(0));
1769 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) |
1770 NUM_VS_THREADS(48) |
1771 NUM_GS_THREADS(4) |
1772 NUM_ES_THREADS(4));
1773 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) |
1774 NUM_VS_STACK_ENTRIES(128));
1775 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) |
1776 NUM_ES_STACK_ENTRIES(0));
1777 } else if (((rdev->family) == CHIP_RV610) ||
1778 ((rdev->family) == CHIP_RV620) ||
ee59f2b4
AD		 1779 ((rdev->family) == CHIP_RS780) ||
1780 ((rdev->family) == CHIP_RS880)) {
3ce0a23d
JG		 1781 /* no vertex cache */
1782 sq_config &= ~VC_ENABLE;
1783
1784 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1785 NUM_VS_GPRS(44) |
1786 NUM_CLAUSE_TEMP_GPRS(2));
1787 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1788 NUM_ES_GPRS(17));
1789 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1790 NUM_VS_THREADS(78) |
1791 NUM_GS_THREADS(4) |
1792 NUM_ES_THREADS(31));
1793 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1794 NUM_VS_STACK_ENTRIES(40));
1795 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1796 NUM_ES_STACK_ENTRIES(16));
1797 } else if (((rdev->family) == CHIP_RV630) ||
1798 ((rdev->family) == CHIP_RV635)) {
1799 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1800 NUM_VS_GPRS(44) |
1801 NUM_CLAUSE_TEMP_GPRS(2));
1802 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) |
1803 NUM_ES_GPRS(18));
1804 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1805 NUM_VS_THREADS(78) |
1806 NUM_GS_THREADS(4) |
1807 NUM_ES_THREADS(31));
1808 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1809 NUM_VS_STACK_ENTRIES(40));
1810 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1811 NUM_ES_STACK_ENTRIES(16));
1812 } else if ((rdev->family) == CHIP_RV670) {
1813 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1814 NUM_VS_GPRS(44) |
1815 NUM_CLAUSE_TEMP_GPRS(2));
1816 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1817 NUM_ES_GPRS(17));
1818 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1819 NUM_VS_THREADS(78) |
1820 NUM_GS_THREADS(4) |
1821 NUM_ES_THREADS(31));
1822 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) |
1823 NUM_VS_STACK_ENTRIES(64));
1824 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) |
1825 NUM_ES_STACK_ENTRIES(64));
1826 }
1827
1828 WREG32(SQ_CONFIG, sq_config);
1829 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
1830 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
1831 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1832 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
1833 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
1834
1835 if (((rdev->family) == CHIP_RV610) ||
1836 ((rdev->family) == CHIP_RV620) ||
ee59f2b4
AD		 1837 ((rdev->family) == CHIP_RS780) ||
1838 ((rdev->family) == CHIP_RS880)) {
3ce0a23d
JG		 1839 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY));
1840 } else {
1841 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC));
1842 }
1843
1844 /* More default values. 2D/3D driver should adjust as needed */
1845 WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) |
1846 S1_X(0x4) | S1_Y(0xc)));
1847 WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) |
1848 S1_X(0x2) | S1_Y(0x2) |
1849 S2_X(0xa) | S2_Y(0x6) |
1850 S3_X(0x6) | S3_Y(0xa)));
1851 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) |
1852 S1_X(0x4) | S1_Y(0xc) |
1853 S2_X(0x1) | S2_Y(0x6) |
1854 S3_X(0xa) | S3_Y(0xe)));
1855 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) |
1856 S5_X(0x0) | S5_Y(0x0) |
1857 S6_X(0xb) | S6_Y(0x4) |
1858 S7_X(0x7) | S7_Y(0x8)));
1859
1860 WREG32(VGT_STRMOUT_EN, 0);
1861 tmp = rdev->config.r600.max_pipes * 16;
1862 switch (rdev->family) {
1863 case CHIP_RV610:
3ce0a23d 1864 case CHIP_RV620:
ee59f2b4
AD		 1865 case CHIP_RS780:
1866 case CHIP_RS880:
3ce0a23d
JG		 1867 tmp += 32;
1868 break;
1869 case CHIP_RV670:
1870 tmp += 128;
1871 break;
1872 default:
1873 break;
1874 }
1875 if (tmp > 256) {
1876 tmp = 256;
1877 }
1878 WREG32(VGT_ES_PER_GS, 128);
1879 WREG32(VGT_GS_PER_ES, tmp);
1880 WREG32(VGT_GS_PER_VS, 2);
1881 WREG32(VGT_GS_VERTEX_REUSE, 16);
1882
1883 /* more default values. 2D/3D driver should adjust as needed */
1884 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1885 WREG32(VGT_STRMOUT_EN, 0);
1886 WREG32(SX_MISC, 0);
1887 WREG32(PA_SC_MODE_CNTL, 0);
1888 WREG32(PA_SC_AA_CONFIG, 0);
1889 WREG32(PA_SC_LINE_STIPPLE, 0);
1890 WREG32(SPI_INPUT_Z, 0);
1891 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
1892 WREG32(CB_COLOR7_FRAG, 0);
1893
1894 /* Clear render buffer base addresses */
1895 WREG32(CB_COLOR0_BASE, 0);
1896 WREG32(CB_COLOR1_BASE, 0);
1897 WREG32(CB_COLOR2_BASE, 0);
1898 WREG32(CB_COLOR3_BASE, 0);
1899 WREG32(CB_COLOR4_BASE, 0);
1900 WREG32(CB_COLOR5_BASE, 0);
1901 WREG32(CB_COLOR6_BASE, 0);
1902 WREG32(CB_COLOR7_BASE, 0);
1903 WREG32(CB_COLOR7_FRAG, 0);
1904
1905 switch (rdev->family) {
1906 case CHIP_RV610:
3ce0a23d 1907 case CHIP_RV620:
ee59f2b4
AD		 1908 case CHIP_RS780:
1909 case CHIP_RS880:
3ce0a23d
JG		 1910 tmp = TC_L2_SIZE(8);
1911 break;
1912 case CHIP_RV630:
1913 case CHIP_RV635:
1914 tmp = TC_L2_SIZE(4);
1915 break;
1916 case CHIP_R600:
1917 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT;
1918 break;
1919 default:
1920 tmp = TC_L2_SIZE(0);
1921 break;
1922 }
1923 WREG32(TC_CNTL, tmp);
1924
1925 tmp = RREG32(HDP_HOST_PATH_CNTL);
1926 WREG32(HDP_HOST_PATH_CNTL, tmp);
1927
1928 tmp = RREG32(ARB_POP);
1929 tmp |= ENABLE_TC128;
1930 WREG32(ARB_POP, tmp);
1931
1932 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1933 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
1934 NUM_CLIP_SEQ(3)));
1935 WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));
b866d133 1936 WREG32(VC_ENHANCE, 0);
3ce0a23d
JG		 1937}
1938
1939
771fe6b9
JG		 1940/*
1941 * Indirect registers accessor
1942 */
3ce0a23d
JG		 1943u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg)
1944{
1945 u32 r;
1946
1947 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1948 (void)RREG32(PCIE_PORT_INDEX);
1949 r = RREG32(PCIE_PORT_DATA);
1950 return r;
1951}
1952
1953void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
1954{
1955 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1956 (void)RREG32(PCIE_PORT_INDEX);
1957 WREG32(PCIE_PORT_DATA, (v));
1958 (void)RREG32(PCIE_PORT_DATA);
1959}
1960
3ce0a23d
JG		 1961/*
1962 * CP & Ring
1963 */
1964void r600_cp_stop(struct radeon_device *rdev)
1965{
53595338 1966 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
3ce0a23d 1967 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
724c80e1 1968 WREG32(SCRATCH_UMSK, 0);
4d75658b 1969 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
3ce0a23d
JG		 1970}
1971
d8f60cfc 1972int r600_init_microcode(struct radeon_device *rdev)
3ce0a23d
JG		 1973{
1974 struct platform_device *pdev;
1975 const char *chip_name;
d8f60cfc
AD		 1976 const char *rlc_chip_name;
1977 size_t pfp_req_size, me_req_size, rlc_req_size;
3ce0a23d
JG		 1978 char fw_name[30];
1979 int err;
1980
1981 DRM_DEBUG("\n");
1982
1983 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
1984 err = IS_ERR(pdev);
1985 if (err) {
1986 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
1987 return -EINVAL;
1988 }
1989
1990 switch (rdev->family) {
d8f60cfc
AD		 1991 case CHIP_R600:
1992 chip_name = "R600";
1993 rlc_chip_name = "R600";
1994 break;
1995 case CHIP_RV610:
1996 chip_name = "RV610";
1997 rlc_chip_name = "R600";
1998 break;
1999 case CHIP_RV630:
2000 chip_name = "RV630";
2001 rlc_chip_name = "R600";
2002 break;
2003 case CHIP_RV620:
2004 chip_name = "RV620";
2005 rlc_chip_name = "R600";
2006 break;
2007 case CHIP_RV635:
2008 chip_name = "RV635";
2009 rlc_chip_name = "R600";
2010 break;
2011 case CHIP_RV670:
2012 chip_name = "RV670";
2013 rlc_chip_name = "R600";
2014 break;
3ce0a23d 2015 case CHIP_RS780:
d8f60cfc
AD		 2016 case CHIP_RS880:
2017 chip_name = "RS780";
2018 rlc_chip_name = "R600";
2019 break;
2020 case CHIP_RV770:
2021 chip_name = "RV770";
2022 rlc_chip_name = "R700";
2023 break;
3ce0a23d 2024 case CHIP_RV730:
d8f60cfc
AD		 2025 case CHIP_RV740:
2026 chip_name = "RV730";
2027 rlc_chip_name = "R700";
2028 break;
2029 case CHIP_RV710:
2030 chip_name = "RV710";
2031 rlc_chip_name = "R700";
2032 break;
fe251e2f
AD		 2033 case CHIP_CEDAR:
2034 chip_name = "CEDAR";
45f9a39b 2035 rlc_chip_name = "CEDAR";
fe251e2f
AD		 2036 break;
2037 case CHIP_REDWOOD:
2038 chip_name = "REDWOOD";
45f9a39b 2039 rlc_chip_name = "REDWOOD";
fe251e2f
AD		 2040 break;
2041 case CHIP_JUNIPER:
2042 chip_name = "JUNIPER";
45f9a39b 2043 rlc_chip_name = "JUNIPER";
fe251e2f
AD		 2044 break;
2045 case CHIP_CYPRESS:
2046 case CHIP_HEMLOCK:
2047 chip_name = "CYPRESS";
45f9a39b 2048 rlc_chip_name = "CYPRESS";
fe251e2f 2049 break;
439bd6cd
AD		 2050 case CHIP_PALM:
2051 chip_name = "PALM";
2052 rlc_chip_name = "SUMO";
2053 break;
d5c5a72f
AD		 2054 case CHIP_SUMO:
2055 chip_name = "SUMO";
2056 rlc_chip_name = "SUMO";
2057 break;
2058 case CHIP_SUMO2:
2059 chip_name = "SUMO2";
2060 rlc_chip_name = "SUMO";
2061 break;
3ce0a23d
JG		 2062 default: BUG();
2063 }
2064
fe251e2f
AD		 2065 if (rdev->family >= CHIP_CEDAR) {
2066 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
2067 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
45f9a39b 2068 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
fe251e2f 2069 } else if (rdev->family >= CHIP_RV770) {
3ce0a23d
JG		 2070 pfp_req_size = R700_PFP_UCODE_SIZE * 4;
2071 me_req_size = R700_PM4_UCODE_SIZE * 4;
d8f60cfc 2072 rlc_req_size = R700_RLC_UCODE_SIZE * 4;
3ce0a23d
JG		 2073 } else {
2074 pfp_req_size = PFP_UCODE_SIZE * 4;
2075 me_req_size = PM4_UCODE_SIZE * 12;
d8f60cfc 2076 rlc_req_size = RLC_UCODE_SIZE * 4;
3ce0a23d
JG		 2077 }
2078
d8f60cfc 2079 DRM_INFO("Loading %s Microcode\n", chip_name);
3ce0a23d
JG		 2080
2081 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
2082 err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
2083 if (err)
2084 goto out;
2085 if (rdev->pfp_fw->size != pfp_req_size) {
2086 printk(KERN_ERR
2087 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
2088 rdev->pfp_fw->size, fw_name);
2089 err = -EINVAL;
2090 goto out;
2091 }
2092
2093 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
2094 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
2095 if (err)
2096 goto out;
2097 if (rdev->me_fw->size != me_req_size) {
2098 printk(KERN_ERR
2099 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
2100 rdev->me_fw->size, fw_name);
2101 err = -EINVAL;
2102 }
d8f60cfc
AD		 2103
2104 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
2105 err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev);
2106 if (err)
2107 goto out;
2108 if (rdev->rlc_fw->size != rlc_req_size) {
2109 printk(KERN_ERR
2110 "r600_rlc: Bogus length %zu in firmware \"%s\"\n",
2111 rdev->rlc_fw->size, fw_name);
2112 err = -EINVAL;
2113 }
2114
3ce0a23d
JG		 2115out:
2116 platform_device_unregister(pdev);
2117
2118 if (err) {
2119 if (err != -EINVAL)
2120 printk(KERN_ERR
2121 "r600_cp: Failed to load firmware \"%s\"\n",
2122 fw_name);
2123 release_firmware(rdev->pfp_fw);
2124 rdev->pfp_fw = NULL;
2125 release_firmware(rdev->me_fw);
2126 rdev->me_fw = NULL;
d8f60cfc
AD		 2127 release_firmware(rdev->rlc_fw);
2128 rdev->rlc_fw = NULL;
3ce0a23d
JG		 2129 }
2130 return err;
2131}
2132
2133static int r600_cp_load_microcode(struct radeon_device *rdev)
2134{
2135 const __be32 *fw_data;
2136 int i;
2137
2138 if (!rdev->me_fw || !rdev->pfp_fw)
2139 return -EINVAL;
2140
2141 r600_cp_stop(rdev);
2142
4eace7fd
CC		 2143 WREG32(CP_RB_CNTL,
2144#ifdef __BIG_ENDIAN
2145 BUF_SWAP_32BIT |
2146#endif
2147 RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
3ce0a23d
JG		 2148
2149 /* Reset cp */
2150 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2151 RREG32(GRBM_SOFT_RESET);
2152 mdelay(15);
2153 WREG32(GRBM_SOFT_RESET, 0);
2154
2155 WREG32(CP_ME_RAM_WADDR, 0);
2156
2157 fw_data = (const __be32 *)rdev->me_fw->data;
2158 WREG32(CP_ME_RAM_WADDR, 0);
2159 for (i = 0; i < PM4_UCODE_SIZE * 3; i++)
2160 WREG32(CP_ME_RAM_DATA,
2161 be32_to_cpup(fw_data++));
2162
2163 fw_data = (const __be32 *)rdev->pfp_fw->data;
2164 WREG32(CP_PFP_UCODE_ADDR, 0);
2165 for (i = 0; i < PFP_UCODE_SIZE; i++)
2166 WREG32(CP_PFP_UCODE_DATA,
2167 be32_to_cpup(fw_data++));
2168
2169 WREG32(CP_PFP_UCODE_ADDR, 0);
2170 WREG32(CP_ME_RAM_WADDR, 0);
2171 WREG32(CP_ME_RAM_RADDR, 0);
2172 return 0;
2173}
2174
2175int r600_cp_start(struct radeon_device *rdev)
2176{
e32eb50d 2177 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3ce0a23d
JG		 2178 int r;
2179 uint32_t cp_me;
2180
e32eb50d 2181 r = radeon_ring_lock(rdev, ring, 7);
3ce0a23d
JG		 2182 if (r) {
2183 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
2184 return r;
2185 }
e32eb50d
CK		 2186 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
2187 radeon_ring_write(ring, 0x1);
7e7b41d2 2188 if (rdev->family >= CHIP_RV770) {
e32eb50d
CK		 2189 radeon_ring_write(ring, 0x0);
2190 radeon_ring_write(ring, rdev->config.rv770.max_hw_contexts - 1);
fe251e2f 2191 } else {
e32eb50d
CK		 2192 radeon_ring_write(ring, 0x3);
2193 radeon_ring_write(ring, rdev->config.r600.max_hw_contexts - 1);
3ce0a23d 2194 }
e32eb50d
CK		 2195 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
2196 radeon_ring_write(ring, 0);
2197 radeon_ring_write(ring, 0);
2198 radeon_ring_unlock_commit(rdev, ring);
3ce0a23d
JG		 2199
2200 cp_me = 0xff;
2201 WREG32(R_0086D8_CP_ME_CNTL, cp_me);
2202 return 0;
2203}
2204
2205int r600_cp_resume(struct radeon_device *rdev)
2206{
e32eb50d 2207 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3ce0a23d
JG		 2208 u32 tmp;
2209 u32 rb_bufsz;
2210 int r;
2211
2212 /* Reset cp */
2213 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2214 RREG32(GRBM_SOFT_RESET);
2215 mdelay(15);
2216 WREG32(GRBM_SOFT_RESET, 0);
2217
2218 /* Set ring buffer size */
e32eb50d 2219 rb_bufsz = drm_order(ring->ring_size / 8);
724c80e1 2220 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
3ce0a23d 2221#ifdef __BIG_ENDIAN
d6f28938 2222 tmp |= BUF_SWAP_32BIT;
3ce0a23d 2223#endif
d6f28938 2224 WREG32(CP_RB_CNTL, tmp);
15d3332f 2225 WREG32(CP_SEM_WAIT_TIMER, 0x0);
3ce0a23d
JG		 2226
2227 /* Set the write pointer delay */
2228 WREG32(CP_RB_WPTR_DELAY, 0);
2229
2230 /* Initialize the ring buffer's read and write pointers */
3ce0a23d
JG		 2231 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
2232 WREG32(CP_RB_RPTR_WR, 0);
e32eb50d
CK		 2233 ring->wptr = 0;
2234 WREG32(CP_RB_WPTR, ring->wptr);
724c80e1
AD		 2235
2236 /* set the wb address whether it's enabled or not */
4eace7fd 2237 WREG32(CP_RB_RPTR_ADDR,
4eace7fd 2238 ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC));
724c80e1
AD		 2239 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
2240 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
2241
2242 if (rdev->wb.enabled)
2243 WREG32(SCRATCH_UMSK, 0xff);
2244 else {
2245 tmp |= RB_NO_UPDATE;
2246 WREG32(SCRATCH_UMSK, 0);
2247 }
2248
3ce0a23d
JG		 2249 mdelay(1);
2250 WREG32(CP_RB_CNTL, tmp);
2251
e32eb50d 2252 WREG32(CP_RB_BASE, ring->gpu_addr >> 8);
3ce0a23d
JG		 2253 WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
2254
e32eb50d 2255 ring->rptr = RREG32(CP_RB_RPTR);
3ce0a23d
JG		 2256
2257 r600_cp_start(rdev);
e32eb50d 2258 ring->ready = true;
f712812e 2259 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
3ce0a23d 2260 if (r) {
e32eb50d 2261 ring->ready = false;
3ce0a23d
JG		 2262 return r;
2263 }
2264 return 0;
2265}
2266
e32eb50d 2267void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size)
3ce0a23d
JG		 2268{
2269 u32 rb_bufsz;
45df6803 2270 int r;
3ce0a23d
JG		 2271
2272 /* Align ring size */
2273 rb_bufsz = drm_order(ring_size / 8);
2274 ring_size = (1 << (rb_bufsz + 1)) * 4;
e32eb50d
CK		 2275 ring->ring_size = ring_size;
2276 ring->align_mask = 16 - 1;
45df6803 2277
89d35807
AD		 2278 if (radeon_ring_supports_scratch_reg(rdev, ring)) {
2279 r = radeon_scratch_get(rdev, &ring->rptr_save_reg);
2280 if (r) {
2281 DRM_ERROR("failed to get scratch reg for rptr save (%d).\n", r);
2282 ring->rptr_save_reg = 0;
2283 }
45df6803 2284 }
3ce0a23d
JG		 2285}
2286
655efd3d
JG		 2287void r600_cp_fini(struct radeon_device *rdev)
2288{
45df6803 2289 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
655efd3d 2290 r600_cp_stop(rdev);
45df6803
CK		 2291 radeon_ring_fini(rdev, ring);
2292 radeon_scratch_free(rdev, ring->rptr_save_reg);
655efd3d
JG		 2293}
2294
4d75658b
AD		 2295/*
2296 * DMA
2297 * Starting with R600, the GPU has an asynchronous
2298 * DMA engine. The programming model is very similar
2299 * to the 3D engine (ring buffer, IBs, etc.), but the
2300 * DMA controller has it's own packet format that is
2301 * different form the PM4 format used by the 3D engine.
2302 * It supports copying data, writing embedded data,
2303 * solid fills, and a number of other things. It also
2304 * has support for tiling/detiling of buffers.
2305 */
2306/**
2307 * r600_dma_stop - stop the async dma engine
2308 *
2309 * @rdev: radeon_device pointer
2310 *
2311 * Stop the async dma engine (r6xx-evergreen).
2312 */
2313void r600_dma_stop(struct radeon_device *rdev)
2314{
2315 u32 rb_cntl = RREG32(DMA_RB_CNTL);
2316
2317 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
2318
2319 rb_cntl &= ~DMA_RB_ENABLE;
2320 WREG32(DMA_RB_CNTL, rb_cntl);
2321
2322 rdev->ring[R600_RING_TYPE_DMA_INDEX].ready = false;
2323}
2324
2325/**
2326 * r600_dma_resume - setup and start the async dma engine
2327 *
2328 * @rdev: radeon_device pointer
2329 *
2330 * Set up the DMA ring buffer and enable it. (r6xx-evergreen).
2331 * Returns 0 for success, error for failure.
2332 */
2333int r600_dma_resume(struct radeon_device *rdev)
2334{
2335 struct radeon_ring *ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
b3dfcb20 2336 u32 rb_cntl, dma_cntl, ib_cntl;
4d75658b
AD		 2337 u32 rb_bufsz;
2338 int r;
2339
2340 /* Reset dma */
2341 if (rdev->family >= CHIP_RV770)
2342 WREG32(SRBM_SOFT_RESET, RV770_SOFT_RESET_DMA);
2343 else
2344 WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA);
2345 RREG32(SRBM_SOFT_RESET);
2346 udelay(50);
2347 WREG32(SRBM_SOFT_RESET, 0);
2348
2349 WREG32(DMA_SEM_INCOMPLETE_TIMER_CNTL, 0);
2350 WREG32(DMA_SEM_WAIT_FAIL_TIMER_CNTL, 0);
2351
2352 /* Set ring buffer size in dwords */
2353 rb_bufsz = drm_order(ring->ring_size / 4);
2354 rb_cntl = rb_bufsz << 1;
2355#ifdef __BIG_ENDIAN
2356 rb_cntl |= DMA_RB_SWAP_ENABLE | DMA_RPTR_WRITEBACK_SWAP_ENABLE;
2357#endif
2358 WREG32(DMA_RB_CNTL, rb_cntl);
2359
2360 /* Initialize the ring buffer's read and write pointers */
2361 WREG32(DMA_RB_RPTR, 0);
2362 WREG32(DMA_RB_WPTR, 0);
2363
2364 /* set the wb address whether it's enabled or not */
2365 WREG32(DMA_RB_RPTR_ADDR_HI,
2366 upper_32_bits(rdev->wb.gpu_addr + R600_WB_DMA_RPTR_OFFSET) & 0xFF);
2367 WREG32(DMA_RB_RPTR_ADDR_LO,
2368 ((rdev->wb.gpu_addr + R600_WB_DMA_RPTR_OFFSET) & 0xFFFFFFFC));
2369
2370 if (rdev->wb.enabled)
2371 rb_cntl |= DMA_RPTR_WRITEBACK_ENABLE;
2372
2373 WREG32(DMA_RB_BASE, ring->gpu_addr >> 8);
2374
2375 /* enable DMA IBs */
b3dfcb20
MD		 2376 ib_cntl = DMA_IB_ENABLE;
2377#ifdef __BIG_ENDIAN
2378 ib_cntl |= DMA_IB_SWAP_ENABLE;
2379#endif
2380 WREG32(DMA_IB_CNTL, ib_cntl);
4d75658b
AD		 2381
2382 dma_cntl = RREG32(DMA_CNTL);
2383 dma_cntl &= ~CTXEMPTY_INT_ENABLE;
2384 WREG32(DMA_CNTL, dma_cntl);
2385
2386 if (rdev->family >= CHIP_RV770)
2387 WREG32(DMA_MODE, 1);
2388
2389 ring->wptr = 0;
2390 WREG32(DMA_RB_WPTR, ring->wptr << 2);
2391
2392 ring->rptr = RREG32(DMA_RB_RPTR) >> 2;
2393
2394 WREG32(DMA_RB_CNTL, rb_cntl | DMA_RB_ENABLE);
2395
2396 ring->ready = true;
2397
2398 r = radeon_ring_test(rdev, R600_RING_TYPE_DMA_INDEX, ring);
2399 if (r) {
2400 ring->ready = false;
2401 return r;
2402 }
2403
2404 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
2405
2406 return 0;
2407}
2408
2409/**
2410 * r600_dma_fini - tear down the async dma engine
2411 *
2412 * @rdev: radeon_device pointer
2413 *
2414 * Stop the async dma engine and free the ring (r6xx-evergreen).
2415 */
2416void r600_dma_fini(struct radeon_device *rdev)
2417{
2418 r600_dma_stop(rdev);
2419 radeon_ring_fini(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX]);
2420}
3ce0a23d
JG		 2421
2422/*
2423 * GPU scratch registers helpers function.
2424 */
2425void r600_scratch_init(struct radeon_device *rdev)
2426{
2427 int i;
2428
2429 rdev->scratch.num_reg = 7;
724c80e1 2430 rdev->scratch.reg_base = SCRATCH_REG0;
3ce0a23d
JG		 2431 for (i = 0; i < rdev->scratch.num_reg; i++) {
2432 rdev->scratch.free[i] = true;
724c80e1 2433 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
3ce0a23d
JG		 2434 }
2435}
2436
e32eb50d 2437int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
3ce0a23d
JG		 2438{
2439 uint32_t scratch;
2440 uint32_t tmp = 0;
8b25ed34 2441 unsigned i;
3ce0a23d
JG		 2442 int r;
2443
2444 r = radeon_scratch_get(rdev, &scratch);
2445 if (r) {
2446 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
2447 return r;
2448 }
2449 WREG32(scratch, 0xCAFEDEAD);
e32eb50d 2450 r = radeon_ring_lock(rdev, ring, 3);
3ce0a23d 2451 if (r) {
8b25ed34 2452 DRM_ERROR("radeon: cp failed to lock ring %d (%d).\n", ring->idx, r);
3ce0a23d
JG		 2453 radeon_scratch_free(rdev, scratch);
2454 return r;
2455 }
e32eb50d
CK		 2456 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2457 radeon_ring_write(ring, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2458 radeon_ring_write(ring, 0xDEADBEEF);
2459 radeon_ring_unlock_commit(rdev, ring);
3ce0a23d
JG		 2460 for (i = 0; i < rdev->usec_timeout; i++) {
2461 tmp = RREG32(scratch);
2462 if (tmp == 0xDEADBEEF)
2463 break;
2464 DRM_UDELAY(1);
2465 }
2466 if (i < rdev->usec_timeout) {
8b25ed34 2467 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
3ce0a23d 2468 } else {
bf852799 2469 DRM_ERROR("radeon: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
8b25ed34 2470 ring->idx, scratch, tmp);
3ce0a23d
JG		 2471 r = -EINVAL;
2472 }
2473 radeon_scratch_free(rdev, scratch);
2474 return r;
2475}
2476
4d75658b
AD		 2477/**
2478 * r600_dma_ring_test - simple async dma engine test
2479 *
2480 * @rdev: radeon_device pointer
2481 * @ring: radeon_ring structure holding ring information
2482 *
2483 * Test the DMA engine by writing using it to write an
2484 * value to memory. (r6xx-SI).
2485 * Returns 0 for success, error for failure.
2486 */
2487int r600_dma_ring_test(struct radeon_device *rdev,
2488 struct radeon_ring *ring)
2489{
2490 unsigned i;
2491 int r;
2492 void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
2493 u32 tmp;
2494
2495 if (!ptr) {
2496 DRM_ERROR("invalid vram scratch pointer\n");
2497 return -EINVAL;
2498 }
2499
2500 tmp = 0xCAFEDEAD;
2501 writel(tmp, ptr);
2502
2503 r = radeon_ring_lock(rdev, ring, 4);
2504 if (r) {
2505 DRM_ERROR("radeon: dma failed to lock ring %d (%d).\n", ring->idx, r);
2506 return r;
2507 }
2508 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1));
2509 radeon_ring_write(ring, rdev->vram_scratch.gpu_addr & 0xfffffffc);
2510 radeon_ring_write(ring, upper_32_bits(rdev->vram_scratch.gpu_addr) & 0xff);
2511 radeon_ring_write(ring, 0xDEADBEEF);
2512 radeon_ring_unlock_commit(rdev, ring);
2513
2514 for (i = 0; i < rdev->usec_timeout; i++) {
2515 tmp = readl(ptr);
2516 if (tmp == 0xDEADBEEF)
2517 break;
2518 DRM_UDELAY(1);
2519 }
2520
2521 if (i < rdev->usec_timeout) {
2522 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
2523 } else {
2524 DRM_ERROR("radeon: ring %d test failed (0x%08X)\n",
2525 ring->idx, tmp);
2526 r = -EINVAL;
2527 }
2528 return r;
2529}
2530
2531/*
2532 * CP fences/semaphores
2533 */
2534
3ce0a23d
JG		 2535void r600_fence_ring_emit(struct radeon_device *rdev,
2536 struct radeon_fence *fence)
2537{
e32eb50d 2538 struct radeon_ring *ring = &rdev->ring[fence->ring];
7b1f2485 2539
d0f8a854 2540 if (rdev->wb.use_event) {
30eb77f4 2541 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
77b1bad4 2542 /* flush read cache over gart */
e32eb50d
CK		 2543 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
2544 radeon_ring_write(ring, PACKET3_TC_ACTION_ENA |
2545 PACKET3_VC_ACTION_ENA |
2546 PACKET3_SH_ACTION_ENA);
2547 radeon_ring_write(ring, 0xFFFFFFFF);
2548 radeon_ring_write(ring, 0);
2549 radeon_ring_write(ring, 10); /* poll interval */
d0f8a854 2550 /* EVENT_WRITE_EOP - flush caches, send int */
e32eb50d
CK		 2551 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
2552 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5));
2553 radeon_ring_write(ring, addr & 0xffffffff);
2554 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
2555 radeon_ring_write(ring, fence->seq);
2556 radeon_ring_write(ring, 0);
d0f8a854 2557 } else {
77b1bad4 2558 /* flush read cache over gart */
e32eb50d
CK		 2559 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
2560 radeon_ring_write(ring, PACKET3_TC_ACTION_ENA |
2561 PACKET3_VC_ACTION_ENA |
2562 PACKET3_SH_ACTION_ENA);
2563 radeon_ring_write(ring, 0xFFFFFFFF);
2564 radeon_ring_write(ring, 0);
2565 radeon_ring_write(ring, 10); /* poll interval */
2566 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
2567 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0));
d0f8a854 2568 /* wait for 3D idle clean */
e32eb50d
CK		 2569 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2570 radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2571 radeon_ring_write(ring, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit);
d0f8a854 2572 /* Emit fence sequence & fire IRQ */
e32eb50d
CK		 2573 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2574 radeon_ring_write(ring, ((rdev->fence_drv[fence->ring].scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2575 radeon_ring_write(ring, fence->seq);
d0f8a854 2576 /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */
e32eb50d
CK		 2577 radeon_ring_write(ring, PACKET0(CP_INT_STATUS, 0));
2578 radeon_ring_write(ring, RB_INT_STAT);
d0f8a854 2579 }
3ce0a23d
JG		 2580}
2581
15d3332f 2582void r600_semaphore_ring_emit(struct radeon_device *rdev,
e32eb50d 2583 struct radeon_ring *ring,
15d3332f 2584 struct radeon_semaphore *semaphore,
7b1f2485 2585 bool emit_wait)
15d3332f
CK		 2586{
2587 uint64_t addr = semaphore->gpu_addr;
2588 unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL;
2589
0be70439
CK		 2590 if (rdev->family < CHIP_CAYMAN)
2591 sel |= PACKET3_SEM_WAIT_ON_SIGNAL;
2592
e32eb50d
CK		 2593 radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1));
2594 radeon_ring_write(ring, addr & 0xffffffff);
2595 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | sel);
15d3332f
CK		 2596}
2597
4d75658b
AD		 2598/*
2599 * DMA fences/semaphores
2600 */
2601
2602/**
2603 * r600_dma_fence_ring_emit - emit a fence on the DMA ring
2604 *
2605 * @rdev: radeon_device pointer
2606 * @fence: radeon fence object
2607 *
2608 * Add a DMA fence packet to the ring to write
2609 * the fence seq number and DMA trap packet to generate
2610 * an interrupt if needed (r6xx-r7xx).
2611 */
2612void r600_dma_fence_ring_emit(struct radeon_device *rdev,
2613 struct radeon_fence *fence)
2614{
2615 struct radeon_ring *ring = &rdev->ring[fence->ring];
2616 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
86a1881d 2617
4d75658b
AD		 2618 /* write the fence */
2619 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_FENCE, 0, 0, 0));
2620 radeon_ring_write(ring, addr & 0xfffffffc);
2621 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff));
86a1881d 2622 radeon_ring_write(ring, lower_32_bits(fence->seq));
4d75658b
AD		 2623 /* generate an interrupt */
2624 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_TRAP, 0, 0, 0));
2625}
2626
2627/**
2628 * r600_dma_semaphore_ring_emit - emit a semaphore on the dma ring
2629 *
2630 * @rdev: radeon_device pointer
2631 * @ring: radeon_ring structure holding ring information
2632 * @semaphore: radeon semaphore object
2633 * @emit_wait: wait or signal semaphore
2634 *
2635 * Add a DMA semaphore packet to the ring wait on or signal
2636 * other rings (r6xx-SI).
2637 */
2638void r600_dma_semaphore_ring_emit(struct radeon_device *rdev,
2639 struct radeon_ring *ring,
2640 struct radeon_semaphore *semaphore,
2641 bool emit_wait)
2642{
2643 u64 addr = semaphore->gpu_addr;
2644 u32 s = emit_wait ? 0 : 1;
2645
2646 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SEMAPHORE, 0, s, 0));
2647 radeon_ring_write(ring, addr & 0xfffffffc);
2648 radeon_ring_write(ring, upper_32_bits(addr) & 0xff);
2649}
2650
3ce0a23d 2651int r600_copy_blit(struct radeon_device *rdev,
003cefe0
AD		 2652 uint64_t src_offset,
2653 uint64_t dst_offset,
2654 unsigned num_gpu_pages,
876dc9f3 2655 struct radeon_fence **fence)
3ce0a23d 2656{
220907d9 2657 struct radeon_semaphore *sem = NULL;
f237750f 2658 struct radeon_sa_bo *vb = NULL;
ff82f052
JG		 2659 int r;
2660
220907d9 2661 r = r600_blit_prepare_copy(rdev, num_gpu_pages, fence, &vb, &sem);
ff82f052 2662 if (r) {
ff82f052
JG		 2663 return r;
2664 }
f237750f 2665 r600_kms_blit_copy(rdev, src_offset, dst_offset, num_gpu_pages, vb);
220907d9 2666 r600_blit_done_copy(rdev, fence, vb, sem);
3ce0a23d
JG		 2667 return 0;
2668}
2669
4d75658b
AD		 2670/**
2671 * r600_copy_dma - copy pages using the DMA engine
2672 *
2673 * @rdev: radeon_device pointer
2674 * @src_offset: src GPU address
2675 * @dst_offset: dst GPU address
2676 * @num_gpu_pages: number of GPU pages to xfer
2677 * @fence: radeon fence object
2678 *
43fb7787 2679 * Copy GPU paging using the DMA engine (r6xx).
4d75658b
AD		 2680 * Used by the radeon ttm implementation to move pages if
2681 * registered as the asic copy callback.
2682 */
2683int r600_copy_dma(struct radeon_device *rdev,
2684 uint64_t src_offset, uint64_t dst_offset,
2685 unsigned num_gpu_pages,
2686 struct radeon_fence **fence)
2687{
2688 struct radeon_semaphore *sem = NULL;
2689 int ring_index = rdev->asic->copy.dma_ring_index;
2690 struct radeon_ring *ring = &rdev->ring[ring_index];
2691 u32 size_in_dw, cur_size_in_dw;
2692 int i, num_loops;
2693 int r = 0;
2694
2695 r = radeon_semaphore_create(rdev, &sem);
2696 if (r) {
2697 DRM_ERROR("radeon: moving bo (%d).\n", r);
2698 return r;
2699 }
2700
2701 size_in_dw = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT) / 4;
43fb7787
AD		 2702 num_loops = DIV_ROUND_UP(size_in_dw, 0xFFFE);
2703 r = radeon_ring_lock(rdev, ring, num_loops * 4 + 8);
4d75658b
AD		 2704 if (r) {
2705 DRM_ERROR("radeon: moving bo (%d).\n", r);
2706 radeon_semaphore_free(rdev, &sem, NULL);
2707 return r;
2708 }
2709
2710 if (radeon_fence_need_sync(*fence, ring->idx)) {
2711 radeon_semaphore_sync_rings(rdev, sem, (*fence)->ring,
2712 ring->idx);
2713 radeon_fence_note_sync(*fence, ring->idx);
2714 } else {
2715 radeon_semaphore_free(rdev, &sem, NULL);
2716 }
2717
2718 for (i = 0; i < num_loops; i++) {
2719 cur_size_in_dw = size_in_dw;
909d9eb6
AD		 2720 if (cur_size_in_dw > 0xFFFE)
2721 cur_size_in_dw = 0xFFFE;
4d75658b
AD		 2722 size_in_dw -= cur_size_in_dw;
2723 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 0, 0, cur_size_in_dw));
2724 radeon_ring_write(ring, dst_offset & 0xfffffffc);
2725 radeon_ring_write(ring, src_offset & 0xfffffffc);
43fb7787
AD		 2726 radeon_ring_write(ring, (((upper_32_bits(dst_offset) & 0xff) << 16) |
2727 (upper_32_bits(src_offset) & 0xff)));
4d75658b
AD		 2728 src_offset += cur_size_in_dw * 4;
2729 dst_offset += cur_size_in_dw * 4;
2730 }
2731
2732 r = radeon_fence_emit(rdev, fence, ring->idx);
2733 if (r) {
2734 radeon_ring_unlock_undo(rdev, ring);
2735 return r;
2736 }
2737
2738 radeon_ring_unlock_commit(rdev, ring);
2739 radeon_semaphore_free(rdev, &sem, *fence);
2740
2741 return r;
2742}
2743
3ce0a23d
JG		 2744int r600_set_surface_reg(struct radeon_device *rdev, int reg,
2745 uint32_t tiling_flags, uint32_t pitch,
2746 uint32_t offset, uint32_t obj_size)
2747{
2748 /* FIXME: implement */
2749 return 0;
2750}
2751
2752void r600_clear_surface_reg(struct radeon_device *rdev, int reg)
2753{
2754 /* FIXME: implement */
2755}
2756
1109ca09 2757static int r600_startup(struct radeon_device *rdev)
3ce0a23d 2758{
4d75658b 2759 struct radeon_ring *ring;
3ce0a23d
JG		 2760 int r;
2761
9e46a48d
AD		 2762 /* enable pcie gen2 link */
2763 r600_pcie_gen2_enable(rdev);
2764
779720a3
AD		 2765 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
2766 r = r600_init_microcode(rdev);
2767 if (r) {
2768 DRM_ERROR("Failed to load firmware!\n");
2769 return r;
2770 }
2771 }
2772
16cdf04d
AD		 2773 r = r600_vram_scratch_init(rdev);
2774 if (r)
2775 return r;
2776
a3c1945a 2777 r600_mc_program(rdev);
1a029b76
JG		 2778 if (rdev->flags & RADEON_IS_AGP) {
2779 r600_agp_enable(rdev);
2780 } else {
2781 r = r600_pcie_gart_enable(rdev);
2782 if (r)
2783 return r;
2784 }
3ce0a23d 2785 r600_gpu_init(rdev);
c38c7b64
JG		 2786 r = r600_blit_init(rdev);
2787 if (r) {
2788 r600_blit_fini(rdev);
27cd7769 2789 rdev->asic->copy.copy = NULL;
c38c7b64
JG		 2790 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
2791 }
b70d6bb3 2792
724c80e1
AD		 2793 /* allocate wb buffer */
2794 r = radeon_wb_init(rdev);
2795 if (r)
2796 return r;
2797
30eb77f4
JG		 2798 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
2799 if (r) {
2800 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
2801 return r;
2802 }
2803
4d75658b
AD		 2804 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX);
2805 if (r) {
2806 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
2807 return r;
2808 }
2809
d8f60cfc 2810 /* Enable IRQ */
d8f60cfc
AD		 2811 r = r600_irq_init(rdev);
2812 if (r) {
2813 DRM_ERROR("radeon: IH init failed (%d).\n", r);
2814 radeon_irq_kms_fini(rdev);
2815 return r;
2816 }
2817 r600_irq_set(rdev);
2818
4d75658b 2819 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
e32eb50d 2820 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
78c5560a
AD		 2821 R600_CP_RB_RPTR, R600_CP_RB_WPTR,
2822 0, 0xfffff, RADEON_CP_PACKET2);
4d75658b
AD		 2823 if (r)
2824 return r;
5596a9db 2825
4d75658b
AD		 2826 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
2827 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
2828 DMA_RB_RPTR, DMA_RB_WPTR,
2829 2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
3ce0a23d
JG		 2830 if (r)
2831 return r;
4d75658b 2832
3ce0a23d
JG		 2833 r = r600_cp_load_microcode(rdev);
2834 if (r)
2835 return r;
2836 r = r600_cp_resume(rdev);
2837 if (r)
2838 return r;
724c80e1 2839
4d75658b
AD		 2840 r = r600_dma_resume(rdev);
2841 if (r)
2842 return r;
2843
2898c348
CK		 2844 r = radeon_ib_pool_init(rdev);
2845 if (r) {
2846 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
b15ba512 2847 return r;
2898c348 2848 }
b15ba512 2849
d4e30ef0
AD		 2850 r = r600_audio_init(rdev);
2851 if (r) {
2852 DRM_ERROR("radeon: audio init failed\n");
2853 return r;
2854 }
2855
3ce0a23d
JG		 2856 return 0;
2857}
2858
28d52043
DA		 2859void r600_vga_set_state(struct radeon_device *rdev, bool state)
2860{
2861 uint32_t temp;
2862
2863 temp = RREG32(CONFIG_CNTL);
2864 if (state == false) {
2865 temp &= ~(1<<0);
2866 temp |= (1<<1);
2867 } else {
2868 temp &= ~(1<<1);
2869 }
2870 WREG32(CONFIG_CNTL, temp);
2871}
2872
fc30b8ef
DA		 2873int r600_resume(struct radeon_device *rdev)
2874{
2875 int r;
2876
1a029b76
JG		 2877 /* Do not reset GPU before posting, on r600 hw unlike on r500 hw,
2878 * posting will perform necessary task to bring back GPU into good
2879 * shape.
2880 */
fc30b8ef 2881 /* post card */
e7d40b9a 2882 atom_asic_init(rdev->mode_info.atom_context);
fc30b8ef 2883
b15ba512 2884 rdev->accel_working = true;
fc30b8ef
DA		 2885 r = r600_startup(rdev);
2886 if (r) {
2887 DRM_ERROR("r600 startup failed on resume\n");
6b7746e8 2888 rdev->accel_working = false;
fc30b8ef
DA		 2889 return r;
2890 }
2891
fc30b8ef
DA		 2892 return r;
2893}
2894
3ce0a23d
JG		 2895int r600_suspend(struct radeon_device *rdev)
2896{
38fd2c6f 2897 r600_audio_fini(rdev);
3ce0a23d 2898 r600_cp_stop(rdev);
4d75658b 2899 r600_dma_stop(rdev);
0c45249f 2900 r600_irq_suspend(rdev);
724c80e1 2901 radeon_wb_disable(rdev);
4aac0473 2902 r600_pcie_gart_disable(rdev);
6ddddfe7 2903
3ce0a23d
JG		 2904 return 0;
2905}
2906
2907/* Plan is to move initialization in that function and use
2908 * helper function so that radeon_device_init pretty much
2909 * do nothing more than calling asic specific function. This
2910 * should also allow to remove a bunch of callback function
2911 * like vram_info.
2912 */
2913int r600_init(struct radeon_device *rdev)
771fe6b9 2914{
3ce0a23d 2915 int r;
771fe6b9 2916
3ce0a23d
JG		 2917 if (r600_debugfs_mc_info_init(rdev)) {
2918 DRM_ERROR("Failed to register debugfs file for mc !\n");
2919 }
3ce0a23d
JG		 2920 /* Read BIOS */
2921 if (!radeon_get_bios(rdev)) {
2922 if (ASIC_IS_AVIVO(rdev))
2923 return -EINVAL;
2924 }
2925 /* Must be an ATOMBIOS */
e7d40b9a
JG		 2926 if (!rdev->is_atom_bios) {
2927 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
3ce0a23d 2928 return -EINVAL;
e7d40b9a 2929 }
3ce0a23d
JG		 2930 r = radeon_atombios_init(rdev);
2931 if (r)
2932 return r;
2933 /* Post card if necessary */
fd909c37 2934 if (!radeon_card_posted(rdev)) {
72542d77
DA		 2935 if (!rdev->bios) {
2936 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
2937 return -EINVAL;
2938 }
3ce0a23d
JG		 2939 DRM_INFO("GPU not posted. posting now...\n");
2940 atom_asic_init(rdev->mode_info.atom_context);
2941 }
2942 /* Initialize scratch registers */
2943 r600_scratch_init(rdev);
2944 /* Initialize surface registers */
2945 radeon_surface_init(rdev);
7433874e 2946 /* Initialize clocks */
5e6dde7e 2947 radeon_get_clock_info(rdev->ddev);
3ce0a23d 2948 /* Fence driver */
30eb77f4 2949 r = radeon_fence_driver_init(rdev);
3ce0a23d
JG		 2950 if (r)
2951 return r;
700a0cc0
JG		 2952 if (rdev->flags & RADEON_IS_AGP) {
2953 r = radeon_agp_init(rdev);
2954 if (r)
2955 radeon_agp_disable(rdev);
2956 }
3ce0a23d 2957 r = r600_mc_init(rdev);
b574f251 2958 if (r)
3ce0a23d 2959 return r;
3ce0a23d 2960 /* Memory manager */
4c788679 2961 r = radeon_bo_init(rdev);
3ce0a23d
JG		 2962 if (r)
2963 return r;
d8f60cfc
AD		 2964
2965 r = radeon_irq_kms_init(rdev);
2966 if (r)
2967 return r;
2968
e32eb50d
CK		 2969 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
2970 r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
3ce0a23d 2971
4d75658b
AD		 2972 rdev->ring[R600_RING_TYPE_DMA_INDEX].ring_obj = NULL;
2973 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX], 64 * 1024);
2974
d8f60cfc
AD		 2975 rdev->ih.ring_obj = NULL;
2976 r600_ih_ring_init(rdev, 64 * 1024);
3ce0a23d 2977
4aac0473
JG		 2978 r = r600_pcie_gart_init(rdev);
2979 if (r)
2980 return r;
2981
779720a3 2982 rdev->accel_working = true;
fc30b8ef 2983 r = r600_startup(rdev);
3ce0a23d 2984 if (r) {
655efd3d
JG		 2985 dev_err(rdev->dev, "disabling GPU acceleration\n");
2986 r600_cp_fini(rdev);
4d75658b 2987 r600_dma_fini(rdev);
655efd3d 2988 r600_irq_fini(rdev);
724c80e1 2989 radeon_wb_fini(rdev);
2898c348 2990 radeon_ib_pool_fini(rdev);
655efd3d 2991 radeon_irq_kms_fini(rdev);
75c81298 2992 r600_pcie_gart_fini(rdev);
733289c2 2993 rdev->accel_working = false;
3ce0a23d 2994 }
dafc3bd5 2995
3ce0a23d
JG		 2996 return 0;
2997}
2998
2999void r600_fini(struct radeon_device *rdev)
3000{
dafc3bd5 3001 r600_audio_fini(rdev);
3ce0a23d 3002 r600_blit_fini(rdev);
655efd3d 3003 r600_cp_fini(rdev);
4d75658b 3004 r600_dma_fini(rdev);
d8f60cfc 3005 r600_irq_fini(rdev);
724c80e1 3006 radeon_wb_fini(rdev);
2898c348 3007 radeon_ib_pool_fini(rdev);
d8f60cfc 3008 radeon_irq_kms_fini(rdev);
4aac0473 3009 r600_pcie_gart_fini(rdev);
16cdf04d 3010 r600_vram_scratch_fini(rdev);
655efd3d 3011 radeon_agp_fini(rdev);
3ce0a23d
JG		 3012 radeon_gem_fini(rdev);
3013 radeon_fence_driver_fini(rdev);
4c788679 3014 radeon_bo_fini(rdev);
e7d40b9a 3015 radeon_atombios_fini(rdev);
3ce0a23d
JG		 3016 kfree(rdev->bios);
3017 rdev->bios = NULL;
3ce0a23d
JG		 3018}
3019
3020
3021/*
3022 * CS stuff
3023 */
3024void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3025{
876dc9f3 3026 struct radeon_ring *ring = &rdev->ring[ib->ring];
89d35807 3027 u32 next_rptr;
7b1f2485 3028
45df6803 3029 if (ring->rptr_save_reg) {
89d35807 3030 next_rptr = ring->wptr + 3 + 4;
45df6803
CK		 3031 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
3032 radeon_ring_write(ring, ((ring->rptr_save_reg -
3033 PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
3034 radeon_ring_write(ring, next_rptr);
89d35807
AD		 3035 } else if (rdev->wb.enabled) {
3036 next_rptr = ring->wptr + 5 + 4;
3037 radeon_ring_write(ring, PACKET3(PACKET3_MEM_WRITE, 3));
3038 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
3039 radeon_ring_write(ring, (upper_32_bits(ring->next_rptr_gpu_addr) & 0xff) | (1 << 18));
3040 radeon_ring_write(ring, next_rptr);
3041 radeon_ring_write(ring, 0);
45df6803
CK		 3042 }
3043
e32eb50d
CK		 3044 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
3045 radeon_ring_write(ring,
4eace7fd
CC		 3046#ifdef __BIG_ENDIAN
3047 (2 << 0) |
3048#endif
3049 (ib->gpu_addr & 0xFFFFFFFC));
e32eb50d
CK		 3050 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF);
3051 radeon_ring_write(ring, ib->length_dw);
3ce0a23d
JG		 3052}
3053
f712812e 3054int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
3ce0a23d 3055{
f2e39221 3056 struct radeon_ib ib;
3ce0a23d
JG		 3057 uint32_t scratch;
3058 uint32_t tmp = 0;
3059 unsigned i;
3060 int r;
3061
3062 r = radeon_scratch_get(rdev, &scratch);
3063 if (r) {
3064 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3065 return r;
3066 }
3067 WREG32(scratch, 0xCAFEDEAD);
4bf3dd92 3068 r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256);
3ce0a23d
JG		 3069 if (r) {
3070 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
af026c5b 3071 goto free_scratch;
3ce0a23d 3072 }
f2e39221
JG		 3073 ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
3074 ib.ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
3075 ib.ptr[2] = 0xDEADBEEF;
3076 ib.length_dw = 3;
4ef72566 3077 r = radeon_ib_schedule(rdev, &ib, NULL);
3ce0a23d 3078 if (r) {
3ce0a23d 3079 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
af026c5b 3080 goto free_ib;
3ce0a23d 3081 }
f2e39221 3082 r = radeon_fence_wait(ib.fence, false);
3ce0a23d
JG		 3083 if (r) {
3084 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
af026c5b 3085 goto free_ib;
3ce0a23d
JG		 3086 }
3087 for (i = 0; i < rdev->usec_timeout; i++) {
3088 tmp = RREG32(scratch);
3089 if (tmp == 0xDEADBEEF)
3090 break;
3091 DRM_UDELAY(1);
3092 }
3093 if (i < rdev->usec_timeout) {
f2e39221 3094 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i);
3ce0a23d 3095 } else {
4417d7f6 3096 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
3ce0a23d
JG		 3097 scratch, tmp);
3098 r = -EINVAL;
3099 }
af026c5b 3100free_ib:
3ce0a23d 3101 radeon_ib_free(rdev, &ib);
af026c5b
MD		 3102free_scratch:
3103 radeon_scratch_free(rdev, scratch);
771fe6b9
JG		 3104 return r;
3105}
3106
4d75658b
AD		 3107/**
3108 * r600_dma_ib_test - test an IB on the DMA engine
3109 *
3110 * @rdev: radeon_device pointer
3111 * @ring: radeon_ring structure holding ring information
3112 *
3113 * Test a simple IB in the DMA ring (r6xx-SI).
3114 * Returns 0 on success, error on failure.
3115 */
3116int r600_dma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
3117{
3118 struct radeon_ib ib;
3119 unsigned i;
3120 int r;
3121 void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
3122 u32 tmp = 0;
3123
3124 if (!ptr) {
3125 DRM_ERROR("invalid vram scratch pointer\n");
3126 return -EINVAL;
3127 }
3128
3129 tmp = 0xCAFEDEAD;
3130 writel(tmp, ptr);
3131
3132 r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256);
3133 if (r) {
3134 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
3135 return r;
3136 }
3137
3138 ib.ptr[0] = DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1);
3139 ib.ptr[1] = rdev->vram_scratch.gpu_addr & 0xfffffffc;
3140 ib.ptr[2] = upper_32_bits(rdev->vram_scratch.gpu_addr) & 0xff;
3141 ib.ptr[3] = 0xDEADBEEF;
3142 ib.length_dw = 4;
3143
3144 r = radeon_ib_schedule(rdev, &ib, NULL);
3145 if (r) {
3146 radeon_ib_free(rdev, &ib);
3147 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
3148 return r;
3149 }
3150 r = radeon_fence_wait(ib.fence, false);
3151 if (r) {
3152 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
3153 return r;
3154 }
3155 for (i = 0; i < rdev->usec_timeout; i++) {
3156 tmp = readl(ptr);
3157 if (tmp == 0xDEADBEEF)
3158 break;
3159 DRM_UDELAY(1);
3160 }
3161 if (i < rdev->usec_timeout) {
3162 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i);
3163 } else {
3164 DRM_ERROR("radeon: ib test failed (0x%08X)\n", tmp);
3165 r = -EINVAL;
3166 }
3167 radeon_ib_free(rdev, &ib);
3168 return r;
3169}
3170
3171/**
3172 * r600_dma_ring_ib_execute - Schedule an IB on the DMA engine
3173 *
3174 * @rdev: radeon_device pointer
3175 * @ib: IB object to schedule
3176 *
3177 * Schedule an IB in the DMA ring (r6xx-r7xx).
3178 */
3179void r600_dma_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3180{
3181 struct radeon_ring *ring = &rdev->ring[ib->ring];
3182
3183 if (rdev->wb.enabled) {
3184 u32 next_rptr = ring->wptr + 4;
3185 while ((next_rptr & 7) != 5)
3186 next_rptr++;
3187 next_rptr += 3;
3188 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1));
3189 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
3190 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff);
3191 radeon_ring_write(ring, next_rptr);
3192 }
3193
3194 /* The indirect buffer packet must end on an 8 DW boundary in the DMA ring.
3195 * Pad as necessary with NOPs.
3196 */
3197 while ((ring->wptr & 7) != 5)
3198 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
3199 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_INDIRECT_BUFFER, 0, 0, 0));
3200 radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0));
3201 radeon_ring_write(ring, (ib->length_dw << 16) | (upper_32_bits(ib->gpu_addr) & 0xFF));
3202
3203}
3204
d8f60cfc
AD		 3205/*
3206 * Interrupts
3207 *
3208 * Interrupts use a ring buffer on r6xx/r7xx hardware. It works pretty
3209 * the same as the CP ring buffer, but in reverse. Rather than the CPU
3210 * writing to the ring and the GPU consuming, the GPU writes to the ring
3211 * and host consumes. As the host irq handler processes interrupts, it
3212 * increments the rptr. When the rptr catches up with the wptr, all the
3213 * current interrupts have been processed.
3214 */
3215
3216void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size)
3217{
3218 u32 rb_bufsz;
3219
3220 /* Align ring size */
3221 rb_bufsz = drm_order(ring_size / 4);
3222 ring_size = (1 << rb_bufsz) * 4;
3223 rdev->ih.ring_size = ring_size;
0c45249f
JG		 3224 rdev->ih.ptr_mask = rdev->ih.ring_size - 1;
3225 rdev->ih.rptr = 0;
d8f60cfc
AD		 3226}
3227
25a857fb 3228int r600_ih_ring_alloc(struct radeon_device *rdev)
d8f60cfc
AD		 3229{
3230 int r;
3231
d8f60cfc
AD		 3232 /* Allocate ring buffer */
3233 if (rdev->ih.ring_obj == NULL) {
441921d5 3234 r = radeon_bo_create(rdev, rdev->ih.ring_size,
268b2510 3235 PAGE_SIZE, true,
4c788679 3236 RADEON_GEM_DOMAIN_GTT,
40f5cf99 3237 NULL, &rdev->ih.ring_obj);
d8f60cfc
AD		 3238 if (r) {
3239 DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r);
3240 return r;
3241 }
4c788679
JG		 3242 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
3243 if (unlikely(r != 0))
3244 return r;
3245 r = radeon_bo_pin(rdev->ih.ring_obj,
3246 RADEON_GEM_DOMAIN_GTT,
3247 &rdev->ih.gpu_addr);
d8f60cfc 3248 if (r) {
4c788679 3249 radeon_bo_unreserve(rdev->ih.ring_obj);
d8f60cfc
AD		 3250 DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r);
3251 return r;
3252 }
4c788679
JG		 3253 r = radeon_bo_kmap(rdev->ih.ring_obj,
3254 (void **)&rdev->ih.ring);
3255 radeon_bo_unreserve(rdev->ih.ring_obj);
d8f60cfc
AD		 3256 if (r) {
3257 DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r);
3258 return r;
3259 }
3260 }
d8f60cfc
AD		 3261 return 0;
3262}
3263
25a857fb 3264void r600_ih_ring_fini(struct radeon_device *rdev)
d8f60cfc 3265{
4c788679 3266 int r;
d8f60cfc 3267 if (rdev->ih.ring_obj) {
4c788679
JG		 3268 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
3269 if (likely(r == 0)) {
3270 radeon_bo_kunmap(rdev->ih.ring_obj);
3271 radeon_bo_unpin(rdev->ih.ring_obj);
3272 radeon_bo_unreserve(rdev->ih.ring_obj);
3273 }
3274 radeon_bo_unref(&rdev->ih.ring_obj);
d8f60cfc
AD		 3275 rdev->ih.ring = NULL;
3276 rdev->ih.ring_obj = NULL;
3277 }
3278}
3279
45f9a39b 3280void r600_rlc_stop(struct radeon_device *rdev)
d8f60cfc
AD		 3281{
3282
45f9a39b
AD		 3283 if ((rdev->family >= CHIP_RV770) &&
3284 (rdev->family <= CHIP_RV740)) {
d8f60cfc
AD		 3285 /* r7xx asics need to soft reset RLC before halting */
3286 WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC);
3287 RREG32(SRBM_SOFT_RESET);
4de833c3 3288 mdelay(15);
d8f60cfc
AD		 3289 WREG32(SRBM_SOFT_RESET, 0);
3290 RREG32(SRBM_SOFT_RESET);
3291 }
3292
3293 WREG32(RLC_CNTL, 0);
3294}
3295
3296static void r600_rlc_start(struct radeon_device *rdev)
3297{
3298 WREG32(RLC_CNTL, RLC_ENABLE);
3299}
3300
3301static int r600_rlc_init(struct radeon_device *rdev)
3302{
3303 u32 i;
3304 const __be32 *fw_data;
3305
3306 if (!rdev->rlc_fw)
3307 return -EINVAL;
3308
3309 r600_rlc_stop(rdev);
3310
d8f60cfc 3311 WREG32(RLC_HB_CNTL, 0);
c420c745
AD		 3312
3313 if (rdev->family == CHIP_ARUBA) {
3314 WREG32(TN_RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8);
3315 WREG32(TN_RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8);
3316 }
3317 if (rdev->family <= CHIP_CAYMAN) {
3318 WREG32(RLC_HB_BASE, 0);
3319 WREG32(RLC_HB_RPTR, 0);
3320 WREG32(RLC_HB_WPTR, 0);
3321 }
12727809
AD		 3322 if (rdev->family <= CHIP_CAICOS) {
3323 WREG32(RLC_HB_WPTR_LSB_ADDR, 0);
3324 WREG32(RLC_HB_WPTR_MSB_ADDR, 0);
3325 }
d8f60cfc
AD		 3326 WREG32(RLC_MC_CNTL, 0);
3327 WREG32(RLC_UCODE_CNTL, 0);
3328
3329 fw_data = (const __be32 *)rdev->rlc_fw->data;
c420c745
AD		 3330 if (rdev->family >= CHIP_ARUBA) {
3331 for (i = 0; i < ARUBA_RLC_UCODE_SIZE; i++) {
3332 WREG32(RLC_UCODE_ADDR, i);
3333 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
3334 }
3335 } else if (rdev->family >= CHIP_CAYMAN) {
12727809
AD		 3336 for (i = 0; i < CAYMAN_RLC_UCODE_SIZE; i++) {
3337 WREG32(RLC_UCODE_ADDR, i);
3338 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
3339 }
3340 } else if (rdev->family >= CHIP_CEDAR) {
45f9a39b
AD		 3341 for (i = 0; i < EVERGREEN_RLC_UCODE_SIZE; i++) {
3342 WREG32(RLC_UCODE_ADDR, i);
3343 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
3344 }
3345 } else if (rdev->family >= CHIP_RV770) {
d8f60cfc
AD		 3346 for (i = 0; i < R700_RLC_UCODE_SIZE; i++) {
3347 WREG32(RLC_UCODE_ADDR, i);
3348 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
3349 }
3350 } else {
3351 for (i = 0; i < RLC_UCODE_SIZE; i++) {
3352 WREG32(RLC_UCODE_ADDR, i);
3353 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
3354 }
3355 }
3356 WREG32(RLC_UCODE_ADDR, 0);
3357
3358 r600_rlc_start(rdev);
3359
3360 return 0;
3361}
3362
3363static void r600_enable_interrupts(struct radeon_device *rdev)
3364{
3365 u32 ih_cntl = RREG32(IH_CNTL);
3366 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
3367
3368 ih_cntl |= ENABLE_INTR;
3369 ih_rb_cntl |= IH_RB_ENABLE;
3370 WREG32(IH_CNTL, ih_cntl);
3371 WREG32(IH_RB_CNTL, ih_rb_cntl);
3372 rdev->ih.enabled = true;
3373}
3374
45f9a39b 3375void r600_disable_interrupts(struct radeon_device *rdev)
d8f60cfc
AD		 3376{
3377 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
3378 u32 ih_cntl = RREG32(IH_CNTL);
3379
3380 ih_rb_cntl &= ~IH_RB_ENABLE;
3381 ih_cntl &= ~ENABLE_INTR;
3382 WREG32(IH_RB_CNTL, ih_rb_cntl);
3383 WREG32(IH_CNTL, ih_cntl);
3384 /* set rptr, wptr to 0 */
3385 WREG32(IH_RB_RPTR, 0);
3386 WREG32(IH_RB_WPTR, 0);
3387 rdev->ih.enabled = false;
d8f60cfc
AD		 3388 rdev->ih.rptr = 0;
3389}
3390
e0df1ac5
AD		 3391static void r600_disable_interrupt_state(struct radeon_device *rdev)
3392{
3393 u32 tmp;
3394
3555e53b 3395 WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
4d75658b
AD		 3396 tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE;
3397 WREG32(DMA_CNTL, tmp);
e0df1ac5
AD		 3398 WREG32(GRBM_INT_CNTL, 0);
3399 WREG32(DxMODE_INT_MASK, 0);
6f34be50
AD		 3400 WREG32(D1GRPH_INTERRUPT_CONTROL, 0);
3401 WREG32(D2GRPH_INTERRUPT_CONTROL, 0);
e0df1ac5
AD		 3402 if (ASIC_IS_DCE3(rdev)) {
3403 WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0);
3404 WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0);
3405 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3406 WREG32(DC_HPD1_INT_CONTROL, tmp);
3407 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3408 WREG32(DC_HPD2_INT_CONTROL, tmp);
3409 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3410 WREG32(DC_HPD3_INT_CONTROL, tmp);
3411 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3412 WREG32(DC_HPD4_INT_CONTROL, tmp);
3413 if (ASIC_IS_DCE32(rdev)) {
3414 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
5898b1f3 3415 WREG32(DC_HPD5_INT_CONTROL, tmp);
e0df1ac5 3416 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
5898b1f3 3417 WREG32(DC_HPD6_INT_CONTROL, tmp);
c6543a6e
RM		 3418 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3419 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp);
3420 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3421 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp);
f122c610
AD		 3422 } else {
3423 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3424 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);
3425 tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3426 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp);
e0df1ac5
AD		 3427 }
3428 } else {
3429 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
3430 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
3431 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
5898b1f3 3432 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
e0df1ac5 3433 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
5898b1f3 3434 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
e0df1ac5 3435 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
5898b1f3 3436 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
f122c610
AD		 3437 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3438 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);
3439 tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3440 WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp);
e0df1ac5
AD		 3441 }
3442}
3443
d8f60cfc
AD		 3444int r600_irq_init(struct radeon_device *rdev)
3445{
3446 int ret = 0;
3447 int rb_bufsz;
3448 u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
3449
3450 /* allocate ring */
0c45249f 3451 ret = r600_ih_ring_alloc(rdev);
d8f60cfc
AD		 3452 if (ret)
3453 return ret;
3454
3455 /* disable irqs */
3456 r600_disable_interrupts(rdev);
3457
3458 /* init rlc */
3459 ret = r600_rlc_init(rdev);
3460 if (ret) {
3461 r600_ih_ring_fini(rdev);
3462 return ret;
3463 }
3464
3465 /* setup interrupt control */
3466 /* set dummy read address to ring address */
3467 WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8);
3468 interrupt_cntl = RREG32(INTERRUPT_CNTL);
3469 /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
3470 * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
3471 */
3472 interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
3473 /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
3474 interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
3475 WREG32(INTERRUPT_CNTL, interrupt_cntl);
3476
3477 WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
3478 rb_bufsz = drm_order(rdev->ih.ring_size / 4);
3479
3480 ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
3481 IH_WPTR_OVERFLOW_CLEAR |
3482 (rb_bufsz << 1));
724c80e1
AD		 3483
3484 if (rdev->wb.enabled)
3485 ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;
3486
3487 /* set the writeback address whether it's enabled or not */
3488 WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC);
3489 WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF);
d8f60cfc
AD		 3490
3491 WREG32(IH_RB_CNTL, ih_rb_cntl);
3492
3493 /* set rptr, wptr to 0 */
3494 WREG32(IH_RB_RPTR, 0);
3495 WREG32(IH_RB_WPTR, 0);
3496
3497 /* Default settings for IH_CNTL (disabled at first) */
3498 ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10);
3499 /* RPTR_REARM only works if msi's are enabled */
3500 if (rdev->msi_enabled)
3501 ih_cntl |= RPTR_REARM;
d8f60cfc
AD		 3502 WREG32(IH_CNTL, ih_cntl);
3503
3504 /* force the active interrupt state to all disabled */
45f9a39b
AD		 3505 if (rdev->family >= CHIP_CEDAR)
3506 evergreen_disable_interrupt_state(rdev);
3507 else
3508 r600_disable_interrupt_state(rdev);
d8f60cfc 3509
2099810f
DA		 3510 /* at this point everything should be setup correctly to enable master */
3511 pci_set_master(rdev->pdev);
3512
d8f60cfc
AD		 3513 /* enable irqs */
3514 r600_enable_interrupts(rdev);
3515
3516 return ret;
3517}
3518
0c45249f 3519void r600_irq_suspend(struct radeon_device *rdev)
d8f60cfc 3520{
45f9a39b 3521 r600_irq_disable(rdev);
d8f60cfc 3522 r600_rlc_stop(rdev);
0c45249f
JG		 3523}
3524
3525void r600_irq_fini(struct radeon_device *rdev)
3526{
3527 r600_irq_suspend(rdev);
d8f60cfc
AD		 3528 r600_ih_ring_fini(rdev);
3529}
3530
3531int r600_irq_set(struct radeon_device *rdev)
3532{
e0df1ac5
AD		 3533 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
3534 u32 mode_int = 0;
3535 u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0;
2031f77c 3536 u32 grbm_int_cntl = 0;
f122c610 3537 u32 hdmi0, hdmi1;
6f34be50 3538 u32 d1grph = 0, d2grph = 0;
4d75658b 3539 u32 dma_cntl;
d8f60cfc 3540
003e69f9 3541 if (!rdev->irq.installed) {
fce7d61b 3542 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
003e69f9
JG		 3543 return -EINVAL;
3544 }
d8f60cfc 3545 /* don't enable anything if the ih is disabled */
79c2bbc5
JG		 3546 if (!rdev->ih.enabled) {
3547 r600_disable_interrupts(rdev);
3548 /* force the active interrupt state to all disabled */
3549 r600_disable_interrupt_state(rdev);
d8f60cfc 3550 return 0;
79c2bbc5 3551 }
d8f60cfc 3552
e0df1ac5
AD		 3553 if (ASIC_IS_DCE3(rdev)) {
3554 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3555 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3556 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3557 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
3558 if (ASIC_IS_DCE32(rdev)) {
3559 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
3560 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
c6543a6e
RM		 3561 hdmi0 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
3562 hdmi1 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
f122c610
AD		 3563 } else {
3564 hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3565 hdmi1 = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
e0df1ac5
AD		 3566 }
3567 } else {
3568 hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3569 hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3570 hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN;
f122c610
AD		 3571 hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3572 hdmi1 = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
e0df1ac5 3573 }
4d75658b 3574 dma_cntl = RREG32(DMA_CNTL) & ~TRAP_ENABLE;
e0df1ac5 3575
736fc37f 3576 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
d8f60cfc
AD		 3577 DRM_DEBUG("r600_irq_set: sw int\n");
3578 cp_int_cntl |= RB_INT_ENABLE;
d0f8a854 3579 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
d8f60cfc 3580 }
4d75658b
AD		 3581
3582 if (atomic_read(&rdev->irq.ring_int[R600_RING_TYPE_DMA_INDEX])) {
3583 DRM_DEBUG("r600_irq_set: sw int dma\n");
3584 dma_cntl |= TRAP_ENABLE;
3585 }
3586
6f34be50 3587 if (rdev->irq.crtc_vblank_int[0] ||
736fc37f 3588 atomic_read(&rdev->irq.pflip[0])) {
d8f60cfc
AD		 3589 DRM_DEBUG("r600_irq_set: vblank 0\n");
3590 mode_int |= D1MODE_VBLANK_INT_MASK;
3591 }
6f34be50 3592 if (rdev->irq.crtc_vblank_int[1] ||
736fc37f 3593 atomic_read(&rdev->irq.pflip[1])) {
d8f60cfc
AD		 3594 DRM_DEBUG("r600_irq_set: vblank 1\n");
3595 mode_int |= D2MODE_VBLANK_INT_MASK;
3596 }
e0df1ac5
AD		 3597 if (rdev->irq.hpd[0]) {
3598 DRM_DEBUG("r600_irq_set: hpd 1\n");
3599 hpd1 |= DC_HPDx_INT_EN;
3600 }
3601 if (rdev->irq.hpd[1]) {
3602 DRM_DEBUG("r600_irq_set: hpd 2\n");
3603 hpd2 |= DC_HPDx_INT_EN;
3604 }
3605 if (rdev->irq.hpd[2]) {
3606 DRM_DEBUG("r600_irq_set: hpd 3\n");
3607 hpd3 |= DC_HPDx_INT_EN;
3608 }
3609 if (rdev->irq.hpd[3]) {
3610 DRM_DEBUG("r600_irq_set: hpd 4\n");
3611 hpd4 |= DC_HPDx_INT_EN;
3612 }
3613 if (rdev->irq.hpd[4]) {
3614 DRM_DEBUG("r600_irq_set: hpd 5\n");
3615 hpd5 |= DC_HPDx_INT_EN;
3616 }
3617 if (rdev->irq.hpd[5]) {
3618 DRM_DEBUG("r600_irq_set: hpd 6\n");
3619 hpd6 |= DC_HPDx_INT_EN;
3620 }
f122c610
AD		 3621 if (rdev->irq.afmt[0]) {
3622 DRM_DEBUG("r600_irq_set: hdmi 0\n");
3623 hdmi0 |= HDMI0_AZ_FORMAT_WTRIG_MASK;
f2594933 3624 }
f122c610
AD		 3625 if (rdev->irq.afmt[1]) {
3626 DRM_DEBUG("r600_irq_set: hdmi 0\n");
3627 hdmi1 |= HDMI0_AZ_FORMAT_WTRIG_MASK;
f2594933 3628 }
d8f60cfc
AD		 3629
3630 WREG32(CP_INT_CNTL, cp_int_cntl);
4d75658b 3631 WREG32(DMA_CNTL, dma_cntl);
d8f60cfc 3632 WREG32(DxMODE_INT_MASK, mode_int);
6f34be50
AD		 3633 WREG32(D1GRPH_INTERRUPT_CONTROL, d1grph);
3634 WREG32(D2GRPH_INTERRUPT_CONTROL, d2grph);
2031f77c 3635 WREG32(GRBM_INT_CNTL, grbm_int_cntl);
e0df1ac5
AD		 3636 if (ASIC_IS_DCE3(rdev)) {
3637 WREG32(DC_HPD1_INT_CONTROL, hpd1);
3638 WREG32(DC_HPD2_INT_CONTROL, hpd2);
3639 WREG32(DC_HPD3_INT_CONTROL, hpd3);
3640 WREG32(DC_HPD4_INT_CONTROL, hpd4);
3641 if (ASIC_IS_DCE32(rdev)) {
3642 WREG32(DC_HPD5_INT_CONTROL, hpd5);
3643 WREG32(DC_HPD6_INT_CONTROL, hpd6);
c6543a6e
RM		 3644 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, hdmi0);
3645 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, hdmi1);
f122c610
AD		 3646 } else {
3647 WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
3648 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, hdmi1);
e0df1ac5
AD		 3649 }
3650 } else {
3651 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
3652 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
3653 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3);
f122c610
AD		 3654 WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
3655 WREG32(HDMI1_AUDIO_PACKET_CONTROL, hdmi1);
e0df1ac5 3656 }
d8f60cfc
AD		 3657
3658 return 0;
3659}
3660
ce580fab 3661static void r600_irq_ack(struct radeon_device *rdev)
d8f60cfc 3662{
e0df1ac5
AD		 3663 u32 tmp;
3664
3665 if (ASIC_IS_DCE3(rdev)) {
6f34be50
AD		 3666 rdev->irq.stat_regs.r600.disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS);
3667 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE);
3668 rdev->irq.stat_regs.r600.disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2);
f122c610 3669 if (ASIC_IS_DCE32(rdev)) {
c6543a6e
RM		 3670 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET0);
3671 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET1);
f122c610
AD		 3672 } else {
3673 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS);
3674 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(DCE3_HDMI1_STATUS);
3675 }
e0df1ac5 3676 } else {
6f34be50
AD		 3677 rdev->irq.stat_regs.r600.disp_int = RREG32(DISP_INTERRUPT_STATUS);
3678 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
3679 rdev->irq.stat_regs.r600.disp_int_cont2 = 0;
f122c610
AD		 3680 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS);
3681 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(HDMI1_STATUS);
6f34be50
AD		 3682 }
3683 rdev->irq.stat_regs.r600.d1grph_int = RREG32(D1GRPH_INTERRUPT_STATUS);
3684 rdev->irq.stat_regs.r600.d2grph_int = RREG32(D2GRPH_INTERRUPT_STATUS);
3685
3686 if (rdev->irq.stat_regs.r600.d1grph_int & DxGRPH_PFLIP_INT_OCCURRED)
3687 WREG32(D1GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR);
3688 if (rdev->irq.stat_regs.r600.d2grph_int & DxGRPH_PFLIP_INT_OCCURRED)
3689 WREG32(D2GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR);
3690 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT)
d8f60cfc 3691 WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
6f34be50 3692 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT)
d8f60cfc 3693 WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
6f34be50 3694 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT)
d8f60cfc 3695 WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
6f34be50 3696 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT)
d8f60cfc 3697 WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
6f34be50 3698 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) {
e0df1ac5
AD		 3699 if (ASIC_IS_DCE3(rdev)) {
3700 tmp = RREG32(DC_HPD1_INT_CONTROL);
3701 tmp |= DC_HPDx_INT_ACK;
3702 WREG32(DC_HPD1_INT_CONTROL, tmp);
3703 } else {
3704 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
3705 tmp |= DC_HPDx_INT_ACK;
3706 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
3707 }
3708 }
6f34be50 3709 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) {
e0df1ac5
AD		 3710 if (ASIC_IS_DCE3(rdev)) {
3711 tmp = RREG32(DC_HPD2_INT_CONTROL);
3712 tmp |= DC_HPDx_INT_ACK;
3713 WREG32(DC_HPD2_INT_CONTROL, tmp);
3714 } else {
3715 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
3716 tmp |= DC_HPDx_INT_ACK;
3717 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
3718 }
3719 }
6f34be50 3720 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) {
e0df1ac5
AD		 3721 if (ASIC_IS_DCE3(rdev)) {
3722 tmp = RREG32(DC_HPD3_INT_CONTROL);
3723 tmp |= DC_HPDx_INT_ACK;
3724 WREG32(DC_HPD3_INT_CONTROL, tmp);
3725 } else {
3726 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
3727 tmp |= DC_HPDx_INT_ACK;
3728 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
3729 }
3730 }
6f34be50 3731 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) {
e0df1ac5
AD		 3732 tmp = RREG32(DC_HPD4_INT_CONTROL);
3733 tmp |= DC_HPDx_INT_ACK;
3734 WREG32(DC_HPD4_INT_CONTROL, tmp);
3735 }
3736 if (ASIC_IS_DCE32(rdev)) {
6f34be50 3737 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) {
e0df1ac5
AD		 3738 tmp = RREG32(DC_HPD5_INT_CONTROL);
3739 tmp |= DC_HPDx_INT_ACK;
3740 WREG32(DC_HPD5_INT_CONTROL, tmp);
3741 }
6f34be50 3742 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) {
e0df1ac5
AD		 3743 tmp = RREG32(DC_HPD5_INT_CONTROL);
3744 tmp |= DC_HPDx_INT_ACK;
3745 WREG32(DC_HPD6_INT_CONTROL, tmp);
3746 }
f122c610 3747 if (rdev->irq.stat_regs.r600.hdmi0_status & AFMT_AZ_FORMAT_WTRIG) {
c6543a6e 3748 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0);
f122c610 3749 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
c6543a6e 3750 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp);
f122c610
AD		 3751 }
3752 if (rdev->irq.stat_regs.r600.hdmi1_status & AFMT_AZ_FORMAT_WTRIG) {
c6543a6e 3753 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1);
f122c610 3754 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
c6543a6e 3755 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp);
f2594933
CK		 3756 }
3757 } else {
f122c610
AD		 3758 if (rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG) {
3759 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL);
3760 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK;
3761 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);
3762 }
3763 if (rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG) {
3764 if (ASIC_IS_DCE3(rdev)) {
3765 tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL);
3766 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK;
3767 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp);
3768 } else {
3769 tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL);
3770 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK;
3771 WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp);
3772 }
f2594933
CK		 3773 }
3774 }
d8f60cfc
AD		 3775}
3776
3777void r600_irq_disable(struct radeon_device *rdev)
3778{
d8f60cfc
AD		 3779 r600_disable_interrupts(rdev);
3780 /* Wait and acknowledge irq */
3781 mdelay(1);
6f34be50 3782 r600_irq_ack(rdev);
e0df1ac5 3783 r600_disable_interrupt_state(rdev);
d8f60cfc
AD		 3784}
3785
ce580fab 3786static u32 r600_get_ih_wptr(struct radeon_device *rdev)
d8f60cfc
AD		 3787{
3788 u32 wptr, tmp;
3ce0a23d 3789
724c80e1 3790 if (rdev->wb.enabled)
204ae24d 3791 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
724c80e1
AD		 3792 else
3793 wptr = RREG32(IH_RB_WPTR);
3ce0a23d 3794
d8f60cfc 3795 if (wptr & RB_OVERFLOW) {
7924e5eb
JG		 3796 /* When a ring buffer overflow happen start parsing interrupt
3797 * from the last not overwritten vector (wptr + 16). Hopefully
3798 * this should allow us to catchup.
3799 */
3800 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
3801 wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
3802 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
d8f60cfc
AD		 3803 tmp = RREG32(IH_RB_CNTL);
3804 tmp |= IH_WPTR_OVERFLOW_CLEAR;
3805 WREG32(IH_RB_CNTL, tmp);
3806 }
0c45249f 3807 return (wptr & rdev->ih.ptr_mask);
d8f60cfc 3808}
3ce0a23d 3809
d8f60cfc
AD		 3810/* r600 IV Ring
3811 * Each IV ring entry is 128 bits:
3812 * [7:0] - interrupt source id
3813 * [31:8] - reserved
3814 * [59:32] - interrupt source data
3815 * [127:60] - reserved
3816 *
3817 * The basic interrupt vector entries
3818 * are decoded as follows:
3819 * src_id src_data description
3820 * 1 0 D1 Vblank
3821 * 1 1 D1 Vline
3822 * 5 0 D2 Vblank
3823 * 5 1 D2 Vline
3824 * 19 0 FP Hot plug detection A
3825 * 19 1 FP Hot plug detection B
3826 * 19 2 DAC A auto-detection
3827 * 19 3 DAC B auto-detection
f2594933
CK		 3828 * 21 4 HDMI block A
3829 * 21 5 HDMI block B
d8f60cfc
AD		 3830 * 176 - CP_INT RB
3831 * 177 - CP_INT IB1
3832 * 178 - CP_INT IB2
3833 * 181 - EOP Interrupt
3834 * 233 - GUI Idle
3835 *
3836 * Note, these are based on r600 and may need to be
3837 * adjusted or added to on newer asics
3838 */
3839
3840int r600_irq_process(struct radeon_device *rdev)
3841{
682f1a54
DA		 3842 u32 wptr;
3843 u32 rptr;
d8f60cfc 3844 u32 src_id, src_data;
6f34be50 3845 u32 ring_index;
d4877cf2 3846 bool queue_hotplug = false;
f122c610 3847 bool queue_hdmi = false;
d8f60cfc 3848
682f1a54 3849 if (!rdev->ih.enabled || rdev->shutdown)
79c2bbc5 3850 return IRQ_NONE;
d8f60cfc 3851
f6a56939
BH		 3852 /* No MSIs, need a dummy read to flush PCI DMAs */
3853 if (!rdev->msi_enabled)
3854 RREG32(IH_RB_WPTR);
3855
682f1a54 3856 wptr = r600_get_ih_wptr(rdev);
d8f60cfc 3857
c20dc369
CK		 3858restart_ih:
3859 /* is somebody else already processing irqs? */
3860 if (atomic_xchg(&rdev->ih.lock, 1))
d8f60cfc 3861 return IRQ_NONE;
d8f60cfc 3862
c20dc369
CK		 3863 rptr = rdev->ih.rptr;
3864 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
3865
964f6645
BH		 3866 /* Order reading of wptr vs. reading of IH ring data */
3867 rmb();
3868
d8f60cfc 3869 /* display interrupts */
6f34be50 3870 r600_irq_ack(rdev);
d8f60cfc 3871
d8f60cfc
AD		 3872 while (rptr != wptr) {
3873 /* wptr/rptr are in bytes! */
3874 ring_index = rptr / 4;
4eace7fd
CC		 3875 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
3876 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
d8f60cfc
AD		 3877
3878 switch (src_id) {
3879 case 1: /* D1 vblank/vline */
3880 switch (src_data) {
3881 case 0: /* D1 vblank */
6f34be50 3882 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT) {
6f34be50
AD		 3883 if (rdev->irq.crtc_vblank_int[0]) {
3884 drm_handle_vblank(rdev->ddev, 0);
3885 rdev->pm.vblank_sync = true;
3886 wake_up(&rdev->irq.vblank_queue);
3887 }
736fc37f 3888 if (atomic_read(&rdev->irq.pflip[0]))
3e4ea742 3889 radeon_crtc_handle_flip(rdev, 0);
6f34be50 3890 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
d8f60cfc
AD		 3891 DRM_DEBUG("IH: D1 vblank\n");
3892 }
3893 break;
3894 case 1: /* D1 vline */
6f34be50
AD		 3895 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT) {
3896 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VLINE_INTERRUPT;
d8f60cfc
AD		 3897 DRM_DEBUG("IH: D1 vline\n");
3898 }
3899 break;
3900 default:
b042589c 3901 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
d8f60cfc
AD		 3902 break;
3903 }
3904 break;
3905 case 5: /* D2 vblank/vline */
3906 switch (src_data) {
3907 case 0: /* D2 vblank */
6f34be50 3908 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT) {
6f34be50
AD		 3909 if (rdev->irq.crtc_vblank_int[1]) {
3910 drm_handle_vblank(rdev->ddev, 1);
3911 rdev->pm.vblank_sync = true;
3912 wake_up(&rdev->irq.vblank_queue);
3913 }
736fc37f 3914 if (atomic_read(&rdev->irq.pflip[1]))
3e4ea742 3915 radeon_crtc_handle_flip(rdev, 1);
6f34be50 3916 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VBLANK_INTERRUPT;
d8f60cfc
AD		 3917 DRM_DEBUG("IH: D2 vblank\n");
3918 }
3919 break;
3920 case 1: /* D1 vline */
6f34be50
AD		 3921 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT) {
3922 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VLINE_INTERRUPT;
d8f60cfc
AD		 3923 DRM_DEBUG("IH: D2 vline\n");
3924 }
3925 break;
3926 default:
b042589c 3927 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
d8f60cfc
AD		 3928 break;
3929 }
3930 break;
e0df1ac5
AD		 3931 case 19: /* HPD/DAC hotplug */
3932 switch (src_data) {
3933 case 0:
6f34be50
AD		 3934 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) {
3935 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD1_INTERRUPT;
d4877cf2
AD		 3936 queue_hotplug = true;
3937 DRM_DEBUG("IH: HPD1\n");
e0df1ac5
AD		 3938 }
3939 break;
3940 case 1:
6f34be50
AD		 3941 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) {
3942 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD2_INTERRUPT;
d4877cf2
AD		 3943 queue_hotplug = true;
3944 DRM_DEBUG("IH: HPD2\n");
e0df1ac5
AD		 3945 }
3946 break;
3947 case 4:
6f34be50
AD		 3948 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) {
3949 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD3_INTERRUPT;
d4877cf2
AD		 3950 queue_hotplug = true;
3951 DRM_DEBUG("IH: HPD3\n");
e0df1ac5
AD		 3952 }
3953 break;
3954 case 5:
6f34be50
AD		 3955 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) {
3956 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD4_INTERRUPT;
d4877cf2
AD		 3957 queue_hotplug = true;
3958 DRM_DEBUG("IH: HPD4\n");
e0df1ac5
AD		 3959 }
3960 break;
3961 case 10:
6f34be50
AD		 3962 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) {
3963 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD5_INTERRUPT;
d4877cf2
AD		 3964 queue_hotplug = true;
3965 DRM_DEBUG("IH: HPD5\n");
e0df1ac5
AD		 3966 }
3967 break;
3968 case 12:
6f34be50
AD		 3969 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) {
3970 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD6_INTERRUPT;
d4877cf2
AD		 3971 queue_hotplug = true;
3972 DRM_DEBUG("IH: HPD6\n");
e0df1ac5
AD		 3973 }
3974 break;
3975 default:
b042589c 3976 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
e0df1ac5
AD		 3977 break;
3978 }
3979 break;
f122c610
AD		 3980 case 21: /* hdmi */
3981 switch (src_data) {
3982 case 4:
3983 if (rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG) {
3984 rdev->irq.stat_regs.r600.hdmi0_status &= ~HDMI0_AZ_FORMAT_WTRIG;
3985 queue_hdmi = true;
3986 DRM_DEBUG("IH: HDMI0\n");
3987 }
3988 break;
3989 case 5:
3990 if (rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG) {
3991 rdev->irq.stat_regs.r600.hdmi1_status &= ~HDMI0_AZ_FORMAT_WTRIG;
3992 queue_hdmi = true;
3993 DRM_DEBUG("IH: HDMI1\n");
3994 }
3995 break;
3996 default:
3997 DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data);
3998 break;
3999 }
f2594933 4000 break;
d8f60cfc
AD		 4001 case 176: /* CP_INT in ring buffer */
4002 case 177: /* CP_INT in IB1 */
4003 case 178: /* CP_INT in IB2 */
4004 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
7465280c 4005 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
d8f60cfc
AD		 4006 break;
4007 case 181: /* CP EOP event */
4008 DRM_DEBUG("IH: CP EOP\n");
7465280c 4009 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
d8f60cfc 4010 break;
4d75658b
AD		 4011 case 224: /* DMA trap event */
4012 DRM_DEBUG("IH: DMA trap\n");
4013 radeon_fence_process(rdev, R600_RING_TYPE_DMA_INDEX);
4014 break;
2031f77c 4015 case 233: /* GUI IDLE */
303c805c 4016 DRM_DEBUG("IH: GUI idle\n");
2031f77c 4017 break;
d8f60cfc 4018 default:
b042589c 4019 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
d8f60cfc
AD		 4020 break;
4021 }
4022
4023 /* wptr/rptr are in bytes! */
0c45249f
JG		 4024 rptr += 16;
4025 rptr &= rdev->ih.ptr_mask;
d8f60cfc 4026 }
d4877cf2 4027 if (queue_hotplug)
32c87fca 4028 schedule_work(&rdev->hotplug_work);
f122c610
AD		 4029 if (queue_hdmi)
4030 schedule_work(&rdev->audio_work);
d8f60cfc
AD		 4031 rdev->ih.rptr = rptr;
4032 WREG32(IH_RB_RPTR, rdev->ih.rptr);
c20dc369
CK		 4033 atomic_set(&rdev->ih.lock, 0);
4034
4035 /* make sure wptr hasn't changed while processing */
4036 wptr = r600_get_ih_wptr(rdev);
4037 if (wptr != rptr)
4038 goto restart_ih;
4039
d8f60cfc
AD		 4040 return IRQ_HANDLED;
4041}
3ce0a23d
JG		 4042
4043/*
4044 * Debugfs info
4045 */
4046#if defined(CONFIG_DEBUG_FS)
4047
3ce0a23d
JG		 4048static int r600_debugfs_mc_info(struct seq_file *m, void *data)
4049{
4050 struct drm_info_node *node = (struct drm_info_node *) m->private;
4051 struct drm_device *dev = node->minor->dev;
4052 struct radeon_device *rdev = dev->dev_private;
4053
4054 DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS);
4055 DREG32_SYS(m, rdev, VM_L2_STATUS);
4056 return 0;
4057}
4058
4059static struct drm_info_list r600_mc_info_list[] = {
4060 {"r600_mc_info", r600_debugfs_mc_info, 0, NULL},
3ce0a23d
JG		 4061};
4062#endif
4063
4064int r600_debugfs_mc_info_init(struct radeon_device *rdev)
4065{
4066#if defined(CONFIG_DEBUG_FS)
4067 return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list));
4068#else
4069 return 0;
4070#endif
771fe6b9 4071}
062b389c
JG		 4072
4073/**
4074 * r600_ioctl_wait_idle - flush host path cache on wait idle ioctl
4075 * rdev: radeon device structure
4076 * bo: buffer object struct which userspace is waiting for idle
4077 *
4078 * Some R6XX/R7XX doesn't seems to take into account HDP flush performed
4079 * through ring buffer, this leads to corruption in rendering, see
4080 * http://bugzilla.kernel.org/show_bug.cgi?id=15186 to avoid this we
4081 * directly perform HDP flush by writing register through MMIO.
4082 */
4083void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo)
4084{
812d0469 4085 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read
f3886f85
AD		 4086 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL.
4087 * This seems to cause problems on some AGP cards. Just use the old
4088 * method for them.
812d0469 4089 */
e488459a 4090 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
f3886f85 4091 rdev->vram_scratch.ptr && !(rdev->flags & RADEON_IS_AGP)) {
87cbf8f2 4092 void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
812d0469
AD		 4093 u32 tmp;
4094
4095 WREG32(HDP_DEBUG1, 0);
4096 tmp = readl((void __iomem *)ptr);
4097 } else
4098 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
062b389c 4099}
3313e3d4
AD		 4100
4101void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes)
4102{
4103 u32 link_width_cntl, mask, target_reg;
4104
4105 if (rdev->flags & RADEON_IS_IGP)
4106 return;
4107
4108 if (!(rdev->flags & RADEON_IS_PCIE))
4109 return;
4110
4111 /* x2 cards have a special sequence */
4112 if (ASIC_IS_X2(rdev))
4113 return;
4114
4115 /* FIXME wait for idle */
4116
4117 switch (lanes) {
4118 case 0:
4119 mask = RADEON_PCIE_LC_LINK_WIDTH_X0;
4120 break;
4121 case 1:
4122 mask = RADEON_PCIE_LC_LINK_WIDTH_X1;
4123 break;
4124 case 2:
4125 mask = RADEON_PCIE_LC_LINK_WIDTH_X2;
4126 break;
4127 case 4:
4128 mask = RADEON_PCIE_LC_LINK_WIDTH_X4;
4129 break;
4130 case 8:
4131 mask = RADEON_PCIE_LC_LINK_WIDTH_X8;
4132 break;
4133 case 12:
4134 mask = RADEON_PCIE_LC_LINK_WIDTH_X12;
4135 break;
4136 case 16:
4137 default:
4138 mask = RADEON_PCIE_LC_LINK_WIDTH_X16;
4139 break;
4140 }
4141
4142 link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
4143
4144 if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) ==
4145 (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT))
4146 return;
4147
4148 if (link_width_cntl & R600_PCIE_LC_UPCONFIGURE_DIS)
4149 return;
4150
4151 link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK |
4152 RADEON_PCIE_LC_RECONFIG_NOW |
4153 R600_PCIE_LC_RENEGOTIATE_EN |
4154 R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE);
4155 link_width_cntl |= mask;
4156
4157 WREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4158
4159 /* some northbridges can renegotiate the link rather than requiring
4160 * a complete re-config.
4161 * e.g., AMD 780/790 northbridges (pci ids: 0x5956, 0x5957, 0x5958, etc.)
4162 */
4163 if (link_width_cntl & R600_PCIE_LC_RENEGOTIATION_SUPPORT)
4164 link_width_cntl |= R600_PCIE_LC_RENEGOTIATE_EN | R600_PCIE_LC_UPCONFIGURE_SUPPORT;
4165 else
4166 link_width_cntl |= R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE;
4167
4168 WREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl |
4169 RADEON_PCIE_LC_RECONFIG_NOW));
4170
4171 if (rdev->family >= CHIP_RV770)
4172 target_reg = R700_TARGET_AND_CURRENT_PROFILE_INDEX;
4173 else
4174 target_reg = R600_TARGET_AND_CURRENT_PROFILE_INDEX;
4175
4176 /* wait for lane set to complete */
4177 link_width_cntl = RREG32(target_reg);
4178 while (link_width_cntl == 0xffffffff)
4179 link_width_cntl = RREG32(target_reg);
4180
4181}
4182
4183int r600_get_pcie_lanes(struct radeon_device *rdev)
4184{
4185 u32 link_width_cntl;
4186
4187 if (rdev->flags & RADEON_IS_IGP)
4188 return 0;
4189
4190 if (!(rdev->flags & RADEON_IS_PCIE))
4191 return 0;
4192
4193 /* x2 cards have a special sequence */
4194 if (ASIC_IS_X2(rdev))
4195 return 0;
4196
4197 /* FIXME wait for idle */
4198
4199 link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
4200
4201 switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) {
4202 case RADEON_PCIE_LC_LINK_WIDTH_X0:
4203 return 0;
4204 case RADEON_PCIE_LC_LINK_WIDTH_X1:
4205 return 1;
4206 case RADEON_PCIE_LC_LINK_WIDTH_X2:
4207 return 2;
4208 case RADEON_PCIE_LC_LINK_WIDTH_X4:
4209 return 4;
4210 case RADEON_PCIE_LC_LINK_WIDTH_X8:
4211 return 8;
4212 case RADEON_PCIE_LC_LINK_WIDTH_X16:
4213 default:
4214 return 16;
4215 }
4216}
4217
9e46a48d
AD		 4218static void r600_pcie_gen2_enable(struct radeon_device *rdev)
4219{
4220 u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp;
4221 u16 link_cntl2;
197bbb3d
DA		 4222 u32 mask;
4223 int ret;
9e46a48d 4224
d42dd579
AD		 4225 if (radeon_pcie_gen2 == 0)
4226 return;
4227
9e46a48d
AD		 4228 if (rdev->flags & RADEON_IS_IGP)
4229 return;
4230
4231 if (!(rdev->flags & RADEON_IS_PCIE))
4232 return;
4233
4234 /* x2 cards have a special sequence */
4235 if (ASIC_IS_X2(rdev))
4236 return;
4237
4238 /* only RV6xx+ chips are supported */
4239 if (rdev->family <= CHIP_R600)
4240 return;
4241
197bbb3d
DA		 4242 ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
4243 if (ret != 0)
4244 return;
4245
4246 if (!(mask & DRM_PCIE_SPEED_50))
4247 return;
4248
3691feea
AD		 4249 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
4250 if (speed_cntl & LC_CURRENT_DATA_RATE) {
4251 DRM_INFO("PCIE gen 2 link speeds already enabled\n");
4252 return;
4253 }
4254
197bbb3d
DA		 4255 DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");
4256
9e46a48d
AD		 4257 /* 55 nm r6xx asics */
4258 if ((rdev->family == CHIP_RV670) ||
4259 (rdev->family == CHIP_RV620) ||
4260 (rdev->family == CHIP_RV635)) {
4261 /* advertise upconfig capability */
4262 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
4263 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
4264 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4265 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
4266 if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) {
4267 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT;
4268 link_width_cntl &= ~(LC_LINK_WIDTH_MASK |
4269 LC_RECONFIG_ARC_MISSING_ESCAPE);
4270 link_width_cntl |= lanes | LC_RECONFIG_NOW | LC_RENEGOTIATE_EN;
4271 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4272 } else {
4273 link_width_cntl |= LC_UPCONFIGURE_DIS;
4274 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4275 }
4276 }
4277
4278 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
4279 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
4280 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
4281
4282 /* 55 nm r6xx asics */
4283 if ((rdev->family == CHIP_RV670) ||
4284 (rdev->family == CHIP_RV620) ||
4285 (rdev->family == CHIP_RV635)) {
4286 WREG32(MM_CFGREGS_CNTL, 0x8);
4287 link_cntl2 = RREG32(0x4088);
4288 WREG32(MM_CFGREGS_CNTL, 0);
4289 /* not supported yet */
4290 if (link_cntl2 & SELECTABLE_DEEMPHASIS)
4291 return;
4292 }
4293
4294 speed_cntl &= ~LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK;
4295 speed_cntl |= (0x3 << LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT);
4296 speed_cntl &= ~LC_VOLTAGE_TIMER_SEL_MASK;
4297 speed_cntl &= ~LC_FORCE_DIS_HW_SPEED_CHANGE;
4298 speed_cntl |= LC_FORCE_EN_HW_SPEED_CHANGE;
4299 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
4300
4301 tmp = RREG32(0x541c);
4302 WREG32(0x541c, tmp | 0x8);
4303 WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN);
4304 link_cntl2 = RREG16(0x4088);
4305 link_cntl2 &= ~TARGET_LINK_SPEED_MASK;
4306 link_cntl2 |= 0x2;
4307 WREG16(0x4088, link_cntl2);
4308 WREG32(MM_CFGREGS_CNTL, 0);
4309
4310 if ((rdev->family == CHIP_RV670) ||
4311 (rdev->family == CHIP_RV620) ||
4312 (rdev->family == CHIP_RV635)) {
4313 training_cntl = RREG32_PCIE_P(PCIE_LC_TRAINING_CNTL);
4314 training_cntl &= ~LC_POINT_7_PLUS_EN;
4315 WREG32_PCIE_P(PCIE_LC_TRAINING_CNTL, training_cntl);
4316 } else {
4317 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
4318 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
4319 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
4320 }
4321
4322 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
4323 speed_cntl |= LC_GEN2_EN_STRAP;
4324 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
4325
4326 } else {
4327 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
4328 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
4329 if (1)
4330 link_width_cntl |= LC_UPCONFIGURE_DIS;
4331 else
4332 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
4333 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4334 }
4335}
6759a0a7
MO		 4336
4337/**
4338 * r600_get_gpu_clock - return GPU clock counter snapshot
4339 *
4340 * @rdev: radeon_device pointer
4341 *
4342 * Fetches a GPU clock counter snapshot (R6xx-cayman).
4343 * Returns the 64 bit clock counter snapshot.
4344 */
4345uint64_t r600_get_gpu_clock(struct radeon_device *rdev)
4346{
4347 uint64_t clock;
4348
4349 mutex_lock(&rdev->gpu_clock_mutex);
4350 WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1);
4351 clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) |
4352 ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
4353 mutex_unlock(&rdev->gpu_clock_mutex);
4354 return clock;
4355}
Linux kernel - Deliverables
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