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drm/radeon/kms: disable VGA rendering engine before taking over VRAM
[deliverable/linux.git] / drivers / gpu / drm / radeon / r600.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
3ce0a23d
JG		 28#include <linux/seq_file.h>
29#include <linux/firmware.h>
30#include <linux/platform_device.h>
771fe6b9 31#include "drmP.h"
3ce0a23d 32#include "radeon_drm.h"
771fe6b9 33#include "radeon.h"
3ce0a23d 34#include "radeon_mode.h"
3ce0a23d
JG		 35#include "r600d.h"
36#include "avivod.h"
37#include "atom.h"
771fe6b9 38
3ce0a23d
JG		 39#define PFP_UCODE_SIZE 576
40#define PM4_UCODE_SIZE 1792
41#define R700_PFP_UCODE_SIZE 848
42#define R700_PM4_UCODE_SIZE 1360
43
44/* Firmware Names */
45MODULE_FIRMWARE("radeon/R600_pfp.bin");
46MODULE_FIRMWARE("radeon/R600_me.bin");
47MODULE_FIRMWARE("radeon/RV610_pfp.bin");
48MODULE_FIRMWARE("radeon/RV610_me.bin");
49MODULE_FIRMWARE("radeon/RV630_pfp.bin");
50MODULE_FIRMWARE("radeon/RV630_me.bin");
51MODULE_FIRMWARE("radeon/RV620_pfp.bin");
52MODULE_FIRMWARE("radeon/RV620_me.bin");
53MODULE_FIRMWARE("radeon/RV635_pfp.bin");
54MODULE_FIRMWARE("radeon/RV635_me.bin");
55MODULE_FIRMWARE("radeon/RV670_pfp.bin");
56MODULE_FIRMWARE("radeon/RV670_me.bin");
57MODULE_FIRMWARE("radeon/RS780_pfp.bin");
58MODULE_FIRMWARE("radeon/RS780_me.bin");
59MODULE_FIRMWARE("radeon/RV770_pfp.bin");
60MODULE_FIRMWARE("radeon/RV770_me.bin");
61MODULE_FIRMWARE("radeon/RV730_pfp.bin");
62MODULE_FIRMWARE("radeon/RV730_me.bin");
63MODULE_FIRMWARE("radeon/RV710_pfp.bin");
64MODULE_FIRMWARE("radeon/RV710_me.bin");
65
66int r600_debugfs_mc_info_init(struct radeon_device *rdev);
771fe6b9
JG		 67
68/* This files gather functions specifics to:
69 * r600,rv610,rv630,rv620,rv635,rv670
70 *
71 * Some of these functions might be used by newer ASICs.
72 */
73int r600_mc_wait_for_idle(struct radeon_device *rdev);
74void r600_gpu_init(struct radeon_device *rdev);
3ce0a23d 75void r600_fini(struct radeon_device *rdev);
771fe6b9
JG		 76
77
78/*
3ce0a23d 79 * R600 PCIE GART
771fe6b9 80 */
3ce0a23d 81int r600_gart_clear_page(struct radeon_device *rdev, int i)
771fe6b9 82{
3ce0a23d
JG		 83 void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
84 u64 pte;
771fe6b9 85
3ce0a23d
JG		 86 if (i < 0 || i > rdev->gart.num_gpu_pages)
87 return -EINVAL;
88 pte = 0;
89 writeq(pte, ((void __iomem *)ptr) + (i * 8));
90 return 0;
91}
771fe6b9 92
3ce0a23d
JG		 93void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
94{
95 unsigned i;
96 u32 tmp;
97
98 WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
99 WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
100 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
101 for (i = 0; i < rdev->usec_timeout; i++) {
102 /* read MC_STATUS */
103 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
104 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
105 if (tmp == 2) {
106 printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
107 return;
108 }
109 if (tmp) {
110 return;
111 }
112 udelay(1);
113 }
114}
115
4aac0473 116int r600_pcie_gart_init(struct radeon_device *rdev)
3ce0a23d 117{
4aac0473 118 int r;
3ce0a23d 119
4aac0473
JG		 120 if (rdev->gart.table.vram.robj) {
121 WARN(1, "R600 PCIE GART already initialized.\n");
122 return 0;
123 }
3ce0a23d
JG		 124 /* Initialize common gart structure */
125 r = radeon_gart_init(rdev);
4aac0473 126 if (r)
3ce0a23d 127 return r;
3ce0a23d 128 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
4aac0473
JG		 129 return radeon_gart_table_vram_alloc(rdev);
130}
131
132int r600_pcie_gart_enable(struct radeon_device *rdev)
133{
134 u32 tmp;
135 int r, i;
136
137 if (rdev->gart.table.vram.robj == NULL) {
138 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
139 return -EINVAL;
771fe6b9 140 }
4aac0473
JG		 141 r = radeon_gart_table_vram_pin(rdev);
142 if (r)
143 return r;
3ce0a23d
JG		 144 for (i = 0; i < rdev->gart.num_gpu_pages; i++)
145 r600_gart_clear_page(rdev, i);
146 /* Setup L2 cache */
147 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
148 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
149 EFFECTIVE_L2_QUEUE_SIZE(7));
150 WREG32(VM_L2_CNTL2, 0);
151 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
152 /* Setup TLB control */
153 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
154 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
155 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
156 ENABLE_WAIT_L2_QUERY;
157 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
158 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
159 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
160 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
161 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
162 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
163 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
164 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
165 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
166 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
167 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
168 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
169 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
170 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
171 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
172 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, (rdev->mc.gtt_end - 1) >> 12);
173 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
174 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
175 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
176 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
177 (u32)(rdev->dummy_page.addr >> 12));
178 for (i = 1; i < 7; i++)
179 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
771fe6b9 180
3ce0a23d
JG		 181 r600_pcie_gart_tlb_flush(rdev);
182 rdev->gart.ready = true;
771fe6b9
JG		 183 return 0;
184}
185
3ce0a23d 186void r600_pcie_gart_disable(struct radeon_device *rdev)
771fe6b9 187{
3ce0a23d
JG		 188 u32 tmp;
189 int i;
771fe6b9 190
3ce0a23d
JG		 191 /* Disable all tables */
192 for (i = 0; i < 7; i++)
193 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
771fe6b9 194
3ce0a23d
JG		 195 /* Disable L2 cache */
196 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
197 EFFECTIVE_L2_QUEUE_SIZE(7));
198 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
199 /* Setup L1 TLB control */
200 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
201 ENABLE_WAIT_L2_QUERY;
202 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
203 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
204 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
205 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
206 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
207 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
208 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
209 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
210 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp);
211 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp);
212 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
213 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
214 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
215 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
4aac0473
JG		 216 if (rdev->gart.table.vram.robj) {
217 radeon_object_kunmap(rdev->gart.table.vram.robj);
218 radeon_object_unpin(rdev->gart.table.vram.robj);
219 }
220}
221
222void r600_pcie_gart_fini(struct radeon_device *rdev)
223{
224 r600_pcie_gart_disable(rdev);
225 radeon_gart_table_vram_free(rdev);
226 radeon_gart_fini(rdev);
771fe6b9
JG		 227}
228
229int r600_mc_wait_for_idle(struct radeon_device *rdev)
230{
3ce0a23d
JG		 231 unsigned i;
232 u32 tmp;
233
234 for (i = 0; i < rdev->usec_timeout; i++) {
235 /* read MC_STATUS */
236 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00;
237 if (!tmp)
238 return 0;
239 udelay(1);
240 }
241 return -1;
771fe6b9
JG		 242}
243
3ce0a23d 244static void r600_mc_resume(struct radeon_device *rdev)
771fe6b9 245{
3ce0a23d
JG		 246 u32 d1vga_control, d2vga_control;
247 u32 vga_render_control, vga_hdp_control;
248 u32 d1crtc_control, d2crtc_control;
249 u32 new_d1grph_primary, new_d1grph_secondary;
250 u32 new_d2grph_primary, new_d2grph_secondary;
251 u64 old_vram_start;
252 u32 tmp;
253 int i, j;
771fe6b9 254
3ce0a23d
JG		 255 /* Initialize HDP */
256 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
257 WREG32((0x2c14 + j), 0x00000000);
258 WREG32((0x2c18 + j), 0x00000000);
259 WREG32((0x2c1c + j), 0x00000000);
260 WREG32((0x2c20 + j), 0x00000000);
261 WREG32((0x2c24 + j), 0x00000000);
262 }
263 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
771fe6b9 264
3ce0a23d
JG		 265 d1vga_control = RREG32(D1VGA_CONTROL);
266 d2vga_control = RREG32(D2VGA_CONTROL);
267 vga_render_control = RREG32(VGA_RENDER_CONTROL);
268 vga_hdp_control = RREG32(VGA_HDP_CONTROL);
269 d1crtc_control = RREG32(D1CRTC_CONTROL);
270 d2crtc_control = RREG32(D2CRTC_CONTROL);
271 old_vram_start = (u64)(RREG32(MC_VM_FB_LOCATION) & 0xFFFF) << 24;
272 new_d1grph_primary = RREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS);
273 new_d1grph_secondary = RREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS);
274 new_d1grph_primary += rdev->mc.vram_start - old_vram_start;
275 new_d1grph_secondary += rdev->mc.vram_start - old_vram_start;
276 new_d2grph_primary = RREG32(D2GRPH_PRIMARY_SURFACE_ADDRESS);
277 new_d2grph_secondary = RREG32(D2GRPH_SECONDARY_SURFACE_ADDRESS);
278 new_d2grph_primary += rdev->mc.vram_start - old_vram_start;
279 new_d2grph_secondary += rdev->mc.vram_start - old_vram_start;
280
281 /* Stop all video */
282 WREG32(D1VGA_CONTROL, 0);
283 WREG32(D2VGA_CONTROL, 0);
284 WREG32(VGA_RENDER_CONTROL, 0);
285 WREG32(D1CRTC_UPDATE_LOCK, 1);
286 WREG32(D2CRTC_UPDATE_LOCK, 1);
287 WREG32(D1CRTC_CONTROL, 0);
288 WREG32(D2CRTC_CONTROL, 0);
289 WREG32(D1CRTC_UPDATE_LOCK, 0);
290 WREG32(D2CRTC_UPDATE_LOCK, 0);
291
292 mdelay(1);
293 if (r600_mc_wait_for_idle(rdev)) {
294 printk(KERN_WARNING "[drm] MC not idle !\n");
295 }
296
297 /* Lockout access through VGA aperture*/
298 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
299
300 /* Update configuration */
301 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
302 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, (rdev->mc.vram_end - 1) >> 12);
303 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
304 tmp = (((rdev->mc.vram_end - 1) >> 24) & 0xFFFF) << 16;
305 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
306 WREG32(MC_VM_FB_LOCATION, tmp);
307 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
308 WREG32(HDP_NONSURFACE_INFO, (2 << 7));
309 WREG32(HDP_NONSURFACE_SIZE, (rdev->mc.mc_vram_size - 1) | 0x3FF);
310 if (rdev->flags & RADEON_IS_AGP) {
311 WREG32(MC_VM_AGP_TOP, (rdev->mc.gtt_end - 1) >> 16);
312 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
313 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
314 } else {
315 WREG32(MC_VM_AGP_BASE, 0);
316 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
317 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
318 }
319 WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS, new_d1grph_primary);
320 WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS, new_d1grph_secondary);
321 WREG32(D2GRPH_PRIMARY_SURFACE_ADDRESS, new_d2grph_primary);
322 WREG32(D2GRPH_SECONDARY_SURFACE_ADDRESS, new_d2grph_secondary);
323 WREG32(VGA_MEMORY_BASE_ADDRESS, rdev->mc.vram_start);
324
325 /* Unlock host access */
326 WREG32(VGA_HDP_CONTROL, vga_hdp_control);
327
328 mdelay(1);
329 if (r600_mc_wait_for_idle(rdev)) {
330 printk(KERN_WARNING "[drm] MC not idle !\n");
331 }
332
333 /* Restore video state */
334 WREG32(D1CRTC_UPDATE_LOCK, 1);
335 WREG32(D2CRTC_UPDATE_LOCK, 1);
336 WREG32(D1CRTC_CONTROL, d1crtc_control);
337 WREG32(D2CRTC_CONTROL, d2crtc_control);
338 WREG32(D1CRTC_UPDATE_LOCK, 0);
339 WREG32(D2CRTC_UPDATE_LOCK, 0);
340 WREG32(D1VGA_CONTROL, d1vga_control);
341 WREG32(D2VGA_CONTROL, d2vga_control);
342 WREG32(VGA_RENDER_CONTROL, vga_render_control);
698443d9
DA		 343
344 /* we need to own VRAM, so turn off the VGA renderer here
345 * to stop it overwriting our objects */
346 radeon_avivo_vga_render_disable(rdev);
3ce0a23d
JG		 347}
348
349int r600_mc_init(struct radeon_device *rdev)
771fe6b9 350{
3ce0a23d
JG		 351 fixed20_12 a;
352 u32 tmp;
771fe6b9 353 int chansize;
3ce0a23d 354 int r;
771fe6b9 355
3ce0a23d 356 /* Get VRAM informations */
771fe6b9
JG		 357 rdev->mc.vram_width = 128;
358 rdev->mc.vram_is_ddr = true;
3ce0a23d
JG		 359 tmp = RREG32(RAMCFG);
360 if (tmp & CHANSIZE_OVERRIDE) {
771fe6b9 361 chansize = 16;
3ce0a23d 362 } else if (tmp & CHANSIZE_MASK) {
771fe6b9
JG		 363 chansize = 64;
364 } else {
365 chansize = 32;
366 }
367 if (rdev->family == CHIP_R600) {
368 rdev->mc.vram_width = 8 * chansize;
369 } else if (rdev->family == CHIP_RV670) {
370 rdev->mc.vram_width = 4 * chansize;
371 } else if ((rdev->family == CHIP_RV610) ||
372 (rdev->family == CHIP_RV620)) {
373 rdev->mc.vram_width = chansize;
374 } else if ((rdev->family == CHIP_RV630) ||
375 (rdev->family == CHIP_RV635)) {
376 rdev->mc.vram_width = 2 * chansize;
377 }
3ce0a23d
JG		 378 /* Could aper size report 0 ? */
379 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
380 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
381 /* Setup GPU memory space */
382 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
383 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
384 if (rdev->flags & RADEON_IS_AGP) {
385 r = radeon_agp_init(rdev);
386 if (r)
387 return r;
388 /* gtt_size is setup by radeon_agp_init */
389 rdev->mc.gtt_location = rdev->mc.agp_base;
390 tmp = 0xFFFFFFFFUL - rdev->mc.agp_base - rdev->mc.gtt_size;
391 /* Try to put vram before or after AGP because we
392 * we want SYSTEM_APERTURE to cover both VRAM and
393 * AGP so that GPU can catch out of VRAM/AGP access
394 */
395 if (rdev->mc.gtt_location > rdev->mc.mc_vram_size) {
396 /* Enought place before */
397 rdev->mc.vram_location = rdev->mc.gtt_location -
398 rdev->mc.mc_vram_size;
399 } else if (tmp > rdev->mc.mc_vram_size) {
400 /* Enought place after */
401 rdev->mc.vram_location = rdev->mc.gtt_location +
402 rdev->mc.gtt_size;
403 } else {
404 /* Try to setup VRAM then AGP might not
405 * not work on some card
406 */
407 rdev->mc.vram_location = 0x00000000UL;
408 rdev->mc.gtt_location = rdev->mc.mc_vram_size;
409 }
410 } else {
411 if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) {
412 rdev->mc.vram_location = (RREG32(MC_VM_FB_LOCATION) &
413 0xFFFF) << 24;
414 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
415 tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size;
416 if ((0xFFFFFFFFUL - tmp) >= rdev->mc.gtt_size) {
417 /* Enough place after vram */
418 rdev->mc.gtt_location = tmp;
419 } else if (rdev->mc.vram_location >= rdev->mc.gtt_size) {
420 /* Enough place before vram */
421 rdev->mc.gtt_location = 0;
422 } else {
423 /* Not enough place after or before shrink
424 * gart size
425 */
426 if (rdev->mc.vram_location > (0xFFFFFFFFUL - tmp)) {
427 rdev->mc.gtt_location = 0;
428 rdev->mc.gtt_size = rdev->mc.vram_location;
429 } else {
430 rdev->mc.gtt_location = tmp;
431 rdev->mc.gtt_size = 0xFFFFFFFFUL - tmp;
432 }
433 }
434 rdev->mc.gtt_location = rdev->mc.mc_vram_size;
435 } else {
436 rdev->mc.vram_location = 0x00000000UL;
437 rdev->mc.gtt_location = rdev->mc.mc_vram_size;
438 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
439 }
440 }
441 rdev->mc.vram_start = rdev->mc.vram_location;
442 rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size;
443 rdev->mc.gtt_start = rdev->mc.gtt_location;
444 rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size;
445 /* FIXME: we should enforce default clock in case GPU is not in
446 * default setup
447 */
448 a.full = rfixed_const(100);
449 rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk);
450 rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
451 return 0;
771fe6b9
JG		 452}
453
3ce0a23d
JG		 454/* We doesn't check that the GPU really needs a reset we simply do the
455 * reset, it's up to the caller to determine if the GPU needs one. We
456 * might add an helper function to check that.
457 */
458int r600_gpu_soft_reset(struct radeon_device *rdev)
771fe6b9 459{
3ce0a23d
JG		 460 u32 grbm_busy_mask = S_008010_VC_BUSY(1) | S_008010_VGT_BUSY_NO_DMA(1) |
461 S_008010_VGT_BUSY(1) | S_008010_TA03_BUSY(1) |
462 S_008010_TC_BUSY(1) | S_008010_SX_BUSY(1) |
463 S_008010_SH_BUSY(1) | S_008010_SPI03_BUSY(1) |
464 S_008010_SMX_BUSY(1) | S_008010_SC_BUSY(1) |
465 S_008010_PA_BUSY(1) | S_008010_DB03_BUSY(1) |
466 S_008010_CR_BUSY(1) | S_008010_CB03_BUSY(1) |
467 S_008010_GUI_ACTIVE(1);
468 u32 grbm2_busy_mask = S_008014_SPI0_BUSY(1) | S_008014_SPI1_BUSY(1) |
469 S_008014_SPI2_BUSY(1) | S_008014_SPI3_BUSY(1) |
470 S_008014_TA0_BUSY(1) | S_008014_TA1_BUSY(1) |
471 S_008014_TA2_BUSY(1) | S_008014_TA3_BUSY(1) |
472 S_008014_DB0_BUSY(1) | S_008014_DB1_BUSY(1) |
473 S_008014_DB2_BUSY(1) | S_008014_DB3_BUSY(1) |
474 S_008014_CB0_BUSY(1) | S_008014_CB1_BUSY(1) |
475 S_008014_CB2_BUSY(1) | S_008014_CB3_BUSY(1);
476 u32 srbm_reset = 0;
771fe6b9 477
3ce0a23d
JG		 478 /* Disable CP parsing/prefetching */
479 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(0xff));
480 /* Check if any of the rendering block is busy and reset it */
481 if ((RREG32(R_008010_GRBM_STATUS) & grbm_busy_mask) ||
482 (RREG32(R_008014_GRBM_STATUS2) & grbm2_busy_mask)) {
483 WREG32(R_008020_GRBM_SOFT_RESET, S_008020_SOFT_RESET_CR(1) |
484 S_008020_SOFT_RESET_DB(1) |
485 S_008020_SOFT_RESET_CB(1) |
486 S_008020_SOFT_RESET_PA(1) |
487 S_008020_SOFT_RESET_SC(1) |
488 S_008020_SOFT_RESET_SMX(1) |
489 S_008020_SOFT_RESET_SPI(1) |
490 S_008020_SOFT_RESET_SX(1) |
491 S_008020_SOFT_RESET_SH(1) |
492 S_008020_SOFT_RESET_TC(1) |
493 S_008020_SOFT_RESET_TA(1) |
494 S_008020_SOFT_RESET_VC(1) |
495 S_008020_SOFT_RESET_VGT(1));
496 (void)RREG32(R_008020_GRBM_SOFT_RESET);
497 udelay(50);
498 WREG32(R_008020_GRBM_SOFT_RESET, 0);
499 (void)RREG32(R_008020_GRBM_SOFT_RESET);
500 }
501 /* Reset CP (we always reset CP) */
502 WREG32(R_008020_GRBM_SOFT_RESET, S_008020_SOFT_RESET_CP(1));
503 (void)RREG32(R_008020_GRBM_SOFT_RESET);
504 udelay(50);
505 WREG32(R_008020_GRBM_SOFT_RESET, 0);
506 (void)RREG32(R_008020_GRBM_SOFT_RESET);
507 /* Reset others GPU block if necessary */
508 if (G_000E50_RLC_BUSY(RREG32(R_000E50_SRBM_STATUS)))
509 srbm_reset |= S_000E60_SOFT_RESET_RLC(1);
510 if (G_000E50_GRBM_RQ_PENDING(RREG32(R_000E50_SRBM_STATUS)))
511 srbm_reset |= S_000E60_SOFT_RESET_GRBM(1);
512 if (G_000E50_HI_RQ_PENDING(RREG32(R_000E50_SRBM_STATUS)))
513 srbm_reset |= S_000E60_SOFT_RESET_IH(1);
514 if (G_000E50_VMC_BUSY(RREG32(R_000E50_SRBM_STATUS)))
515 srbm_reset |= S_000E60_SOFT_RESET_VMC(1);
516 if (G_000E50_MCB_BUSY(RREG32(R_000E50_SRBM_STATUS)))
517 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
518 if (G_000E50_MCDZ_BUSY(RREG32(R_000E50_SRBM_STATUS)))
519 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
520 if (G_000E50_MCDY_BUSY(RREG32(R_000E50_SRBM_STATUS)))
521 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
522 if (G_000E50_MCDX_BUSY(RREG32(R_000E50_SRBM_STATUS)))
523 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
524 if (G_000E50_MCDW_BUSY(RREG32(R_000E50_SRBM_STATUS)))
525 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
526 if (G_000E50_RLC_BUSY(RREG32(R_000E50_SRBM_STATUS)))
527 srbm_reset |= S_000E60_SOFT_RESET_RLC(1);
528 if (G_000E50_SEM_BUSY(RREG32(R_000E50_SRBM_STATUS)))
529 srbm_reset |= S_000E60_SOFT_RESET_SEM(1);
530 WREG32(R_000E60_SRBM_SOFT_RESET, srbm_reset);
531 (void)RREG32(R_000E60_SRBM_SOFT_RESET);
532 udelay(50);
533 WREG32(R_000E60_SRBM_SOFT_RESET, 0);
534 (void)RREG32(R_000E60_SRBM_SOFT_RESET);
535 /* Wait a little for things to settle down */
536 udelay(50);
537 return 0;
538}
539
540int r600_gpu_reset(struct radeon_device *rdev)
541{
542 return r600_gpu_soft_reset(rdev);
543}
544
545static u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
546 u32 num_backends,
547 u32 backend_disable_mask)
548{
549 u32 backend_map = 0;
550 u32 enabled_backends_mask;
551 u32 enabled_backends_count;
552 u32 cur_pipe;
553 u32 swizzle_pipe[R6XX_MAX_PIPES];
554 u32 cur_backend;
555 u32 i;
556
557 if (num_tile_pipes > R6XX_MAX_PIPES)
558 num_tile_pipes = R6XX_MAX_PIPES;
559 if (num_tile_pipes < 1)
560 num_tile_pipes = 1;
561 if (num_backends > R6XX_MAX_BACKENDS)
562 num_backends = R6XX_MAX_BACKENDS;
563 if (num_backends < 1)
564 num_backends = 1;
565
566 enabled_backends_mask = 0;
567 enabled_backends_count = 0;
568 for (i = 0; i < R6XX_MAX_BACKENDS; ++i) {
569 if (((backend_disable_mask >> i) & 1) == 0) {
570 enabled_backends_mask |= (1 << i);
571 ++enabled_backends_count;
572 }
573 if (enabled_backends_count == num_backends)
574 break;
575 }
576
577 if (enabled_backends_count == 0) {
578 enabled_backends_mask = 1;
579 enabled_backends_count = 1;
580 }
581
582 if (enabled_backends_count != num_backends)
583 num_backends = enabled_backends_count;
584
585 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES);
586 switch (num_tile_pipes) {
587 case 1:
588 swizzle_pipe[0] = 0;
589 break;
590 case 2:
591 swizzle_pipe[0] = 0;
592 swizzle_pipe[1] = 1;
593 break;
594 case 3:
595 swizzle_pipe[0] = 0;
596 swizzle_pipe[1] = 1;
597 swizzle_pipe[2] = 2;
598 break;
599 case 4:
600 swizzle_pipe[0] = 0;
601 swizzle_pipe[1] = 1;
602 swizzle_pipe[2] = 2;
603 swizzle_pipe[3] = 3;
604 break;
605 case 5:
606 swizzle_pipe[0] = 0;
607 swizzle_pipe[1] = 1;
608 swizzle_pipe[2] = 2;
609 swizzle_pipe[3] = 3;
610 swizzle_pipe[4] = 4;
611 break;
612 case 6:
613 swizzle_pipe[0] = 0;
614 swizzle_pipe[1] = 2;
615 swizzle_pipe[2] = 4;
616 swizzle_pipe[3] = 5;
617 swizzle_pipe[4] = 1;
618 swizzle_pipe[5] = 3;
619 break;
620 case 7:
621 swizzle_pipe[0] = 0;
622 swizzle_pipe[1] = 2;
623 swizzle_pipe[2] = 4;
624 swizzle_pipe[3] = 6;
625 swizzle_pipe[4] = 1;
626 swizzle_pipe[5] = 3;
627 swizzle_pipe[6] = 5;
628 break;
629 case 8:
630 swizzle_pipe[0] = 0;
631 swizzle_pipe[1] = 2;
632 swizzle_pipe[2] = 4;
633 swizzle_pipe[3] = 6;
634 swizzle_pipe[4] = 1;
635 swizzle_pipe[5] = 3;
636 swizzle_pipe[6] = 5;
637 swizzle_pipe[7] = 7;
638 break;
639 }
640
641 cur_backend = 0;
642 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
643 while (((1 << cur_backend) & enabled_backends_mask) == 0)
644 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
645
646 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
647
648 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
649 }
650
651 return backend_map;
652}
653
654int r600_count_pipe_bits(uint32_t val)
655{
656 int i, ret = 0;
657
658 for (i = 0; i < 32; i++) {
659 ret += val & 1;
660 val >>= 1;
661 }
662 return ret;
771fe6b9
JG		 663}
664
3ce0a23d
JG		 665void r600_gpu_init(struct radeon_device *rdev)
666{
667 u32 tiling_config;
668 u32 ramcfg;
669 u32 tmp;
670 int i, j;
671 u32 sq_config;
672 u32 sq_gpr_resource_mgmt_1 = 0;
673 u32 sq_gpr_resource_mgmt_2 = 0;
674 u32 sq_thread_resource_mgmt = 0;
675 u32 sq_stack_resource_mgmt_1 = 0;
676 u32 sq_stack_resource_mgmt_2 = 0;
677
678 /* FIXME: implement */
679 switch (rdev->family) {
680 case CHIP_R600:
681 rdev->config.r600.max_pipes = 4;
682 rdev->config.r600.max_tile_pipes = 8;
683 rdev->config.r600.max_simds = 4;
684 rdev->config.r600.max_backends = 4;
685 rdev->config.r600.max_gprs = 256;
686 rdev->config.r600.max_threads = 192;
687 rdev->config.r600.max_stack_entries = 256;
688 rdev->config.r600.max_hw_contexts = 8;
689 rdev->config.r600.max_gs_threads = 16;
690 rdev->config.r600.sx_max_export_size = 128;
691 rdev->config.r600.sx_max_export_pos_size = 16;
692 rdev->config.r600.sx_max_export_smx_size = 128;
693 rdev->config.r600.sq_num_cf_insts = 2;
694 break;
695 case CHIP_RV630:
696 case CHIP_RV635:
697 rdev->config.r600.max_pipes = 2;
698 rdev->config.r600.max_tile_pipes = 2;
699 rdev->config.r600.max_simds = 3;
700 rdev->config.r600.max_backends = 1;
701 rdev->config.r600.max_gprs = 128;
702 rdev->config.r600.max_threads = 192;
703 rdev->config.r600.max_stack_entries = 128;
704 rdev->config.r600.max_hw_contexts = 8;
705 rdev->config.r600.max_gs_threads = 4;
706 rdev->config.r600.sx_max_export_size = 128;
707 rdev->config.r600.sx_max_export_pos_size = 16;
708 rdev->config.r600.sx_max_export_smx_size = 128;
709 rdev->config.r600.sq_num_cf_insts = 2;
710 break;
711 case CHIP_RV610:
712 case CHIP_RV620:
713 case CHIP_RS780:
714 case CHIP_RS880:
715 rdev->config.r600.max_pipes = 1;
716 rdev->config.r600.max_tile_pipes = 1;
717 rdev->config.r600.max_simds = 2;
718 rdev->config.r600.max_backends = 1;
719 rdev->config.r600.max_gprs = 128;
720 rdev->config.r600.max_threads = 192;
721 rdev->config.r600.max_stack_entries = 128;
722 rdev->config.r600.max_hw_contexts = 4;
723 rdev->config.r600.max_gs_threads = 4;
724 rdev->config.r600.sx_max_export_size = 128;
725 rdev->config.r600.sx_max_export_pos_size = 16;
726 rdev->config.r600.sx_max_export_smx_size = 128;
727 rdev->config.r600.sq_num_cf_insts = 1;
728 break;
729 case CHIP_RV670:
730 rdev->config.r600.max_pipes = 4;
731 rdev->config.r600.max_tile_pipes = 4;
732 rdev->config.r600.max_simds = 4;
733 rdev->config.r600.max_backends = 4;
734 rdev->config.r600.max_gprs = 192;
735 rdev->config.r600.max_threads = 192;
736 rdev->config.r600.max_stack_entries = 256;
737 rdev->config.r600.max_hw_contexts = 8;
738 rdev->config.r600.max_gs_threads = 16;
739 rdev->config.r600.sx_max_export_size = 128;
740 rdev->config.r600.sx_max_export_pos_size = 16;
741 rdev->config.r600.sx_max_export_smx_size = 128;
742 rdev->config.r600.sq_num_cf_insts = 2;
743 break;
744 default:
745 break;
746 }
747
748 /* Initialize HDP */
749 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
750 WREG32((0x2c14 + j), 0x00000000);
751 WREG32((0x2c18 + j), 0x00000000);
752 WREG32((0x2c1c + j), 0x00000000);
753 WREG32((0x2c20 + j), 0x00000000);
754 WREG32((0x2c24 + j), 0x00000000);
755 }
756
757 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
758
759 /* Setup tiling */
760 tiling_config = 0;
761 ramcfg = RREG32(RAMCFG);
762 switch (rdev->config.r600.max_tile_pipes) {
763 case 1:
764 tiling_config |= PIPE_TILING(0);
765 break;
766 case 2:
767 tiling_config |= PIPE_TILING(1);
768 break;
769 case 4:
770 tiling_config |= PIPE_TILING(2);
771 break;
772 case 8:
773 tiling_config |= PIPE_TILING(3);
774 break;
775 default:
776 break;
777 }
778 tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
779 tiling_config |= GROUP_SIZE(0);
780 tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
781 if (tmp > 3) {
782 tiling_config |= ROW_TILING(3);
783 tiling_config |= SAMPLE_SPLIT(3);
784 } else {
785 tiling_config |= ROW_TILING(tmp);
786 tiling_config |= SAMPLE_SPLIT(tmp);
787 }
788 tiling_config |= BANK_SWAPS(1);
789 tmp = r600_get_tile_pipe_to_backend_map(rdev->config.r600.max_tile_pipes,
790 rdev->config.r600.max_backends,
791 (0xff << rdev->config.r600.max_backends) & 0xff);
792 tiling_config |= BACKEND_MAP(tmp);
793 WREG32(GB_TILING_CONFIG, tiling_config);
794 WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff);
795 WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff);
796
797 tmp = BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << rdev->config.r600.max_backends) & R6XX_MAX_BACKENDS_MASK);
798 WREG32(CC_RB_BACKEND_DISABLE, tmp);
799
800 /* Setup pipes */
801 tmp = INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << rdev->config.r600.max_pipes) & R6XX_MAX_PIPES_MASK);
802 tmp |= INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << rdev->config.r600.max_simds) & R6XX_MAX_SIMDS_MASK);
803 WREG32(CC_GC_SHADER_PIPE_CONFIG, tmp);
804 WREG32(GC_USER_SHADER_PIPE_CONFIG, tmp);
805
806 tmp = R6XX_MAX_BACKENDS - r600_count_pipe_bits(tmp & INACTIVE_QD_PIPES_MASK);
807 WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);
808 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK);
809
810 /* Setup some CP states */
811 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b)));
812 WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40)));
813
814 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT |
815 SYNC_WALKER | SYNC_ALIGNER));
816 /* Setup various GPU states */
817 if (rdev->family == CHIP_RV670)
818 WREG32(ARB_GDEC_RD_CNTL, 0x00000021);
819
820 tmp = RREG32(SX_DEBUG_1);
821 tmp |= SMX_EVENT_RELEASE;
822 if ((rdev->family > CHIP_R600))
823 tmp |= ENABLE_NEW_SMX_ADDRESS;
824 WREG32(SX_DEBUG_1, tmp);
825
826 if (((rdev->family) == CHIP_R600) ||
827 ((rdev->family) == CHIP_RV630) ||
828 ((rdev->family) == CHIP_RV610) ||
829 ((rdev->family) == CHIP_RV620) ||
830 ((rdev->family) == CHIP_RS780)) {
831 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE);
832 } else {
833 WREG32(DB_DEBUG, 0);
834 }
835 WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) |
836 DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4)));
837
838 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
839 WREG32(VGT_NUM_INSTANCES, 0);
840
841 WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
842 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0));
843
844 tmp = RREG32(SQ_MS_FIFO_SIZES);
845 if (((rdev->family) == CHIP_RV610) ||
846 ((rdev->family) == CHIP_RV620) ||
847 ((rdev->family) == CHIP_RS780)) {
848 tmp = (CACHE_FIFO_SIZE(0xa) |
849 FETCH_FIFO_HIWATER(0xa) |
850 DONE_FIFO_HIWATER(0xe0) |
851 ALU_UPDATE_FIFO_HIWATER(0x8));
852 } else if (((rdev->family) == CHIP_R600) ||
853 ((rdev->family) == CHIP_RV630)) {
854 tmp &= ~DONE_FIFO_HIWATER(0xff);
855 tmp |= DONE_FIFO_HIWATER(0x4);
856 }
857 WREG32(SQ_MS_FIFO_SIZES, tmp);
858
859 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
860 * should be adjusted as needed by the 2D/3D drivers. This just sets default values
861 */
862 sq_config = RREG32(SQ_CONFIG);
863 sq_config &= ~(PS_PRIO(3) |
864 VS_PRIO(3) |
865 GS_PRIO(3) |
866 ES_PRIO(3));
867 sq_config |= (DX9_CONSTS |
868 VC_ENABLE |
869 PS_PRIO(0) |
870 VS_PRIO(1) |
871 GS_PRIO(2) |
872 ES_PRIO(3));
873
874 if ((rdev->family) == CHIP_R600) {
875 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) |
876 NUM_VS_GPRS(124) |
877 NUM_CLAUSE_TEMP_GPRS(4));
878 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) |
879 NUM_ES_GPRS(0));
880 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) |
881 NUM_VS_THREADS(48) |
882 NUM_GS_THREADS(4) |
883 NUM_ES_THREADS(4));
884 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) |
885 NUM_VS_STACK_ENTRIES(128));
886 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) |
887 NUM_ES_STACK_ENTRIES(0));
888 } else if (((rdev->family) == CHIP_RV610) ||
889 ((rdev->family) == CHIP_RV620) ||
890 ((rdev->family) == CHIP_RS780)) {
891 /* no vertex cache */
892 sq_config &= ~VC_ENABLE;
893
894 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
895 NUM_VS_GPRS(44) |
896 NUM_CLAUSE_TEMP_GPRS(2));
897 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
898 NUM_ES_GPRS(17));
899 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
900 NUM_VS_THREADS(78) |
901 NUM_GS_THREADS(4) |
902 NUM_ES_THREADS(31));
903 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
904 NUM_VS_STACK_ENTRIES(40));
905 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
906 NUM_ES_STACK_ENTRIES(16));
907 } else if (((rdev->family) == CHIP_RV630) ||
908 ((rdev->family) == CHIP_RV635)) {
909 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
910 NUM_VS_GPRS(44) |
911 NUM_CLAUSE_TEMP_GPRS(2));
912 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) |
913 NUM_ES_GPRS(18));
914 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
915 NUM_VS_THREADS(78) |
916 NUM_GS_THREADS(4) |
917 NUM_ES_THREADS(31));
918 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
919 NUM_VS_STACK_ENTRIES(40));
920 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
921 NUM_ES_STACK_ENTRIES(16));
922 } else if ((rdev->family) == CHIP_RV670) {
923 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
924 NUM_VS_GPRS(44) |
925 NUM_CLAUSE_TEMP_GPRS(2));
926 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
927 NUM_ES_GPRS(17));
928 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
929 NUM_VS_THREADS(78) |
930 NUM_GS_THREADS(4) |
931 NUM_ES_THREADS(31));
932 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) |
933 NUM_VS_STACK_ENTRIES(64));
934 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) |
935 NUM_ES_STACK_ENTRIES(64));
936 }
937
938 WREG32(SQ_CONFIG, sq_config);
939 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
940 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
941 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
942 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
943 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
944
945 if (((rdev->family) == CHIP_RV610) ||
946 ((rdev->family) == CHIP_RV620) ||
947 ((rdev->family) == CHIP_RS780)) {
948 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY));
949 } else {
950 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC));
951 }
952
953 /* More default values. 2D/3D driver should adjust as needed */
954 WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) |
955 S1_X(0x4) | S1_Y(0xc)));
956 WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) |
957 S1_X(0x2) | S1_Y(0x2) |
958 S2_X(0xa) | S2_Y(0x6) |
959 S3_X(0x6) | S3_Y(0xa)));
960 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) |
961 S1_X(0x4) | S1_Y(0xc) |
962 S2_X(0x1) | S2_Y(0x6) |
963 S3_X(0xa) | S3_Y(0xe)));
964 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) |
965 S5_X(0x0) | S5_Y(0x0) |
966 S6_X(0xb) | S6_Y(0x4) |
967 S7_X(0x7) | S7_Y(0x8)));
968
969 WREG32(VGT_STRMOUT_EN, 0);
970 tmp = rdev->config.r600.max_pipes * 16;
971 switch (rdev->family) {
972 case CHIP_RV610:
973 case CHIP_RS780:
974 case CHIP_RV620:
975 tmp += 32;
976 break;
977 case CHIP_RV670:
978 tmp += 128;
979 break;
980 default:
981 break;
982 }
983 if (tmp > 256) {
984 tmp = 256;
985 }
986 WREG32(VGT_ES_PER_GS, 128);
987 WREG32(VGT_GS_PER_ES, tmp);
988 WREG32(VGT_GS_PER_VS, 2);
989 WREG32(VGT_GS_VERTEX_REUSE, 16);
990
991 /* more default values. 2D/3D driver should adjust as needed */
992 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
993 WREG32(VGT_STRMOUT_EN, 0);
994 WREG32(SX_MISC, 0);
995 WREG32(PA_SC_MODE_CNTL, 0);
996 WREG32(PA_SC_AA_CONFIG, 0);
997 WREG32(PA_SC_LINE_STIPPLE, 0);
998 WREG32(SPI_INPUT_Z, 0);
999 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
1000 WREG32(CB_COLOR7_FRAG, 0);
1001
1002 /* Clear render buffer base addresses */
1003 WREG32(CB_COLOR0_BASE, 0);
1004 WREG32(CB_COLOR1_BASE, 0);
1005 WREG32(CB_COLOR2_BASE, 0);
1006 WREG32(CB_COLOR3_BASE, 0);
1007 WREG32(CB_COLOR4_BASE, 0);
1008 WREG32(CB_COLOR5_BASE, 0);
1009 WREG32(CB_COLOR6_BASE, 0);
1010 WREG32(CB_COLOR7_BASE, 0);
1011 WREG32(CB_COLOR7_FRAG, 0);
1012
1013 switch (rdev->family) {
1014 case CHIP_RV610:
1015 case CHIP_RS780:
1016 case CHIP_RV620:
1017 tmp = TC_L2_SIZE(8);
1018 break;
1019 case CHIP_RV630:
1020 case CHIP_RV635:
1021 tmp = TC_L2_SIZE(4);
1022 break;
1023 case CHIP_R600:
1024 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT;
1025 break;
1026 default:
1027 tmp = TC_L2_SIZE(0);
1028 break;
1029 }
1030 WREG32(TC_CNTL, tmp);
1031
1032 tmp = RREG32(HDP_HOST_PATH_CNTL);
1033 WREG32(HDP_HOST_PATH_CNTL, tmp);
1034
1035 tmp = RREG32(ARB_POP);
1036 tmp |= ENABLE_TC128;
1037 WREG32(ARB_POP, tmp);
1038
1039 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1040 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
1041 NUM_CLIP_SEQ(3)));
1042 WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));
1043}
1044
1045
771fe6b9
JG		 1046/*
1047 * Indirect registers accessor
1048 */
3ce0a23d
JG		 1049u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg)
1050{
1051 u32 r;
1052
1053 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1054 (void)RREG32(PCIE_PORT_INDEX);
1055 r = RREG32(PCIE_PORT_DATA);
1056 return r;
1057}
1058
1059void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
1060{
1061 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1062 (void)RREG32(PCIE_PORT_INDEX);
1063 WREG32(PCIE_PORT_DATA, (v));
1064 (void)RREG32(PCIE_PORT_DATA);
1065}
1066
1067
1068/*
1069 * CP & Ring
1070 */
1071void r600_cp_stop(struct radeon_device *rdev)
1072{
1073 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1074}
1075
1076int r600_cp_init_microcode(struct radeon_device *rdev)
1077{
1078 struct platform_device *pdev;
1079 const char *chip_name;
1080 size_t pfp_req_size, me_req_size;
1081 char fw_name[30];
1082 int err;
1083
1084 DRM_DEBUG("\n");
1085
1086 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
1087 err = IS_ERR(pdev);
1088 if (err) {
1089 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
1090 return -EINVAL;
1091 }
1092
1093 switch (rdev->family) {
1094 case CHIP_R600: chip_name = "R600"; break;
1095 case CHIP_RV610: chip_name = "RV610"; break;
1096 case CHIP_RV630: chip_name = "RV630"; break;
1097 case CHIP_RV620: chip_name = "RV620"; break;
1098 case CHIP_RV635: chip_name = "RV635"; break;
1099 case CHIP_RV670: chip_name = "RV670"; break;
1100 case CHIP_RS780:
1101 case CHIP_RS880: chip_name = "RS780"; break;
1102 case CHIP_RV770: chip_name = "RV770"; break;
1103 case CHIP_RV730:
1104 case CHIP_RV740: chip_name = "RV730"; break;
1105 case CHIP_RV710: chip_name = "RV710"; break;
1106 default: BUG();
1107 }
1108
1109 if (rdev->family >= CHIP_RV770) {
1110 pfp_req_size = R700_PFP_UCODE_SIZE * 4;
1111 me_req_size = R700_PM4_UCODE_SIZE * 4;
1112 } else {
1113 pfp_req_size = PFP_UCODE_SIZE * 4;
1114 me_req_size = PM4_UCODE_SIZE * 12;
1115 }
1116
1117 DRM_INFO("Loading %s CP Microcode\n", chip_name);
1118
1119 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
1120 err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
1121 if (err)
1122 goto out;
1123 if (rdev->pfp_fw->size != pfp_req_size) {
1124 printk(KERN_ERR
1125 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
1126 rdev->pfp_fw->size, fw_name);
1127 err = -EINVAL;
1128 goto out;
1129 }
1130
1131 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
1132 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
1133 if (err)
1134 goto out;
1135 if (rdev->me_fw->size != me_req_size) {
1136 printk(KERN_ERR
1137 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
1138 rdev->me_fw->size, fw_name);
1139 err = -EINVAL;
1140 }
1141out:
1142 platform_device_unregister(pdev);
1143
1144 if (err) {
1145 if (err != -EINVAL)
1146 printk(KERN_ERR
1147 "r600_cp: Failed to load firmware \"%s\"\n",
1148 fw_name);
1149 release_firmware(rdev->pfp_fw);
1150 rdev->pfp_fw = NULL;
1151 release_firmware(rdev->me_fw);
1152 rdev->me_fw = NULL;
1153 }
1154 return err;
1155}
1156
1157static int r600_cp_load_microcode(struct radeon_device *rdev)
1158{
1159 const __be32 *fw_data;
1160 int i;
1161
1162 if (!rdev->me_fw || !rdev->pfp_fw)
1163 return -EINVAL;
1164
1165 r600_cp_stop(rdev);
1166
1167 WREG32(CP_RB_CNTL, RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
1168
1169 /* Reset cp */
1170 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
1171 RREG32(GRBM_SOFT_RESET);
1172 mdelay(15);
1173 WREG32(GRBM_SOFT_RESET, 0);
1174
1175 WREG32(CP_ME_RAM_WADDR, 0);
1176
1177 fw_data = (const __be32 *)rdev->me_fw->data;
1178 WREG32(CP_ME_RAM_WADDR, 0);
1179 for (i = 0; i < PM4_UCODE_SIZE * 3; i++)
1180 WREG32(CP_ME_RAM_DATA,
1181 be32_to_cpup(fw_data++));
1182
1183 fw_data = (const __be32 *)rdev->pfp_fw->data;
1184 WREG32(CP_PFP_UCODE_ADDR, 0);
1185 for (i = 0; i < PFP_UCODE_SIZE; i++)
1186 WREG32(CP_PFP_UCODE_DATA,
1187 be32_to_cpup(fw_data++));
1188
1189 WREG32(CP_PFP_UCODE_ADDR, 0);
1190 WREG32(CP_ME_RAM_WADDR, 0);
1191 WREG32(CP_ME_RAM_RADDR, 0);
1192 return 0;
1193}
1194
1195int r600_cp_start(struct radeon_device *rdev)
1196{
1197 int r;
1198 uint32_t cp_me;
1199
1200 r = radeon_ring_lock(rdev, 7);
1201 if (r) {
1202 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1203 return r;
1204 }
1205 radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5));
1206 radeon_ring_write(rdev, 0x1);
1207 if (rdev->family < CHIP_RV770) {
1208 radeon_ring_write(rdev, 0x3);
1209 radeon_ring_write(rdev, rdev->config.r600.max_hw_contexts - 1);
1210 } else {
1211 radeon_ring_write(rdev, 0x0);
1212 radeon_ring_write(rdev, rdev->config.rv770.max_hw_contexts - 1);
1213 }
1214 radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1215 radeon_ring_write(rdev, 0);
1216 radeon_ring_write(rdev, 0);
1217 radeon_ring_unlock_commit(rdev);
1218
1219 cp_me = 0xff;
1220 WREG32(R_0086D8_CP_ME_CNTL, cp_me);
1221 return 0;
1222}
1223
1224int r600_cp_resume(struct radeon_device *rdev)
1225{
1226 u32 tmp;
1227 u32 rb_bufsz;
1228 int r;
1229
1230 /* Reset cp */
1231 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
1232 RREG32(GRBM_SOFT_RESET);
1233 mdelay(15);
1234 WREG32(GRBM_SOFT_RESET, 0);
1235
1236 /* Set ring buffer size */
1237 rb_bufsz = drm_order(rdev->cp.ring_size / 8);
1238#ifdef __BIG_ENDIAN
1239 WREG32(CP_RB_CNTL, BUF_SWAP_32BIT | RB_NO_UPDATE |
1240 (drm_order(4096/8) << 8) | rb_bufsz);
1241#else
1242 WREG32(CP_RB_CNTL, RB_NO_UPDATE | (drm_order(4096/8) << 8) | rb_bufsz);
1243#endif
1244 WREG32(CP_SEM_WAIT_TIMER, 0x4);
1245
1246 /* Set the write pointer delay */
1247 WREG32(CP_RB_WPTR_DELAY, 0);
1248
1249 /* Initialize the ring buffer's read and write pointers */
1250 tmp = RREG32(CP_RB_CNTL);
1251 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
1252 WREG32(CP_RB_RPTR_WR, 0);
1253 WREG32(CP_RB_WPTR, 0);
1254 WREG32(CP_RB_RPTR_ADDR, rdev->cp.gpu_addr & 0xFFFFFFFF);
1255 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->cp.gpu_addr));
1256 mdelay(1);
1257 WREG32(CP_RB_CNTL, tmp);
1258
1259 WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8);
1260 WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
1261
1262 rdev->cp.rptr = RREG32(CP_RB_RPTR);
1263 rdev->cp.wptr = RREG32(CP_RB_WPTR);
1264
1265 r600_cp_start(rdev);
1266 rdev->cp.ready = true;
1267 r = radeon_ring_test(rdev);
1268 if (r) {
1269 rdev->cp.ready = false;
1270 return r;
1271 }
1272 return 0;
1273}
1274
1275void r600_cp_commit(struct radeon_device *rdev)
1276{
1277 WREG32(CP_RB_WPTR, rdev->cp.wptr);
1278 (void)RREG32(CP_RB_WPTR);
1279}
1280
1281void r600_ring_init(struct radeon_device *rdev, unsigned ring_size)
1282{
1283 u32 rb_bufsz;
1284
1285 /* Align ring size */
1286 rb_bufsz = drm_order(ring_size / 8);
1287 ring_size = (1 << (rb_bufsz + 1)) * 4;
1288 rdev->cp.ring_size = ring_size;
1289 rdev->cp.align_mask = 16 - 1;
1290}
1291
1292
1293/*
1294 * GPU scratch registers helpers function.
1295 */
1296void r600_scratch_init(struct radeon_device *rdev)
1297{
1298 int i;
1299
1300 rdev->scratch.num_reg = 7;
1301 for (i = 0; i < rdev->scratch.num_reg; i++) {
1302 rdev->scratch.free[i] = true;
1303 rdev->scratch.reg[i] = SCRATCH_REG0 + (i * 4);
1304 }
1305}
1306
1307int r600_ring_test(struct radeon_device *rdev)
1308{
1309 uint32_t scratch;
1310 uint32_t tmp = 0;
1311 unsigned i;
1312 int r;
1313
1314 r = radeon_scratch_get(rdev, &scratch);
1315 if (r) {
1316 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
1317 return r;
1318 }
1319 WREG32(scratch, 0xCAFEDEAD);
1320 r = radeon_ring_lock(rdev, 3);
1321 if (r) {
1322 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1323 radeon_scratch_free(rdev, scratch);
1324 return r;
1325 }
1326 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1327 radeon_ring_write(rdev, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
1328 radeon_ring_write(rdev, 0xDEADBEEF);
1329 radeon_ring_unlock_commit(rdev);
1330 for (i = 0; i < rdev->usec_timeout; i++) {
1331 tmp = RREG32(scratch);
1332 if (tmp == 0xDEADBEEF)
1333 break;
1334 DRM_UDELAY(1);
1335 }
1336 if (i < rdev->usec_timeout) {
1337 DRM_INFO("ring test succeeded in %d usecs\n", i);
1338 } else {
1339 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
1340 scratch, tmp);
1341 r = -EINVAL;
1342 }
1343 radeon_scratch_free(rdev, scratch);
1344 return r;
1345}
1346
1347/*
1348 * Writeback
1349 */
1350int r600_wb_init(struct radeon_device *rdev)
1351{
1352 int r;
1353
1354 if (rdev->wb.wb_obj == NULL) {
1355 r = radeon_object_create(rdev, NULL, 4096,
1356 true,
1357 RADEON_GEM_DOMAIN_GTT,
1358 false, &rdev->wb.wb_obj);
1359 if (r) {
1360 DRM_ERROR("radeon: failed to create WB buffer (%d).\n", r);
1361 return r;
1362 }
1363 r = radeon_object_pin(rdev->wb.wb_obj,
1364 RADEON_GEM_DOMAIN_GTT,
1365 &rdev->wb.gpu_addr);
1366 if (r) {
1367 DRM_ERROR("radeon: failed to pin WB buffer (%d).\n", r);
1368 return r;
1369 }
1370 r = radeon_object_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
1371 if (r) {
1372 DRM_ERROR("radeon: failed to map WB buffer (%d).\n", r);
1373 return r;
1374 }
1375 }
1376 WREG32(SCRATCH_ADDR, (rdev->wb.gpu_addr >> 8) & 0xFFFFFFFF);
1377 WREG32(CP_RB_RPTR_ADDR, (rdev->wb.gpu_addr + 1024) & 0xFFFFFFFC);
1378 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + 1024) & 0xFF);
1379 WREG32(SCRATCH_UMSK, 0xff);
1380 return 0;
1381}
1382
1383void r600_wb_fini(struct radeon_device *rdev)
1384{
1385 if (rdev->wb.wb_obj) {
1386 radeon_object_kunmap(rdev->wb.wb_obj);
1387 radeon_object_unpin(rdev->wb.wb_obj);
1388 radeon_object_unref(&rdev->wb.wb_obj);
1389 rdev->wb.wb = NULL;
1390 rdev->wb.wb_obj = NULL;
1391 }
1392}
1393
1394
1395/*
1396 * CS
1397 */
1398void r600_fence_ring_emit(struct radeon_device *rdev,
1399 struct radeon_fence *fence)
1400{
1401 /* Emit fence sequence & fire IRQ */
1402 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1403 radeon_ring_write(rdev, ((rdev->fence_drv.scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
1404 radeon_ring_write(rdev, fence->seq);
1405}
1406
1407int r600_copy_dma(struct radeon_device *rdev,
1408 uint64_t src_offset,
1409 uint64_t dst_offset,
1410 unsigned num_pages,
1411 struct radeon_fence *fence)
1412{
1413 /* FIXME: implement */
1414 return 0;
1415}
1416
1417int r600_copy_blit(struct radeon_device *rdev,
1418 uint64_t src_offset, uint64_t dst_offset,
1419 unsigned num_pages, struct radeon_fence *fence)
1420{
1421 r600_blit_prepare_copy(rdev, num_pages * 4096);
1422 r600_kms_blit_copy(rdev, src_offset, dst_offset, num_pages * 4096);
1423 r600_blit_done_copy(rdev, fence);
1424 return 0;
1425}
1426
1427int r600_irq_process(struct radeon_device *rdev)
1428{
1429 /* FIXME: implement */
1430 return 0;
1431}
1432
1433int r600_irq_set(struct radeon_device *rdev)
1434{
1435 /* FIXME: implement */
1436 return 0;
1437}
1438
1439int r600_set_surface_reg(struct radeon_device *rdev, int reg,
1440 uint32_t tiling_flags, uint32_t pitch,
1441 uint32_t offset, uint32_t obj_size)
1442{
1443 /* FIXME: implement */
1444 return 0;
1445}
1446
1447void r600_clear_surface_reg(struct radeon_device *rdev, int reg)
1448{
1449 /* FIXME: implement */
1450}
1451
1452
1453bool r600_card_posted(struct radeon_device *rdev)
1454{
1455 uint32_t reg;
1456
1457 /* first check CRTCs */
1458 reg = RREG32(D1CRTC_CONTROL) |
1459 RREG32(D2CRTC_CONTROL);
1460 if (reg & CRTC_EN)
1461 return true;
1462
1463 /* then check MEM_SIZE, in case the crtcs are off */
1464 if (RREG32(CONFIG_MEMSIZE))
1465 return true;
1466
1467 return false;
1468}
1469
1470int r600_resume(struct radeon_device *rdev)
1471{
1472 int r;
1473
1474 r600_gpu_reset(rdev);
1475 r600_mc_resume(rdev);
1476 r = r600_pcie_gart_enable(rdev);
1477 if (r)
1478 return r;
1479 r600_gpu_init(rdev);
1480 r = radeon_ring_init(rdev, rdev->cp.ring_size);
1481 if (r)
1482 return r;
1483 r = r600_cp_load_microcode(rdev);
1484 if (r)
1485 return r;
1486 r = r600_cp_resume(rdev);
1487 if (r)
1488 return r;
1489 r = r600_wb_init(rdev);
1490 if (r)
1491 return r;
1492 return 0;
1493}
1494
1495int r600_suspend(struct radeon_device *rdev)
1496{
1497 /* FIXME: we should wait for ring to be empty */
1498 r600_cp_stop(rdev);
4aac0473 1499 r600_pcie_gart_disable(rdev);
3ce0a23d
JG		 1500 return 0;
1501}
1502
1503/* Plan is to move initialization in that function and use
1504 * helper function so that radeon_device_init pretty much
1505 * do nothing more than calling asic specific function. This
1506 * should also allow to remove a bunch of callback function
1507 * like vram_info.
1508 */
1509int r600_init(struct radeon_device *rdev)
771fe6b9 1510{
3ce0a23d 1511 int r;
771fe6b9 1512
3ce0a23d
JG		 1513 rdev->new_init_path = true;
1514 r = radeon_dummy_page_init(rdev);
1515 if (r)
1516 return r;
1517 if (r600_debugfs_mc_info_init(rdev)) {
1518 DRM_ERROR("Failed to register debugfs file for mc !\n");
1519 }
1520 /* This don't do much */
1521 r = radeon_gem_init(rdev);
1522 if (r)
1523 return r;
1524 /* Read BIOS */
1525 if (!radeon_get_bios(rdev)) {
1526 if (ASIC_IS_AVIVO(rdev))
1527 return -EINVAL;
1528 }
1529 /* Must be an ATOMBIOS */
1530 if (!rdev->is_atom_bios)
1531 return -EINVAL;
1532 r = radeon_atombios_init(rdev);
1533 if (r)
1534 return r;
1535 /* Post card if necessary */
1536 if (!r600_card_posted(rdev) && rdev->bios) {
1537 DRM_INFO("GPU not posted. posting now...\n");
1538 atom_asic_init(rdev->mode_info.atom_context);
1539 }
1540 /* Initialize scratch registers */
1541 r600_scratch_init(rdev);
1542 /* Initialize surface registers */
1543 radeon_surface_init(rdev);
5e6dde7e 1544 radeon_get_clock_info(rdev->ddev);
3ce0a23d
JG		 1545 r = radeon_clocks_init(rdev);
1546 if (r)
1547 return r;
1548 /* Fence driver */
1549 r = radeon_fence_driver_init(rdev);
1550 if (r)
1551 return r;
1552 r = r600_mc_init(rdev);
1553 if (r) {
1554 if (rdev->flags & RADEON_IS_AGP) {
1555 /* Retry with disabling AGP */
1556 r600_fini(rdev);
1557 rdev->flags &= ~RADEON_IS_AGP;
1558 return r600_init(rdev);
1559 }
1560 return r;
1561 }
1562 /* Memory manager */
1563 r = radeon_object_init(rdev);
1564 if (r)
1565 return r;
1566 rdev->cp.ring_obj = NULL;
1567 r600_ring_init(rdev, 1024 * 1024);
1568
1569 if (!rdev->me_fw || !rdev->pfp_fw) {
1570 r = r600_cp_init_microcode(rdev);
1571 if (r) {
1572 DRM_ERROR("Failed to load firmware!\n");
1573 return r;
1574 }
1575 }
1576
4aac0473
JG		 1577 r = r600_pcie_gart_init(rdev);
1578 if (r)
1579 return r;
1580
733289c2 1581 rdev->accel_working = true;
3ce0a23d
JG		 1582 r = r600_resume(rdev);
1583 if (r) {
1584 if (rdev->flags & RADEON_IS_AGP) {
1585 /* Retry with disabling AGP */
1586 r600_fini(rdev);
1587 rdev->flags &= ~RADEON_IS_AGP;
1588 return r600_init(rdev);
1589 }
733289c2 1590 rdev->accel_working = false;
3ce0a23d 1591 }
733289c2
JG		 1592 if (rdev->accel_working) {
1593 r = radeon_ib_pool_init(rdev);
1594 if (r) {
1595 DRM_ERROR("radeon: failled initializing IB pool (%d).\n", r);
1596 rdev->accel_working = false;
1597 }
1598 r = r600_blit_init(rdev);
1599 if (r) {
1600 DRM_ERROR("radeon: failled blitter (%d).\n", r);
1601 rdev->accel_working = false;
1602 }
1603 r = radeon_ib_test(rdev);
1604 if (r) {
1605 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
1606 rdev->accel_working = false;
1607 }
3ce0a23d
JG		 1608 }
1609 return 0;
1610}
1611
1612void r600_fini(struct radeon_device *rdev)
1613{
1614 /* Suspend operations */
1615 r600_suspend(rdev);
1616
1617 r600_blit_fini(rdev);
1618 radeon_ring_fini(rdev);
4aac0473 1619 r600_pcie_gart_fini(rdev);
3ce0a23d
JG		 1620 radeon_gem_fini(rdev);
1621 radeon_fence_driver_fini(rdev);
1622 radeon_clocks_fini(rdev);
1623#if __OS_HAS_AGP
1624 if (rdev->flags & RADEON_IS_AGP)
1625 radeon_agp_fini(rdev);
1626#endif
1627 radeon_object_fini(rdev);
1628 if (rdev->is_atom_bios)
1629 radeon_atombios_fini(rdev);
1630 else
1631 radeon_combios_fini(rdev);
1632 kfree(rdev->bios);
1633 rdev->bios = NULL;
1634 radeon_dummy_page_fini(rdev);
1635}
1636
1637
1638/*
1639 * CS stuff
1640 */
1641void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
1642{
1643 /* FIXME: implement */
1644 radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
1645 radeon_ring_write(rdev, ib->gpu_addr & 0xFFFFFFFC);
1646 radeon_ring_write(rdev, upper_32_bits(ib->gpu_addr) & 0xFF);
1647 radeon_ring_write(rdev, ib->length_dw);
1648}
1649
1650int r600_ib_test(struct radeon_device *rdev)
1651{
1652 struct radeon_ib *ib;
1653 uint32_t scratch;
1654 uint32_t tmp = 0;
1655 unsigned i;
1656 int r;
1657
1658 r = radeon_scratch_get(rdev, &scratch);
1659 if (r) {
1660 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
1661 return r;
1662 }
1663 WREG32(scratch, 0xCAFEDEAD);
1664 r = radeon_ib_get(rdev, &ib);
1665 if (r) {
1666 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
1667 return r;
1668 }
1669 ib->ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
1670 ib->ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
1671 ib->ptr[2] = 0xDEADBEEF;
1672 ib->ptr[3] = PACKET2(0);
1673 ib->ptr[4] = PACKET2(0);
1674 ib->ptr[5] = PACKET2(0);
1675 ib->ptr[6] = PACKET2(0);
1676 ib->ptr[7] = PACKET2(0);
1677 ib->ptr[8] = PACKET2(0);
1678 ib->ptr[9] = PACKET2(0);
1679 ib->ptr[10] = PACKET2(0);
1680 ib->ptr[11] = PACKET2(0);
1681 ib->ptr[12] = PACKET2(0);
1682 ib->ptr[13] = PACKET2(0);
1683 ib->ptr[14] = PACKET2(0);
1684 ib->ptr[15] = PACKET2(0);
1685 ib->length_dw = 16;
1686 r = radeon_ib_schedule(rdev, ib);
1687 if (r) {
1688 radeon_scratch_free(rdev, scratch);
1689 radeon_ib_free(rdev, &ib);
1690 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
1691 return r;
1692 }
1693 r = radeon_fence_wait(ib->fence, false);
1694 if (r) {
1695 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
1696 return r;
1697 }
1698 for (i = 0; i < rdev->usec_timeout; i++) {
1699 tmp = RREG32(scratch);
1700 if (tmp == 0xDEADBEEF)
1701 break;
1702 DRM_UDELAY(1);
1703 }
1704 if (i < rdev->usec_timeout) {
1705 DRM_INFO("ib test succeeded in %u usecs\n", i);
1706 } else {
1707 DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n",
1708 scratch, tmp);
1709 r = -EINVAL;
1710 }
1711 radeon_scratch_free(rdev, scratch);
1712 radeon_ib_free(rdev, &ib);
771fe6b9
JG		 1713 return r;
1714}
1715
3ce0a23d
JG		 1716
1717
1718
1719/*
1720 * Debugfs info
1721 */
1722#if defined(CONFIG_DEBUG_FS)
1723
1724static int r600_debugfs_cp_ring_info(struct seq_file *m, void *data)
771fe6b9 1725{
3ce0a23d
JG		 1726 struct drm_info_node *node = (struct drm_info_node *) m->private;
1727 struct drm_device *dev = node->minor->dev;
1728 struct radeon_device *rdev = dev->dev_private;
1729 uint32_t rdp, wdp;
1730 unsigned count, i, j;
1731
1732 radeon_ring_free_size(rdev);
1733 rdp = RREG32(CP_RB_RPTR);
1734 wdp = RREG32(CP_RB_WPTR);
1735 count = (rdp + rdev->cp.ring_size - wdp) & rdev->cp.ptr_mask;
1736 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(CP_STAT));
1737 seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
1738 seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
1739 seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
1740 seq_printf(m, "%u dwords in ring\n", count);
1741 for (j = 0; j <= count; j++) {
1742 i = (rdp + j) & rdev->cp.ptr_mask;
1743 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
1744 }
1745 return 0;
1746}
1747
1748static int r600_debugfs_mc_info(struct seq_file *m, void *data)
1749{
1750 struct drm_info_node *node = (struct drm_info_node *) m->private;
1751 struct drm_device *dev = node->minor->dev;
1752 struct radeon_device *rdev = dev->dev_private;
1753
1754 DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS);
1755 DREG32_SYS(m, rdev, VM_L2_STATUS);
1756 return 0;
1757}
1758
1759static struct drm_info_list r600_mc_info_list[] = {
1760 {"r600_mc_info", r600_debugfs_mc_info, 0, NULL},
1761 {"r600_ring_info", r600_debugfs_cp_ring_info, 0, NULL},
1762};
1763#endif
1764
1765int r600_debugfs_mc_info_init(struct radeon_device *rdev)
1766{
1767#if defined(CONFIG_DEBUG_FS)
1768 return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list));
1769#else
1770 return 0;
1771#endif
771fe6b9 1772}
Linux kernel - Deliverables
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