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Merge branch 'for-linus' of git://git.infradead.org/ubi-2.6
[deliverable/linux.git] / drivers / gpu / drm / radeon / r600.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
5a0e3ad6 28#include <linux/slab.h>
3ce0a23d
JG		 29#include <linux/seq_file.h>
30#include <linux/firmware.h>
31#include <linux/platform_device.h>
771fe6b9 32#include "drmP.h"
3ce0a23d 33#include "radeon_drm.h"
771fe6b9 34#include "radeon.h"
e6990375 35#include "radeon_asic.h"
3ce0a23d 36#include "radeon_mode.h"
3ce0a23d 37#include "r600d.h"
3ce0a23d 38#include "atom.h"
d39c3b89 39#include "avivod.h"
771fe6b9 40
3ce0a23d
JG		 41#define PFP_UCODE_SIZE 576
42#define PM4_UCODE_SIZE 1792
d8f60cfc 43#define RLC_UCODE_SIZE 768
3ce0a23d
JG		 44#define R700_PFP_UCODE_SIZE 848
45#define R700_PM4_UCODE_SIZE 1360
d8f60cfc 46#define R700_RLC_UCODE_SIZE 1024
fe251e2f
AD		 47#define EVERGREEN_PFP_UCODE_SIZE 1120
48#define EVERGREEN_PM4_UCODE_SIZE 1376
45f9a39b 49#define EVERGREEN_RLC_UCODE_SIZE 768
3ce0a23d
JG		 50
51/* Firmware Names */
52MODULE_FIRMWARE("radeon/R600_pfp.bin");
53MODULE_FIRMWARE("radeon/R600_me.bin");
54MODULE_FIRMWARE("radeon/RV610_pfp.bin");
55MODULE_FIRMWARE("radeon/RV610_me.bin");
56MODULE_FIRMWARE("radeon/RV630_pfp.bin");
57MODULE_FIRMWARE("radeon/RV630_me.bin");
58MODULE_FIRMWARE("radeon/RV620_pfp.bin");
59MODULE_FIRMWARE("radeon/RV620_me.bin");
60MODULE_FIRMWARE("radeon/RV635_pfp.bin");
61MODULE_FIRMWARE("radeon/RV635_me.bin");
62MODULE_FIRMWARE("radeon/RV670_pfp.bin");
63MODULE_FIRMWARE("radeon/RV670_me.bin");
64MODULE_FIRMWARE("radeon/RS780_pfp.bin");
65MODULE_FIRMWARE("radeon/RS780_me.bin");
66MODULE_FIRMWARE("radeon/RV770_pfp.bin");
67MODULE_FIRMWARE("radeon/RV770_me.bin");
68MODULE_FIRMWARE("radeon/RV730_pfp.bin");
69MODULE_FIRMWARE("radeon/RV730_me.bin");
70MODULE_FIRMWARE("radeon/RV710_pfp.bin");
71MODULE_FIRMWARE("radeon/RV710_me.bin");
d8f60cfc
AD		 72MODULE_FIRMWARE("radeon/R600_rlc.bin");
73MODULE_FIRMWARE("radeon/R700_rlc.bin");
fe251e2f
AD		 74MODULE_FIRMWARE("radeon/CEDAR_pfp.bin");
75MODULE_FIRMWARE("radeon/CEDAR_me.bin");
45f9a39b 76MODULE_FIRMWARE("radeon/CEDAR_rlc.bin");
fe251e2f
AD		 77MODULE_FIRMWARE("radeon/REDWOOD_pfp.bin");
78MODULE_FIRMWARE("radeon/REDWOOD_me.bin");
45f9a39b 79MODULE_FIRMWARE("radeon/REDWOOD_rlc.bin");
fe251e2f
AD		 80MODULE_FIRMWARE("radeon/JUNIPER_pfp.bin");
81MODULE_FIRMWARE("radeon/JUNIPER_me.bin");
45f9a39b 82MODULE_FIRMWARE("radeon/JUNIPER_rlc.bin");
a7433742 83MODULE_FIRMWARE("radeon/CYPRESS_pfp.bin");
fe251e2f 84MODULE_FIRMWARE("radeon/CYPRESS_me.bin");
45f9a39b 85MODULE_FIRMWARE("radeon/CYPRESS_rlc.bin");
439bd6cd
AD		 86MODULE_FIRMWARE("radeon/PALM_pfp.bin");
87MODULE_FIRMWARE("radeon/PALM_me.bin");
88MODULE_FIRMWARE("radeon/SUMO_rlc.bin");
3ce0a23d
JG		 89
90int r600_debugfs_mc_info_init(struct radeon_device *rdev);
771fe6b9 91
1a029b76 92/* r600,rv610,rv630,rv620,rv635,rv670 */
771fe6b9
JG		 93int r600_mc_wait_for_idle(struct radeon_device *rdev);
94void r600_gpu_init(struct radeon_device *rdev);
3ce0a23d 95void r600_fini(struct radeon_device *rdev);
45f9a39b 96void r600_irq_disable(struct radeon_device *rdev);
9e46a48d 97static void r600_pcie_gen2_enable(struct radeon_device *rdev);
771fe6b9 98
21a8122a
AD		 99/* get temperature in millidegrees */
100u32 rv6xx_get_temp(struct radeon_device *rdev)
101{
102 u32 temp = (RREG32(CG_THERMAL_STATUS) & ASIC_T_MASK) >>
103 ASIC_T_SHIFT;
21a8122a 104
b2298fd2 105 return temp * 1000;
21a8122a
AD		 106}
107
ce8f5370 108void r600_pm_get_dynpm_state(struct radeon_device *rdev)
a48b9b4e
AD		 109{
110 int i;
111
ce8f5370
AD		 112 rdev->pm.dynpm_can_upclock = true;
113 rdev->pm.dynpm_can_downclock = true;
a48b9b4e
AD		 114
115 /* power state array is low to high, default is first */
116 if ((rdev->flags & RADEON_IS_IGP) || (rdev->family == CHIP_R600)) {
117 int min_power_state_index = 0;
118
119 if (rdev->pm.num_power_states > 2)
120 min_power_state_index = 1;
121
ce8f5370
AD		 122 switch (rdev->pm.dynpm_planned_action) {
123 case DYNPM_ACTION_MINIMUM:
a48b9b4e
AD		 124 rdev->pm.requested_power_state_index = min_power_state_index;
125 rdev->pm.requested_clock_mode_index = 0;
ce8f5370 126 rdev->pm.dynpm_can_downclock = false;
a48b9b4e 127 break;
ce8f5370 128 case DYNPM_ACTION_DOWNCLOCK:
a48b9b4e
AD		 129 if (rdev->pm.current_power_state_index == min_power_state_index) {
130 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
ce8f5370 131 rdev->pm.dynpm_can_downclock = false;
a48b9b4e
AD		 132 } else {
133 if (rdev->pm.active_crtc_count > 1) {
134 for (i = 0; i < rdev->pm.num_power_states; i++) {
d7311171 135 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
a48b9b4e
AD		 136 continue;
137 else if (i >= rdev->pm.current_power_state_index) {
138 rdev->pm.requested_power_state_index =
139 rdev->pm.current_power_state_index;
140 break;
141 } else {
142 rdev->pm.requested_power_state_index = i;
143 break;
144 }
145 }
773c3fa3
AD		 146 } else {
147 if (rdev->pm.current_power_state_index == 0)
148 rdev->pm.requested_power_state_index =
149 rdev->pm.num_power_states - 1;
150 else
151 rdev->pm.requested_power_state_index =
152 rdev->pm.current_power_state_index - 1;
153 }
a48b9b4e
AD		 154 }
155 rdev->pm.requested_clock_mode_index = 0;
d7311171
AD		 156 /* don't use the power state if crtcs are active and no display flag is set */
157 if ((rdev->pm.active_crtc_count > 0) &&
158 (rdev->pm.power_state[rdev->pm.requested_power_state_index].
159 clock_info[rdev->pm.requested_clock_mode_index].flags &
160 RADEON_PM_MODE_NO_DISPLAY)) {
161 rdev->pm.requested_power_state_index++;
162 }
a48b9b4e 163 break;
ce8f5370 164 case DYNPM_ACTION_UPCLOCK:
a48b9b4e
AD		 165 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
166 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
ce8f5370 167 rdev->pm.dynpm_can_upclock = false;
a48b9b4e
AD		 168 } else {
169 if (rdev->pm.active_crtc_count > 1) {
170 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
d7311171 171 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
a48b9b4e
AD		 172 continue;
173 else if (i <= rdev->pm.current_power_state_index) {
174 rdev->pm.requested_power_state_index =
175 rdev->pm.current_power_state_index;
176 break;
177 } else {
178 rdev->pm.requested_power_state_index = i;
179 break;
180 }
181 }
182 } else
183 rdev->pm.requested_power_state_index =
184 rdev->pm.current_power_state_index + 1;
185 }
186 rdev->pm.requested_clock_mode_index = 0;
187 break;
ce8f5370 188 case DYNPM_ACTION_DEFAULT:
58e21dff
AD		 189 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
190 rdev->pm.requested_clock_mode_index = 0;
ce8f5370 191 rdev->pm.dynpm_can_upclock = false;
58e21dff 192 break;
ce8f5370 193 case DYNPM_ACTION_NONE:
a48b9b4e
AD		 194 default:
195 DRM_ERROR("Requested mode for not defined action\n");
196 return;
197 }
198 } else {
199 /* XXX select a power state based on AC/DC, single/dualhead, etc. */
200 /* for now just select the first power state and switch between clock modes */
201 /* power state array is low to high, default is first (0) */
202 if (rdev->pm.active_crtc_count > 1) {
203 rdev->pm.requested_power_state_index = -1;
204 /* start at 1 as we don't want the default mode */
205 for (i = 1; i < rdev->pm.num_power_states; i++) {
d7311171 206 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
a48b9b4e
AD		 207 continue;
208 else if ((rdev->pm.power_state[i].type == POWER_STATE_TYPE_PERFORMANCE) ||
209 (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY)) {
210 rdev->pm.requested_power_state_index = i;
211 break;
212 }
213 }
214 /* if nothing selected, grab the default state. */
215 if (rdev->pm.requested_power_state_index == -1)
216 rdev->pm.requested_power_state_index = 0;
217 } else
218 rdev->pm.requested_power_state_index = 1;
219
ce8f5370
AD		 220 switch (rdev->pm.dynpm_planned_action) {
221 case DYNPM_ACTION_MINIMUM:
a48b9b4e 222 rdev->pm.requested_clock_mode_index = 0;
ce8f5370 223 rdev->pm.dynpm_can_downclock = false;
a48b9b4e 224 break;
ce8f5370 225 case DYNPM_ACTION_DOWNCLOCK:
a48b9b4e
AD		 226 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
227 if (rdev->pm.current_clock_mode_index == 0) {
228 rdev->pm.requested_clock_mode_index = 0;
ce8f5370 229 rdev->pm.dynpm_can_downclock = false;
a48b9b4e
AD		 230 } else
231 rdev->pm.requested_clock_mode_index =
232 rdev->pm.current_clock_mode_index - 1;
233 } else {
234 rdev->pm.requested_clock_mode_index = 0;
ce8f5370 235 rdev->pm.dynpm_can_downclock = false;
a48b9b4e 236 }
d7311171
AD		 237 /* don't use the power state if crtcs are active and no display flag is set */
238 if ((rdev->pm.active_crtc_count > 0) &&
239 (rdev->pm.power_state[rdev->pm.requested_power_state_index].
240 clock_info[rdev->pm.requested_clock_mode_index].flags &
241 RADEON_PM_MODE_NO_DISPLAY)) {
242 rdev->pm.requested_clock_mode_index++;
243 }
a48b9b4e 244 break;
ce8f5370 245 case DYNPM_ACTION_UPCLOCK:
a48b9b4e
AD		 246 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
247 if (rdev->pm.current_clock_mode_index ==
248 (rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1)) {
249 rdev->pm.requested_clock_mode_index = rdev->pm.current_clock_mode_index;
ce8f5370 250 rdev->pm.dynpm_can_upclock = false;
a48b9b4e
AD		 251 } else
252 rdev->pm.requested_clock_mode_index =
253 rdev->pm.current_clock_mode_index + 1;
254 } else {
255 rdev->pm.requested_clock_mode_index =
256 rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1;
ce8f5370 257 rdev->pm.dynpm_can_upclock = false;
a48b9b4e
AD		 258 }
259 break;
ce8f5370 260 case DYNPM_ACTION_DEFAULT:
58e21dff
AD		 261 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
262 rdev->pm.requested_clock_mode_index = 0;
ce8f5370 263 rdev->pm.dynpm_can_upclock = false;
58e21dff 264 break;
ce8f5370 265 case DYNPM_ACTION_NONE:
a48b9b4e
AD		 266 default:
267 DRM_ERROR("Requested mode for not defined action\n");
268 return;
269 }
270 }
271
d9fdaafb 272 DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
ce8a3eb2
AD		 273 rdev->pm.power_state[rdev->pm.requested_power_state_index].
274 clock_info[rdev->pm.requested_clock_mode_index].sclk,
275 rdev->pm.power_state[rdev->pm.requested_power_state_index].
276 clock_info[rdev->pm.requested_clock_mode_index].mclk,
277 rdev->pm.power_state[rdev->pm.requested_power_state_index].
278 pcie_lanes);
a48b9b4e
AD		 279}
280
ce8f5370
AD		 281static int r600_pm_get_type_index(struct radeon_device *rdev,
282 enum radeon_pm_state_type ps_type,
283 int instance)
bae6b562 284{
ce8f5370
AD		 285 int i;
286 int found_instance = -1;
bae6b562 287
ce8f5370
AD		 288 for (i = 0; i < rdev->pm.num_power_states; i++) {
289 if (rdev->pm.power_state[i].type == ps_type) {
290 found_instance++;
291 if (found_instance == instance)
292 return i;
a424816f 293 }
ce8f5370
AD		 294 }
295 /* return default if no match */
296 return rdev->pm.default_power_state_index;
297}
298
299void rs780_pm_init_profile(struct radeon_device *rdev)
300{
301 if (rdev->pm.num_power_states == 2) {
302 /* default */
303 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
304 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
305 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
306 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
307 /* low sh */
308 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
309 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
310 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
311 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 312 /* mid sh */
313 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
314 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
315 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
316 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 317 /* high sh */
318 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
319 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
320 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
321 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
322 /* low mh */
323 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
324 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
325 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
326 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 327 /* mid mh */
328 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
329 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
330 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
331 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 332 /* high mh */
333 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
334 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 1;
335 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
336 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
337 } else if (rdev->pm.num_power_states == 3) {
338 /* default */
339 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
340 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
341 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
342 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
343 /* low sh */
344 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
345 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
346 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
347 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 348 /* mid sh */
349 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
350 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
351 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
352 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 353 /* high sh */
354 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
355 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 2;
356 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
357 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
358 /* low mh */
359 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 1;
360 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 1;
361 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
362 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 363 /* mid mh */
364 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 1;
365 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 1;
366 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
367 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 368 /* high mh */
369 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 1;
370 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
371 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
372 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
373 } else {
374 /* default */
375 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
376 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
377 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
378 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
379 /* low sh */
380 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 2;
381 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 2;
382 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
383 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 384 /* mid sh */
385 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 2;
386 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 2;
387 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
388 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 389 /* high sh */
390 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 2;
391 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 3;
392 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
393 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
394 /* low mh */
395 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
396 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
397 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
398 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 399 /* mid mh */
400 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
401 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
402 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
403 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 404 /* high mh */
405 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
406 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 3;
407 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
408 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
409 }
410}
bae6b562 411
ce8f5370
AD		 412void r600_pm_init_profile(struct radeon_device *rdev)
413{
414 if (rdev->family == CHIP_R600) {
415 /* XXX */
416 /* default */
417 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
418 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
419 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
4bff5171 420 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 421 /* low sh */
422 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
423 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
424 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
4bff5171 425 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 426 /* mid sh */
427 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
428 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
429 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
430 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 431 /* high sh */
432 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
433 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
434 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
4bff5171 435 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 436 /* low mh */
437 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
438 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
439 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
4bff5171 440 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 441 /* mid mh */
442 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
443 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
444 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
445 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 446 /* high mh */
447 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
448 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
449 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
4bff5171 450 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 451 } else {
452 if (rdev->pm.num_power_states < 4) {
453 /* default */
454 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
455 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
456 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
457 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
458 /* low sh */
4bff5171
AD		 459 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
460 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
ce8f5370 461 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
c9e75b21
AD		 462 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
463 /* mid sh */
464 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
465 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
466 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
467 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
ce8f5370 468 /* high sh */
4bff5171
AD		 469 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
470 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
ce8f5370
AD		 471 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
472 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
473 /* low mh */
4bff5171
AD		 474 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
475 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 2;
ce8f5370 476 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
c9e75b21
AD		 477 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
478 /* low mh */
479 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
480 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 2;
481 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
482 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
ce8f5370 483 /* high mh */
4bff5171
AD		 484 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
485 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
ce8f5370
AD		 486 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
487 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
488 } else {
489 /* default */
490 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
491 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
492 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
493 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
494 /* low sh */
4bff5171
AD		 495 if (rdev->flags & RADEON_IS_MOBILITY) {
496 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx =
497 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
498 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx =
499 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
500 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
c9e75b21 501 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
4bff5171
AD		 502 } else {
503 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx =
504 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
505 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx =
506 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
507 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
c9e75b21
AD		 508 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
509 }
510 /* mid sh */
511 if (rdev->flags & RADEON_IS_MOBILITY) {
512 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx =
513 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
514 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx =
515 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
516 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
517 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
518 } else {
519 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx =
520 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
521 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx =
522 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
523 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
524 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
4bff5171 525 }
ce8f5370 526 /* high sh */
4bff5171
AD		 527 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx =
528 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
529 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx =
530 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
ce8f5370
AD		 531 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
532 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
533 /* low mh */
4bff5171
AD		 534 if (rdev->flags & RADEON_IS_MOBILITY) {
535 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx =
536 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
537 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx =
538 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
539 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
c9e75b21 540 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
4bff5171
AD		 541 } else {
542 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx =
543 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
544 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx =
545 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
546 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
c9e75b21
AD		 547 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
548 }
549 /* mid mh */
550 if (rdev->flags & RADEON_IS_MOBILITY) {
551 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx =
552 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
553 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx =
554 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
555 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
556 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
557 } else {
558 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx =
559 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
560 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx =
561 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
562 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
563 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
4bff5171 564 }
ce8f5370 565 /* high mh */
4bff5171
AD		 566 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx =
567 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
568 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx =
569 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
ce8f5370
AD		 570 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
571 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
572 }
573 }
bae6b562
AD		 574}
575
49e02b73
AD		 576void r600_pm_misc(struct radeon_device *rdev)
577{
a081a9d6
RM		 578 int req_ps_idx = rdev->pm.requested_power_state_index;
579 int req_cm_idx = rdev->pm.requested_clock_mode_index;
580 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
581 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
7ac9aa5a 582
4d60173f
AD		 583 if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
584 if (voltage->voltage != rdev->pm.current_vddc) {
585 radeon_atom_set_voltage(rdev, voltage->voltage);
586 rdev->pm.current_vddc = voltage->voltage;
d9fdaafb 587 DRM_DEBUG_DRIVER("Setting: v: %d\n", voltage->voltage);
4d60173f
AD		 588 }
589 }
49e02b73
AD		 590}
591
def9ba9c
AD		 592bool r600_gui_idle(struct radeon_device *rdev)
593{
594 if (RREG32(GRBM_STATUS) & GUI_ACTIVE)
595 return false;
596 else
597 return true;
598}
599
e0df1ac5
AD		 600/* hpd for digital panel detect/disconnect */
601bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
602{
603 bool connected = false;
604
605 if (ASIC_IS_DCE3(rdev)) {
606 switch (hpd) {
607 case RADEON_HPD_1:
608 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
609 connected = true;
610 break;
611 case RADEON_HPD_2:
612 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
613 connected = true;
614 break;
615 case RADEON_HPD_3:
616 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
617 connected = true;
618 break;
619 case RADEON_HPD_4:
620 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
621 connected = true;
622 break;
623 /* DCE 3.2 */
624 case RADEON_HPD_5:
625 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
626 connected = true;
627 break;
628 case RADEON_HPD_6:
629 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
630 connected = true;
631 break;
632 default:
633 break;
634 }
635 } else {
636 switch (hpd) {
637 case RADEON_HPD_1:
638 if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
639 connected = true;
640 break;
641 case RADEON_HPD_2:
642 if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
643 connected = true;
644 break;
645 case RADEON_HPD_3:
646 if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
647 connected = true;
648 break;
649 default:
650 break;
651 }
652 }
653 return connected;
654}
655
656void r600_hpd_set_polarity(struct radeon_device *rdev,
429770b3 657 enum radeon_hpd_id hpd)
e0df1ac5
AD		 658{
659 u32 tmp;
660 bool connected = r600_hpd_sense(rdev, hpd);
661
662 if (ASIC_IS_DCE3(rdev)) {
663 switch (hpd) {
664 case RADEON_HPD_1:
665 tmp = RREG32(DC_HPD1_INT_CONTROL);
666 if (connected)
667 tmp &= ~DC_HPDx_INT_POLARITY;
668 else
669 tmp |= DC_HPDx_INT_POLARITY;
670 WREG32(DC_HPD1_INT_CONTROL, tmp);
671 break;
672 case RADEON_HPD_2:
673 tmp = RREG32(DC_HPD2_INT_CONTROL);
674 if (connected)
675 tmp &= ~DC_HPDx_INT_POLARITY;
676 else
677 tmp |= DC_HPDx_INT_POLARITY;
678 WREG32(DC_HPD2_INT_CONTROL, tmp);
679 break;
680 case RADEON_HPD_3:
681 tmp = RREG32(DC_HPD3_INT_CONTROL);
682 if (connected)
683 tmp &= ~DC_HPDx_INT_POLARITY;
684 else
685 tmp |= DC_HPDx_INT_POLARITY;
686 WREG32(DC_HPD3_INT_CONTROL, tmp);
687 break;
688 case RADEON_HPD_4:
689 tmp = RREG32(DC_HPD4_INT_CONTROL);
690 if (connected)
691 tmp &= ~DC_HPDx_INT_POLARITY;
692 else
693 tmp |= DC_HPDx_INT_POLARITY;
694 WREG32(DC_HPD4_INT_CONTROL, tmp);
695 break;
696 case RADEON_HPD_5:
697 tmp = RREG32(DC_HPD5_INT_CONTROL);
698 if (connected)
699 tmp &= ~DC_HPDx_INT_POLARITY;
700 else
701 tmp |= DC_HPDx_INT_POLARITY;
702 WREG32(DC_HPD5_INT_CONTROL, tmp);
703 break;
704 /* DCE 3.2 */
705 case RADEON_HPD_6:
706 tmp = RREG32(DC_HPD6_INT_CONTROL);
707 if (connected)
708 tmp &= ~DC_HPDx_INT_POLARITY;
709 else
710 tmp |= DC_HPDx_INT_POLARITY;
711 WREG32(DC_HPD6_INT_CONTROL, tmp);
712 break;
713 default:
714 break;
715 }
716 } else {
717 switch (hpd) {
718 case RADEON_HPD_1:
719 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
720 if (connected)
721 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
722 else
723 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
724 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
725 break;
726 case RADEON_HPD_2:
727 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
728 if (connected)
729 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
730 else
731 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
732 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
733 break;
734 case RADEON_HPD_3:
735 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
736 if (connected)
737 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
738 else
739 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
740 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
741 break;
742 default:
743 break;
744 }
745 }
746}
747
748void r600_hpd_init(struct radeon_device *rdev)
749{
750 struct drm_device *dev = rdev->ddev;
751 struct drm_connector *connector;
752
753 if (ASIC_IS_DCE3(rdev)) {
754 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa);
755 if (ASIC_IS_DCE32(rdev))
756 tmp |= DC_HPDx_EN;
757
758 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
759 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
760 switch (radeon_connector->hpd.hpd) {
761 case RADEON_HPD_1:
762 WREG32(DC_HPD1_CONTROL, tmp);
763 rdev->irq.hpd[0] = true;
764 break;
765 case RADEON_HPD_2:
766 WREG32(DC_HPD2_CONTROL, tmp);
767 rdev->irq.hpd[1] = true;
768 break;
769 case RADEON_HPD_3:
770 WREG32(DC_HPD3_CONTROL, tmp);
771 rdev->irq.hpd[2] = true;
772 break;
773 case RADEON_HPD_4:
774 WREG32(DC_HPD4_CONTROL, tmp);
775 rdev->irq.hpd[3] = true;
776 break;
777 /* DCE 3.2 */
778 case RADEON_HPD_5:
779 WREG32(DC_HPD5_CONTROL, tmp);
780 rdev->irq.hpd[4] = true;
781 break;
782 case RADEON_HPD_6:
783 WREG32(DC_HPD6_CONTROL, tmp);
784 rdev->irq.hpd[5] = true;
785 break;
786 default:
787 break;
788 }
789 }
790 } else {
791 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
792 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
793 switch (radeon_connector->hpd.hpd) {
794 case RADEON_HPD_1:
795 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN);
796 rdev->irq.hpd[0] = true;
797 break;
798 case RADEON_HPD_2:
799 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN);
800 rdev->irq.hpd[1] = true;
801 break;
802 case RADEON_HPD_3:
803 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN);
804 rdev->irq.hpd[2] = true;
805 break;
806 default:
807 break;
808 }
809 }
810 }
003e69f9
JG		 811 if (rdev->irq.installed)
812 r600_irq_set(rdev);
e0df1ac5
AD		 813}
814
815void r600_hpd_fini(struct radeon_device *rdev)
816{
817 struct drm_device *dev = rdev->ddev;
818 struct drm_connector *connector;
819
820 if (ASIC_IS_DCE3(rdev)) {
821 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
822 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
823 switch (radeon_connector->hpd.hpd) {
824 case RADEON_HPD_1:
825 WREG32(DC_HPD1_CONTROL, 0);
826 rdev->irq.hpd[0] = false;
827 break;
828 case RADEON_HPD_2:
829 WREG32(DC_HPD2_CONTROL, 0);
830 rdev->irq.hpd[1] = false;
831 break;
832 case RADEON_HPD_3:
833 WREG32(DC_HPD3_CONTROL, 0);
834 rdev->irq.hpd[2] = false;
835 break;
836 case RADEON_HPD_4:
837 WREG32(DC_HPD4_CONTROL, 0);
838 rdev->irq.hpd[3] = false;
839 break;
840 /* DCE 3.2 */
841 case RADEON_HPD_5:
842 WREG32(DC_HPD5_CONTROL, 0);
843 rdev->irq.hpd[4] = false;
844 break;
845 case RADEON_HPD_6:
846 WREG32(DC_HPD6_CONTROL, 0);
847 rdev->irq.hpd[5] = false;
848 break;
849 default:
850 break;
851 }
852 }
853 } else {
854 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
855 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
856 switch (radeon_connector->hpd.hpd) {
857 case RADEON_HPD_1:
858 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0);
859 rdev->irq.hpd[0] = false;
860 break;
861 case RADEON_HPD_2:
862 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0);
863 rdev->irq.hpd[1] = false;
864 break;
865 case RADEON_HPD_3:
866 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0);
867 rdev->irq.hpd[2] = false;
868 break;
869 default:
870 break;
871 }
872 }
873 }
874}
875
771fe6b9 876/*
3ce0a23d 877 * R600 PCIE GART
771fe6b9 878 */
3ce0a23d
JG		 879void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
880{
881 unsigned i;
882 u32 tmp;
883
2e98f10a 884 /* flush hdp cache so updates hit vram */
f3886f85
AD		 885 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
886 !(rdev->flags & RADEON_IS_AGP)) {
812d0469
AD		 887 void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
888 u32 tmp;
889
890 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read
891 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL
f3886f85
AD		 892 * This seems to cause problems on some AGP cards. Just use the old
893 * method for them.
812d0469
AD		 894 */
895 WREG32(HDP_DEBUG1, 0);
896 tmp = readl((void __iomem *)ptr);
897 } else
898 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
2e98f10a 899
3ce0a23d
JG		 900 WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
901 WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
902 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
903 for (i = 0; i < rdev->usec_timeout; i++) {
904 /* read MC_STATUS */
905 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
906 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
907 if (tmp == 2) {
908 printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
909 return;
910 }
911 if (tmp) {
912 return;
913 }
914 udelay(1);
915 }
916}
917
4aac0473 918int r600_pcie_gart_init(struct radeon_device *rdev)
3ce0a23d 919{
4aac0473 920 int r;
3ce0a23d 921
4aac0473 922 if (rdev->gart.table.vram.robj) {
fce7d61b 923 WARN(1, "R600 PCIE GART already initialized\n");
4aac0473
JG		 924 return 0;
925 }
3ce0a23d
JG		 926 /* Initialize common gart structure */
927 r = radeon_gart_init(rdev);
4aac0473 928 if (r)
3ce0a23d 929 return r;
3ce0a23d 930 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
4aac0473
JG		 931 return radeon_gart_table_vram_alloc(rdev);
932}
933
934int r600_pcie_gart_enable(struct radeon_device *rdev)
935{
936 u32 tmp;
937 int r, i;
938
939 if (rdev->gart.table.vram.robj == NULL) {
940 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
941 return -EINVAL;
771fe6b9 942 }
4aac0473
JG		 943 r = radeon_gart_table_vram_pin(rdev);
944 if (r)
945 return r;
82568565 946 radeon_gart_restore(rdev);
bc1a631e 947
3ce0a23d
JG		 948 /* Setup L2 cache */
949 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
950 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
951 EFFECTIVE_L2_QUEUE_SIZE(7));
952 WREG32(VM_L2_CNTL2, 0);
953 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
954 /* Setup TLB control */
955 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
956 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
957 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
958 ENABLE_WAIT_L2_QUERY;
959 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
960 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
961 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
962 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
963 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
964 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
965 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
966 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
967 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
968 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
969 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
970 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
971 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
972 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
973 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
1a029b76 974 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
3ce0a23d
JG		 975 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
976 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
977 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
978 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
979 (u32)(rdev->dummy_page.addr >> 12));
980 for (i = 1; i < 7; i++)
981 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
771fe6b9 982
3ce0a23d
JG		 983 r600_pcie_gart_tlb_flush(rdev);
984 rdev->gart.ready = true;
771fe6b9
JG		 985 return 0;
986}
987
3ce0a23d 988void r600_pcie_gart_disable(struct radeon_device *rdev)
771fe6b9 989{
3ce0a23d 990 u32 tmp;
4c788679 991 int i, r;
771fe6b9 992
3ce0a23d
JG		 993 /* Disable all tables */
994 for (i = 0; i < 7; i++)
995 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
771fe6b9 996
3ce0a23d
JG		 997 /* Disable L2 cache */
998 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
999 EFFECTIVE_L2_QUEUE_SIZE(7));
1000 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
1001 /* Setup L1 TLB control */
1002 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
1003 ENABLE_WAIT_L2_QUERY;
1004 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
1005 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
1006 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
1007 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
1008 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
1009 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
1010 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
1011 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
1012 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp);
1013 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp);
1014 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
1015 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
1016 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
1017 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
4aac0473 1018 if (rdev->gart.table.vram.robj) {
4c788679
JG		 1019 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
1020 if (likely(r == 0)) {
1021 radeon_bo_kunmap(rdev->gart.table.vram.robj);
1022 radeon_bo_unpin(rdev->gart.table.vram.robj);
1023 radeon_bo_unreserve(rdev->gart.table.vram.robj);
1024 }
4aac0473
JG		 1025 }
1026}
1027
1028void r600_pcie_gart_fini(struct radeon_device *rdev)
1029{
f9274562 1030 radeon_gart_fini(rdev);
4aac0473
JG		 1031 r600_pcie_gart_disable(rdev);
1032 radeon_gart_table_vram_free(rdev);
771fe6b9
JG		 1033}
1034
1a029b76
JG		 1035void r600_agp_enable(struct radeon_device *rdev)
1036{
1037 u32 tmp;
1038 int i;
1039
1040 /* Setup L2 cache */
1041 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
1042 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1043 EFFECTIVE_L2_QUEUE_SIZE(7));
1044 WREG32(VM_L2_CNTL2, 0);
1045 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
1046 /* Setup TLB control */
1047 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1048 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1049 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
1050 ENABLE_WAIT_L2_QUERY;
1051 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
1052 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
1053 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
1054 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
1055 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
1056 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
1057 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
1058 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
1059 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
1060 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
1061 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
1062 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
1063 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1064 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1065 for (i = 0; i < 7; i++)
1066 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
1067}
1068
771fe6b9
JG		 1069int r600_mc_wait_for_idle(struct radeon_device *rdev)
1070{
3ce0a23d
JG		 1071 unsigned i;
1072 u32 tmp;
1073
1074 for (i = 0; i < rdev->usec_timeout; i++) {
1075 /* read MC_STATUS */
1076 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00;
1077 if (!tmp)
1078 return 0;
1079 udelay(1);
1080 }
1081 return -1;
771fe6b9
JG		 1082}
1083
a3c1945a 1084static void r600_mc_program(struct radeon_device *rdev)
771fe6b9 1085{
a3c1945a 1086 struct rv515_mc_save save;
3ce0a23d
JG		 1087 u32 tmp;
1088 int i, j;
771fe6b9 1089
3ce0a23d
JG		 1090 /* Initialize HDP */
1091 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1092 WREG32((0x2c14 + j), 0x00000000);
1093 WREG32((0x2c18 + j), 0x00000000);
1094 WREG32((0x2c1c + j), 0x00000000);
1095 WREG32((0x2c20 + j), 0x00000000);
1096 WREG32((0x2c24 + j), 0x00000000);
1097 }
1098 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
771fe6b9 1099
a3c1945a 1100 rv515_mc_stop(rdev, &save);
3ce0a23d 1101 if (r600_mc_wait_for_idle(rdev)) {
a3c1945a 1102 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
3ce0a23d 1103 }
a3c1945a 1104 /* Lockout access through VGA aperture (doesn't exist before R600) */
3ce0a23d 1105 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
3ce0a23d 1106 /* Update configuration */
1a029b76
JG		 1107 if (rdev->flags & RADEON_IS_AGP) {
1108 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1109 /* VRAM before AGP */
1110 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1111 rdev->mc.vram_start >> 12);
1112 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1113 rdev->mc.gtt_end >> 12);
1114 } else {
1115 /* VRAM after AGP */
1116 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1117 rdev->mc.gtt_start >> 12);
1118 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1119 rdev->mc.vram_end >> 12);
1120 }
1121 } else {
1122 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
1123 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12);
1124 }
3ce0a23d 1125 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
1a029b76 1126 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
3ce0a23d
JG		 1127 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1128 WREG32(MC_VM_FB_LOCATION, tmp);
1129 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1130 WREG32(HDP_NONSURFACE_INFO, (2 << 7));
46fcd2b3 1131 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
3ce0a23d 1132 if (rdev->flags & RADEON_IS_AGP) {
1a029b76
JG		 1133 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22);
1134 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22);
3ce0a23d
JG		 1135 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1136 } else {
1137 WREG32(MC_VM_AGP_BASE, 0);
1138 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1139 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1140 }
3ce0a23d 1141 if (r600_mc_wait_for_idle(rdev)) {
a3c1945a 1142 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
3ce0a23d 1143 }
a3c1945a 1144 rv515_mc_resume(rdev, &save);
698443d9
DA		 1145 /* we need to own VRAM, so turn off the VGA renderer here
1146 * to stop it overwriting our objects */
d39c3b89 1147 rv515_vga_render_disable(rdev);
3ce0a23d
JG		 1148}
1149
d594e46a
JG		 1150/**
1151 * r600_vram_gtt_location - try to find VRAM & GTT location
1152 * @rdev: radeon device structure holding all necessary informations
1153 * @mc: memory controller structure holding memory informations
1154 *
1155 * Function will place try to place VRAM at same place as in CPU (PCI)
1156 * address space as some GPU seems to have issue when we reprogram at
1157 * different address space.
1158 *
1159 * If there is not enough space to fit the unvisible VRAM after the
1160 * aperture then we limit the VRAM size to the aperture.
1161 *
1162 * If we are using AGP then place VRAM adjacent to AGP aperture are we need
1163 * them to be in one from GPU point of view so that we can program GPU to
1164 * catch access outside them (weird GPU policy see ??).
1165 *
1166 * This function will never fails, worst case are limiting VRAM or GTT.
1167 *
1168 * Note: GTT start, end, size should be initialized before calling this
1169 * function on AGP platform.
1170 */
0ef0c1f7 1171static void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
d594e46a
JG		 1172{
1173 u64 size_bf, size_af;
1174
1175 if (mc->mc_vram_size > 0xE0000000) {
1176 /* leave room for at least 512M GTT */
1177 dev_warn(rdev->dev, "limiting VRAM\n");
1178 mc->real_vram_size = 0xE0000000;
1179 mc->mc_vram_size = 0xE0000000;
1180 }
1181 if (rdev->flags & RADEON_IS_AGP) {
1182 size_bf = mc->gtt_start;
1183 size_af = 0xFFFFFFFF - mc->gtt_end + 1;
1184 if (size_bf > size_af) {
1185 if (mc->mc_vram_size > size_bf) {
1186 dev_warn(rdev->dev, "limiting VRAM\n");
1187 mc->real_vram_size = size_bf;
1188 mc->mc_vram_size = size_bf;
1189 }
1190 mc->vram_start = mc->gtt_start - mc->mc_vram_size;
1191 } else {
1192 if (mc->mc_vram_size > size_af) {
1193 dev_warn(rdev->dev, "limiting VRAM\n");
1194 mc->real_vram_size = size_af;
1195 mc->mc_vram_size = size_af;
1196 }
1197 mc->vram_start = mc->gtt_end;
1198 }
1199 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
1200 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
1201 mc->mc_vram_size >> 20, mc->vram_start,
1202 mc->vram_end, mc->real_vram_size >> 20);
1203 } else {
1204 u64 base = 0;
8961d52d
AD		 1205 if (rdev->flags & RADEON_IS_IGP) {
1206 base = RREG32(MC_VM_FB_LOCATION) & 0xFFFF;
1207 base <<= 24;
1208 }
d594e46a 1209 radeon_vram_location(rdev, &rdev->mc, base);
8d369bb1 1210 rdev->mc.gtt_base_align = 0;
d594e46a
JG		 1211 radeon_gtt_location(rdev, mc);
1212 }
1213}
1214
3ce0a23d 1215int r600_mc_init(struct radeon_device *rdev)
771fe6b9 1216{
3ce0a23d 1217 u32 tmp;
5885b7a9 1218 int chansize, numchan;
771fe6b9 1219
3ce0a23d 1220 /* Get VRAM informations */
771fe6b9 1221 rdev->mc.vram_is_ddr = true;
3ce0a23d
JG		 1222 tmp = RREG32(RAMCFG);
1223 if (tmp & CHANSIZE_OVERRIDE) {
771fe6b9 1224 chansize = 16;
3ce0a23d 1225 } else if (tmp & CHANSIZE_MASK) {
771fe6b9
JG		 1226 chansize = 64;
1227 } else {
1228 chansize = 32;
1229 }
5885b7a9
AD		 1230 tmp = RREG32(CHMAP);
1231 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1232 case 0:
1233 default:
1234 numchan = 1;
1235 break;
1236 case 1:
1237 numchan = 2;
1238 break;
1239 case 2:
1240 numchan = 4;
1241 break;
1242 case 3:
1243 numchan = 8;
1244 break;
771fe6b9 1245 }
5885b7a9 1246 rdev->mc.vram_width = numchan * chansize;
3ce0a23d 1247 /* Could aper size report 0 ? */
01d73a69
JC		 1248 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
1249 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
3ce0a23d
JG		 1250 /* Setup GPU memory space */
1251 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
1252 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
51e5fcd3 1253 rdev->mc.visible_vram_size = rdev->mc.aper_size;
c919b371 1254 rdev->mc.active_vram_size = rdev->mc.visible_vram_size;
d594e46a 1255 r600_vram_gtt_location(rdev, &rdev->mc);
f47299c5 1256
f892034a
AD		 1257 if (rdev->flags & RADEON_IS_IGP) {
1258 rs690_pm_info(rdev);
06b6476d 1259 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
f892034a 1260 }
f47299c5 1261 radeon_update_bandwidth_info(rdev);
3ce0a23d 1262 return 0;
771fe6b9
JG		 1263}
1264
3ce0a23d
JG		 1265/* We doesn't check that the GPU really needs a reset we simply do the
1266 * reset, it's up to the caller to determine if the GPU needs one. We
1267 * might add an helper function to check that.
1268 */
1269int r600_gpu_soft_reset(struct radeon_device *rdev)
771fe6b9 1270{
a3c1945a 1271 struct rv515_mc_save save;
3ce0a23d
JG		 1272 u32 grbm_busy_mask = S_008010_VC_BUSY(1) | S_008010_VGT_BUSY_NO_DMA(1) |
1273 S_008010_VGT_BUSY(1) | S_008010_TA03_BUSY(1) |
1274 S_008010_TC_BUSY(1) | S_008010_SX_BUSY(1) |
1275 S_008010_SH_BUSY(1) | S_008010_SPI03_BUSY(1) |
1276 S_008010_SMX_BUSY(1) | S_008010_SC_BUSY(1) |
1277 S_008010_PA_BUSY(1) | S_008010_DB03_BUSY(1) |
1278 S_008010_CR_BUSY(1) | S_008010_CB03_BUSY(1) |
1279 S_008010_GUI_ACTIVE(1);
1280 u32 grbm2_busy_mask = S_008014_SPI0_BUSY(1) | S_008014_SPI1_BUSY(1) |
1281 S_008014_SPI2_BUSY(1) | S_008014_SPI3_BUSY(1) |
1282 S_008014_TA0_BUSY(1) | S_008014_TA1_BUSY(1) |
1283 S_008014_TA2_BUSY(1) | S_008014_TA3_BUSY(1) |
1284 S_008014_DB0_BUSY(1) | S_008014_DB1_BUSY(1) |
1285 S_008014_DB2_BUSY(1) | S_008014_DB3_BUSY(1) |
1286 S_008014_CB0_BUSY(1) | S_008014_CB1_BUSY(1) |
1287 S_008014_CB2_BUSY(1) | S_008014_CB3_BUSY(1);
a3c1945a 1288 u32 tmp;
771fe6b9 1289
8d96fe93
AD		 1290 if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
1291 return 0;
1292
1a029b76
JG		 1293 dev_info(rdev->dev, "GPU softreset \n");
1294 dev_info(rdev->dev, " R_008010_GRBM_STATUS=0x%08X\n",
1295 RREG32(R_008010_GRBM_STATUS));
1296 dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n",
a3c1945a 1297 RREG32(R_008014_GRBM_STATUS2));
1a029b76
JG		 1298 dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n",
1299 RREG32(R_000E50_SRBM_STATUS));
a3c1945a
JG		 1300 rv515_mc_stop(rdev, &save);
1301 if (r600_mc_wait_for_idle(rdev)) {
1302 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1303 }
3ce0a23d 1304 /* Disable CP parsing/prefetching */
90aca4d2 1305 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
3ce0a23d
JG		 1306 /* Check if any of the rendering block is busy and reset it */
1307 if ((RREG32(R_008010_GRBM_STATUS) & grbm_busy_mask) ||
1308 (RREG32(R_008014_GRBM_STATUS2) & grbm2_busy_mask)) {
a3c1945a 1309 tmp = S_008020_SOFT_RESET_CR(1) |
3ce0a23d
JG		 1310 S_008020_SOFT_RESET_DB(1) |
1311 S_008020_SOFT_RESET_CB(1) |
1312 S_008020_SOFT_RESET_PA(1) |
1313 S_008020_SOFT_RESET_SC(1) |
1314 S_008020_SOFT_RESET_SMX(1) |
1315 S_008020_SOFT_RESET_SPI(1) |
1316 S_008020_SOFT_RESET_SX(1) |
1317 S_008020_SOFT_RESET_SH(1) |
1318 S_008020_SOFT_RESET_TC(1) |
1319 S_008020_SOFT_RESET_TA(1) |
1320 S_008020_SOFT_RESET_VC(1) |
a3c1945a 1321 S_008020_SOFT_RESET_VGT(1);
1a029b76 1322 dev_info(rdev->dev, " R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
a3c1945a 1323 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
90aca4d2
JG		 1324 RREG32(R_008020_GRBM_SOFT_RESET);
1325 mdelay(15);
3ce0a23d 1326 WREG32(R_008020_GRBM_SOFT_RESET, 0);
3ce0a23d
JG		 1327 }
1328 /* Reset CP (we always reset CP) */
a3c1945a
JG		 1329 tmp = S_008020_SOFT_RESET_CP(1);
1330 dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
1331 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
90aca4d2
JG		 1332 RREG32(R_008020_GRBM_SOFT_RESET);
1333 mdelay(15);
3ce0a23d 1334 WREG32(R_008020_GRBM_SOFT_RESET, 0);
3ce0a23d 1335 /* Wait a little for things to settle down */
225758d8 1336 mdelay(1);
1a029b76
JG		 1337 dev_info(rdev->dev, " R_008010_GRBM_STATUS=0x%08X\n",
1338 RREG32(R_008010_GRBM_STATUS));
1339 dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n",
1340 RREG32(R_008014_GRBM_STATUS2));
1341 dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n",
1342 RREG32(R_000E50_SRBM_STATUS));
a3c1945a 1343 rv515_mc_resume(rdev, &save);
3ce0a23d
JG		 1344 return 0;
1345}
1346
225758d8
JG		 1347bool r600_gpu_is_lockup(struct radeon_device *rdev)
1348{
1349 u32 srbm_status;
1350 u32 grbm_status;
1351 u32 grbm_status2;
e29ff729 1352 struct r100_gpu_lockup *lockup;
225758d8
JG		 1353 int r;
1354
e29ff729
AD		 1355 if (rdev->family >= CHIP_RV770)
1356 lockup = &rdev->config.rv770.lockup;
1357 else
1358 lockup = &rdev->config.r600.lockup;
1359
225758d8
JG		 1360 srbm_status = RREG32(R_000E50_SRBM_STATUS);
1361 grbm_status = RREG32(R_008010_GRBM_STATUS);
1362 grbm_status2 = RREG32(R_008014_GRBM_STATUS2);
1363 if (!G_008010_GUI_ACTIVE(grbm_status)) {
e29ff729 1364 r100_gpu_lockup_update(lockup, &rdev->cp);
225758d8
JG		 1365 return false;
1366 }
1367 /* force CP activities */
1368 r = radeon_ring_lock(rdev, 2);
1369 if (!r) {
1370 /* PACKET2 NOP */
1371 radeon_ring_write(rdev, 0x80000000);
1372 radeon_ring_write(rdev, 0x80000000);
1373 radeon_ring_unlock_commit(rdev);
1374 }
1375 rdev->cp.rptr = RREG32(R600_CP_RB_RPTR);
e29ff729 1376 return r100_gpu_cp_is_lockup(rdev, lockup, &rdev->cp);
225758d8
JG		 1377}
1378
a2d07b74 1379int r600_asic_reset(struct radeon_device *rdev)
3ce0a23d
JG		 1380{
1381 return r600_gpu_soft_reset(rdev);
1382}
1383
1384static u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
1385 u32 num_backends,
1386 u32 backend_disable_mask)
1387{
1388 u32 backend_map = 0;
1389 u32 enabled_backends_mask;
1390 u32 enabled_backends_count;
1391 u32 cur_pipe;
1392 u32 swizzle_pipe[R6XX_MAX_PIPES];
1393 u32 cur_backend;
1394 u32 i;
1395
1396 if (num_tile_pipes > R6XX_MAX_PIPES)
1397 num_tile_pipes = R6XX_MAX_PIPES;
1398 if (num_tile_pipes < 1)
1399 num_tile_pipes = 1;
1400 if (num_backends > R6XX_MAX_BACKENDS)
1401 num_backends = R6XX_MAX_BACKENDS;
1402 if (num_backends < 1)
1403 num_backends = 1;
1404
1405 enabled_backends_mask = 0;
1406 enabled_backends_count = 0;
1407 for (i = 0; i < R6XX_MAX_BACKENDS; ++i) {
1408 if (((backend_disable_mask >> i) & 1) == 0) {
1409 enabled_backends_mask |= (1 << i);
1410 ++enabled_backends_count;
1411 }
1412 if (enabled_backends_count == num_backends)
1413 break;
1414 }
1415
1416 if (enabled_backends_count == 0) {
1417 enabled_backends_mask = 1;
1418 enabled_backends_count = 1;
1419 }
1420
1421 if (enabled_backends_count != num_backends)
1422 num_backends = enabled_backends_count;
1423
1424 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES);
1425 switch (num_tile_pipes) {
1426 case 1:
1427 swizzle_pipe[0] = 0;
1428 break;
1429 case 2:
1430 swizzle_pipe[0] = 0;
1431 swizzle_pipe[1] = 1;
1432 break;
1433 case 3:
1434 swizzle_pipe[0] = 0;
1435 swizzle_pipe[1] = 1;
1436 swizzle_pipe[2] = 2;
1437 break;
1438 case 4:
1439 swizzle_pipe[0] = 0;
1440 swizzle_pipe[1] = 1;
1441 swizzle_pipe[2] = 2;
1442 swizzle_pipe[3] = 3;
1443 break;
1444 case 5:
1445 swizzle_pipe[0] = 0;
1446 swizzle_pipe[1] = 1;
1447 swizzle_pipe[2] = 2;
1448 swizzle_pipe[3] = 3;
1449 swizzle_pipe[4] = 4;
1450 break;
1451 case 6:
1452 swizzle_pipe[0] = 0;
1453 swizzle_pipe[1] = 2;
1454 swizzle_pipe[2] = 4;
1455 swizzle_pipe[3] = 5;
1456 swizzle_pipe[4] = 1;
1457 swizzle_pipe[5] = 3;
1458 break;
1459 case 7:
1460 swizzle_pipe[0] = 0;
1461 swizzle_pipe[1] = 2;
1462 swizzle_pipe[2] = 4;
1463 swizzle_pipe[3] = 6;
1464 swizzle_pipe[4] = 1;
1465 swizzle_pipe[5] = 3;
1466 swizzle_pipe[6] = 5;
1467 break;
1468 case 8:
1469 swizzle_pipe[0] = 0;
1470 swizzle_pipe[1] = 2;
1471 swizzle_pipe[2] = 4;
1472 swizzle_pipe[3] = 6;
1473 swizzle_pipe[4] = 1;
1474 swizzle_pipe[5] = 3;
1475 swizzle_pipe[6] = 5;
1476 swizzle_pipe[7] = 7;
1477 break;
1478 }
1479
1480 cur_backend = 0;
1481 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
1482 while (((1 << cur_backend) & enabled_backends_mask) == 0)
1483 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
1484
1485 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
1486
1487 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
1488 }
1489
1490 return backend_map;
1491}
1492
1493int r600_count_pipe_bits(uint32_t val)
1494{
1495 int i, ret = 0;
1496
1497 for (i = 0; i < 32; i++) {
1498 ret += val & 1;
1499 val >>= 1;
1500 }
1501 return ret;
771fe6b9
JG		 1502}
1503
3ce0a23d
JG		 1504void r600_gpu_init(struct radeon_device *rdev)
1505{
1506 u32 tiling_config;
1507 u32 ramcfg;
d03f5d59
AD		 1508 u32 backend_map;
1509 u32 cc_rb_backend_disable;
1510 u32 cc_gc_shader_pipe_config;
3ce0a23d
JG		 1511 u32 tmp;
1512 int i, j;
1513 u32 sq_config;
1514 u32 sq_gpr_resource_mgmt_1 = 0;
1515 u32 sq_gpr_resource_mgmt_2 = 0;
1516 u32 sq_thread_resource_mgmt = 0;
1517 u32 sq_stack_resource_mgmt_1 = 0;
1518 u32 sq_stack_resource_mgmt_2 = 0;
1519
1520 /* FIXME: implement */
1521 switch (rdev->family) {
1522 case CHIP_R600:
1523 rdev->config.r600.max_pipes = 4;
1524 rdev->config.r600.max_tile_pipes = 8;
1525 rdev->config.r600.max_simds = 4;
1526 rdev->config.r600.max_backends = 4;
1527 rdev->config.r600.max_gprs = 256;
1528 rdev->config.r600.max_threads = 192;
1529 rdev->config.r600.max_stack_entries = 256;
1530 rdev->config.r600.max_hw_contexts = 8;
1531 rdev->config.r600.max_gs_threads = 16;
1532 rdev->config.r600.sx_max_export_size = 128;
1533 rdev->config.r600.sx_max_export_pos_size = 16;
1534 rdev->config.r600.sx_max_export_smx_size = 128;
1535 rdev->config.r600.sq_num_cf_insts = 2;
1536 break;
1537 case CHIP_RV630:
1538 case CHIP_RV635:
1539 rdev->config.r600.max_pipes = 2;
1540 rdev->config.r600.max_tile_pipes = 2;
1541 rdev->config.r600.max_simds = 3;
1542 rdev->config.r600.max_backends = 1;
1543 rdev->config.r600.max_gprs = 128;
1544 rdev->config.r600.max_threads = 192;
1545 rdev->config.r600.max_stack_entries = 128;
1546 rdev->config.r600.max_hw_contexts = 8;
1547 rdev->config.r600.max_gs_threads = 4;
1548 rdev->config.r600.sx_max_export_size = 128;
1549 rdev->config.r600.sx_max_export_pos_size = 16;
1550 rdev->config.r600.sx_max_export_smx_size = 128;
1551 rdev->config.r600.sq_num_cf_insts = 2;
1552 break;
1553 case CHIP_RV610:
1554 case CHIP_RV620:
1555 case CHIP_RS780:
1556 case CHIP_RS880:
1557 rdev->config.r600.max_pipes = 1;
1558 rdev->config.r600.max_tile_pipes = 1;
1559 rdev->config.r600.max_simds = 2;
1560 rdev->config.r600.max_backends = 1;
1561 rdev->config.r600.max_gprs = 128;
1562 rdev->config.r600.max_threads = 192;
1563 rdev->config.r600.max_stack_entries = 128;
1564 rdev->config.r600.max_hw_contexts = 4;
1565 rdev->config.r600.max_gs_threads = 4;
1566 rdev->config.r600.sx_max_export_size = 128;
1567 rdev->config.r600.sx_max_export_pos_size = 16;
1568 rdev->config.r600.sx_max_export_smx_size = 128;
1569 rdev->config.r600.sq_num_cf_insts = 1;
1570 break;
1571 case CHIP_RV670:
1572 rdev->config.r600.max_pipes = 4;
1573 rdev->config.r600.max_tile_pipes = 4;
1574 rdev->config.r600.max_simds = 4;
1575 rdev->config.r600.max_backends = 4;
1576 rdev->config.r600.max_gprs = 192;
1577 rdev->config.r600.max_threads = 192;
1578 rdev->config.r600.max_stack_entries = 256;
1579 rdev->config.r600.max_hw_contexts = 8;
1580 rdev->config.r600.max_gs_threads = 16;
1581 rdev->config.r600.sx_max_export_size = 128;
1582 rdev->config.r600.sx_max_export_pos_size = 16;
1583 rdev->config.r600.sx_max_export_smx_size = 128;
1584 rdev->config.r600.sq_num_cf_insts = 2;
1585 break;
1586 default:
1587 break;
1588 }
1589
1590 /* Initialize HDP */
1591 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1592 WREG32((0x2c14 + j), 0x00000000);
1593 WREG32((0x2c18 + j), 0x00000000);
1594 WREG32((0x2c1c + j), 0x00000000);
1595 WREG32((0x2c20 + j), 0x00000000);
1596 WREG32((0x2c24 + j), 0x00000000);
1597 }
1598
1599 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1600
1601 /* Setup tiling */
1602 tiling_config = 0;
1603 ramcfg = RREG32(RAMCFG);
1604 switch (rdev->config.r600.max_tile_pipes) {
1605 case 1:
1606 tiling_config |= PIPE_TILING(0);
1607 break;
1608 case 2:
1609 tiling_config |= PIPE_TILING(1);
1610 break;
1611 case 4:
1612 tiling_config |= PIPE_TILING(2);
1613 break;
1614 case 8:
1615 tiling_config |= PIPE_TILING(3);
1616 break;
1617 default:
1618 break;
1619 }
d03f5d59 1620 rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes;
961fb597 1621 rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
3ce0a23d 1622 tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
881fe6c1
AD		 1623 tiling_config |= GROUP_SIZE((ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
1624 if ((ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT)
1625 rdev->config.r600.tiling_group_size = 512;
1626 else
1627 rdev->config.r600.tiling_group_size = 256;
3ce0a23d
JG		 1628 tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
1629 if (tmp > 3) {
1630 tiling_config |= ROW_TILING(3);
1631 tiling_config |= SAMPLE_SPLIT(3);
1632 } else {
1633 tiling_config |= ROW_TILING(tmp);
1634 tiling_config |= SAMPLE_SPLIT(tmp);
1635 }
1636 tiling_config |= BANK_SWAPS(1);
d03f5d59
AD		 1637
1638 cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000;
1639 cc_rb_backend_disable |=
1640 BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << rdev->config.r600.max_backends) & R6XX_MAX_BACKENDS_MASK);
1641
1642 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00;
1643 cc_gc_shader_pipe_config |=
1644 INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << rdev->config.r600.max_pipes) & R6XX_MAX_PIPES_MASK);
1645 cc_gc_shader_pipe_config |=
1646 INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << rdev->config.r600.max_simds) & R6XX_MAX_SIMDS_MASK);
1647
1648 backend_map = r600_get_tile_pipe_to_backend_map(rdev->config.r600.max_tile_pipes,
1649 (R6XX_MAX_BACKENDS -
1650 r600_count_pipe_bits((cc_rb_backend_disable &
1651 R6XX_MAX_BACKENDS_MASK) >> 16)),
1652 (cc_rb_backend_disable >> 16));
e7aeeba6 1653 rdev->config.r600.tile_config = tiling_config;
d03f5d59 1654 tiling_config |= BACKEND_MAP(backend_map);
3ce0a23d
JG		 1655 WREG32(GB_TILING_CONFIG, tiling_config);
1656 WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff);
1657 WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff);
1658
3ce0a23d 1659 /* Setup pipes */
d03f5d59
AD		 1660 WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
1661 WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
f867c60d 1662 WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
3ce0a23d 1663
d03f5d59 1664 tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
3ce0a23d
JG		 1665 WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);
1666 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK);
1667
1668 /* Setup some CP states */
1669 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b)));
1670 WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40)));
1671
1672 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT |
1673 SYNC_WALKER | SYNC_ALIGNER));
1674 /* Setup various GPU states */
1675 if (rdev->family == CHIP_RV670)
1676 WREG32(ARB_GDEC_RD_CNTL, 0x00000021);
1677
1678 tmp = RREG32(SX_DEBUG_1);
1679 tmp |= SMX_EVENT_RELEASE;
1680 if ((rdev->family > CHIP_R600))
1681 tmp |= ENABLE_NEW_SMX_ADDRESS;
1682 WREG32(SX_DEBUG_1, tmp);
1683
1684 if (((rdev->family) == CHIP_R600) ||
1685 ((rdev->family) == CHIP_RV630) ||
1686 ((rdev->family) == CHIP_RV610) ||
1687 ((rdev->family) == CHIP_RV620) ||
ee59f2b4
AD		 1688 ((rdev->family) == CHIP_RS780) ||
1689 ((rdev->family) == CHIP_RS880)) {
3ce0a23d
JG		 1690 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE);
1691 } else {
1692 WREG32(DB_DEBUG, 0);
1693 }
1694 WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) |
1695 DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4)));
1696
1697 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1698 WREG32(VGT_NUM_INSTANCES, 0);
1699
1700 WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
1701 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0));
1702
1703 tmp = RREG32(SQ_MS_FIFO_SIZES);
1704 if (((rdev->family) == CHIP_RV610) ||
1705 ((rdev->family) == CHIP_RV620) ||
ee59f2b4
AD		 1706 ((rdev->family) == CHIP_RS780) ||
1707 ((rdev->family) == CHIP_RS880)) {
3ce0a23d
JG		 1708 tmp = (CACHE_FIFO_SIZE(0xa) |
1709 FETCH_FIFO_HIWATER(0xa) |
1710 DONE_FIFO_HIWATER(0xe0) |
1711 ALU_UPDATE_FIFO_HIWATER(0x8));
1712 } else if (((rdev->family) == CHIP_R600) ||
1713 ((rdev->family) == CHIP_RV630)) {
1714 tmp &= ~DONE_FIFO_HIWATER(0xff);
1715 tmp |= DONE_FIFO_HIWATER(0x4);
1716 }
1717 WREG32(SQ_MS_FIFO_SIZES, tmp);
1718
1719 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
1720 * should be adjusted as needed by the 2D/3D drivers. This just sets default values
1721 */
1722 sq_config = RREG32(SQ_CONFIG);
1723 sq_config &= ~(PS_PRIO(3) |
1724 VS_PRIO(3) |
1725 GS_PRIO(3) |
1726 ES_PRIO(3));
1727 sq_config |= (DX9_CONSTS |
1728 VC_ENABLE |
1729 PS_PRIO(0) |
1730 VS_PRIO(1) |
1731 GS_PRIO(2) |
1732 ES_PRIO(3));
1733
1734 if ((rdev->family) == CHIP_R600) {
1735 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) |
1736 NUM_VS_GPRS(124) |
1737 NUM_CLAUSE_TEMP_GPRS(4));
1738 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) |
1739 NUM_ES_GPRS(0));
1740 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) |
1741 NUM_VS_THREADS(48) |
1742 NUM_GS_THREADS(4) |
1743 NUM_ES_THREADS(4));
1744 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) |
1745 NUM_VS_STACK_ENTRIES(128));
1746 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) |
1747 NUM_ES_STACK_ENTRIES(0));
1748 } else if (((rdev->family) == CHIP_RV610) ||
1749 ((rdev->family) == CHIP_RV620) ||
ee59f2b4
AD		 1750 ((rdev->family) == CHIP_RS780) ||
1751 ((rdev->family) == CHIP_RS880)) {
3ce0a23d
JG		 1752 /* no vertex cache */
1753 sq_config &= ~VC_ENABLE;
1754
1755 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1756 NUM_VS_GPRS(44) |
1757 NUM_CLAUSE_TEMP_GPRS(2));
1758 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1759 NUM_ES_GPRS(17));
1760 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1761 NUM_VS_THREADS(78) |
1762 NUM_GS_THREADS(4) |
1763 NUM_ES_THREADS(31));
1764 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1765 NUM_VS_STACK_ENTRIES(40));
1766 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1767 NUM_ES_STACK_ENTRIES(16));
1768 } else if (((rdev->family) == CHIP_RV630) ||
1769 ((rdev->family) == CHIP_RV635)) {
1770 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1771 NUM_VS_GPRS(44) |
1772 NUM_CLAUSE_TEMP_GPRS(2));
1773 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) |
1774 NUM_ES_GPRS(18));
1775 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1776 NUM_VS_THREADS(78) |
1777 NUM_GS_THREADS(4) |
1778 NUM_ES_THREADS(31));
1779 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1780 NUM_VS_STACK_ENTRIES(40));
1781 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1782 NUM_ES_STACK_ENTRIES(16));
1783 } else if ((rdev->family) == CHIP_RV670) {
1784 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1785 NUM_VS_GPRS(44) |
1786 NUM_CLAUSE_TEMP_GPRS(2));
1787 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1788 NUM_ES_GPRS(17));
1789 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1790 NUM_VS_THREADS(78) |
1791 NUM_GS_THREADS(4) |
1792 NUM_ES_THREADS(31));
1793 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) |
1794 NUM_VS_STACK_ENTRIES(64));
1795 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) |
1796 NUM_ES_STACK_ENTRIES(64));
1797 }
1798
1799 WREG32(SQ_CONFIG, sq_config);
1800 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
1801 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
1802 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1803 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
1804 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
1805
1806 if (((rdev->family) == CHIP_RV610) ||
1807 ((rdev->family) == CHIP_RV620) ||
ee59f2b4
AD		 1808 ((rdev->family) == CHIP_RS780) ||
1809 ((rdev->family) == CHIP_RS880)) {
3ce0a23d
JG		 1810 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY));
1811 } else {
1812 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC));
1813 }
1814
1815 /* More default values. 2D/3D driver should adjust as needed */
1816 WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) |
1817 S1_X(0x4) | S1_Y(0xc)));
1818 WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) |
1819 S1_X(0x2) | S1_Y(0x2) |
1820 S2_X(0xa) | S2_Y(0x6) |
1821 S3_X(0x6) | S3_Y(0xa)));
1822 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) |
1823 S1_X(0x4) | S1_Y(0xc) |
1824 S2_X(0x1) | S2_Y(0x6) |
1825 S3_X(0xa) | S3_Y(0xe)));
1826 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) |
1827 S5_X(0x0) | S5_Y(0x0) |
1828 S6_X(0xb) | S6_Y(0x4) |
1829 S7_X(0x7) | S7_Y(0x8)));
1830
1831 WREG32(VGT_STRMOUT_EN, 0);
1832 tmp = rdev->config.r600.max_pipes * 16;
1833 switch (rdev->family) {
1834 case CHIP_RV610:
3ce0a23d 1835 case CHIP_RV620:
ee59f2b4
AD		 1836 case CHIP_RS780:
1837 case CHIP_RS880:
3ce0a23d
JG		 1838 tmp += 32;
1839 break;
1840 case CHIP_RV670:
1841 tmp += 128;
1842 break;
1843 default:
1844 break;
1845 }
1846 if (tmp > 256) {
1847 tmp = 256;
1848 }
1849 WREG32(VGT_ES_PER_GS, 128);
1850 WREG32(VGT_GS_PER_ES, tmp);
1851 WREG32(VGT_GS_PER_VS, 2);
1852 WREG32(VGT_GS_VERTEX_REUSE, 16);
1853
1854 /* more default values. 2D/3D driver should adjust as needed */
1855 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1856 WREG32(VGT_STRMOUT_EN, 0);
1857 WREG32(SX_MISC, 0);
1858 WREG32(PA_SC_MODE_CNTL, 0);
1859 WREG32(PA_SC_AA_CONFIG, 0);
1860 WREG32(PA_SC_LINE_STIPPLE, 0);
1861 WREG32(SPI_INPUT_Z, 0);
1862 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
1863 WREG32(CB_COLOR7_FRAG, 0);
1864
1865 /* Clear render buffer base addresses */
1866 WREG32(CB_COLOR0_BASE, 0);
1867 WREG32(CB_COLOR1_BASE, 0);
1868 WREG32(CB_COLOR2_BASE, 0);
1869 WREG32(CB_COLOR3_BASE, 0);
1870 WREG32(CB_COLOR4_BASE, 0);
1871 WREG32(CB_COLOR5_BASE, 0);
1872 WREG32(CB_COLOR6_BASE, 0);
1873 WREG32(CB_COLOR7_BASE, 0);
1874 WREG32(CB_COLOR7_FRAG, 0);
1875
1876 switch (rdev->family) {
1877 case CHIP_RV610:
3ce0a23d 1878 case CHIP_RV620:
ee59f2b4
AD		 1879 case CHIP_RS780:
1880 case CHIP_RS880:
3ce0a23d
JG		 1881 tmp = TC_L2_SIZE(8);
1882 break;
1883 case CHIP_RV630:
1884 case CHIP_RV635:
1885 tmp = TC_L2_SIZE(4);
1886 break;
1887 case CHIP_R600:
1888 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT;
1889 break;
1890 default:
1891 tmp = TC_L2_SIZE(0);
1892 break;
1893 }
1894 WREG32(TC_CNTL, tmp);
1895
1896 tmp = RREG32(HDP_HOST_PATH_CNTL);
1897 WREG32(HDP_HOST_PATH_CNTL, tmp);
1898
1899 tmp = RREG32(ARB_POP);
1900 tmp |= ENABLE_TC128;
1901 WREG32(ARB_POP, tmp);
1902
1903 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1904 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
1905 NUM_CLIP_SEQ(3)));
1906 WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));
1907}
1908
1909
771fe6b9
JG		 1910/*
1911 * Indirect registers accessor
1912 */
3ce0a23d
JG		 1913u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg)
1914{
1915 u32 r;
1916
1917 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1918 (void)RREG32(PCIE_PORT_INDEX);
1919 r = RREG32(PCIE_PORT_DATA);
1920 return r;
1921}
1922
1923void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
1924{
1925 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1926 (void)RREG32(PCIE_PORT_INDEX);
1927 WREG32(PCIE_PORT_DATA, (v));
1928 (void)RREG32(PCIE_PORT_DATA);
1929}
1930
3ce0a23d
JG		 1931/*
1932 * CP & Ring
1933 */
1934void r600_cp_stop(struct radeon_device *rdev)
1935{
c919b371 1936 rdev->mc.active_vram_size = rdev->mc.visible_vram_size;
3ce0a23d 1937 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
724c80e1 1938 WREG32(SCRATCH_UMSK, 0);
3ce0a23d
JG		 1939}
1940
d8f60cfc 1941int r600_init_microcode(struct radeon_device *rdev)
3ce0a23d
JG		 1942{
1943 struct platform_device *pdev;
1944 const char *chip_name;
d8f60cfc
AD		 1945 const char *rlc_chip_name;
1946 size_t pfp_req_size, me_req_size, rlc_req_size;
3ce0a23d
JG		 1947 char fw_name[30];
1948 int err;
1949
1950 DRM_DEBUG("\n");
1951
1952 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
1953 err = IS_ERR(pdev);
1954 if (err) {
1955 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
1956 return -EINVAL;
1957 }
1958
1959 switch (rdev->family) {
d8f60cfc
AD		 1960 case CHIP_R600:
1961 chip_name = "R600";
1962 rlc_chip_name = "R600";
1963 break;
1964 case CHIP_RV610:
1965 chip_name = "RV610";
1966 rlc_chip_name = "R600";
1967 break;
1968 case CHIP_RV630:
1969 chip_name = "RV630";
1970 rlc_chip_name = "R600";
1971 break;
1972 case CHIP_RV620:
1973 chip_name = "RV620";
1974 rlc_chip_name = "R600";
1975 break;
1976 case CHIP_RV635:
1977 chip_name = "RV635";
1978 rlc_chip_name = "R600";
1979 break;
1980 case CHIP_RV670:
1981 chip_name = "RV670";
1982 rlc_chip_name = "R600";
1983 break;
3ce0a23d 1984 case CHIP_RS780:
d8f60cfc
AD		 1985 case CHIP_RS880:
1986 chip_name = "RS780";
1987 rlc_chip_name = "R600";
1988 break;
1989 case CHIP_RV770:
1990 chip_name = "RV770";
1991 rlc_chip_name = "R700";
1992 break;
3ce0a23d 1993 case CHIP_RV730:
d8f60cfc
AD		 1994 case CHIP_RV740:
1995 chip_name = "RV730";
1996 rlc_chip_name = "R700";
1997 break;
1998 case CHIP_RV710:
1999 chip_name = "RV710";
2000 rlc_chip_name = "R700";
2001 break;
fe251e2f
AD		 2002 case CHIP_CEDAR:
2003 chip_name = "CEDAR";
45f9a39b 2004 rlc_chip_name = "CEDAR";
fe251e2f
AD		 2005 break;
2006 case CHIP_REDWOOD:
2007 chip_name = "REDWOOD";
45f9a39b 2008 rlc_chip_name = "REDWOOD";
fe251e2f
AD		 2009 break;
2010 case CHIP_JUNIPER:
2011 chip_name = "JUNIPER";
45f9a39b 2012 rlc_chip_name = "JUNIPER";
fe251e2f
AD		 2013 break;
2014 case CHIP_CYPRESS:
2015 case CHIP_HEMLOCK:
2016 chip_name = "CYPRESS";
45f9a39b 2017 rlc_chip_name = "CYPRESS";
fe251e2f 2018 break;
439bd6cd
AD		 2019 case CHIP_PALM:
2020 chip_name = "PALM";
2021 rlc_chip_name = "SUMO";
2022 break;
3ce0a23d
JG		 2023 default: BUG();
2024 }
2025
fe251e2f
AD		 2026 if (rdev->family >= CHIP_CEDAR) {
2027 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
2028 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
45f9a39b 2029 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
fe251e2f 2030 } else if (rdev->family >= CHIP_RV770) {
3ce0a23d
JG		 2031 pfp_req_size = R700_PFP_UCODE_SIZE * 4;
2032 me_req_size = R700_PM4_UCODE_SIZE * 4;
d8f60cfc 2033 rlc_req_size = R700_RLC_UCODE_SIZE * 4;
3ce0a23d
JG		 2034 } else {
2035 pfp_req_size = PFP_UCODE_SIZE * 4;
2036 me_req_size = PM4_UCODE_SIZE * 12;
d8f60cfc 2037 rlc_req_size = RLC_UCODE_SIZE * 4;
3ce0a23d
JG		 2038 }
2039
d8f60cfc 2040 DRM_INFO("Loading %s Microcode\n", chip_name);
3ce0a23d
JG		 2041
2042 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
2043 err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
2044 if (err)
2045 goto out;
2046 if (rdev->pfp_fw->size != pfp_req_size) {
2047 printk(KERN_ERR
2048 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
2049 rdev->pfp_fw->size, fw_name);
2050 err = -EINVAL;
2051 goto out;
2052 }
2053
2054 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
2055 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
2056 if (err)
2057 goto out;
2058 if (rdev->me_fw->size != me_req_size) {
2059 printk(KERN_ERR
2060 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
2061 rdev->me_fw->size, fw_name);
2062 err = -EINVAL;
2063 }
d8f60cfc
AD		 2064
2065 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
2066 err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev);
2067 if (err)
2068 goto out;
2069 if (rdev->rlc_fw->size != rlc_req_size) {
2070 printk(KERN_ERR
2071 "r600_rlc: Bogus length %zu in firmware \"%s\"\n",
2072 rdev->rlc_fw->size, fw_name);
2073 err = -EINVAL;
2074 }
2075
3ce0a23d
JG		 2076out:
2077 platform_device_unregister(pdev);
2078
2079 if (err) {
2080 if (err != -EINVAL)
2081 printk(KERN_ERR
2082 "r600_cp: Failed to load firmware \"%s\"\n",
2083 fw_name);
2084 release_firmware(rdev->pfp_fw);
2085 rdev->pfp_fw = NULL;
2086 release_firmware(rdev->me_fw);
2087 rdev->me_fw = NULL;
d8f60cfc
AD		 2088 release_firmware(rdev->rlc_fw);
2089 rdev->rlc_fw = NULL;
3ce0a23d
JG		 2090 }
2091 return err;
2092}
2093
2094static int r600_cp_load_microcode(struct radeon_device *rdev)
2095{
2096 const __be32 *fw_data;
2097 int i;
2098
2099 if (!rdev->me_fw || !rdev->pfp_fw)
2100 return -EINVAL;
2101
2102 r600_cp_stop(rdev);
2103
2104 WREG32(CP_RB_CNTL, RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
2105
2106 /* Reset cp */
2107 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2108 RREG32(GRBM_SOFT_RESET);
2109 mdelay(15);
2110 WREG32(GRBM_SOFT_RESET, 0);
2111
2112 WREG32(CP_ME_RAM_WADDR, 0);
2113
2114 fw_data = (const __be32 *)rdev->me_fw->data;
2115 WREG32(CP_ME_RAM_WADDR, 0);
2116 for (i = 0; i < PM4_UCODE_SIZE * 3; i++)
2117 WREG32(CP_ME_RAM_DATA,
2118 be32_to_cpup(fw_data++));
2119
2120 fw_data = (const __be32 *)rdev->pfp_fw->data;
2121 WREG32(CP_PFP_UCODE_ADDR, 0);
2122 for (i = 0; i < PFP_UCODE_SIZE; i++)
2123 WREG32(CP_PFP_UCODE_DATA,
2124 be32_to_cpup(fw_data++));
2125
2126 WREG32(CP_PFP_UCODE_ADDR, 0);
2127 WREG32(CP_ME_RAM_WADDR, 0);
2128 WREG32(CP_ME_RAM_RADDR, 0);
2129 return 0;
2130}
2131
2132int r600_cp_start(struct radeon_device *rdev)
2133{
2134 int r;
2135 uint32_t cp_me;
2136
2137 r = radeon_ring_lock(rdev, 7);
2138 if (r) {
2139 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
2140 return r;
2141 }
2142 radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5));
2143 radeon_ring_write(rdev, 0x1);
7e7b41d2 2144 if (rdev->family >= CHIP_RV770) {
3ce0a23d
JG		 2145 radeon_ring_write(rdev, 0x0);
2146 radeon_ring_write(rdev, rdev->config.rv770.max_hw_contexts - 1);
fe251e2f
AD		 2147 } else {
2148 radeon_ring_write(rdev, 0x3);
2149 radeon_ring_write(rdev, rdev->config.r600.max_hw_contexts - 1);
3ce0a23d
JG		 2150 }
2151 radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
2152 radeon_ring_write(rdev, 0);
2153 radeon_ring_write(rdev, 0);
2154 radeon_ring_unlock_commit(rdev);
2155
2156 cp_me = 0xff;
2157 WREG32(R_0086D8_CP_ME_CNTL, cp_me);
2158 return 0;
2159}
2160
2161int r600_cp_resume(struct radeon_device *rdev)
2162{
2163 u32 tmp;
2164 u32 rb_bufsz;
2165 int r;
2166
2167 /* Reset cp */
2168 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2169 RREG32(GRBM_SOFT_RESET);
2170 mdelay(15);
2171 WREG32(GRBM_SOFT_RESET, 0);
2172
2173 /* Set ring buffer size */
2174 rb_bufsz = drm_order(rdev->cp.ring_size / 8);
724c80e1 2175 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
3ce0a23d 2176#ifdef __BIG_ENDIAN
d6f28938 2177 tmp |= BUF_SWAP_32BIT;
3ce0a23d 2178#endif
d6f28938 2179 WREG32(CP_RB_CNTL, tmp);
3ce0a23d
JG		 2180 WREG32(CP_SEM_WAIT_TIMER, 0x4);
2181
2182 /* Set the write pointer delay */
2183 WREG32(CP_RB_WPTR_DELAY, 0);
2184
2185 /* Initialize the ring buffer's read and write pointers */
3ce0a23d
JG		 2186 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
2187 WREG32(CP_RB_RPTR_WR, 0);
2188 WREG32(CP_RB_WPTR, 0);
724c80e1
AD		 2189
2190 /* set the wb address whether it's enabled or not */
2191 WREG32(CP_RB_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC);
2192 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
2193 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
2194
2195 if (rdev->wb.enabled)
2196 WREG32(SCRATCH_UMSK, 0xff);
2197 else {
2198 tmp |= RB_NO_UPDATE;
2199 WREG32(SCRATCH_UMSK, 0);
2200 }
2201
3ce0a23d
JG		 2202 mdelay(1);
2203 WREG32(CP_RB_CNTL, tmp);
2204
2205 WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8);
2206 WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
2207
2208 rdev->cp.rptr = RREG32(CP_RB_RPTR);
2209 rdev->cp.wptr = RREG32(CP_RB_WPTR);
2210
2211 r600_cp_start(rdev);
2212 rdev->cp.ready = true;
2213 r = radeon_ring_test(rdev);
2214 if (r) {
2215 rdev->cp.ready = false;
2216 return r;
2217 }
2218 return 0;
2219}
2220
2221void r600_cp_commit(struct radeon_device *rdev)
2222{
2223 WREG32(CP_RB_WPTR, rdev->cp.wptr);
2224 (void)RREG32(CP_RB_WPTR);
2225}
2226
2227void r600_ring_init(struct radeon_device *rdev, unsigned ring_size)
2228{
2229 u32 rb_bufsz;
2230
2231 /* Align ring size */
2232 rb_bufsz = drm_order(ring_size / 8);
2233 ring_size = (1 << (rb_bufsz + 1)) * 4;
2234 rdev->cp.ring_size = ring_size;
2235 rdev->cp.align_mask = 16 - 1;
2236}
2237
655efd3d
JG		 2238void r600_cp_fini(struct radeon_device *rdev)
2239{
2240 r600_cp_stop(rdev);
2241 radeon_ring_fini(rdev);
2242}
2243
3ce0a23d
JG		 2244
2245/*
2246 * GPU scratch registers helpers function.
2247 */
2248void r600_scratch_init(struct radeon_device *rdev)
2249{
2250 int i;
2251
2252 rdev->scratch.num_reg = 7;
724c80e1 2253 rdev->scratch.reg_base = SCRATCH_REG0;
3ce0a23d
JG		 2254 for (i = 0; i < rdev->scratch.num_reg; i++) {
2255 rdev->scratch.free[i] = true;
724c80e1 2256 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
3ce0a23d
JG		 2257 }
2258}
2259
2260int r600_ring_test(struct radeon_device *rdev)
2261{
2262 uint32_t scratch;
2263 uint32_t tmp = 0;
2264 unsigned i;
2265 int r;
2266
2267 r = radeon_scratch_get(rdev, &scratch);
2268 if (r) {
2269 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
2270 return r;
2271 }
2272 WREG32(scratch, 0xCAFEDEAD);
2273 r = radeon_ring_lock(rdev, 3);
2274 if (r) {
2275 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
2276 radeon_scratch_free(rdev, scratch);
2277 return r;
2278 }
2279 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2280 radeon_ring_write(rdev, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2281 radeon_ring_write(rdev, 0xDEADBEEF);
2282 radeon_ring_unlock_commit(rdev);
2283 for (i = 0; i < rdev->usec_timeout; i++) {
2284 tmp = RREG32(scratch);
2285 if (tmp == 0xDEADBEEF)
2286 break;
2287 DRM_UDELAY(1);
2288 }
2289 if (i < rdev->usec_timeout) {
2290 DRM_INFO("ring test succeeded in %d usecs\n", i);
2291 } else {
2292 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
2293 scratch, tmp);
2294 r = -EINVAL;
2295 }
2296 radeon_scratch_free(rdev, scratch);
2297 return r;
2298}
2299
3ce0a23d
JG		 2300void r600_fence_ring_emit(struct radeon_device *rdev,
2301 struct radeon_fence *fence)
2302{
d0f8a854
AD		 2303 if (rdev->wb.use_event) {
2304 u64 addr = rdev->wb.gpu_addr + R600_WB_EVENT_OFFSET +
2305 (u64)(rdev->fence_drv.scratch_reg - rdev->scratch.reg_base);
2306 /* EVENT_WRITE_EOP - flush caches, send int */
2307 radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
2308 radeon_ring_write(rdev, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5));
2309 radeon_ring_write(rdev, addr & 0xffffffff);
2310 radeon_ring_write(rdev, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
2311 radeon_ring_write(rdev, fence->seq);
2312 radeon_ring_write(rdev, 0);
2313 } else {
2314 radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE, 0));
2315 radeon_ring_write(rdev, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0));
2316 /* wait for 3D idle clean */
2317 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2318 radeon_ring_write(rdev, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2319 radeon_ring_write(rdev, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit);
2320 /* Emit fence sequence & fire IRQ */
2321 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2322 radeon_ring_write(rdev, ((rdev->fence_drv.scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2323 radeon_ring_write(rdev, fence->seq);
2324 /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */
2325 radeon_ring_write(rdev, PACKET0(CP_INT_STATUS, 0));
2326 radeon_ring_write(rdev, RB_INT_STAT);
2327 }
3ce0a23d
JG		 2328}
2329
3ce0a23d
JG		 2330int r600_copy_blit(struct radeon_device *rdev,
2331 uint64_t src_offset, uint64_t dst_offset,
2332 unsigned num_pages, struct radeon_fence *fence)
2333{
ff82f052
JG		 2334 int r;
2335
2336 mutex_lock(&rdev->r600_blit.mutex);
2337 rdev->r600_blit.vb_ib = NULL;
2338 r = r600_blit_prepare_copy(rdev, num_pages * RADEON_GPU_PAGE_SIZE);
2339 if (r) {
2340 if (rdev->r600_blit.vb_ib)
2341 radeon_ib_free(rdev, &rdev->r600_blit.vb_ib);
2342 mutex_unlock(&rdev->r600_blit.mutex);
2343 return r;
2344 }
a77f1718 2345 r600_kms_blit_copy(rdev, src_offset, dst_offset, num_pages * RADEON_GPU_PAGE_SIZE);
3ce0a23d 2346 r600_blit_done_copy(rdev, fence);
ff82f052 2347 mutex_unlock(&rdev->r600_blit.mutex);
3ce0a23d
JG		 2348 return 0;
2349}
2350
3ce0a23d
JG		 2351int r600_set_surface_reg(struct radeon_device *rdev, int reg,
2352 uint32_t tiling_flags, uint32_t pitch,
2353 uint32_t offset, uint32_t obj_size)
2354{
2355 /* FIXME: implement */
2356 return 0;
2357}
2358
2359void r600_clear_surface_reg(struct radeon_device *rdev, int reg)
2360{
2361 /* FIXME: implement */
2362}
2363
fc30b8ef 2364int r600_startup(struct radeon_device *rdev)
3ce0a23d
JG		 2365{
2366 int r;
2367
9e46a48d
AD		 2368 /* enable pcie gen2 link */
2369 r600_pcie_gen2_enable(rdev);
2370
779720a3
AD		 2371 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
2372 r = r600_init_microcode(rdev);
2373 if (r) {
2374 DRM_ERROR("Failed to load firmware!\n");
2375 return r;
2376 }
2377 }
2378
a3c1945a 2379 r600_mc_program(rdev);
1a029b76
JG		 2380 if (rdev->flags & RADEON_IS_AGP) {
2381 r600_agp_enable(rdev);
2382 } else {
2383 r = r600_pcie_gart_enable(rdev);
2384 if (r)
2385 return r;
2386 }
3ce0a23d 2387 r600_gpu_init(rdev);
c38c7b64
JG		 2388 r = r600_blit_init(rdev);
2389 if (r) {
2390 r600_blit_fini(rdev);
2391 rdev->asic->copy = NULL;
2392 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
2393 }
b70d6bb3 2394
724c80e1
AD		 2395 /* allocate wb buffer */
2396 r = radeon_wb_init(rdev);
2397 if (r)
2398 return r;
2399
d8f60cfc 2400 /* Enable IRQ */
d8f60cfc
AD		 2401 r = r600_irq_init(rdev);
2402 if (r) {
2403 DRM_ERROR("radeon: IH init failed (%d).\n", r);
2404 radeon_irq_kms_fini(rdev);
2405 return r;
2406 }
2407 r600_irq_set(rdev);
2408
3ce0a23d
JG		 2409 r = radeon_ring_init(rdev, rdev->cp.ring_size);
2410 if (r)
2411 return r;
2412 r = r600_cp_load_microcode(rdev);
2413 if (r)
2414 return r;
2415 r = r600_cp_resume(rdev);
2416 if (r)
2417 return r;
724c80e1 2418
3ce0a23d
JG		 2419 return 0;
2420}
2421
28d52043
DA		 2422void r600_vga_set_state(struct radeon_device *rdev, bool state)
2423{
2424 uint32_t temp;
2425
2426 temp = RREG32(CONFIG_CNTL);
2427 if (state == false) {
2428 temp &= ~(1<<0);
2429 temp |= (1<<1);
2430 } else {
2431 temp &= ~(1<<1);
2432 }
2433 WREG32(CONFIG_CNTL, temp);
2434}
2435
fc30b8ef
DA		 2436int r600_resume(struct radeon_device *rdev)
2437{
2438 int r;
2439
1a029b76
JG		 2440 /* Do not reset GPU before posting, on r600 hw unlike on r500 hw,
2441 * posting will perform necessary task to bring back GPU into good
2442 * shape.
2443 */
fc30b8ef 2444 /* post card */
e7d40b9a 2445 atom_asic_init(rdev->mode_info.atom_context);
fc30b8ef
DA		 2446
2447 r = r600_startup(rdev);
2448 if (r) {
2449 DRM_ERROR("r600 startup failed on resume\n");
2450 return r;
2451 }
2452
62a8ea3f 2453 r = r600_ib_test(rdev);
fc30b8ef
DA		 2454 if (r) {
2455 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
2456 return r;
2457 }
38fd2c6f
RM		 2458
2459 r = r600_audio_init(rdev);
2460 if (r) {
2461 DRM_ERROR("radeon: audio resume failed\n");
2462 return r;
2463 }
2464
fc30b8ef
DA		 2465 return r;
2466}
2467
3ce0a23d
JG		 2468int r600_suspend(struct radeon_device *rdev)
2469{
4c788679
JG		 2470 int r;
2471
38fd2c6f 2472 r600_audio_fini(rdev);
3ce0a23d
JG		 2473 /* FIXME: we should wait for ring to be empty */
2474 r600_cp_stop(rdev);
bc1a631e 2475 rdev->cp.ready = false;
0c45249f 2476 r600_irq_suspend(rdev);
724c80e1 2477 radeon_wb_disable(rdev);
4aac0473 2478 r600_pcie_gart_disable(rdev);
bc1a631e 2479 /* unpin shaders bo */
30d2d9a5
JG		 2480 if (rdev->r600_blit.shader_obj) {
2481 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
2482 if (!r) {
2483 radeon_bo_unpin(rdev->r600_blit.shader_obj);
2484 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
2485 }
2486 }
3ce0a23d
JG		 2487 return 0;
2488}
2489
2490/* Plan is to move initialization in that function and use
2491 * helper function so that radeon_device_init pretty much
2492 * do nothing more than calling asic specific function. This
2493 * should also allow to remove a bunch of callback function
2494 * like vram_info.
2495 */
2496int r600_init(struct radeon_device *rdev)
771fe6b9 2497{
3ce0a23d 2498 int r;
771fe6b9 2499
3ce0a23d
JG		 2500 r = radeon_dummy_page_init(rdev);
2501 if (r)
2502 return r;
2503 if (r600_debugfs_mc_info_init(rdev)) {
2504 DRM_ERROR("Failed to register debugfs file for mc !\n");
2505 }
2506 /* This don't do much */
2507 r = radeon_gem_init(rdev);
2508 if (r)
2509 return r;
2510 /* Read BIOS */
2511 if (!radeon_get_bios(rdev)) {
2512 if (ASIC_IS_AVIVO(rdev))
2513 return -EINVAL;
2514 }
2515 /* Must be an ATOMBIOS */
e7d40b9a
JG		 2516 if (!rdev->is_atom_bios) {
2517 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
3ce0a23d 2518 return -EINVAL;
e7d40b9a 2519 }
3ce0a23d
JG		 2520 r = radeon_atombios_init(rdev);
2521 if (r)
2522 return r;
2523 /* Post card if necessary */
fd909c37 2524 if (!radeon_card_posted(rdev)) {
72542d77
DA		 2525 if (!rdev->bios) {
2526 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
2527 return -EINVAL;
2528 }
3ce0a23d
JG		 2529 DRM_INFO("GPU not posted. posting now...\n");
2530 atom_asic_init(rdev->mode_info.atom_context);
2531 }
2532 /* Initialize scratch registers */
2533 r600_scratch_init(rdev);
2534 /* Initialize surface registers */
2535 radeon_surface_init(rdev);
7433874e 2536 /* Initialize clocks */
5e6dde7e 2537 radeon_get_clock_info(rdev->ddev);
3ce0a23d
JG		 2538 /* Fence driver */
2539 r = radeon_fence_driver_init(rdev);
2540 if (r)
2541 return r;
700a0cc0
JG		 2542 if (rdev->flags & RADEON_IS_AGP) {
2543 r = radeon_agp_init(rdev);
2544 if (r)
2545 radeon_agp_disable(rdev);
2546 }
3ce0a23d 2547 r = r600_mc_init(rdev);
b574f251 2548 if (r)
3ce0a23d 2549 return r;
3ce0a23d 2550 /* Memory manager */
4c788679 2551 r = radeon_bo_init(rdev);
3ce0a23d
JG		 2552 if (r)
2553 return r;
d8f60cfc
AD		 2554
2555 r = radeon_irq_kms_init(rdev);
2556 if (r)
2557 return r;
2558
3ce0a23d
JG		 2559 rdev->cp.ring_obj = NULL;
2560 r600_ring_init(rdev, 1024 * 1024);
2561
d8f60cfc
AD		 2562 rdev->ih.ring_obj = NULL;
2563 r600_ih_ring_init(rdev, 64 * 1024);
3ce0a23d 2564
4aac0473
JG		 2565 r = r600_pcie_gart_init(rdev);
2566 if (r)
2567 return r;
2568
779720a3 2569 rdev->accel_working = true;
fc30b8ef 2570 r = r600_startup(rdev);
3ce0a23d 2571 if (r) {
655efd3d
JG		 2572 dev_err(rdev->dev, "disabling GPU acceleration\n");
2573 r600_cp_fini(rdev);
655efd3d 2574 r600_irq_fini(rdev);
724c80e1 2575 radeon_wb_fini(rdev);
655efd3d 2576 radeon_irq_kms_fini(rdev);
75c81298 2577 r600_pcie_gart_fini(rdev);
733289c2 2578 rdev->accel_working = false;
3ce0a23d 2579 }
733289c2
JG		 2580 if (rdev->accel_working) {
2581 r = radeon_ib_pool_init(rdev);
2582 if (r) {
db96380e 2583 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
733289c2 2584 rdev->accel_working = false;
db96380e
JG		 2585 } else {
2586 r = r600_ib_test(rdev);
2587 if (r) {
2588 dev_err(rdev->dev, "IB test failed (%d).\n", r);
2589 rdev->accel_working = false;
2590 }
733289c2 2591 }
3ce0a23d 2592 }
dafc3bd5
CK		 2593
2594 r = r600_audio_init(rdev);
2595 if (r)
2596 return r; /* TODO error handling */
3ce0a23d
JG		 2597 return 0;
2598}
2599
2600void r600_fini(struct radeon_device *rdev)
2601{
dafc3bd5 2602 r600_audio_fini(rdev);
3ce0a23d 2603 r600_blit_fini(rdev);
655efd3d 2604 r600_cp_fini(rdev);
d8f60cfc 2605 r600_irq_fini(rdev);
724c80e1 2606 radeon_wb_fini(rdev);
d8f60cfc 2607 radeon_irq_kms_fini(rdev);
4aac0473 2608 r600_pcie_gart_fini(rdev);
655efd3d 2609 radeon_agp_fini(rdev);
3ce0a23d
JG		 2610 radeon_gem_fini(rdev);
2611 radeon_fence_driver_fini(rdev);
4c788679 2612 radeon_bo_fini(rdev);
e7d40b9a 2613 radeon_atombios_fini(rdev);
3ce0a23d
JG		 2614 kfree(rdev->bios);
2615 rdev->bios = NULL;
2616 radeon_dummy_page_fini(rdev);
2617}
2618
2619
2620/*
2621 * CS stuff
2622 */
2623void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
2624{
2625 /* FIXME: implement */
2626 radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
2627 radeon_ring_write(rdev, ib->gpu_addr & 0xFFFFFFFC);
2628 radeon_ring_write(rdev, upper_32_bits(ib->gpu_addr) & 0xFF);
2629 radeon_ring_write(rdev, ib->length_dw);
2630}
2631
2632int r600_ib_test(struct radeon_device *rdev)
2633{
2634 struct radeon_ib *ib;
2635 uint32_t scratch;
2636 uint32_t tmp = 0;
2637 unsigned i;
2638 int r;
2639
2640 r = radeon_scratch_get(rdev, &scratch);
2641 if (r) {
2642 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
2643 return r;
2644 }
2645 WREG32(scratch, 0xCAFEDEAD);
2646 r = radeon_ib_get(rdev, &ib);
2647 if (r) {
2648 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
2649 return r;
2650 }
2651 ib->ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
2652 ib->ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2653 ib->ptr[2] = 0xDEADBEEF;
2654 ib->ptr[3] = PACKET2(0);
2655 ib->ptr[4] = PACKET2(0);
2656 ib->ptr[5] = PACKET2(0);
2657 ib->ptr[6] = PACKET2(0);
2658 ib->ptr[7] = PACKET2(0);
2659 ib->ptr[8] = PACKET2(0);
2660 ib->ptr[9] = PACKET2(0);
2661 ib->ptr[10] = PACKET2(0);
2662 ib->ptr[11] = PACKET2(0);
2663 ib->ptr[12] = PACKET2(0);
2664 ib->ptr[13] = PACKET2(0);
2665 ib->ptr[14] = PACKET2(0);
2666 ib->ptr[15] = PACKET2(0);
2667 ib->length_dw = 16;
2668 r = radeon_ib_schedule(rdev, ib);
2669 if (r) {
2670 radeon_scratch_free(rdev, scratch);
2671 radeon_ib_free(rdev, &ib);
2672 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
2673 return r;
2674 }
2675 r = radeon_fence_wait(ib->fence, false);
2676 if (r) {
2677 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
2678 return r;
2679 }
2680 for (i = 0; i < rdev->usec_timeout; i++) {
2681 tmp = RREG32(scratch);
2682 if (tmp == 0xDEADBEEF)
2683 break;
2684 DRM_UDELAY(1);
2685 }
2686 if (i < rdev->usec_timeout) {
2687 DRM_INFO("ib test succeeded in %u usecs\n", i);
2688 } else {
4417d7f6 2689 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
3ce0a23d
JG		 2690 scratch, tmp);
2691 r = -EINVAL;
2692 }
2693 radeon_scratch_free(rdev, scratch);
2694 radeon_ib_free(rdev, &ib);
771fe6b9
JG		 2695 return r;
2696}
2697
d8f60cfc
AD		 2698/*
2699 * Interrupts
2700 *
2701 * Interrupts use a ring buffer on r6xx/r7xx hardware. It works pretty
2702 * the same as the CP ring buffer, but in reverse. Rather than the CPU
2703 * writing to the ring and the GPU consuming, the GPU writes to the ring
2704 * and host consumes. As the host irq handler processes interrupts, it
2705 * increments the rptr. When the rptr catches up with the wptr, all the
2706 * current interrupts have been processed.
2707 */
2708
2709void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size)
2710{
2711 u32 rb_bufsz;
2712
2713 /* Align ring size */
2714 rb_bufsz = drm_order(ring_size / 4);
2715 ring_size = (1 << rb_bufsz) * 4;
2716 rdev->ih.ring_size = ring_size;
0c45249f
JG		 2717 rdev->ih.ptr_mask = rdev->ih.ring_size - 1;
2718 rdev->ih.rptr = 0;
d8f60cfc
AD		 2719}
2720
0c45249f 2721static int r600_ih_ring_alloc(struct radeon_device *rdev)
d8f60cfc
AD		 2722{
2723 int r;
2724
d8f60cfc
AD		 2725 /* Allocate ring buffer */
2726 if (rdev->ih.ring_obj == NULL) {
4c788679 2727 r = radeon_bo_create(rdev, NULL, rdev->ih.ring_size,
268b2510 2728 PAGE_SIZE, true,
4c788679
JG		 2729 RADEON_GEM_DOMAIN_GTT,
2730 &rdev->ih.ring_obj);
d8f60cfc
AD		 2731 if (r) {
2732 DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r);
2733 return r;
2734 }
4c788679
JG		 2735 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
2736 if (unlikely(r != 0))
2737 return r;
2738 r = radeon_bo_pin(rdev->ih.ring_obj,
2739 RADEON_GEM_DOMAIN_GTT,
2740 &rdev->ih.gpu_addr);
d8f60cfc 2741 if (r) {
4c788679 2742 radeon_bo_unreserve(rdev->ih.ring_obj);
d8f60cfc
AD		 2743 DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r);
2744 return r;
2745 }
4c788679
JG		 2746 r = radeon_bo_kmap(rdev->ih.ring_obj,
2747 (void **)&rdev->ih.ring);
2748 radeon_bo_unreserve(rdev->ih.ring_obj);
d8f60cfc
AD		 2749 if (r) {
2750 DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r);
2751 return r;
2752 }
2753 }
d8f60cfc
AD		 2754 return 0;
2755}
2756
2757static void r600_ih_ring_fini(struct radeon_device *rdev)
2758{
4c788679 2759 int r;
d8f60cfc 2760 if (rdev->ih.ring_obj) {
4c788679
JG		 2761 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
2762 if (likely(r == 0)) {
2763 radeon_bo_kunmap(rdev->ih.ring_obj);
2764 radeon_bo_unpin(rdev->ih.ring_obj);
2765 radeon_bo_unreserve(rdev->ih.ring_obj);
2766 }
2767 radeon_bo_unref(&rdev->ih.ring_obj);
d8f60cfc
AD		 2768 rdev->ih.ring = NULL;
2769 rdev->ih.ring_obj = NULL;
2770 }
2771}
2772
45f9a39b 2773void r600_rlc_stop(struct radeon_device *rdev)
d8f60cfc
AD		 2774{
2775
45f9a39b
AD		 2776 if ((rdev->family >= CHIP_RV770) &&
2777 (rdev->family <= CHIP_RV740)) {
d8f60cfc
AD		 2778 /* r7xx asics need to soft reset RLC before halting */
2779 WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC);
2780 RREG32(SRBM_SOFT_RESET);
2781 udelay(15000);
2782 WREG32(SRBM_SOFT_RESET, 0);
2783 RREG32(SRBM_SOFT_RESET);
2784 }
2785
2786 WREG32(RLC_CNTL, 0);
2787}
2788
2789static void r600_rlc_start(struct radeon_device *rdev)
2790{
2791 WREG32(RLC_CNTL, RLC_ENABLE);
2792}
2793
2794static int r600_rlc_init(struct radeon_device *rdev)
2795{
2796 u32 i;
2797 const __be32 *fw_data;
2798
2799 if (!rdev->rlc_fw)
2800 return -EINVAL;
2801
2802 r600_rlc_stop(rdev);
2803
2804 WREG32(RLC_HB_BASE, 0);
2805 WREG32(RLC_HB_CNTL, 0);
2806 WREG32(RLC_HB_RPTR, 0);
2807 WREG32(RLC_HB_WPTR, 0);
2808 WREG32(RLC_HB_WPTR_LSB_ADDR, 0);
2809 WREG32(RLC_HB_WPTR_MSB_ADDR, 0);
2810 WREG32(RLC_MC_CNTL, 0);
2811 WREG32(RLC_UCODE_CNTL, 0);
2812
2813 fw_data = (const __be32 *)rdev->rlc_fw->data;
45f9a39b
AD		 2814 if (rdev->family >= CHIP_CEDAR) {
2815 for (i = 0; i < EVERGREEN_RLC_UCODE_SIZE; i++) {
2816 WREG32(RLC_UCODE_ADDR, i);
2817 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2818 }
2819 } else if (rdev->family >= CHIP_RV770) {
d8f60cfc
AD		 2820 for (i = 0; i < R700_RLC_UCODE_SIZE; i++) {
2821 WREG32(RLC_UCODE_ADDR, i);
2822 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2823 }
2824 } else {
2825 for (i = 0; i < RLC_UCODE_SIZE; i++) {
2826 WREG32(RLC_UCODE_ADDR, i);
2827 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2828 }
2829 }
2830 WREG32(RLC_UCODE_ADDR, 0);
2831
2832 r600_rlc_start(rdev);
2833
2834 return 0;
2835}
2836
2837static void r600_enable_interrupts(struct radeon_device *rdev)
2838{
2839 u32 ih_cntl = RREG32(IH_CNTL);
2840 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2841
2842 ih_cntl |= ENABLE_INTR;
2843 ih_rb_cntl |= IH_RB_ENABLE;
2844 WREG32(IH_CNTL, ih_cntl);
2845 WREG32(IH_RB_CNTL, ih_rb_cntl);
2846 rdev->ih.enabled = true;
2847}
2848
45f9a39b 2849void r600_disable_interrupts(struct radeon_device *rdev)
d8f60cfc
AD		 2850{
2851 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2852 u32 ih_cntl = RREG32(IH_CNTL);
2853
2854 ih_rb_cntl &= ~IH_RB_ENABLE;
2855 ih_cntl &= ~ENABLE_INTR;
2856 WREG32(IH_RB_CNTL, ih_rb_cntl);
2857 WREG32(IH_CNTL, ih_cntl);
2858 /* set rptr, wptr to 0 */
2859 WREG32(IH_RB_RPTR, 0);
2860 WREG32(IH_RB_WPTR, 0);
2861 rdev->ih.enabled = false;
2862 rdev->ih.wptr = 0;
2863 rdev->ih.rptr = 0;
2864}
2865
e0df1ac5
AD		 2866static void r600_disable_interrupt_state(struct radeon_device *rdev)
2867{
2868 u32 tmp;
2869
3555e53b 2870 WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
e0df1ac5
AD		 2871 WREG32(GRBM_INT_CNTL, 0);
2872 WREG32(DxMODE_INT_MASK, 0);
6f34be50
AD		 2873 WREG32(D1GRPH_INTERRUPT_CONTROL, 0);
2874 WREG32(D2GRPH_INTERRUPT_CONTROL, 0);
e0df1ac5
AD		 2875 if (ASIC_IS_DCE3(rdev)) {
2876 WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0);
2877 WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0);
2878 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2879 WREG32(DC_HPD1_INT_CONTROL, tmp);
2880 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2881 WREG32(DC_HPD2_INT_CONTROL, tmp);
2882 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2883 WREG32(DC_HPD3_INT_CONTROL, tmp);
2884 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2885 WREG32(DC_HPD4_INT_CONTROL, tmp);
2886 if (ASIC_IS_DCE32(rdev)) {
2887 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
5898b1f3 2888 WREG32(DC_HPD5_INT_CONTROL, tmp);
e0df1ac5 2889 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
5898b1f3 2890 WREG32(DC_HPD6_INT_CONTROL, tmp);
e0df1ac5
AD		 2891 }
2892 } else {
2893 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
2894 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
2895 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
5898b1f3 2896 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
e0df1ac5 2897 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
5898b1f3 2898 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
e0df1ac5 2899 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
5898b1f3 2900 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
e0df1ac5
AD		 2901 }
2902}
2903
d8f60cfc
AD		 2904int r600_irq_init(struct radeon_device *rdev)
2905{
2906 int ret = 0;
2907 int rb_bufsz;
2908 u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
2909
2910 /* allocate ring */
0c45249f 2911 ret = r600_ih_ring_alloc(rdev);
d8f60cfc
AD		 2912 if (ret)
2913 return ret;
2914
2915 /* disable irqs */
2916 r600_disable_interrupts(rdev);
2917
2918 /* init rlc */
2919 ret = r600_rlc_init(rdev);
2920 if (ret) {
2921 r600_ih_ring_fini(rdev);
2922 return ret;
2923 }
2924
2925 /* setup interrupt control */
2926 /* set dummy read address to ring address */
2927 WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8);
2928 interrupt_cntl = RREG32(INTERRUPT_CNTL);
2929 /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
2930 * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
2931 */
2932 interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
2933 /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
2934 interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
2935 WREG32(INTERRUPT_CNTL, interrupt_cntl);
2936
2937 WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
2938 rb_bufsz = drm_order(rdev->ih.ring_size / 4);
2939
2940 ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
2941 IH_WPTR_OVERFLOW_CLEAR |
2942 (rb_bufsz << 1));
724c80e1
AD		 2943
2944 if (rdev->wb.enabled)
2945 ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;
2946
2947 /* set the writeback address whether it's enabled or not */
2948 WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC);
2949 WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF);
d8f60cfc
AD		 2950
2951 WREG32(IH_RB_CNTL, ih_rb_cntl);
2952
2953 /* set rptr, wptr to 0 */
2954 WREG32(IH_RB_RPTR, 0);
2955 WREG32(IH_RB_WPTR, 0);
2956
2957 /* Default settings for IH_CNTL (disabled at first) */
2958 ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10);
2959 /* RPTR_REARM only works if msi's are enabled */
2960 if (rdev->msi_enabled)
2961 ih_cntl |= RPTR_REARM;
2962
2963#ifdef __BIG_ENDIAN
2964 ih_cntl |= IH_MC_SWAP(IH_MC_SWAP_32BIT);
2965#endif
2966 WREG32(IH_CNTL, ih_cntl);
2967
2968 /* force the active interrupt state to all disabled */
45f9a39b
AD		 2969 if (rdev->family >= CHIP_CEDAR)
2970 evergreen_disable_interrupt_state(rdev);
2971 else
2972 r600_disable_interrupt_state(rdev);
d8f60cfc
AD		 2973
2974 /* enable irqs */
2975 r600_enable_interrupts(rdev);
2976
2977 return ret;
2978}
2979
0c45249f 2980void r600_irq_suspend(struct radeon_device *rdev)
d8f60cfc 2981{
45f9a39b 2982 r600_irq_disable(rdev);
d8f60cfc 2983 r600_rlc_stop(rdev);
0c45249f
JG		 2984}
2985
2986void r600_irq_fini(struct radeon_device *rdev)
2987{
2988 r600_irq_suspend(rdev);
d8f60cfc
AD		 2989 r600_ih_ring_fini(rdev);
2990}
2991
2992int r600_irq_set(struct radeon_device *rdev)
2993{
e0df1ac5
AD		 2994 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
2995 u32 mode_int = 0;
2996 u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0;
2031f77c 2997 u32 grbm_int_cntl = 0;
f2594933 2998 u32 hdmi1, hdmi2;
6f34be50 2999 u32 d1grph = 0, d2grph = 0;
d8f60cfc 3000
003e69f9 3001 if (!rdev->irq.installed) {
fce7d61b 3002 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
003e69f9
JG		 3003 return -EINVAL;
3004 }
d8f60cfc 3005 /* don't enable anything if the ih is disabled */
79c2bbc5
JG		 3006 if (!rdev->ih.enabled) {
3007 r600_disable_interrupts(rdev);
3008 /* force the active interrupt state to all disabled */
3009 r600_disable_interrupt_state(rdev);
d8f60cfc 3010 return 0;
79c2bbc5 3011 }
d8f60cfc 3012
f2594933 3013 hdmi1 = RREG32(R600_HDMI_BLOCK1 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN;
e0df1ac5 3014 if (ASIC_IS_DCE3(rdev)) {
f2594933 3015 hdmi2 = RREG32(R600_HDMI_BLOCK3 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN;
e0df1ac5
AD		 3016 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3017 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3018 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3019 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
3020 if (ASIC_IS_DCE32(rdev)) {
3021 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
3022 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
3023 }
3024 } else {
f2594933 3025 hdmi2 = RREG32(R600_HDMI_BLOCK2 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN;
e0df1ac5
AD		 3026 hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3027 hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3028 hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3029 }
3030
d8f60cfc
AD		 3031 if (rdev->irq.sw_int) {
3032 DRM_DEBUG("r600_irq_set: sw int\n");
3033 cp_int_cntl |= RB_INT_ENABLE;
d0f8a854 3034 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
d8f60cfc 3035 }
6f34be50
AD		 3036 if (rdev->irq.crtc_vblank_int[0] ||
3037 rdev->irq.pflip[0]) {
d8f60cfc
AD		 3038 DRM_DEBUG("r600_irq_set: vblank 0\n");
3039 mode_int |= D1MODE_VBLANK_INT_MASK;
3040 }
6f34be50
AD		 3041 if (rdev->irq.crtc_vblank_int[1] ||
3042 rdev->irq.pflip[1]) {
d8f60cfc
AD		 3043 DRM_DEBUG("r600_irq_set: vblank 1\n");
3044 mode_int |= D2MODE_VBLANK_INT_MASK;
3045 }
e0df1ac5
AD		 3046 if (rdev->irq.hpd[0]) {
3047 DRM_DEBUG("r600_irq_set: hpd 1\n");
3048 hpd1 |= DC_HPDx_INT_EN;
3049 }
3050 if (rdev->irq.hpd[1]) {
3051 DRM_DEBUG("r600_irq_set: hpd 2\n");
3052 hpd2 |= DC_HPDx_INT_EN;
3053 }
3054 if (rdev->irq.hpd[2]) {
3055 DRM_DEBUG("r600_irq_set: hpd 3\n");
3056 hpd3 |= DC_HPDx_INT_EN;
3057 }
3058 if (rdev->irq.hpd[3]) {
3059 DRM_DEBUG("r600_irq_set: hpd 4\n");
3060 hpd4 |= DC_HPDx_INT_EN;
3061 }
3062 if (rdev->irq.hpd[4]) {
3063 DRM_DEBUG("r600_irq_set: hpd 5\n");
3064 hpd5 |= DC_HPDx_INT_EN;
3065 }
3066 if (rdev->irq.hpd[5]) {
3067 DRM_DEBUG("r600_irq_set: hpd 6\n");
3068 hpd6 |= DC_HPDx_INT_EN;
3069 }
f2594933
CK		 3070 if (rdev->irq.hdmi[0]) {
3071 DRM_DEBUG("r600_irq_set: hdmi 1\n");
3072 hdmi1 |= R600_HDMI_INT_EN;
3073 }
3074 if (rdev->irq.hdmi[1]) {
3075 DRM_DEBUG("r600_irq_set: hdmi 2\n");
3076 hdmi2 |= R600_HDMI_INT_EN;
3077 }
2031f77c
AD		 3078 if (rdev->irq.gui_idle) {
3079 DRM_DEBUG("gui idle\n");
3080 grbm_int_cntl |= GUI_IDLE_INT_ENABLE;
3081 }
d8f60cfc
AD		 3082
3083 WREG32(CP_INT_CNTL, cp_int_cntl);
3084 WREG32(DxMODE_INT_MASK, mode_int);
6f34be50
AD		 3085 WREG32(D1GRPH_INTERRUPT_CONTROL, d1grph);
3086 WREG32(D2GRPH_INTERRUPT_CONTROL, d2grph);
2031f77c 3087 WREG32(GRBM_INT_CNTL, grbm_int_cntl);
f2594933 3088 WREG32(R600_HDMI_BLOCK1 + R600_HDMI_CNTL, hdmi1);
e0df1ac5 3089 if (ASIC_IS_DCE3(rdev)) {
f2594933 3090 WREG32(R600_HDMI_BLOCK3 + R600_HDMI_CNTL, hdmi2);
e0df1ac5
AD		 3091 WREG32(DC_HPD1_INT_CONTROL, hpd1);
3092 WREG32(DC_HPD2_INT_CONTROL, hpd2);
3093 WREG32(DC_HPD3_INT_CONTROL, hpd3);
3094 WREG32(DC_HPD4_INT_CONTROL, hpd4);
3095 if (ASIC_IS_DCE32(rdev)) {
3096 WREG32(DC_HPD5_INT_CONTROL, hpd5);
3097 WREG32(DC_HPD6_INT_CONTROL, hpd6);
3098 }
3099 } else {
f2594933 3100 WREG32(R600_HDMI_BLOCK2 + R600_HDMI_CNTL, hdmi2);
e0df1ac5
AD		 3101 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
3102 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
3103 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3);
3104 }
d8f60cfc
AD		 3105
3106 return 0;
3107}
3108
6f34be50 3109static inline void r600_irq_ack(struct radeon_device *rdev)
d8f60cfc 3110{
e0df1ac5
AD		 3111 u32 tmp;
3112
3113 if (ASIC_IS_DCE3(rdev)) {
6f34be50
AD		 3114 rdev->irq.stat_regs.r600.disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS);
3115 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE);
3116 rdev->irq.stat_regs.r600.disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2);
e0df1ac5 3117 } else {
6f34be50
AD		 3118 rdev->irq.stat_regs.r600.disp_int = RREG32(DISP_INTERRUPT_STATUS);
3119 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
3120 rdev->irq.stat_regs.r600.disp_int_cont2 = 0;
3121 }
3122 rdev->irq.stat_regs.r600.d1grph_int = RREG32(D1GRPH_INTERRUPT_STATUS);
3123 rdev->irq.stat_regs.r600.d2grph_int = RREG32(D2GRPH_INTERRUPT_STATUS);
3124
3125 if (rdev->irq.stat_regs.r600.d1grph_int & DxGRPH_PFLIP_INT_OCCURRED)
3126 WREG32(D1GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR);
3127 if (rdev->irq.stat_regs.r600.d2grph_int & DxGRPH_PFLIP_INT_OCCURRED)
3128 WREG32(D2GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR);
3129 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT)
d8f60cfc 3130 WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
6f34be50 3131 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT)
d8f60cfc 3132 WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
6f34be50 3133 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT)
d8f60cfc 3134 WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
6f34be50 3135 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT)
d8f60cfc 3136 WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
6f34be50 3137 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) {
e0df1ac5
AD		 3138 if (ASIC_IS_DCE3(rdev)) {
3139 tmp = RREG32(DC_HPD1_INT_CONTROL);
3140 tmp |= DC_HPDx_INT_ACK;
3141 WREG32(DC_HPD1_INT_CONTROL, tmp);
3142 } else {
3143 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
3144 tmp |= DC_HPDx_INT_ACK;
3145 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
3146 }
3147 }
6f34be50 3148 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) {
e0df1ac5
AD		 3149 if (ASIC_IS_DCE3(rdev)) {
3150 tmp = RREG32(DC_HPD2_INT_CONTROL);
3151 tmp |= DC_HPDx_INT_ACK;
3152 WREG32(DC_HPD2_INT_CONTROL, tmp);
3153 } else {
3154 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
3155 tmp |= DC_HPDx_INT_ACK;
3156 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
3157 }
3158 }
6f34be50 3159 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) {
e0df1ac5
AD		 3160 if (ASIC_IS_DCE3(rdev)) {
3161 tmp = RREG32(DC_HPD3_INT_CONTROL);
3162 tmp |= DC_HPDx_INT_ACK;
3163 WREG32(DC_HPD3_INT_CONTROL, tmp);
3164 } else {
3165 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
3166 tmp |= DC_HPDx_INT_ACK;
3167 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
3168 }
3169 }
6f34be50 3170 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) {
e0df1ac5
AD		 3171 tmp = RREG32(DC_HPD4_INT_CONTROL);
3172 tmp |= DC_HPDx_INT_ACK;
3173 WREG32(DC_HPD4_INT_CONTROL, tmp);
3174 }
3175 if (ASIC_IS_DCE32(rdev)) {
6f34be50 3176 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) {
e0df1ac5
AD		 3177 tmp = RREG32(DC_HPD5_INT_CONTROL);
3178 tmp |= DC_HPDx_INT_ACK;
3179 WREG32(DC_HPD5_INT_CONTROL, tmp);
3180 }
6f34be50 3181 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) {
e0df1ac5
AD		 3182 tmp = RREG32(DC_HPD5_INT_CONTROL);
3183 tmp |= DC_HPDx_INT_ACK;
3184 WREG32(DC_HPD6_INT_CONTROL, tmp);
3185 }
3186 }
f2594933
CK		 3187 if (RREG32(R600_HDMI_BLOCK1 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) {
3188 WREG32_P(R600_HDMI_BLOCK1 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK);
3189 }
3190 if (ASIC_IS_DCE3(rdev)) {
3191 if (RREG32(R600_HDMI_BLOCK3 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) {
3192 WREG32_P(R600_HDMI_BLOCK3 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK);
3193 }
3194 } else {
3195 if (RREG32(R600_HDMI_BLOCK2 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) {
3196 WREG32_P(R600_HDMI_BLOCK2 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK);
3197 }
3198 }
d8f60cfc
AD		 3199}
3200
3201void r600_irq_disable(struct radeon_device *rdev)
3202{
d8f60cfc
AD		 3203 r600_disable_interrupts(rdev);
3204 /* Wait and acknowledge irq */
3205 mdelay(1);
6f34be50 3206 r600_irq_ack(rdev);
e0df1ac5 3207 r600_disable_interrupt_state(rdev);
d8f60cfc
AD		 3208}
3209
3210static inline u32 r600_get_ih_wptr(struct radeon_device *rdev)
3211{
3212 u32 wptr, tmp;
3ce0a23d 3213
724c80e1
AD		 3214 if (rdev->wb.enabled)
3215 wptr = rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4];
3216 else
3217 wptr = RREG32(IH_RB_WPTR);
3ce0a23d 3218
d8f60cfc 3219 if (wptr & RB_OVERFLOW) {
7924e5eb
JG		 3220 /* When a ring buffer overflow happen start parsing interrupt
3221 * from the last not overwritten vector (wptr + 16). Hopefully
3222 * this should allow us to catchup.
3223 */
3224 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
3225 wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
3226 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
d8f60cfc
AD		 3227 tmp = RREG32(IH_RB_CNTL);
3228 tmp |= IH_WPTR_OVERFLOW_CLEAR;
3229 WREG32(IH_RB_CNTL, tmp);
3230 }
0c45249f 3231 return (wptr & rdev->ih.ptr_mask);
d8f60cfc 3232}
3ce0a23d 3233
d8f60cfc
AD		 3234/* r600 IV Ring
3235 * Each IV ring entry is 128 bits:
3236 * [7:0] - interrupt source id
3237 * [31:8] - reserved
3238 * [59:32] - interrupt source data
3239 * [127:60] - reserved
3240 *
3241 * The basic interrupt vector entries
3242 * are decoded as follows:
3243 * src_id src_data description
3244 * 1 0 D1 Vblank
3245 * 1 1 D1 Vline
3246 * 5 0 D2 Vblank
3247 * 5 1 D2 Vline
3248 * 19 0 FP Hot plug detection A
3249 * 19 1 FP Hot plug detection B
3250 * 19 2 DAC A auto-detection
3251 * 19 3 DAC B auto-detection
f2594933
CK		 3252 * 21 4 HDMI block A
3253 * 21 5 HDMI block B
d8f60cfc
AD		 3254 * 176 - CP_INT RB
3255 * 177 - CP_INT IB1
3256 * 178 - CP_INT IB2
3257 * 181 - EOP Interrupt
3258 * 233 - GUI Idle
3259 *
3260 * Note, these are based on r600 and may need to be
3261 * adjusted or added to on newer asics
3262 */
3263
3264int r600_irq_process(struct radeon_device *rdev)
3265{
3266 u32 wptr = r600_get_ih_wptr(rdev);
3267 u32 rptr = rdev->ih.rptr;
3268 u32 src_id, src_data;
6f34be50 3269 u32 ring_index;
d8f60cfc 3270 unsigned long flags;
d4877cf2 3271 bool queue_hotplug = false;
d8f60cfc
AD		 3272
3273 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
79c2bbc5
JG		 3274 if (!rdev->ih.enabled)
3275 return IRQ_NONE;
d8f60cfc
AD		 3276
3277 spin_lock_irqsave(&rdev->ih.lock, flags);
3278
3279 if (rptr == wptr) {
3280 spin_unlock_irqrestore(&rdev->ih.lock, flags);
3281 return IRQ_NONE;
3282 }
3283 if (rdev->shutdown) {
3284 spin_unlock_irqrestore(&rdev->ih.lock, flags);
3285 return IRQ_NONE;
3286 }
3287
3288restart_ih:
3289 /* display interrupts */
6f34be50 3290 r600_irq_ack(rdev);
d8f60cfc
AD		 3291
3292 rdev->ih.wptr = wptr;
3293 while (rptr != wptr) {
3294 /* wptr/rptr are in bytes! */
3295 ring_index = rptr / 4;
3296 src_id = rdev->ih.ring[ring_index] & 0xff;
3297 src_data = rdev->ih.ring[ring_index + 1] & 0xfffffff;
3298
3299 switch (src_id) {
3300 case 1: /* D1 vblank/vline */
3301 switch (src_data) {
3302 case 0: /* D1 vblank */
6f34be50 3303 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT) {
6f34be50
AD		 3304 if (rdev->irq.crtc_vblank_int[0]) {
3305 drm_handle_vblank(rdev->ddev, 0);
3306 rdev->pm.vblank_sync = true;
3307 wake_up(&rdev->irq.vblank_queue);
3308 }
3e4ea742
MK		 3309 if (rdev->irq.pflip[0])
3310 radeon_crtc_handle_flip(rdev, 0);
6f34be50 3311 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
d8f60cfc
AD		 3312 DRM_DEBUG("IH: D1 vblank\n");
3313 }
3314 break;
3315 case 1: /* D1 vline */
6f34be50
AD		 3316 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT) {
3317 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VLINE_INTERRUPT;
d8f60cfc
AD		 3318 DRM_DEBUG("IH: D1 vline\n");
3319 }
3320 break;
3321 default:
b042589c 3322 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
d8f60cfc
AD		 3323 break;
3324 }
3325 break;
3326 case 5: /* D2 vblank/vline */
3327 switch (src_data) {
3328 case 0: /* D2 vblank */
6f34be50 3329 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT) {
6f34be50
AD		 3330 if (rdev->irq.crtc_vblank_int[1]) {
3331 drm_handle_vblank(rdev->ddev, 1);
3332 rdev->pm.vblank_sync = true;
3333 wake_up(&rdev->irq.vblank_queue);
3334 }
3e4ea742
MK		 3335 if (rdev->irq.pflip[1])
3336 radeon_crtc_handle_flip(rdev, 1);
6f34be50 3337 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VBLANK_INTERRUPT;
d8f60cfc
AD		 3338 DRM_DEBUG("IH: D2 vblank\n");
3339 }
3340 break;
3341 case 1: /* D1 vline */
6f34be50
AD		 3342 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT) {
3343 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VLINE_INTERRUPT;
d8f60cfc
AD		 3344 DRM_DEBUG("IH: D2 vline\n");
3345 }
3346 break;
3347 default:
b042589c 3348 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
d8f60cfc
AD		 3349 break;
3350 }
3351 break;
e0df1ac5
AD		 3352 case 19: /* HPD/DAC hotplug */
3353 switch (src_data) {
3354 case 0:
6f34be50
AD		 3355 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) {
3356 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD1_INTERRUPT;
d4877cf2
AD		 3357 queue_hotplug = true;
3358 DRM_DEBUG("IH: HPD1\n");
e0df1ac5
AD		 3359 }
3360 break;
3361 case 1:
6f34be50
AD		 3362 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) {
3363 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD2_INTERRUPT;
d4877cf2
AD		 3364 queue_hotplug = true;
3365 DRM_DEBUG("IH: HPD2\n");
e0df1ac5
AD		 3366 }
3367 break;
3368 case 4:
6f34be50
AD		 3369 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) {
3370 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD3_INTERRUPT;
d4877cf2
AD		 3371 queue_hotplug = true;
3372 DRM_DEBUG("IH: HPD3\n");
e0df1ac5
AD		 3373 }
3374 break;
3375 case 5:
6f34be50
AD		 3376 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) {
3377 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD4_INTERRUPT;
d4877cf2
AD		 3378 queue_hotplug = true;
3379 DRM_DEBUG("IH: HPD4\n");
e0df1ac5
AD		 3380 }
3381 break;
3382 case 10:
6f34be50
AD		 3383 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) {
3384 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD5_INTERRUPT;
d4877cf2
AD		 3385 queue_hotplug = true;
3386 DRM_DEBUG("IH: HPD5\n");
e0df1ac5
AD		 3387 }
3388 break;
3389 case 12:
6f34be50
AD		 3390 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) {
3391 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD6_INTERRUPT;
d4877cf2
AD		 3392 queue_hotplug = true;
3393 DRM_DEBUG("IH: HPD6\n");
e0df1ac5
AD		 3394 }
3395 break;
3396 default:
b042589c 3397 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
e0df1ac5
AD		 3398 break;
3399 }
3400 break;
f2594933
CK		 3401 case 21: /* HDMI */
3402 DRM_DEBUG("IH: HDMI: 0x%x\n", src_data);
3403 r600_audio_schedule_polling(rdev);
3404 break;
d8f60cfc
AD		 3405 case 176: /* CP_INT in ring buffer */
3406 case 177: /* CP_INT in IB1 */
3407 case 178: /* CP_INT in IB2 */
3408 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
3409 radeon_fence_process(rdev);
3410 break;
3411 case 181: /* CP EOP event */
3412 DRM_DEBUG("IH: CP EOP\n");
d0f8a854 3413 radeon_fence_process(rdev);
d8f60cfc 3414 break;
2031f77c
AD		 3415 case 233: /* GUI IDLE */
3416 DRM_DEBUG("IH: CP EOP\n");
3417 rdev->pm.gui_idle = true;
3418 wake_up(&rdev->irq.idle_queue);
3419 break;
d8f60cfc 3420 default:
b042589c 3421 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
d8f60cfc
AD		 3422 break;
3423 }
3424
3425 /* wptr/rptr are in bytes! */
0c45249f
JG		 3426 rptr += 16;
3427 rptr &= rdev->ih.ptr_mask;
d8f60cfc
AD		 3428 }
3429 /* make sure wptr hasn't changed while processing */
3430 wptr = r600_get_ih_wptr(rdev);
3431 if (wptr != rdev->ih.wptr)
3432 goto restart_ih;
d4877cf2 3433 if (queue_hotplug)
32c87fca 3434 schedule_work(&rdev->hotplug_work);
d8f60cfc
AD		 3435 rdev->ih.rptr = rptr;
3436 WREG32(IH_RB_RPTR, rdev->ih.rptr);
3437 spin_unlock_irqrestore(&rdev->ih.lock, flags);
3438 return IRQ_HANDLED;
3439}
3ce0a23d
JG		 3440
3441/*
3442 * Debugfs info
3443 */
3444#if defined(CONFIG_DEBUG_FS)
3445
3446static int r600_debugfs_cp_ring_info(struct seq_file *m, void *data)
771fe6b9 3447{
3ce0a23d
JG		 3448 struct drm_info_node *node = (struct drm_info_node *) m->private;
3449 struct drm_device *dev = node->minor->dev;
3450 struct radeon_device *rdev = dev->dev_private;
3ce0a23d
JG		 3451 unsigned count, i, j;
3452
3453 radeon_ring_free_size(rdev);
d6840766 3454 count = (rdev->cp.ring_size / 4) - rdev->cp.ring_free_dw;
3ce0a23d 3455 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(CP_STAT));
d6840766
RM		 3456 seq_printf(m, "CP_RB_WPTR 0x%08x\n", RREG32(CP_RB_WPTR));
3457 seq_printf(m, "CP_RB_RPTR 0x%08x\n", RREG32(CP_RB_RPTR));
3458 seq_printf(m, "driver's copy of the CP_RB_WPTR 0x%08x\n", rdev->cp.wptr);
3459 seq_printf(m, "driver's copy of the CP_RB_RPTR 0x%08x\n", rdev->cp.rptr);
3ce0a23d
JG		 3460 seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
3461 seq_printf(m, "%u dwords in ring\n", count);
d6840766 3462 i = rdev->cp.rptr;
3ce0a23d 3463 for (j = 0; j <= count; j++) {
3ce0a23d 3464 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
d6840766 3465 i = (i + 1) & rdev->cp.ptr_mask;
3ce0a23d
JG		 3466 }
3467 return 0;
3468}
3469
3470static int r600_debugfs_mc_info(struct seq_file *m, void *data)
3471{
3472 struct drm_info_node *node = (struct drm_info_node *) m->private;
3473 struct drm_device *dev = node->minor->dev;
3474 struct radeon_device *rdev = dev->dev_private;
3475
3476 DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS);
3477 DREG32_SYS(m, rdev, VM_L2_STATUS);
3478 return 0;
3479}
3480
3481static struct drm_info_list r600_mc_info_list[] = {
3482 {"r600_mc_info", r600_debugfs_mc_info, 0, NULL},
3483 {"r600_ring_info", r600_debugfs_cp_ring_info, 0, NULL},
3484};
3485#endif
3486
3487int r600_debugfs_mc_info_init(struct radeon_device *rdev)
3488{
3489#if defined(CONFIG_DEBUG_FS)
3490 return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list));
3491#else
3492 return 0;
3493#endif
771fe6b9 3494}
062b389c
JG		 3495
3496/**
3497 * r600_ioctl_wait_idle - flush host path cache on wait idle ioctl
3498 * rdev: radeon device structure
3499 * bo: buffer object struct which userspace is waiting for idle
3500 *
3501 * Some R6XX/R7XX doesn't seems to take into account HDP flush performed
3502 * through ring buffer, this leads to corruption in rendering, see
3503 * http://bugzilla.kernel.org/show_bug.cgi?id=15186 to avoid this we
3504 * directly perform HDP flush by writing register through MMIO.
3505 */
3506void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo)
3507{
812d0469 3508 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read
f3886f85
AD		 3509 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL.
3510 * This seems to cause problems on some AGP cards. Just use the old
3511 * method for them.
812d0469 3512 */
e488459a 3513 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
f3886f85 3514 rdev->vram_scratch.ptr && !(rdev->flags & RADEON_IS_AGP)) {
87cbf8f2 3515 void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
812d0469
AD		 3516 u32 tmp;
3517
3518 WREG32(HDP_DEBUG1, 0);
3519 tmp = readl((void __iomem *)ptr);
3520 } else
3521 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
062b389c 3522}
3313e3d4
AD		 3523
3524void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes)
3525{
3526 u32 link_width_cntl, mask, target_reg;
3527
3528 if (rdev->flags & RADEON_IS_IGP)
3529 return;
3530
3531 if (!(rdev->flags & RADEON_IS_PCIE))
3532 return;
3533
3534 /* x2 cards have a special sequence */
3535 if (ASIC_IS_X2(rdev))
3536 return;
3537
3538 /* FIXME wait for idle */
3539
3540 switch (lanes) {
3541 case 0:
3542 mask = RADEON_PCIE_LC_LINK_WIDTH_X0;
3543 break;
3544 case 1:
3545 mask = RADEON_PCIE_LC_LINK_WIDTH_X1;
3546 break;
3547 case 2:
3548 mask = RADEON_PCIE_LC_LINK_WIDTH_X2;
3549 break;
3550 case 4:
3551 mask = RADEON_PCIE_LC_LINK_WIDTH_X4;
3552 break;
3553 case 8:
3554 mask = RADEON_PCIE_LC_LINK_WIDTH_X8;
3555 break;
3556 case 12:
3557 mask = RADEON_PCIE_LC_LINK_WIDTH_X12;
3558 break;
3559 case 16:
3560 default:
3561 mask = RADEON_PCIE_LC_LINK_WIDTH_X16;
3562 break;
3563 }
3564
3565 link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
3566
3567 if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) ==
3568 (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT))
3569 return;
3570
3571 if (link_width_cntl & R600_PCIE_LC_UPCONFIGURE_DIS)
3572 return;
3573
3574 link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK |
3575 RADEON_PCIE_LC_RECONFIG_NOW |
3576 R600_PCIE_LC_RENEGOTIATE_EN |
3577 R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE);
3578 link_width_cntl |= mask;
3579
3580 WREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3581
3582 /* some northbridges can renegotiate the link rather than requiring
3583 * a complete re-config.
3584 * e.g., AMD 780/790 northbridges (pci ids: 0x5956, 0x5957, 0x5958, etc.)
3585 */
3586 if (link_width_cntl & R600_PCIE_LC_RENEGOTIATION_SUPPORT)
3587 link_width_cntl |= R600_PCIE_LC_RENEGOTIATE_EN | R600_PCIE_LC_UPCONFIGURE_SUPPORT;
3588 else
3589 link_width_cntl |= R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE;
3590
3591 WREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl |
3592 RADEON_PCIE_LC_RECONFIG_NOW));
3593
3594 if (rdev->family >= CHIP_RV770)
3595 target_reg = R700_TARGET_AND_CURRENT_PROFILE_INDEX;
3596 else
3597 target_reg = R600_TARGET_AND_CURRENT_PROFILE_INDEX;
3598
3599 /* wait for lane set to complete */
3600 link_width_cntl = RREG32(target_reg);
3601 while (link_width_cntl == 0xffffffff)
3602 link_width_cntl = RREG32(target_reg);
3603
3604}
3605
3606int r600_get_pcie_lanes(struct radeon_device *rdev)
3607{
3608 u32 link_width_cntl;
3609
3610 if (rdev->flags & RADEON_IS_IGP)
3611 return 0;
3612
3613 if (!(rdev->flags & RADEON_IS_PCIE))
3614 return 0;
3615
3616 /* x2 cards have a special sequence */
3617 if (ASIC_IS_X2(rdev))
3618 return 0;
3619
3620 /* FIXME wait for idle */
3621
3622 link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
3623
3624 switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) {
3625 case RADEON_PCIE_LC_LINK_WIDTH_X0:
3626 return 0;
3627 case RADEON_PCIE_LC_LINK_WIDTH_X1:
3628 return 1;
3629 case RADEON_PCIE_LC_LINK_WIDTH_X2:
3630 return 2;
3631 case RADEON_PCIE_LC_LINK_WIDTH_X4:
3632 return 4;
3633 case RADEON_PCIE_LC_LINK_WIDTH_X8:
3634 return 8;
3635 case RADEON_PCIE_LC_LINK_WIDTH_X16:
3636 default:
3637 return 16;
3638 }
3639}
3640
9e46a48d
AD		 3641static void r600_pcie_gen2_enable(struct radeon_device *rdev)
3642{
3643 u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp;
3644 u16 link_cntl2;
3645
d42dd579
AD		 3646 if (radeon_pcie_gen2 == 0)
3647 return;
3648
9e46a48d
AD		 3649 if (rdev->flags & RADEON_IS_IGP)
3650 return;
3651
3652 if (!(rdev->flags & RADEON_IS_PCIE))
3653 return;
3654
3655 /* x2 cards have a special sequence */
3656 if (ASIC_IS_X2(rdev))
3657 return;
3658
3659 /* only RV6xx+ chips are supported */
3660 if (rdev->family <= CHIP_R600)
3661 return;
3662
3663 /* 55 nm r6xx asics */
3664 if ((rdev->family == CHIP_RV670) ||
3665 (rdev->family == CHIP_RV620) ||
3666 (rdev->family == CHIP_RV635)) {
3667 /* advertise upconfig capability */
3668 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3669 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3670 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3671 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3672 if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) {
3673 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT;
3674 link_width_cntl &= ~(LC_LINK_WIDTH_MASK |
3675 LC_RECONFIG_ARC_MISSING_ESCAPE);
3676 link_width_cntl |= lanes | LC_RECONFIG_NOW | LC_RENEGOTIATE_EN;
3677 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3678 } else {
3679 link_width_cntl |= LC_UPCONFIGURE_DIS;
3680 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3681 }
3682 }
3683
3684 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3685 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
3686 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
3687
3688 /* 55 nm r6xx asics */
3689 if ((rdev->family == CHIP_RV670) ||
3690 (rdev->family == CHIP_RV620) ||
3691 (rdev->family == CHIP_RV635)) {
3692 WREG32(MM_CFGREGS_CNTL, 0x8);
3693 link_cntl2 = RREG32(0x4088);
3694 WREG32(MM_CFGREGS_CNTL, 0);
3695 /* not supported yet */
3696 if (link_cntl2 & SELECTABLE_DEEMPHASIS)
3697 return;
3698 }
3699
3700 speed_cntl &= ~LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK;
3701 speed_cntl |= (0x3 << LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT);
3702 speed_cntl &= ~LC_VOLTAGE_TIMER_SEL_MASK;
3703 speed_cntl &= ~LC_FORCE_DIS_HW_SPEED_CHANGE;
3704 speed_cntl |= LC_FORCE_EN_HW_SPEED_CHANGE;
3705 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3706
3707 tmp = RREG32(0x541c);
3708 WREG32(0x541c, tmp | 0x8);
3709 WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN);
3710 link_cntl2 = RREG16(0x4088);
3711 link_cntl2 &= ~TARGET_LINK_SPEED_MASK;
3712 link_cntl2 |= 0x2;
3713 WREG16(0x4088, link_cntl2);
3714 WREG32(MM_CFGREGS_CNTL, 0);
3715
3716 if ((rdev->family == CHIP_RV670) ||
3717 (rdev->family == CHIP_RV620) ||
3718 (rdev->family == CHIP_RV635)) {
3719 training_cntl = RREG32_PCIE_P(PCIE_LC_TRAINING_CNTL);
3720 training_cntl &= ~LC_POINT_7_PLUS_EN;
3721 WREG32_PCIE_P(PCIE_LC_TRAINING_CNTL, training_cntl);
3722 } else {
3723 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3724 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
3725 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3726 }
3727
3728 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3729 speed_cntl |= LC_GEN2_EN_STRAP;
3730 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3731
3732 } else {
3733 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3734 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
3735 if (1)
3736 link_width_cntl |= LC_UPCONFIGURE_DIS;
3737 else
3738 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3739 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3740 }
3741}
Linux kernel - Deliverables
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