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drm/radeon/kms: fix bug in r600_gpu_is_lockup
[deliverable/linux.git] / drivers / gpu / drm / radeon / r600.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
5a0e3ad6 28#include <linux/slab.h>
3ce0a23d
JG		 29#include <linux/seq_file.h>
30#include <linux/firmware.h>
31#include <linux/platform_device.h>
771fe6b9 32#include "drmP.h"
3ce0a23d 33#include "radeon_drm.h"
771fe6b9 34#include "radeon.h"
e6990375 35#include "radeon_asic.h"
3ce0a23d 36#include "radeon_mode.h"
3ce0a23d 37#include "r600d.h"
3ce0a23d 38#include "atom.h"
d39c3b89 39#include "avivod.h"
771fe6b9 40
3ce0a23d
JG		 41#define PFP_UCODE_SIZE 576
42#define PM4_UCODE_SIZE 1792
d8f60cfc 43#define RLC_UCODE_SIZE 768
3ce0a23d
JG		 44#define R700_PFP_UCODE_SIZE 848
45#define R700_PM4_UCODE_SIZE 1360
d8f60cfc 46#define R700_RLC_UCODE_SIZE 1024
fe251e2f
AD		 47#define EVERGREEN_PFP_UCODE_SIZE 1120
48#define EVERGREEN_PM4_UCODE_SIZE 1376
45f9a39b 49#define EVERGREEN_RLC_UCODE_SIZE 768
3ce0a23d
JG		 50
51/* Firmware Names */
52MODULE_FIRMWARE("radeon/R600_pfp.bin");
53MODULE_FIRMWARE("radeon/R600_me.bin");
54MODULE_FIRMWARE("radeon/RV610_pfp.bin");
55MODULE_FIRMWARE("radeon/RV610_me.bin");
56MODULE_FIRMWARE("radeon/RV630_pfp.bin");
57MODULE_FIRMWARE("radeon/RV630_me.bin");
58MODULE_FIRMWARE("radeon/RV620_pfp.bin");
59MODULE_FIRMWARE("radeon/RV620_me.bin");
60MODULE_FIRMWARE("radeon/RV635_pfp.bin");
61MODULE_FIRMWARE("radeon/RV635_me.bin");
62MODULE_FIRMWARE("radeon/RV670_pfp.bin");
63MODULE_FIRMWARE("radeon/RV670_me.bin");
64MODULE_FIRMWARE("radeon/RS780_pfp.bin");
65MODULE_FIRMWARE("radeon/RS780_me.bin");
66MODULE_FIRMWARE("radeon/RV770_pfp.bin");
67MODULE_FIRMWARE("radeon/RV770_me.bin");
68MODULE_FIRMWARE("radeon/RV730_pfp.bin");
69MODULE_FIRMWARE("radeon/RV730_me.bin");
70MODULE_FIRMWARE("radeon/RV710_pfp.bin");
71MODULE_FIRMWARE("radeon/RV710_me.bin");
d8f60cfc
AD		 72MODULE_FIRMWARE("radeon/R600_rlc.bin");
73MODULE_FIRMWARE("radeon/R700_rlc.bin");
fe251e2f
AD		 74MODULE_FIRMWARE("radeon/CEDAR_pfp.bin");
75MODULE_FIRMWARE("radeon/CEDAR_me.bin");
45f9a39b 76MODULE_FIRMWARE("radeon/CEDAR_rlc.bin");
fe251e2f
AD		 77MODULE_FIRMWARE("radeon/REDWOOD_pfp.bin");
78MODULE_FIRMWARE("radeon/REDWOOD_me.bin");
45f9a39b 79MODULE_FIRMWARE("radeon/REDWOOD_rlc.bin");
fe251e2f
AD		 80MODULE_FIRMWARE("radeon/JUNIPER_pfp.bin");
81MODULE_FIRMWARE("radeon/JUNIPER_me.bin");
45f9a39b 82MODULE_FIRMWARE("radeon/JUNIPER_rlc.bin");
a7433742 83MODULE_FIRMWARE("radeon/CYPRESS_pfp.bin");
fe251e2f 84MODULE_FIRMWARE("radeon/CYPRESS_me.bin");
45f9a39b 85MODULE_FIRMWARE("radeon/CYPRESS_rlc.bin");
3ce0a23d
JG		 86
87int r600_debugfs_mc_info_init(struct radeon_device *rdev);
771fe6b9 88
1a029b76 89/* r600,rv610,rv630,rv620,rv635,rv670 */
771fe6b9
JG		 90int r600_mc_wait_for_idle(struct radeon_device *rdev);
91void r600_gpu_init(struct radeon_device *rdev);
3ce0a23d 92void r600_fini(struct radeon_device *rdev);
45f9a39b 93void r600_irq_disable(struct radeon_device *rdev);
771fe6b9 94
21a8122a
AD		 95/* get temperature in millidegrees */
96u32 rv6xx_get_temp(struct radeon_device *rdev)
97{
98 u32 temp = (RREG32(CG_THERMAL_STATUS) & ASIC_T_MASK) >>
99 ASIC_T_SHIFT;
21a8122a 100
b2298fd2 101 return temp * 1000;
21a8122a
AD		 102}
103
ce8f5370 104void r600_pm_get_dynpm_state(struct radeon_device *rdev)
a48b9b4e
AD		 105{
106 int i;
107
ce8f5370
AD		 108 rdev->pm.dynpm_can_upclock = true;
109 rdev->pm.dynpm_can_downclock = true;
a48b9b4e
AD		 110
111 /* power state array is low to high, default is first */
112 if ((rdev->flags & RADEON_IS_IGP) || (rdev->family == CHIP_R600)) {
113 int min_power_state_index = 0;
114
115 if (rdev->pm.num_power_states > 2)
116 min_power_state_index = 1;
117
ce8f5370
AD		 118 switch (rdev->pm.dynpm_planned_action) {
119 case DYNPM_ACTION_MINIMUM:
a48b9b4e
AD		 120 rdev->pm.requested_power_state_index = min_power_state_index;
121 rdev->pm.requested_clock_mode_index = 0;
ce8f5370 122 rdev->pm.dynpm_can_downclock = false;
a48b9b4e 123 break;
ce8f5370 124 case DYNPM_ACTION_DOWNCLOCK:
a48b9b4e
AD		 125 if (rdev->pm.current_power_state_index == min_power_state_index) {
126 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
ce8f5370 127 rdev->pm.dynpm_can_downclock = false;
a48b9b4e
AD		 128 } else {
129 if (rdev->pm.active_crtc_count > 1) {
130 for (i = 0; i < rdev->pm.num_power_states; i++) {
d7311171 131 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
a48b9b4e
AD		 132 continue;
133 else if (i >= rdev->pm.current_power_state_index) {
134 rdev->pm.requested_power_state_index =
135 rdev->pm.current_power_state_index;
136 break;
137 } else {
138 rdev->pm.requested_power_state_index = i;
139 break;
140 }
141 }
773c3fa3
AD		 142 } else {
143 if (rdev->pm.current_power_state_index == 0)
144 rdev->pm.requested_power_state_index =
145 rdev->pm.num_power_states - 1;
146 else
147 rdev->pm.requested_power_state_index =
148 rdev->pm.current_power_state_index - 1;
149 }
a48b9b4e
AD		 150 }
151 rdev->pm.requested_clock_mode_index = 0;
d7311171
AD		 152 /* don't use the power state if crtcs are active and no display flag is set */
153 if ((rdev->pm.active_crtc_count > 0) &&
154 (rdev->pm.power_state[rdev->pm.requested_power_state_index].
155 clock_info[rdev->pm.requested_clock_mode_index].flags &
156 RADEON_PM_MODE_NO_DISPLAY)) {
157 rdev->pm.requested_power_state_index++;
158 }
a48b9b4e 159 break;
ce8f5370 160 case DYNPM_ACTION_UPCLOCK:
a48b9b4e
AD		 161 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
162 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
ce8f5370 163 rdev->pm.dynpm_can_upclock = false;
a48b9b4e
AD		 164 } else {
165 if (rdev->pm.active_crtc_count > 1) {
166 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
d7311171 167 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
a48b9b4e
AD		 168 continue;
169 else if (i <= rdev->pm.current_power_state_index) {
170 rdev->pm.requested_power_state_index =
171 rdev->pm.current_power_state_index;
172 break;
173 } else {
174 rdev->pm.requested_power_state_index = i;
175 break;
176 }
177 }
178 } else
179 rdev->pm.requested_power_state_index =
180 rdev->pm.current_power_state_index + 1;
181 }
182 rdev->pm.requested_clock_mode_index = 0;
183 break;
ce8f5370 184 case DYNPM_ACTION_DEFAULT:
58e21dff
AD		 185 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
186 rdev->pm.requested_clock_mode_index = 0;
ce8f5370 187 rdev->pm.dynpm_can_upclock = false;
58e21dff 188 break;
ce8f5370 189 case DYNPM_ACTION_NONE:
a48b9b4e
AD		 190 default:
191 DRM_ERROR("Requested mode for not defined action\n");
192 return;
193 }
194 } else {
195 /* XXX select a power state based on AC/DC, single/dualhead, etc. */
196 /* for now just select the first power state and switch between clock modes */
197 /* power state array is low to high, default is first (0) */
198 if (rdev->pm.active_crtc_count > 1) {
199 rdev->pm.requested_power_state_index = -1;
200 /* start at 1 as we don't want the default mode */
201 for (i = 1; i < rdev->pm.num_power_states; i++) {
d7311171 202 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
a48b9b4e
AD		 203 continue;
204 else if ((rdev->pm.power_state[i].type == POWER_STATE_TYPE_PERFORMANCE) ||
205 (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY)) {
206 rdev->pm.requested_power_state_index = i;
207 break;
208 }
209 }
210 /* if nothing selected, grab the default state. */
211 if (rdev->pm.requested_power_state_index == -1)
212 rdev->pm.requested_power_state_index = 0;
213 } else
214 rdev->pm.requested_power_state_index = 1;
215
ce8f5370
AD		 216 switch (rdev->pm.dynpm_planned_action) {
217 case DYNPM_ACTION_MINIMUM:
a48b9b4e 218 rdev->pm.requested_clock_mode_index = 0;
ce8f5370 219 rdev->pm.dynpm_can_downclock = false;
a48b9b4e 220 break;
ce8f5370 221 case DYNPM_ACTION_DOWNCLOCK:
a48b9b4e
AD		 222 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
223 if (rdev->pm.current_clock_mode_index == 0) {
224 rdev->pm.requested_clock_mode_index = 0;
ce8f5370 225 rdev->pm.dynpm_can_downclock = false;
a48b9b4e
AD		 226 } else
227 rdev->pm.requested_clock_mode_index =
228 rdev->pm.current_clock_mode_index - 1;
229 } else {
230 rdev->pm.requested_clock_mode_index = 0;
ce8f5370 231 rdev->pm.dynpm_can_downclock = false;
a48b9b4e 232 }
d7311171
AD		 233 /* don't use the power state if crtcs are active and no display flag is set */
234 if ((rdev->pm.active_crtc_count > 0) &&
235 (rdev->pm.power_state[rdev->pm.requested_power_state_index].
236 clock_info[rdev->pm.requested_clock_mode_index].flags &
237 RADEON_PM_MODE_NO_DISPLAY)) {
238 rdev->pm.requested_clock_mode_index++;
239 }
a48b9b4e 240 break;
ce8f5370 241 case DYNPM_ACTION_UPCLOCK:
a48b9b4e
AD		 242 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
243 if (rdev->pm.current_clock_mode_index ==
244 (rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1)) {
245 rdev->pm.requested_clock_mode_index = rdev->pm.current_clock_mode_index;
ce8f5370 246 rdev->pm.dynpm_can_upclock = false;
a48b9b4e
AD		 247 } else
248 rdev->pm.requested_clock_mode_index =
249 rdev->pm.current_clock_mode_index + 1;
250 } else {
251 rdev->pm.requested_clock_mode_index =
252 rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1;
ce8f5370 253 rdev->pm.dynpm_can_upclock = false;
a48b9b4e
AD		 254 }
255 break;
ce8f5370 256 case DYNPM_ACTION_DEFAULT:
58e21dff
AD		 257 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
258 rdev->pm.requested_clock_mode_index = 0;
ce8f5370 259 rdev->pm.dynpm_can_upclock = false;
58e21dff 260 break;
ce8f5370 261 case DYNPM_ACTION_NONE:
a48b9b4e
AD		 262 default:
263 DRM_ERROR("Requested mode for not defined action\n");
264 return;
265 }
266 }
267
d9fdaafb 268 DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
ce8a3eb2
AD		 269 rdev->pm.power_state[rdev->pm.requested_power_state_index].
270 clock_info[rdev->pm.requested_clock_mode_index].sclk,
271 rdev->pm.power_state[rdev->pm.requested_power_state_index].
272 clock_info[rdev->pm.requested_clock_mode_index].mclk,
273 rdev->pm.power_state[rdev->pm.requested_power_state_index].
274 pcie_lanes);
a48b9b4e
AD		 275}
276
ce8f5370
AD		 277static int r600_pm_get_type_index(struct radeon_device *rdev,
278 enum radeon_pm_state_type ps_type,
279 int instance)
bae6b562 280{
ce8f5370
AD		 281 int i;
282 int found_instance = -1;
bae6b562 283
ce8f5370
AD		 284 for (i = 0; i < rdev->pm.num_power_states; i++) {
285 if (rdev->pm.power_state[i].type == ps_type) {
286 found_instance++;
287 if (found_instance == instance)
288 return i;
a424816f 289 }
ce8f5370
AD		 290 }
291 /* return default if no match */
292 return rdev->pm.default_power_state_index;
293}
294
295void rs780_pm_init_profile(struct radeon_device *rdev)
296{
297 if (rdev->pm.num_power_states == 2) {
298 /* default */
299 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
300 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
301 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
302 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
303 /* low sh */
304 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
305 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
306 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
307 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 308 /* mid sh */
309 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
310 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
311 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
312 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 313 /* high sh */
314 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
315 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
316 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
317 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
318 /* low mh */
319 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
320 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
321 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
322 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 323 /* mid mh */
324 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
325 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
326 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
327 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 328 /* high mh */
329 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
330 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 1;
331 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
332 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
333 } else if (rdev->pm.num_power_states == 3) {
334 /* default */
335 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
336 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
337 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
338 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
339 /* low sh */
340 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
341 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
342 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
343 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 344 /* mid sh */
345 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
346 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
347 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
348 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 349 /* high sh */
350 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
351 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 2;
352 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
353 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
354 /* low mh */
355 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 1;
356 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 1;
357 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
358 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 359 /* mid mh */
360 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 1;
361 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 1;
362 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
363 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 364 /* high mh */
365 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 1;
366 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
367 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
368 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
369 } else {
370 /* default */
371 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
372 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
373 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
374 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
375 /* low sh */
376 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 2;
377 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 2;
378 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
379 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 380 /* mid sh */
381 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 2;
382 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 2;
383 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
384 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 385 /* high sh */
386 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 2;
387 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 3;
388 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
389 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
390 /* low mh */
391 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
392 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
393 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
394 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 395 /* mid mh */
396 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
397 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
398 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
399 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 400 /* high mh */
401 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
402 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 3;
403 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
404 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
405 }
406}
bae6b562 407
ce8f5370
AD		 408void r600_pm_init_profile(struct radeon_device *rdev)
409{
410 if (rdev->family == CHIP_R600) {
411 /* XXX */
412 /* default */
413 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
414 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
415 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
4bff5171 416 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 417 /* low sh */
418 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
419 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
420 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
4bff5171 421 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 422 /* mid sh */
423 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
424 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
425 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
426 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 427 /* high sh */
428 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
429 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
430 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
4bff5171 431 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 432 /* low mh */
433 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
434 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
435 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
4bff5171 436 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 437 /* mid mh */
438 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
439 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
440 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
441 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 442 /* high mh */
443 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
444 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
445 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
4bff5171 446 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 447 } else {
448 if (rdev->pm.num_power_states < 4) {
449 /* default */
450 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
451 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
452 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
453 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
454 /* low sh */
4bff5171
AD		 455 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
456 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
ce8f5370 457 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
c9e75b21
AD		 458 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
459 /* mid sh */
460 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
461 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
462 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
463 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
ce8f5370 464 /* high sh */
4bff5171
AD		 465 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
466 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
ce8f5370
AD		 467 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
468 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
469 /* low mh */
4bff5171
AD		 470 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
471 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 2;
ce8f5370 472 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
c9e75b21
AD		 473 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
474 /* low mh */
475 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
476 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 2;
477 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
478 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
ce8f5370 479 /* high mh */
4bff5171
AD		 480 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
481 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
ce8f5370
AD		 482 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
483 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
484 } else {
485 /* default */
486 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
487 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
488 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
489 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
490 /* low sh */
4bff5171
AD		 491 if (rdev->flags & RADEON_IS_MOBILITY) {
492 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx =
493 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
494 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx =
495 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
496 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
c9e75b21 497 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
4bff5171
AD		 498 } else {
499 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx =
500 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
501 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx =
502 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
503 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
c9e75b21
AD		 504 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
505 }
506 /* mid sh */
507 if (rdev->flags & RADEON_IS_MOBILITY) {
508 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx =
509 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
510 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx =
511 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
512 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
513 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
514 } else {
515 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx =
516 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
517 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx =
518 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
519 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
520 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
4bff5171 521 }
ce8f5370 522 /* high sh */
4bff5171
AD		 523 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx =
524 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
525 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx =
526 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
ce8f5370
AD		 527 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
528 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
529 /* low mh */
4bff5171
AD		 530 if (rdev->flags & RADEON_IS_MOBILITY) {
531 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx =
532 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
533 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx =
534 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
535 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
c9e75b21 536 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
4bff5171
AD		 537 } else {
538 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx =
539 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
540 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx =
541 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
542 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
c9e75b21
AD		 543 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
544 }
545 /* mid mh */
546 if (rdev->flags & RADEON_IS_MOBILITY) {
547 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx =
548 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
549 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx =
550 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
551 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
552 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
553 } else {
554 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx =
555 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
556 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx =
557 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
558 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
559 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
4bff5171 560 }
ce8f5370 561 /* high mh */
4bff5171
AD		 562 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx =
563 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
564 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx =
565 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
ce8f5370
AD		 566 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
567 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
568 }
569 }
bae6b562
AD		 570}
571
49e02b73
AD		 572void r600_pm_misc(struct radeon_device *rdev)
573{
a081a9d6
RM		 574 int req_ps_idx = rdev->pm.requested_power_state_index;
575 int req_cm_idx = rdev->pm.requested_clock_mode_index;
576 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
577 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
7ac9aa5a 578
4d60173f
AD		 579 if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
580 if (voltage->voltage != rdev->pm.current_vddc) {
581 radeon_atom_set_voltage(rdev, voltage->voltage);
582 rdev->pm.current_vddc = voltage->voltage;
d9fdaafb 583 DRM_DEBUG_DRIVER("Setting: v: %d\n", voltage->voltage);
4d60173f
AD		 584 }
585 }
49e02b73
AD		 586}
587
def9ba9c
AD		 588bool r600_gui_idle(struct radeon_device *rdev)
589{
590 if (RREG32(GRBM_STATUS) & GUI_ACTIVE)
591 return false;
592 else
593 return true;
594}
595
e0df1ac5
AD		 596/* hpd for digital panel detect/disconnect */
597bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
598{
599 bool connected = false;
600
601 if (ASIC_IS_DCE3(rdev)) {
602 switch (hpd) {
603 case RADEON_HPD_1:
604 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
605 connected = true;
606 break;
607 case RADEON_HPD_2:
608 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
609 connected = true;
610 break;
611 case RADEON_HPD_3:
612 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
613 connected = true;
614 break;
615 case RADEON_HPD_4:
616 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
617 connected = true;
618 break;
619 /* DCE 3.2 */
620 case RADEON_HPD_5:
621 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
622 connected = true;
623 break;
624 case RADEON_HPD_6:
625 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
626 connected = true;
627 break;
628 default:
629 break;
630 }
631 } else {
632 switch (hpd) {
633 case RADEON_HPD_1:
634 if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
635 connected = true;
636 break;
637 case RADEON_HPD_2:
638 if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
639 connected = true;
640 break;
641 case RADEON_HPD_3:
642 if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
643 connected = true;
644 break;
645 default:
646 break;
647 }
648 }
649 return connected;
650}
651
652void r600_hpd_set_polarity(struct radeon_device *rdev,
429770b3 653 enum radeon_hpd_id hpd)
e0df1ac5
AD		 654{
655 u32 tmp;
656 bool connected = r600_hpd_sense(rdev, hpd);
657
658 if (ASIC_IS_DCE3(rdev)) {
659 switch (hpd) {
660 case RADEON_HPD_1:
661 tmp = RREG32(DC_HPD1_INT_CONTROL);
662 if (connected)
663 tmp &= ~DC_HPDx_INT_POLARITY;
664 else
665 tmp |= DC_HPDx_INT_POLARITY;
666 WREG32(DC_HPD1_INT_CONTROL, tmp);
667 break;
668 case RADEON_HPD_2:
669 tmp = RREG32(DC_HPD2_INT_CONTROL);
670 if (connected)
671 tmp &= ~DC_HPDx_INT_POLARITY;
672 else
673 tmp |= DC_HPDx_INT_POLARITY;
674 WREG32(DC_HPD2_INT_CONTROL, tmp);
675 break;
676 case RADEON_HPD_3:
677 tmp = RREG32(DC_HPD3_INT_CONTROL);
678 if (connected)
679 tmp &= ~DC_HPDx_INT_POLARITY;
680 else
681 tmp |= DC_HPDx_INT_POLARITY;
682 WREG32(DC_HPD3_INT_CONTROL, tmp);
683 break;
684 case RADEON_HPD_4:
685 tmp = RREG32(DC_HPD4_INT_CONTROL);
686 if (connected)
687 tmp &= ~DC_HPDx_INT_POLARITY;
688 else
689 tmp |= DC_HPDx_INT_POLARITY;
690 WREG32(DC_HPD4_INT_CONTROL, tmp);
691 break;
692 case RADEON_HPD_5:
693 tmp = RREG32(DC_HPD5_INT_CONTROL);
694 if (connected)
695 tmp &= ~DC_HPDx_INT_POLARITY;
696 else
697 tmp |= DC_HPDx_INT_POLARITY;
698 WREG32(DC_HPD5_INT_CONTROL, tmp);
699 break;
700 /* DCE 3.2 */
701 case RADEON_HPD_6:
702 tmp = RREG32(DC_HPD6_INT_CONTROL);
703 if (connected)
704 tmp &= ~DC_HPDx_INT_POLARITY;
705 else
706 tmp |= DC_HPDx_INT_POLARITY;
707 WREG32(DC_HPD6_INT_CONTROL, tmp);
708 break;
709 default:
710 break;
711 }
712 } else {
713 switch (hpd) {
714 case RADEON_HPD_1:
715 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
716 if (connected)
717 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
718 else
719 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
720 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
721 break;
722 case RADEON_HPD_2:
723 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
724 if (connected)
725 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
726 else
727 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
728 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
729 break;
730 case RADEON_HPD_3:
731 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
732 if (connected)
733 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
734 else
735 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
736 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
737 break;
738 default:
739 break;
740 }
741 }
742}
743
744void r600_hpd_init(struct radeon_device *rdev)
745{
746 struct drm_device *dev = rdev->ddev;
747 struct drm_connector *connector;
748
749 if (ASIC_IS_DCE3(rdev)) {
750 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa);
751 if (ASIC_IS_DCE32(rdev))
752 tmp |= DC_HPDx_EN;
753
754 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
755 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
756 switch (radeon_connector->hpd.hpd) {
757 case RADEON_HPD_1:
758 WREG32(DC_HPD1_CONTROL, tmp);
759 rdev->irq.hpd[0] = true;
760 break;
761 case RADEON_HPD_2:
762 WREG32(DC_HPD2_CONTROL, tmp);
763 rdev->irq.hpd[1] = true;
764 break;
765 case RADEON_HPD_3:
766 WREG32(DC_HPD3_CONTROL, tmp);
767 rdev->irq.hpd[2] = true;
768 break;
769 case RADEON_HPD_4:
770 WREG32(DC_HPD4_CONTROL, tmp);
771 rdev->irq.hpd[3] = true;
772 break;
773 /* DCE 3.2 */
774 case RADEON_HPD_5:
775 WREG32(DC_HPD5_CONTROL, tmp);
776 rdev->irq.hpd[4] = true;
777 break;
778 case RADEON_HPD_6:
779 WREG32(DC_HPD6_CONTROL, tmp);
780 rdev->irq.hpd[5] = true;
781 break;
782 default:
783 break;
784 }
785 }
786 } else {
787 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
788 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
789 switch (radeon_connector->hpd.hpd) {
790 case RADEON_HPD_1:
791 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN);
792 rdev->irq.hpd[0] = true;
793 break;
794 case RADEON_HPD_2:
795 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN);
796 rdev->irq.hpd[1] = true;
797 break;
798 case RADEON_HPD_3:
799 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN);
800 rdev->irq.hpd[2] = true;
801 break;
802 default:
803 break;
804 }
805 }
806 }
003e69f9
JG		 807 if (rdev->irq.installed)
808 r600_irq_set(rdev);
e0df1ac5
AD		 809}
810
811void r600_hpd_fini(struct radeon_device *rdev)
812{
813 struct drm_device *dev = rdev->ddev;
814 struct drm_connector *connector;
815
816 if (ASIC_IS_DCE3(rdev)) {
817 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
818 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
819 switch (radeon_connector->hpd.hpd) {
820 case RADEON_HPD_1:
821 WREG32(DC_HPD1_CONTROL, 0);
822 rdev->irq.hpd[0] = false;
823 break;
824 case RADEON_HPD_2:
825 WREG32(DC_HPD2_CONTROL, 0);
826 rdev->irq.hpd[1] = false;
827 break;
828 case RADEON_HPD_3:
829 WREG32(DC_HPD3_CONTROL, 0);
830 rdev->irq.hpd[2] = false;
831 break;
832 case RADEON_HPD_4:
833 WREG32(DC_HPD4_CONTROL, 0);
834 rdev->irq.hpd[3] = false;
835 break;
836 /* DCE 3.2 */
837 case RADEON_HPD_5:
838 WREG32(DC_HPD5_CONTROL, 0);
839 rdev->irq.hpd[4] = false;
840 break;
841 case RADEON_HPD_6:
842 WREG32(DC_HPD6_CONTROL, 0);
843 rdev->irq.hpd[5] = false;
844 break;
845 default:
846 break;
847 }
848 }
849 } else {
850 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
851 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
852 switch (radeon_connector->hpd.hpd) {
853 case RADEON_HPD_1:
854 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0);
855 rdev->irq.hpd[0] = false;
856 break;
857 case RADEON_HPD_2:
858 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0);
859 rdev->irq.hpd[1] = false;
860 break;
861 case RADEON_HPD_3:
862 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0);
863 rdev->irq.hpd[2] = false;
864 break;
865 default:
866 break;
867 }
868 }
869 }
870}
871
771fe6b9 872/*
3ce0a23d 873 * R600 PCIE GART
771fe6b9 874 */
3ce0a23d
JG		 875void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
876{
877 unsigned i;
878 u32 tmp;
879
2e98f10a 880 /* flush hdp cache so updates hit vram */
f3886f85
AD		 881 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
882 !(rdev->flags & RADEON_IS_AGP)) {
812d0469
AD		 883 void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
884 u32 tmp;
885
886 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read
887 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL
f3886f85
AD		 888 * This seems to cause problems on some AGP cards. Just use the old
889 * method for them.
812d0469
AD		 890 */
891 WREG32(HDP_DEBUG1, 0);
892 tmp = readl((void __iomem *)ptr);
893 } else
894 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
2e98f10a 895
3ce0a23d
JG		 896 WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
897 WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
898 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
899 for (i = 0; i < rdev->usec_timeout; i++) {
900 /* read MC_STATUS */
901 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
902 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
903 if (tmp == 2) {
904 printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
905 return;
906 }
907 if (tmp) {
908 return;
909 }
910 udelay(1);
911 }
912}
913
4aac0473 914int r600_pcie_gart_init(struct radeon_device *rdev)
3ce0a23d 915{
4aac0473 916 int r;
3ce0a23d 917
4aac0473 918 if (rdev->gart.table.vram.robj) {
fce7d61b 919 WARN(1, "R600 PCIE GART already initialized\n");
4aac0473
JG		 920 return 0;
921 }
3ce0a23d
JG		 922 /* Initialize common gart structure */
923 r = radeon_gart_init(rdev);
4aac0473 924 if (r)
3ce0a23d 925 return r;
3ce0a23d 926 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
4aac0473
JG		 927 return radeon_gart_table_vram_alloc(rdev);
928}
929
930int r600_pcie_gart_enable(struct radeon_device *rdev)
931{
932 u32 tmp;
933 int r, i;
934
935 if (rdev->gart.table.vram.robj == NULL) {
936 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
937 return -EINVAL;
771fe6b9 938 }
4aac0473
JG		 939 r = radeon_gart_table_vram_pin(rdev);
940 if (r)
941 return r;
82568565 942 radeon_gart_restore(rdev);
bc1a631e 943
3ce0a23d
JG		 944 /* Setup L2 cache */
945 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
946 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
947 EFFECTIVE_L2_QUEUE_SIZE(7));
948 WREG32(VM_L2_CNTL2, 0);
949 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
950 /* Setup TLB control */
951 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
952 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
953 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
954 ENABLE_WAIT_L2_QUERY;
955 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
956 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
957 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
958 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
959 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
960 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
961 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
962 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
963 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
964 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
965 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
966 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
967 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
968 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
969 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
1a029b76 970 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
3ce0a23d
JG		 971 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
972 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
973 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
974 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
975 (u32)(rdev->dummy_page.addr >> 12));
976 for (i = 1; i < 7; i++)
977 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
771fe6b9 978
3ce0a23d
JG		 979 r600_pcie_gart_tlb_flush(rdev);
980 rdev->gart.ready = true;
771fe6b9
JG		 981 return 0;
982}
983
3ce0a23d 984void r600_pcie_gart_disable(struct radeon_device *rdev)
771fe6b9 985{
3ce0a23d 986 u32 tmp;
4c788679 987 int i, r;
771fe6b9 988
3ce0a23d
JG		 989 /* Disable all tables */
990 for (i = 0; i < 7; i++)
991 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
771fe6b9 992
3ce0a23d
JG		 993 /* Disable L2 cache */
994 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
995 EFFECTIVE_L2_QUEUE_SIZE(7));
996 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
997 /* Setup L1 TLB control */
998 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
999 ENABLE_WAIT_L2_QUERY;
1000 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
1001 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
1002 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
1003 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
1004 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
1005 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
1006 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
1007 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
1008 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp);
1009 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp);
1010 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
1011 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
1012 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
1013 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
4aac0473 1014 if (rdev->gart.table.vram.robj) {
4c788679
JG		 1015 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
1016 if (likely(r == 0)) {
1017 radeon_bo_kunmap(rdev->gart.table.vram.robj);
1018 radeon_bo_unpin(rdev->gart.table.vram.robj);
1019 radeon_bo_unreserve(rdev->gart.table.vram.robj);
1020 }
4aac0473
JG		 1021 }
1022}
1023
1024void r600_pcie_gart_fini(struct radeon_device *rdev)
1025{
f9274562 1026 radeon_gart_fini(rdev);
4aac0473
JG		 1027 r600_pcie_gart_disable(rdev);
1028 radeon_gart_table_vram_free(rdev);
771fe6b9
JG		 1029}
1030
1a029b76
JG		 1031void r600_agp_enable(struct radeon_device *rdev)
1032{
1033 u32 tmp;
1034 int i;
1035
1036 /* Setup L2 cache */
1037 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
1038 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1039 EFFECTIVE_L2_QUEUE_SIZE(7));
1040 WREG32(VM_L2_CNTL2, 0);
1041 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
1042 /* Setup TLB control */
1043 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1044 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1045 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
1046 ENABLE_WAIT_L2_QUERY;
1047 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
1048 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
1049 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
1050 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
1051 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
1052 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
1053 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
1054 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
1055 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
1056 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
1057 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
1058 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
1059 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1060 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1061 for (i = 0; i < 7; i++)
1062 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
1063}
1064
771fe6b9
JG		 1065int r600_mc_wait_for_idle(struct radeon_device *rdev)
1066{
3ce0a23d
JG		 1067 unsigned i;
1068 u32 tmp;
1069
1070 for (i = 0; i < rdev->usec_timeout; i++) {
1071 /* read MC_STATUS */
1072 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00;
1073 if (!tmp)
1074 return 0;
1075 udelay(1);
1076 }
1077 return -1;
771fe6b9
JG		 1078}
1079
a3c1945a 1080static void r600_mc_program(struct radeon_device *rdev)
771fe6b9 1081{
a3c1945a 1082 struct rv515_mc_save save;
3ce0a23d
JG		 1083 u32 tmp;
1084 int i, j;
771fe6b9 1085
3ce0a23d
JG		 1086 /* Initialize HDP */
1087 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1088 WREG32((0x2c14 + j), 0x00000000);
1089 WREG32((0x2c18 + j), 0x00000000);
1090 WREG32((0x2c1c + j), 0x00000000);
1091 WREG32((0x2c20 + j), 0x00000000);
1092 WREG32((0x2c24 + j), 0x00000000);
1093 }
1094 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
771fe6b9 1095
a3c1945a 1096 rv515_mc_stop(rdev, &save);
3ce0a23d 1097 if (r600_mc_wait_for_idle(rdev)) {
a3c1945a 1098 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
3ce0a23d 1099 }
a3c1945a 1100 /* Lockout access through VGA aperture (doesn't exist before R600) */
3ce0a23d 1101 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
3ce0a23d 1102 /* Update configuration */
1a029b76
JG		 1103 if (rdev->flags & RADEON_IS_AGP) {
1104 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1105 /* VRAM before AGP */
1106 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1107 rdev->mc.vram_start >> 12);
1108 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1109 rdev->mc.gtt_end >> 12);
1110 } else {
1111 /* VRAM after AGP */
1112 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1113 rdev->mc.gtt_start >> 12);
1114 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1115 rdev->mc.vram_end >> 12);
1116 }
1117 } else {
1118 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
1119 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12);
1120 }
3ce0a23d 1121 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
1a029b76 1122 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
3ce0a23d
JG		 1123 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1124 WREG32(MC_VM_FB_LOCATION, tmp);
1125 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1126 WREG32(HDP_NONSURFACE_INFO, (2 << 7));
46fcd2b3 1127 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
3ce0a23d 1128 if (rdev->flags & RADEON_IS_AGP) {
1a029b76
JG		 1129 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22);
1130 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22);
3ce0a23d
JG		 1131 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1132 } else {
1133 WREG32(MC_VM_AGP_BASE, 0);
1134 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1135 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1136 }
3ce0a23d 1137 if (r600_mc_wait_for_idle(rdev)) {
a3c1945a 1138 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
3ce0a23d 1139 }
a3c1945a 1140 rv515_mc_resume(rdev, &save);
698443d9
DA		 1141 /* we need to own VRAM, so turn off the VGA renderer here
1142 * to stop it overwriting our objects */
d39c3b89 1143 rv515_vga_render_disable(rdev);
3ce0a23d
JG		 1144}
1145
d594e46a
JG		 1146/**
1147 * r600_vram_gtt_location - try to find VRAM & GTT location
1148 * @rdev: radeon device structure holding all necessary informations
1149 * @mc: memory controller structure holding memory informations
1150 *
1151 * Function will place try to place VRAM at same place as in CPU (PCI)
1152 * address space as some GPU seems to have issue when we reprogram at
1153 * different address space.
1154 *
1155 * If there is not enough space to fit the unvisible VRAM after the
1156 * aperture then we limit the VRAM size to the aperture.
1157 *
1158 * If we are using AGP then place VRAM adjacent to AGP aperture are we need
1159 * them to be in one from GPU point of view so that we can program GPU to
1160 * catch access outside them (weird GPU policy see ??).
1161 *
1162 * This function will never fails, worst case are limiting VRAM or GTT.
1163 *
1164 * Note: GTT start, end, size should be initialized before calling this
1165 * function on AGP platform.
1166 */
1167void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
1168{
1169 u64 size_bf, size_af;
1170
1171 if (mc->mc_vram_size > 0xE0000000) {
1172 /* leave room for at least 512M GTT */
1173 dev_warn(rdev->dev, "limiting VRAM\n");
1174 mc->real_vram_size = 0xE0000000;
1175 mc->mc_vram_size = 0xE0000000;
1176 }
1177 if (rdev->flags & RADEON_IS_AGP) {
1178 size_bf = mc->gtt_start;
1179 size_af = 0xFFFFFFFF - mc->gtt_end + 1;
1180 if (size_bf > size_af) {
1181 if (mc->mc_vram_size > size_bf) {
1182 dev_warn(rdev->dev, "limiting VRAM\n");
1183 mc->real_vram_size = size_bf;
1184 mc->mc_vram_size = size_bf;
1185 }
1186 mc->vram_start = mc->gtt_start - mc->mc_vram_size;
1187 } else {
1188 if (mc->mc_vram_size > size_af) {
1189 dev_warn(rdev->dev, "limiting VRAM\n");
1190 mc->real_vram_size = size_af;
1191 mc->mc_vram_size = size_af;
1192 }
1193 mc->vram_start = mc->gtt_end;
1194 }
1195 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
1196 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
1197 mc->mc_vram_size >> 20, mc->vram_start,
1198 mc->vram_end, mc->real_vram_size >> 20);
1199 } else {
1200 u64 base = 0;
8961d52d
AD		 1201 if (rdev->flags & RADEON_IS_IGP) {
1202 base = RREG32(MC_VM_FB_LOCATION) & 0xFFFF;
1203 base <<= 24;
1204 }
d594e46a 1205 radeon_vram_location(rdev, &rdev->mc, base);
8d369bb1 1206 rdev->mc.gtt_base_align = 0;
d594e46a
JG		 1207 radeon_gtt_location(rdev, mc);
1208 }
1209}
1210
3ce0a23d 1211int r600_mc_init(struct radeon_device *rdev)
771fe6b9 1212{
3ce0a23d 1213 u32 tmp;
5885b7a9 1214 int chansize, numchan;
771fe6b9 1215
3ce0a23d 1216 /* Get VRAM informations */
771fe6b9 1217 rdev->mc.vram_is_ddr = true;
3ce0a23d
JG		 1218 tmp = RREG32(RAMCFG);
1219 if (tmp & CHANSIZE_OVERRIDE) {
771fe6b9 1220 chansize = 16;
3ce0a23d 1221 } else if (tmp & CHANSIZE_MASK) {
771fe6b9
JG		 1222 chansize = 64;
1223 } else {
1224 chansize = 32;
1225 }
5885b7a9
AD		 1226 tmp = RREG32(CHMAP);
1227 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1228 case 0:
1229 default:
1230 numchan = 1;
1231 break;
1232 case 1:
1233 numchan = 2;
1234 break;
1235 case 2:
1236 numchan = 4;
1237 break;
1238 case 3:
1239 numchan = 8;
1240 break;
771fe6b9 1241 }
5885b7a9 1242 rdev->mc.vram_width = numchan * chansize;
3ce0a23d 1243 /* Could aper size report 0 ? */
01d73a69
JC		 1244 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
1245 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
3ce0a23d
JG		 1246 /* Setup GPU memory space */
1247 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
1248 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
51e5fcd3 1249 rdev->mc.visible_vram_size = rdev->mc.aper_size;
c919b371 1250 rdev->mc.active_vram_size = rdev->mc.visible_vram_size;
d594e46a 1251 r600_vram_gtt_location(rdev, &rdev->mc);
f47299c5 1252
f892034a
AD		 1253 if (rdev->flags & RADEON_IS_IGP) {
1254 rs690_pm_info(rdev);
06b6476d 1255 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
f892034a 1256 }
f47299c5 1257 radeon_update_bandwidth_info(rdev);
3ce0a23d 1258 return 0;
771fe6b9
JG		 1259}
1260
3ce0a23d
JG		 1261/* We doesn't check that the GPU really needs a reset we simply do the
1262 * reset, it's up to the caller to determine if the GPU needs one. We
1263 * might add an helper function to check that.
1264 */
1265int r600_gpu_soft_reset(struct radeon_device *rdev)
771fe6b9 1266{
a3c1945a 1267 struct rv515_mc_save save;
3ce0a23d
JG		 1268 u32 grbm_busy_mask = S_008010_VC_BUSY(1) | S_008010_VGT_BUSY_NO_DMA(1) |
1269 S_008010_VGT_BUSY(1) | S_008010_TA03_BUSY(1) |
1270 S_008010_TC_BUSY(1) | S_008010_SX_BUSY(1) |
1271 S_008010_SH_BUSY(1) | S_008010_SPI03_BUSY(1) |
1272 S_008010_SMX_BUSY(1) | S_008010_SC_BUSY(1) |
1273 S_008010_PA_BUSY(1) | S_008010_DB03_BUSY(1) |
1274 S_008010_CR_BUSY(1) | S_008010_CB03_BUSY(1) |
1275 S_008010_GUI_ACTIVE(1);
1276 u32 grbm2_busy_mask = S_008014_SPI0_BUSY(1) | S_008014_SPI1_BUSY(1) |
1277 S_008014_SPI2_BUSY(1) | S_008014_SPI3_BUSY(1) |
1278 S_008014_TA0_BUSY(1) | S_008014_TA1_BUSY(1) |
1279 S_008014_TA2_BUSY(1) | S_008014_TA3_BUSY(1) |
1280 S_008014_DB0_BUSY(1) | S_008014_DB1_BUSY(1) |
1281 S_008014_DB2_BUSY(1) | S_008014_DB3_BUSY(1) |
1282 S_008014_CB0_BUSY(1) | S_008014_CB1_BUSY(1) |
1283 S_008014_CB2_BUSY(1) | S_008014_CB3_BUSY(1);
a3c1945a 1284 u32 tmp;
771fe6b9 1285
1a029b76
JG		 1286 dev_info(rdev->dev, "GPU softreset \n");
1287 dev_info(rdev->dev, " R_008010_GRBM_STATUS=0x%08X\n",
1288 RREG32(R_008010_GRBM_STATUS));
1289 dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n",
a3c1945a 1290 RREG32(R_008014_GRBM_STATUS2));
1a029b76
JG		 1291 dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n",
1292 RREG32(R_000E50_SRBM_STATUS));
a3c1945a
JG		 1293 rv515_mc_stop(rdev, &save);
1294 if (r600_mc_wait_for_idle(rdev)) {
1295 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1296 }
3ce0a23d 1297 /* Disable CP parsing/prefetching */
90aca4d2 1298 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
3ce0a23d
JG		 1299 /* Check if any of the rendering block is busy and reset it */
1300 if ((RREG32(R_008010_GRBM_STATUS) & grbm_busy_mask) ||
1301 (RREG32(R_008014_GRBM_STATUS2) & grbm2_busy_mask)) {
a3c1945a 1302 tmp = S_008020_SOFT_RESET_CR(1) |
3ce0a23d
JG		 1303 S_008020_SOFT_RESET_DB(1) |
1304 S_008020_SOFT_RESET_CB(1) |
1305 S_008020_SOFT_RESET_PA(1) |
1306 S_008020_SOFT_RESET_SC(1) |
1307 S_008020_SOFT_RESET_SMX(1) |
1308 S_008020_SOFT_RESET_SPI(1) |
1309 S_008020_SOFT_RESET_SX(1) |
1310 S_008020_SOFT_RESET_SH(1) |
1311 S_008020_SOFT_RESET_TC(1) |
1312 S_008020_SOFT_RESET_TA(1) |
1313 S_008020_SOFT_RESET_VC(1) |
a3c1945a 1314 S_008020_SOFT_RESET_VGT(1);
1a029b76 1315 dev_info(rdev->dev, " R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
a3c1945a 1316 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
90aca4d2
JG		 1317 RREG32(R_008020_GRBM_SOFT_RESET);
1318 mdelay(15);
3ce0a23d 1319 WREG32(R_008020_GRBM_SOFT_RESET, 0);
3ce0a23d
JG		 1320 }
1321 /* Reset CP (we always reset CP) */
a3c1945a
JG		 1322 tmp = S_008020_SOFT_RESET_CP(1);
1323 dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
1324 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
90aca4d2
JG		 1325 RREG32(R_008020_GRBM_SOFT_RESET);
1326 mdelay(15);
3ce0a23d 1327 WREG32(R_008020_GRBM_SOFT_RESET, 0);
3ce0a23d 1328 /* Wait a little for things to settle down */
225758d8 1329 mdelay(1);
1a029b76
JG		 1330 dev_info(rdev->dev, " R_008010_GRBM_STATUS=0x%08X\n",
1331 RREG32(R_008010_GRBM_STATUS));
1332 dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n",
1333 RREG32(R_008014_GRBM_STATUS2));
1334 dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n",
1335 RREG32(R_000E50_SRBM_STATUS));
a3c1945a 1336 rv515_mc_resume(rdev, &save);
3ce0a23d
JG		 1337 return 0;
1338}
1339
225758d8
JG		 1340bool r600_gpu_is_lockup(struct radeon_device *rdev)
1341{
1342 u32 srbm_status;
1343 u32 grbm_status;
1344 u32 grbm_status2;
e29ff729 1345 struct r100_gpu_lockup *lockup;
225758d8
JG		 1346 int r;
1347
e29ff729
AD		 1348 if (rdev->family >= CHIP_RV770)
1349 lockup = &rdev->config.rv770.lockup;
1350 else
1351 lockup = &rdev->config.r600.lockup;
1352
225758d8
JG		 1353 srbm_status = RREG32(R_000E50_SRBM_STATUS);
1354 grbm_status = RREG32(R_008010_GRBM_STATUS);
1355 grbm_status2 = RREG32(R_008014_GRBM_STATUS2);
1356 if (!G_008010_GUI_ACTIVE(grbm_status)) {
e29ff729 1357 r100_gpu_lockup_update(lockup, &rdev->cp);
225758d8
JG		 1358 return false;
1359 }
1360 /* force CP activities */
1361 r = radeon_ring_lock(rdev, 2);
1362 if (!r) {
1363 /* PACKET2 NOP */
1364 radeon_ring_write(rdev, 0x80000000);
1365 radeon_ring_write(rdev, 0x80000000);
1366 radeon_ring_unlock_commit(rdev);
1367 }
1368 rdev->cp.rptr = RREG32(R600_CP_RB_RPTR);
e29ff729 1369 return r100_gpu_cp_is_lockup(rdev, lockup, &rdev->cp);
225758d8
JG		 1370}
1371
a2d07b74 1372int r600_asic_reset(struct radeon_device *rdev)
3ce0a23d
JG		 1373{
1374 return r600_gpu_soft_reset(rdev);
1375}
1376
1377static u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
1378 u32 num_backends,
1379 u32 backend_disable_mask)
1380{
1381 u32 backend_map = 0;
1382 u32 enabled_backends_mask;
1383 u32 enabled_backends_count;
1384 u32 cur_pipe;
1385 u32 swizzle_pipe[R6XX_MAX_PIPES];
1386 u32 cur_backend;
1387 u32 i;
1388
1389 if (num_tile_pipes > R6XX_MAX_PIPES)
1390 num_tile_pipes = R6XX_MAX_PIPES;
1391 if (num_tile_pipes < 1)
1392 num_tile_pipes = 1;
1393 if (num_backends > R6XX_MAX_BACKENDS)
1394 num_backends = R6XX_MAX_BACKENDS;
1395 if (num_backends < 1)
1396 num_backends = 1;
1397
1398 enabled_backends_mask = 0;
1399 enabled_backends_count = 0;
1400 for (i = 0; i < R6XX_MAX_BACKENDS; ++i) {
1401 if (((backend_disable_mask >> i) & 1) == 0) {
1402 enabled_backends_mask |= (1 << i);
1403 ++enabled_backends_count;
1404 }
1405 if (enabled_backends_count == num_backends)
1406 break;
1407 }
1408
1409 if (enabled_backends_count == 0) {
1410 enabled_backends_mask = 1;
1411 enabled_backends_count = 1;
1412 }
1413
1414 if (enabled_backends_count != num_backends)
1415 num_backends = enabled_backends_count;
1416
1417 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES);
1418 switch (num_tile_pipes) {
1419 case 1:
1420 swizzle_pipe[0] = 0;
1421 break;
1422 case 2:
1423 swizzle_pipe[0] = 0;
1424 swizzle_pipe[1] = 1;
1425 break;
1426 case 3:
1427 swizzle_pipe[0] = 0;
1428 swizzle_pipe[1] = 1;
1429 swizzle_pipe[2] = 2;
1430 break;
1431 case 4:
1432 swizzle_pipe[0] = 0;
1433 swizzle_pipe[1] = 1;
1434 swizzle_pipe[2] = 2;
1435 swizzle_pipe[3] = 3;
1436 break;
1437 case 5:
1438 swizzle_pipe[0] = 0;
1439 swizzle_pipe[1] = 1;
1440 swizzle_pipe[2] = 2;
1441 swizzle_pipe[3] = 3;
1442 swizzle_pipe[4] = 4;
1443 break;
1444 case 6:
1445 swizzle_pipe[0] = 0;
1446 swizzle_pipe[1] = 2;
1447 swizzle_pipe[2] = 4;
1448 swizzle_pipe[3] = 5;
1449 swizzle_pipe[4] = 1;
1450 swizzle_pipe[5] = 3;
1451 break;
1452 case 7:
1453 swizzle_pipe[0] = 0;
1454 swizzle_pipe[1] = 2;
1455 swizzle_pipe[2] = 4;
1456 swizzle_pipe[3] = 6;
1457 swizzle_pipe[4] = 1;
1458 swizzle_pipe[5] = 3;
1459 swizzle_pipe[6] = 5;
1460 break;
1461 case 8:
1462 swizzle_pipe[0] = 0;
1463 swizzle_pipe[1] = 2;
1464 swizzle_pipe[2] = 4;
1465 swizzle_pipe[3] = 6;
1466 swizzle_pipe[4] = 1;
1467 swizzle_pipe[5] = 3;
1468 swizzle_pipe[6] = 5;
1469 swizzle_pipe[7] = 7;
1470 break;
1471 }
1472
1473 cur_backend = 0;
1474 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
1475 while (((1 << cur_backend) & enabled_backends_mask) == 0)
1476 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
1477
1478 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
1479
1480 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
1481 }
1482
1483 return backend_map;
1484}
1485
1486int r600_count_pipe_bits(uint32_t val)
1487{
1488 int i, ret = 0;
1489
1490 for (i = 0; i < 32; i++) {
1491 ret += val & 1;
1492 val >>= 1;
1493 }
1494 return ret;
771fe6b9
JG		 1495}
1496
3ce0a23d
JG		 1497void r600_gpu_init(struct radeon_device *rdev)
1498{
1499 u32 tiling_config;
1500 u32 ramcfg;
d03f5d59
AD		 1501 u32 backend_map;
1502 u32 cc_rb_backend_disable;
1503 u32 cc_gc_shader_pipe_config;
3ce0a23d
JG		 1504 u32 tmp;
1505 int i, j;
1506 u32 sq_config;
1507 u32 sq_gpr_resource_mgmt_1 = 0;
1508 u32 sq_gpr_resource_mgmt_2 = 0;
1509 u32 sq_thread_resource_mgmt = 0;
1510 u32 sq_stack_resource_mgmt_1 = 0;
1511 u32 sq_stack_resource_mgmt_2 = 0;
1512
1513 /* FIXME: implement */
1514 switch (rdev->family) {
1515 case CHIP_R600:
1516 rdev->config.r600.max_pipes = 4;
1517 rdev->config.r600.max_tile_pipes = 8;
1518 rdev->config.r600.max_simds = 4;
1519 rdev->config.r600.max_backends = 4;
1520 rdev->config.r600.max_gprs = 256;
1521 rdev->config.r600.max_threads = 192;
1522 rdev->config.r600.max_stack_entries = 256;
1523 rdev->config.r600.max_hw_contexts = 8;
1524 rdev->config.r600.max_gs_threads = 16;
1525 rdev->config.r600.sx_max_export_size = 128;
1526 rdev->config.r600.sx_max_export_pos_size = 16;
1527 rdev->config.r600.sx_max_export_smx_size = 128;
1528 rdev->config.r600.sq_num_cf_insts = 2;
1529 break;
1530 case CHIP_RV630:
1531 case CHIP_RV635:
1532 rdev->config.r600.max_pipes = 2;
1533 rdev->config.r600.max_tile_pipes = 2;
1534 rdev->config.r600.max_simds = 3;
1535 rdev->config.r600.max_backends = 1;
1536 rdev->config.r600.max_gprs = 128;
1537 rdev->config.r600.max_threads = 192;
1538 rdev->config.r600.max_stack_entries = 128;
1539 rdev->config.r600.max_hw_contexts = 8;
1540 rdev->config.r600.max_gs_threads = 4;
1541 rdev->config.r600.sx_max_export_size = 128;
1542 rdev->config.r600.sx_max_export_pos_size = 16;
1543 rdev->config.r600.sx_max_export_smx_size = 128;
1544 rdev->config.r600.sq_num_cf_insts = 2;
1545 break;
1546 case CHIP_RV610:
1547 case CHIP_RV620:
1548 case CHIP_RS780:
1549 case CHIP_RS880:
1550 rdev->config.r600.max_pipes = 1;
1551 rdev->config.r600.max_tile_pipes = 1;
1552 rdev->config.r600.max_simds = 2;
1553 rdev->config.r600.max_backends = 1;
1554 rdev->config.r600.max_gprs = 128;
1555 rdev->config.r600.max_threads = 192;
1556 rdev->config.r600.max_stack_entries = 128;
1557 rdev->config.r600.max_hw_contexts = 4;
1558 rdev->config.r600.max_gs_threads = 4;
1559 rdev->config.r600.sx_max_export_size = 128;
1560 rdev->config.r600.sx_max_export_pos_size = 16;
1561 rdev->config.r600.sx_max_export_smx_size = 128;
1562 rdev->config.r600.sq_num_cf_insts = 1;
1563 break;
1564 case CHIP_RV670:
1565 rdev->config.r600.max_pipes = 4;
1566 rdev->config.r600.max_tile_pipes = 4;
1567 rdev->config.r600.max_simds = 4;
1568 rdev->config.r600.max_backends = 4;
1569 rdev->config.r600.max_gprs = 192;
1570 rdev->config.r600.max_threads = 192;
1571 rdev->config.r600.max_stack_entries = 256;
1572 rdev->config.r600.max_hw_contexts = 8;
1573 rdev->config.r600.max_gs_threads = 16;
1574 rdev->config.r600.sx_max_export_size = 128;
1575 rdev->config.r600.sx_max_export_pos_size = 16;
1576 rdev->config.r600.sx_max_export_smx_size = 128;
1577 rdev->config.r600.sq_num_cf_insts = 2;
1578 break;
1579 default:
1580 break;
1581 }
1582
1583 /* Initialize HDP */
1584 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1585 WREG32((0x2c14 + j), 0x00000000);
1586 WREG32((0x2c18 + j), 0x00000000);
1587 WREG32((0x2c1c + j), 0x00000000);
1588 WREG32((0x2c20 + j), 0x00000000);
1589 WREG32((0x2c24 + j), 0x00000000);
1590 }
1591
1592 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1593
1594 /* Setup tiling */
1595 tiling_config = 0;
1596 ramcfg = RREG32(RAMCFG);
1597 switch (rdev->config.r600.max_tile_pipes) {
1598 case 1:
1599 tiling_config |= PIPE_TILING(0);
1600 break;
1601 case 2:
1602 tiling_config |= PIPE_TILING(1);
1603 break;
1604 case 4:
1605 tiling_config |= PIPE_TILING(2);
1606 break;
1607 case 8:
1608 tiling_config |= PIPE_TILING(3);
1609 break;
1610 default:
1611 break;
1612 }
d03f5d59 1613 rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes;
961fb597 1614 rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
3ce0a23d 1615 tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
881fe6c1
AD		 1616 tiling_config |= GROUP_SIZE((ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
1617 if ((ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT)
1618 rdev->config.r600.tiling_group_size = 512;
1619 else
1620 rdev->config.r600.tiling_group_size = 256;
3ce0a23d
JG		 1621 tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
1622 if (tmp > 3) {
1623 tiling_config |= ROW_TILING(3);
1624 tiling_config |= SAMPLE_SPLIT(3);
1625 } else {
1626 tiling_config |= ROW_TILING(tmp);
1627 tiling_config |= SAMPLE_SPLIT(tmp);
1628 }
1629 tiling_config |= BANK_SWAPS(1);
d03f5d59
AD		 1630
1631 cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000;
1632 cc_rb_backend_disable |=
1633 BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << rdev->config.r600.max_backends) & R6XX_MAX_BACKENDS_MASK);
1634
1635 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00;
1636 cc_gc_shader_pipe_config |=
1637 INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << rdev->config.r600.max_pipes) & R6XX_MAX_PIPES_MASK);
1638 cc_gc_shader_pipe_config |=
1639 INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << rdev->config.r600.max_simds) & R6XX_MAX_SIMDS_MASK);
1640
1641 backend_map = r600_get_tile_pipe_to_backend_map(rdev->config.r600.max_tile_pipes,
1642 (R6XX_MAX_BACKENDS -
1643 r600_count_pipe_bits((cc_rb_backend_disable &
1644 R6XX_MAX_BACKENDS_MASK) >> 16)),
1645 (cc_rb_backend_disable >> 16));
e7aeeba6 1646 rdev->config.r600.tile_config = tiling_config;
d03f5d59 1647 tiling_config |= BACKEND_MAP(backend_map);
3ce0a23d
JG		 1648 WREG32(GB_TILING_CONFIG, tiling_config);
1649 WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff);
1650 WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff);
1651
3ce0a23d 1652 /* Setup pipes */
d03f5d59
AD		 1653 WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
1654 WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
f867c60d 1655 WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
3ce0a23d 1656
d03f5d59 1657 tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
3ce0a23d
JG		 1658 WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);
1659 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK);
1660
1661 /* Setup some CP states */
1662 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b)));
1663 WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40)));
1664
1665 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT |
1666 SYNC_WALKER | SYNC_ALIGNER));
1667 /* Setup various GPU states */
1668 if (rdev->family == CHIP_RV670)
1669 WREG32(ARB_GDEC_RD_CNTL, 0x00000021);
1670
1671 tmp = RREG32(SX_DEBUG_1);
1672 tmp |= SMX_EVENT_RELEASE;
1673 if ((rdev->family > CHIP_R600))
1674 tmp |= ENABLE_NEW_SMX_ADDRESS;
1675 WREG32(SX_DEBUG_1, tmp);
1676
1677 if (((rdev->family) == CHIP_R600) ||
1678 ((rdev->family) == CHIP_RV630) ||
1679 ((rdev->family) == CHIP_RV610) ||
1680 ((rdev->family) == CHIP_RV620) ||
ee59f2b4
AD		 1681 ((rdev->family) == CHIP_RS780) ||
1682 ((rdev->family) == CHIP_RS880)) {
3ce0a23d
JG		 1683 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE);
1684 } else {
1685 WREG32(DB_DEBUG, 0);
1686 }
1687 WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) |
1688 DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4)));
1689
1690 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1691 WREG32(VGT_NUM_INSTANCES, 0);
1692
1693 WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
1694 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0));
1695
1696 tmp = RREG32(SQ_MS_FIFO_SIZES);
1697 if (((rdev->family) == CHIP_RV610) ||
1698 ((rdev->family) == CHIP_RV620) ||
ee59f2b4
AD		 1699 ((rdev->family) == CHIP_RS780) ||
1700 ((rdev->family) == CHIP_RS880)) {
3ce0a23d
JG		 1701 tmp = (CACHE_FIFO_SIZE(0xa) |
1702 FETCH_FIFO_HIWATER(0xa) |
1703 DONE_FIFO_HIWATER(0xe0) |
1704 ALU_UPDATE_FIFO_HIWATER(0x8));
1705 } else if (((rdev->family) == CHIP_R600) ||
1706 ((rdev->family) == CHIP_RV630)) {
1707 tmp &= ~DONE_FIFO_HIWATER(0xff);
1708 tmp |= DONE_FIFO_HIWATER(0x4);
1709 }
1710 WREG32(SQ_MS_FIFO_SIZES, tmp);
1711
1712 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
1713 * should be adjusted as needed by the 2D/3D drivers. This just sets default values
1714 */
1715 sq_config = RREG32(SQ_CONFIG);
1716 sq_config &= ~(PS_PRIO(3) |
1717 VS_PRIO(3) |
1718 GS_PRIO(3) |
1719 ES_PRIO(3));
1720 sq_config |= (DX9_CONSTS |
1721 VC_ENABLE |
1722 PS_PRIO(0) |
1723 VS_PRIO(1) |
1724 GS_PRIO(2) |
1725 ES_PRIO(3));
1726
1727 if ((rdev->family) == CHIP_R600) {
1728 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) |
1729 NUM_VS_GPRS(124) |
1730 NUM_CLAUSE_TEMP_GPRS(4));
1731 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) |
1732 NUM_ES_GPRS(0));
1733 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) |
1734 NUM_VS_THREADS(48) |
1735 NUM_GS_THREADS(4) |
1736 NUM_ES_THREADS(4));
1737 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) |
1738 NUM_VS_STACK_ENTRIES(128));
1739 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) |
1740 NUM_ES_STACK_ENTRIES(0));
1741 } else if (((rdev->family) == CHIP_RV610) ||
1742 ((rdev->family) == CHIP_RV620) ||
ee59f2b4
AD		 1743 ((rdev->family) == CHIP_RS780) ||
1744 ((rdev->family) == CHIP_RS880)) {
3ce0a23d
JG		 1745 /* no vertex cache */
1746 sq_config &= ~VC_ENABLE;
1747
1748 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1749 NUM_VS_GPRS(44) |
1750 NUM_CLAUSE_TEMP_GPRS(2));
1751 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1752 NUM_ES_GPRS(17));
1753 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1754 NUM_VS_THREADS(78) |
1755 NUM_GS_THREADS(4) |
1756 NUM_ES_THREADS(31));
1757 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1758 NUM_VS_STACK_ENTRIES(40));
1759 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1760 NUM_ES_STACK_ENTRIES(16));
1761 } else if (((rdev->family) == CHIP_RV630) ||
1762 ((rdev->family) == CHIP_RV635)) {
1763 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1764 NUM_VS_GPRS(44) |
1765 NUM_CLAUSE_TEMP_GPRS(2));
1766 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) |
1767 NUM_ES_GPRS(18));
1768 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1769 NUM_VS_THREADS(78) |
1770 NUM_GS_THREADS(4) |
1771 NUM_ES_THREADS(31));
1772 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1773 NUM_VS_STACK_ENTRIES(40));
1774 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1775 NUM_ES_STACK_ENTRIES(16));
1776 } else if ((rdev->family) == CHIP_RV670) {
1777 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1778 NUM_VS_GPRS(44) |
1779 NUM_CLAUSE_TEMP_GPRS(2));
1780 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1781 NUM_ES_GPRS(17));
1782 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1783 NUM_VS_THREADS(78) |
1784 NUM_GS_THREADS(4) |
1785 NUM_ES_THREADS(31));
1786 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) |
1787 NUM_VS_STACK_ENTRIES(64));
1788 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) |
1789 NUM_ES_STACK_ENTRIES(64));
1790 }
1791
1792 WREG32(SQ_CONFIG, sq_config);
1793 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
1794 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
1795 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1796 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
1797 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
1798
1799 if (((rdev->family) == CHIP_RV610) ||
1800 ((rdev->family) == CHIP_RV620) ||
ee59f2b4
AD		 1801 ((rdev->family) == CHIP_RS780) ||
1802 ((rdev->family) == CHIP_RS880)) {
3ce0a23d
JG		 1803 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY));
1804 } else {
1805 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC));
1806 }
1807
1808 /* More default values. 2D/3D driver should adjust as needed */
1809 WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) |
1810 S1_X(0x4) | S1_Y(0xc)));
1811 WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) |
1812 S1_X(0x2) | S1_Y(0x2) |
1813 S2_X(0xa) | S2_Y(0x6) |
1814 S3_X(0x6) | S3_Y(0xa)));
1815 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) |
1816 S1_X(0x4) | S1_Y(0xc) |
1817 S2_X(0x1) | S2_Y(0x6) |
1818 S3_X(0xa) | S3_Y(0xe)));
1819 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) |
1820 S5_X(0x0) | S5_Y(0x0) |
1821 S6_X(0xb) | S6_Y(0x4) |
1822 S7_X(0x7) | S7_Y(0x8)));
1823
1824 WREG32(VGT_STRMOUT_EN, 0);
1825 tmp = rdev->config.r600.max_pipes * 16;
1826 switch (rdev->family) {
1827 case CHIP_RV610:
3ce0a23d 1828 case CHIP_RV620:
ee59f2b4
AD		 1829 case CHIP_RS780:
1830 case CHIP_RS880:
3ce0a23d
JG		 1831 tmp += 32;
1832 break;
1833 case CHIP_RV670:
1834 tmp += 128;
1835 break;
1836 default:
1837 break;
1838 }
1839 if (tmp > 256) {
1840 tmp = 256;
1841 }
1842 WREG32(VGT_ES_PER_GS, 128);
1843 WREG32(VGT_GS_PER_ES, tmp);
1844 WREG32(VGT_GS_PER_VS, 2);
1845 WREG32(VGT_GS_VERTEX_REUSE, 16);
1846
1847 /* more default values. 2D/3D driver should adjust as needed */
1848 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1849 WREG32(VGT_STRMOUT_EN, 0);
1850 WREG32(SX_MISC, 0);
1851 WREG32(PA_SC_MODE_CNTL, 0);
1852 WREG32(PA_SC_AA_CONFIG, 0);
1853 WREG32(PA_SC_LINE_STIPPLE, 0);
1854 WREG32(SPI_INPUT_Z, 0);
1855 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
1856 WREG32(CB_COLOR7_FRAG, 0);
1857
1858 /* Clear render buffer base addresses */
1859 WREG32(CB_COLOR0_BASE, 0);
1860 WREG32(CB_COLOR1_BASE, 0);
1861 WREG32(CB_COLOR2_BASE, 0);
1862 WREG32(CB_COLOR3_BASE, 0);
1863 WREG32(CB_COLOR4_BASE, 0);
1864 WREG32(CB_COLOR5_BASE, 0);
1865 WREG32(CB_COLOR6_BASE, 0);
1866 WREG32(CB_COLOR7_BASE, 0);
1867 WREG32(CB_COLOR7_FRAG, 0);
1868
1869 switch (rdev->family) {
1870 case CHIP_RV610:
3ce0a23d 1871 case CHIP_RV620:
ee59f2b4
AD		 1872 case CHIP_RS780:
1873 case CHIP_RS880:
3ce0a23d
JG		 1874 tmp = TC_L2_SIZE(8);
1875 break;
1876 case CHIP_RV630:
1877 case CHIP_RV635:
1878 tmp = TC_L2_SIZE(4);
1879 break;
1880 case CHIP_R600:
1881 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT;
1882 break;
1883 default:
1884 tmp = TC_L2_SIZE(0);
1885 break;
1886 }
1887 WREG32(TC_CNTL, tmp);
1888
1889 tmp = RREG32(HDP_HOST_PATH_CNTL);
1890 WREG32(HDP_HOST_PATH_CNTL, tmp);
1891
1892 tmp = RREG32(ARB_POP);
1893 tmp |= ENABLE_TC128;
1894 WREG32(ARB_POP, tmp);
1895
1896 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1897 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
1898 NUM_CLIP_SEQ(3)));
1899 WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));
1900}
1901
1902
771fe6b9
JG		 1903/*
1904 * Indirect registers accessor
1905 */
3ce0a23d
JG		 1906u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg)
1907{
1908 u32 r;
1909
1910 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1911 (void)RREG32(PCIE_PORT_INDEX);
1912 r = RREG32(PCIE_PORT_DATA);
1913 return r;
1914}
1915
1916void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
1917{
1918 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1919 (void)RREG32(PCIE_PORT_INDEX);
1920 WREG32(PCIE_PORT_DATA, (v));
1921 (void)RREG32(PCIE_PORT_DATA);
1922}
1923
3ce0a23d
JG		 1924/*
1925 * CP & Ring
1926 */
1927void r600_cp_stop(struct radeon_device *rdev)
1928{
c919b371 1929 rdev->mc.active_vram_size = rdev->mc.visible_vram_size;
3ce0a23d 1930 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
724c80e1 1931 WREG32(SCRATCH_UMSK, 0);
3ce0a23d
JG		 1932}
1933
d8f60cfc 1934int r600_init_microcode(struct radeon_device *rdev)
3ce0a23d
JG		 1935{
1936 struct platform_device *pdev;
1937 const char *chip_name;
d8f60cfc
AD		 1938 const char *rlc_chip_name;
1939 size_t pfp_req_size, me_req_size, rlc_req_size;
3ce0a23d
JG		 1940 char fw_name[30];
1941 int err;
1942
1943 DRM_DEBUG("\n");
1944
1945 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
1946 err = IS_ERR(pdev);
1947 if (err) {
1948 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
1949 return -EINVAL;
1950 }
1951
1952 switch (rdev->family) {
d8f60cfc
AD		 1953 case CHIP_R600:
1954 chip_name = "R600";
1955 rlc_chip_name = "R600";
1956 break;
1957 case CHIP_RV610:
1958 chip_name = "RV610";
1959 rlc_chip_name = "R600";
1960 break;
1961 case CHIP_RV630:
1962 chip_name = "RV630";
1963 rlc_chip_name = "R600";
1964 break;
1965 case CHIP_RV620:
1966 chip_name = "RV620";
1967 rlc_chip_name = "R600";
1968 break;
1969 case CHIP_RV635:
1970 chip_name = "RV635";
1971 rlc_chip_name = "R600";
1972 break;
1973 case CHIP_RV670:
1974 chip_name = "RV670";
1975 rlc_chip_name = "R600";
1976 break;
3ce0a23d 1977 case CHIP_RS780:
d8f60cfc
AD		 1978 case CHIP_RS880:
1979 chip_name = "RS780";
1980 rlc_chip_name = "R600";
1981 break;
1982 case CHIP_RV770:
1983 chip_name = "RV770";
1984 rlc_chip_name = "R700";
1985 break;
3ce0a23d 1986 case CHIP_RV730:
d8f60cfc
AD		 1987 case CHIP_RV740:
1988 chip_name = "RV730";
1989 rlc_chip_name = "R700";
1990 break;
1991 case CHIP_RV710:
1992 chip_name = "RV710";
1993 rlc_chip_name = "R700";
1994 break;
fe251e2f
AD		 1995 case CHIP_CEDAR:
1996 chip_name = "CEDAR";
45f9a39b 1997 rlc_chip_name = "CEDAR";
fe251e2f
AD		 1998 break;
1999 case CHIP_REDWOOD:
2000 chip_name = "REDWOOD";
45f9a39b 2001 rlc_chip_name = "REDWOOD";
fe251e2f
AD		 2002 break;
2003 case CHIP_JUNIPER:
2004 chip_name = "JUNIPER";
45f9a39b 2005 rlc_chip_name = "JUNIPER";
fe251e2f
AD		 2006 break;
2007 case CHIP_CYPRESS:
2008 case CHIP_HEMLOCK:
2009 chip_name = "CYPRESS";
45f9a39b 2010 rlc_chip_name = "CYPRESS";
fe251e2f 2011 break;
3ce0a23d
JG		 2012 default: BUG();
2013 }
2014
fe251e2f
AD		 2015 if (rdev->family >= CHIP_CEDAR) {
2016 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
2017 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
45f9a39b 2018 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
fe251e2f 2019 } else if (rdev->family >= CHIP_RV770) {
3ce0a23d
JG		 2020 pfp_req_size = R700_PFP_UCODE_SIZE * 4;
2021 me_req_size = R700_PM4_UCODE_SIZE * 4;
d8f60cfc 2022 rlc_req_size = R700_RLC_UCODE_SIZE * 4;
3ce0a23d
JG		 2023 } else {
2024 pfp_req_size = PFP_UCODE_SIZE * 4;
2025 me_req_size = PM4_UCODE_SIZE * 12;
d8f60cfc 2026 rlc_req_size = RLC_UCODE_SIZE * 4;
3ce0a23d
JG		 2027 }
2028
d8f60cfc 2029 DRM_INFO("Loading %s Microcode\n", chip_name);
3ce0a23d
JG		 2030
2031 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
2032 err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
2033 if (err)
2034 goto out;
2035 if (rdev->pfp_fw->size != pfp_req_size) {
2036 printk(KERN_ERR
2037 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
2038 rdev->pfp_fw->size, fw_name);
2039 err = -EINVAL;
2040 goto out;
2041 }
2042
2043 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
2044 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
2045 if (err)
2046 goto out;
2047 if (rdev->me_fw->size != me_req_size) {
2048 printk(KERN_ERR
2049 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
2050 rdev->me_fw->size, fw_name);
2051 err = -EINVAL;
2052 }
d8f60cfc
AD		 2053
2054 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
2055 err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev);
2056 if (err)
2057 goto out;
2058 if (rdev->rlc_fw->size != rlc_req_size) {
2059 printk(KERN_ERR
2060 "r600_rlc: Bogus length %zu in firmware \"%s\"\n",
2061 rdev->rlc_fw->size, fw_name);
2062 err = -EINVAL;
2063 }
2064
3ce0a23d
JG		 2065out:
2066 platform_device_unregister(pdev);
2067
2068 if (err) {
2069 if (err != -EINVAL)
2070 printk(KERN_ERR
2071 "r600_cp: Failed to load firmware \"%s\"\n",
2072 fw_name);
2073 release_firmware(rdev->pfp_fw);
2074 rdev->pfp_fw = NULL;
2075 release_firmware(rdev->me_fw);
2076 rdev->me_fw = NULL;
d8f60cfc
AD		 2077 release_firmware(rdev->rlc_fw);
2078 rdev->rlc_fw = NULL;
3ce0a23d
JG		 2079 }
2080 return err;
2081}
2082
2083static int r600_cp_load_microcode(struct radeon_device *rdev)
2084{
2085 const __be32 *fw_data;
2086 int i;
2087
2088 if (!rdev->me_fw || !rdev->pfp_fw)
2089 return -EINVAL;
2090
2091 r600_cp_stop(rdev);
2092
2093 WREG32(CP_RB_CNTL, RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
2094
2095 /* Reset cp */
2096 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2097 RREG32(GRBM_SOFT_RESET);
2098 mdelay(15);
2099 WREG32(GRBM_SOFT_RESET, 0);
2100
2101 WREG32(CP_ME_RAM_WADDR, 0);
2102
2103 fw_data = (const __be32 *)rdev->me_fw->data;
2104 WREG32(CP_ME_RAM_WADDR, 0);
2105 for (i = 0; i < PM4_UCODE_SIZE * 3; i++)
2106 WREG32(CP_ME_RAM_DATA,
2107 be32_to_cpup(fw_data++));
2108
2109 fw_data = (const __be32 *)rdev->pfp_fw->data;
2110 WREG32(CP_PFP_UCODE_ADDR, 0);
2111 for (i = 0; i < PFP_UCODE_SIZE; i++)
2112 WREG32(CP_PFP_UCODE_DATA,
2113 be32_to_cpup(fw_data++));
2114
2115 WREG32(CP_PFP_UCODE_ADDR, 0);
2116 WREG32(CP_ME_RAM_WADDR, 0);
2117 WREG32(CP_ME_RAM_RADDR, 0);
2118 return 0;
2119}
2120
2121int r600_cp_start(struct radeon_device *rdev)
2122{
2123 int r;
2124 uint32_t cp_me;
2125
2126 r = radeon_ring_lock(rdev, 7);
2127 if (r) {
2128 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
2129 return r;
2130 }
2131 radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5));
2132 radeon_ring_write(rdev, 0x1);
7e7b41d2 2133 if (rdev->family >= CHIP_RV770) {
3ce0a23d
JG		 2134 radeon_ring_write(rdev, 0x0);
2135 radeon_ring_write(rdev, rdev->config.rv770.max_hw_contexts - 1);
fe251e2f
AD		 2136 } else {
2137 radeon_ring_write(rdev, 0x3);
2138 radeon_ring_write(rdev, rdev->config.r600.max_hw_contexts - 1);
3ce0a23d
JG		 2139 }
2140 radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
2141 radeon_ring_write(rdev, 0);
2142 radeon_ring_write(rdev, 0);
2143 radeon_ring_unlock_commit(rdev);
2144
2145 cp_me = 0xff;
2146 WREG32(R_0086D8_CP_ME_CNTL, cp_me);
2147 return 0;
2148}
2149
2150int r600_cp_resume(struct radeon_device *rdev)
2151{
2152 u32 tmp;
2153 u32 rb_bufsz;
2154 int r;
2155
2156 /* Reset cp */
2157 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2158 RREG32(GRBM_SOFT_RESET);
2159 mdelay(15);
2160 WREG32(GRBM_SOFT_RESET, 0);
2161
2162 /* Set ring buffer size */
2163 rb_bufsz = drm_order(rdev->cp.ring_size / 8);
724c80e1 2164 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
3ce0a23d 2165#ifdef __BIG_ENDIAN
d6f28938 2166 tmp |= BUF_SWAP_32BIT;
3ce0a23d 2167#endif
d6f28938 2168 WREG32(CP_RB_CNTL, tmp);
3ce0a23d
JG		 2169 WREG32(CP_SEM_WAIT_TIMER, 0x4);
2170
2171 /* Set the write pointer delay */
2172 WREG32(CP_RB_WPTR_DELAY, 0);
2173
2174 /* Initialize the ring buffer's read and write pointers */
3ce0a23d
JG		 2175 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
2176 WREG32(CP_RB_RPTR_WR, 0);
2177 WREG32(CP_RB_WPTR, 0);
724c80e1
AD		 2178
2179 /* set the wb address whether it's enabled or not */
2180 WREG32(CP_RB_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC);
2181 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
2182 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
2183
2184 if (rdev->wb.enabled)
2185 WREG32(SCRATCH_UMSK, 0xff);
2186 else {
2187 tmp |= RB_NO_UPDATE;
2188 WREG32(SCRATCH_UMSK, 0);
2189 }
2190
3ce0a23d
JG		 2191 mdelay(1);
2192 WREG32(CP_RB_CNTL, tmp);
2193
2194 WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8);
2195 WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
2196
2197 rdev->cp.rptr = RREG32(CP_RB_RPTR);
2198 rdev->cp.wptr = RREG32(CP_RB_WPTR);
2199
2200 r600_cp_start(rdev);
2201 rdev->cp.ready = true;
2202 r = radeon_ring_test(rdev);
2203 if (r) {
2204 rdev->cp.ready = false;
2205 return r;
2206 }
2207 return 0;
2208}
2209
2210void r600_cp_commit(struct radeon_device *rdev)
2211{
2212 WREG32(CP_RB_WPTR, rdev->cp.wptr);
2213 (void)RREG32(CP_RB_WPTR);
2214}
2215
2216void r600_ring_init(struct radeon_device *rdev, unsigned ring_size)
2217{
2218 u32 rb_bufsz;
2219
2220 /* Align ring size */
2221 rb_bufsz = drm_order(ring_size / 8);
2222 ring_size = (1 << (rb_bufsz + 1)) * 4;
2223 rdev->cp.ring_size = ring_size;
2224 rdev->cp.align_mask = 16 - 1;
2225}
2226
655efd3d
JG		 2227void r600_cp_fini(struct radeon_device *rdev)
2228{
2229 r600_cp_stop(rdev);
2230 radeon_ring_fini(rdev);
2231}
2232
3ce0a23d
JG		 2233
2234/*
2235 * GPU scratch registers helpers function.
2236 */
2237void r600_scratch_init(struct radeon_device *rdev)
2238{
2239 int i;
2240
2241 rdev->scratch.num_reg = 7;
724c80e1 2242 rdev->scratch.reg_base = SCRATCH_REG0;
3ce0a23d
JG		 2243 for (i = 0; i < rdev->scratch.num_reg; i++) {
2244 rdev->scratch.free[i] = true;
724c80e1 2245 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
3ce0a23d
JG		 2246 }
2247}
2248
2249int r600_ring_test(struct radeon_device *rdev)
2250{
2251 uint32_t scratch;
2252 uint32_t tmp = 0;
2253 unsigned i;
2254 int r;
2255
2256 r = radeon_scratch_get(rdev, &scratch);
2257 if (r) {
2258 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
2259 return r;
2260 }
2261 WREG32(scratch, 0xCAFEDEAD);
2262 r = radeon_ring_lock(rdev, 3);
2263 if (r) {
2264 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
2265 radeon_scratch_free(rdev, scratch);
2266 return r;
2267 }
2268 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2269 radeon_ring_write(rdev, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2270 radeon_ring_write(rdev, 0xDEADBEEF);
2271 radeon_ring_unlock_commit(rdev);
2272 for (i = 0; i < rdev->usec_timeout; i++) {
2273 tmp = RREG32(scratch);
2274 if (tmp == 0xDEADBEEF)
2275 break;
2276 DRM_UDELAY(1);
2277 }
2278 if (i < rdev->usec_timeout) {
2279 DRM_INFO("ring test succeeded in %d usecs\n", i);
2280 } else {
2281 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
2282 scratch, tmp);
2283 r = -EINVAL;
2284 }
2285 radeon_scratch_free(rdev, scratch);
2286 return r;
2287}
2288
3ce0a23d
JG		 2289void r600_fence_ring_emit(struct radeon_device *rdev,
2290 struct radeon_fence *fence)
2291{
d0f8a854
AD		 2292 if (rdev->wb.use_event) {
2293 u64 addr = rdev->wb.gpu_addr + R600_WB_EVENT_OFFSET +
2294 (u64)(rdev->fence_drv.scratch_reg - rdev->scratch.reg_base);
2295 /* EVENT_WRITE_EOP - flush caches, send int */
2296 radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
2297 radeon_ring_write(rdev, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5));
2298 radeon_ring_write(rdev, addr & 0xffffffff);
2299 radeon_ring_write(rdev, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
2300 radeon_ring_write(rdev, fence->seq);
2301 radeon_ring_write(rdev, 0);
2302 } else {
2303 radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE, 0));
2304 radeon_ring_write(rdev, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0));
2305 /* wait for 3D idle clean */
2306 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2307 radeon_ring_write(rdev, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2308 radeon_ring_write(rdev, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit);
2309 /* Emit fence sequence & fire IRQ */
2310 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2311 radeon_ring_write(rdev, ((rdev->fence_drv.scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2312 radeon_ring_write(rdev, fence->seq);
2313 /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */
2314 radeon_ring_write(rdev, PACKET0(CP_INT_STATUS, 0));
2315 radeon_ring_write(rdev, RB_INT_STAT);
2316 }
3ce0a23d
JG		 2317}
2318
3ce0a23d
JG		 2319int r600_copy_blit(struct radeon_device *rdev,
2320 uint64_t src_offset, uint64_t dst_offset,
2321 unsigned num_pages, struct radeon_fence *fence)
2322{
ff82f052
JG		 2323 int r;
2324
2325 mutex_lock(&rdev->r600_blit.mutex);
2326 rdev->r600_blit.vb_ib = NULL;
2327 r = r600_blit_prepare_copy(rdev, num_pages * RADEON_GPU_PAGE_SIZE);
2328 if (r) {
2329 if (rdev->r600_blit.vb_ib)
2330 radeon_ib_free(rdev, &rdev->r600_blit.vb_ib);
2331 mutex_unlock(&rdev->r600_blit.mutex);
2332 return r;
2333 }
a77f1718 2334 r600_kms_blit_copy(rdev, src_offset, dst_offset, num_pages * RADEON_GPU_PAGE_SIZE);
3ce0a23d 2335 r600_blit_done_copy(rdev, fence);
ff82f052 2336 mutex_unlock(&rdev->r600_blit.mutex);
3ce0a23d
JG		 2337 return 0;
2338}
2339
3ce0a23d
JG		 2340int r600_set_surface_reg(struct radeon_device *rdev, int reg,
2341 uint32_t tiling_flags, uint32_t pitch,
2342 uint32_t offset, uint32_t obj_size)
2343{
2344 /* FIXME: implement */
2345 return 0;
2346}
2347
2348void r600_clear_surface_reg(struct radeon_device *rdev, int reg)
2349{
2350 /* FIXME: implement */
2351}
2352
2353
2354bool r600_card_posted(struct radeon_device *rdev)
2355{
2356 uint32_t reg;
2357
2358 /* first check CRTCs */
2359 reg = RREG32(D1CRTC_CONTROL) |
2360 RREG32(D2CRTC_CONTROL);
2361 if (reg & CRTC_EN)
2362 return true;
2363
2364 /* then check MEM_SIZE, in case the crtcs are off */
2365 if (RREG32(CONFIG_MEMSIZE))
2366 return true;
2367
2368 return false;
2369}
2370
fc30b8ef 2371int r600_startup(struct radeon_device *rdev)
3ce0a23d
JG		 2372{
2373 int r;
2374
779720a3
AD		 2375 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
2376 r = r600_init_microcode(rdev);
2377 if (r) {
2378 DRM_ERROR("Failed to load firmware!\n");
2379 return r;
2380 }
2381 }
2382
a3c1945a 2383 r600_mc_program(rdev);
1a029b76
JG		 2384 if (rdev->flags & RADEON_IS_AGP) {
2385 r600_agp_enable(rdev);
2386 } else {
2387 r = r600_pcie_gart_enable(rdev);
2388 if (r)
2389 return r;
2390 }
3ce0a23d 2391 r600_gpu_init(rdev);
c38c7b64
JG		 2392 r = r600_blit_init(rdev);
2393 if (r) {
2394 r600_blit_fini(rdev);
2395 rdev->asic->copy = NULL;
2396 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
2397 }
b70d6bb3 2398
724c80e1
AD		 2399 /* allocate wb buffer */
2400 r = radeon_wb_init(rdev);
2401 if (r)
2402 return r;
2403
d8f60cfc 2404 /* Enable IRQ */
d8f60cfc
AD		 2405 r = r600_irq_init(rdev);
2406 if (r) {
2407 DRM_ERROR("radeon: IH init failed (%d).\n", r);
2408 radeon_irq_kms_fini(rdev);
2409 return r;
2410 }
2411 r600_irq_set(rdev);
2412
3ce0a23d
JG		 2413 r = radeon_ring_init(rdev, rdev->cp.ring_size);
2414 if (r)
2415 return r;
2416 r = r600_cp_load_microcode(rdev);
2417 if (r)
2418 return r;
2419 r = r600_cp_resume(rdev);
2420 if (r)
2421 return r;
724c80e1 2422
3ce0a23d
JG		 2423 return 0;
2424}
2425
28d52043
DA		 2426void r600_vga_set_state(struct radeon_device *rdev, bool state)
2427{
2428 uint32_t temp;
2429
2430 temp = RREG32(CONFIG_CNTL);
2431 if (state == false) {
2432 temp &= ~(1<<0);
2433 temp |= (1<<1);
2434 } else {
2435 temp &= ~(1<<1);
2436 }
2437 WREG32(CONFIG_CNTL, temp);
2438}
2439
fc30b8ef
DA		 2440int r600_resume(struct radeon_device *rdev)
2441{
2442 int r;
2443
1a029b76
JG		 2444 /* Do not reset GPU before posting, on r600 hw unlike on r500 hw,
2445 * posting will perform necessary task to bring back GPU into good
2446 * shape.
2447 */
fc30b8ef 2448 /* post card */
e7d40b9a 2449 atom_asic_init(rdev->mode_info.atom_context);
fc30b8ef
DA		 2450
2451 r = r600_startup(rdev);
2452 if (r) {
2453 DRM_ERROR("r600 startup failed on resume\n");
2454 return r;
2455 }
2456
62a8ea3f 2457 r = r600_ib_test(rdev);
fc30b8ef
DA		 2458 if (r) {
2459 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
2460 return r;
2461 }
38fd2c6f
RM		 2462
2463 r = r600_audio_init(rdev);
2464 if (r) {
2465 DRM_ERROR("radeon: audio resume failed\n");
2466 return r;
2467 }
2468
fc30b8ef
DA		 2469 return r;
2470}
2471
3ce0a23d
JG		 2472int r600_suspend(struct radeon_device *rdev)
2473{
4c788679
JG		 2474 int r;
2475
38fd2c6f 2476 r600_audio_fini(rdev);
3ce0a23d
JG		 2477 /* FIXME: we should wait for ring to be empty */
2478 r600_cp_stop(rdev);
bc1a631e 2479 rdev->cp.ready = false;
0c45249f 2480 r600_irq_suspend(rdev);
724c80e1 2481 radeon_wb_disable(rdev);
4aac0473 2482 r600_pcie_gart_disable(rdev);
bc1a631e 2483 /* unpin shaders bo */
30d2d9a5
JG		 2484 if (rdev->r600_blit.shader_obj) {
2485 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
2486 if (!r) {
2487 radeon_bo_unpin(rdev->r600_blit.shader_obj);
2488 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
2489 }
2490 }
3ce0a23d
JG		 2491 return 0;
2492}
2493
2494/* Plan is to move initialization in that function and use
2495 * helper function so that radeon_device_init pretty much
2496 * do nothing more than calling asic specific function. This
2497 * should also allow to remove a bunch of callback function
2498 * like vram_info.
2499 */
2500int r600_init(struct radeon_device *rdev)
771fe6b9 2501{
3ce0a23d 2502 int r;
771fe6b9 2503
3ce0a23d
JG		 2504 r = radeon_dummy_page_init(rdev);
2505 if (r)
2506 return r;
2507 if (r600_debugfs_mc_info_init(rdev)) {
2508 DRM_ERROR("Failed to register debugfs file for mc !\n");
2509 }
2510 /* This don't do much */
2511 r = radeon_gem_init(rdev);
2512 if (r)
2513 return r;
2514 /* Read BIOS */
2515 if (!radeon_get_bios(rdev)) {
2516 if (ASIC_IS_AVIVO(rdev))
2517 return -EINVAL;
2518 }
2519 /* Must be an ATOMBIOS */
e7d40b9a
JG		 2520 if (!rdev->is_atom_bios) {
2521 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
3ce0a23d 2522 return -EINVAL;
e7d40b9a 2523 }
3ce0a23d
JG		 2524 r = radeon_atombios_init(rdev);
2525 if (r)
2526 return r;
2527 /* Post card if necessary */
72542d77
DA		 2528 if (!r600_card_posted(rdev)) {
2529 if (!rdev->bios) {
2530 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
2531 return -EINVAL;
2532 }
3ce0a23d
JG		 2533 DRM_INFO("GPU not posted. posting now...\n");
2534 atom_asic_init(rdev->mode_info.atom_context);
2535 }
2536 /* Initialize scratch registers */
2537 r600_scratch_init(rdev);
2538 /* Initialize surface registers */
2539 radeon_surface_init(rdev);
7433874e 2540 /* Initialize clocks */
5e6dde7e 2541 radeon_get_clock_info(rdev->ddev);
3ce0a23d
JG		 2542 /* Fence driver */
2543 r = radeon_fence_driver_init(rdev);
2544 if (r)
2545 return r;
700a0cc0
JG		 2546 if (rdev->flags & RADEON_IS_AGP) {
2547 r = radeon_agp_init(rdev);
2548 if (r)
2549 radeon_agp_disable(rdev);
2550 }
3ce0a23d 2551 r = r600_mc_init(rdev);
b574f251 2552 if (r)
3ce0a23d 2553 return r;
3ce0a23d 2554 /* Memory manager */
4c788679 2555 r = radeon_bo_init(rdev);
3ce0a23d
JG		 2556 if (r)
2557 return r;
d8f60cfc
AD		 2558
2559 r = radeon_irq_kms_init(rdev);
2560 if (r)
2561 return r;
2562
3ce0a23d
JG		 2563 rdev->cp.ring_obj = NULL;
2564 r600_ring_init(rdev, 1024 * 1024);
2565
d8f60cfc
AD		 2566 rdev->ih.ring_obj = NULL;
2567 r600_ih_ring_init(rdev, 64 * 1024);
3ce0a23d 2568
4aac0473
JG		 2569 r = r600_pcie_gart_init(rdev);
2570 if (r)
2571 return r;
2572
779720a3 2573 rdev->accel_working = true;
fc30b8ef 2574 r = r600_startup(rdev);
3ce0a23d 2575 if (r) {
655efd3d
JG		 2576 dev_err(rdev->dev, "disabling GPU acceleration\n");
2577 r600_cp_fini(rdev);
655efd3d 2578 r600_irq_fini(rdev);
724c80e1 2579 radeon_wb_fini(rdev);
655efd3d 2580 radeon_irq_kms_fini(rdev);
75c81298 2581 r600_pcie_gart_fini(rdev);
733289c2 2582 rdev->accel_working = false;
3ce0a23d 2583 }
733289c2
JG		 2584 if (rdev->accel_working) {
2585 r = radeon_ib_pool_init(rdev);
2586 if (r) {
db96380e 2587 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
733289c2 2588 rdev->accel_working = false;
db96380e
JG		 2589 } else {
2590 r = r600_ib_test(rdev);
2591 if (r) {
2592 dev_err(rdev->dev, "IB test failed (%d).\n", r);
2593 rdev->accel_working = false;
2594 }
733289c2 2595 }
3ce0a23d 2596 }
dafc3bd5
CK		 2597
2598 r = r600_audio_init(rdev);
2599 if (r)
2600 return r; /* TODO error handling */
3ce0a23d
JG		 2601 return 0;
2602}
2603
2604void r600_fini(struct radeon_device *rdev)
2605{
dafc3bd5 2606 r600_audio_fini(rdev);
3ce0a23d 2607 r600_blit_fini(rdev);
655efd3d 2608 r600_cp_fini(rdev);
d8f60cfc 2609 r600_irq_fini(rdev);
724c80e1 2610 radeon_wb_fini(rdev);
d8f60cfc 2611 radeon_irq_kms_fini(rdev);
4aac0473 2612 r600_pcie_gart_fini(rdev);
655efd3d 2613 radeon_agp_fini(rdev);
3ce0a23d
JG		 2614 radeon_gem_fini(rdev);
2615 radeon_fence_driver_fini(rdev);
4c788679 2616 radeon_bo_fini(rdev);
e7d40b9a 2617 radeon_atombios_fini(rdev);
3ce0a23d
JG		 2618 kfree(rdev->bios);
2619 rdev->bios = NULL;
2620 radeon_dummy_page_fini(rdev);
2621}
2622
2623
2624/*
2625 * CS stuff
2626 */
2627void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
2628{
2629 /* FIXME: implement */
2630 radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
2631 radeon_ring_write(rdev, ib->gpu_addr & 0xFFFFFFFC);
2632 radeon_ring_write(rdev, upper_32_bits(ib->gpu_addr) & 0xFF);
2633 radeon_ring_write(rdev, ib->length_dw);
2634}
2635
2636int r600_ib_test(struct radeon_device *rdev)
2637{
2638 struct radeon_ib *ib;
2639 uint32_t scratch;
2640 uint32_t tmp = 0;
2641 unsigned i;
2642 int r;
2643
2644 r = radeon_scratch_get(rdev, &scratch);
2645 if (r) {
2646 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
2647 return r;
2648 }
2649 WREG32(scratch, 0xCAFEDEAD);
2650 r = radeon_ib_get(rdev, &ib);
2651 if (r) {
2652 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
2653 return r;
2654 }
2655 ib->ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
2656 ib->ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2657 ib->ptr[2] = 0xDEADBEEF;
2658 ib->ptr[3] = PACKET2(0);
2659 ib->ptr[4] = PACKET2(0);
2660 ib->ptr[5] = PACKET2(0);
2661 ib->ptr[6] = PACKET2(0);
2662 ib->ptr[7] = PACKET2(0);
2663 ib->ptr[8] = PACKET2(0);
2664 ib->ptr[9] = PACKET2(0);
2665 ib->ptr[10] = PACKET2(0);
2666 ib->ptr[11] = PACKET2(0);
2667 ib->ptr[12] = PACKET2(0);
2668 ib->ptr[13] = PACKET2(0);
2669 ib->ptr[14] = PACKET2(0);
2670 ib->ptr[15] = PACKET2(0);
2671 ib->length_dw = 16;
2672 r = radeon_ib_schedule(rdev, ib);
2673 if (r) {
2674 radeon_scratch_free(rdev, scratch);
2675 radeon_ib_free(rdev, &ib);
2676 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
2677 return r;
2678 }
2679 r = radeon_fence_wait(ib->fence, false);
2680 if (r) {
2681 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
2682 return r;
2683 }
2684 for (i = 0; i < rdev->usec_timeout; i++) {
2685 tmp = RREG32(scratch);
2686 if (tmp == 0xDEADBEEF)
2687 break;
2688 DRM_UDELAY(1);
2689 }
2690 if (i < rdev->usec_timeout) {
2691 DRM_INFO("ib test succeeded in %u usecs\n", i);
2692 } else {
4417d7f6 2693 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
3ce0a23d
JG		 2694 scratch, tmp);
2695 r = -EINVAL;
2696 }
2697 radeon_scratch_free(rdev, scratch);
2698 radeon_ib_free(rdev, &ib);
771fe6b9
JG		 2699 return r;
2700}
2701
d8f60cfc
AD		 2702/*
2703 * Interrupts
2704 *
2705 * Interrupts use a ring buffer on r6xx/r7xx hardware. It works pretty
2706 * the same as the CP ring buffer, but in reverse. Rather than the CPU
2707 * writing to the ring and the GPU consuming, the GPU writes to the ring
2708 * and host consumes. As the host irq handler processes interrupts, it
2709 * increments the rptr. When the rptr catches up with the wptr, all the
2710 * current interrupts have been processed.
2711 */
2712
2713void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size)
2714{
2715 u32 rb_bufsz;
2716
2717 /* Align ring size */
2718 rb_bufsz = drm_order(ring_size / 4);
2719 ring_size = (1 << rb_bufsz) * 4;
2720 rdev->ih.ring_size = ring_size;
0c45249f
JG		 2721 rdev->ih.ptr_mask = rdev->ih.ring_size - 1;
2722 rdev->ih.rptr = 0;
d8f60cfc
AD		 2723}
2724
0c45249f 2725static int r600_ih_ring_alloc(struct radeon_device *rdev)
d8f60cfc
AD		 2726{
2727 int r;
2728
d8f60cfc
AD		 2729 /* Allocate ring buffer */
2730 if (rdev->ih.ring_obj == NULL) {
4c788679 2731 r = radeon_bo_create(rdev, NULL, rdev->ih.ring_size,
268b2510 2732 PAGE_SIZE, true,
4c788679
JG		 2733 RADEON_GEM_DOMAIN_GTT,
2734 &rdev->ih.ring_obj);
d8f60cfc
AD		 2735 if (r) {
2736 DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r);
2737 return r;
2738 }
4c788679
JG		 2739 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
2740 if (unlikely(r != 0))
2741 return r;
2742 r = radeon_bo_pin(rdev->ih.ring_obj,
2743 RADEON_GEM_DOMAIN_GTT,
2744 &rdev->ih.gpu_addr);
d8f60cfc 2745 if (r) {
4c788679 2746 radeon_bo_unreserve(rdev->ih.ring_obj);
d8f60cfc
AD		 2747 DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r);
2748 return r;
2749 }
4c788679
JG		 2750 r = radeon_bo_kmap(rdev->ih.ring_obj,
2751 (void **)&rdev->ih.ring);
2752 radeon_bo_unreserve(rdev->ih.ring_obj);
d8f60cfc
AD		 2753 if (r) {
2754 DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r);
2755 return r;
2756 }
2757 }
d8f60cfc
AD		 2758 return 0;
2759}
2760
2761static void r600_ih_ring_fini(struct radeon_device *rdev)
2762{
4c788679 2763 int r;
d8f60cfc 2764 if (rdev->ih.ring_obj) {
4c788679
JG		 2765 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
2766 if (likely(r == 0)) {
2767 radeon_bo_kunmap(rdev->ih.ring_obj);
2768 radeon_bo_unpin(rdev->ih.ring_obj);
2769 radeon_bo_unreserve(rdev->ih.ring_obj);
2770 }
2771 radeon_bo_unref(&rdev->ih.ring_obj);
d8f60cfc
AD		 2772 rdev->ih.ring = NULL;
2773 rdev->ih.ring_obj = NULL;
2774 }
2775}
2776
45f9a39b 2777void r600_rlc_stop(struct radeon_device *rdev)
d8f60cfc
AD		 2778{
2779
45f9a39b
AD		 2780 if ((rdev->family >= CHIP_RV770) &&
2781 (rdev->family <= CHIP_RV740)) {
d8f60cfc
AD		 2782 /* r7xx asics need to soft reset RLC before halting */
2783 WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC);
2784 RREG32(SRBM_SOFT_RESET);
2785 udelay(15000);
2786 WREG32(SRBM_SOFT_RESET, 0);
2787 RREG32(SRBM_SOFT_RESET);
2788 }
2789
2790 WREG32(RLC_CNTL, 0);
2791}
2792
2793static void r600_rlc_start(struct radeon_device *rdev)
2794{
2795 WREG32(RLC_CNTL, RLC_ENABLE);
2796}
2797
2798static int r600_rlc_init(struct radeon_device *rdev)
2799{
2800 u32 i;
2801 const __be32 *fw_data;
2802
2803 if (!rdev->rlc_fw)
2804 return -EINVAL;
2805
2806 r600_rlc_stop(rdev);
2807
2808 WREG32(RLC_HB_BASE, 0);
2809 WREG32(RLC_HB_CNTL, 0);
2810 WREG32(RLC_HB_RPTR, 0);
2811 WREG32(RLC_HB_WPTR, 0);
2812 WREG32(RLC_HB_WPTR_LSB_ADDR, 0);
2813 WREG32(RLC_HB_WPTR_MSB_ADDR, 0);
2814 WREG32(RLC_MC_CNTL, 0);
2815 WREG32(RLC_UCODE_CNTL, 0);
2816
2817 fw_data = (const __be32 *)rdev->rlc_fw->data;
45f9a39b
AD		 2818 if (rdev->family >= CHIP_CEDAR) {
2819 for (i = 0; i < EVERGREEN_RLC_UCODE_SIZE; i++) {
2820 WREG32(RLC_UCODE_ADDR, i);
2821 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2822 }
2823 } else if (rdev->family >= CHIP_RV770) {
d8f60cfc
AD		 2824 for (i = 0; i < R700_RLC_UCODE_SIZE; i++) {
2825 WREG32(RLC_UCODE_ADDR, i);
2826 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2827 }
2828 } else {
2829 for (i = 0; i < RLC_UCODE_SIZE; i++) {
2830 WREG32(RLC_UCODE_ADDR, i);
2831 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2832 }
2833 }
2834 WREG32(RLC_UCODE_ADDR, 0);
2835
2836 r600_rlc_start(rdev);
2837
2838 return 0;
2839}
2840
2841static void r600_enable_interrupts(struct radeon_device *rdev)
2842{
2843 u32 ih_cntl = RREG32(IH_CNTL);
2844 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2845
2846 ih_cntl |= ENABLE_INTR;
2847 ih_rb_cntl |= IH_RB_ENABLE;
2848 WREG32(IH_CNTL, ih_cntl);
2849 WREG32(IH_RB_CNTL, ih_rb_cntl);
2850 rdev->ih.enabled = true;
2851}
2852
45f9a39b 2853void r600_disable_interrupts(struct radeon_device *rdev)
d8f60cfc
AD		 2854{
2855 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2856 u32 ih_cntl = RREG32(IH_CNTL);
2857
2858 ih_rb_cntl &= ~IH_RB_ENABLE;
2859 ih_cntl &= ~ENABLE_INTR;
2860 WREG32(IH_RB_CNTL, ih_rb_cntl);
2861 WREG32(IH_CNTL, ih_cntl);
2862 /* set rptr, wptr to 0 */
2863 WREG32(IH_RB_RPTR, 0);
2864 WREG32(IH_RB_WPTR, 0);
2865 rdev->ih.enabled = false;
2866 rdev->ih.wptr = 0;
2867 rdev->ih.rptr = 0;
2868}
2869
e0df1ac5
AD		 2870static void r600_disable_interrupt_state(struct radeon_device *rdev)
2871{
2872 u32 tmp;
2873
3555e53b 2874 WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
e0df1ac5
AD		 2875 WREG32(GRBM_INT_CNTL, 0);
2876 WREG32(DxMODE_INT_MASK, 0);
2877 if (ASIC_IS_DCE3(rdev)) {
2878 WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0);
2879 WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0);
2880 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2881 WREG32(DC_HPD1_INT_CONTROL, tmp);
2882 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2883 WREG32(DC_HPD2_INT_CONTROL, tmp);
2884 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2885 WREG32(DC_HPD3_INT_CONTROL, tmp);
2886 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2887 WREG32(DC_HPD4_INT_CONTROL, tmp);
2888 if (ASIC_IS_DCE32(rdev)) {
2889 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
5898b1f3 2890 WREG32(DC_HPD5_INT_CONTROL, tmp);
e0df1ac5 2891 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
5898b1f3 2892 WREG32(DC_HPD6_INT_CONTROL, tmp);
e0df1ac5
AD		 2893 }
2894 } else {
2895 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
2896 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
2897 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
5898b1f3 2898 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
e0df1ac5 2899 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
5898b1f3 2900 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
e0df1ac5 2901 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
5898b1f3 2902 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
e0df1ac5
AD		 2903 }
2904}
2905
d8f60cfc
AD		 2906int r600_irq_init(struct radeon_device *rdev)
2907{
2908 int ret = 0;
2909 int rb_bufsz;
2910 u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
2911
2912 /* allocate ring */
0c45249f 2913 ret = r600_ih_ring_alloc(rdev);
d8f60cfc
AD		 2914 if (ret)
2915 return ret;
2916
2917 /* disable irqs */
2918 r600_disable_interrupts(rdev);
2919
2920 /* init rlc */
2921 ret = r600_rlc_init(rdev);
2922 if (ret) {
2923 r600_ih_ring_fini(rdev);
2924 return ret;
2925 }
2926
2927 /* setup interrupt control */
2928 /* set dummy read address to ring address */
2929 WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8);
2930 interrupt_cntl = RREG32(INTERRUPT_CNTL);
2931 /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
2932 * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
2933 */
2934 interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
2935 /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
2936 interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
2937 WREG32(INTERRUPT_CNTL, interrupt_cntl);
2938
2939 WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
2940 rb_bufsz = drm_order(rdev->ih.ring_size / 4);
2941
2942 ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
2943 IH_WPTR_OVERFLOW_CLEAR |
2944 (rb_bufsz << 1));
724c80e1
AD		 2945
2946 if (rdev->wb.enabled)
2947 ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;
2948
2949 /* set the writeback address whether it's enabled or not */
2950 WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC);
2951 WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF);
d8f60cfc
AD		 2952
2953 WREG32(IH_RB_CNTL, ih_rb_cntl);
2954
2955 /* set rptr, wptr to 0 */
2956 WREG32(IH_RB_RPTR, 0);
2957 WREG32(IH_RB_WPTR, 0);
2958
2959 /* Default settings for IH_CNTL (disabled at first) */
2960 ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10);
2961 /* RPTR_REARM only works if msi's are enabled */
2962 if (rdev->msi_enabled)
2963 ih_cntl |= RPTR_REARM;
2964
2965#ifdef __BIG_ENDIAN
2966 ih_cntl |= IH_MC_SWAP(IH_MC_SWAP_32BIT);
2967#endif
2968 WREG32(IH_CNTL, ih_cntl);
2969
2970 /* force the active interrupt state to all disabled */
45f9a39b
AD		 2971 if (rdev->family >= CHIP_CEDAR)
2972 evergreen_disable_interrupt_state(rdev);
2973 else
2974 r600_disable_interrupt_state(rdev);
d8f60cfc
AD		 2975
2976 /* enable irqs */
2977 r600_enable_interrupts(rdev);
2978
2979 return ret;
2980}
2981
0c45249f 2982void r600_irq_suspend(struct radeon_device *rdev)
d8f60cfc 2983{
45f9a39b 2984 r600_irq_disable(rdev);
d8f60cfc 2985 r600_rlc_stop(rdev);
0c45249f
JG		 2986}
2987
2988void r600_irq_fini(struct radeon_device *rdev)
2989{
2990 r600_irq_suspend(rdev);
d8f60cfc
AD		 2991 r600_ih_ring_fini(rdev);
2992}
2993
2994int r600_irq_set(struct radeon_device *rdev)
2995{
e0df1ac5
AD		 2996 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
2997 u32 mode_int = 0;
2998 u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0;
2031f77c 2999 u32 grbm_int_cntl = 0;
f2594933 3000 u32 hdmi1, hdmi2;
d8f60cfc 3001
003e69f9 3002 if (!rdev->irq.installed) {
fce7d61b 3003 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
003e69f9
JG		 3004 return -EINVAL;
3005 }
d8f60cfc 3006 /* don't enable anything if the ih is disabled */
79c2bbc5
JG		 3007 if (!rdev->ih.enabled) {
3008 r600_disable_interrupts(rdev);
3009 /* force the active interrupt state to all disabled */
3010 r600_disable_interrupt_state(rdev);
d8f60cfc 3011 return 0;
79c2bbc5 3012 }
d8f60cfc 3013
f2594933 3014 hdmi1 = RREG32(R600_HDMI_BLOCK1 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN;
e0df1ac5 3015 if (ASIC_IS_DCE3(rdev)) {
f2594933 3016 hdmi2 = RREG32(R600_HDMI_BLOCK3 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN;
e0df1ac5
AD		 3017 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3018 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3019 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3020 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
3021 if (ASIC_IS_DCE32(rdev)) {
3022 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
3023 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
3024 }
3025 } else {
f2594933 3026 hdmi2 = RREG32(R600_HDMI_BLOCK2 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN;
e0df1ac5
AD		 3027 hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3028 hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3029 hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3030 }
3031
d8f60cfc
AD		 3032 if (rdev->irq.sw_int) {
3033 DRM_DEBUG("r600_irq_set: sw int\n");
3034 cp_int_cntl |= RB_INT_ENABLE;
d0f8a854 3035 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
d8f60cfc
AD		 3036 }
3037 if (rdev->irq.crtc_vblank_int[0]) {
3038 DRM_DEBUG("r600_irq_set: vblank 0\n");
3039 mode_int |= D1MODE_VBLANK_INT_MASK;
3040 }
3041 if (rdev->irq.crtc_vblank_int[1]) {
3042 DRM_DEBUG("r600_irq_set: vblank 1\n");
3043 mode_int |= D2MODE_VBLANK_INT_MASK;
3044 }
e0df1ac5
AD		 3045 if (rdev->irq.hpd[0]) {
3046 DRM_DEBUG("r600_irq_set: hpd 1\n");
3047 hpd1 |= DC_HPDx_INT_EN;
3048 }
3049 if (rdev->irq.hpd[1]) {
3050 DRM_DEBUG("r600_irq_set: hpd 2\n");
3051 hpd2 |= DC_HPDx_INT_EN;
3052 }
3053 if (rdev->irq.hpd[2]) {
3054 DRM_DEBUG("r600_irq_set: hpd 3\n");
3055 hpd3 |= DC_HPDx_INT_EN;
3056 }
3057 if (rdev->irq.hpd[3]) {
3058 DRM_DEBUG("r600_irq_set: hpd 4\n");
3059 hpd4 |= DC_HPDx_INT_EN;
3060 }
3061 if (rdev->irq.hpd[4]) {
3062 DRM_DEBUG("r600_irq_set: hpd 5\n");
3063 hpd5 |= DC_HPDx_INT_EN;
3064 }
3065 if (rdev->irq.hpd[5]) {
3066 DRM_DEBUG("r600_irq_set: hpd 6\n");
3067 hpd6 |= DC_HPDx_INT_EN;
3068 }
f2594933
CK		 3069 if (rdev->irq.hdmi[0]) {
3070 DRM_DEBUG("r600_irq_set: hdmi 1\n");
3071 hdmi1 |= R600_HDMI_INT_EN;
3072 }
3073 if (rdev->irq.hdmi[1]) {
3074 DRM_DEBUG("r600_irq_set: hdmi 2\n");
3075 hdmi2 |= R600_HDMI_INT_EN;
3076 }
2031f77c
AD		 3077 if (rdev->irq.gui_idle) {
3078 DRM_DEBUG("gui idle\n");
3079 grbm_int_cntl |= GUI_IDLE_INT_ENABLE;
3080 }
d8f60cfc
AD		 3081
3082 WREG32(CP_INT_CNTL, cp_int_cntl);
3083 WREG32(DxMODE_INT_MASK, mode_int);
2031f77c 3084 WREG32(GRBM_INT_CNTL, grbm_int_cntl);
f2594933 3085 WREG32(R600_HDMI_BLOCK1 + R600_HDMI_CNTL, hdmi1);
e0df1ac5 3086 if (ASIC_IS_DCE3(rdev)) {
f2594933 3087 WREG32(R600_HDMI_BLOCK3 + R600_HDMI_CNTL, hdmi2);
e0df1ac5
AD		 3088 WREG32(DC_HPD1_INT_CONTROL, hpd1);
3089 WREG32(DC_HPD2_INT_CONTROL, hpd2);
3090 WREG32(DC_HPD3_INT_CONTROL, hpd3);
3091 WREG32(DC_HPD4_INT_CONTROL, hpd4);
3092 if (ASIC_IS_DCE32(rdev)) {
3093 WREG32(DC_HPD5_INT_CONTROL, hpd5);
3094 WREG32(DC_HPD6_INT_CONTROL, hpd6);
3095 }
3096 } else {
f2594933 3097 WREG32(R600_HDMI_BLOCK2 + R600_HDMI_CNTL, hdmi2);
e0df1ac5
AD		 3098 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
3099 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
3100 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3);
3101 }
d8f60cfc
AD		 3102
3103 return 0;
3104}
3105
e0df1ac5
AD		 3106static inline void r600_irq_ack(struct radeon_device *rdev,
3107 u32 *disp_int,
3108 u32 *disp_int_cont,
3109 u32 *disp_int_cont2)
d8f60cfc 3110{
e0df1ac5
AD		 3111 u32 tmp;
3112
3113 if (ASIC_IS_DCE3(rdev)) {
3114 *disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS);
3115 *disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE);
3116 *disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2);
3117 } else {
3118 *disp_int = RREG32(DISP_INTERRUPT_STATUS);
3119 *disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
3120 *disp_int_cont2 = 0;
3121 }
d8f60cfc 3122
e0df1ac5 3123 if (*disp_int & LB_D1_VBLANK_INTERRUPT)
d8f60cfc 3124 WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
e0df1ac5 3125 if (*disp_int & LB_D1_VLINE_INTERRUPT)
d8f60cfc 3126 WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
e0df1ac5 3127 if (*disp_int & LB_D2_VBLANK_INTERRUPT)
d8f60cfc 3128 WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
e0df1ac5 3129 if (*disp_int & LB_D2_VLINE_INTERRUPT)
d8f60cfc 3130 WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
e0df1ac5
AD		 3131 if (*disp_int & DC_HPD1_INTERRUPT) {
3132 if (ASIC_IS_DCE3(rdev)) {
3133 tmp = RREG32(DC_HPD1_INT_CONTROL);
3134 tmp |= DC_HPDx_INT_ACK;
3135 WREG32(DC_HPD1_INT_CONTROL, tmp);
3136 } else {
3137 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
3138 tmp |= DC_HPDx_INT_ACK;
3139 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
3140 }
3141 }
3142 if (*disp_int & DC_HPD2_INTERRUPT) {
3143 if (ASIC_IS_DCE3(rdev)) {
3144 tmp = RREG32(DC_HPD2_INT_CONTROL);
3145 tmp |= DC_HPDx_INT_ACK;
3146 WREG32(DC_HPD2_INT_CONTROL, tmp);
3147 } else {
3148 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
3149 tmp |= DC_HPDx_INT_ACK;
3150 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
3151 }
3152 }
3153 if (*disp_int_cont & DC_HPD3_INTERRUPT) {
3154 if (ASIC_IS_DCE3(rdev)) {
3155 tmp = RREG32(DC_HPD3_INT_CONTROL);
3156 tmp |= DC_HPDx_INT_ACK;
3157 WREG32(DC_HPD3_INT_CONTROL, tmp);
3158 } else {
3159 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
3160 tmp |= DC_HPDx_INT_ACK;
3161 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
3162 }
3163 }
3164 if (*disp_int_cont & DC_HPD4_INTERRUPT) {
3165 tmp = RREG32(DC_HPD4_INT_CONTROL);
3166 tmp |= DC_HPDx_INT_ACK;
3167 WREG32(DC_HPD4_INT_CONTROL, tmp);
3168 }
3169 if (ASIC_IS_DCE32(rdev)) {
3170 if (*disp_int_cont2 & DC_HPD5_INTERRUPT) {
3171 tmp = RREG32(DC_HPD5_INT_CONTROL);
3172 tmp |= DC_HPDx_INT_ACK;
3173 WREG32(DC_HPD5_INT_CONTROL, tmp);
3174 }
3175 if (*disp_int_cont2 & DC_HPD6_INTERRUPT) {
3176 tmp = RREG32(DC_HPD5_INT_CONTROL);
3177 tmp |= DC_HPDx_INT_ACK;
3178 WREG32(DC_HPD6_INT_CONTROL, tmp);
3179 }
3180 }
f2594933
CK		 3181 if (RREG32(R600_HDMI_BLOCK1 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) {
3182 WREG32_P(R600_HDMI_BLOCK1 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK);
3183 }
3184 if (ASIC_IS_DCE3(rdev)) {
3185 if (RREG32(R600_HDMI_BLOCK3 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) {
3186 WREG32_P(R600_HDMI_BLOCK3 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK);
3187 }
3188 } else {
3189 if (RREG32(R600_HDMI_BLOCK2 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) {
3190 WREG32_P(R600_HDMI_BLOCK2 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK);
3191 }
3192 }
d8f60cfc
AD		 3193}
3194
3195void r600_irq_disable(struct radeon_device *rdev)
3196{
e0df1ac5 3197 u32 disp_int, disp_int_cont, disp_int_cont2;
d8f60cfc
AD		 3198
3199 r600_disable_interrupts(rdev);
3200 /* Wait and acknowledge irq */
3201 mdelay(1);
e0df1ac5
AD		 3202 r600_irq_ack(rdev, &disp_int, &disp_int_cont, &disp_int_cont2);
3203 r600_disable_interrupt_state(rdev);
d8f60cfc
AD		 3204}
3205
3206static inline u32 r600_get_ih_wptr(struct radeon_device *rdev)
3207{
3208 u32 wptr, tmp;
3ce0a23d 3209
724c80e1
AD		 3210 if (rdev->wb.enabled)
3211 wptr = rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4];
3212 else
3213 wptr = RREG32(IH_RB_WPTR);
3ce0a23d 3214
d8f60cfc 3215 if (wptr & RB_OVERFLOW) {
7924e5eb
JG		 3216 /* When a ring buffer overflow happen start parsing interrupt
3217 * from the last not overwritten vector (wptr + 16). Hopefully
3218 * this should allow us to catchup.
3219 */
3220 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
3221 wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
3222 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
d8f60cfc
AD		 3223 tmp = RREG32(IH_RB_CNTL);
3224 tmp |= IH_WPTR_OVERFLOW_CLEAR;
3225 WREG32(IH_RB_CNTL, tmp);
3226 }
0c45249f 3227 return (wptr & rdev->ih.ptr_mask);
d8f60cfc 3228}
3ce0a23d 3229
d8f60cfc
AD		 3230/* r600 IV Ring
3231 * Each IV ring entry is 128 bits:
3232 * [7:0] - interrupt source id
3233 * [31:8] - reserved
3234 * [59:32] - interrupt source data
3235 * [127:60] - reserved
3236 *
3237 * The basic interrupt vector entries
3238 * are decoded as follows:
3239 * src_id src_data description
3240 * 1 0 D1 Vblank
3241 * 1 1 D1 Vline
3242 * 5 0 D2 Vblank
3243 * 5 1 D2 Vline
3244 * 19 0 FP Hot plug detection A
3245 * 19 1 FP Hot plug detection B
3246 * 19 2 DAC A auto-detection
3247 * 19 3 DAC B auto-detection
f2594933
CK		 3248 * 21 4 HDMI block A
3249 * 21 5 HDMI block B
d8f60cfc
AD		 3250 * 176 - CP_INT RB
3251 * 177 - CP_INT IB1
3252 * 178 - CP_INT IB2
3253 * 181 - EOP Interrupt
3254 * 233 - GUI Idle
3255 *
3256 * Note, these are based on r600 and may need to be
3257 * adjusted or added to on newer asics
3258 */
3259
3260int r600_irq_process(struct radeon_device *rdev)
3261{
3262 u32 wptr = r600_get_ih_wptr(rdev);
3263 u32 rptr = rdev->ih.rptr;
3264 u32 src_id, src_data;
e0df1ac5 3265 u32 ring_index, disp_int, disp_int_cont, disp_int_cont2;
d8f60cfc 3266 unsigned long flags;
d4877cf2 3267 bool queue_hotplug = false;
d8f60cfc
AD		 3268
3269 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
79c2bbc5
JG		 3270 if (!rdev->ih.enabled)
3271 return IRQ_NONE;
d8f60cfc
AD		 3272
3273 spin_lock_irqsave(&rdev->ih.lock, flags);
3274
3275 if (rptr == wptr) {
3276 spin_unlock_irqrestore(&rdev->ih.lock, flags);
3277 return IRQ_NONE;
3278 }
3279 if (rdev->shutdown) {
3280 spin_unlock_irqrestore(&rdev->ih.lock, flags);
3281 return IRQ_NONE;
3282 }
3283
3284restart_ih:
3285 /* display interrupts */
e0df1ac5 3286 r600_irq_ack(rdev, &disp_int, &disp_int_cont, &disp_int_cont2);
d8f60cfc
AD		 3287
3288 rdev->ih.wptr = wptr;
3289 while (rptr != wptr) {
3290 /* wptr/rptr are in bytes! */
3291 ring_index = rptr / 4;
3292 src_id = rdev->ih.ring[ring_index] & 0xff;
3293 src_data = rdev->ih.ring[ring_index + 1] & 0xfffffff;
3294
3295 switch (src_id) {
3296 case 1: /* D1 vblank/vline */
3297 switch (src_data) {
3298 case 0: /* D1 vblank */
3299 if (disp_int & LB_D1_VBLANK_INTERRUPT) {
3300 drm_handle_vblank(rdev->ddev, 0);
839461d3 3301 rdev->pm.vblank_sync = true;
73a6d3fc 3302 wake_up(&rdev->irq.vblank_queue);
d8f60cfc
AD		 3303 disp_int &= ~LB_D1_VBLANK_INTERRUPT;
3304 DRM_DEBUG("IH: D1 vblank\n");
3305 }
3306 break;
3307 case 1: /* D1 vline */
3308 if (disp_int & LB_D1_VLINE_INTERRUPT) {
3309 disp_int &= ~LB_D1_VLINE_INTERRUPT;
3310 DRM_DEBUG("IH: D1 vline\n");
3311 }
3312 break;
3313 default:
b042589c 3314 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
d8f60cfc
AD		 3315 break;
3316 }
3317 break;
3318 case 5: /* D2 vblank/vline */
3319 switch (src_data) {
3320 case 0: /* D2 vblank */
3321 if (disp_int & LB_D2_VBLANK_INTERRUPT) {
3322 drm_handle_vblank(rdev->ddev, 1);
839461d3 3323 rdev->pm.vblank_sync = true;
73a6d3fc 3324 wake_up(&rdev->irq.vblank_queue);
d8f60cfc
AD		 3325 disp_int &= ~LB_D2_VBLANK_INTERRUPT;
3326 DRM_DEBUG("IH: D2 vblank\n");
3327 }
3328 break;
3329 case 1: /* D1 vline */
3330 if (disp_int & LB_D2_VLINE_INTERRUPT) {
3331 disp_int &= ~LB_D2_VLINE_INTERRUPT;
3332 DRM_DEBUG("IH: D2 vline\n");
3333 }
3334 break;
3335 default:
b042589c 3336 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
d8f60cfc
AD		 3337 break;
3338 }
3339 break;
e0df1ac5
AD		 3340 case 19: /* HPD/DAC hotplug */
3341 switch (src_data) {
3342 case 0:
3343 if (disp_int & DC_HPD1_INTERRUPT) {
3344 disp_int &= ~DC_HPD1_INTERRUPT;
d4877cf2
AD		 3345 queue_hotplug = true;
3346 DRM_DEBUG("IH: HPD1\n");
e0df1ac5
AD		 3347 }
3348 break;
3349 case 1:
3350 if (disp_int & DC_HPD2_INTERRUPT) {
3351 disp_int &= ~DC_HPD2_INTERRUPT;
d4877cf2
AD		 3352 queue_hotplug = true;
3353 DRM_DEBUG("IH: HPD2\n");
e0df1ac5
AD		 3354 }
3355 break;
3356 case 4:
3357 if (disp_int_cont & DC_HPD3_INTERRUPT) {
3358 disp_int_cont &= ~DC_HPD3_INTERRUPT;
d4877cf2
AD		 3359 queue_hotplug = true;
3360 DRM_DEBUG("IH: HPD3\n");
e0df1ac5
AD		 3361 }
3362 break;
3363 case 5:
3364 if (disp_int_cont & DC_HPD4_INTERRUPT) {
3365 disp_int_cont &= ~DC_HPD4_INTERRUPT;
d4877cf2
AD		 3366 queue_hotplug = true;
3367 DRM_DEBUG("IH: HPD4\n");
e0df1ac5
AD		 3368 }
3369 break;
3370 case 10:
3371 if (disp_int_cont2 & DC_HPD5_INTERRUPT) {
5898b1f3 3372 disp_int_cont2 &= ~DC_HPD5_INTERRUPT;
d4877cf2
AD		 3373 queue_hotplug = true;
3374 DRM_DEBUG("IH: HPD5\n");
e0df1ac5
AD		 3375 }
3376 break;
3377 case 12:
3378 if (disp_int_cont2 & DC_HPD6_INTERRUPT) {
5898b1f3 3379 disp_int_cont2 &= ~DC_HPD6_INTERRUPT;
d4877cf2
AD		 3380 queue_hotplug = true;
3381 DRM_DEBUG("IH: HPD6\n");
e0df1ac5
AD		 3382 }
3383 break;
3384 default:
b042589c 3385 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
e0df1ac5
AD		 3386 break;
3387 }
3388 break;
f2594933
CK		 3389 case 21: /* HDMI */
3390 DRM_DEBUG("IH: HDMI: 0x%x\n", src_data);
3391 r600_audio_schedule_polling(rdev);
3392 break;
d8f60cfc
AD		 3393 case 176: /* CP_INT in ring buffer */
3394 case 177: /* CP_INT in IB1 */
3395 case 178: /* CP_INT in IB2 */
3396 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
3397 radeon_fence_process(rdev);
3398 break;
3399 case 181: /* CP EOP event */
3400 DRM_DEBUG("IH: CP EOP\n");
d0f8a854 3401 radeon_fence_process(rdev);
d8f60cfc 3402 break;
2031f77c
AD		 3403 case 233: /* GUI IDLE */
3404 DRM_DEBUG("IH: CP EOP\n");
3405 rdev->pm.gui_idle = true;
3406 wake_up(&rdev->irq.idle_queue);
3407 break;
d8f60cfc 3408 default:
b042589c 3409 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
d8f60cfc
AD		 3410 break;
3411 }
3412
3413 /* wptr/rptr are in bytes! */
0c45249f
JG		 3414 rptr += 16;
3415 rptr &= rdev->ih.ptr_mask;
d8f60cfc
AD		 3416 }
3417 /* make sure wptr hasn't changed while processing */
3418 wptr = r600_get_ih_wptr(rdev);
3419 if (wptr != rdev->ih.wptr)
3420 goto restart_ih;
d4877cf2
AD		 3421 if (queue_hotplug)
3422 queue_work(rdev->wq, &rdev->hotplug_work);
d8f60cfc
AD		 3423 rdev->ih.rptr = rptr;
3424 WREG32(IH_RB_RPTR, rdev->ih.rptr);
3425 spin_unlock_irqrestore(&rdev->ih.lock, flags);
3426 return IRQ_HANDLED;
3427}
3ce0a23d
JG		 3428
3429/*
3430 * Debugfs info
3431 */
3432#if defined(CONFIG_DEBUG_FS)
3433
3434static int r600_debugfs_cp_ring_info(struct seq_file *m, void *data)
771fe6b9 3435{
3ce0a23d
JG		 3436 struct drm_info_node *node = (struct drm_info_node *) m->private;
3437 struct drm_device *dev = node->minor->dev;
3438 struct radeon_device *rdev = dev->dev_private;
3ce0a23d
JG		 3439 unsigned count, i, j;
3440
3441 radeon_ring_free_size(rdev);
d6840766 3442 count = (rdev->cp.ring_size / 4) - rdev->cp.ring_free_dw;
3ce0a23d 3443 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(CP_STAT));
d6840766
RM		 3444 seq_printf(m, "CP_RB_WPTR 0x%08x\n", RREG32(CP_RB_WPTR));
3445 seq_printf(m, "CP_RB_RPTR 0x%08x\n", RREG32(CP_RB_RPTR));
3446 seq_printf(m, "driver's copy of the CP_RB_WPTR 0x%08x\n", rdev->cp.wptr);
3447 seq_printf(m, "driver's copy of the CP_RB_RPTR 0x%08x\n", rdev->cp.rptr);
3ce0a23d
JG		 3448 seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
3449 seq_printf(m, "%u dwords in ring\n", count);
d6840766 3450 i = rdev->cp.rptr;
3ce0a23d 3451 for (j = 0; j <= count; j++) {
3ce0a23d 3452 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
d6840766 3453 i = (i + 1) & rdev->cp.ptr_mask;
3ce0a23d
JG		 3454 }
3455 return 0;
3456}
3457
3458static int r600_debugfs_mc_info(struct seq_file *m, void *data)
3459{
3460 struct drm_info_node *node = (struct drm_info_node *) m->private;
3461 struct drm_device *dev = node->minor->dev;
3462 struct radeon_device *rdev = dev->dev_private;
3463
3464 DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS);
3465 DREG32_SYS(m, rdev, VM_L2_STATUS);
3466 return 0;
3467}
3468
3469static struct drm_info_list r600_mc_info_list[] = {
3470 {"r600_mc_info", r600_debugfs_mc_info, 0, NULL},
3471 {"r600_ring_info", r600_debugfs_cp_ring_info, 0, NULL},
3472};
3473#endif
3474
3475int r600_debugfs_mc_info_init(struct radeon_device *rdev)
3476{
3477#if defined(CONFIG_DEBUG_FS)
3478 return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list));
3479#else
3480 return 0;
3481#endif
771fe6b9 3482}
062b389c
JG		 3483
3484/**
3485 * r600_ioctl_wait_idle - flush host path cache on wait idle ioctl
3486 * rdev: radeon device structure
3487 * bo: buffer object struct which userspace is waiting for idle
3488 *
3489 * Some R6XX/R7XX doesn't seems to take into account HDP flush performed
3490 * through ring buffer, this leads to corruption in rendering, see
3491 * http://bugzilla.kernel.org/show_bug.cgi?id=15186 to avoid this we
3492 * directly perform HDP flush by writing register through MMIO.
3493 */
3494void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo)
3495{
812d0469 3496 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read
f3886f85
AD		 3497 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL.
3498 * This seems to cause problems on some AGP cards. Just use the old
3499 * method for them.
812d0469 3500 */
e488459a 3501 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
f3886f85 3502 rdev->vram_scratch.ptr && !(rdev->flags & RADEON_IS_AGP)) {
87cbf8f2 3503 void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
812d0469
AD		 3504 u32 tmp;
3505
3506 WREG32(HDP_DEBUG1, 0);
3507 tmp = readl((void __iomem *)ptr);
3508 } else
3509 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
062b389c 3510}
Linux kernel - Deliverables
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