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dafc3bd5 CK |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Christian König. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Christian König | |
25 | */ | |
760285e7 | 26 | #include <drm/drmP.h> |
dafc3bd5 CK |
27 | #include "radeon.h" |
28 | #include "radeon_reg.h" | |
3574dda4 | 29 | #include "radeon_asic.h" |
dafc3bd5 CK |
30 | #include "atom.h" |
31 | ||
cfcbd6d3 RM |
32 | /* |
33 | * check if enc_priv stores radeon_encoder_atom_dig | |
34 | */ | |
35 | static bool radeon_dig_encoder(struct drm_encoder *encoder) | |
36 | { | |
37 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
38 | switch (radeon_encoder->encoder_id) { | |
39 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: | |
40 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: | |
41 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: | |
42 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: | |
43 | case ENCODER_OBJECT_ID_INTERNAL_DVO1: | |
44 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: | |
45 | case ENCODER_OBJECT_ID_INTERNAL_DDI: | |
46 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: | |
47 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: | |
48 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: | |
49 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: | |
50 | return true; | |
51 | } | |
52 | return false; | |
53 | } | |
54 | ||
dafc3bd5 CK |
55 | /* |
56 | * check if the chipset is supported | |
57 | */ | |
58 | static int r600_audio_chipset_supported(struct radeon_device *rdev) | |
59 | { | |
26250e65 | 60 | return ASIC_IS_DCE2(rdev) && !ASIC_IS_DCE6(rdev); |
dafc3bd5 CK |
61 | } |
62 | ||
3299de95 | 63 | struct r600_audio r600_audio_status(struct radeon_device *rdev) |
dafc3bd5 | 64 | { |
3299de95 RM |
65 | struct r600_audio status; |
66 | uint32_t value; | |
dafc3bd5 | 67 | |
3299de95 | 68 | value = RREG32(R600_AUDIO_RATE_BPS_CHANNEL); |
dafc3bd5 | 69 | |
3299de95 RM |
70 | /* number of channels */ |
71 | status.channels = (value & 0x7) + 1; | |
dafc3bd5 | 72 | |
3299de95 RM |
73 | /* bits per sample */ |
74 | switch ((value & 0xF0) >> 4) { | |
75 | case 0x0: | |
76 | status.bits_per_sample = 8; | |
77 | break; | |
78 | case 0x1: | |
79 | status.bits_per_sample = 16; | |
80 | break; | |
81 | case 0x2: | |
82 | status.bits_per_sample = 20; | |
83 | break; | |
84 | case 0x3: | |
85 | status.bits_per_sample = 24; | |
86 | break; | |
87 | case 0x4: | |
88 | status.bits_per_sample = 32; | |
89 | break; | |
90 | default: | |
91 | dev_err(rdev->dev, "Unknown bits per sample 0x%x, using 16\n", | |
92 | (int)value); | |
93 | status.bits_per_sample = 16; | |
94 | } | |
dafc3bd5 | 95 | |
3299de95 | 96 | /* current sampling rate in HZ */ |
dafc3bd5 | 97 | if (value & 0x4000) |
3299de95 | 98 | status.rate = 44100; |
dafc3bd5 | 99 | else |
3299de95 RM |
100 | status.rate = 48000; |
101 | status.rate *= ((value >> 11) & 0x7) + 1; | |
102 | status.rate /= ((value >> 8) & 0x7) + 1; | |
dafc3bd5 | 103 | |
3299de95 | 104 | value = RREG32(R600_AUDIO_STATUS_BITS); |
dafc3bd5 | 105 | |
3299de95 RM |
106 | /* iec 60958 status bits */ |
107 | status.status_bits = value & 0xff; | |
dafc3bd5 | 108 | |
3299de95 RM |
109 | /* iec 60958 category code */ |
110 | status.category_code = (value >> 8) & 0xff; | |
dafc3bd5 | 111 | |
3299de95 | 112 | return status; |
dafc3bd5 CK |
113 | } |
114 | ||
115 | /* | |
116 | * update all hdmi interfaces with current audio parameters | |
117 | */ | |
f122c610 | 118 | void r600_audio_update_hdmi(struct work_struct *work) |
dafc3bd5 | 119 | { |
f122c610 AD |
120 | struct radeon_device *rdev = container_of(work, struct radeon_device, |
121 | audio_work); | |
dafc3bd5 | 122 | struct drm_device *dev = rdev->ddev; |
3299de95 | 123 | struct r600_audio audio_status = r600_audio_status(rdev); |
dafc3bd5 | 124 | struct drm_encoder *encoder; |
3299de95 RM |
125 | bool changed = false; |
126 | ||
127 | if (rdev->audio_status.channels != audio_status.channels || | |
128 | rdev->audio_status.rate != audio_status.rate || | |
129 | rdev->audio_status.bits_per_sample != audio_status.bits_per_sample || | |
130 | rdev->audio_status.status_bits != audio_status.status_bits || | |
131 | rdev->audio_status.category_code != audio_status.category_code) { | |
132 | rdev->audio_status = audio_status; | |
133 | changed = true; | |
dafc3bd5 CK |
134 | } |
135 | ||
136 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
cfcbd6d3 RM |
137 | if (!radeon_dig_encoder(encoder)) |
138 | continue; | |
3299de95 | 139 | if (changed || r600_hdmi_buffer_status_changed(encoder)) |
f2594933 | 140 | r600_hdmi_update_audio_settings(encoder); |
dafc3bd5 | 141 | } |
dafc3bd5 CK |
142 | } |
143 | ||
5230aea6 RM |
144 | /* |
145 | * turn on/off audio engine | |
146 | */ | |
147 | static void r600_audio_engine_enable(struct radeon_device *rdev, bool enable) | |
148 | { | |
69d2ae57 | 149 | u32 value = 0; |
219de62a | 150 | DRM_INFO("%s audio support\n", enable ? "Enabling" : "Disabling"); |
69d2ae57 RM |
151 | if (ASIC_IS_DCE4(rdev)) { |
152 | if (enable) { | |
153 | value |= 0x81000000; /* Required to enable audio */ | |
154 | value |= 0x0e1000f0; /* fglrx sets that too */ | |
155 | } | |
156 | WREG32(EVERGREEN_AUDIO_ENABLE, value); | |
157 | } else { | |
158 | WREG32_P(R600_AUDIO_ENABLE, | |
159 | enable ? 0x81000000 : 0x0, ~0x81000000); | |
160 | } | |
3299de95 | 161 | rdev->audio_enabled = enable; |
5230aea6 RM |
162 | } |
163 | ||
dafc3bd5 | 164 | /* |
f122c610 | 165 | * initialize the audio vars |
dafc3bd5 CK |
166 | */ |
167 | int r600_audio_init(struct radeon_device *rdev) | |
168 | { | |
c8792d5e | 169 | if (!radeon_audio || !r600_audio_chipset_supported(rdev)) |
dafc3bd5 CK |
170 | return 0; |
171 | ||
c8792d5e | 172 | r600_audio_engine_enable(rdev, true); |
dafc3bd5 | 173 | |
3299de95 RM |
174 | rdev->audio_status.channels = -1; |
175 | rdev->audio_status.rate = -1; | |
176 | rdev->audio_status.bits_per_sample = -1; | |
177 | rdev->audio_status.status_bits = 0; | |
178 | rdev->audio_status.category_code = 0; | |
dafc3bd5 | 179 | |
58bd0863 CK |
180 | return 0; |
181 | } | |
182 | ||
dafc3bd5 CK |
183 | /* |
184 | * release the audio timer | |
185 | * TODO: How to do this correctly on SMP systems? | |
186 | */ | |
187 | void r600_audio_fini(struct radeon_device *rdev) | |
188 | { | |
3299de95 | 189 | if (!rdev->audio_enabled) |
dafc3bd5 CK |
190 | return; |
191 | ||
5230aea6 | 192 | r600_audio_engine_enable(rdev, false); |
dafc3bd5 | 193 | } |