projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/radeon/kms: add r600 KMS support
[deliverable/linux.git] / drivers / gpu / drm / radeon / r600_blit_kms.c
CommitLineData
3ce0a23d
JG		 1#include "drmP.h"
2#include "drm.h"
3#include "radeon_drm.h"
4#include "radeon.h"
5
6#include "r600d.h"
7#include "r600_blit_shaders.h"
8
9#define DI_PT_RECTLIST 0x11
10#define DI_INDEX_SIZE_16_BIT 0x0
11#define DI_SRC_SEL_AUTO_INDEX 0x2
12
13#define FMT_8 0x1
14#define FMT_5_6_5 0x8
15#define FMT_8_8_8_8 0x1a
16#define COLOR_8 0x1
17#define COLOR_5_6_5 0x8
18#define COLOR_8_8_8_8 0x1a
19
20/* emits 21 on rv770+, 23 on r600 */
21static void
22set_render_target(struct radeon_device *rdev, int format,
23 int w, int h, u64 gpu_addr)
24{
25 u32 cb_color_info;
26 int pitch, slice;
27
28 h = (h + 7) & ~7;
29 if (h < 8)
30 h = 8;
31
32 cb_color_info = ((format << 2) | (1 << 27));
33 pitch = (w / 8) - 1;
34 slice = ((w * h) / 64) - 1;
35
36 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
37 radeon_ring_write(rdev, (CB_COLOR0_BASE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
38 radeon_ring_write(rdev, gpu_addr >> 8);
39
40 if (rdev->family > CHIP_R600 && rdev->family < CHIP_RV770) {
41 radeon_ring_write(rdev, PACKET3(PACKET3_SURFACE_BASE_UPDATE, 0));
42 radeon_ring_write(rdev, 2 << 0);
43 }
44
45 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
46 radeon_ring_write(rdev, (CB_COLOR0_SIZE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
47 radeon_ring_write(rdev, (pitch << 0) | (slice << 10));
48
49 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
50 radeon_ring_write(rdev, (CB_COLOR0_VIEW - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
51 radeon_ring_write(rdev, 0);
52
53 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
54 radeon_ring_write(rdev, (CB_COLOR0_INFO - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
55 radeon_ring_write(rdev, cb_color_info);
56
57 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
58 radeon_ring_write(rdev, (CB_COLOR0_TILE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
59 radeon_ring_write(rdev, 0);
60
61 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
62 radeon_ring_write(rdev, (CB_COLOR0_FRAG - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
63 radeon_ring_write(rdev, 0);
64
65 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
66 radeon_ring_write(rdev, (CB_COLOR0_MASK - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
67 radeon_ring_write(rdev, 0);
68}
69
70/* emits 5dw */
71static void
72cp_set_surface_sync(struct radeon_device *rdev,
73 u32 sync_type, u32 size,
74 u64 mc_addr)
75{
76 u32 cp_coher_size;
77
78 if (size == 0xffffffff)
79 cp_coher_size = 0xffffffff;
80 else
81 cp_coher_size = ((size + 255) >> 8);
82
83 radeon_ring_write(rdev, PACKET3(PACKET3_SURFACE_SYNC, 3));
84 radeon_ring_write(rdev, sync_type);
85 radeon_ring_write(rdev, cp_coher_size);
86 radeon_ring_write(rdev, mc_addr >> 8);
87 radeon_ring_write(rdev, 10); /* poll interval */
88}
89
90/* emits 21dw + 1 surface sync = 26dw */
91static void
92set_shaders(struct radeon_device *rdev)
93{
94 u64 gpu_addr;
95 u32 sq_pgm_resources;
96
97 /* setup shader regs */
98 sq_pgm_resources = (1 << 0);
99
100 /* VS */
101 gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset;
102 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
103 radeon_ring_write(rdev, (SQ_PGM_START_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
104 radeon_ring_write(rdev, gpu_addr >> 8);
105
106 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
107 radeon_ring_write(rdev, (SQ_PGM_RESOURCES_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
108 radeon_ring_write(rdev, sq_pgm_resources);
109
110 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
111 radeon_ring_write(rdev, (SQ_PGM_CF_OFFSET_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
112 radeon_ring_write(rdev, 0);
113
114 /* PS */
115 gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.ps_offset;
116 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
117 radeon_ring_write(rdev, (SQ_PGM_START_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
118 radeon_ring_write(rdev, gpu_addr >> 8);
119
120 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
121 radeon_ring_write(rdev, (SQ_PGM_RESOURCES_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
122 radeon_ring_write(rdev, sq_pgm_resources | (1 << 28));
123
124 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
125 radeon_ring_write(rdev, (SQ_PGM_EXPORTS_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
126 radeon_ring_write(rdev, 2);
127
128 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
129 radeon_ring_write(rdev, (SQ_PGM_CF_OFFSET_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
130 radeon_ring_write(rdev, 0);
131
132 cp_set_surface_sync(rdev, PACKET3_SH_ACTION_ENA, 512, gpu_addr);
133}
134
135/* emits 9 + 1 sync (5) = 14*/
136static void
137set_vtx_resource(struct radeon_device *rdev, u64 gpu_addr)
138{
139 u32 sq_vtx_constant_word2;
140
141 sq_vtx_constant_word2 = ((upper_32_bits(gpu_addr) & 0xff) | (16 << 8));
142
143 radeon_ring_write(rdev, PACKET3(PACKET3_SET_RESOURCE, 7));
144 radeon_ring_write(rdev, 0x460);
145 radeon_ring_write(rdev, gpu_addr & 0xffffffff);
146 radeon_ring_write(rdev, 48 - 1);
147 radeon_ring_write(rdev, sq_vtx_constant_word2);
148 radeon_ring_write(rdev, 1 << 0);
149 radeon_ring_write(rdev, 0);
150 radeon_ring_write(rdev, 0);
151 radeon_ring_write(rdev, SQ_TEX_VTX_VALID_BUFFER << 30);
152
153 if ((rdev->family == CHIP_RV610) ||
154 (rdev->family == CHIP_RV620) ||
155 (rdev->family == CHIP_RS780) ||
156 (rdev->family == CHIP_RS880) ||
157 (rdev->family == CHIP_RV710))
158 cp_set_surface_sync(rdev,
159 PACKET3_TC_ACTION_ENA, 48, gpu_addr);
160 else
161 cp_set_surface_sync(rdev,
162 PACKET3_VC_ACTION_ENA, 48, gpu_addr);
163}
164
165/* emits 9 */
166static void
167set_tex_resource(struct radeon_device *rdev,
168 int format, int w, int h, int pitch,
169 u64 gpu_addr)
170{
171 uint32_t sq_tex_resource_word0, sq_tex_resource_word1, sq_tex_resource_word4;
172
173 if (h < 1)
174 h = 1;
175
176 sq_tex_resource_word0 = (1 << 0);
177 sq_tex_resource_word0 |= ((((pitch >> 3) - 1) << 8) |
178 ((w - 1) << 19));
179
180 sq_tex_resource_word1 = (format << 26);
181 sq_tex_resource_word1 |= ((h - 1) << 0);
182
183 sq_tex_resource_word4 = ((1 << 14) |
184 (0 << 16) |
185 (1 << 19) |
186 (2 << 22) |
187 (3 << 25));
188
189 radeon_ring_write(rdev, PACKET3(PACKET3_SET_RESOURCE, 7));
190 radeon_ring_write(rdev, 0);
191 radeon_ring_write(rdev, sq_tex_resource_word0);
192 radeon_ring_write(rdev, sq_tex_resource_word1);
193 radeon_ring_write(rdev, gpu_addr >> 8);
194 radeon_ring_write(rdev, gpu_addr >> 8);
195 radeon_ring_write(rdev, sq_tex_resource_word4);
196 radeon_ring_write(rdev, 0);
197 radeon_ring_write(rdev, SQ_TEX_VTX_VALID_TEXTURE << 30);
198}
199
200/* emits 12 */
201static void
202set_scissors(struct radeon_device *rdev, int x1, int y1,
203 int x2, int y2)
204{
205 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
206 radeon_ring_write(rdev, (PA_SC_SCREEN_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
207 radeon_ring_write(rdev, (x1 << 0) | (y1 << 16));
208 radeon_ring_write(rdev, (x2 << 0) | (y2 << 16));
209
210 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
211 radeon_ring_write(rdev, (PA_SC_GENERIC_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
212 radeon_ring_write(rdev, (x1 << 0) | (y1 << 16) | (1 << 31));
213 radeon_ring_write(rdev, (x2 << 0) | (y2 << 16));
214
215 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
216 radeon_ring_write(rdev, (PA_SC_WINDOW_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
217 radeon_ring_write(rdev, (x1 << 0) | (y1 << 16) | (1 << 31));
218 radeon_ring_write(rdev, (x2 << 0) | (y2 << 16));
219}
220
221/* emits 10 */
222static void
223draw_auto(struct radeon_device *rdev)
224{
225 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
226 radeon_ring_write(rdev, (VGT_PRIMITIVE_TYPE - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
227 radeon_ring_write(rdev, DI_PT_RECTLIST);
228
229 radeon_ring_write(rdev, PACKET3(PACKET3_INDEX_TYPE, 0));
230 radeon_ring_write(rdev, DI_INDEX_SIZE_16_BIT);
231
232 radeon_ring_write(rdev, PACKET3(PACKET3_NUM_INSTANCES, 0));
233 radeon_ring_write(rdev, 1);
234
235 radeon_ring_write(rdev, PACKET3(PACKET3_DRAW_INDEX_AUTO, 1));
236 radeon_ring_write(rdev, 3);
237 radeon_ring_write(rdev, DI_SRC_SEL_AUTO_INDEX);
238
239}
240
241/* emits 14 */
242static void
243set_default_state(struct radeon_device *rdev)
244{
245 u32 sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2;
246 u32 sq_thread_resource_mgmt, sq_stack_resource_mgmt_1, sq_stack_resource_mgmt_2;
247 int num_ps_gprs, num_vs_gprs, num_temp_gprs, num_gs_gprs, num_es_gprs;
248 int num_ps_threads, num_vs_threads, num_gs_threads, num_es_threads;
249 int num_ps_stack_entries, num_vs_stack_entries, num_gs_stack_entries, num_es_stack_entries;
250 u64 gpu_addr;
251
252 switch (rdev->family) {
253 case CHIP_R600:
254 num_ps_gprs = 192;
255 num_vs_gprs = 56;
256 num_temp_gprs = 4;
257 num_gs_gprs = 0;
258 num_es_gprs = 0;
259 num_ps_threads = 136;
260 num_vs_threads = 48;
261 num_gs_threads = 4;
262 num_es_threads = 4;
263 num_ps_stack_entries = 128;
264 num_vs_stack_entries = 128;
265 num_gs_stack_entries = 0;
266 num_es_stack_entries = 0;
267 break;
268 case CHIP_RV630:
269 case CHIP_RV635:
270 num_ps_gprs = 84;
271 num_vs_gprs = 36;
272 num_temp_gprs = 4;
273 num_gs_gprs = 0;
274 num_es_gprs = 0;
275 num_ps_threads = 144;
276 num_vs_threads = 40;
277 num_gs_threads = 4;
278 num_es_threads = 4;
279 num_ps_stack_entries = 40;
280 num_vs_stack_entries = 40;
281 num_gs_stack_entries = 32;
282 num_es_stack_entries = 16;
283 break;
284 case CHIP_RV610:
285 case CHIP_RV620:
286 case CHIP_RS780:
287 case CHIP_RS880:
288 default:
289 num_ps_gprs = 84;
290 num_vs_gprs = 36;
291 num_temp_gprs = 4;
292 num_gs_gprs = 0;
293 num_es_gprs = 0;
294 num_ps_threads = 136;
295 num_vs_threads = 48;
296 num_gs_threads = 4;
297 num_es_threads = 4;
298 num_ps_stack_entries = 40;
299 num_vs_stack_entries = 40;
300 num_gs_stack_entries = 32;
301 num_es_stack_entries = 16;
302 break;
303 case CHIP_RV670:
304 num_ps_gprs = 144;
305 num_vs_gprs = 40;
306 num_temp_gprs = 4;
307 num_gs_gprs = 0;
308 num_es_gprs = 0;
309 num_ps_threads = 136;
310 num_vs_threads = 48;
311 num_gs_threads = 4;
312 num_es_threads = 4;
313 num_ps_stack_entries = 40;
314 num_vs_stack_entries = 40;
315 num_gs_stack_entries = 32;
316 num_es_stack_entries = 16;
317 break;
318 case CHIP_RV770:
319 num_ps_gprs = 192;
320 num_vs_gprs = 56;
321 num_temp_gprs = 4;
322 num_gs_gprs = 0;
323 num_es_gprs = 0;
324 num_ps_threads = 188;
325 num_vs_threads = 60;
326 num_gs_threads = 0;
327 num_es_threads = 0;
328 num_ps_stack_entries = 256;
329 num_vs_stack_entries = 256;
330 num_gs_stack_entries = 0;
331 num_es_stack_entries = 0;
332 break;
333 case CHIP_RV730:
334 case CHIP_RV740:
335 num_ps_gprs = 84;
336 num_vs_gprs = 36;
337 num_temp_gprs = 4;
338 num_gs_gprs = 0;
339 num_es_gprs = 0;
340 num_ps_threads = 188;
341 num_vs_threads = 60;
342 num_gs_threads = 0;
343 num_es_threads = 0;
344 num_ps_stack_entries = 128;
345 num_vs_stack_entries = 128;
346 num_gs_stack_entries = 0;
347 num_es_stack_entries = 0;
348 break;
349 case CHIP_RV710:
350 num_ps_gprs = 192;
351 num_vs_gprs = 56;
352 num_temp_gprs = 4;
353 num_gs_gprs = 0;
354 num_es_gprs = 0;
355 num_ps_threads = 144;
356 num_vs_threads = 48;
357 num_gs_threads = 0;
358 num_es_threads = 0;
359 num_ps_stack_entries = 128;
360 num_vs_stack_entries = 128;
361 num_gs_stack_entries = 0;
362 num_es_stack_entries = 0;
363 break;
364 }
365
366 if ((rdev->family == CHIP_RV610) ||
367 (rdev->family == CHIP_RV620) ||
368 (rdev->family == CHIP_RS780) ||
369 (rdev->family == CHIP_RS780) ||
370 (rdev->family == CHIP_RV710))
371 sq_config = 0;
372 else
373 sq_config = VC_ENABLE;
374
375 sq_config |= (DX9_CONSTS |
376 ALU_INST_PREFER_VECTOR |
377 PS_PRIO(0) |
378 VS_PRIO(1) |
379 GS_PRIO(2) |
380 ES_PRIO(3));
381
382 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(num_ps_gprs) |
383 NUM_VS_GPRS(num_vs_gprs) |
384 NUM_CLAUSE_TEMP_GPRS(num_temp_gprs));
385 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(num_gs_gprs) |
386 NUM_ES_GPRS(num_es_gprs));
387 sq_thread_resource_mgmt = (NUM_PS_THREADS(num_ps_threads) |
388 NUM_VS_THREADS(num_vs_threads) |
389 NUM_GS_THREADS(num_gs_threads) |
390 NUM_ES_THREADS(num_es_threads));
391 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(num_ps_stack_entries) |
392 NUM_VS_STACK_ENTRIES(num_vs_stack_entries));
393 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(num_gs_stack_entries) |
394 NUM_ES_STACK_ENTRIES(num_es_stack_entries));
395
396 /* emit an IB pointing at default state */
397 gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.state_offset;
398 radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
399 radeon_ring_write(rdev, gpu_addr & 0xFFFFFFFC);
400 radeon_ring_write(rdev, upper_32_bits(gpu_addr) & 0xFF);
401 radeon_ring_write(rdev, (rdev->r600_blit.state_len / 4));
402
403 radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE, 0));
404 radeon_ring_write(rdev, CACHE_FLUSH_AND_INV_EVENT);
405 /* SQ config */
406 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 6));
407 radeon_ring_write(rdev, (SQ_CONFIG - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
408 radeon_ring_write(rdev, sq_config);
409 radeon_ring_write(rdev, sq_gpr_resource_mgmt_1);
410 radeon_ring_write(rdev, sq_gpr_resource_mgmt_2);
411 radeon_ring_write(rdev, sq_thread_resource_mgmt);
412 radeon_ring_write(rdev, sq_stack_resource_mgmt_1);
413 radeon_ring_write(rdev, sq_stack_resource_mgmt_2);
414}
415
416static inline uint32_t i2f(uint32_t input)
417{
418 u32 result, i, exponent, fraction;
419
420 if ((input & 0x3fff) == 0)
421 result = 0; /* 0 is a special case */
422 else {
423 exponent = 140; /* exponent biased by 127; */
424 fraction = (input & 0x3fff) << 10; /* cheat and only
425 handle numbers below 2^^15 */
426 for (i = 0; i < 14; i++) {
427 if (fraction & 0x800000)
428 break;
429 else {
430 fraction = fraction << 1; /* keep
431 shifting left until top bit = 1 */
432 exponent = exponent - 1;
433 }
434 }
435 result = exponent << 23 | (fraction & 0x7fffff); /* mask
436 off top bit; assumed 1 */
437 }
438 return result;
439}
440
441int r600_blit_init(struct radeon_device *rdev)
442{
443 u32 obj_size;
444 int r;
445 void *ptr;
446
447 rdev->r600_blit.state_offset = 0;
448
449 if (rdev->family >= CHIP_RV770)
450 rdev->r600_blit.state_len = r7xx_default_size * 4;
451 else
452 rdev->r600_blit.state_len = r6xx_default_size * 4;
453
454 obj_size = rdev->r600_blit.state_len;
455 obj_size = ALIGN(obj_size, 256);
456
457 rdev->r600_blit.vs_offset = obj_size;
458 obj_size += r6xx_vs_size * 4;
459 obj_size = ALIGN(obj_size, 256);
460
461 rdev->r600_blit.ps_offset = obj_size;
462 obj_size += r6xx_ps_size * 4;
463 obj_size = ALIGN(obj_size, 256);
464
465 r = radeon_object_create(rdev, NULL, obj_size,
466 true, RADEON_GEM_DOMAIN_VRAM,
467 false, &rdev->r600_blit.shader_obj);
468 if (r) {
469 DRM_ERROR("r600 failed to allocate shader\n");
470 return r;
471 }
472
473 r = radeon_object_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
474 &rdev->r600_blit.shader_gpu_addr);
475 if (r) {
476 DRM_ERROR("failed to pin blit object %d\n", r);
477 return r;
478 }
479
480 DRM_DEBUG("r6xx blit allocated bo @ 0x%16llx %08x vs %08x ps %08x\n",
481 rdev->r600_blit.shader_gpu_addr, obj_size,
482 rdev->r600_blit.vs_offset, rdev->r600_blit.ps_offset);
483
484 r = radeon_object_kmap(rdev->r600_blit.shader_obj, &ptr);
485 if (r) {
486 DRM_ERROR("failed to map blit object %d\n", r);
487 return r;
488 }
489
490 if (rdev->family >= CHIP_RV770)
491 memcpy_toio(ptr + rdev->r600_blit.state_offset, r7xx_default_state, rdev->r600_blit.state_len);
492 else
493 memcpy_toio(ptr + rdev->r600_blit.state_offset, r6xx_default_state, rdev->r600_blit.state_len);
494
495 memcpy(ptr + rdev->r600_blit.vs_offset, r6xx_vs, r6xx_vs_size * 4);
496 memcpy(ptr + rdev->r600_blit.ps_offset, r6xx_ps, r6xx_ps_size * 4);
497
498 radeon_object_kunmap(rdev->r600_blit.shader_obj);
499 return 0;
500}
501
502void r600_blit_fini(struct radeon_device *rdev)
503{
504 radeon_object_unpin(rdev->r600_blit.shader_obj);
505 radeon_object_unref(&rdev->r600_blit.shader_obj);
506}
507
508int r600_vb_ib_get(struct radeon_device *rdev)
509{
510 int r;
511 r = radeon_ib_get(rdev, &rdev->r600_blit.vb_ib);
512 if (r) {
513 DRM_ERROR("failed to get IB for vertex buffer\n");
514 return r;
515 }
516
517 rdev->r600_blit.vb_total = 64*1024;
518 rdev->r600_blit.vb_used = 0;
519 return 0;
520}
521
522void r600_vb_ib_put(struct radeon_device *rdev)
523{
524 mutex_lock(&rdev->ib_pool.mutex);
525 radeon_fence_emit(rdev, rdev->r600_blit.vb_ib->fence);
526 list_add_tail(&rdev->r600_blit.vb_ib->list, &rdev->ib_pool.scheduled_ibs);
527 mutex_unlock(&rdev->ib_pool.mutex);
528 radeon_ib_free(rdev, &rdev->r600_blit.vb_ib);
529}
530
531int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes)
532{
533 int r;
534 int ring_size;
535 const int max_size = 8192*8192;
536
537 r = r600_vb_ib_get(rdev);
538 WARN_ON(r);
539
540 /* loops of emits 64 + fence emit possible */
541 ring_size = ((size_bytes + max_size) / max_size) * 78;
542 /* set default + shaders */
543 ring_size += 40; /* shaders + def state */
544 ring_size += 3; /* fence emit for VB IB */
545 ring_size += 5; /* done copy */
546 ring_size += 3; /* fence emit for done copy */
547 r = radeon_ring_lock(rdev, ring_size);
548 WARN_ON(r);
549
550 set_default_state(rdev); /* 14 */
551 set_shaders(rdev); /* 26 */
552 return 0;
553}
554
555void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence)
556{
557 int r;
558
559 radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE, 0));
560 radeon_ring_write(rdev, CACHE_FLUSH_AND_INV_EVENT);
561 /* wait for 3D idle clean */
562 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
563 radeon_ring_write(rdev, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
564 radeon_ring_write(rdev, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit);
565
566 if (rdev->r600_blit.vb_ib)
567 r600_vb_ib_put(rdev);
568
569 if (fence)
570 r = radeon_fence_emit(rdev, fence);
571
572 radeon_ring_unlock_commit(rdev);
573}
574
575void r600_kms_blit_copy(struct radeon_device *rdev,
576 u64 src_gpu_addr, u64 dst_gpu_addr,
577 int size_bytes)
578{
579 int max_bytes;
580 u64 vb_gpu_addr;
581 u32 *vb;
582
583 DRM_DEBUG("emitting copy %16llx %16llx %d %d\n", src_gpu_addr, dst_gpu_addr,
584 size_bytes, rdev->r600_blit.vb_used);
585 vb = (u32 *)(rdev->r600_blit.vb_ib->ptr + rdev->r600_blit.vb_used);
586 if ((size_bytes & 3) || (src_gpu_addr & 3) || (dst_gpu_addr & 3)) {
587 max_bytes = 8192;
588
589 while (size_bytes) {
590 int cur_size = size_bytes;
591 int src_x = src_gpu_addr & 255;
592 int dst_x = dst_gpu_addr & 255;
593 int h = 1;
594 src_gpu_addr = src_gpu_addr & ~255;
595 dst_gpu_addr = dst_gpu_addr & ~255;
596
597 if (!src_x && !dst_x) {
598 h = (cur_size / max_bytes);
599 if (h > 8192)
600 h = 8192;
601 if (h == 0)
602 h = 1;
603 else
604 cur_size = max_bytes;
605 } else {
606 if (cur_size > max_bytes)
607 cur_size = max_bytes;
608 if (cur_size > (max_bytes - dst_x))
609 cur_size = (max_bytes - dst_x);
610 if (cur_size > (max_bytes - src_x))
611 cur_size = (max_bytes - src_x);
612 }
613
614 if ((rdev->r600_blit.vb_used + 48) > rdev->r600_blit.vb_total) {
615 WARN_ON(1);
616
617#if 0
618 r600_vb_ib_put(rdev);
619
620 r600_nomm_put_vb(dev);
621 r600_nomm_get_vb(dev);
622 if (!dev_priv->blit_vb)
623 return;
624 set_shaders(dev);
625 vb = r600_nomm_get_vb_ptr(dev);
626#endif
627 }
628
629 vb[0] = i2f(dst_x);
630 vb[1] = 0;
631 vb[2] = i2f(src_x);
632 vb[3] = 0;
633
634 vb[4] = i2f(dst_x);
635 vb[5] = i2f(h);
636 vb[6] = i2f(src_x);
637 vb[7] = i2f(h);
638
639 vb[8] = i2f(dst_x + cur_size);
640 vb[9] = i2f(h);
641 vb[10] = i2f(src_x + cur_size);
642 vb[11] = i2f(h);
643
644 /* src 9 */
645 set_tex_resource(rdev, FMT_8,
646 src_x + cur_size, h, src_x + cur_size,
647 src_gpu_addr);
648
649 /* 5 */
650 cp_set_surface_sync(rdev,
651 PACKET3_TC_ACTION_ENA, (src_x + cur_size * h), src_gpu_addr);
652
653 /* dst 23 */
654 set_render_target(rdev, COLOR_8,
655 dst_x + cur_size, h,
656 dst_gpu_addr);
657
658 /* scissors 12 */
659 set_scissors(rdev, dst_x, 0, dst_x + cur_size, h);
660
661 /* 14 */
662 vb_gpu_addr = rdev->r600_blit.vb_ib->gpu_addr + rdev->r600_blit.vb_used;
663 set_vtx_resource(rdev, vb_gpu_addr);
664
665 /* draw 10 */
666 draw_auto(rdev);
667
668 /* 5 */
669 cp_set_surface_sync(rdev,
670 PACKET3_CB_ACTION_ENA | PACKET3_CB0_DEST_BASE_ENA,
671 cur_size * h, dst_gpu_addr);
672
673 vb += 12;
674 rdev->r600_blit.vb_used += 12 * 4;
675
676 src_gpu_addr += cur_size * h;
677 dst_gpu_addr += cur_size * h;
678 size_bytes -= cur_size * h;
679 }
680 } else {
681 max_bytes = 8192 * 4;
682
683 while (size_bytes) {
684 int cur_size = size_bytes;
685 int src_x = (src_gpu_addr & 255);
686 int dst_x = (dst_gpu_addr & 255);
687 int h = 1;
688 src_gpu_addr = src_gpu_addr & ~255;
689 dst_gpu_addr = dst_gpu_addr & ~255;
690
691 if (!src_x && !dst_x) {
692 h = (cur_size / max_bytes);
693 if (h > 8192)
694 h = 8192;
695 if (h == 0)
696 h = 1;
697 else
698 cur_size = max_bytes;
699 } else {
700 if (cur_size > max_bytes)
701 cur_size = max_bytes;
702 if (cur_size > (max_bytes - dst_x))
703 cur_size = (max_bytes - dst_x);
704 if (cur_size > (max_bytes - src_x))
705 cur_size = (max_bytes - src_x);
706 }
707
708 if ((rdev->r600_blit.vb_used + 48) > rdev->r600_blit.vb_total) {
709 WARN_ON(1);
710 }
711#if 0
712 if ((rdev->blit_vb->used + 48) > rdev->blit_vb->total) {
713 r600_nomm_put_vb(dev);
714 r600_nomm_get_vb(dev);
715 if (!rdev->blit_vb)
716 return;
717
718 set_shaders(dev);
719 vb = r600_nomm_get_vb_ptr(dev);
720 }
721#endif
722
723 vb[0] = i2f(dst_x / 4);
724 vb[1] = 0;
725 vb[2] = i2f(src_x / 4);
726 vb[3] = 0;
727
728 vb[4] = i2f(dst_x / 4);
729 vb[5] = i2f(h);
730 vb[6] = i2f(src_x / 4);
731 vb[7] = i2f(h);
732
733 vb[8] = i2f((dst_x + cur_size) / 4);
734 vb[9] = i2f(h);
735 vb[10] = i2f((src_x + cur_size) / 4);
736 vb[11] = i2f(h);
737
738 /* src 9 */
739 set_tex_resource(rdev, FMT_8_8_8_8,
740 (src_x + cur_size) / 4,
741 h, (src_x + cur_size) / 4,
742 src_gpu_addr);
743 /* 5 */
744 cp_set_surface_sync(rdev,
745 PACKET3_TC_ACTION_ENA, (src_x + cur_size * h), src_gpu_addr);
746
747 /* dst 23 */
748 set_render_target(rdev, COLOR_8_8_8_8,
749 dst_x + cur_size, h,
750 dst_gpu_addr);
751
752 /* scissors 12 */
753 set_scissors(rdev, (dst_x / 4), 0, (dst_x + cur_size / 4), h);
754
755 /* Vertex buffer setup 14 */
756 vb_gpu_addr = rdev->r600_blit.vb_ib->gpu_addr + rdev->r600_blit.vb_used;
757 set_vtx_resource(rdev, vb_gpu_addr);
758
759 /* draw 10 */
760 draw_auto(rdev);
761
762 /* 5 */
763 cp_set_surface_sync(rdev,
764 PACKET3_CB_ACTION_ENA | PACKET3_CB0_DEST_BASE_ENA,
765 cur_size * h, dst_gpu_addr);
766
767 /* 78 ring dwords per loop */
768 vb += 12;
769 rdev->r600_blit.vb_used += 12 * 4;
770
771 src_gpu_addr += cur_size * h;
772 dst_gpu_addr += cur_size * h;
773 size_bytes -= cur_size * h;
774 }
775 }
776}
777
Linux kernel - Deliverables
This page took 0.051882 seconds and 5 git commands to generate.