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drm/radeon/kms: demystify evergreen blit code
[deliverable/linux.git] / drivers / gpu / drm / radeon / r600_blit_kms.c
CommitLineData
27849044
AD		 1/*
2 * Copyright 2009 Advanced Micro Devices, Inc.
3 * Copyright 2009 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 */
25
3ce0a23d
JG		 26#include "drmP.h"
27#include "drm.h"
28#include "radeon_drm.h"
29#include "radeon.h"
30
31#include "r600d.h"
32#include "r600_blit_shaders.h"
33
34#define DI_PT_RECTLIST 0x11
35#define DI_INDEX_SIZE_16_BIT 0x0
36#define DI_SRC_SEL_AUTO_INDEX 0x2
37
38#define FMT_8 0x1
39#define FMT_5_6_5 0x8
40#define FMT_8_8_8_8 0x1a
41#define COLOR_8 0x1
42#define COLOR_5_6_5 0x8
43#define COLOR_8_8_8_8 0x1a
44
7dbf41db
AD		 45#define RECT_UNIT_H 32
46#define RECT_UNIT_W (RADEON_GPU_PAGE_SIZE / 4 / RECT_UNIT_H)
47#define MAX_RECT_DIM 8192
48
3ce0a23d
JG		 49/* emits 21 on rv770+, 23 on r600 */
50static void
51set_render_target(struct radeon_device *rdev, int format,
52 int w, int h, u64 gpu_addr)
53{
54 u32 cb_color_info;
55 int pitch, slice;
56
d964fc54 57 h = ALIGN(h, 8);
3ce0a23d
JG		 58 if (h < 8)
59 h = 8;
60
1ea9dbf2 61 cb_color_info = ((format << 2) | (1 << 27) | (1 << 8));
3ce0a23d
JG		 62 pitch = (w / 8) - 1;
63 slice = ((w * h) / 64) - 1;
64
65 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
66 radeon_ring_write(rdev, (CB_COLOR0_BASE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
67 radeon_ring_write(rdev, gpu_addr >> 8);
68
69 if (rdev->family > CHIP_R600 && rdev->family < CHIP_RV770) {
70 radeon_ring_write(rdev, PACKET3(PACKET3_SURFACE_BASE_UPDATE, 0));
71 radeon_ring_write(rdev, 2 << 0);
72 }
73
74 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
75 radeon_ring_write(rdev, (CB_COLOR0_SIZE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
76 radeon_ring_write(rdev, (pitch << 0) | (slice << 10));
77
78 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
79 radeon_ring_write(rdev, (CB_COLOR0_VIEW - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
80 radeon_ring_write(rdev, 0);
81
82 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
83 radeon_ring_write(rdev, (CB_COLOR0_INFO - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
84 radeon_ring_write(rdev, cb_color_info);
85
86 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
87 radeon_ring_write(rdev, (CB_COLOR0_TILE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
88 radeon_ring_write(rdev, 0);
89
90 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
91 radeon_ring_write(rdev, (CB_COLOR0_FRAG - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
92 radeon_ring_write(rdev, 0);
93
94 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
95 radeon_ring_write(rdev, (CB_COLOR0_MASK - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
96 radeon_ring_write(rdev, 0);
97}
98
99/* emits 5dw */
100static void
101cp_set_surface_sync(struct radeon_device *rdev,
102 u32 sync_type, u32 size,
103 u64 mc_addr)
104{
105 u32 cp_coher_size;
106
107 if (size == 0xffffffff)
108 cp_coher_size = 0xffffffff;
109 else
110 cp_coher_size = ((size + 255) >> 8);
111
112 radeon_ring_write(rdev, PACKET3(PACKET3_SURFACE_SYNC, 3));
113 radeon_ring_write(rdev, sync_type);
114 radeon_ring_write(rdev, cp_coher_size);
115 radeon_ring_write(rdev, mc_addr >> 8);
116 radeon_ring_write(rdev, 10); /* poll interval */
117}
118
119/* emits 21dw + 1 surface sync = 26dw */
120static void
121set_shaders(struct radeon_device *rdev)
122{
123 u64 gpu_addr;
124 u32 sq_pgm_resources;
125
126 /* setup shader regs */
127 sq_pgm_resources = (1 << 0);
128
129 /* VS */
130 gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset;
131 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
132 radeon_ring_write(rdev, (SQ_PGM_START_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
133 radeon_ring_write(rdev, gpu_addr >> 8);
134
135 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
136 radeon_ring_write(rdev, (SQ_PGM_RESOURCES_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
137 radeon_ring_write(rdev, sq_pgm_resources);
138
139 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
140 radeon_ring_write(rdev, (SQ_PGM_CF_OFFSET_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
141 radeon_ring_write(rdev, 0);
142
143 /* PS */
144 gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.ps_offset;
145 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
146 radeon_ring_write(rdev, (SQ_PGM_START_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
147 radeon_ring_write(rdev, gpu_addr >> 8);
148
149 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
150 radeon_ring_write(rdev, (SQ_PGM_RESOURCES_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
151 radeon_ring_write(rdev, sq_pgm_resources | (1 << 28));
152
153 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
154 radeon_ring_write(rdev, (SQ_PGM_EXPORTS_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
155 radeon_ring_write(rdev, 2);
156
157 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
158 radeon_ring_write(rdev, (SQ_PGM_CF_OFFSET_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
159 radeon_ring_write(rdev, 0);
160
119e20dc 161 gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset;
3ce0a23d
JG		 162 cp_set_surface_sync(rdev, PACKET3_SH_ACTION_ENA, 512, gpu_addr);
163}
164
165/* emits 9 + 1 sync (5) = 14*/
166static void
167set_vtx_resource(struct radeon_device *rdev, u64 gpu_addr)
168{
169 u32 sq_vtx_constant_word2;
170
171 sq_vtx_constant_word2 = ((upper_32_bits(gpu_addr) & 0xff) | (16 << 8));
4eace7fd
CC		 172#ifdef __BIG_ENDIAN
173 sq_vtx_constant_word2 |= (2 << 30);
174#endif
3ce0a23d
JG		 175
176 radeon_ring_write(rdev, PACKET3(PACKET3_SET_RESOURCE, 7));
177 radeon_ring_write(rdev, 0x460);
178 radeon_ring_write(rdev, gpu_addr & 0xffffffff);
179 radeon_ring_write(rdev, 48 - 1);
180 radeon_ring_write(rdev, sq_vtx_constant_word2);
181 radeon_ring_write(rdev, 1 << 0);
182 radeon_ring_write(rdev, 0);
183 radeon_ring_write(rdev, 0);
184 radeon_ring_write(rdev, SQ_TEX_VTX_VALID_BUFFER << 30);
185
186 if ((rdev->family == CHIP_RV610) ||
187 (rdev->family == CHIP_RV620) ||
188 (rdev->family == CHIP_RS780) ||
189 (rdev->family == CHIP_RS880) ||
190 (rdev->family == CHIP_RV710))
191 cp_set_surface_sync(rdev,
192 PACKET3_TC_ACTION_ENA, 48, gpu_addr);
193 else
194 cp_set_surface_sync(rdev,
195 PACKET3_VC_ACTION_ENA, 48, gpu_addr);
196}
197
198/* emits 9 */
199static void
200set_tex_resource(struct radeon_device *rdev,
201 int format, int w, int h, int pitch,
202 u64 gpu_addr)
203{
204 uint32_t sq_tex_resource_word0, sq_tex_resource_word1, sq_tex_resource_word4;
205
206 if (h < 1)
207 h = 1;
208
1ea9dbf2 209 sq_tex_resource_word0 = (1 << 0) | (1 << 3);
3ce0a23d
JG		 210 sq_tex_resource_word0 |= ((((pitch >> 3) - 1) << 8) |
211 ((w - 1) << 19));
212
213 sq_tex_resource_word1 = (format << 26);
214 sq_tex_resource_word1 |= ((h - 1) << 0);
215
216 sq_tex_resource_word4 = ((1 << 14) |
217 (0 << 16) |
218 (1 << 19) |
219 (2 << 22) |
220 (3 << 25));
221
222 radeon_ring_write(rdev, PACKET3(PACKET3_SET_RESOURCE, 7));
223 radeon_ring_write(rdev, 0);
224 radeon_ring_write(rdev, sq_tex_resource_word0);
225 radeon_ring_write(rdev, sq_tex_resource_word1);
226 radeon_ring_write(rdev, gpu_addr >> 8);
227 radeon_ring_write(rdev, gpu_addr >> 8);
228 radeon_ring_write(rdev, sq_tex_resource_word4);
229 radeon_ring_write(rdev, 0);
230 radeon_ring_write(rdev, SQ_TEX_VTX_VALID_TEXTURE << 30);
231}
232
233/* emits 12 */
234static void
235set_scissors(struct radeon_device *rdev, int x1, int y1,
236 int x2, int y2)
237{
238 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
239 radeon_ring_write(rdev, (PA_SC_SCREEN_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
240 radeon_ring_write(rdev, (x1 << 0) | (y1 << 16));
241 radeon_ring_write(rdev, (x2 << 0) | (y2 << 16));
242
243 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
244 radeon_ring_write(rdev, (PA_SC_GENERIC_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
245 radeon_ring_write(rdev, (x1 << 0) | (y1 << 16) | (1 << 31));
246 radeon_ring_write(rdev, (x2 << 0) | (y2 << 16));
247
248 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
249 radeon_ring_write(rdev, (PA_SC_WINDOW_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
250 radeon_ring_write(rdev, (x1 << 0) | (y1 << 16) | (1 << 31));
251 radeon_ring_write(rdev, (x2 << 0) | (y2 << 16));
252}
253
254/* emits 10 */
255static void
256draw_auto(struct radeon_device *rdev)
257{
258 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
259 radeon_ring_write(rdev, (VGT_PRIMITIVE_TYPE - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
260 radeon_ring_write(rdev, DI_PT_RECTLIST);
261
262 radeon_ring_write(rdev, PACKET3(PACKET3_INDEX_TYPE, 0));
4eace7fd
CC		 263 radeon_ring_write(rdev,
264#ifdef __BIG_ENDIAN
265 (2 << 2) |
266#endif
267 DI_INDEX_SIZE_16_BIT);
3ce0a23d
JG		 268
269 radeon_ring_write(rdev, PACKET3(PACKET3_NUM_INSTANCES, 0));
270 radeon_ring_write(rdev, 1);
271
272 radeon_ring_write(rdev, PACKET3(PACKET3_DRAW_INDEX_AUTO, 1));
273 radeon_ring_write(rdev, 3);
274 radeon_ring_write(rdev, DI_SRC_SEL_AUTO_INDEX);
275
276}
277
278/* emits 14 */
279static void
280set_default_state(struct radeon_device *rdev)
281{
282 u32 sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2;
283 u32 sq_thread_resource_mgmt, sq_stack_resource_mgmt_1, sq_stack_resource_mgmt_2;
284 int num_ps_gprs, num_vs_gprs, num_temp_gprs, num_gs_gprs, num_es_gprs;
285 int num_ps_threads, num_vs_threads, num_gs_threads, num_es_threads;
286 int num_ps_stack_entries, num_vs_stack_entries, num_gs_stack_entries, num_es_stack_entries;
287 u64 gpu_addr;
119e20dc 288 int dwords;
3ce0a23d
JG		 289
290 switch (rdev->family) {
291 case CHIP_R600:
292 num_ps_gprs = 192;
293 num_vs_gprs = 56;
294 num_temp_gprs = 4;
295 num_gs_gprs = 0;
296 num_es_gprs = 0;
297 num_ps_threads = 136;
298 num_vs_threads = 48;
299 num_gs_threads = 4;
300 num_es_threads = 4;
301 num_ps_stack_entries = 128;
302 num_vs_stack_entries = 128;
303 num_gs_stack_entries = 0;
304 num_es_stack_entries = 0;
305 break;
306 case CHIP_RV630:
307 case CHIP_RV635:
308 num_ps_gprs = 84;
309 num_vs_gprs = 36;
310 num_temp_gprs = 4;
311 num_gs_gprs = 0;
312 num_es_gprs = 0;
313 num_ps_threads = 144;
314 num_vs_threads = 40;
315 num_gs_threads = 4;
316 num_es_threads = 4;
317 num_ps_stack_entries = 40;
318 num_vs_stack_entries = 40;
319 num_gs_stack_entries = 32;
320 num_es_stack_entries = 16;
321 break;
322 case CHIP_RV610:
323 case CHIP_RV620:
324 case CHIP_RS780:
325 case CHIP_RS880:
326 default:
327 num_ps_gprs = 84;
328 num_vs_gprs = 36;
329 num_temp_gprs = 4;
330 num_gs_gprs = 0;
331 num_es_gprs = 0;
332 num_ps_threads = 136;
333 num_vs_threads = 48;
334 num_gs_threads = 4;
335 num_es_threads = 4;
336 num_ps_stack_entries = 40;
337 num_vs_stack_entries = 40;
338 num_gs_stack_entries = 32;
339 num_es_stack_entries = 16;
340 break;
341 case CHIP_RV670:
342 num_ps_gprs = 144;
343 num_vs_gprs = 40;
344 num_temp_gprs = 4;
345 num_gs_gprs = 0;
346 num_es_gprs = 0;
347 num_ps_threads = 136;
348 num_vs_threads = 48;
349 num_gs_threads = 4;
350 num_es_threads = 4;
351 num_ps_stack_entries = 40;
352 num_vs_stack_entries = 40;
353 num_gs_stack_entries = 32;
354 num_es_stack_entries = 16;
355 break;
356 case CHIP_RV770:
357 num_ps_gprs = 192;
358 num_vs_gprs = 56;
359 num_temp_gprs = 4;
360 num_gs_gprs = 0;
361 num_es_gprs = 0;
362 num_ps_threads = 188;
363 num_vs_threads = 60;
364 num_gs_threads = 0;
365 num_es_threads = 0;
366 num_ps_stack_entries = 256;
367 num_vs_stack_entries = 256;
368 num_gs_stack_entries = 0;
369 num_es_stack_entries = 0;
370 break;
371 case CHIP_RV730:
372 case CHIP_RV740:
373 num_ps_gprs = 84;
374 num_vs_gprs = 36;
375 num_temp_gprs = 4;
376 num_gs_gprs = 0;
377 num_es_gprs = 0;
378 num_ps_threads = 188;
379 num_vs_threads = 60;
380 num_gs_threads = 0;
381 num_es_threads = 0;
382 num_ps_stack_entries = 128;
383 num_vs_stack_entries = 128;
384 num_gs_stack_entries = 0;
385 num_es_stack_entries = 0;
386 break;
387 case CHIP_RV710:
388 num_ps_gprs = 192;
389 num_vs_gprs = 56;
390 num_temp_gprs = 4;
391 num_gs_gprs = 0;
392 num_es_gprs = 0;
393 num_ps_threads = 144;
394 num_vs_threads = 48;
395 num_gs_threads = 0;
396 num_es_threads = 0;
397 num_ps_stack_entries = 128;
398 num_vs_stack_entries = 128;
399 num_gs_stack_entries = 0;
400 num_es_stack_entries = 0;
401 break;
402 }
403
404 if ((rdev->family == CHIP_RV610) ||
405 (rdev->family == CHIP_RV620) ||
406 (rdev->family == CHIP_RS780) ||
ee59f2b4 407 (rdev->family == CHIP_RS880) ||
3ce0a23d
JG		 408 (rdev->family == CHIP_RV710))
409 sq_config = 0;
410 else
411 sq_config = VC_ENABLE;
412
413 sq_config |= (DX9_CONSTS |
414 ALU_INST_PREFER_VECTOR |
415 PS_PRIO(0) |
416 VS_PRIO(1) |
417 GS_PRIO(2) |
418 ES_PRIO(3));
419
420 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(num_ps_gprs) |
421 NUM_VS_GPRS(num_vs_gprs) |
422 NUM_CLAUSE_TEMP_GPRS(num_temp_gprs));
423 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(num_gs_gprs) |
424 NUM_ES_GPRS(num_es_gprs));
425 sq_thread_resource_mgmt = (NUM_PS_THREADS(num_ps_threads) |
426 NUM_VS_THREADS(num_vs_threads) |
427 NUM_GS_THREADS(num_gs_threads) |
428 NUM_ES_THREADS(num_es_threads));
429 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(num_ps_stack_entries) |
430 NUM_VS_STACK_ENTRIES(num_vs_stack_entries));
431 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(num_gs_stack_entries) |
432 NUM_ES_STACK_ENTRIES(num_es_stack_entries));
433
434 /* emit an IB pointing at default state */
d964fc54 435 dwords = ALIGN(rdev->r600_blit.state_len, 0x10);
3ce0a23d
JG		 436 gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.state_offset;
437 radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
4eace7fd
CC		 438 radeon_ring_write(rdev,
439#ifdef __BIG_ENDIAN
440 (2 << 0) |
441#endif
442 (gpu_addr & 0xFFFFFFFC));
3ce0a23d 443 radeon_ring_write(rdev, upper_32_bits(gpu_addr) & 0xFF);
119e20dc 444 radeon_ring_write(rdev, dwords);
3ce0a23d 445
3ce0a23d
JG		 446 /* SQ config */
447 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 6));
448 radeon_ring_write(rdev, (SQ_CONFIG - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
449 radeon_ring_write(rdev, sq_config);
450 radeon_ring_write(rdev, sq_gpr_resource_mgmt_1);
451 radeon_ring_write(rdev, sq_gpr_resource_mgmt_2);
452 radeon_ring_write(rdev, sq_thread_resource_mgmt);
453 radeon_ring_write(rdev, sq_stack_resource_mgmt_1);
454 radeon_ring_write(rdev, sq_stack_resource_mgmt_2);
455}
456
ce580fab 457static uint32_t i2f(uint32_t input)
3ce0a23d
JG		 458{
459 u32 result, i, exponent, fraction;
460
461 if ((input & 0x3fff) == 0)
462 result = 0; /* 0 is a special case */
463 else {
464 exponent = 140; /* exponent biased by 127; */
465 fraction = (input & 0x3fff) << 10; /* cheat and only
466 handle numbers below 2^^15 */
467 for (i = 0; i < 14; i++) {
468 if (fraction & 0x800000)
469 break;
470 else {
471 fraction = fraction << 1; /* keep
472 shifting left until top bit = 1 */
473 exponent = exponent - 1;
474 }
475 }
476 result = exponent << 23 | (fraction & 0x7fffff); /* mask
477 off top bit; assumed 1 */
478 }
479 return result;
480}
481
482int r600_blit_init(struct radeon_device *rdev)
483{
484 u32 obj_size;
4eace7fd 485 int i, r, dwords;
3ce0a23d 486 void *ptr;
119e20dc
AD		 487 u32 packet2s[16];
488 int num_packet2s = 0;
3ce0a23d 489
b70d6bb3 490 /* pin copy shader into vram if already initialized */
90aca4d2 491 if (rdev->r600_blit.shader_obj)
b70d6bb3
AD		 492 goto done;
493
ff82f052 494 mutex_init(&rdev->r600_blit.mutex);
3ce0a23d
JG		 495 rdev->r600_blit.state_offset = 0;
496
497 if (rdev->family >= CHIP_RV770)
119e20dc 498 rdev->r600_blit.state_len = r7xx_default_size;
3ce0a23d 499 else
119e20dc
AD		 500 rdev->r600_blit.state_len = r6xx_default_size;
501
502 dwords = rdev->r600_blit.state_len;
503 while (dwords & 0xf) {
4eace7fd 504 packet2s[num_packet2s++] = cpu_to_le32(PACKET2(0));
119e20dc
AD		 505 dwords++;
506 }
3ce0a23d 507
119e20dc 508 obj_size = dwords * 4;
3ce0a23d
JG		 509 obj_size = ALIGN(obj_size, 256);
510
511 rdev->r600_blit.vs_offset = obj_size;
512 obj_size += r6xx_vs_size * 4;
513 obj_size = ALIGN(obj_size, 256);
514
515 rdev->r600_blit.ps_offset = obj_size;
516 obj_size += r6xx_ps_size * 4;
517 obj_size = ALIGN(obj_size, 256);
518
441921d5 519 r = radeon_bo_create(rdev, obj_size, PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
4c788679 520 &rdev->r600_blit.shader_obj);
3ce0a23d
JG		 521 if (r) {
522 DRM_ERROR("r600 failed to allocate shader\n");
523 return r;
524 }
525
bc1a631e
DA		 526 DRM_DEBUG("r6xx blit allocated bo %08x vs %08x ps %08x\n",
527 obj_size,
3ce0a23d
JG		 528 rdev->r600_blit.vs_offset, rdev->r600_blit.ps_offset);
529
4c788679
JG		 530 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
531 if (unlikely(r != 0))
532 return r;
533 r = radeon_bo_kmap(rdev->r600_blit.shader_obj, &ptr);
3ce0a23d
JG		 534 if (r) {
535 DRM_ERROR("failed to map blit object %d\n", r);
536 return r;
537 }
3ce0a23d 538 if (rdev->family >= CHIP_RV770)
119e20dc
AD		 539 memcpy_toio(ptr + rdev->r600_blit.state_offset,
540 r7xx_default_state, rdev->r600_blit.state_len * 4);
3ce0a23d 541 else
119e20dc
AD		 542 memcpy_toio(ptr + rdev->r600_blit.state_offset,
543 r6xx_default_state, rdev->r600_blit.state_len * 4);
544 if (num_packet2s)
545 memcpy_toio(ptr + rdev->r600_blit.state_offset + (rdev->r600_blit.state_len * 4),
546 packet2s, num_packet2s * 4);
4eace7fd
CC		 547 for (i = 0; i < r6xx_vs_size; i++)
548 *(u32 *)((unsigned long)ptr + rdev->r600_blit.vs_offset + i * 4) = cpu_to_le32(r6xx_vs[i]);
549 for (i = 0; i < r6xx_ps_size; i++)
550 *(u32 *)((unsigned long)ptr + rdev->r600_blit.ps_offset + i * 4) = cpu_to_le32(r6xx_ps[i]);
4c788679
JG		 551 radeon_bo_kunmap(rdev->r600_blit.shader_obj);
552 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
b70d6bb3
AD		 553
554done:
555 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
556 if (unlikely(r != 0))
557 return r;
558 r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
559 &rdev->r600_blit.shader_gpu_addr);
560 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
561 if (r) {
562 dev_err(rdev->dev, "(%d) pin blit object failed\n", r);
563 return r;
564 }
53595338 565 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
3ce0a23d
JG		 566 return 0;
567}
568
569void r600_blit_fini(struct radeon_device *rdev)
570{
4c788679
JG		 571 int r;
572
53595338 573 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
30d2d9a5
JG		 574 if (rdev->r600_blit.shader_obj == NULL)
575 return;
576 /* If we can't reserve the bo, unref should be enough to destroy
577 * it when it becomes idle.
578 */
4c788679 579 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
30d2d9a5
JG		 580 if (!r) {
581 radeon_bo_unpin(rdev->r600_blit.shader_obj);
582 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
4c788679 583 }
4c788679 584 radeon_bo_unref(&rdev->r600_blit.shader_obj);
3ce0a23d
JG		 585}
586
d7ccd8fc 587static int r600_vb_ib_get(struct radeon_device *rdev)
3ce0a23d
JG		 588{
589 int r;
590 r = radeon_ib_get(rdev, &rdev->r600_blit.vb_ib);
591 if (r) {
592 DRM_ERROR("failed to get IB for vertex buffer\n");
593 return r;
594 }
595
596 rdev->r600_blit.vb_total = 64*1024;
597 rdev->r600_blit.vb_used = 0;
598 return 0;
599}
600
d7ccd8fc 601static void r600_vb_ib_put(struct radeon_device *rdev)
3ce0a23d 602{
3ce0a23d 603 radeon_fence_emit(rdev, rdev->r600_blit.vb_ib->fence);
3ce0a23d
JG		 604 radeon_ib_free(rdev, &rdev->r600_blit.vb_ib);
605}
606
7dbf41db
AD		 607/* FIXME: the function is very similar to evergreen_blit_create_rect, except
608 that it different predefined constants; consider commonizing */
609static unsigned r600_blit_create_rect(unsigned num_pages, int *width, int *height)
610{
611 unsigned max_pages;
612 unsigned pages = num_pages;
613 int w, h;
614
615 if (num_pages == 0) {
616 /* not supposed to be called with no pages, but just in case */
617 h = 0;
618 w = 0;
619 pages = 0;
620 WARN_ON(1);
621 } else {
622 int rect_order = 2;
623 h = RECT_UNIT_H;
624 while (num_pages / rect_order) {
625 h *= 2;
626 rect_order *= 4;
627 if (h >= MAX_RECT_DIM) {
628 h = MAX_RECT_DIM;
629 break;
630 }
631 }
632 max_pages = (MAX_RECT_DIM * h) / (RECT_UNIT_W * RECT_UNIT_H);
633 if (pages > max_pages)
634 pages = max_pages;
635 w = (pages * RECT_UNIT_W * RECT_UNIT_H) / h;
636 w = (w / RECT_UNIT_W) * RECT_UNIT_W;
637 pages = (w * h) / (RECT_UNIT_W * RECT_UNIT_H);
638 BUG_ON(pages == 0);
639 }
640
641
642 DRM_DEBUG("blit_rectangle: h=%d, w=%d, pages=%d\n", h, w, pages);
643
644 /* return width and height only of the caller wants it */
645 if (height)
646 *height = h;
647 if (width)
648 *width = w;
649
650 return pages;
651}
652
653
654int r600_blit_prepare_copy(struct radeon_device *rdev, unsigned num_pages)
3ce0a23d
JG		 655{
656 int r;
7dbf41db 657 int ring_size;
1be34056 658 /* loops of emits 64 + fence emit possible */
7dbf41db 659 int dwords_per_loop = 76, num_loops = 0;
7cbb355e
DA		 660
661 r = r600_vb_ib_get(rdev);
ff82f052
JG		 662 if (r)
663 return r;
1be34056
AD		 664
665 /* set_render_target emits 2 extra dwords on rv6xx */
666 if (rdev->family > CHIP_R600 && rdev->family < CHIP_RV770)
667 dwords_per_loop += 2;
119e20dc 668
7dbf41db
AD		 669 /* num loops */
670 while (num_pages) {
671 num_pages -= r600_blit_create_rect(num_pages, NULL, NULL);
672 num_loops++;
673 }
3ce0a23d 674
7cbb355e
DA		 675 /* calculate number of loops correctly */
676 ring_size = num_loops * dwords_per_loop;
3ce0a23d
JG		 677 /* set default + shaders */
678 ring_size += 40; /* shaders + def state */
6ad86c31 679 ring_size += 10; /* fence emit for VB IB */
3ce0a23d 680 ring_size += 5; /* done copy */
6ad86c31 681 ring_size += 10; /* fence emit for done copy */
3ce0a23d 682 r = radeon_ring_lock(rdev, ring_size);
ff82f052
JG		 683 if (r)
684 return r;
3ce0a23d
JG		 685
686 set_default_state(rdev); /* 14 */
687 set_shaders(rdev); /* 26 */
688 return 0;
689}
690
691void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence)
692{
693 int r;
694
3ce0a23d
JG		 695 if (rdev->r600_blit.vb_ib)
696 r600_vb_ib_put(rdev);
697
698 if (fence)
699 r = radeon_fence_emit(rdev, fence);
700
701 radeon_ring_unlock_commit(rdev);
702}
703
704void r600_kms_blit_copy(struct radeon_device *rdev,
705 u64 src_gpu_addr, u64 dst_gpu_addr,
7dbf41db 706 unsigned num_pages)
3ce0a23d 707{
3ce0a23d
JG		 708 u64 vb_gpu_addr;
709 u32 *vb;
710
711 DRM_DEBUG("emitting copy %16llx %16llx %d %d\n", src_gpu_addr, dst_gpu_addr,
7dbf41db 712 num_pages, rdev->r600_blit.vb_used);
ceeb5027 713 vb = (u32 *)(rdev->r600_blit.vb_ib->ptr + rdev->r600_blit.vb_used);
3ce0a23d 714
7dbf41db
AD		 715 while (num_pages) {
716 int w, h;
717 unsigned size_in_bytes;
718 unsigned pages_per_loop = r600_blit_create_rect(num_pages, &w, &h);
3ce0a23d 719
7dbf41db
AD		 720 size_in_bytes = pages_per_loop * RADEON_GPU_PAGE_SIZE;
721 DRM_DEBUG("rectangle w=%d h=%d\n", w, h);
3ce0a23d 722
7dbf41db
AD		 723 if ((rdev->r600_blit.vb_used + 48) > rdev->r600_blit.vb_total) {
724 WARN_ON(1);
725 }
3ce0a23d 726
7dbf41db
AD		 727 vb[0] = 0;
728 vb[1] = 0;
729 vb[2] = 0;
730 vb[3] = 0;
3ce0a23d 731
7dbf41db
AD		 732 vb[4] = 0;
733 vb[5] = i2f(h);
734 vb[6] = 0;
735 vb[7] = i2f(h);
3ce0a23d 736
7dbf41db
AD		 737 vb[8] = i2f(w);
738 vb[9] = i2f(h);
739 vb[10] = i2f(w);
740 vb[11] = i2f(h);
3ce0a23d 741
7dbf41db
AD		 742 /* src 9 */
743 set_tex_resource(rdev, FMT_8_8_8_8, w, h, w, src_gpu_addr);
3ce0a23d 744
7dbf41db
AD		 745 /* 5 */
746 cp_set_surface_sync(rdev,
747 PACKET3_TC_ACTION_ENA, size_in_bytes, src_gpu_addr);
3ce0a23d 748
7dbf41db
AD		 749 /* dst 23 */
750 set_render_target(rdev, COLOR_8_8_8_8, w, h, dst_gpu_addr);
3ce0a23d 751
7dbf41db
AD		 752 /* scissors 12 */
753 set_scissors(rdev, 0, 0, w, h);
3ce0a23d 754
7dbf41db
AD		 755 /* Vertex buffer setup 14 */
756 vb_gpu_addr = rdev->r600_blit.vb_ib->gpu_addr + rdev->r600_blit.vb_used;
757 set_vtx_resource(rdev, vb_gpu_addr);
3ce0a23d 758
7dbf41db
AD		 759 /* draw 10 */
760 draw_auto(rdev);
3ce0a23d 761
7dbf41db
AD		 762 /* 5 */
763 cp_set_surface_sync(rdev,
764 PACKET3_CB_ACTION_ENA | PACKET3_CB0_DEST_BASE_ENA,
765 size_in_bytes, dst_gpu_addr);
766
767 /* 78 ring dwords per loop */
768 vb += 12;
769 rdev->r600_blit.vb_used += 4*12;
770 src_gpu_addr += size_in_bytes;
771 dst_gpu_addr += size_in_bytes;
772 num_pages -= pages_per_loop;
3ce0a23d
JG		 773 }
774}
Linux kernel - Deliverables
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